FEATURES

CCD30–11 Front Illuminated Open Electrode
High Performance CCD Sensor
FEATURES









1024 by 256 Pixel Format
26 µm Square Pixels
Image Area 26.6 x 6.7 mm
Wide Dynamic Range
Symmetrical Anti-static Gate Protection
Open Electrode Structure for Enhanced Quantum
Efficiency
Advanced Inverted Mode Operation
Anti-blooming Readout Register
Zero Light Emitting Output Amplifier.
APPLICATIONS



Spectroscopy
Scientific Imaging
TDI Operation.
INTRODUCTION
The open electrode CCD30-11 is a high performance CCD
sensor designed as an upgrade for the standard CCD30-11,
for use in the scientific spectroscopy instrument market,
where enhanced quantum efficiency is required at nearultraviolet wavelengths. With an array of 1024 x 256 26 µm
square pixels it has an imaging area to suit most
spectrometer outputs of 26.6 x 6.7 mm (1.05 x 0.26 inch).
The readout register is organised along the long (1024 pixel)
edge of the sensor and contains an anti-blooming drain to
allow high speed binning operations of low level signals
which may be adjacent to much stronger signals. The novel
output amplifier design has no light emission.
Standard three phase clocking and buried channel charge
transfer are employed and Advanced Inverted Mode
Operation (AIMO) is included as standard.
The open electrode CCD30-11 is packaged in a 20-pin DIL
ceramic package and is pin compatible (but not completely
clock compatible) with the standard CCD30-11.
Designers are advised to consult e2v technologies should
they be considering using CCD sensors in abnormal
environments or if they require customised packaging.
TYPICAL PERFORMANCE
Pixel readout frequency
Output amplifier sensitivity
Peak signal
Dynamic range
Spectral range
Readout noise
QE at 700nm
Peak output voltage
45 kHz
1.8 µV/e300 ke-/pixel
75000:1
200 – 1060 nm
4 e- rms
50 %
540 mV
GENERAL DATA
Format
Image area
Active pixels
Pixel size
26.6 x 6.7 mm
1024 (H) x 256 (V)
26 x 26 µm
Package
Package size
Number of pins
Inter-pin spacing
Inter-row spacing
32.89 x 20.07 mm
20
2.54 mm
15.24 mm
quartz or removable
glass
Window material
Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof
and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in its standard conditions of sale in
respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.
e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Holding Company: e2v technologies plc
Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492
Contact e2v by e-mail: enquiries@e2v.com or visit www.e2v.com for global sales and operations centres.
© e2v technologies (uk) limited 2013
A1A-100008 Version 10, September 2013
115188
PERFORMANCE
Min
Typical
Peak charge storage
Max
Units
300,000
Peak output voltage (unbinned)
250
Charge transfer efficiency
e /pixel
1
mV
1
e /pixel/s
2, 6
540
Dark signal at 293 K
Note


500
Parallel
>99.999
%
Serial
>99.999
%
3
1.8
2.3
µV/e
Readout noise at 253 K
4
6
rms e/pixel
4
Readout frequency
45
5000
kHz
5
Photo response non-uniformity (std. deviation)
Binned column dark signal non-uniformity at
293 K (std. deviation)
No. of columns
>50 ke-/s
Binned column DSNU
spikes at 293 K
No. of columns
>200 ke-/s
3
Output amplifier sensitivity
1.3
% of mean
e/pixel/s
15
6
10
6
2
6
ELECTRICAL INTERFACE CHARACTERISTICS
Electrode capacitances (at mid-clock level):
IØ/IØ interphase
Typical
Units
2.0
nF
RØ/RØ interphase
70
pF
IØ/SS
11
nF
RØ/SS
185
pF
Output impedance
300
Ω
NOTES
White column
1.
Black column
2.
3.
4.
5.
6.
Signal level at which resolution begins to degrade. The
typical values are those expected from design.
The typical average (background) dark signal at any
temperature T (kelvin) between 230 and 300 K is given
by:
Qd/Qd0 = 1.14 x 106T3e-9080/T
where Qd0 is the dark current at 293 K. Note that this is
typical performance and some variation may be seen
between devices. Below 230 K additional dark current
components with a weaker temperature dependence
may become significant.
Not routinely measured but expected to exceed the
typical value.
Measured at a pixel readout frequency of 18 KHz using
a dual-slope integrator technique (i.e. correlated
double sampling). All other tests measured at 45 kHz.
Readout above 5000 kHz can be achieved but
performance to the parameters given cannot be
guaranteed.
Dark signal and DSNU values specified at 293 K are
calculated from tests performed at 273 K.
BLEMISH SPECIFICATION
Traps
Black spots
Pixels where charge is temporarily held.
Traps can be seen as a line of trailing
charge.
Are counted when they have a
responsivity outside 10% of the local
mean signal.
© e2v technologies (uk) limited 2013
White spots
A column which contains at least 9 white
defects.
A column which contains at least 9 black
defects.
Are counted when they have a
generation rate 40 times the specified
maximum dark signal generation rate at
293 K. The typical temperature
dependence of white spot blemishes is
different from that of the average dark
signal and is given by:
Qd/Qd0 = 122T3e-6400/T
GRADE
Column defects:
black
white
0
1
2
0
1
6
0
0
0
Black spots
9
16
80
Traps
1
2
5
White spots
10
10
15
Minimum separation between
adjacent black columns ...................................... 50 pixels
Note The amplitude of white spots and columns will
decrease rapidly with temperature.
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A1A-100008 Version 10, page 2
TYPICAL OUTPUT CIRCUIT NOISE (If measured using clamp and sample)
TYPICAL SPECTRAL RESPONSE (No window)
NOTE
7.
Quantum Efficiency is not measured during factory tests. See technical paper on the e2v website titled “UV Conversion
Coatings”.
TYPICAL VARIATION OF DARK CURRENT WITH SUBSTRATE VOLTAGE
© e2v technologies (uk) limited 2013
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A1A-100008 Version 10, page 3
TYPICAL VARIATION OF DARK CURRENT WITH TEMPERATURE
DEVICE SCHEMATIC
© e2v technologies (uk) limited 2013
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A1A-100008 Version 10, page 4
CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS
CLOCK AMPLITUDE OR DC LEVEL
(V) (see note 10)
Min
Typical
Max
MAX RATINGS
with respect to
Substrate SS
PIN
REF
DESCRIPTION
1
-
No connection
2
IØ3
Image section, phase 3 (clock pulse)
10
12
15
20 V
3
IØ2
Image section, phase 2 (clock pulse)
10
12
15
20 V
4
IØ1
Image section, phase 1 (clock pulse)
10
12
15
20 V
5
SS
Substrate
8
8.5
11
-
-
-
6
ØR
Output reset pulse
10
12
15
20 V
7
RØ3
Reset register, phase 3 (clock pulse)
10
12
15
20 V
8
RØ2
Reset register, phase 2 (clock pulse)
10
12
15
20 V
9
RØ1
Reset register, phase 1 (clock pulse)
10
12
15
20 V
10
-
No connection
-
11
-
No connection
-
12
OG
Output gate
13
OS
Output transistor source
14
OD
Output drain
27
30
31
-0.3 to +25 V
15
RD
Reset transistor drain
17
18
19
-0.3 to +25 V
16
SS
Substrate
8
8.5
11
-0.3 to +25 V
17
-
No connection
18
DD
Dump drain
20
22
25
-0.3 to +25 V
19
SG
Spare gate
0
0
VSS +19
20 V
20
-
No connection
2
3.5
5
See note 8
20 V
-0.3 to +25 V
-
-
-
-
If all voltages are set to the ‘typical’ values, operation at or close to typical specification should be obtained. Some adjustment
within the minimum – maximum range specified may be required to optimise performance.
Voltage between pairs of pins: OS to OD + 15 V. Maximum current through any source or drain pin: 10 mA.
SG needs to be grounded to prevent unwanted charge moving into the register.
DD controls the anti blooming function of the register and also biases the drains around the edge of the CCD, protecting the
image and register from charge generated elsewhere spilling into these sensitive regions of the device.
OUTPUT CIRCUIT
NOTES
8.
9.
10.
11.
Not critical; can be a 1 – 5 mA constant current source, or 5 – 10 kΩ resistor.
The amplifier has a DC restoration circuit, which is activated internally whenever IØ3 is pulsed high.
All pulse low levels 0  0.5 V.
Output node capacity is typically 4 times that of the image section.
© e2v technologies (uk) limited 2013
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A1A-100008 Version 10, page 5
FRAME READOUT TIMING DIAGRAM
DETAIL OF LINE TRANSFER
© e2v technologies (uk) limited 2013
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A1A-100008 Version 10, page 6
DETAIL OF OUTPUT CLOCKING
LINE OUTPUT FORMAT
CLOCK TIMING REQUIREMENTS
Symbol
Ti
twi
tri
tfi
toi
tli
tdir
tdri
Tr
trr
tfr
tor
twx
trx , tfx
tdx
Description
Image clock period
Image clock pulse width
Image clock pulse rise time (10 to 90%)
Image clock pulse fall time (10 to 90%)
Image clock pulse overlap
Image clock pulse, two phase low
Delay time, IØ stop to RØ start
Delay time, RØ stop to IØ start
Output register clock cycle period
Clock pulse rise time (10 to 90%)
Clock pulse fall time (10 to 90%)
Clock pulse overlap
Reset pulse width
Reset pulse rise and fall times
Delay time, ØR low to RØ3 low
Min
50
25
5
tri
3
2
3
1
200
50
trr
20
30
20
30
Typ
90
45
20
20
10
10
10
2
See note 13
0.1Tr
0.1Tr
0.5trr
0.1Tr
0.5trr
0.5Tr
Max
See note 12
See note 12
0.5toi
0.5toi
0.2Ti
0.2Ti
See note 12
See note 12
See note 12
0.3Tr
0.3Tr
0.1Tr
0.2Tr
0.2Tr
0.8Tr
Unit
s
s
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
ns
NOTES
12. No maximum other than that necessary to achieve an acceptable dark signal at the longer readout times.
13. As set by the readout period. See note 4.
© e2v technologies (uk) limited 2013
Document subject to disclaimer on page 1
A1A-100008 Version 10, page 7
OUTLINE
(All dimensions without limits are nominal)
Outline Note
The device is normally supplied with a temporary glass
window for protection purposes. It can also be supplied with
a fixed, quartz or fibre-optic window where required.
Ref
Millimetres
A
32.89  0.38
B
C
D
20.07  0.25
6.7
E
15.24  0.25
+ 0.051
0.254
 0.025
5.21
F
G
H
J
3.30  0.33
0.46  0.05
2.54  0.13
K
22.86  0.13
L
M
1.65  0.56
26.6
© e2v technologies (uk) limited 2013
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A1A-100008 Version 10, page 8
ORDERING INFORMATION
HANDLING CCD SENSORS
Options include:
 Temporary Quartz Window
 Permanent Quartz Window
 Temporary Glass Window
For further information on the performance of these and
other options, please contact e2v technologies.
CCD sensors, in common with most high performance MOS
IC devices, are static sensitive. In certain cases a discharge
of static electricity may destroy or irreversibly degrade the
device. Accordingly, full antistatic handling precautions
should be taken whenever using a CCD sensor or module.
These include: Working at a fully grounded workbench
 Operator wearing a grounded wrist strap
 All receiving socket pins to be positively grounded
 Unattended CCDs should not be left out of their
conducting foam or socket.
Evidence of incorrect handling will invalidate the warranty.
All devices are provided with internal protection circuits to
the gate electrodes (pins 2, 3, 4, 6, 7, 8, 9, 12, 19) but not to
the other pins.
HIGH ENERGY RADIATION
Device characteristics will change when subject to ionising
radiation.
Users planning to operate CCDs in high radiation
environments are advised to contact e2v technologies.
TEMPERATURE LIMITS
Min
Storage ............................. 73
Operating .......................... 73
Typical
–
233
Max
373
323
K
K
Operation or storage in humid conditions may give rise to
ice on the sensor surface, causing irreversible damage.
Maximum device heating/cooling ........................... 5 K/min
© e2v technologies (uk) limited 2013
Document subject to disclaimer on page 1
A1A-100008 Version 10, page 9
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