User manual | ATmega1284_P

”Data Retention” on page 9 for details.

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

•

QTouch

library support

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix acquisition

– Up to 64 sense channels

•

JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel, 10-bit ADC

Differential mode with selectable gain at 1x, 10x or 200x

– Byte-oriented Two-wire Serial Interface

– Two Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

•

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and

Extended Standby

•

I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF

– 44-pad DRQFN

– 49-ball VFBGA

•

Operating Voltages

– 1.8 - 5.5V

•

Speed Grades

– 0 - 4MHz @ 1.8 - 5.5V

– 0 - 10MHz @ 2.7 - 5.5V

– 0 - 20MHz @ 4.5 - 5.5V

•

Power Consumption at 1MHz, 1.8V, 25

°C

– Active: 0.4mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.6µA (Including 32kHz RTC)

Note: 1. See

8-bit Atmel

Microcontroller with

16/32/64/128K

Bytes In-System

Programmable

Flash

ATmega164A

ATmega164PA

ATmega324A

ATmega324PA

ATmega644A

ATmega644PA

ATmega1284

ATmega1284P

Summary

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

1. Pin Configurations

1.1

Pinout - PDIP/TQFP/VQFN/QFN/MLF for

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P

Figure 1-1.

Pinout

(PCINT8/XCK0/T0) PB0

(PCINT9/CLKO/T1) PB1

(PCINT10/INT2/AIN0) PB2

(PCINT11/OC0A/AIN1) PB3

(PCINT12/OC0B/SS) PB4

(PCINT13/ICP3/MOSI) PB5

(PCINT14/OC3A/MISO) PB6

(PCINT15/OC3B/SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(PCINT24/RXD0/T3) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

PA4 (ADC4/PCINT4)

PA5 (ADC5/PCINT5)

PA6 (ADC6/PCINT6)

PA7 (ADC7/PCINT7)

AREF

GND

AVCC

PC7 (TOSC2/PCINT23)

PC6 (TOSC1/PCINT22)

PC5 (TDI/PCINT21)

PC4 (TDO/PCINT20)

PC3 (TMS/PCINT19)

PC2 (TCK/PCINT18)

PC1 (SDA/PCINT17)

PC0 (SCL/PCINT16)

PD7 (OC2A/PCINT31)

TQFP/QFN/MLF

8272CS–AVR–06/11

PB4 (SS/OC0B/PCINT12) PB3 (AIN1/OC0A/PCINT1 PB2 (AIN0/INT2/PCINT10) PB1 (T1/CLKO/PCINT9) PB0 (XCK0/T0/PCINT8) GND VCC PA

(PCINT13/ICP3/MOSI) PB5

(PCINT14/OC3A/MISO) PB6

(PCINT15/OC3B/SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(PCINT24/RXD0/T3) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

PA4 (ADC4/PCINT4)

PA5 (ADC5/PCINT5)

PA6 (ADC6/PCINT6)

PA7 (ADC7/PCINT7)

AREF

GND

AVCC

PC7 (TOSC2/PCINT23)

PC6 (TOSC1/PCINT22)

PC5 (TDI/PCINT21)

PC4 (TDO/PCINT20)

VCC GND

(PCINT16/SCL) PC0 (PCINT17/SDA) PC1 (PCINT18/TCK) PC2 (PCINT19/TMS) PC3

(PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4

Note: The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.

ATmega164A/PA/324A/PA/644A/PA/1284/P

1.2

Pinout - DRQFN for ATmega164A/164PA/324A/324PA

Figure 1-2.

DRQFN - Pinout

Top view Bottom view

A18

B15

A17

B14

A16

B13

A15

B12

A14

B11

A13

A18

B15

A17

B14

A16

B13

A15

B12

A14

B11

A13

Table 1-1.

DRQFN - Pinout

PB5

PB6

PB7

RESET

VCC

GND

XTAL2

XTAL1

PD0

PD1

PD2

A10

A11

B10

A12

PD3

PD4

PD5

PD6

PD7

VCC

GND

PC0

PC1

PC2

PC3

A13

B11

A14

B12

A15

B13

A16

B14

A17

B15

A18

PC4

PC5

PC6

PC7

AVCC

GND

AREF

PA7

PA6

PA5

PA4

A19

B16

A20

B17

A21

B18

A22

B19

A23

B20

A24

PA3

PA2

PA1

PA0

VCC

GND

PB0

PB1

PB2

PB3

PB4

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

1.3

Pinout - VFBGA for ATmega164A/164PA/324A/324PA

Figure 1-3.

VFBGA - Pinout

Top view

2 3 4 5 6 7

Bottom view

7 6 5 4 3 2

Table 1-2.

BGA - Pinout

1 2

GND

PB6

VCC

GND

XTAL1

PD2

GND

PB4

PB5

RESET

XTAL2

PD1

PD3

PD4

PB2

PB3

PB7

PD0

PD5

PD6

VCC

GND

PB0

PB1

GND

PD7

PC0

GND

VCC

PA0

PA1

PA4

PC5

PC2

PC1

PA2

PA3

PA6

PA7

PC7

PC4

PC3

GND

PA5

AREF

GND

AVCC

PC6

GND

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

2. Overview

2.1

Block Diagram

The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Figure 2-1.

Block Diagram

PA7..0

PB7..0

VCC

RESET

GND

XTAL1

Power

Supervision

POR / BOD &

RESET

Watchdog

Timer

Watchdog

Oscillator

Circuits /

Clock

Generation

PORT A (8)

A/D

Converter

EEPROM

Internal

Bandgap reference

PORT B (8)

Analog

Comparator

SPI

USART 0

XTAL2

JTAG/OCD

TWI FLASH

CPU

SRAM

8bit T/C 0

16bit T/C 1

8bit T/C 2

16bit T/C 3

16bit T/C 1

USART 1

8272CS–AVR–06/11

PORT C (8) PORT D (8)

TOSC2/PC7 TOSC1/PC6 PC5..0

PD7..0

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following features:

16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities,

512/1K/2K/4Kbytes EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit

ADC with optional differential input stage with programmable gain, programmable Watchdog

Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC

Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and

ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

Atmel offers the QTouch

library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key

Suppression

(AKS

™

) technology for unambiguous detection of key events. The easy-to-use

QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

ATmega164A/PA/324A/PA/644A/PA/1284/P

2.2

Comparison Between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA,

ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P

Table 2-1.

Device

ATmega164A

ATmega164PA

Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A,

ATmega644PA, ATmega1284 and ATmega1284P

Flash EEPROM RAM Units

16 K

512

1 K

ATmega324A

ATmega324PA

ATmega644A

ATmega644PA

ATmega1284

ATmega1284P

32 K

64 K

128 K

1 K

2 K

4 K

2 K

4 K

16 K

16 K bytes

2.3

Pin Descriptions

2.3.1

2.3.2

2.3.3

2.3.4

2.3.5

VCC

Digital supply voltage.

GND

Ground.

Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Converter.

Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

P o r t A a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 80 .

Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

P o r t B a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 82 .

Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

2.3.6

2.3.7

2.3.8

2.3.9

2.3.10

2.3.11

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 85 .

Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

P o r t D a l s o s e r v e s t h e f u n c t i o n s o f v a r i o u s s p e c i a l f e a t u r e s o f t h e

ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 88 .

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characteristics” on page 337 . Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

through a low-pass filter.

AREF

This is the analog reference pin for the Analog-to-digital Converter.

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

3. Resources

A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr.

4. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

The code examples assume that the part specific header file is included before compilation. For

I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and

"STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

Note: 1.

5. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

6. Capacitive touch sensing

The Atmel

QTouch

Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR

microcontrollers. The QTouch Library includes support for the

QTouch and QMatrix

acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states.

The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary . For implementation details and other information, refer to the

Atmel QTouch Library User Guide - also available for download from the Atmel website.

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

7. Register Summary

Address

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

Name

Reserved

UDR1

UBRR1H

UBRR1L

Reserved

UCSR1C

UCSR1B

UCSR1A

Reserved

UDR0

UBRR0H

UBRR0L

Reserved

UCSR0C

UCSR0B

Reserved

UMSEL10

TXCIE1

TXC1

UMSEL00

TXCIE0

Bit 6

UMSEL11

RXCIE1

RXC1

UMSEL01

RXCIE0

Bit 7

UPM11

UDRIE1

UDRE1

UPM01

UDRIE0

Bit 5

Bit 4 Bit 3 Bit 2 Bit 1

USART1 I/O Data Register

USART1 Baud Rate Register High Byte

USART1 Baud Rate Register Low Byte

UPM10

RXEN1

FE1

UPM00

RXEN0

USBS1

TXEN1

DOR1

USBS0

TXEN0

UCSZ11/UDORD0

UCSZ12

UPE1

UCSZ10/UCPHA0

RXB81

U2X1

USART0 I/O Data Register

USART0 Baud Rate Register High Byte

USART0 Baud Rate Register Low Byte

UCSZ01/UDORD0

UCSZ02

UCSZ00/UCPHA0

RXB80

Bit 0

Page

UCPOL1

TXB81

MPCM1

UCPOL0

TXB80

192

196 / 209

194 / 208

193 / 207

192 / 207

192

196 / 209

194 / 208

193 / 207

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

Name

TCCR3A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Reserved

OCR3BH

OCR3BL

OCR3AH

OCR3AL

ICR3H

ICR3L

TCNT3H

TCNT3L

Reserved

TCCR3C

TCCR3B

TCCR2A

Reserved

UCSR0A

Reserved

TWAMR

TWCR

TWDR

TWAR

TWSR

TWBR

Reserved

ASSR

Reserved

OCR2B

OCR2A

TCNT2

TCCR2B

Address

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xC0)

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

Bit 7

RXC0

TWAM6

TWINT

TWA6

TWS7

Bit 6

TXC0

TWAM5

TWEA

TWA5

TWS6

EXCLK

FOC2A

COM2A1

FOC2B

COM2A0

FOC3A

ICNC3

COM3A1

FOC3B

ICES3

COM3A0

FOC1A

ICNC1

COM1A1

FOC1B

ICES1

COM1A0

Bit 5

UDRE0

TWAM4

TWSTA

TWA4

TWS5

AS2

COM2B1

COM3B1

COM1B1

Bit 4 Bit 3 Bit 2

COM2B0

FE0

TWAM3

DOR0

TWAM2

UPE0

TWAM1

TWSTO TWWC TWEN

2-wire Serial Interface Data Register

TWA3

TWS4

TWA2

TWS3

TWA1

2-wire Serial Interface Bit Rate Register

TCN2UB

OCR2AUB

OCR2BUB

Timer/Counter2 Output Compare Register B

Timer/Counter2 Output Compare Register A

Timer/Counter2 (8 Bit)

WGM22 CS22

Timer/Counter3 - Output Compare Register B High Byte

Timer/Counter3 - Output Compare Register B Low Byte

Timer/Counter3 - Output Compare Register A High Byte

Timer/Counter3 - Output Compare Register A Low Byte

Timer/Counter3 - Input Capture Register High Byte

Timer/Counter3 - Input Capture Register Low Byte

Timer/Counter3 - Counter Register High Byte

Timer/Counter3 - Counter Register Low Byte

WGM33

WGM32

CS32

COM3B0

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

Timer/Counter1 - Counter Register Low Byte

WGM13

WGM12

CS12

COM1B0

Bit 1

U2X0

TWAM0

TWA0

TWPS1

TCR2AUB

CS31

WGM31

CS11

WGM11

AIN1D

CS21

WGM21

CS20

WGM20

Bit 0

MPCM0

TWIE

TWGCE

TWPS0

TCR2BUB

Page

192 / 207

238

235

237

238

237

235

161

160

159

156

CS30

WGM30

137

136

137

136

135

134

132

CS10

WGM10

AIN0D

137

136

137

136

135

134

132

242

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

Name

SPDR

SPSR

SPCR

GPIOR2

GPIOR1

Reserved

OCR0B

OCR0A

TCNT0

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

EEDR

EECR

GPIOR0

EIMSK

SPH

SPL

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

Reserved

OCDR

ACSR

Reserved

TIMSK0

PCMSK2

PCMSK1

PCMSK0

Reserved

EICRA

PCICR

Reserved

OSCCAL

Reserved

PRR

Reserved

CLKPR

WDTCSR

SREG

DIDR0

Reserved

ADMUX

ADCSRB

ADCSRA

ADCH

ADCL

Reserved

PCMSK3

Reserved

TIMSK3

TIMSK2

TIMSK1

Address

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

(0x6E)

(0x6D)

(0x6C)

(0x6B)

(0x6A)

(0x69)

(0x68)

(0x67)

(0x66)

(0x65)

(0x64)

(0x63)

(0x62)

(0x61)

(0x60)

0x3F (0x5F)

(0x76)

(0x75)

(0x74)

(0x73)

(0x72)

(0x71)

(0x70)

(0x6F)

(0x7E)

(0x7D)

(0x7C)

(0x7B)

(0x7A)

(0x79)

(0x78)

(0x77)

PRTIM2

WDIE

SP14

SP6

RWWSB

BODS

(6)

ACBG

PCINT30

PCINT22

PCINT14

PCINT6

WCOL0

SPE0

PRTWI

CLKPCE

WDIF

SP15

SP7

SPMIE

JTD

ACD

PCINT31

PCINT23

PCINT15

PCINT7

SPIF0

SPIE0

Bit 7

ADC7D

REFS1

ADEN

FOC0A

COM0A1

TSM

FOC0B

COM0A0

Bit 6

ADC6D

REFS0

ACME

ADSC

Bit 5

ADC5D

ADLAR

ADATE

PRTIM0

WDP3

SP13

SP5

SIGRD

BODSE

(6)

ACO

PCINT29

ICIE3

ICIE1

PCINT21

PCINT13

PCINT5

ISC21

DORD0

COM0B1

EEPM1

Bit 4 Bit 3 Bit 2 Bit 1

ADC4D

MUX4

ADC3D

MUX3

ADC2D

MUX2

ADTS2

ADIF ADIE

ADC Data Register High byte

ADPS2

ADC Data Register Low byte

PCINT28

PCINT20

PCINT12

PCINT4

ISC20

PCINT27

PCINT19

PCINT11

PCINT3

ISC11

PCIE3

PCINT26

OCIE3B

OCIE2B

OCIE1B

OCIE0B

PCINT18

PCINT10

PCINT2

ISC10

PCIE2

ADC1D

MUX1

ADTS1

ADPS1

Oscillator Calibration Register

PRUSART1

PRTIM1

PRSPI

WDCE

CLKPS3

WDE

CLKPS2

WDP2

SP12

SP4

RWWSRE

SP11

SP3

BLBSET

SP10

SP2

PGWRT

PUD

JTRF

WDRF

SM2

BORF

SM1

ACI

On-Chip Debug Register

ACIE

ACIC

MSTR0

SPI 0 Data Register

CPOL0

General Purpose I/O Register 2

CPHA0

IVSEL

EXTRF

SM0

ACIS1

SPR01

General Purpose I/O Register 1

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

COM0B0

Timer/Counter0 (8 Bit)

WGM02

CS02

CS01

WGM01

PSRASY

EEPROM Address Register High Byte

EEPROM Address Register Low Byte

EEPM0

EEPROM Data Register

EERIE EEMPE EEPE

General Purpose I/O Register 0

INT2 INT1

PRUSART0

CLKPS1

WDP1

SP9

SP1

PGERS

PCINT25

OCIE3A

OCIE2A

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

ISC01

PCIE1

Bit 0

ADC0D

MUX0

ADTS0

ADPS0

CS00

WGM00

PSRSYNC

EERE

INT0

295

91 / 278

58 / 278

268

260

108

107

108

163

173

172

171

PRADC

CLKPS0

WDP0

SP8

SP0

SPMEN

IVCE

PORF

ACIS0

PCINT24

TOIE3

TOIE2

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

ISC00

PCIE0

SPI2X0

SPR00

139

162

138

109

Page

262

258

241

260

261

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

Address

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

Name

Reserved

PORTD

DDRD

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

PORTA

DDRA

PINA

EIFR

PCIFR

Reserved

TIFR3

TIFR2

TIFR1

TIFR0

Reserved

Bit 6

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

PORTA6

DDA6

PINA6

Bit 7

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

PORTA7

DDA7

PINA7

Bit 4

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

PORTA4

DDA4

PINA4

Bit 5

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

PORTA5

DDA5

PINA5

ICF3

ICF1

Bit 2

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

PORTA2

DDA2

PINA2

INTF2

PCIF2

OCF3B

OCF2B

OCF1B

OCF0B

Bit 3

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

PORTA3

DDA3

PINA3

PCIF3

Bit 1

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

PORTA1

DDA1

PINA1

INTF1

PCIF1

OCF3A

OCF2A

OCF1A

OCF0A

Page

140

162

139

109

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses.

The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

5. USART in SPI Master Mode.

6. Only available in the ATmega164PA/324PA/644PA/1284P.

Bit 0

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

PORTA0

DDA0

PINA0

INTF0

PCIF0

TOV3

TOV2

TOV1

TOV0

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

8. Instruction Set Summary

Mnemonics Operands Description

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

SBRS

SBIC

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRHC

BRTS

BRTC

BRVS

ORI

EOR

COM

NEG

SBR

CBR

INC

DEC

TST

CLR

SER

MUL

MULS

MULSU

FMUL

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr

ADC Rd, Rr

Add two Registers

Add with Carry two Registers

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd, K

Rd, Rr

Rd,K

Rd, Rr

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Multiply Unsigned

Multiply Signed

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

CALL

RET

RETI

CPSE

CPC

CPI

SBRC

FMULS

FMULSU

Rd, Rr

BRANCH INSTRUCTIONS

RJMP k

IJMP

JMP

RCALL

ICALL k k k

Rd,Rr

Rd,K

Rr, b

Relative Jump

Indirect Jump to (Z)

Direct Jump

Relative Subroutine Call

Indirect Call to (Z)

Direct Subroutine Call

Subroutine Return

Interrupt Return

Compare, Skip if Equal

Compare

Compare with Carry

Compare Register with Immediate

Skip if Bit in Register Cleared

k s, k

Rr, b

P, b

P, b s, k

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Operation

← Rd + Rr

← Rd + Rr + C

Rdh:Rdl

← Rdh:Rdl + K

← Rd - Rr

← Rd - K

← Rd - Rr - C

← Rd - K - C

Rdh:Rdl

← Rdh:Rdl - K

← Rd • Rr

← Rd • K

← Rd v Rr

← Rd v K

← Rd ⊕ Rr

← 0xFF − Rd

← 0x00 − Rd

← Rd v K

← Rd • (0xFF - K)

← Rd + 1

← Rd − 1

← Rd • Rd

← Rd ⊕ Rd

← 0xFF

R1:R0

← Rd x Rr

R1:R0

← Rd x Rr

R1:R0

← Rd x Rr

R1:R0

← (Rd x Rr) << 1

R1:R0

← (Rd x Rr) << 1

R1:R0

← (Rd x Rr) << 1

← PC + k + 1

← Z

← k

← PC + k + 1

← Z

← k

← STACK

← STACK if (Rd = Rr) PC

← PC + 2 or 3

− Rr

− Rr − C

− K if (Rr(b)=0) PC

← PC + 2 or 3 if (Rr(b)=1) PC

← PC + 2 or 3 if (P(b)=0) PC

← PC + 2 or 3 if (P(b)=1) PC

← PC + 2 or 3 if (SREG(s) = 1) then PC

←PC+k + 1 if (SREG(s) = 0) then PC

←PC+k + 1 if (Z = 1) then PC

← PC + k + 1 if (Z = 0) then PC

← PC + k + 1 if (C = 1) then PC

← PC + k + 1 if (C = 0) then PC

← PC + k + 1 if (C = 1) then PC

← PC + k + 1 if (N = 1) then PC

← PC + k + 1 if (N = 0) then PC

← PC + k + 1 if (N

⊕ V= 0) then PC ← PC + k + 1 if (N

⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC

← PC + k + 1 if (H = 0) then PC

← PC + k + 1 if (T = 1) then PC

← PC + k + 1 if (T = 0) then PC

← PC + k + 1 if (V = 1) then PC

← PC + k + 1

#Clocks

1/2

1/2/3

1/2

1/2/3

Flags

None

Z, N,V,C,H

None

Z,C

Z,C,N,V,H

Z,N,V

None

Z,C

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

Z,C,N,V

8272CS–AVR–06/11

Mnemonics Operands

STD

STS

LPM

SPM

OUT

LDS

STD

LDD

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BRVC

BRIE

BRID

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b

CBI

LSL

LSR

P,b

Rd s s

Rr, b

Rd, b

CLI

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr

MOVW Rd, Rr

LDI

Rd, K

Rd, X

Rd, X+

Rd, - X

Rd, k

X, Rr

X+, Rr

- X, Rr

Y, Rr

Y+, Rr

- Y, Rr

Y+q,Rr

Rd, Y

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Rd, Z+

Rd, -Z

Rd, Z+q

Z, Rr

Z+, Rr

-Z, Rr

Z+q,Rr k, Rr

Rd, Z

Rd, Z+

Rd, P

P, Rr

Description

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Flag Set

Flag Clear

Bit Store from Register to T

Bit load from T to Register

Set Carry

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

Move Between Registers

Copy Register Word

Load Immediate

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

Out Port

ATmega164A/PA/324A/PA/644A/PA/1284/P

← Rr

Rd+1:Rd

← Rr+1:Rr

← K

← (X)

← (X), X ← X + 1

← X - 1, Rd ← (X)

← (Y)

← (Y), Y ← Y + 1

← Y - 1, Rd ← (Y)

← (Y + q)

← (Z)

← (Z), Z ← Z+1

← Z - 1, Rd ← (Z)

← (Z + q)

← (k)

(X)

← Rr

(X)

← Rr, X ← X + 1

← X - 1, (X) ← Rr

(Y)

← Rr

(Y)

← Rr, Y ← Y + 1

← Y - 1, (Y) ← Rr

(Y + q)

← Rr

(Z)

← Rr

(Z)

← Rr, Z ← Z + 1

← Z - 1, (Z) ← Rr

(Z + q)

← Rr

(k)

← Rr

← (Z)

← (Z), Z ← Z+1

(Z)

← R1:R0

← P

← Rr

Operation

if (V = 0) then PC

← PC + k + 1 if ( I = 1) then PC

← PC + k + 1 if ( I = 0) then PC

← PC + k + 1

← 1

← 0

← 1

← 0

← 1

← 0

← 1

← 0

← 1

← 0

← 1

← 0

← 1

← 0

I/O(P,b)

← 1

I/O(P,b)

← 0

Rd(n+1)

← Rd(n), Rd(0) ← 0

Rd(n)

← Rd(n+1), Rd(7) ← 0

Rd(0)

←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)

←C,Rd(n)← Rd(n+1),C←Rd(0)

Rd(n)

← Rd(n+1), n=0..6

Rd(3..0)

←Rd(7..4),Rd(7..4)←Rd(3..0)

SREG(s)

← 1

SREG(s)

← 0

← Rr(b)

Rd(b)

← T

← 1

← 0

#Clocks

1/2

Flags

None

Z,C,N,V

None

SREG(s)

None

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

Mnemonics Operands

PUSH

POP

MCU CONTROL INSTRUCTIONS

NOP

SLEEP

WDR

BREAK

Push Register on Stack

Pop Register from Stack

Description

No Operation

Sleep

Watchdog Reset

Break

STACK

← Rr

← STACK

Operation

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Flags

None

#Clocks

N/A

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

9. Ordering Information

9.1

ATmega164A

Power Supply

20 1.8 - 5.5V

Ordering Code

ATmega164A-AU

ATmega164A-AUR

ATmega164A-PU

ATmega164A-MU

ATmega164A-MCHR

(4)(5)

ATmega164A-CU

ATmega164A-CUR

Package

44A

40P6

44M1

44MC

49C2

Operational Range

Industrial

(-40 o

C to 85 o

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 335 .

4. NiPdAu Lead Finish.

5. Tape & Reel.

44A

40P6

44M1

44MC

49C2

8272CS–AVR–06/11

Package Type

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)

44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN)

49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)

ATmega164A/PA/324A/PA/644A/PA/1284/P

9.2

ATmega164PA

Power Supply

20 1.8 - 5.5V

Ordering Code

ATmega164PA-AU

ATmega164PA-AUR

ATmega164PA-PU

ATmega164PA-MU

ATmega164PA-MUR

ATmega164PA-MCH

ATmega164PA-MCHR

(4)(5)

ATmega164PA-CU

ATmega164PA-CUR

Package

44A

40P6

44M1

44MC

49C2

Operational Range

Industrial

(-40 o

C to 85 o

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 335 .

4. NiPdAu Lead Finish.

5. Tape & Reel.

44A

40P6

44M1

44MC

49C2

8272CS–AVR–06/11

Package Type

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)

44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN)

49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)

ATmega164A/PA/324A/PA/644A/PA/1284/P

9.3

ATmega324A

Power Supply

20 1.8 - 5.5V

Ordering Code

ATmega324A-AU

ATmega324A-AUR

ATmega324A-PU

ATmega324A-MU

ATmega324A-MCHR

(4)(5)

ATmega324A-CU

ATmega324A-CUR

Package

44A

40P6

44M1

44MC

49C2

Operational Range

Industrial

(-40 o

C to 85 o

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 335 .

4. NiPdAu Lead Finish.

5. Tape & Reel.

44A

40P6

44M1

44MC

49C2

8272CS–AVR–06/11

Package Type

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)

44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN)

49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)

ATmega164A/PA/324A/PA/644A/PA/1284/P

9.4

ATmega324PA

Speed (MHz)

(3)

Power Supply

20 1.8 - 5.5V

Ordering Code

(2)

ATmega324PA-AU

ATmega324PA-AUR

ATmega324PA-PU

ATmega324PA-MU

ATmega324PA-MUR

ATmega324PA-MCH

(4)

ATmega324PA-MCHR

(4)(5)

ATmega324PA-CU

ATmega324PA-CUR

Package

44A

40P6

44M1

44MC

49C2

(1)

Operational Range

Industrial

(-40 o

C to 85 o

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 335 .

4. NiPdAu Lead Finish.

5. Tape & Reel.

44A

40P6

44M1

44MC

49C2

8272CS–AVR–06/11

Package Type

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)

44-lead (2-row Staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No-Lead Package (QFN)

49-ball, (7 x 7 Array) 0.65 mm Pitch, 5 x 5 x 1 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)

ATmega164A/PA/324A/PA/644A/PA/1284/P

9.5

ATmega644A

Power Supply

20 1.8 - 5.5V

Ordering Code

ATmega644A-AU

ATmega644A-AUR

ATmega644A-PU

ATmega644A-MU

ATmega644A-MUR

Package

(1)

44A

40P6

44M1

Operational Range

Industrial

(-40 o

C to 85 o

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 335 .

4. Taper & Reel.

44A

40P6

44M1

8272CS–AVR–06/11

Package Type

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)

ATmega164A/PA/324A/PA/644A/PA/1284/P

9.6

ATmega644PA

Power Supply

20 1.8 - 5.5V

Ordering Code

ATmega644PA-AU

ATmega644PA-AUR

ATmega644PA-PU

ATmega644PA-MU

ATmega644PA-MUR

Package

(1)

44A

40P6

44M1

Operational Range

Industrial

(-40 o

C to 85 o

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 335 .

4. Taper & Reel.

44A

40P6

44M1

8272CS–AVR–06/11

Package Type

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)

ATmega164A/PA/324A/PA/644A/PA/1284/P

9.7

ATmega1284

Power Supply

20 1.8 - 5.5V

Ordering Code

ATmega1284-AU

ATmega1284-AUR

ATmega1284-PU

ATmega1284-MU

ATmega1284-MUR

Package

44A

40P6

44M1

Operational Range

Industrial

(-40 o

C to 85 o

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V

see ”Speed Grades” on page 335 .

4. Tape & Reel.

44A

40P6

44M1

Package Type

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

8272CS–AVR–06/11

ATmega164A/PA/324A/PA/644A/PA/1284/P

9.8

ATmega1284P

Power Supply

20 1.8 - 5.5V

Ordering Code

ATmega1284P-AU

ATmega1284P-AUR

ATmega1284P-PU

ATmega1284P-MU

ATmega1284P-MUR

Package