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Virtex-5 FPGA Embedded
Tri-Mode Ethernet MAC Wrapper v1.7
Product Specification DS550 April 19, 2010
Introduction
The LogiCORE™ IP Virtex®-5 FPGA Embedded
Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded
Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-5
LXT, SXT, FXT and TXT FPGAs using the Xilinx®
CORE Generator™ software.
VHDL and Verilog instantiation templates are available in the Libraries Guide for the Virtex-5 FPGA Ethernet
MAC primitive; however, due to the complexity and large number of ports, the CORE Generator software simplifies integration of the Ethernet MAC by providing HDL examples based on user-selectable configurations.
Features
• Allows selection of one or both Ethernet MACs
(EMAC0/EMAC1) from the Ethernet MAC primitive
• Sets the EMAC0/EMAC1 attributes based on user options
• Provides user-configurable Ethernet MAC physical interfaces
♦ Supports MII, GMII, RGMII v1.3, RGMII v2.0,
SGMII, and 1000BASE-X PCS/PMA interfaces
♦ Instantiates clock buffers, DCMs, Virtex-5
FPGA RocketIO™ GTP or GTX transceivers, and logic as required for the selected physical interfaces
• Provides a simple FIFO-loopback example design, connected to the MAC client interfaces
• Provides a simple demonstration test bench based on the selected configuration
• Generates VHDL or Verilog
LogiCORE IP Facts
Supported FPGA
Family 1
Virtex-5
Performance
10 Mbps, 100 Mbps, 1 Gbps
Example Design Resources
LUTs 380-930 2
FFs 440-1220 2
Block RAMs (18k) 4-10 2
DCM 0-1 2
BUFG 2-10 2
Wrapper Highlights
Optimized Clocking
Logic
HDL Example Design
Hardware Verified
Example Designs
Demonstration Test Bench
Documentation
Constraints File
Provided with Wrapper
Product Specification
Getting Started Guide
User Guide 3
Design File Formats HDL Example Design,
Demonstration Test Bench, Scripts
User Constraints File (.ucf)
Example FIFO connected to Client I/F
Demonstration Test Environment
Supported HDL
Design Tool Requirements
VHDL and/or Verilog
Synthesis
XST 12.1
Xilinx Tools
ISE® 12.1
Simulation Tools 4 Mentor Graphics ModelSim 6.5c and above 5
Cadence Incisive Enterprise Simulator
(IES) v9.2 and above 5
Synopsys VCS and VCS MX 2009.12
and above 5
1.
For the complete list of supported devices, see the 12.1 release notes for this core.
2.
The precise number depends on user configuration; see
3.
Available from www.xilinx.com/support/documentation/ ip_documentation/ug194.pdf
.
4.
Requires a Verilog LRM-IEEE 1364-2005 encryption-compliant simulator. For VHDL simulation, a mixed HDL license is required.
5.
Scripts provided for listed simulators only.
© 2006-2010 Xilinx, Inc. Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their respective owners.
DS550 April 19, 2010
Product Specification www.xilinx.com
1
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
Ethernet Architecture Overview
X-Ref Target - Figure 1
Physical Sublayers
TCP IP
FIFO
I/F
Ethernet
MAC
GMII/MII
RGMII
SGMII (RocketIO)
PCS
Figure 1: Typical Ethernet Architecture
PMA
1000BASE-X
(RocketIO)
PMD
displays the Ethernet MAC architecture from the MAC to the right, as defined in the IEEE
802.3 specification, and also illustrates where the supported physical interfaces fit into the architecture.
MAC
The Ethernet MAC is defined in the IEEE 802.3 specification clauses 2, 3, and 4. A MAC is responsible for the Ethernet framing protocols and error detection of these frames. The MAC is independent of, and can connect to, any type of physical sublayer.
GMII/MII
The Media Independent Interface (MII), defined in IEEE 802.3 clause 22, is a parallel interface that connects a 10-Mbps and/or 100-Mbps capable MAC to the physical sublayers. The Gigabit Media Independent Interface (GMII), defined in IEEE 802.3 clause 35, is an extension of the MII used to connect a
1-Gbps capable MAC to the physical sublayers. MII can be considered a subset of GMII, and as a result,
GMII/MII can carry Ethernet traffic at 10 Mbps, 100 Mbps, and 1 Gbps.
RGMII
The Reduced-GMII (RGMII) is an alternative to GMII/MII. RGMII achieves a 50-percent reduction in the pin count, achieved by the use of double-data-rate (DDR) flip-flops. For this reason, RGMII is preferred over GMII by PCB designers. RGMII can carry Ethernet traffic at 10 Mbps, 100 Mbps, and 1
Gbps.
SGMII
The Serial-GMII (SGMII) interface is an alternative to GMII/MII. SGMII converts the parallel interface of the GMII/MII into a serial format using a RocketIO GTP or GTX transceiver, radically reducing the
I/O count. For this reason, it is often the preferred interface of PCB designers. SGMII can carry Ethernet traffic at 10 Mbps, 100 Mbps, and 1 Gbps.
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Product Specification
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
PCS, PMA, PMD
The combination of the Physical Coding Sublayer (PCS), the Physical Medium Attachment (PMA), and the Physical Medium Dependent (PMD) sublayer comprise the physical layers of the Ethernet protocol.
Two main physical standards are specified for Ethernet:
• BASE-T, a copper standard using twisted pair cabling systems
• BASE-X, usually a fibre optical physical standard using short and long wavelength laser
BASE-T devices, supporting 10 Mbps, 100 Mbps, and 1 Gbps Ethernet speeds, are readily available as off-the-shelf parts. As illustrated in
, these can be connected using GMII/MII, RGMII, or
SGMII to provide a tri-speed Ethernet port.
The Ethernet MAC has built-in 1000BASE-X PCS/PMA functionality and can be connected to a Rock-
etIO GTP or GTX transceiver to provide a 1 Gbps fibre optic port, as illustrated in Figure 3
.
Applications
Typical applications for the Ethernet MAC core include
•
Ethernet Tri-speed BASE-T Port
•
Ethernet Tri-speed BASE-T Port
illustrates a typical application for a single Ethernet MAC. The PHY side of the core is implementing an external GMII/MII by connecting it to IOBs; the external GMII/MII is connected to an off-the-shelf Ethernet PHY device, which performs the BASE-T standard at 1 Gbps, 100 Mbps, and 10
Mbps speeds. Alternatively, the external GMII/MII can be replaced with an RGMII (as shown) or as an
SGMII (which requires the use of a RocketIO GTP or GTX transceiver). GMII, RGMII, and SGMII functionality are demonstrated in the HDL examples provided with the example design.
The client side of the Ethernet MAC is shown connected to the 10 Mbps, 100 Mbps, 1 Gbps Ethernet
FIFO (delivered with the example design) to complete a single Ethernet port. This port is displayed connected to a Switch or Routing matrix, which can contain several ports.
X-Ref Target - Figure 2
GMII/MII
(or RGMII)
Virtex-5 Device
Ethernet MAC
Switch or
Router
10 Mbps,
100 Mbps,
1 Gbps
Ethernet FIFO
MAC
IOBs
Tri-speed
BASE-T
PHY
Twisted
Copper
Pair
10 Mbps,
100 Mbps,
1 Gbps
Figure 2: Typical 1000BASE-T Application
DS550 April 19, 2010
Product Specification www.xilinx.com
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Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
Ethernet 1000BASE-X Port
illustrates a typical application for a single Ethernet MAC. The PHY side of the MAC is connected to a RocketIO GTP or GTX transceiver, which in turn is connected to an external off-the-shelf
GBIC or SFP optical transceiver. The 1000BASE-X logic can be optionally provided by the Ethernet
MAC, as displayed. 1000BASE-X functionality is demonstrated in the HDL examples provided with the example design.
The client side of the Ethernet MAC is shown connected to the 10 Mbps, 100 Mbps, 1 Gbps Ethernet
FIFO (delivered with the example design) to complete a single Gigabit Ethernet port. This port is connected to a Switch or Routing matrix, which can contain several ports
X-Ref Target - Figure 3
PMA
Ethernet MAC
Switch or
Router
10 Mbps,
100 Mbps,
1 Gbps
Ethernet FIFO
MAC
RocketIO
Transceiver
TXP/TXN
GBIC or
SFP
Optical
Transceiver
Optical
Fiber
RXP/RXN
1 Gbps
Figure 3: Typical 1000BASE-X Application
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Product Specification
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
Example Design Overview
illustrates the major functional blocks of the Ethernet MAC example design. All illustrated components are provided in HDL, with the exception of the Ethernet MAC component.
X-Ref Target - Figure 4 component_name_example_design
FPGA
Fabric
Clock
Circuitry component_name_locallink component_name_block
Address
Swap
Module
10M/100M/1G
Ethernet FIFO Client
Interface
Tx Client
FIFO
Rx Client
FIFO
Embedded Ethernet
MAC Wrapper
Embedded
Ethernet MAC
EMAC0
Physical
Interface
Physical I/F
(GMII/MII,
RGMII, or RocketIO
Host
Interface
Address
Swap
Module
10M/100M/1G
Ethernet FIFO
Tx Client
FIFO
Rx Client
FIFO
EMAC1
Physical I/F
(GMII/MII,
RGMII, or
RocketIO)
Figure 4: Example Design
DS550 April 19, 2010
Product Specification www.xilinx.com
5
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
Ethernet MAC Example Design
The example design is arranged for quick adaptation and can be downloaded onto an FPGA to provide a real hardware test environment. In addition, all the clock management logic required to operate the
Ethernet MAC and its example design is provided. DCMs, BUFGs, and so forth are instantiated as required.
The data is looped back at the client interface, enabling the Ethernet MAC to be quickly connected to a protocol tester—frames injected into the Ethernet MAC PHY Receive port are relayed back through the
Ethernet MAC and out through the Ethernet MACs PHY Transmit port. Using this method, they are received back at the protocol tester.
The design includes an Address Swapping Module and a FIFO. Frames received by the Ethernet MAC are passed through the Receive side of the FIFO. Data from the Receive side of the FIFO is passed into the Address Swap Module and then on to the Transmit side of the FIFO using a LocalLink interface.
The Transmit FIFO queues frames for transmission and connects directly to the client side Transmit interface of the Ethernet MAC.
Address Swap Module
The Address Swap Module switches the Destination Address and Source Address within the received
MAC frame. Using this method, frames received from a link partner, for example a protocol tester, are relayed back to the correct Destination Address.
10 Mbps, 100 Mbps, 1 Gbps Ethernet FIFO
The 10 Mbps, 100 Mbps, 1 Gbps Ethernet FIFO is a wrapper file around the Receive and Transmit FIFO components. These components can be used in more complex client applications, as illustrated in
and 3 . To use the FIFOs, the component_name_locallink component can be instantiated in the
user design.
Receive Client FIFO
The Receive (Rx) Client FIFO, a 4k-byte FIFO implemented in block RAMs, can be used for more complex client applications and can be connected directly to the Rx Client Interface of the Ethernet MAC.
The Rx Client provides a LocalLink connection for the user.
• The FIFO operates at all Ethernet speeds supported by the Ethernet MAC.
• The FIFO drops all frames marked as bad from the Ethernet MAC so that only error-free frames are passed to the Ethernet client.
Transmit Client FIFO
The Transmit (Tx) Client FIFO, a 4k-byte FIFO implemented in block RAMs, can used for more complex client applications and can be connected directly to the Tx Client Interface of the Ethernet MAC. The Tx
Client FIFO provides a LocalLink connection for the user.
• The FIFO operates at all Ethernet speeds supported by the Ethernet MAC.
• The FIFO is capable of half-duplex re-transmission. For this reason, if a collision occurs on the medium, the Ethernet MAC indicates a collision on the Tx Client interface and the FIFO automatically re-queues the frame for re-transmission.
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Product Specification
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
Ethernet MAC Wrapper
The Ethernet MAC wrapper file instantiates the full Ethernet MAC primitive. For one or both Ethernet
MACs (EMAC0/EMAC1), the following applies:
• All unused input ports on the primitive are tied to the appropriate logic level; all unused output ports are left unconnected.
• The Ethernet MAC attributes are set based on options selected in the CORE Generator software.
• Only used ports are connected to the ports of the wrapper file.
This simplified wrapper should be used as the instantiation template for the Ethernet MAC in customer designs.
Physical I/F
An appropriate Physical Interface is provided for each selected EMAC0/EMAC1. This interface connects the physical interface of the Ethernet MAC block to the I/O of the FPGA. As required, the following components are provided:
• For GMII/MII, this component contains Input/Output block (IOB) buffers and IOB flip-flops.
• For RGMII, this component contains contain IOB buffers, IOB Double-Data Rate flip-flops and
IODELAY elements to align the incoming data with the receiver clock. An IODELAY element is also used to delay the transmitted clock in RGMII V2.0.
• For 1000BASE-X PCS/PMA or SGMII, this component instantiates and connects a RocketIO GTP or GTX transceiver.
DS550 April 19, 2010
Product Specification www.xilinx.com
7
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
Device Utilization
The following sections provide approximate device-utilization figures for common configurations of the Ethernet MAC and its example design:
•
•
•
Of interest is the utilization of clock resources, specifically the global clock usage (BUFGs), which should influence the selection of the interface type. Note that these clock resource figures do not consider any clock that can be used for the Host Interface.
1 Gbps Only Operation
defines approximate utilization figures for common configurations of the Ethernet MAC and its example design for 1 Gbps operation.
Table 1: Device Utilization for 1 Gbps Operation
Parameter Values
Physical
Interface
GMII
Ethernet MAC
Usage
Single EMAC
Both EMACs
LUTs
380
760
Registers
450
880
RGMII 1.3
RGMII 2.0
SGMII
1000BASE-X
(8-bit client)
1000BASE-X
(16-bit client)
Single EMAC
Both EMACs
Single EMAC
Both EMACs
Single EMAC
Both EMACs
Single EMAC
Both EMACs
Single EMAC
Both EMACs
390
780
390
780
380
760
380
760
370
730
440
870
440
870
460
900
460
900
560
1120
Device Resources
18K Block
RAMs
4
8
4
8
4
8
4
8
4
8
4
8
BUFGs
1
1
1
1
3
3
2 1
3
2
3
2
3
DCMs
0
0
0
0
0
0
0
0
1
1
0
0
1.
These implementations use IDLEAY elements, which require a 200MHz reference clock for the associated IDELAYCTRL. The reference clock's BUFG is not accounted for.
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Product Specification
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
Tri-Speed Operation
defines approximate utilization figures for common configurations of the Ethernet MAC and its example design 10 Mbps, 100 Mbps, or 1 Gbps operation.
Table 2: Device Utilization for Tri-Speed Operation
Parameter Values
Physical
Interface
Ethernet MAC
Usage
LUTs
Device Resources
Registers
18K Block
RAMs
BUFGs
GMII/MII
(standard clocking)
GMII/MII (with clock enable)
Single EMAC
Both EMACs
Single EMAC
400
790
400
480
950
500
4
8
4
5
1
GMII/MII (with byte PHY)
RGMII 1.3
(standard clocking)
Both EMACs
Single EMAC
Both EMACs
Single EMAC
Both EMACs
790
410
810
400
790
980
510
990
490
970
8
4
8
4
8
RGMII 1.3
(with clock enable)
RGMII 2.0
(standard clocking)
Single EMAC
Both EMACs
Single EMAC
Both EMACs
400
790
400
790
510
1000
490
970
4
8
4
8
RGMII 2.0
(with clock enable)
SGMII
Single EMAC
Both EMACs
Single EMAC
400
790
470
510
1000
620
4
8
5
2
RCLKs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Both EMACs 930 1220 10 3 2
1.
These implementations use IDLEAY elements, which require a 200MHz reference clock for the associated IDELAYCTRL. The reference clock's BUFG is not accounted for.
DS550 April 19, 2010
Product Specification www.xilinx.com
9
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
100 Mbps or 10 Mbps Operation
provides approximate utilization figures for common configurations of the Ethernet MAC and
.
Table 3: Device Utilization for 10 Mbps, 100 Mbps Operation
Parameter Values Device Resources
Physical
Interface
Ethernet MAC
Usage
LUTs Registers
18K Block
RAMs
BUFGs
MII (standard clocking)
MII (with clock enable)
MII (with byte
PHY)
Single EMAC
Both EMACs
Single EMAC
Both EMACs
Single EMAC
Both EMACs
400
780
390
780
400
800
460
920
480
950
480
960
4
8
4
8
4
8
2
4
4
8
2
4
Ordering Information
The Ethernet MAC wrapper is provided under the End User License Agreement and can be generated using CORE Generator software v12.1 and higher. The CORE Generator software is shipped with
Xilinx ISE Design Suite Series Development software.
In ISE v12.1 and later, a license key is not required to access the IP. To access the wrapper in ISE v11.4
and older, a no cost full license must be obtained from Xilinx. See the product page: www.xilinx.com/products/ipcenter/V5_Embedded_TEMAC_Wrapper.htm
Contact your local Xilinx sales representative for pricing and availability of other Xilinx LogiCORE IP modules and software. Information on additional LogiCORE IP modules is available on the Xilinx IP
Center .
Revision History
Date
10/23/06
2/15/07
8/8/05
3/24/08
9/19/08
4/24/09
4/9/10
Version
1.0
2.0
2.2
3.0
4.0
5.0
6.0
Revision
Initial Xilinx release.
Core updated to version 1.2; Xilinx tools 9.1i.
Core updated to version 1.3; Xilinx tools 9.2, IUS v5.8.
Core updated to version 1.4; Xilinx tools 10.1; Virtex-5 FXT FPGA support.
Core updated to version 1.5; Virtex-5 TXT FPGA support.
Core updated to version 1.6 and Xilinx tools updated to version 11.1.
Core updated to version 1.7 and Xilinx tools updated to version 12.1.
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Product Specification
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
Notice of Disclaimer
Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. All specifications are subject to change without notice. XILINX
EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANY
WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE. Except as stated herein, none of the Information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
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