Renesas Starter Kit for RL78/G1G CPU Board Schematics

Renesas Starter Kit for RL78/G1G CPU Board Schematics
5
4
3
2
1
REV
1.00
Renesas Starter Kit for RL78/G1G
CPU Board Schematics
REF
Release
DATE
15.10.2014
DRAWN BY
YOI
D
D
PAGE
Note:
DESCRIPTION
1
INDEX
2
RL78/G1G Microcontroller
3
PSU, Reset, Switches, LEDs
4
E1, USB to Serial
5
MCU Pin Function Select,
Application Headers, Header Function Select
Pmod, Pmod Header Function Select
6
IIC EEPROM
C
7
Microcontroller Pin Headers
C : Capacitor
D : Diode
R : Fixed Resistor
RV : Potentiometer
U : Integrated Circuit
X : Crystal
RES : Reset Switch
SW : Switch
LED : Light Emitting Diode
PWR : Power Jack
J : Connector, Jumper
C
* "DNF" marking means that component
does not fit by default.
Board Variation:
R0K5011EFC000BE : RSKRL78G1G MP Board
B
B
A
A
REEL Drawing No. D013202_04
Renesas System Design Co., Ltd.
Title
RSKRL78G1G [INDEX]
Size
Date:
5
4
3
2
Document Number
R20UT3017EG0100
Wednesday, October 15, 2014
Rev
1.00
Sheet
1
1
of
7
5
4
3
2
1
UC_VDD
U1
RESETn
ADC Channel / AVREF Cofiguration
RL78G1G-44pin
3
RESET
9
REGC
VDD
11
C27
470nF
Enables AD Channel
Enables AVREF
R41, R42
Remove
Fit
R40, R43, R91
Fit
Remove
C13, C14
Remove
Fit
C28
100nF
D
R42
0R(DNF)
AVREFP
R43
0R
ANI0
GROUND
VSS
TI00_TxD1_CMP0P
TO00_RxD1_PGA
43
42
P00/TI00/TxD1/CMP0P/ANI17/(TRJO0)
P01/TO00/RxD1/PGAI/ANI16/TRJIO0
TRDIOD1
TRDIOC1
TRDIOB1
TRDIOA1
TRDIOD0
TRDIOB0
P-INTP5_A-INTP5_TRDIOC0
P17_TI02
31
30
29
28
27
26
25
24
P10/TRDIOD1
P11/TRDIOC1
P12/TRDIOB1
P13/TRDIOA1
P14/TRDIOD0
P15/PCLBUZ1/TRDIOB0
P16/TI01/TO01/INTP5/TRDIOC0
P17/TI02/TO02/TRDIOA0/TRDCLK
41
40
39
38
37
36
35
34
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
21
16
P30/INTP3/SCK00/SCL00/TRJO0
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
ADPOT
ANI0_AVREFP
ANI1_AVREFM
ANI2
ANI3
ANI4
ANI5
ANI6
P27_ANI7
SCL00_P-SCK00_A-SCK00_INTP3
P-INTP4_A-INTP4_TO03
C
2
1
TOOL0
LED0
22
23
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/(TRJO0)
P51/INTP2/SO00/TxD0/TOOLTxD
P60_IO0
P61_IO1
P62_IO2_M1UD
LED1_IO3
12
13
14
15
P60
P61
P62/SSI00
P63
SW1_IO4
P71_IO5
LED2_IO6
LED3_IO7
20
19
18
17
P70/KR0
P71/KR1
P72/KR2
P73/KR3
CMP1P
P121
P122
SW3
SW2
44
8
7
5
4
P120/ANI19/CMP1P
P121/X1
P122/X2/EXCLK
P123
P124
RL78G1C_CTS_P146
RL78G1C_RTS_P147
ANI0_AVREFP
C14
100nF(DNF)
GROUND
ANI1_AVREFM
6
P137/INTP0
32
33
P146
P147/ANI18
D
+ C13
10uF(DNF)
R40
0R
ANI1
R41
0R(DNF)
AVREFM
Board_VDD
P40/TOOL0
P41/(TRJIO0)
SDA00_P-SI00_RxD0_A-SI00_RxD0_INTP1
P-SO00_TxD0_A-SO00_TxD0
P-INTP0_A-INTP0
10
C
ANI0
R91
0R
RV1
10K
C19
100nF
+ C18
10uF
C20
100pF
GROUND
B
B
P121
P122
R57
0R
R59 0R(DNF)
CON_X1
R56 0R(DNF)
CON_EXCLK
R58
0R
X1
20MHz
1
C16
6pF
2
C17
6pF
GROUND
A
A
Renesas System Design Co., Ltd.
Title
RSKRL78G1G [Micon]
Size
Date:
5
4
3
2
Document Number
R20UT3017EG0100
Wednesday, October 15, 2014
Rev
1.00
Sheet
1
2
of
7
5
4
3
2
1
Power Supply Unit
CON_5V
Unregulated_VDD
R38
0R
D
Board_5V
CON_3V3
R44
0R(DNF)
R55
0R
U4
LM1117MPX-3.3/NOPB
R33
3
1
2
3
OUT
GND
IN
PWR
KLDX-SMT2-0202-A
0R
R49
0R
Board_VDD
UC_VDD
J6(DNF)
1
2
J14
VSEL(DNF)
Board_3V3
Ground Test Point
GND1(DNF)
D
GND3(DNF)
GND2(DNF)
GND4(DNF)
R118 0R
+ C15
10uF
C26
100nF
R116 0R
1
2
GROUND
D2
GF1A
C25
100nF
+ C11
10uF
C12
100nF
Positive centre
5VDC
GROUND
GROUND
GROUND
GROUND
C
C
Switches, LEDs, RESET
Board_VDD
Board_VDD
D1
1N4148W(DNF)
Board_VDD
R5
4K7
RES
T_RESETn
B
SW1
R94
100K
C3
100nF(DNF)
SW1
SW2
R93
R92
RESETn
100K
GROUND
SW2
SW3
B
R117 10K
100K
SW3
GROUND
R64
0R
Board_VDD
LED0
R39
1K6
A
LED1
LED2
GREEN
1K6
R53
1K6
R54
1K6
R62
1K6
LED0
ORANGE
LED1
RED
POWER
GREEN
LED3
R52
A
LED2
RED
LED3
Renesas System Design Co., Ltd.
Title
RSKRL78G1G [PSU, Reset, Switches, LEDs]
GROUND
Size
Date:
5
4
3
2
Document Number
R20UT3017EG0100
Wednesday, October 15, 2014
Rev
1.00
Sheet
1
3
of
7
5
4
3
2
E1 Emulator Interface
RL78_5V
C5
100nF
To App Header
Board_VDD
Board_VDD
D
5
RESETn
A-SO00_TxD0
T_RESETn
TxD1
TOOL0
J7(DNF)
U5
SN74LVC2G17QDCKRQ1
RL78G1C_RTS
1
2
3
R122 0R
5
VCC
1
3
1A
2A
2
GND
6
4
1Y
2Y
RL78G1C_P60
RL78G1C_P50
D
4K7
TOOL0
R115 0R
UART0 / UART1
4K7
_TRESET
6
R.F.U
R.F.U
R.F.U
R.F.U
GND
GND
GND
R114
1K
10
13
GROUND
R12
2
12
14
NC
_RESET
_RESET
R119 0R(DNF)
R13
7
VDD
EMVDD
RL78_5V
R120 0R(DNF)
RS232TX
RS232RX
Board_VDD
E1
HTST-107-01-T-DV
8
9
1
GROUND
1
3
4
11
J8(DNF)
A-SI00_RxD0
RxD1
GROUND
Board_VDD
1
2
3
GROUND
U6
SN74LVC2G17QDCKRQ1
VCC 5
R121 0R
6
4
RL78G1C_CTS
2
4K7
C8
100nF
4K7
GND
RL78G1C_P61
RL78G1C_P51
R17
1
3
R18
1A
2A
1Y
2Y
Board_VDD
GROUND
USB to Serial Interface
GROUND
RL78_5V
RL78_5V
GROUND
C
C
R96
R98
1K
10K
R97
D3
1N4148W(DNF)
J5(DNF)
E1_I/F
1
2
3
4
5
100K
VDD
TOOL0
RESET_OUT
RESET_IN
GND
GROUND
RL78_5V
U2
2
B
RESET
31
30
P00
P01
18
17
P16
P17
29
28
27
26
25
P20
P21
P22
P23
P24
14
12
P30
P31
P40
RL78G1C_P50
RL78G1C_P51
15
16
P50
P51
RL78G1C_P60
RL78G1C_P61
9
10
11
P60
P61
P62
13
P70
32
5
4
P120
P121
P122
3
P137
R15
1
VDD
R14
R6
8
100R
C24
1uF_3216
+ C10
1uF
VSS
C22
1uF_3216
C9
100nF
GROUND
GROUND
B
7
GROUND
G1CUSB0
UVDD
6
5
4
3
2
1
21
C7
330nF
FRAME
GND
ID
D+
DVBUS
GROUND
UDP1
UDM1
20
19
UVBUS
UDP0
UDM0
22
24
23
REGC
6
KMBX-SMT-5S-S-30TR
(DX2R005HN2E700)
GROUND
GROUND
C6
470nF
0R
A
RL78_5V
RL78G1C-32pin
A
TBD(DNF)
GROUND
2
3
1
Renesas System Design Co., Ltd.
X2
CSTCE12M0G52 12MHz(10pF)
Title
RSKRL78G1G [E1, USB to Serial]
GROUND
Size
Date:
5
4
3
2
Document Number
R20UT3017EG0100
Wednesday, October 15, 2014
Rev
1.00
Sheet
1
4
of
7
5
4
3
2
Application Headers
1
Option pull-up resistor
CON_5V
Board_VDD
CON_3V3
JA1
D
AVREFP
ANI0
ANI2
IO0
IO2
IO4
IO6
INTP3
JA1_SDA00
5V
3V3
AVDD
AVREF
ADC0
ADC2
DAC0
IO_0
IO_2
IO_4
IO_6
IRQ3/IRQAEC/M2_HSIN0
IIC_SDA
1
3
5
7
9
11
13
15
17
19
21
23
25
R86
100K
A-INTP0
R84
100K
INTP1
R85
100K
INTP3
R90
100K
A-INTP4
R89
100K
A-INTP5
R37
JA2
0V
0V
AVSS
ADTRG
ADC1
ADC3
DAC1
IO_1
IO_3
IO_5
IO_7
IIC_EX
IIC_SCL
2
4
6
8
10
12
14
16
18
20
22
24
26
RESETn
AVREFM
INTP1
A-INTP4
M1UD
TRDIOB0
TRDIOA1
TRDIOB1
TO00
TI00
A-INTP5
ANI1
ANI3
IO1
IO3
IO5
IO7
JA1_SCL00
RESET
NMI
WDT_OVF
IRQ0/WKUP/M1_HSIN0
IRQ1/M1_HSIN1
M1_UD
M1_UP
M1_VP
M1_WP
TimerOut
TimerIn
IRQ2/M1_EncZ/M1_HSIN2
M1_TRCCLK
1
3
5
7
9
11
13
15
17
19
21
23
25
APP1(DNF)
EXTAL
Vss1
SCIaTX
SCIaRX
SCIaCK
CTSRTS
M1_UN
M1_VN
M1_WN
TimerOut
TimerIn
M1_POE
M1_TRDCLK
2
4
6
8
10
12
14
16
18
20
22
24
26
CON_EXCLK
A-SO00_TxD0
A-SI00_RxD0
A-SCK00
TRDIOD0
TRDIOC1
TRDIOD1
TO03
TI02
JA2_PIN24
Board_3V3
APP2(DNF)
GROUND
GROUND
D
100K
P-INTP0
R102 100K
P-INTP4
R26
P-INTP5
100K
Unregulated_VDD
JA5
ANI4
ANI6
C
ADC4
ADC6
CAN1TX
CAN2TX
IRQ4/M2_EncZ/M2_HSIN1
M2_UD
M2_Vin
M2_Toggle
M2_TRCCLK
M2_UP
M2_VP
M2_WP
1
3
5
7
9
11
13
15
17
19
21
23
JA6
2
4
6
8
10
12
14
16
18
20
22
24
ADC5
ADC7
CAN1RX
CAN2RX
IRQ5/M2_HSIN2
M2_Uin
M2_Win
M2_POE
M2_TRDCLK
M2_UN
M2_VN
M2_WN
ANI5
ANI7
RS232TX
RxD1
TRDIOC0
APP5(DNF)
DREQ
TEND
RS232TX
SCIbRX
SCIcTX
SCIcCK
M1_Toggle
M1_Vin
Reserved
Reserved
Reserved
Unregulated_VDD
1
3
5
7
9
11
13
15
17
19
21
23
DACK
STBYn
RS232RX
SCIbTX
SCIbCK
SCIcRX
M1_Uin
M1_Win
Reserved
CMP0P
CMP1P
Vss
2
4
6
8
10
12
14
16
18
20
22
24
APP6(DNF)
NOTE:
CMP0P and CMP1P are not standard
RSK App Header Specification.
Normally, JA6.Pin20 and JA6.Pin22 are reserved header.
Header Function Select
RS232RX
TxD1
R87
R88
JA2_PIN24
0R
0R(DNF)
A-INTP0
PGA
C
CMP0P
CMP1P
GROUND
MCU Pin Function Select
J13 P51(DNF)
P00(Pin43)
TI00_TxD1_CMP0P
P51(Pin23)
R47
R48
R51
0R(DNF)
0R
0R(DNF)
TI00
TxD1
CMP0P
R45
R46
R50
0R(DNF)
0R
0R(DNF)
TO00
RxD1
PGA
R27
R29
R28
0R(DNF)
0R
0R(DNF)
P-INTP5
A-INTP5
TRDIOC0
P-SO00_TxD0_A-SO00_TxD0
TO00_RxD1_PGA
P16(Pin25)
P-INTP5_A-INTP5_TRDIOC0
B
P17(Pin24)
P17_TI02
P27(Pin34)
P27_ANI7
P30(Pin21)
SCL00_P-SCK00_A-SCK00_INTP3
P60_IO0
P61(Pin13)
P61_IO1
P62(Pin14)
R31
R30
0R
0R(DNF)
P17
TI02
R34
R32
0R(DNF)
0R
P27
ANI7
J9
P60(Pin12)
P62_IO2_M1UD
P63(Pin15)
LED1_IO3
P30_1
P70(Pin20)
SCL00
1
2
3
SW1_IO4
P-SCK00
P71(Pin19)
P71_IO5
J10 P30_2(DNF)
A-SCK00
1
2
3
P31(Pin16)
R66
R69
R70
P-INTP4_A-INTP4_TO03
P72(Pin18)
INTP3
0R(DNF)
0R
0R(DNF)
LED2_IO6
P73(Pin17)
P-INTP4
A-INTP4
TO03
LED3_IO7
P137(Pin6)
P50(Pin22)
SDA00_P-SI00_RxD0_A-SI00_RxD0_INTP1
P-INTP0_A-INTP0
J11 P50_1
1
2
3
P146(Pin32)
RL78G1C_CTS_P146
P-SO00_TxD0
R123 0R
P01(Pin42)
A
A-SO00_TxD0
1
2
3
P147(Pin33)
RL78G1C_RTS_P147
R81
R83
0R
0R(DNF)
R82
R80
0R
0R(DNF)
R73
R76
R77
0R
0R(DNF)
0R(DNF)
R75
R74
0R
0R(DNF)
LED1
IO3
R60
R61
0R
0R(DNF)
SW1
IO4
R68
R67
0R
0R(DNF)
R63
R65
0R
0R(DNF)
LED2
IO6
R72
R71
0R
0R(DNF)
LED3
IO7
R78
R79
0R(DNF)
0R
P-INTP0
A-INTP0
0R(DNF)
0R
RL78G1C_CTS
P146
R21
R20
0R(DNF)
0R
RL78G1C_RTS
P147
P60
IO0
P61
IO1
B
P62
IO2
M1UD
P71
IO5
A
SDA00
INTP1
Renesas System Design Co., Ltd.
J12 P50_2(DNF)
1
2
3
R23
R22
Title
P-SI00_RxD0
RSKRL78G1G [MCU Pin Function Select, Application Headers]
A-SI00_RxD0
Size
Date:
5
4
3
2
Document Number
R20UT3017EG0100
Wednesday, October 15, 2014
Rev
1.00
Sheet
1
5
of
7
5
4
3
Board_VDD
Board_5V
EEPROM only supports single device on bus. To allow external
IIC devices two option links R2 and R3 have to be removed.
PMOD1: Angle type connector (for LCD)
4K7
0R
0R
PMOD2: Vertical type connector (Spare)
D
Board_3V3
C23
100nF
U3
R1EX24016ASAS0G
(R1EX24016ASAS0I)
(R1EX24016ASAS0A)
1 A0
VCC 8
2 A1
3 A2
5 SDA
6 SCL
7 WP
GND 4
R107 100K
VCC = Board_VDD
or
Board_5V
C21
100nF
Board_3V3
Board_3V3
R108 22K
R2
R3
0R(DNF)
R99
4K7
R106 0R(DNF)
R95
100R
100R
R8
NEVER FIT R7 and R8 simultaneously.
0R
Warning:
R7
D
R1
R4
1
Pmod Interface
IIC Serial EEPROM(16Kbits)
SDA00
SCL00
2
GROUND
C4
100nF
PMOD1
GROUND
P60
P61
PMOD1_PIN8
P-INTP4
12
11
10
9
8
7
R105 200R
R104 200R
R103 200R
R101 200R
6
5
4
3
2
1
R112 200R
R111 200R
R110 200R
P-SCK00
P-SI00_RxD0
P-SO00_TxD0
P62
R109 200R
PMOD_CON
C
C
GROUND
GROUND
GROUND
R100 0R
JA1_SDA00
JA1_SCL00
Board_3V3
C1
100nF
C2
100nF
Board_3V3
Board_3V3
R19
GROUND
22K
PMOD2
12
11
10
9
8
7
B
R9
R10
R11
P147
P146
PMOD2_PIN8
200R
200R
200R
T1
PMOD2_PIN7(DNF)
6
5
4
3
2
1
B
R16
200R
P17
PMOD_CON
R113 200R
GROUND
GROUND
Pmod Function Select
PMOD1_PIN8
R24
R25
0R
0R(DNF)
P71
P-INTP5
PMOD2_PIN8
R35
R36
0R(DNF)
0R(DNF)
P27
P-INTP0
A
A
Renesas System Design Co., Ltd.
Title
RSKRL78G1G [Pmod, Pmod Header Function Select, IIC EEPROM]
Size
Date:
5
4
3
2
Document Number
R20UT3017EG0100
Wednesday, October 15, 2014
Rev
1.00
Sheet
1
6
of
7
5
4
3
2
1
Microcontroller Pin Headers
UC_VDD
D
D
J1
LED0
RESETn
SW3
CON_EXCLK
J4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
TOOL0
SW2
P-INTP0_A-INTP0
CON_X1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
PIN1_11(DNF)
P27_ANI7
ANI5
ANI3
ANI1_AVREFM
TO00_RxD1_PGA
CMP1P
GROUND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
ANI6
ANI4
ANI2
ANI0_AVREFP
TI00_TxD1_CMP0P
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
PIN34_44(DNF)
C
C
J2
P60_IO0
P62_IO2_M1UD
P-INTP4_A-INTP4_TO03
LED2_IO6
SW1_IO4
SDA00_P-SI00_RxD0_A-SI00_RxD0_INTP1
B
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
J3
P61_IO1
LED1_IO3
LED3_IO7
P71_IO5
SCL00_P-SCK00_A-SCK00_INTP3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
P-SO00_TxD0_A-SO00_TxD0
P-INTP5_A-INTP5_TRDIOC0
TRDIOD0
TRDIOB1
TRDIOD1
RL78G1C_RTS_P147
PIN12_22(DNF)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
P17_TI02
TRDIOB0
TRDIOA1
TRDIOC1
RL78G1C_CTS_P146
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
B
PIN23_33(DNF)
A
A
Renesas System Design Co., Ltd.
Title
RSKRL78G1G [MCU Pin Headers]
Size
Date:
5
4
3
2
Document Number
R20UT3017EG0100
Wednesday, October 15, 2014
Rev
1.00
Sheet
1
7
of
7
5
4
3
2
1
Revision History
REV
1.00
DATE
15.10.2014
PAGE
-
DESCRIPTION
1st release edition.
D
D
C
C
B
B
A
A
Renesas System Design Co., Ltd.
Title
RSKRL78G1G [Revision History]
Size
Date:
5
4
3
2
Document Number
R20UT3017EG0100
Wednesday, October 15, 2014
Rev
1.00
Sheet
1
x
of
x
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