datasheet for MFM8516S by Apta Group

datasheet for MFM8516S by Apta Group
512K x 8 FLASH
MFM8516 - 55/70/90/12
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Description
The MFM8516 is a 4M Bit CMOS 5V only Flash
monolithic device organised : 512K x 8. The device
offers fast access times of 55/70/90 and 120ns and
5V program/erase.
The device has a 64 KByte sector size. The Program
and Erase procedure is simplified via automatic
program and erase algorithms.
The MFM8516 has a 10K cycle write erase cycle
endurance (100K cycle E-Part) and a 10 year data
retention time.
Issue 5.0 : April 2001
524,288 bit FLASH EEPROM
Features
• 4 Megabit FLASH memory.
• Fast Access Times of 55/70/90/120 ns.
• Operating Power 248 mW (max),
Low Power Standby (CMOS) 633µW (max).
• Automatic Write/Erase by Embedded Algorithm - end of
Write/Erase indicated by DATA Polling and Toggle Bit.
• Flexible Sector Erase Architecture - 64K byte sector
size, with hardware protection of any number of sectors.
• Byte Program of 16µs (Typ), Sector Program of 2s (Typ)
• Erase/Write Cycle Endurance, Standard 10,000 (min)
Extended 100,000 (min)
• 10 year data retention.
• May be screened in accordance with MIL-STD-883.
Block Diagram
Pin Definitions
DQ0-DQ7
Vcc
Vss
Input/Output
Buffers
Erase Voltage
Generator
WE
State
Control
STB
Vcc Detector
Timer
A
d
d
r
L
a
t
c
h
A0-A18
Data
Latch
Chip Enable
Output Enable
Logic
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
S,V
PACKAGE
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V CC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
A12
A15
A16
A18
Vcc
WE
A17
PGM Voltage
Generator
CE
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4
3
2
1
32
31
30
Command
Register
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
A7
A6
A5
A4
A3
A2
A1
A0
D0
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CS
D7
20
19
18
17
16
15
14
D6
D5
D4
D3
GND
D2
D1
Package Details
Pin Count
32
32
Description
Pin Functions
Package Type
Dual In-line
JLCC (J Leaded Chip Carrier)
S
J
A0-A18
D0-D7
CS
WE
OE
Vcc
GND
Address Inputs
Data Inputs/Outputs
Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
MFM8516 - 55/70/90/12
Issue 5.0 : April 2001
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
unit
Voltage on any pin w.r.t. Gnd
-2.0 to +7
V
Supply Voltage (2)
-2.0 to +7
V
-2.0 to +14
V
-65 to +150
°C
Voltage on A9 w.r.t. Gnd
(3)
Storage Temperature
Notes : (1)
(2)
(3)
Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at those or any other conditions above those indicated in the operational sections of this
specification is not implied.
Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V
During transitions voltage may overshoot by +/-1V for up to 10ns
Minimum DC input voltage on A9 is -0.5V during voltage transitions, A9 may overshoot Vss to -1V for periods of up to
10ns, maximum DC input voltage in A9 is 13.5V which may overshoot to 14.0V for periods up to 10ns
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage (TTL)
Input Low Voltage (TTL)
Input High Voltage (CMOS)
Input Low Voltage (CMOS)
Operating Temperature
VCC
VIH
VIL
VIH
VIL
TA
TAI
TAM
min
typ
max
4.5
2.0
-0.5
0.7VCC
-0.5
0
-40
-55
5.0
-
5.5
VCC+0.5
0.8
VCC+0.3
0.8
70
85
125
unit
V
V
V
V
V
°C
O
C (-I suffix)
O
C (-M\MB suffix)
DC Electrical Characteristic (TA=-55°C to +125°C,VCC=5V ± 10%)
Parameter
I/P Leakage Current
Symbol Test Condition
Address, OE
min
typ max
Unit
ILI1
VCC = VCC max, VIN = 0V or VCC
-
-
±1
µA
ILI2
VCC = VCC max, A9 = 12.5V
-
-
50
µA
ILI3
VCC = VCC max, VIN = 0V or VCC
-
-
±1
µA
Output Leakage Current
ILO
VCC = VCC max, VOUT = 0V or VCC
-
-
±1
µA
VCC Operating Current
ICCO
CS = VIL, OS = VIH, IOUT = 0mA, f = 6MHz
-
-
45
mA
VCC Program/Erase Current
ICCP
Programming in Progress
-
-
65
mA
ISB
VCC = VCC max, CS = VIH OE = VIH
-
-
1.5
mA
CMOS
ISB1
VCC = VCC max, CS = VCC+0.5, OE = VIL
-
-
115
µA
Autoselect / Sector Protect Voltage
VID
VCC = 5.0V
11.5
-
12.5
V
Output Low Voltage
VOL
IOL = 5.8mA. VCC = VCC min.
-
-
0.45
V
Output High Voltage
VOH1
IOH = -2.5mA. VCC = VCC min.
2.4
-
-
V
Low VCC Lock-Out Voltage
VLKO
3.2
-
4.2
V
A9 Input Leakage Current
Other Pins
Standby Supply Current
TTL
2
MFM8516 - 55/70/90/12
Issue 5.0 : April 2001
Capacitance (TA=25°C,f=1MHz)
Parameter
Symbol
Test Condition
Input Capacitance
CIN1
VIN = 0V
Control Pin Capacitance
CIN2
Output Capacitance
COUT
typ
max
Unit
-
10
pF
VPP = 0V
-
12
pF
VOUT = 0V
-
12
pF
Note: These parameters are calculated, not measured.
AC Test Conditions
* Input pulse levels : 0.0V to 3.0V
* Input rise and fall times : 5 ns
* Input and output timing reference levels : 1.5V
* VCC = 5V + 10%
I/O Pin
166 Ω
1.76V
30pF
3
MFM8516 - 55/70/90/12
Issue 5.0 : April 2001
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
Read Cycle Time
tRC
Address to output delay
tACC
Chip enable to output
tCE
Output enable to output
tOE
Output enable to output High Z
tDF
Output hold time from address
tOH
CS or OE whichever occurs first
Parameter
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55
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12345678901234567890123456789012123
min
typ
max
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12345678901234567890123456789012123
55
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
55
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
55
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
30
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
12345678901234567890123456789012123
18
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12345678901234567890123456789012123
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0
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Symbol
min
70
70
typ
-
max
-
Unit
ns
-
-
70
ns
-
-
70
ns
-
-
30
ns
-
-
20
ns
0
-
-
ns
90
typ
-
max
-
min
120
120
typ
-
max
-
Unit
ns
Read Cycle Time
tRC
min
90
Address to output delay
tACC
-
-
90
-
-
120
ns
Chip enable to output
tCE
-
-
90
-
-
120
ns
Output enable to output
tOE
-
-
35
-
-
50
ns
Output enable to output High Z
tDF
-
-
20
-
-
30
ns
Output hold time from address
tOH
0
-
-
0
-
-
ns
CS or OE whichever occurs first
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4
MFM8516 - 55/70/90/12
Issue 5.0 : April 2001
Write/Erase/Program
Parameter
Symbol
Write Cycle time (2)
tWC
Address Setup time
tAS
Address Hold time
tAH
Data Setup Time
tDS
Data hold Time
tDH
Output Enable Setup Time
tOES
Read Recover before Write
tGHWL
CS setup time
tCE
CS hold time
tCH
WE Pulse Width
tWP
WE Pulse Width High
tWPH
Byte Programming operation
tWHWH1
Sector Erase operation (1)
tWHWH2
Chip Erase operation
(1)
tWHWH3
Vcc setup time (2)
tVCS
Parameter
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55
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12345678901234567890123456789012
12345678901234567890123456789012
min
typ
max
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12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
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55
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
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0
12345678901234567890123456789012
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12345678901234567890123456789012
40
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
25
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
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0
12345678901234567890123456789012
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12345678901234567890123456789012
0
12345678901234567890123456789012
12345678901234567890123456789012
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12345678901234567890123456789012
0
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
0
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
0
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
40
12345678901234567890123456789012
12345678901234567890123456789012
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20
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12345678901234567890123456789012
16
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2
30
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14
120
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12345678901234567890123456789012
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12345678901234567890123456789012
50
12345678901234567890123456789012
12345678901234567890123456789012
Symbol
min
70
typ
max
unit
70
-
-
ns
0
-
-
ns
45
-
-
ns
30
-
-
ns
0
-
-
ns
0
-
-
ns
0
-
-
ns
0
-
-
ns
0
-
-
ns
35
-
-
ns
20
-
-
ns
-
16
-
µs
-
2
30
sec
-
14
120
sec
50
-
-
µs
min
90
typ
max
min
120
typ
max
unit
Write Cycle time (2)
tWC
90
-
-
120
-
-
ns
Address Setup time
tAS
0
-
-
0
-
-
ns
Address Hold time
tAH
45
-
-
50
-
-
ns
Data Setup Time
tDS
45
-
-
50
-
-
ns
Data hold Time
tDH
0
-
-
0
-
-
ns
Output Enable Setup Time
tOES
0
-
-
0
-
-
ns
Read Recover before Write
tGHWL
0
-
-
0
-
-
ns
CS setup time
tCE
0
-
-
0
-
-
ns
CS hold time
tCH
0
-
-
0
-
-
ns
WE Pulse Width
tWP
45
-
-
50
-
-
ns
WE Pulse Width High
tWPH
20
-
-
20
-
-
ns
Byte Programming operation
tWHWH1
-
16
-
-
16
-
µs
Sector Erase operation (1)
tWHWH2
-
2
30
-
2
30
sec
tWHWH3
-
14
120
-
14
120
sec
tVCS
50
-
-
50
-
-
µs
Chip Erase operation
(1)
Vcc setup time (2)
Notes: (1) This does not include the preprogramming time.
(2) Not 100% tested.
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5
MFM8516 - 55/70/90/12
Issue 5.0 : April 2001
Write/Erase/Program Alternate CS controlled Writes
Parameter
Symbol
Write Cycle time (2)
tWC
Address Setup time
tAS
Address Hold time
tAH
Data Setup Time
tDS
Data hold Time
tDH
Output Enable Setup Time
tOES
Read Recover before Write
tGHEL
WE setup time
tWS
WE hold time
tWH
CS Pulse Width
tCP
CS Pulse Width High
tCPH
Programming operation
tWHWH1
Sector Erase operation (1)
tWHWH2
Chip Erase operation (1)
tWHWH3
Vcc setup time
(2)
tVCS
Parameter
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12345678901234567890123456789012
55
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
min
typ
max
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12345678901234567890123456789012
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12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
55
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
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0
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
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12345678901234567890123456789012
40
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
25
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
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0
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
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12345678901234567890123456789012
0
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
0
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
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12345678901234567890123456789012
0
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
0
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
30
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
20
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
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16
12345678901234567890123456789012
12345678901234567890123456789012
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2
30
12345678901234567890123456789012
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14
120
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12345678901234567890123456789012
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12345678901234567890123456789012
50
12345678901234567890123456789012
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Symbol
min
70
typ
max
unit
70
-
-
ns
0
-
-
ns
45
-
-
ns
30
-
-
ns
0
-
-
ns
0
-
-
ns
0
-
-
ns
0
-
-
ns
0
-
-
ns
35
-
-
ns
20
-
-
ns
-
16
-
us
-
2
30
sec
-
14
120
sec
-
50
-
us
min
90
typ
max
min
120
typ
max
unit
Write Cycle time (2)
tWC
90
-
-
120
-
-
ns
Address Setup time
tAS
0
-
-
0
-
-
ns
Address Hold time
tAH
45
-
-
50
-
-
ns
Data Setup Time
tDS
45
-
-
50
-
-
ns
Data hold Time
tDH
0
-
-
0
-
-
ns
Output Enable Setup Time
tOES
0
-
-
0
-
-
ns
Read Recover before Write
tGHEL
0
-
-
0
-
-
ns
WE setup time
tWS
0
-
-
0
-
-
ns
WE hold time
tWH
0
-
-
0
-
-
ns
CS Pulse Width
tCP
45
-
-
50
-
-
ns
CS Pulse Width High
tCPH
20
-
-
20
-
-
ns
tWHWH1
-
16
-
-
16
-
us
tWHWH2
-
2
30
-
2
30
sec
tWHWH3
-
14
120
-
14
120
sec
tVCS
-
50
-
-
50
-
us
Programming operation
Sector Erase operation
(1)
Chip Erase operation (1)
Vcc setup time
(2)
Note: (1) Does not include pre-programming time.
(2) Not 100% tested.
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6
MFM8516 - 55/70/90/12
Issue 5.0 : April 2001
AC Waveforms for Read Operation
t RC
Address
Address Stable
t ACC
t DF
CS
t OE
OE
WE
t OH
t CE
High Z
High Z
Outputs
Output Valid
AC Waveforms Program
Data Polling
Address
5555H
PA
t AS
t WC
CS
PA
t RC
t AH
t GHWL
OE
t WP t WHP
WE
DATA
t CS
t WHWH1
t OE
t DH
PD
A0H
D7
t DF
D OUT
t DS
VCC
t CE
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
7
t OH
MFM8516 - 55/70/90/12
Issue 5.0 : April 2001
A.C Waveforms - Alternate CS controlled Program operation timings
Data Polling
Address
5555H
PA
tAS
tWC
PA
tAH
t RC
WE
tGHEL
OE
tCP tCHP
CS
tWS
tOE
tDH
A0H
DATA
tWHWH1
PD
D7
t DF
DOUT
tDS
VCC
tCE
tOH
NOTES:
1. PA is address of memory location to be programmed.
2. PD is data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
AC Waveforms for Data Polling During Embedded Algorithm Operations
tCH
CS
t DF
tOE
OE
t OEH
WE
tCE
t OH
*
D7
D7 =
Valid Data
D7
HIGH Z
t WHWH1 OR 2
D0-D6
= Invalid
D0-D6
D0-D6=
Vaild Data
tOE
8
HIGH Z
MFM8516 - 55/70/90/12
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AC Waveforms for Toggle Bit During Embedded Algorithm Operations
CS
WE
t OEH
OE
*
DATA
(D0-D7)
D6 = Toggle
D6 = Toggle
D6 =
Stop Toggling
D0-D7
Valid
t OE
* D6 stops toggling ( the device has completed the embedded operations)
AC Waveforms Chip / Sector Erase
t AS
5555H
Address
t AH
2AAAH
5555H
5555H
2AAAH
SA
CS
t GHWL
OE
t WP
WE
t WPH
t CS
t DH
Data
AAH
55H
80H
AAH
55H
t DS
Vcc
t VCS
NOTES:
1. SA is the address for sector erase. Addresses = don't care for Chip Erase.
9
10H/30H
MFM8516 - 55/70/90/12
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EMBEDDED PROGRAMMING ALGORITHM
Start
Write Program Command
Sequence
(see below)
Data Poll Device
Increment Address
Last
Address
?
No
Yes
Programming
Completed
Program Command Sequence (Address /Command)
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program data
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EMBEDDED ERASE ALGORITHM
START
Write Erase Command Sequence
See below
Data Poll or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
Individual Sector/Mulitiple Sector
(Address/Command):
Erase Command Sequence
(Address/Command):
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
5555H/10H
2AAAH/55H
Sector Address/30H
Sector Address/30H
Sector Address/30H
11
}
Additional sector
erase commands
are optional
MFM8516 - 55/70/90/12
Issue 5.0 : April 2001
DATA POLLING ALGORITHM
START
Read D7~D0
Addr=VA
Yes
D7=Data?
D5=1?
No
Yes
Read D7~D0
Addr = VA
Yes
D7=Data?
No
FAIL
PASS
Note :
1. VA = Valid Address for programming. During a sector erase operartion, a valid adddress
is an address within any sector selected for erasure. During chip erase, a valid address is
any non-protected sector address.
2. D7 should be rechecked even if D5 = ’1’ beceause D7 may change simultaneously with D5.
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MFM8516 - 55/70/90/12
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TOGGLE BIT ALGORITHM
Start
VA = Byte Address for programming
Read Byte
(D0 - D7)
Addr=VA
= Any of the sector addresses
within the sector being erased
during sector erase operation.
= XXXXH during chip erase
No
D6 = Toggle?
Yes
No
D5=1?
Yes
Read Byte
(D0 - D7)
Addr=VA
No
D6 = Toggle?
Pass
Yes
Fail
Note : D6 is rechecked even if D5 = "1" beceause D6 may stop toggling at the same time
as D5 changing to "1"
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DEVICE OPERATION
Read Mode
The MFM8516 has two control functions which must be satisfied in order to obtain data at the outputs
CS is the power control and should be used for device selection.
OE is the output control and should be used to gate data to the output pins if the device is selected.
Standby Mode
Two standby modes are available : CMOS standby :
TTL standby :
CS held at Vcc +/- 0.5V
CS held at VIH
In the standby mode the outputs are in a high impedance state independent of the OE input. If the device is
deselected during erasure or programming the device will draw active current until the operation is completed.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
This mode is intended for use by programming equipment. This mode is functional over the full military
temperature range. The autoselect codes as follows :
Type
Sector
Protection
A18
A17
A16
Sector Address
A6
A1
A0
Code
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
VIL
VIH
VIL
01H*
0
0
0
0
0
0
0
1
* Outputs 01H at protected sector address
To activate this mode the programming equipment must force VID on address A9 . All addresses are don't
care apart from A0, A1 & A6.
Write
Device erasure and programming are accomplished via the command register. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The register is a latch used to store the commands along with the address and data information required to
execute the command. The command register is written by bringing WE to VIL while CS is at VIL and
OE is at VIH. Addresses are latched on the falling edge of WE or CS, whichever happens later; while data is
latched on the rising edge of WE or CS, whichever happens first.
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MFM8516 - 55/70/90/12
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COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
The following table defines these register command sequences.
Command
Sequence
Read/Reset
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Addr
Data
Second Bus
Write Cycle
Third Bus
Write Cycle
Addr
Data
Addr
Fourth Bus
Read/Write
Cycle
Data
Addr
Data
RA
RD
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr
Data
Addr
Data
Read/Reset
1
XXXH
F0H
Read/Reset
4
5555H
AAH
2AAAH
55H
5555H
F0H
Autoselect
3
5555H
AAH
2AAAH
55H
5555H
90H
Byte Program
4
5555H
AAH
2AAAH
55H
5555H
A0H
PA
Data
Chip Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Sector Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA
30H
Sector Erase Suspend
Erase can be suspended during sector erase with Addr (don’t care) Data (B0H)
Sector Erase Resume
Erase can be resumed after suspend with Addr (Don’t Care), Data (30H)
NOTES:
1. Address bit A15,A16,A17, A18=X=Don't care. Write Sequences may be initiated with A15 in either state.
2. Address bit A15,A16,A17, A18=X=Don't care for all address commands except for Program Address (PA) and
Sector Address (SA).
3. RA=Address of the memory location to be read.
PA=Address of memory location to be programmed. Addresses are latched on the falling edge of the WE
pulse.
SA=Address of the sector to be erased. The combination of A18, A17 and A16 will uniquely select any
sector.
4. RD=Data read from location RA during read operation.
PD=Data to be programmed at location PA. Data is latched on the rising edge of WE
5. Read and byte program functions to non-erasing sectors are allowed in the Erase Suspend mode.
Read / Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for
reads until the command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for specific timing parameters.
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Sector Protection
The MFM8516 features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 8). The sector protect feature is enabled using programming equipment at the users site. The device is shipped with all sectors unprotected.
It is also possible to determine if a sector is protected in the system by writing the Autoselect command.
Performing a read operation at the address location XX02H, where the higher order addresses (A16, A17,
A18) are the sector addresses will produce a logical "1" at D0 for a protected sector.
Sector Address Table
A18
A17
A16
Address Range
SA0
0
0
0
00000h-0FFFFh
SA1
0
0
1
10000h-1FFFFh
SA2
0
1
0
20000h-2FFFFh
SA3
0
1
1
30000h-3FFFFh
SA4
1
0
0
40000h-4FFFFh
SA5
1
0
1
50000h-5FFFFh
SA6
1
1
0
60000h-6FFFFh
SA7
1
1
1
70000h-7FFFFh
Sector Unprotect
The MFM8516 also features a sector unprotect mode so that a potected sector may be unprotected to
incorporate any changes in the code. The sector unprotect is enabled using programming equipment at the
user's site. It is also possible to determine if a sector is unprotected in the system by writing the autoselect
command and A6 is set at VIH. Performing a read operation at address location XXX2H, where the higher
order addresses (A18, A17, and A16) define a particular sector address, will produce 00H at data outputs (D0
- D7) for an unprotected sector.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally a desired system design practice.
The device contains an autoselect operation to supplement traditional PROM programming methodology. The
operation is initiated by writing the autoselect command sequence into the command register.
Following command write, scanning the sector addresses on A16, A17, & A18 while A6, A1 & A0 = 0, 1, 0 will
produce a logical "1" at device output D0 for a protected sector.
To terminate the operation, it is necessary to write the read/reset command sequence into the register.
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Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycle. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of WE or CS, whichever happens later, while the data are latched on the rising edge
of WE or CS whichever happens first. The rising edge of WE or CS begins programming. Upon executing the
Embedded Program Algorithm Command sequence the system is not required to provide further controls or
timings. The device will automatically provide adequate internally generated program pulses and verify the
programmed cell margin. The automatic programming operation is completed when the data on D7 is equivalent to data written to this bit (see Write Operations Status) at which time the device returns to the read mode
and addresses are no longer latched. Data Polling must be performed at the memory location which is being
programmed.
Programming is allowed in any address sequence and across sector boundaries.
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock"write cycles. These are followed by writing
the "Set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The
sector address (any address location within the desired sector) is latched on the falling edge of WE, while the
command (data) is latched on the rising edge of WE. A time-out of 80µs from the rising edge of the last sector
erase command will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be
concurrently erased. The time between writes must be less than 80µs, otherwise the command will not be
accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition.
The interrupts can be-enabled after the last Sector Erase command is written. A time-out of 80µs from the
rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of
the WE occurs within the 80us time-out window the timer is reset. Any command other than Sector Erase or
Erase Suspend during this period and afterwards will reset the device to read mode, ignoring the previous
command string. Resetting the device after it has begun execution will result in the data of the operated
sectors being undefined. In that case, restart the erase on those sectors and allow them to complete. Loading
the sector erase buffer may be done in any sequence and with any number of sectors.
Sector erase doesn't require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors
the remaining unselected sectors are not affected. The system is not required to provide any controls or
timings during these operations.
The automatic sector erase begins after the 100µs time-out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on D7 is "1" ( see Written Operation Status
Section) at which time the device returns to read mode. Data polling must be preformed at an address within
any of the sectors being erased.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device automatically will program and verify the entire memory for an
all zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings
during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on D7 is "1" (See Written Operation Section) at which time the device returns to read the mode.
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Erase Suspend
Erase suspend allows the user to interrupt a Sector Erase operation and then perform data reads or programs
to a sector not being erased. This command is only applicable during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during Chip
Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during the Sector
Erase time-out results in immediate termination of the time-out period and suspension of the erase operation.
Any other command written during the Erase Suspend mode will be ignored except the Erase Resume
command. Writing the Erase Resume command resumes the erase operation. The addresses are "don'tcares" when writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a
maximum of 15µs to suspend the erase operation. When the device has entered the erase-suspend mode, D7
bit will be a logic '1', and D6 will stop toggling. The user must use the address of the erasing sector for reading
D6 and D7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend
command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read
from sectors that have not been erase-suspended. Successively reading from the erase-suspend sector while
the device is in the erase-suspend-read mode will cause D2 to toggle.
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Byte Program. This program mode is known as the erase-suspend-program mode.
Again, programming in this mode is the same as programming in the regular Byte Program mode except that
the data must be programmed to sectors that are not erase-suspended. Successively reading from the erasesuspended sector while the device is in the erase-suspend-program mode will cause D2 to toggle. The end of
the erase-suspend-program operation is detected by Data Polling of D7, or by the Toggle bit (D6) which is the
same as the regular Byte Program operation. Note that D7 must be read from the byte program address while
D6 can be read from any address.
To resume the operation of Sector Erase, the Resume command should be written. Any further writes of the
Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip
has resumed erasing.
WRITE OPERATIONS STATUS
In Progress
Status
D7
D6
D5
D3
Byte Programming in Embedded Algorithm
D7
Toggle
0
0
Embedded Erase Algorithm
0
Toggle
0
1
Erase
Erase Suspended Sector
1
No Tog
0
1
Suspended Mode
Non-Erase Suspended Sector
Data
Data
Data
Data
D7
Toggle
1
0
0
Toggle
1
1
D7
Toggle
1
1
Exceeded
Byte-Programming in Embedded Algorithm
Time Limits
Embedded Erase Algorithm
Program in Erase Suspended Mode
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Operating Modes
The following modes are used to control the device.
OPERATION
CS
OE
WE
A0
A1
A6
A9
I /O
Read(1)
L
L
H
A0
A1
A6
A9
DOUT
Standby
H
X
X
X
X
X
X
High Z
Output Disable
L
H
H
X
X
X
X
High Z
Write
L
H
L
A0
A1
A6
A9
Din
Verify Sector Protect
L
L
H
L
H
L
VID
Code
Auto-Select Device Unprotected Code
L
L
H
H
H
L
VID
Code
1) L=VIL, H=VIH, X=Don't Care
NOTE:
1) WE can be VIL if OE is VIL , OE at VIH initiates write operation.
D7 Data Polling
The MFM8516 features Data Polling as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During the Embedded Programming Algorithm, an attempt to read the
device will produce complement data of the data last written to D7. Upon completion of the Embedded Programming Algorithm an attempt to read the device will produce the true data last written to D7. During the
Embedded Erase Algorithm, During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the D7 output.
For chip erase, the Data Polling is valid after the rising edge of the six WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data
Polling must be performed at sector address within any of the sectors being erased or not a protected sector.
Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed,
the device data pins (D7) may change asynchronously while OE is asserted low. This means that the device is
driving status information on D7 at one instant of time and then that byte's valid data at the next instant of time.
Depending on when the system samples the D7 output, it may read the status or valid data. Even if the device
has completed the Embedded Algorithm operation and D7 has a valid data, the data outputs on D0-D6 may
still be invalid. The valid data on D0-D7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out.
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MFM8516 - 55/70/90/12
D6
Issue 5.0 : April 2001
Toggle Bit
The MFM8516 also features the "toggle bit" as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the device
will result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is
completed, D6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle bit is valid after the rising edge of the forth WE pulse in the four write pulse sequence. For
chip erase, the Toggle bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.
For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erare WE pulse. The Toggle Bit
is active during the sector time-out.
D5 Exceeding Time Limits
D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will
produce "1", indicating the program or erase cycle was not successfully completed . Data Polling is the only
operating function of the device under this condition. The CS circuit will partially power down the device under
these conditions (to approximately 2mA). The OE and WE pins will control the output disable functions .
If this failure occurs during sector erase operations, it specifies that a particular sector is bad and may not be
re-used. The device must be reset to use other sectors. Write the reset command sequence and execute
program or erase command sequence. This allows the system to continue to use the other active sectors in
the device.
If this failure occurs during chip erase operation , it specifies that the device chip or combination of sectors
are bad.
If this failure occurs during the byte programming operation, it specifies that the entire sectors containing that
byte is bad and may not be re-used.
The D5 failure condition may also appear if the user tries to program a non blank location without erasing. In
this case the device locks out and never completes the embedded algorithm operation. Hence the system
never reads a valid data on D7 and D6 never stops toggling. Once the device has exceeded timing limits, the
D5 bit will indicate '1'
D3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may
be used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase
cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional
sector erase commands. To insure the command has been accepted, the system software should check the
status of D3 prior to and following each subsequent sector erase command. If D3 were high on the second
status check, the command may not have been accepted.
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DATA PROTECTION
The MFM8516 is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its controls register architecture , alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up
and power down transitions or system noise.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during VCC power up and power down, a write cycle is locked out for
VCC<VLKO. When VCC<VLKO, the command register is disabled and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes will be ignored until the VCC>VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE, CS, WE will not initiate a write cycle
Logical Inhibit
Writing is inhibited by holding any one of OE=VIL, CS=VIH or WE=VIH. To initiate a write cycle CS and WE
must be logical zero while OE is a logical one.
Power Up Write Inhibit
Power-up of the device with WE = CS = VIL and OE = VIH will not accept commands on the rising edge of
WE. The internal state machine is automatically reset to the read mode on power-up.
Sector Protect
Sectors of the MFM8516 may be hardware protected at the users factory. The protection circuitry will disable
both program and erase functions for the protected sector(s). Requests to program or erase a protected sector
will be ignored by the device.
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time
Notes:
Min
Limits
Typ
1
(Note 1)
8
Max
Unit
15
sec
120
sec
7
1000
(Note 1)
3.6
25
(Note 1) (Note 2)
µs
Excludes 00H programming
prior to erasure.
Excludes 00H programming
prior to erasure.
Excludes System-level overhead.
sec
Excludes system-level overhead.
(1) 25OC, 5V VCC, 10,000 cycles.
(2) The Embedded Algorithms allow for 2.5ms byte program time.
21
Comments
MFM8516 - 55/70/90/12
Issue 5.0 : April 2001
PACKAGE DETAILS
32 pin 0.6" Dual-In-Line (DIL) - 'S' Package
41.05 (1.615)
15.56 (0.610)
15.05 (0.590)
40.26 (1.585)
1.52 (0.060)
1.02 (0.040)
4.30 (0.170)
3.30 (0.130)
4.00 (0.157)
3.00 (0.117)
0.51 (0.020)
2.67 (0.105)
2.41 (0.095)
0.41 (0.016)
32 Pin J-Leaded Chip Carrier (JLCC) - 'J' Package
9.91 (0.390)
10.41 (0.410)
13.95 (0.510)
13.45 (0.530)
No. 1 Index
13.84 (0.545)
11.30 (0.445)
0.71 (0.028) typ
1.27 (0.050) typ
1.90 (0.075)
1.65 (0.065)
14.22 (0.560)
11.70 (0.460)
0.43 (0.017)
typ
4.32 (0.170)
7.87 (0.310)
3.80 (0.150)
7.37 (0.290)
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MFM8516 - 55/70/90/12
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SCREENING
Military Screening Procedure
Component Screening Flow for high reliability product using methods from 5004.
MB COMPONENT SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Mechanical
Temperature cycle
Constant acceleration
Pre-Burn-in electrical
Burn-in
Endurance
1010 Condition C (10 Cycles,-65°C to +150°C)
2001 Condition E (Y, only) (30,000g)
Per applicable device specifications at TA=+25°C
Method 1015,Condition D,TA=+125°C,160hrs min
100%
100%
100%
100%
As per internal specification
Write Cycle endurance and
Data Retention performance
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective allowable (PDA)
Calculated at post-burn-in at TA=+25°C
5%
Hermeticity
1014
Fine
Gross
Condition A
Condition C
100%
100%
External Visual
2009 Per vendor or customer specification
100%
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ORDERING INFORMATION
MFM8516SMB - 55E
Write Cycle Endurance
Speed
E = 100,000 cycles (min)
Blank = 10,000 cycles (min)
55
70
90
12
=
=
=
=
55 ns - Consult factory
70 ns
90 ns
120 ns
Temp. range/screening Blank
I
M
MB
=
=
=
=
Commercial Temperature
Industrial Temperature
Military Temperature
Processed in accordance with
MIL-STD-883
Packages
S = 32 pin Ceramic Dual In-line
J = 32 pad Ceramic JLCC
Organisation
8516 = 512Kx 8 Flash Memory
Technology
F = FLASH Memory
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantability or fitness for a particular purpose.
Our Products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express approval of a company
director.
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