NXP LPC2109FBD64 Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash Data Sheet
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LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN
Rev. 7 — 14 June 2011 Product data sheet
The LPC2109/2119/2129 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 64/128/256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.
With their compact 64-pin package, low power consumption, various 32-bit timers,
4-channel 10-bit ADC, two advanced CAN channels, PWM channels and 46 fast GPIO lines with up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications, as well as medical systems and fault-tolerant maintenance buses. With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2109/2119/2129 will apply to devices with and without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate from other devices only when necessary.
2. Features and benefits
2.1 Key features brought by LPC2109/2119/2129/01 devices
Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.
They also allow for a port pin to be read at any time regardless of its function.
Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are
5 V tolerant when configured for digital I/O function(s).
UART0/1 include fractional baud rate generator, auto-bauding capabilities and handshake flow-control fully implemented in hardware.
Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
SPI programmable data length and master mode enhancement.
Diversified Code Read Protection (CRP) enables different security levels to be implemented. This feature is available in LPC2109/2119/2129/00 devices as well.
General purpose timers can operate as external event counters.
2.2 Key features common for all devices
16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
8/16 kB on-chip SRAM.
NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
64/128/256 kB on-chip flash program memory. 128-bit wide interface/accelerator enables high speed 60 MHz operation.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or full chip erase takes 400 ms.
EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service routines can continue to execute while the foreground task is debugged with the on-chip RealMonitor software.
Embedded Trace Macrocell (ETM) enables non-intrusive high speed real-time tracing of instruction execution.
Two interconnected CAN interfaces (one for LPC2109) with advanced acceptance filters.
Four-channel 10-bit A/D converter with conversion time as low as 2.44
s.
Multiple serial interfaces including two UARTs (16C550), Fast I 2 C-bus (400 kbit/s) and two SPIs.
60 MHz maximum CPU clock available from programmable on-chip Phase-Locked
Loop with settling time of 100
s.
Vectored Interrupt Controller with configurable priorities and vector addresses.
Two 32-bit timers (with four capture and four compare channels), PWM unit (six outputs), Real-Time Clock (RTC) and watchdog.
Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level sensitive external interrupt pins available.
On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
Two low power modes, Idle and Power-down.
Processor wake-up from Power-down mode via external interrupt.
Individual enable/disable of peripheral functions for power optimization.
Dual power supply:
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V
0.15 V).
I/O power supply range of 3.0 V to 3.6 V (3.3 V
10 %) with 5 V tolerant I/O pads.
Table 1.
Ordering information
Type number Package
Name
LPC2109FBD64/01 LQFP64
LPC2119FBD64/01
LPC2129FBD64/01
LQFP64
LQFP64
Description plastic low profile quad flat package; 64 leads; body 10
10 1.4 mm plastic low profile quad flat package; 64 leads; body 10
10 1.4 mm plastic low profile quad flat package; 64 leads; body 10
10 1.4 mm
Version
SOT314-2
SOT314-2
SOT314-2
LPC2109_2119_2129
Product data sheet
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NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
3.1 Ordering options
Table 2.
Ordering options
Type number Flash memory
LPC2109FBD64/01 64 kB
LPC2119FBD64/01 128 kB
LPC2129FBD64/01 256 kB
RAM
8 kB
16 kB
16 kB
CAN
1 channel
2 channels
2 channels
Fast GPIO/
SSP/
Enhanced
UART, ADC,
Timer
Temperature range yes yes yes
40 C to +85 C
40 C to +85 C
40 C to +85 C
LPC2109_2119_2129
Product data sheet
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NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
TRST
TMS
(2)
(2)
TCK
TDI
(2)
(2)
RTCK
TDO
(2)
XTAL2
XTAL1 RESET
P0[30:27],
P0[25:0]
P1[31:16]
LPC2109
LPC2119
LPC2129
HIGH-SPEED
GPI/O
(4)
46 PINS TOTAL
ARM7 LOCAL BUS
TEST/DEBUG
INTERFACE
ARM7TDMI-S
AHB BRIDGE system clock
PLL
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
AMBA Advanced High-performance
Bus (AHB)
V
DD(3V3)
V
DD(1V8)
V
SS
EINT[3:0]
(1)
4 × CAP0
4
×
CAP1
(1)
(1)
4 × MAT0
(1)
4
×
MAT1
(1)
AIN[3:0]
(1)
P0[30:27],
P0[25:0]
P1[31:16]
PWM[6:1]
(1)
INTERNAL
SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
8/16 kB
SRAM
64/128/256 kB
FLASH
EXTERNAL
INTERRUPTS
CAPTURE/
COMPARE
TIMER 0/TIMER 1
A/D CONVERTER
AHB TO APB
BRIDGE
APB
DIVIDER
AHB
DECODER
I
2
C-BUS SERIAL
INTERFACE
SPI1/SSP
(4)
SERIAL
INTERFACE
SPI0 SERIAL
INTERFACE
UART0/UART1
SCL
(1)
SDA
(1)
SCK1
(1)
MOSI1
(1)
MISO1
(1)
SSEL1
(1)
SCK0
(1)
MOSI0
(1)
MISO0
(1)
SSEL0
(1)
TXD[1:0]
(1)
RXD[1:0]
(1)
DSR1
(1)
, CTS1
(1)
,
RTS1
(1)
, DTR1
(1)
,
DCD1
(1)
, RI1
(1)
GENERAL
PURPOSE I/O
PWM0
WATCHDOG
TIMER
SYSTEM
CONTROL
RD[2:1]
(1)
TD[2:1]
(1)
CAN INTERFACE 1 AND 2
ACCEPTANCE FILTERS
(3)
REAL-TIME CLOCK
002aad172
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) Only 1 for LPC2109.
(4) SSP interface and high-speed GPIO are available on LPC2109/01, LPC2119/01, and LPC2129/01 only.
Fig 1.
Block diagram
LPC2109_2119_2129
Product data sheet
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5.1 Pinning
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
P0[21]/PWM5/CAP1[3]
P0[22]/CAP0[0]/MAT0[0]
P0[23]/RD2
(1)
P1[19]/TRACEPKT3
P0[24]/TD2
(1)
V
SS
V
DDA(3V3)
P1[18]/TRACEPKT2
P0[25]/RD1
TD1
P0[27]/AIN0/CAP0[1]/MAT0[1]
P1[17]/TRACEPKT1
P0[28]/AIN1/CAP0[2]/MAT0[2]
P0[29]/AIN2/CAP0[3]/MAT0[3]
P0[30]/AIN3/EINT3/CAP0[0]
P1[16]/TRACEPKT0
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
LPC2109
LPC2119
LPC2129 (2)
36
35
34
33
40
39
38
37
44
43
42
41
48
47
46
45
P1[20]/TRACESYNC
P0[17]/CAP1[2]/SCK1/MAT1[2]
P0[16]/EINT0/MAT0[2]/CAP0[2]
P0[15]/RI1/EINT2
P1[21]/PIPESTAT0
V
DD(3V3)
V
SS
P0[14]/DCD1/EINT1
P1[22]/PIPESTAT1
P0[13]/DTR1/MAT1[1]
P0[12]/DSR1/MAT1[0]
P0[11]/CTS1/CAP1[1]
P1[23]/PIPESTAT2
P0[10]/RTS1/CAP1[0]
P0[9]/RXD1/PWM6/EINT3
P0[8]/TXD1/PWM4
002aad173
(1) No TD2 and RD2 for LPC2109.
(2) Pin configuration is identical for devices with and without /00 and /01 suffixes.
Fig 2.
Pin configuration
LPC2109_2119_2129
Product data sheet
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LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
P0[0]/TXD0/
PWM1
P0[1]/RXD0/
PWM3/EINT0
P0[2]/SCL/
CAP0[0]
P0[3]/SDA/
MAT0[0]/EINT1
P0[4]/SCK0/
CAP0[1]
P0[5]/MISO0/
MAT0[1]
P0[6]/MOSI0/
CAP0[2]
P0[7]/SSEL0/
PWM2/EINT2
P0[8]/TXD1/
PWM4
P0[9]/RXD1/
PWM6/EINT3
P0[10]/RTS1/
CAP1[0]
P0[11]/CTS1/
CAP1[1]
P0[12]/DSR1/
MAT1[0]
P0[13]/DTR1/
MAT1[1]
P0[14]/DCD1/
EINT1
5.2 Pin description
Table 3.
Pin description
Symbol
P0[0] to P0[31]
Pin
19
21
22
26
27
29
30
31
33
34
35
37
38
39
41
I
I
I
O
O
O
I
I
I
O
I
O
I
O
I
O
I
O
O
O
I
O
Type Description
I/O Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit.
The operation of port 0 pins depends upon the pin function selected via the Pin
Connect Block. Pins 26 and 31 of port 0 are not available.
TXD0 — Transmitter output for UART0.
PWM1 — Pulse Width Modulator output 1.
RXD0 — Receiver input for UART0.
PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input
I/O SCL — I 2 C-bus clock input/output. Open-drain output (for I 2 C-bus compliance).
I CAP0[0] — Capture input for Timer 0, channel 0.
I/O SDA — I 2 C-bus data input/output. Open-drain output (for I 2 C-bus compliance).
I
O MAT0[0] — Match output for Timer 0, channel 0.
EINT1 — External interrupt 1 input.
I
I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
CAP0[1] — Capture input for Timer 0, channel 1.
I/O MISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data output from SPI slave.
I
O MAT0[1] — Match output for Timer 0, channel 1.
I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave.
CAP0[2] — Capture input for Timer 0, channel 2.
SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
PWM2 — Pulse Width Modulator output 2.
EINT2 — External interrupt 2 input.
TXD1 — Transmitter output for UART1.
PWM4 — Pulse Width Modulator output 4.
RXD1 — Receiver input for UART1.
PWM6 — Pulse Width Modulator output 6.
EINT3 — External interrupt 3 input.
RTS1 — Request to Send output for UART1.
CAP1[0] — Capture input for Timer 1, channel 0.
CTS1 — Clear to Send input for UART1.
CAP1[1] — Capture input for Timer 1, channel 1.
DSR1 — Data Set Ready input for UART1.
MAT1[0] — Match output for Timer 1, channel 0.
DTR1 — Data Terminal Ready output for UART1.
MAT1[1] — Match output for Timer 1, channel 1.
DCD1 — Data Carrier Detect input for UART1.
EINT1 — External interrupt 1 input.
Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take control of the part after reset.
LPC2109_2119_2129
Product data sheet
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Rev. 7 — 14 June 2011
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Single-chip 16/32-bit microcontrollers
Table 3.
Pin description …continued
Symbol Pin
P0[15]/RI1/EINT2 45 I
Type Description
RI1 — Ring Indicator input for UART1.
P0[16]/EINT0/
MAT0[2]/CAP0[2]
46
I
I
O
EINT2 — External interrupt 2 input.
EINT0 — External interrupt 0 input.
MAT0[2] — Match output for Timer 0, channel 2.
P0[17]/CAP1[2]/
SCK1/MAT1[2]
P0[18]/CAP1[3]/
MISO1/MAT1[3]
P0[19]/MAT1[2]/
MOSI1/CAP1[2]
P0[20]/MAT1[3]/
SSEL1/EINT3
47
53
54
55
I CAP0[2] — Capture input for Timer 0, channel 2.
I CAP1[2] — Capture input for Timer 1, channel 2.
I/O SCK1 — Serial Clock for SPI1/SSP
. SPI clock output from master or input to slave.
O MAT1[2] — Match output for Timer 1, channel 2.
I CAP1[3] — Capture input for Timer 1, channel 3.
I/O MISO1 — Master In Slave Out for SPI1/SSP
. Data input to SPI master or data output from SPI slave.
I
I
I
O
O MAT1[3] — Match output for Timer 1, channel 3.
O MAT1[2] — Match output for Timer 1, channel 2.
I/O
MOSI1 — Master Out Slave In for SPI1/SSP [1]
. Data output from SPI master or data input to SPI slave.
CAP1[2] — Capture input for Timer 1, channel 2.
MAT1[3] — Match output for Timer 1, channel 3.
SSEL1 — Slave Select for SPI1/SSP
[1] . Selects the SPI interface as a slave.
EINT3 — External interrupt 3 input.
P0[21]/PWM5/
CAP1[3]
P0[22]/CAP0[0]/
MAT0[0]
P0[23]/RD2
P0[24]/TD2
P0[25]/RD1
P0[27]/AIN0/
CAP0[1]/MAT0[1]
P0[28]/AIN1/
CAP0[2]/MAT0[2]
P0[29]/AIN2/
CAP0[3]/MAT0[3]
P0[30]/AIN3/
EINT3/CAP0[0]
P1[0] to P1[31]
1
2
3
5
9
11
13
14
15
I
O
I
O
I
I
I
O
I
I
I
O
I
O
I
O
PWM5 — Pulse Width Modulator output 5.
CAP1[3] — Capture input for Timer 1, channel 3.
CAP0[0] — Capture input for Timer 0, channel 0.
MAT0[0] — Match output for Timer 0, channel 0.
CAN2 receiver input (not available on LPC2109).
CAN2 transmitter output (not available on LPC2109).
CAN1 receiver input.
AIN0 — A/D converter, input 0. This analog input is always connected to its pin.
CAP0[1] — Capture input for Timer 0, channel 1.
MAT0[1] — Match output for Timer 0, channel 1.
AIN1 — A/D converter, input 1. This analog input is always connected to its pin.
CAP0[2] — Capture input for Timer 0, channel 2.
MAT0[2] — Match output for Timer 0, channel 2.
AIN2 — A/D converter, input 2. This analog input is always connected to its pin.
CAP0[3] — Capture input for Timer 0, Channel 3.
MAT0[3] — Match output for Timer 0, channel 3.
I
I AIN3 — A/D converter, input 3. This analog input is always connected to its pin.
EINT3 — External interrupt 3 input.
I CAP0[0] — Capture input for Timer 0, channel 0.
I/O Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit.
The operation of port 1 pins depends upon the pin function selected via the Pin
Connect Block. Pins 0 through 15 of port 1 are not available.
LPC2109_2119_2129
Product data sheet
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LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
Table 3.
Pin description …continued
Symbol Pin Type Description
P1[16]/
TRACEPKT0
16 O Trace Packet, bit 0. Standard I/O port with internal pull-up.
12 O Trace Packet, bit 1. Standard I/O port with internal pull-up.
P1[17]/
TRACEPKT1
P1[18]/
TRACEPKT2
8 O Trace Packet, bit 2. Standard I/O port with internal pull-up.
P1[19]/
TRACEPKT3
P1[20]/
TRACESYNC
4
48
44
O
O
O
Trace Packet, bit 3. Standard I/O port with internal pull-up.
Trace Synchronization. Standard I/O port with internal pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to operate as
Trace port after reset.
Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P1[21]/
PIPESTAT0
P1[22]/
PIPESTAT1
P1[23]/
PIPESTAT2
P1[24]/
TRACECLK
P1[25]/EXTIN0
P1[26]/RTCK
40
36
32
28
24
O
O
O
Pipeline Status, bit 1. Standard I/O port with internal pull-up.
Pipeline Status, bit 2. Standard I/O port with internal pull-up.
Trace Clock. Standard I/O port with internal pull-up.
P1[27]/TDO
P1[28]/TDI
P1[29]/TCK
P1[30]/TMS
P1[31]/TRST
TD1
RESET
XTAL1
XTAL2
V
SS
V
SSA
64
60
56
52
20
10
57
62
61
6, 18, 25,
42, 50
59 I
I
I
O
I
I
I
O
I
I
I External Trigger Input. Standard I/O with internal pull-up.
I/O Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as
Debug port after reset.
O Test Data out for JTAG interface.
Test Data in for JTAG interface.
Test Clock for JTAG interface. This clock must be slower than 1 ⁄
6
of the CPU clock
(CCLK) for the JTAG interface to operate.
Test Mode Select for JTAG interface.
Test Reset for JTAG interface.
CAN1 transmitter output.
External reset input; a LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Ground: 0 V reference.
V
V
SSA(PLL)
DD(1V8)
58
17, 49 I
I
Analog ground; 0 V reference. This should nominally be the same voltage as V
SS
, but should be isolated to minimize noise and error.
PLL analog ground; 0 V reference. This should nominally be the same voltage as
V
SS
, but should be isolated to minimize noise and error.
1.8 V core power supply; this is the power supply voltage for internal circuitry.
LPC2109_2119_2129
Product data sheet
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LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
Table 3.
Pin description …continued
Symbol Pin Type Description
V
DDA(1V8)
63 I
V
DD(3V3)
V
DDA(3V3)
23, 43, 51
7 I
I
Analog 1.8 V core power supply; this is the power supply voltage for internal circuitry. This should be nominally the same voltage as V
DD(1V8)
but should be isolated to minimize noise and error.
3.3 V pad power supply; this is the power supply voltage for the I/O ports.
Analog 3.3 V pad power supply; this should be nominally the same voltage as
V
DD(3V3)
but should be isolated to minimize noise and error.
[1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only.
LPC2109_2119_2129
Product data sheet
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NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
LPC2109_2119_2129
Product data sheet
Details of the LPC2109/2119/2129 systems and peripheral functions are described in the following sections.
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2 On-chip flash program memory
The LPC2109/2119/2129 incorporate a 64/128/256 kB flash memory system, respectively.
This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. When on-chip bootloader is used, 60/120/248 kB of flash memory is available for user code.
The LPC2109/2119/2129 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data retention.
On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the
LPC2109/2119/2129 on-chip flash memory. When the CRP is enabled, the JTAG debug port and ISP commands accessing either the on-chip RAM or flash memory are disabled.
All information provided in this document is subject to legal disclaimers.
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© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
However, the ISP flash erase command can be executed at any time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of full on-chip user flash.
With the CRP off, full access to the chip via the JTAG and/or ISP is restored.
6.3 On-chip SRAM
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8 bit, 16 bit, and 32 bit. The LPC2109/2119/2129 provide 8 kB of SRAM for the
LPC2109 and 16 kB for the LPC2119 and LPC2129.
6.4 Memory map
The LPC2109/2119/2129 memory maps incorporate several distinct regions, as shown in
.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip SRAM. This is described in Section 6.18 “System control”
.
LPC2109_2119_2129
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2011
© NXP B.V. 2011. All rights reserved.
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4.0 GB
3.75 GB
3.5 GB
3.0 GB
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
AHB PERIPHERALS
APB PERIPHERALS
0xFFFF FFFF
0xF000 0000
0xEFFF FFFF
0xE000 0000
0xDFFF FFFF
0xC000 0000
RESERVED ADDRESS SPACE
2.0 GB
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP FLASH MEMORY)
RESERVED ADDRESS SPACE
16 kB ON-CHIP STATIC RAM (LPC2119/2129)
8 kB ON-CHIP STATIC RAM (LPC2109)
1.0 GB
0x8000 0000
0x7FFF FFFF
0x7FFF E000
0x7FFF DFFF
0x4000 4000
0x4000 3FFF
0x4000 1FFF
0x4000 0000
0x3FFF FFFF
0.0 GB
RESERVED ADDRESS SPACE
256 kB ON-CHIP FLASH MEMORY (LPC2129)
128 kB ON-CHIP FLASH MEMORY (LPC2119)
64 kB ON-CHIP FLASH MEMORY (LPC2109)
0x0004 0000
0x0003 FFFF
0x0002 0000
0x0001 FFFF
0x0001 0000
0x0000 FFFF
0x0000 0000
002aad174
Fig 3.
LPC2109/2119/2129 memory map
LPC2109_2119_2129
Product data sheet
6.5 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt reQuest (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.
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Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has
one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
Table 4.
Interrupt sources
Block Flag(s)
WDT
-
ARM Core
ARM Core
Timer 0
Watchdog Interrupt (WDINT)
Reserved for software interrupts only
EmbeddedICE, DbgCommRx
Timer 1
UART0
EmbeddedICE, DbgCommTx
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
UART1
PWM0
I 2 C-bus
SPI0
PLL
RTC
Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
SI (state change)
SPIF, MODF
SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS
PLL Lock (PLOCK)
RTCCIF (Counter Increment), RTCALF (Alarm)
11
12
13
8
9
10
3
4
1
2
VIC channel #
0
5
6
7
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Table 4.
Interrupt sources …continued
Block Flag(s)
System Control External Interrupt 0 (EINT0)
ADC
CAN
External Interrupt 1 (EINT1)
External Interrupt 2 (EINT2)
External Interrupt 3 (EINT3)
A/D Converter
CAN1, CAN2 and Acceptance Filter
[1] SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only.
VIC channel #
14
15
16
17
18
19 to 23
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.
6.7 General purpose parallel I/O (GPIO) and Fast I/O
Device pins that are not connected to a specific peripheral function are controlled by the parallel I/O registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins.
6.7.1 Features
• Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port.
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
6.7.2 Features added with the Fast GPIO set of registers available on
LPC2109/2119/2129/01 only
• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.
• Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.
• All Fast GPIO registers are byte addressable.
• Entire port value can be written in one instruction.
• Ports are accessible via either the legacy group of registers (GPIOs) or the group of registers providing accelerated port access (Fast GPIOs).
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6.8 10-bit ADC
The LPC2109/2119/2129 each contain a single 10-bit successive approximation ADC with four multiplexed channels.
6.8.1 Features
• Measurement range of 0 V to 3 V.
• Capable of performing more than 400000 10-bit samples per second.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
6.8.2 ADC features available in LPC2109/2119/2129/01 only
• Every analog input has a dedicated result register to reduce interrupt overhead.
• Every analog input can generate an interrupt once the conversion is completed.
• The ADC pads are 5 V tolerant when configured for digital I/O function(s).
6.9 CAN controllers and acceptance filter
The LPC2119 and LPC2129 each contain two CAN controllers, while the LPC2109 has one CAN controller. The CAN is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low-cost multiplex wiring.
6.9.1 Features
• Data rates up to 1 Mbit/s on each bus.
• 32-bit register and RAM access.
• Compatible with CAN specification 2.0 B, ISO 11898-1.
• Global Acceptance Filter recognizes 11-bit and 29-bit Rx identifiers for all CAN buses.
• Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard identifiers.
6.10 UARTs
The LPC2109/2119/2129 each contain two UARTs. In addition to standard transmit and receive data lines, the UART1 also provides a full modem control handshake interface.
6.10.1 Features
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.
• Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs.
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• UART1 is equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS).
6.10.2 UART features available in LPC2109/2119/2129/01 only
Compared to previous LPC2000 microcontrollers, UARTs in LPC2109/2119/2129/01 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 Bd with any crystal frequency above
2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware.
• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be achieved with any crystal frequency above 2 MHz.
• Auto-bauding.
• Auto-CTS/RTS flow-control fully implemented in hardware.
6.11 I 2 C-bus serial I/O controller
The I 2 C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I 2 C-bus is a multi-master bus; it can be controlled by more than one bus master connected to it.
The I 2 C-bus implemented in LPC2109/2119/2129 supports a bit rate up to 400 kbit/s (Fast
I 2 C-bus).
6.11.1 Features
• Standard I 2 C-bus compliant interface.
• Easy to configure as Master, Slave, or Master/Slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.
• The I 2 C-bus may be used for test and diagnostic purposes.
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6.12 SPI serial I/O controller
The LPC2109/2119/2129 each contain two SPIs. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.
6.12.1 Features
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex communication.
• Combined SPI master and slave.
• Maximum data bit rate of 1 ⁄
8
of the input clock rate.
6.12.2 Features available in LPC2109/2119/2129/01 only
• Eight to 16 bits per frame.
• When the SPI interface is used in Master mode, the SSELn pin is not needed (can be used for a different function).
6.13 SSP controller (LPC2109/2119/2129/01 only)
Remark: This peripheral is available in LPC2109/2119/2129/01 only.
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of four to 16 bits of data flowing from the master to the slave and from the slave to the master.
While the SSP and SPI1 peripherals share the same physical pins, it is not possible to have both of these two peripherals active at the same time. Application can switch on the fly from SPI1 to SSP and back.
6.13.1 Features
• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
• Synchronous serial communication.
• Master or slave operation.
• 8-frame FIFOs for both transmit and receive.
• Four to 16 bits per frame.
6.14 General purpose timers
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs
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Single-chip 16/32-bit microcontrollers to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
6.14.1 Features
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
• Timer or external event counter operation
• Four 32-bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Four external outputs per timer corresponding to match registers, with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
6.14.2 Features available in LPC2109/2119/2129/01 only
The LPC2109/2119/2129/01 can count external events on one of the capture inputs if the external pulse lasts at least one half of the period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts.
• Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied clock.
• When counting cycles of an externally supplied clock, only one of the timer’s capture inputs can be selected as the timer’s clock. The rate of such a clock is limited to
PCLK / 4. Duration of HIGH/LOW levels on the selected CAPn input cannot be shorter than 1 / (2PCLK).
6.15 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time.
6.15.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
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• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.
• Incorrect/incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal pre-scaler.
• Selectable time period from (T cy(PCLK)
T cy(PCLK)
4.
256 4) to (T cy(PCLK)
2 32 4) in multiples of
6.16 Real-time clock
The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
6.16.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
• Programmable reference clock divider allows adjustment of the RTC to match various crystal frequencies.
6.17 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2109/2119/2129. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The
PWM function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions.
Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs.
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Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).
6.17.1 Features
• Seven match registers allow up to six single edge controlled or three double edge controlled PWM outputs, or a mix of both types.
• The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.
• Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
6.18 System control
6.18.1 Crystal oscillator
The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output frequency is called f osc
and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc.. f osc
and CCLK are the same value unless the PLL is running and connected. Refer to
for additional information.
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6.18.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip Reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100
s.
6.18.3 Reset and wake-up timer
Reset has two sources on the LPC2109/2119/2129: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which is the Reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V
DD
ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
6.18.4 Code security (Code Read Protection - CRP)
This feature of the LPC2109/2119/2129 allows the user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
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CAUTION
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CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.
Remark: Devices without the suffix /00 or /01 have only a security level equivalent to
CRP2 available.
6.18.5 External interrupt inputs
The LPC2109/2119/2129 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.
6.18.6 Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip SRAM. This allows code running in different memory spaces to have control of the interrupts.
6.18.7 Power control
The LPC2109/2119/2129 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.
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6.18.8 APB
The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via APB so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB may be slowed down to 1 ⁄
2
to 1 ⁄
4
of the processor clock rate. Because the APB must work properly at power-up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB), the default condition at reset is for the APB to run at 1 ⁄
4
of the processor clock rate. The second purpose of the APB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate.
Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
6.19 Emulation and debugging
The LPC2109/2119/2129 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself.
6.19.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than 1 ⁄
6
of the CPU clock (CCLK) for the JTAG interface to operate.
6.19.2 Embedded trace macrocell
Since the LPC2109/2119/2129 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the
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Single-chip 16/32-bit microcontrollers pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction.
6.19.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables real time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC (Debug
Communications Channel), which is present in the EmbeddedICE logic. The
LPC2109/2119/2129 contain a specific configuration of RealMonitor software programmed into the on-chip flash memory.
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Single-chip 16/32-bit microcontrollers
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter supply voltage (1.8 V)
Conditions
V
DD(1V8)
V
DD(3V3)
V
DDA(3V3)
V
IA
V
I supply voltage (3.3 V) analog supply voltage (3.3 V) analog input voltage input voltage 5 V tolerant I/O pins other I/O pins supply current I
DD
I
SS
T j
T stg
P tot(pack)
V esd ground current junction temperature storage temperature total power dissipation (per package) based on package heat transfer, not device power consumption electrostatic discharge voltage human body model; all pins
Min
0.5
0.5
0.5
0.5
0.5
0.5
-
-
-
65
-
2000
Max
+2.5
+3.6
+4.6
+5.1
+6.0
V
DD(3V3)
100
100
150
+150
1.5
+2000
+ 0.5
V
V
V mA mA
C
C
W
V
V
Unit
V
V
[1] The following applies to
: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless otherwise noted.
[2] Internal rail.
[3] External rail.
[4] Including voltage on outputs in 3-state mode.
[5] Only valid when the V
DD(3V3)
supply voltage is present.
[6] Not to exceed 4.6 V.
[7] Per supply pin.
[8] The peak current is limited to 25 times the corresponding maximum current.
[9] Per ground pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k
series resistor.
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Single-chip 16/32-bit microcontrollers
Table 6.
Static characteristics
T amb
=
40
C to +85
C for industrial applications, unless otherwise specified.
Symbol Parameter Conditions Min
1.65
V
DD(1V8) supply voltage (1.8 V)
V
DD(3V3) supply voltage (3.3 V)
V
DDA(3V3) analog supply voltage
(3.3 V)
3.0
2.5
I
I
V
I
V
O
V
IH
V
IL
V hys
V
OH
V
OL
I
OH
I
OL
I
OHS
I
Standard port pins, RESET, RTCK
I
IL
I
IH
I
OZ latch
LOW-level input current V
HIGH-level input current V
I
I
= 0 V; no pull-up
= V
DD(3V3)
; no pull-down
OFF-state output current V
O
= 0 V; V
O
= V no pull-up/down
DD(3V3)
;
I/O latch-up current
(0.5V
DD(3V3)
) < V
I
<
(1.5V
DD(3V3)
); T j
< 125
C input voltage output voltage
HIGH-level input voltage
LOW-level input voltage hysteresis voltage
HIGH-level output voltage I output active
LOW-level output voltage I
OL
HIGH-level output current
LOW-level output current V
HIGH-level short-circuit output current
OH
V
V
OH
OL
OH
=
4 mA
= 4 mA
= V
DD(3V3)
= 0.4 V
= 0 V
0.4 V
I
OLS
V
OL
= V
DD(3V3) pd pu
LOW-level short-circuit output current pull-down current pull-up current
V
V
I
I
= 5 V
= 0 V
V
DD(3V3)
< V
I
< 5 V
-
-
0
0
-
2.0
-
-
0.4
-
V
DD(3V3)
0.4 -
-
4
-
4 -
-
-
-
-
-
-
-
-
-
100
10
15
0
-
-
-
Typ
1.8
3.3
3.3
50
50
0
Max
1.95
3.6
3.6
-
3
3
3
5.5
-
V
DD(3V3)
0.8
-
-
0.4
-
-
45
50
150
85
0 mA
A
A
A
V
V mA mA mA
V
V
V
V
V
A
A
A mA
V
V
Unit
V
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V
IH
V
IL
V hys
V
OL
I
LI
Table 6.
Static characteristics …continued
T amb
=
40
C to +85
C for industrial applications, unless otherwise specified.
Symbol Parameter Conditions Min
Power consumption LPC2109/00, LPC2119, LPC2119/00, LPC2129, LPC2129/00
I
DD(act) active mode supply current
V
DD(1V8)
= 1.8 V;
CCLK = 60 MHz;
T amb
= 25
C; code while(1){} executed from flash; all peripherals enabled via
register but not configured to run
I
I
DD(pd)
Power-down mode supply current
V
DD(1V8)
= 1.8 V;
T amb
= 25
C
V
DD(1V8)
T amb
= 1.8 V;
= 85
C
Power consumption LPC2109/01, LPC2119/01, LPC2129/01
DD(act) active mode supply current
V
DD(1V8)
= 1.8 V;
CCLK = 60 MHz;
T amb
= 25
C; code while(1){} executed from flash; all peripherals enabled via
register but not configured to run
I
DD(idle)
Idle mode supply current V
DD(1V8)
= 1.8 V;
CCLK = 60 MHz;
T amb
= 25
C; executed from flash; all peripherals enabled via
register but not configured to run
I
DD(pd)
Power-down mode supply current
V
DD(1V8)
= 1.8 V;
T amb
= 25
C
V
DD(1V8)
= 1.8 V;
T amb
= 85
C
I 2 C-bus pins
-
-
-
-
-
-
HIGH-level input voltage
LOW-level input voltage hysteresis voltage
LOW-level output voltage I
OLS
= 3 mA input leakage current V
I
= V
DD(3V3)
V
I
= 5 V
-
-
-
-
-
0.7V
DD(3V3)
Typ [1]
60
10
110
41.5
9
10
110
-
-
-
-
-
Max
500
500
Unit mA
A
A mA mA
A
A
-
0.3V
DD(3V3)
-
0.05V
DD(3V3)
-
0.4
2
10
4
22
V
V
V
V
A
A
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Single-chip 16/32-bit microcontrollers
Table 6.
Static characteristics …continued
T amb
=
40
C to +85
C for industrial applications, unless otherwise specified.
Symbol Parameter Conditions Min
Oscillator pins
0 V i(XTAL1) input voltage on pin
XTAL1
V o(XTAL2) output voltage on pin
XTAL2
0 -
-
Typ [1]
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply voltages.
[2] Internal rail.
[3] External rail.
[4] Including voltage on outputs in 3-state mode.
[5] V
DD(3V3)
supply voltages must be present.
[6] 3-state outputs go into 3-state mode when V
DD(3V3)
is grounded.
[7] Accounts for 100 mV voltage drop in all supply lines.
[8] Only allowed for a short time period.
[9] Minimum condition for V
I
= 4.5 V, maximum condition for V
I
= 5.5 V.
[10] Applies to P1[25:16].
[11] See LPC2119/2129/2194/2292/2294 User Manual.
[12] To V
SS
.
Max
1.8
1.8
Unit
V
V
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Single-chip 16/32-bit microcontrollers
Table 7.
ADC static characteristics
V
DDA
= 2.5 V to 3.6 V unless otherwise specified; T
4.5 MHz.
amb
=
40
C to +85
C unless otherwise specified. ADC frequency
Conditions Symbol
V
IA
C ia
E
D
E
L(adj)
E
O
E
G
E
T
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error
-
-
-
-
-
-
Min
0
-
-
-
-
-
-
-
Typ Max
V
DDA
1
1
2
3
0.5
4
Unit
V pF
LSB
LSB
LSB
%
LSB
[1] Conditions: V
SSA
= 0 V, V
DDA
= 3.3 V.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See
[4] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See
[5] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
.
[6] The gain error (E
G
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 4
.
[7] The absolute voltage error (E
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See
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Single-chip 16/32-bit microcontrollers offset error
E
O gain error
E
G
1023
1022
1021
1020
1019
1018
(2) code out
7
6
5
(5)
4
3
(4)
(3)
2
1
0
1 2 3 4
1 LSB
(ideal)
5 6 7
V
IA
(LSB ideal
) offset error
E
O
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (E
D
).
(4) Integral non-linearity (E
L(adj)
).
(5) Center of a step of the actual transfer curve.
Fig 4.
ADC characteristics
(1)
1018 1019 1020 1021 1022 1023 1024
1 LSB =
V
DDA
−
V
SSA
1024
002aaa668
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8.1 Power consumption measurements for LPC2109/01, LPC2119/01,
LPC2129/01 devices
The power consumption measurements represent typical values for the given conditions.
The peripherals were enabled through the PCONP register, but for these measurements, the peripherals were not configured to run. Peripherals were disabled through the PCONP register. Refer to the LPC2119/2129/2194/2292/2294 User Manual for a description of the
PCONP register.
002aad127
45
I
DD(act)
(mA)
35 all peripherals enabled all peripherals disabled
25
15
5
12 20 28 36 44
Test conditions: Active mode entered executing code from on-chip flash; PCLK =
CCLK
⁄
4
;
T amb
= 25
C; core voltage 1.8 V.
Fig 5.
Typical LPC2109/01 I
DD(act)
measured at different frequencies
45
I
DD(act)
(mA)
35
60 MHz
48 MHz
52 frequency (MHz)
60
002aad128
25
15
12 MHz
5
1.65
1.70
1.75
1.80
1.85
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK ⁄
4
;
T amb
= 25
C; core voltage 1.8 V; all peripherals enabled.
Fig 6.
Typical LPC2109/01 I
DD(act)
measured at different voltages
1.90
voltage (V)
1.95
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Single-chip 16/32-bit microcontrollers
10
I
DD(idle)
(mA)
8
6
4
2 all peripherals enabled all peripherals disabled
0
12 20 28 36 44
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK ⁄
4
;
T amb
= 25
C; core voltage 1.8 V.
Fig 7.
Typical LPC2109/01 I
DD(idle)
measured at different frequencies
10
I
DD(idle)
(mA)
7.5
60 MHz
48 MHz
5.0
002aad129
52 frequency (MHz)
60
002aad130
2.5
12 MHz
0
1.65
1.70
1.75
1.80
1.85
Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
CCLK
⁄
4
;
T amb
= 25
C; core voltage 1.8 V; all peripherals enabled.
Fig 8.
Typical LPC2109/01 I
DD(idle)
measured at different voltages
1.90
voltage (V)
1.95
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LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers all peripherals enabled all peripherals disabled
002aad131
45
I
DD(act)
(mA)
35
25
15
5
12 20 28 36 44
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK ⁄
4
;
T amb
= 25
C; core voltage 1.8 V.
Fig 9.
Typical LPC2119/01 and LPC2129/01 I
DD(act)
measured at different frequencies
50
I
DD(act)
(mA)
40
60 MHz
48 MHz
30
52 frequency (MHz)
60
002aad132
20
10
12 MHz
0
1.65
1.70
1.75
1.80
1.85
Test conditions: Active mode entered executing code from on-chip flash; PCLK =
CCLK
⁄
4
;
T amb
= 25
C; core voltage 1.8 V; all peripherals enabled.
Fig 10. Typical LPC2119/01 and LPC2129/01 I
DD(act)
measured at different voltages
1.90
voltage (V)
1.95
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LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers all peripherals enabled all peripherals disabled
002aad133
10
I
DD(idle)
(mA)
8
6
4
2
0
12 20 28 36 44
Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK ⁄
4
;
T amb
= 25
C; core voltage 1.8 V.
Fig 11. Typical LPC2119/01 and LPC2129/01 I
DD(idle)
measured at different frequencies
10
I
DD(idle)
(mA)
8
60 MHz
48 MHz
52 frequency (MHz)
60
002aad134
6
4
2
12 MHz
0
1.65
1.70
1.75
1.80
1.85
Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
CCLK
⁄
4
;
T amb
= 25
C; core voltage 1.8 V; all peripherals enabled.
Fig 12. Typical LPC2119/01 and LPC2129/01 I
DD(idle)
measured at different voltages
1.90
voltage (V)
1.95
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Single-chip 16/32-bit microcontrollers
60 MHz
48 MHz
002aad135
45
I
DD(act)
(mA)
35
25
15
12 MHz
5
1.65
1.70
1.75
1.80
1.85
1.90
voltage (V)
1.95
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK ⁄
4
;
Temp = 25
C; core voltage 1.8 V; all peripherals disabled.
Fig 13. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I
DD(act)
measured at different voltages
002aad136
8
I
DD(idle)
(mA)
6 60 MHz
48 MHz
4
2
12 MHz
0
1.65
1.70
1.75
1.80
1.85
1.90
voltage (V)
1.95
Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
CCLK
⁄
4
;
Temp = 25
C; core voltage 1.8 V; all peripherals disabled.
Fig 14. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I
DD(idle)
measured at different voltages
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LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
60 MHz
48 MHz
002aad137
45
I
DD(act)
(mA)
35
25
15
12 MHz
5
− 40 − 15 10 35 60 temperature (
°
C)
85
Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK ⁄
4
; core voltage 1.8 V; all peripherals disabled.
Fig 15. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I
DD(act)
measured at different temperatures
002aad138
6
I
DD(idle)
(mA)
5
60 MHz
48 MHz
4
3
2
12 MHz
1
−
40
−
15 10 35 60 temperature ( ° C)
85
Test conditions: Idle mode entered executing code from on-chip flash; PCLK =
CCLK
⁄
4
; core voltage 1.8 V; all peripherals disabled.
Fig 16. Typical LPC2109/01, LPC2119/01, and LPC2129/01 I
DD(idle)
measured at different temperatures
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Single-chip 16/32-bit microcontrollers
1.95 V
1.8 V
1.65 V
002aad139
200
I
DD(pd)
(
μ
A)
160
120
80
40
0
− 40 − 15 10 35 60 temperature (
°
C)
85
Test conditions: Power-down mode entered executing code from on-chip flash.
Fig 17. Typical LPC2109/01, LPC2119/01, and LPC2129/01 core power-down current I
DD(pd)
measured at different temperatures
Timer0
Timer1
UART0
UART1
PWM0
I 2 C-bus
SPI0/1
RTC
ADC
CAN1
Table 8.
Typical LPC2109/01 peripheral power consumption in active mode
Core voltage 1.8 V; T amb
= 25
C; all measurements in
A; PCLK = CCLK ⁄
4
.
Peripheral CCLK = 12 MHz CCLK = 48 MHz CCLK = 60 MHz
103
9
6
16
43
46
98
103
33
230
341
37
27
55
141
150
320
351
128
764
407
53
29
78
184
180
398
421
167
914
LPC2109_2119_2129
Product data sheet
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Single-chip 16/32-bit microcontrollers
Timer0
Timer1
UART0
UART1
PWM0
I 2 C-bus
SPI0/1
RTC
ADC
CAN1/2
Table 9.
Typical LPC2119/01 and LPC2129/01 peripheral power consumption in active mode
Core voltage 1.8 V; T amb
= 25
C; all measurements in
A; PCLK = CCLK ⁄
4
.
Peripheral CCLK = 12 MHz CCLK = 48 MHz CCLK = 60 MHz
103
9
6
16
43
46
98
103
33
229
341
37
27
55
141
150
320
351
128
771
407
53
29
78
184
180
398
421
167
914
LPC2109_2119_2129
Product data sheet
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LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
Table 10.
Dynamic characteristics
T amb
=
40
C to +85
C for industrial applications; V
DD(1V8)
, V
DD(3V3)
over specified ranges.
Symbol Parameter Conditions Min Typ
External clock f osc oscillator frequency 1 supplied by an external oscillator (signal generator) external clock frequency supplied by an external crystal oscillator external clock frequency if on-chip PLL is used external clock frequency if on-chip bootloader is used for initial code download
1
10
10 -
-
-
T cy(clk) t
CHCX t
CLCX t
CLCH clock cycle time clock HIGH time clock LOW time clock rise time t
CHCL clock fall time
Port pins (except P0[2] and P0[3]) t r rise time t f fall time
I 2 C-bus pins (P0[2] and P0[3]) t f fall time V
IH
to V
IL
-
-
-
-
20
T cy(clk)
0.4
-
T cy(clk)
0.4
-
-
-
-
20 + 0.1
C b
-
10
10
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Bus capacitance C b
in pF, from 10 pF to 400 pF.
Max
50
30
Unit
MHz
MHz
25
25
-
-
-
-
5
-
1000
5 ns ns ns ns ns ns ns ns
MHz
MHz
LPC2109_2119_2129
Product data sheet
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Single-chip 16/32-bit microcontrollers
9.1 Timing t
CHCL t
CLCX
T cy(clk) t
CHCX t
CLCH
002aaa907
Fig 18. External clock timing (with an amplitude of at least V i(RMS)
= 200 mV)
LPC2109_2119_2129
Product data sheet
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NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
10. Package outline
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y
X
A
49
48 33
32 Z E
64
1 e pin 1 index b p
D
H
D w
M e
E
H
E w M b p
16
Z D
17 v M A
B v M B
A
A
2
A
1 detail X
L
L p
θ
0 2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
A max.
A
1
A
2
A
3 b p c mm 1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
D
(1)
E
(1)
10.1
9.9
10.1
9.9
e H
D
H
E
0.5
12.15
11.85
12.15
11.85
L
1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
L p
0.75
0.45
v
0.2
w y
0.12
0.1
Z
D
(1)
Z
E
(1)
1.45
1.05
1.45
1.05
θ
7 o
0 o
OUTLINE
VERSION
SOT314-2
IEC
136E10
REFERENCES
JEDEC JEITA
MS-026
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 19. Package outline SOT314-2 (LQFP64)
LPC2109_2119_2129
Product data sheet
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NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
11. Abbreviations
DCC
FIFO
GPIO
I/O
PLL
PWM
RAM
SPI
Table 11.
Abbreviations
Acronym
ADC
Description
Analog-to-Digital Converter
AMBA
APB
CAN
CPU
Advanced Microcontroller Bus Architecture
Advanced Peripheral Bus
Controller Area Network
Central Processing Unit
SRAM
SSI
SSP
TTL
UART
Debug Communications Channel
First In, First Out
General Purpose Input/Output
Input/Output
Phase-Locked Loop
Pulse Width Modulator
Random Access Memory
Serial Peripheral Interface
Static Random Access Memory
Synchronous Serial Interface
Synchronous Serial Port
Transistor-Transistor Logic
Universal Asynchronous Receiver/Transmitter
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Product data sheet
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Single-chip 16/32-bit microcontrollers
12. Revision history
Table 12.
Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC2109_2119_2129 v.7
20110614
Modifications:
Product data sheet 201004021F LPC2109_2119_2129 v.6
•
Table 6 “Static characteristics”
; Changed /01 Power-down mode supply current (I from 180
A to 500 A for industrial temperature range.
DD(pd)
)
•
Table 6 “Static characteristics”
; Moved V hys
voltage from typical to minimum.
•
Table 6 “Static characteristics”
; Changed I 2 C pad hysteresis from 0.5V
DD(3V3)
to
0.05V
DD(3V3)
.
LPC2109_2119_2129 v.6
20071210
Modifications:
Product data sheet LPC2109_2119_2129 v.5
•
Type number LPC2109FBD64/01 has been added.
•
Type number LPC2119FBD64/01 has been added.
•
Type number LPC2129FBD64/01 has been added.
•
Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP) and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) have been added.
•
Power measurements for LPC2109/2119/2129/01 devices have been added.
•
Description of JTAG pin TCK has been updated.
LPC2109_2119_2129 v.5
20070627 Product data sheet LPC2119_2129 v.4
LPC2119_2129 v.4
20060714 Product data sheet LPC2119_2129 v.3
LPC2119_2129 v.3
LPC2119_2129 v.2
LPC2119_2129 v.1
20041222
20040202
20031118
Product data
Preliminary data
Preliminary data
-
-
-
LPC2119_2129 v.2
LPC2119_2129 v.1
LPC2109_2119_2129
Product data sheet
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© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
13. Legal information
Document status
[1][2]
Objective [short] data sheet
Product status
[3]
Development
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
Definition
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com
.
13.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the
Product data sheet.
13.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
LPC2109_2119_2129
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2011 malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors
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Single-chip 16/32-bit microcontrollers
Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
14. Contact information
own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
I 2 C-bus — logo is a trademark of NXP B.V.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Product data sheet
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Single-chip 16/32-bit microcontrollers
15. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
LPC2109/2119/2129/01 devices. . . . . . . . . . . . 1
Key features common for all devices . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 10
Architectural overview . . . . . . . . . . . . . . . . . . 10
On-chip flash program memory . . . . . . . . . . . 10
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13
Pin connect block . . . . . . . . . . . . . . . . . . . . . . 14
General purpose parallel I/O (GPIO) and
Fast I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Features added with the Fast GPIO set of registers available on
LPC2109/2119/2129/01 only . . . . . . . . . . . . . 14
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LPC2109/2119/2129/01 only . . . . . . . . . . . . . 15
CAN controllers and acceptance filter . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.10 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.10.2 UART features available in
LPC2109/2119/2129/01 only . . . . . . . . . . . . . 16
C-bus serial I/O controller . . . . . . . . . . . . . . 16
6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.12 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 17
6.13 SSP controller (LPC2109/2119/2129/01 only) 17
6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.14 General purpose timers . . . . . . . . . . . . . . . . . 17
6.15 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 18
6.15.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.16 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . 19
6.16.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.17 Pulse width modulator . . . . . . . . . . . . . . . . . . 19
6.17.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.18 System control . . . . . . . . . . . . . . . . . . . . . . . . 20
6.18.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 20
6.18.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.18.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 21
6.18.4 Code security (Code Read Protection - CRP) 21
6.18.6 Memory mapping control . . . . . . . . . . . . . . . . 22
6.18.7 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.18.8 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.19 Emulation and debugging . . . . . . . . . . . . . . . 23
6.19.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 23
6.19.2 Embedded trace macrocell . . . . . . . . . . . . . . 23
6.19.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25
Static characteristics . . . . . . . . . . . . . . . . . . . 26
Power consumption measurements for
Dynamic characteristics. . . . . . . . . . . . . . . . . 39
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 41
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision history . . . . . . . . . . . . . . . . . . . . . . . 43
Legal information . . . . . . . . . . . . . . . . . . . . . . 44
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 44
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Contact information . . . . . . . . . . . . . . . . . . . . 45
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 June 2011
Document identifier: LPC2109_2119_2129
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