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The Programmable
Logic Company SM
Inside This Issue:
GENERAL
The Fawcett - Getting to the Core ... 2
Guest Editorial: The Defining Year .. 3
New Look, Content for WebLINX ... 6
Customer Success Story ...................... 7
Upcoming Events .................................. 8
New Product Literature ....................... 8
Financial Results .................................... 8
Technical Training Update ................. 9
1997 Spring Seminar Series ............... 9
PRODUCTS
XC4062XL Debuts .............................. 10
Faster XC4000E-1 FPGAs .................. 10
Product Discontinuance Update .... 11
Xilinx Receives QML Cert. ......... 12-13
XC5200 Breaks $4 Barrier ................ 13
DEVELOPMENT SYSTEMS
XACTstep M1 Software Released .. 14
XABEL-CPLD for Windows 95 ......... 14
Foundation v6.0.2 Service Pack ..... 15
ProSeries with Workview Office .... 15
OrCAD to Support Interface ........... 16
DSP Module Generator .................... 16
USB and PCMCIA AllianceCOREs . 17
AllianceCORE Partners Chart .......... 17
LogiCORE PCI Target ......................... 18
Virtual Computing XC6200 Kit ....... 18
HINTS & ISSUES
XC9500 Benchmarks .......................... 19
Trouble-Free Clock Switching .......... 20
Demultiplexing 200 MHz Data ...... 21
FPGA Highs and Lows ....................... 21
Using the HW-130 .............................. 22
Technical Questions & Answers ..... 23
Technical Support Resources .......... 23
Component Availability Chart ... 24-25
Programming Support Charts .... 26-27
Alliance Program Charts ............. 28-30
Development Systems Chart ........... 31
Fax Back Form ...................................... 32
X CELL
T H E Q U A R T E R L Y J O U R N A L F O R X I L I N X P R O G R A M M A B L E L O G I C U S E R S
Issue 24
First Quarter 1997
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GENERAL FEATURES
The Year that
Defines the Future
Marketing V.P. Sandeep Vij previews new product innovations for 1997 and beyond ...
See page 3
PRODUCT INFORMATION
XC4062XL FPGA Debuts
Shipments of the world’s highest-capacity FPGA begin ...
See Page 10
USB and PCMCIA
Cores Now Available
The first AllianceCORE products are released by CAE/Inventra and Mobile
Media Research...
See Page 17
Xilinx Earns QML Certification
Military/hi-rel product testing requirements reduced...
See Page 12
DESIGN TIPS & HINTS
More XC9500 CPLD
Benchmarks
New benchmarks illustrate the superior performance and pin-locking capabilities of the
FLASH-based XC9500 CPLD family ...
See Page 19
2
XCell
Please direct inquiries, comments and submissions to:
Editor: Bradly Fawcett
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Phone: 408-879-5097
FAX: 408-879-4676
E-Mail: brad.fawcett@ xilinx.com
©1997 Xilinx Inc.
All rights reserved.
XCell is published quarterly for customers of Xilinx, Inc.
Xilinx, the Xilinx logo, XACT,
FPGA Foundry, and NeoCAD are registered trademarks; all
XC-designated products,
HardWire, XACTstep,
LogiCORE, AllianceCORE,
Foundation Series, XABEL,
WebLINX, SmartSearch, and
EZTag are trademarks; and
“The Programmable Logic
Company” is a service mark of
Xilinx, Inc. All other trademarks are the property of their respective owners.
R
FROM THE FAWCETT
Getting to the Core
By BRADLY FAWCETT ◆ Editor
C ontinuing improvements to both fabrication processes and device architectures have led to dramatic increases in FPGA capacity and performance, as evidenced by the new XC4000EX family devices. Taking advantage of these increasing capabilities can pose formidable challenges to the user — challenges that cannot always be met by traditional gate-level design techniques, or even HDLs and synthesis-based design.
For many users, reusable intellectual property in the form of design
“cores” are becoming a key tool in meeting the twin challenges of increasing design complexity and shorter development cycles.
Simply put, cores are complex, pre-designed and reusable functional blocks, typically hundreds to thousands of gates in size, that can be included as part of a larger FPGA design. Cores can be developed internally
(for example, re-used portions of previousgeneration designs) or purchased as intellectual property from the FPGA vendor or a third-party provider.
The main benefit of cores is the decreased development time and effort associated with using a pre-designed, proven function.
Designers can focus their efforts on the proprietary portions of their designs, rather than
“re-inventing” a standard function.
Xilinx is committed to the development of a broad selection of cores optimized for use in
Xilinx devices. We are fulfilling that commitment in two ways — through the internal development of our own core products, called
LogiCORE TM modules, and by partnering with leading third-party core developers through the Xilinx AllianceCORE TM program. The goal is to allow Xilinx FPGA users to act as system integrators, easily combining proven functional blocks with the proprietary logic of the particular application.
To date, the Xilinx LogiCORE PCI Interface has been the most-successful core-based product in the programmable logic industry.
With its combination of logic complexity and strict performance requirements, the PCI interface also is one of the most-challenging designs ever to be placed in an FPGA core. We are now using the considerable experience that we gained in developing, selling, and servicing the PCI interface to improve future
LogiCORE products and shape our relationships with third-party core developers.
Two of the most-important lessons that we learned are (1) cores should be fullyoptimized for the target FPGA architecture, and (2) cores must be delivered to the user as part of a complete product solution.
Some third-party ASIC core vendors are seeking to expand their potential market by re-targeting their “generic” HDL code to various FPGAs. However, with such an HDLbased core, there is little guarantee that the physical implementation will be optimal for the target FPGA architecture. The utilization levels and performance will vary dependent on the efficiency of the synthesis tools and how the core is combined with adjacent logic.
The time and effort spent in overcoming these problems can quickly eliminate the time-tomarket advantage that initially motivated the use of a core.
In contrast, cores optimized for the target
FPGA can use all the available features of the architecture, such as dedicated arithmetic carry logic, internal three-state buffers, and on-chip memory, to achieve optimal logic utilization. Placement and timing constraints, used in conjunction with re-entrant, timingdriven ‘place and route’ tools, result in predictable and optimized performance levels.
However, there is much more to delivering a core-based solution than just supplying the
GUEST EDITORIAL
1997
The Year That
Defines the Future
by SANDEEP VIJ ◆ Vice-President, Marketing
I n 1985, Xilinx introduced the world’s first FPGA device, creating an important new product category in the semiconductor industry. Since then, a steady stream of new, innovative component and development system products has allowed Xilinx to grow into the industry’s leading supplier of programmable logic.
In 1997, the pace of innovation will increase. By aggressively applying architectural improvements and the latest process technologies, Xilinx will be setting new standards for FPGA capacity, performance, and cost-effectiveness. All 10 members of the new XC4000XL family will be available by mid-year. Based on 0.35 µ technology, this family provides usable logic gate densities ranging from 5,000 to
85,000 gates (about 500 to 7,500 “logic cells,” where a logic cell consists of a
4-input look-up table and a register). These are true “logic gates,” not the “combined logic and memory gates” metrics used by others to inflate their gate counts.
By mid-year, we expect to be sampling the first FPGA based on a 0.25 µ process, and we will be working with 0.18 µ technology by year-end. Our next-generation architecture also should be available by year-end, and is projected to reach densities of over 30,000 logic cells (about 400,000 logic gates) in 1998. Of course, correspondingly faster speed grades also will be introduced, reaching true 100 MHz chip-to-chip performance later this year. Our next-generation of place and route tools will support these new offerings.
The XC5200 series FPGAs also will be migrated to a 0.35 µ process this year.
Die sizes for these cost-optimized devices will shrink to the point where they are “pad limited”; that is, the die size is constrained by the number of I/O pads
❝Xilinx
will be setting new
required, not the logic gate density. When this occurs, traditional gate arrays will have no die size advantage and, therefore, no cost advantage over FPGAs.
Lower FPGA costs will open new markets to programmable logic devices in applications such as Internet applicances, PC add-in cards, consumer electron-
standards for FPGA capacity, performance, and cost-effectiveness.
❞ ics, automotive electronics and large household appliances.
The Xilinx CPLD product lines will benefit equally from aggressive process migration this year. The industry has adopted FLASH memory technology as the mainstream floating-gate technology, facilitating the migration of the FLASH-based XC9500 family down the process curve. Xilinx CPLDs will continue to be the lowest-priced in the industry, while offering the best routability and pin-locking capabilities of any available CPLD.
Optimizing the Process
Advanced process technology is critical to providing leading-edge performance, density and cost-effectiveness. Xilinx is firmly committed to always having and using the most advanced IC fabrication processes available. One of the major advantages of being a
“fabless” semiconductor company is the ability to form manufacturing partnerships with the process leaders at any point in time. An in-house staff of process engineers allows Xilinx to work with our fabrication partners to quickly bring new processes on-line.
R
3
4
GUEST EDITORIAL
Continued from the previous page
Rapidly shrinking device geometries will require the use of smaller supply voltages.
The leading semiconductor foundries are eager to use Xilinx FPGAs to drive their process development. The regularity and testability of our FPGA architectures facilitates defect analysis and fault testing. With their large transistor counts (the XC4062XL device has about twice as many transistors as the Intel Pentium Pro processor), FPGAs are a very good “test vehicle” for the most-advanced fabrication lines.
The Voltage Staircase
In order to reap the benefits of advancing process technology — increased performance, increased density, lower power consumption and lower price — users must be willing to migrate their designs down the “voltage staircase.” The graph shows how CMOS process technology has improved from 1.2 µ design rules in 1990 to today’s 0.5 µ processes, while maintaining 5 volt logic levels. As geometries shrink below 0.5 µ, the smallest transistors cannot withstand 5 volts without damage. This leads to the voltage levels shown in the graph, with each successive process generation using a smaller supply voltage.
Xilinx is taking an active lead in working with our users to plan an orderly migration from one voltage standard to the next. A major part of our migration strategy is to maintain I/O compatibility across multiple generations. For example, all of the 3.3 V products in the
XC5200L and XC4000XL families have I/O structures that are fully 5 V compatible — accepting full 5 V signals on all I/Os and being able to drive TTL-like levels into any 5 V devices. Even our future 0.25 µ, 2.5 V components will employ split I/O and core power supplies to maintain I/O compatibility with either 5 V or 3.3 V devices.
This is not meant to imply that Xilinx will discontinue production of 5 V devices anytime soon. Although we encourage our users to migrate their designs to the lower voltage standards as these new products become available, we recognize that designs based on the 5 V standard will continue in production for many years to come, and we remain firmly committed to supporting those designs.
Complete Solutions
Users require complete solutions that meet their logic requirements, not just the biggest or fastest device. We realize that programmable logic solutions consist of a combination of many elements, including device architecture, device packaging, EDA interface software, synthesis software, place and route implementation software, pre-designed cores, sales support, and technical support. We intend to continue to lead the market in all these areas.
In summary, Xilinx will be releasing a formidable array of new products in the coming year. These will include:
• The industry’s highest-density FPGAs
• The fastest FPGAs
• The first full family of FPGAs available for
3.3 V systems
• The first FPGAs using a 0.25 µ process
• The next major release of the Xilinx development software
• A broad offering of pre-designed cores
• The introduction of the next-generation
FPGA architecture.
This will set the stage for the next five years, during which FPGA speeds are expected to increase five-fold, and FPGA densities will increase to 150,000 logic cells
(2 million logic gates).
◆
THE FAWCETT (con’t) core’s design netlist. Potential users should also consider three other main factors that lead to a “complete” solution: silicon, software, and service.
Core-based designs are most appropriate for high-density FPGAs with a rich feature set.
FPGA device features such as flexible clocking, numerous and flexible output enables, on-chip memory capability, and on-chip three-state bussing are critical to the implementation of system-level solutions. Broad product families, such as the Xilinx XC4000 series, allow the choice of the most-appropriate device for a given application.
The FPGA development environment must support the appropriate design entry, synthesis, implementation, and verification tools needed for the particular core design. The methodology and tools used to pre-define the implementation of critical paths, such as placement and timing constraint files or guide designs, should be well-understood. Where appropriate, simulation models and test benches should be part of the package supplied to the user, thereby facilitating the verification of the completed design. System software and prototyping equipment also may be required to ease the rapid integration of a core into a complete design.
To ensure the productivity gains that motivated the use of a core, extensive documentation and application support must be available.
Of course, the degree of support required for core integration is often proportional to the complexity and flexibility of the core.
Recognizing these needs, the LogiCORE and AllianceCORE programs are emphasizing quality over quantity. For example, we are taking an active role in working with our
AllianceCORE partners in the process of
“productizing” their cores. A core must meet a minimum set of criteria before it can receive the AllianceCORE label, in terms of “sensibility,” format, and completeness.
First, the core must “make sense” — it must provide value over an ASIC or standard product version of the same function, and be costeffective when implemented in a Xilinx device.
We are not interested in promoting generic, synthesizable functions as AllianceCORE prod-
Continued from page 2 ucts. The core must be optimized for the target Xilinx FPGA architecture and be delivered as a parametizable “black box” that allows needed customization in critical areas.
Timing-critical cores designed to adhere to an industry standard (such as PCI and USB bus interfaces) must be supplied with the appropriate constraints files in order to guarantee functionality and compliance.
The core must be packaged as part of a complete product, including adequate documentation, the availability of technical support, and, where appropriate, additional elements such as test benches, simulation models, and prototyping equipment.
Xilinx recently announced the availability of the first AllianceCORE products, USB modules from CAE/Inventra, and PCMCIA modules from Mobile Media Research
notable that their offerings include
❝ T
he intention
is to provide our users with complete
important system integration tools such as simulation models and
solutions that preserve the value of using Xilinx programmable logic devices, as
prototyping boards.
17 lists the partners that are currently
opposed to just filling pages in a catalog of products by promoting the use of generic
developing products under the
AllianceCORE program; expect future
cores developed for other technologies.
❞ additions and deletions to this list as we discover which providers can meet our stringent quality criteria.
Of course, this emphasis on complete, optimized solutions and our high level of involvement will limit the number of partners that we can work with at a given time and, subsequently, the number of available
AllianceCORE products. Again, the intention is to provide our users with complete solutions that preserve the value of using Xilinx programmable logic devices, as opposed to just filling pages in a catalog of products by promoting the use of generic cores developed for other technologies.
◆
5
6
New Look, More Content for WebLINX www.xilinx.com
V isitors to WebLINX, TM the Xilinx home page on the World Wide Web, will have noticed its new look and feel. Designed to provide users with quick, easy and intuitive access to the desired information, the home page features a “virtual desktop,” complete with labeled icons for direct links to the site’s various sections. Fewer steps are required to get to information.
WebLINX holds a wealth of Xilinx information, but SmartSearch TM , our industry-wide search engine, goes a step further. The definitive resource for all Programmable Logic information on the web, SmartSearch indexes and connects you to more than 50 PLD-rich web sites. SmartSearch Agents will watch the
Web for you and inform you via e-mail when new or updated information is added to any of the sites served by SmartSearch.
New information is constantly being added to WebLINX. Technical information on the site now includes:
➤ More than 60 application notes organized by system type (e.g., PCI, DSP, and
PCMCIA), function (e.g., memory functions, arithmetic functions, and busses), component product family and application.
➤ Complete and detailed datasheets on all
Xilinx products.
➤ Hundreds of records in our technical answers database
➤ Xilinx product change notices and customer updates
➤ Access to back issues of XCell
➤ Software updates and patches
➤ Links to technical Xilinx presentations via Marshall Electronics
NetSeminar™ archives.
So visit WebLINX and stay abreast of the latest developments from Xilinx, the industry’s leading supplier of programmable logic.
◆
CUSTOMER SUCCESS STORY
Xilinx CPLDs Satisfy High-Speed Processing Needs
T ranstech Parallel Systems Ltd. (High
Wycombe, United Kingdom) designs and manufacturers a wide range of embedded multi-processing products for OEM, end-user and scientific research applications. Specializing in meeting the needs of demanding highperformance, high-bandwidth applications,
Transtech’s products include every state-ofthe-art microprocessor available today.
For example, three new board-level products are based on the 200 MHz PowerPC
603eV and 604eV processors: two TSP family
VMEbus boards, and the TTM610 board featuring the popular TRAM format. The TTM610
TRAM module combines the PowerPC processor with a T805 transputer and up to 32
Mbytes of high-speed Synchronous DRAM
(SDRAM), and is tailored for scalable, highperformance multi-processor solutions. Shared
SDRAM memory is used for inter-processor communication
To take full advantage of these high-performance processors and memories, equally high-performance interface logic was required.
This need, coupled with fast time-to-market requirements, led Transtech engineers to the
Xilinx XC7300 and XC9500 CPLD families.
To support the fastest possible memory cycles, two XC7336-5 CPLDs were selected for implementing high-speed memory decode circuits on the TTM610 board. The XC7336 device was the only available CPLD that could perform the necessary decoding functions while maintaining a pin-to-pin delay of just 5 ns.
Two 108-macrocell XC95108-10 CPLD devices hold the more complex, highspeed state machine functions within the processor/memory interfaces. With an aggressive development schedule that dictated the parallel design of the logic and the PCB layout, the pin-locking capabilities of the
XC9500 architecture proved crucial. In the words of Transtech design engineer Hugh
Tarver, “The increased routability of the Xilinx
XC95108 CPLD enabled a number of logic design iterations to be completed without the risk of the XC95108 changing its pinout assignment. This enabled us to complete our transputer board design quickly and without
PCB modification.”
A further attraction of the XC95108 CPLD was its in-system-programming capabilities.
High-density packaging was required for the densely-populated TTM601 and TSP boards.
In-system-programming eliminated the extra handling of the 100-pin PQFP packages that would have been required if an external programmer were used.
Multiple XC7336 and XC95108 CPLDs implement similar high-speed processor-tomemory and processor-to-processor interfaces on the TSP family VME boards, which feature up to four PowerPC processors per board. All the CPLD designs were developed using the
Xilinx XABEL-CPLD TM software package on a
PC platform.
High-speed systems need high-speed logic.
The combination of the high performance and flexible, highly-routable architectures of the
Xilinx CPLD devices were essential to meeting the needs of Transtech Parallel Systems’ new
PowerPC-based, high-performance multiprocessing systems. ◆
T R A N S T E C H
7
8
New
Product
Literature
L earn about the newest Xilinx products and services through our extensive library of product literature. The most recent pieces are listed below. To order or to obtain a complete list of all available literature, please contact your local Xilinx sales representative.
◆
DESCRIPTION NUMBER TITLE
Corporate
AppLINX CD
Xilinx Educational Services & Course Brochure
CPLD
ISP Applications Guide
HardWire
HardWire Data Book
Technical Data
Technical Date
Technical Data
#106425-03
#0010134-06
#0010290-02
#0010164-03
UPCOMING EVENTS
L ook for Xilinx technical papers and/or product exhibits at these upcoming industry forums.
For further information about any of these conferences, please contact Kathleen Pizzo
(Tel: 408-879-5377 FAX: 408-879-4676).
◆
11th International
Parallel Processing
Symposium (IPPS)
(Reconfigurable Architectures Workshop)
Apr. 1-5
Geneva, Switzerland
PCI Plus ’97
April 13-18
Santa Clara, California
5th Annual IEEE
Symposium on
Custom Computing Machines
(FCCM)
Apr. 16-18
Napa, California
DSP World
Mar. 25-26
Washington, DC
The Advanced PLD
& FPGA Conference
May 13-14
London, UK
The Advanced PLD
& FPGA Conference
May 20
Stockholm, Sweden
Design Automation Conference
June 9-13
Anaheim, California
Xilinx Inc.
stock is traded on the NASDAQ exchange under symbol XLNX.
FINANCIAL RESULTS
Quarterly Revenues Up 4%
X ilinx sales revenues for the
December-ending quarter increased 4%
From a product viewpoint, revenues from the XC5200 FPGA family increased sequentially to $135.6 million, but were 45% to comprise 8% of total revenue. The down 6% compared to the same quarter new XC9500 in-system-programmable one year ago.
CPLD family contributed its first $1 million
International revenues grew to comin revenues. Development system revprise 38% of total sales. Both Japan and enues increased 13% sequentially, and, for the Asia-Pacific region posted sales revthe second quarter in a row, the number enue increases of more than 15% compared to the previous quarter.
of installed development system seats increased by nearly 1,400 units.
◆
TECHNICAL TRAINING UPDATE
XACTstep M1 Course Available
A
new training course using XACTstep TM
M1, the new release of the Xilinx development system, is now available at the regional level and at Xilinx headquarters in San Jose,
Calif. M1 integrates the best of the Xilinx and
Neocad tools into a new tool set (see page 14).
The currently released M1.1, a version that is workstation-based and emphasizes the
XC4000EX FPGA family, makes the course most appropriate for designers using
XC4000EX devices. General availability of the M1-based course will coincide with the upcoming M1 software release; check the next issue of XCell for updates on M1 training courses.
VHDL Courses
VHDL workshops and seminars continue to be in great demand. In North America, twoday workshops, sponsored by distributors
Marshall, Hamilton-Hallmark, and Insight use
Foundation TM tools and Xilinx devices for lab exercises. A Xilinx-sponsored one-day seminar for new VHDL users stresses the basics of the language. Contact your local Xilinx representative or distributor to ask about VHDL workshops and seminars in your area.
The entire training course schedule, including schematic- and synthesis-based courses and VHDL seminars, is available on
WebLINX (www.xilinx.com).
◆
Xilinx 1997 Seminar Series
Coming Soon to a Location Near You
X ilinx technical seminars provide an easy way to learn about the latest programmable logic technologies to carry your designs through the ‘90s and beyond. Sessions are planned for May and June in more than 40 cities worldwide. Presented by members of the
Xilinx technical support staff, the program covers solutions for all phases of the design cycle, including:
➤ An evaluation of logic alternatives
➤ Estimating design needs
➤ Design implementation and optimization techniques
➤ Getting the most out of Xilinx programmable logic devices
Several new Xilinx products will be highlighted, including the XC4000EX FPGA family, the XC9500 CPLD family and LogiCore TM drop-in modules. Each segment of the program will be supported by actual applications examples. In addition, hands-on demonstrations will enable you to operate the newest versions of our Foundation TM and Alliance TM series development tools.
Watch For Your Personal Invitation!
Invitiations for the 1997 Xilinx seminar series will be mailed directly to everyone on the XCell mailing list. You can respond by registering to attend a seminar via
WebLINX (www.xilinx.com), phone, fax, e-mail or reply card. If your invitation does not arrive or you would like information, contact your sales representative or visit
WebLINX.
◆
9
10
PRODUCT INFORMATION-COMPONENTS
XC4062
XL
Debuts:
Xilinx Extends High-Density
FPGA Leadership
I n January, Xilinx began sampling the XC4062XL FPGA device, currently the world’s highest-capacity FPGA. Xilinx has shipped more than $90 million worth of high-density FPGAs over the past
12 months, more than all competitors combined.
The XC4062XL device, the largest available member of the
XC4000XL family, is manufactured on an advanced 0.35 µ process and operates at 3.3 volts. It contains 2,304 CLBs (5,472 logic cells).
Logic cells are fast becoming the industry-standard metric for comparing densities of SRAM-based FPGAs. A logic cell is defined as the combination of a 4-input look-up table (LUT) and a dedicated register that reside in the same block, such that the output of the LUT can be the data input to the register.
The majority of FPGAs in use today are SRAM-based FPGAs whose logic blocks are based on a combination of memory lookup tables (LUTs) and dedicated registers. Thus, logic cells are a more direct and objective capacity metric than gate counts. Each
XC4000 CLB, with two 4-input LUTs, one 3-input LUT, and two registers, is equivalent to 2.375 logic cells.
The XC4062XL is available in 560-pin ball grid array (BGA),
475-pin pin grid array (PGA) and 240-pin high performance quad flat pack (HQFP) packages.
◆
Faster XC4000E-1 FPGAs Support High-
Performance Applications
O nce again, continuing process improvements have led to the release of a new, in the 80 MHz range — about 20% higher performance than the XC4000E-2 FPGAs. The faster speed grade for the XC4000E
FPGA family. Devices with the new
-1 speed grade are expected to start sampling in March and enter full production in
June.
Based on an optimized 0.5 µ
Max. System Speed =
1/(Clock-to-Out + Global Set-Up) three-layer-metal process, the new -1 rated devices support typical system clock speeds
XC4000E-1 devices are applicable to a wide range of highdensity, highperformance applications, such as
PCI bus interfaces, fast ATM switches and video processing.
For pricing and availability information, please contact your local Xilinx sales representative.
◆
R
Product Discontinuance Policy Update
T he Xilinx Product Discontinuance Policy provides for the early notification of future product changes and discontinuances, generous last-time buy periods, and relationships with end-of-life suppliers. Refer to page 14 in
XCell 23 for information about the development of the policy.
“End-of-Life” Supplier Selected
Xilinx has selected Rochester Electron-
ics, Inc. (REI) as “end-of-life” supplier for
Xilinx discontinued products. REI is the industry leader in after-market support for semicondutor suppliers. Our relationship with
REI will provide for product availability beyond the Xilinx last-time-buy and last-timeship periods. REI also provides capabilities such as assembly and test. Contact REI at its
Newburyport, MA headquarters by phone at
508-462-9332, by e-mail at [email protected], or on the internet at www.rocelec.com.
However, higher-performance XC3000 series devices are getting less expensive. The most recent price reductions for the XC3000-
100 and XC3100A-4 devices have eliminated the need for the XC3000-70 and XC3100A-5 devices, so we are dicontinuing the C and I grades of those two devices. Users of these discontinued products can now move to the next-highest speed grade, maintaining pin and bitstream compatibility, and take advantage of decreased component costs.
For further information about these products, including a complete list of the ordering codes for the discontinued products, please contact your local sales office or visit the
Xilinx WebLINX website.
◆
Product Discontinuance Schedule
XC2000 Shipments to End in 1999
On December 20, 1996, Xilinx issued
Product Discontinuance Notification
PCN96010 for the XC2000 FPGA family. Included in the discontinuance are all commercial, industrial, military and hi-rel products.
The last-time-buy period extends until January 1, 1999 (see table).
The XC2000 devices, first introduced in
1985, can be replaced by more cost-effective
FPGA and CPLD product families, such as the
XC5200, XC7300 and XC9500 families, or by their HardWire TM equivalent, the XC2318.
MILESTONE
XC2000 Product Line Discontinuance
Notification
Last-time-buy
Last-time-ship
12/20/96
1/1/99
6/30/99
XC3000 -70 (C and I) Discontinuance
Notification
Last-time-buy
Last-time-ship
XC3000 Low Volume Packages
Notification
Last-time-buy
Last-time-ship
DATE
1/31/97
1/31/98
4/30/98
1/31/97
12/31/98
3/31/99
NOTES
PCN96010
PDN97003
PDN97005
XC3100A -5 (C and I) Discontinuance
XC3000 Series Product
Line Streamlining
We plan to improve our leadtimes by removing device and package combinations with extremely low order volumes. A few
XC3000 series components, mostly slower speed grades and unpopular pin grid array package combinations, will be discontinued within the next two years.
Notification
Last-time-buy
Last-time-ship
XC3100A Low Volume Packages
Notification
Last-time-buy
Last-time-ship
1/31/97
1/31/98
4/30/98
1/31/97
12/31/98
3/31/99
PDN97004
PDN97006
11
12
Xilinx Receives QML Certification
T he Defense Supply Center Columbus
(formerly DESC) has awarded Xilinx transitional certification to MIL-PRF-38535 Qualified
Manufacturer Listing (QML). As with our ISO
9000 certification, QML demonstrates our status as a proven, world-class supplier of programmable logic.
About the QML Program
The QML program involves the certification of a quality and manufacturing system applicable to both military and commercial products — a “dual-use” system. Developed in 1988 at the direction of the Defense Science Board, QML calls for the use of “best commercial practices” for manufacturing and testing, allowing the supplier to optimize the manufacturing, assembly, screening and test flows. The QML certification is basically a validation that the company is well-managed and technically sound enough to be “world class” with minimal government interference. As acceleration tests, and full electrical testing both before and after a “burn-in” period.
These requirements apply to all products that we supply as SMD-qualified; each indi- vidual product is subject to the standard’s screening and qualification requirements.
The QML program works to ensure the same high quality levels as MIL-STD-833 without all of its onerous testing requirements.
The QML program focuses on the generic qualification of an envelope of processes and materials, rather than individual products. It allows for the use of pertinent existing military and commercial reliability data, statistical process controls (SPC), and in-process monitors. In short, the QML program encourages the use of the “best commercial practices” that are commensurate with military performance, quality and reliability.
a result, we have greater flexibility in controling the ways that we qualify, manufacture and test our military products.
Suppliers new to the QML program, such as Xilinx, are awarded “transitional” certification as they move from MIL-STD-883 to QML.
It is our target to achieve full QML status before the end of 1997, but we will begin operating as a QML supplier immediately.
QML and MIL-STD-883
Xilinx has been qualified to MIL-STD-883 since 1988, and we have been a very active supporter of the Standard Microcircuit Drawing (SMD) Program. Under MIL-STD-883, we have been operating under a system that specifies the manufacturing requirements for our military products. For example, these requirements include temperature cycling and
Benefits of the QML Program.
The benefits of being a QML supplier are significant, both to Xilinx and our users.
➤ More Rapid Product Introductions —
Historically, the MIL-STD-883 standards have caused a significant time lag between the release of new commercial products and their military/hi-rel versions. Under
QML, this time lag will be greatly reduced, if not eliminated entirely.
➤ Improved Manufacturing Efficiency —
Since we now have the ability to begin optimizing military screening previously mandated by MIL-STD-883, we will become a more efficient and cost-effective supplier to the military/hi-rel market.
➤ Access to Military Programs Requiring
QML Product — There are some military programs that require the use of QML parts. Xilinx programmable logic solutions will now be available for those programs.
➤ Greater Access to New Markets —
Since the QML program is based on the concept of “best commercial practices,” the opportunity exists for Xilinx to explore the possibilities of using commercial pack-
aging technology (i.e., plastic packages) for use in high-reliability applications.
More work is required in this area, but we now have the basis for evaluation.
How the program will be implemented
Our QML certification encompasses manufacturing and test processes at Xilinx,
Seiko-Epson (wafer fabrication) and Anam
Philippines (assembly). Consequently, all of our current Standard Microcircuit Drawing
(SMD) products will be immediately transitioned to QML. We will begin marking our SMD parts with a “Q” to indicate QML.
SMD documents will be updated to reflect our
QML status. The SMD program will continue
— as we introduce new products, they will be included in the SMD program as QMLcertified, rather than MIL-STD-883 certified.
Because many of the new products that we intend to introduce for the military/hi-rel market will be produced at another foundry,
United Microelectronics Corp. (UMC), it is our intention to seek QML certification for this facility by the end of 1997.
While other manufacturers are abandoning their military/hi-rel users, the participation of Xilinx in the QML program is one more demonstration of our strong commitment to support military and high-reliability applications, as well as a testament to the quality of
Xilinx processes and products.
◆
XC5200 Family Breaks The
$ 4
Price Barrier
FPGA benefits now available to consumer and high-volume markets
X ilinx shipped the millionth unit of the XC5200 FPGA family in the fourth quarter of 1996. The XC5200 family reached this milestone faster than any previous FPGA product family.
As one result of the migration of this family to 0.5 µ three-layer-metal process technology, Xilinx has significantly reduced component die sizes, leading to dramatically reduced prices. In fact, Xilinx has introduced the world’s first FPGA for less than $4. The direct price for the 256-logic-cell XC5202-6PC84C is now $3.95 (in 25,000 piece quantities).
The migration of the family to the 0.5 µ process has resulted in a “pad-limited” die size; that is, a die size limited by the number of I/O on the device, not the amount of logic.
This, in turn, leads to production cost parity with low-end gate arrays. As a result, highvolume products can now achieve their cost and margin targets while obtaining all the traditional benefits of FPGA technology, including design flexibility and off-the-shelf availability. The XC5200 family is now the ideal logic solution for consumer and other high-volume products that require both low cost and fast time-to-market, such as set-top boxes, PC add-in cards, cable modems, and digital cameras.
With five XC5200 family devices ranging from 2,000 to
23,000 maximum logic gates in 15 different packages, there are now over
100 different device/ package/speed combinations available to meet your exact design requirements, all at very affordable prices.
◆
13
PRODUCT INFORMATION-DEVELOPMENT SYSTEMS
14
New XACTstep M1 Software for High-Density Design
X ilinx has begun shipments of the first version of its new XACTstep TM M1 software, geared for high-density XC4000EX/XL applications. This software solution delivers unprecedented speed, utilization, and run-time performance for high-density FPGA designs.
XACTstep M1.1 includes a new generation of core implementation applications, including mapping, optimization, timing-driven placement and routing, and timing analysis programs. This state-of-the-art software environment builds on technology from the Xilinx
XACT TM and NeoCAD FPGA Foundry TM design systems to deliver high-performance with intuitive, easy-to-use design tools. Key features of this system include:
➤ Multi-level design support, with automatic netlist translation and integration
➤ A comprehensive timing-constraint language (Timespecs), with automatic links to synthesis tools
➤ Advanced, timing driven-placement and routing, with both push-button flows and auto-interactive capabilities
➤ Superior pin-locking and incremental design capabilities
➤ 100% back-annotation, with EDIF,
VITAL and Verilog/SDF back-annotation interfaces
Designer feedback on this software has been very positive. One user who targeted a
90%-utilized XC4028EX device stated, “The
M1 software is very easy to use with very little tweaking and no hand assist. The power of Timespecs made the timing constraints very simple to meet and verify.”
XACTstep M1.1, available for Solaris,
SunOS, and HP UNIX platforms, includes libraries and interfaces for Synopsys, Mentor
Graphics, and Viewlogic design environments. Future releases will provide EDA interface and Windows NT/95 support, as well as integrated solutions for the XC9500 and XC7300 CPLD families, the XC4000 and
XC5200 FPGA series, and the XC3000A family.
XACTstep M1.1 is being provided now to selected users known to have high-density
FPGA designs in progress. All XACTstep users with active maintenance contracts will be upgraded to this new version around midyear. Please contact customer service to renew or check the status of your software maintenance agreement.
◆
XABEL-CPLD Available for Windows 95 and 3.x
X
ABEL-CPLD TM v6.1.2 now executes on both Windows 95 and Windows 3.x
platforms. Existing XABEL-CPLD users can receive a free update upon request through normal Xilinx Customer Service channels.
The update includes new
EZTAG TM download software, but no cable.
◆
PRODUCT NAME
XABEL-CPLD v6.1.2
XABEL-CPLD v6.1.2 Update
PART NUMBER
DS-571-PC1
SC-571-PC1-CU
PRICE
$495
No charge
R
Update Your Foundation Software with the v6.0.2 Service Pack
X ilinx is pleased to offer all registered Foundation TM users an update to their current software. The new Foundation Service Pack updates your v6.0.1
software to v6.0.2. Shipments of this update to all registered Foundation owners began in February. To speed the distribution process, Foundation package owners are urged to register their software licenses if they have not already done so.
The v6.0.2 update includes numerous improvements to this integrated package of schematic entry, simulation,
VHDL synthesis, and programmable logic implementation tools. A sampling of some of the enhancements are listed in the table. Foundation owners who have not yet received this update can download the files from the Xilinx FTP site or bulletin board, or call their Xilinx Customer Service representative to request the service pack CD.
Sampling of Foundation v6.0.2 improvements:
Schematic
✓ New design rule checker
✓ Improved bus connectivity and naming
✓ New schematic generation tool
✓ Wired schematic creation from XNF or ABL files
✓ Improved importing capability for Viewlogic schematics and symbols
✓ More user-friendly query/find feature
✓ More flexible symbol editor
Simulation
✓ Better Viewlogic simulation command language compatibility
✓ More intuitive graphical user interfaces
✓ Improved functionality in waveform viewer
✓ Context-sensitive help
Synthesis
✓ New graphical user interface status information
✓ Improved macrocell usage for comparators, adders, subtractors and up-down counters
✓ New documentation on compilation methodology
✓ Improved and more verbose information in error messages ◆
ProSeries
Users
Upgraded with
Workview
Office
V iewlogic started shipping versions 7.12 and 7.2 of Workview Office to in-warranty
Xilinx ProSeries TM users in December (to be completed by the end of 1Q97). Workview
Office 7.2 can be installed under Windows 95 or NT. However, Xilinx and Viewlogic have tested the integration of the Viewlogic toolset with the XACTstep TM development system on Windows 95 only, not Windows NT.
Xilinx will be shipping the next version of Workview Office, version 7.3, with the next major XACTstep release later this year. In version 7.3, the Viewsynthesis optimizer will be significantly enhanced, including 100% Synopsys language compatibility.
If you are currently an in-warranty ProSeries owner and have not received your free upgrade to Workview office, please contact Viewlogic via fax (508) 481 3961 or e-mail [email protected]. For any technical questions please contact Xilinx technical support.
◆
15
16
OrCAD to Provide Support for
OrCAD-Xilinx Interface
F or several years, Xilinx has developed, distributed and supported products that allowed OrCAD users to seamlessly interface their schematic designs with Xilinx devices.
Due to OrCAD’s growing reputa-
❝It has
become evident that
tion for offering quality program-
OrCAD is in the best position to offer
mable logic solutions, it has be-
support for designers wishing to use
come evident that
OrCAD is in the
OrCAD products with Xilinx devices.❞
best position to offer support for designers wishing to use OrCAD products with
Xilinx devices. As always, OrCAD and Xilinx will continue to work together so that designers can take advantage of the powerful features of OrCAD’s solutions and the latest advancements in Xilinx devices.
With our users’ best interests in mind,
Xilinx and OrCAD have jointly agreed to the following:
➤ The new recommended OrCAD/Xilinx solution consists of OrCAD FPGA Designer
Pack (including OrCAD Capture and
Simulate for Windows) for schematic entry, functional simulation, and timing simulation. All Xilinx schematic libraries, simulation models and the XNF interface are included in the FPGA Designer Pack. Only the “back-end” implementation (place and route) tools need to be acquired from
Xilinx. The new design flow is very straightforward: from OrCAD Capture, generate an XNF file that is input into the
XACTstep TM tools for physical implementation; the post-routed XNF file is then input to OrCAD Simulate for post-route timing simulation.
COMING SOON:
DSP Module Generator
T he key to high-performance, FPGA-based digital signal processing is to craft the DSP algorithm for efficient implementation in the target FPGA architecture. Ironically, many DSP designers, while well-versed in the algorithmic approaches suitable for programming commercially-available digital signal processors, are not familiar with distributed arithmetic and similar techniques applicable to the hardware structures of FPGA devices.
To aid designers in implementing optimized DSP designs, Xilinx is developing a library of module generators for DSP functions, targeted for the XC4000 FPGA architecture. The production version of the Xilinx DSP Module Generator will be available in July. The first release includes modules to generate customized implementations of FIR filters, comb filters, integrators, multipliers, square root functions and various basic DSP building blocks. The tool outputs logic implementations compatible with the Xilinx implementation tools, behavioral models for simulation, instantiation code and schematic capture symbols. Additional modules will be available as plug-ins on an on-going basis.
For further information, see WebLINX (www.xilinx.com).
◆
➤ Starting with the next XACTstep release,
Xilinx will transfer development and support to OrCAD for the OrCAD/Xilinx Kit
(DS-35), the Base System with OrCAD
Interface package (DS-OR-BAS-PCI-C), and the Standard System with OrCAD Interface package (DS-OR-STD-PCI-C). (These packages include OrCAD’s SDT386+ schematic capture tool and VST386+ simulation tool.
SDT386+ and VST386+ have been replaced by Capture and Simulate for Windows, respectively.) Xilinx will no longer provide direct support for the OrCAD products.
We anticipate a very smooth transition. However, if you need any assistance, please contact your account manager or call OrCAD at 800-671-9505.
◆
USB and PCMCIA
AllianceCOREs
Now Available
T he first products in the AllianceCORE TM program are now available:
• Cores for Universal Serial Bus (USB) applications from CAE/Inventra, Inc., and
• Cores for PCMCIA card design from Mobile Media Research, Inc.
The AllianceCORE program is a cooperative effort between Xilinx and independent third-party developers, with the goal of providing a broad selection of industry-standard cores that are optimized and verified for
Xilinx programmable logic devices.
Universal Serial Bus
The USB AllianceCORE products from
CAE/Inventra include a full-speed USB function controller, low-speed USB function controller, and three-port USB hub. These cores, targeted for the XC4000E and XC4000EX
FPGA architectures and their HardWire TM equivalents, are delivered as XNF netlists
(source code in Verilog RTL format also is available). They are fully-compliant to the
USB v1.0 specification, and the FPGA-implementations were verified in hardware at a
USB-IF sponsored interoperability workshop.
To facilitate the integration of these cores,
CAE/Inventra also offers a USB simulation model and FPGA-based prototyping board, for both hub and function controllers.
PCMCIA Fax/Modem
Mobile Media Research offers a PCMCIA fax/modem interface macro and a PCMCIA interface library. Fully PCMCIA v2.0 compliant, the fax/modem core is designed for implementation in XC3000 and XC5000 series
FPGAs; when used with an external fax/ modem chipset, it forms a complete PCMCIA fax/modem card. The PCMCIA library provides the basic building blocks for constructing a custom PC-card interface. Additional products include an FPGA-based prototyping board with 12 square inches of breadboarding area, a Windows-based CIS (Card Information Structure) generator, and system-level debug software.
These products are available now from their respective vendors. For vendor contact information, please see the AllianceCORE
Partners chart below. Additional information about the AllianceCORE program can be found at WebLINX TM (www.xilinx.com).
◆
The chart below will join the other Alliance
Program charts in the
next issue of XCell.
AllianceCORE Partners - Feb. 1997
ARM Semiconductor (USA)
1095 E. Duane Ave., Suite 211
Sunnyvale, CA 94086 (USA)
Tel: 408-733-3344
Fax: 408-733-9922 [email protected]
Microprocessors, microcontrollers, peripherals, communications
CAE/Inventra
1001 Ridder Park Drive
San Jose, CA 95131 (USA)
Tel: 408-451-5814
Fax: 408-451-5690 [email protected]
USB, PCI
Comit Systems
1250 Oakmead Pkwy, #210
Sunnyvale, CA 94088 (USA)
Tel: 408-988-2988
Fax: 408-988-2133 [email protected]
www.comit.com
Base functions, communications
CoreEL Microsystems
46750 Fremont Blvd #208
Fremont, CA 94538 (USA)
Tel: 510-770-2277
Fax: 510-770-2288 [email protected]
ATM, communications
Eureka Technology
4962 El Camino Real, #108
Los Altos, CA 94022 (USA)
Tel: 415-960-3800
Fax: 415-960-3805 [email protected]
PCI, PowerPC peripherals
Integrated Silicon Systems, Ltd.
29 Chlorine Gardens
Belfast, BT9 5DL (No. Ire.)
Tel: +44 1232 664664
Fax: +44 1232 669664 [email protected]; www.iss-dsp.com
DSP functions
Logic Innovations
6205 Lusk Boulevard
San Diego, CA 92121 (USA)
Tel: 619-455-7200
Fax: 619-455-7273 [email protected]; www.logici.com
PCI, MPEG-2, ATM, commun.
Rice Electronics
PO Box 741
Florissant, MO 63032 (USA)
Tel: 314-838-2942
Fax: 314-838-2942 [email protected]
SAND Microelectronics
1630 Oakland Road, A103
San Jose, CA 95131 (USA)
DSP
Tel: 408-441-7138
Fax: 408-441-7538 [email protected]
www.sandmicro.com PCI, USB
Memec Design Services
1819 S. Dobson Rd., Suite 203
Mesa, AZ 85202 (USA)
Tel: 602-491-4311
Fax: 602-491-4907 [email protected]
www.mds.memec.com
Microprocessor peripherals, base functions, Xilinx design
Mobile Media Research, Inc.
1977 O’Toole Ave., Suite B207
San Jose, CA 95131 (USA)
Tel: 408-428-0310
Fax: 408-428-0379 [email protected]
www.mobmedres.com
PCMCIA, CardBus
Sierra Research and Tech.
465 Fairchild Dr., Suite 130
Sunnyvale, CA 94088 (USA)
Tel: 415-988-4800
Fax: 415-988-0582 [email protected]
Communications, PCI, CPU
Toucan Technology
Technology Centre
Mervue Industrial Estate
Galway, Ireland
Tel: +353-91-757223
Fax: +353-91-755635 [email protected]; www.toucan.ie
PCI, communications
Phoenix Tech./Virtual Chips
2107 N. First Street, Suite 100
San Jose, CA 95131 (USA)
Tel: 408-452-1600
Fax: 408-452-0952 [email protected]; www.vchips.com
PCI, USB, CardBus, ATM
VAutomation
20 Trafalgar Square
Suite 443 (4th Floor)
Nashua, NH 03063 (USA)
Tel: 603-882-2282
Fax: 603-882-1587 [email protected]
www.vautomation.com
Microprocessors, microcontrollers, communications
VisitWebLINX for more information: http://www.xilinx.com/products/logicore/tblpart.htm
17
18
New LogiCORE PCI Target Eases System Integration
T he new LogiCORE TM PCI Slave (targetonly) v1.1 has been shipped to all LogiCore
PCI owners with current maintenance agreements. This updated release will further simplify integration of the core with the user’s unique back-end logic. The design has been fine-tuned and constraints (e.g., new guide files) have been added. As a result, timing has
D
EVICE
XC4020E
XC4013E
P
ACKAGE
HQ240
PQ208
HQ240
PQ208
PQ160
PCI M
ASTER
April 1997
April 1997
April 1997
✓
* Available on the web for registered LogiCORE customers
PCI S
LAVE
✓ *
✓ *
✓
✓
✓ improved, and the new version is more robust than its predecessor.
The improved User’s Guide has been restructured to take the designer step-by-step through the design process. In addition, two new documents have been added to the product: a LogiCORE PCI Check List detailing the PCI commands that are supported by the core, and a PCI reference text book, PCI
Systems Architecture (T. Shanley and D.
Anderson, Mindshare Press). Furthermore, support for several new devices and package options has been added (see table).
For complete data sheets and other information, please visit the LogiCORE site at WebLINX (www.xilinx.com/products/ logicore/logicore.htm).
◆
Virtual Computing Debuts XC6200 Development Kit
V irtual Computing Corp. (Reseda, CA) has introduced the H.O.T. Works 6200 Development System, a complete programming and development system for the Xilinx XC6200 family of Reconfigurable Processing Units
(RPUs). H.O.T. Works 6200 includes the PCI-
XC6200 plug-in board and a number of software development tools:
➤ XACT-6000 TM — the Xilinx implementation tool set for the XC6200 family
➤ XC6200 VHDL Elaborator — a VHDL analyzer and EDIF netlist generator
➤ Hardware Object Technology (H.O.T.)
Interface — tools that provide for the insertion of designs into executable C programs, enabling run-time reconfigurable computing
➤ The Lola Programming System — a simple, object-oriented hardware description language for describing synchronous, digital circuits that was developed at ETH
Zurich by Niklaus Wirth (the author of
Pascal and Modula2)
➤ WebScope 6200 — a Java tool for real-time design emulation using the
PCI-XC6200 board
➤ Design and application examples
The PCI-XC6200 board is a single PCI bus board featuring an XC6216 RPU, XC4013E
FPGA (used for the PCI interface), 512Kb of
SRAM, a programmable oscillator, and PCI mezzanine connectors for daughter boards.
List price for the entire kit is $995.
For further information, contact Virtual
Computer Corp. (tel: 818-342-8294; fax:
818-342-0240; e-mail: [email protected]) or visit its web page at www.vcc.com
.
◆
DESIGN HINTS AND ISSUES
Benchmarks Again Demonstrate
XC9500 Pinlocking Capabilities
A
new set of XC9500 pinlocking benchmarks focuses on two commonly-used comparator functions — magnitude and equality compares. Magnitude comparators are often used in digital peak detector circuits in audio and video applications. Equality comparators are a key part of page mode
DRAM memory controllers.
As with previously-published CPLD benchmarks (XCell 22, page 18), the comparator benchmarks illustrate the CPLD device’s capability to accommodate design changes with fixed pinouts while maintaining an acceptable level of design performance; in other words, not only must the iterated design route when the pinout is maintained, it must do so with minimal impact on design performance.
The following two sets of benchmark data show the relative pinlocking performance of the
XC9500 CPLDs and a competitor’s
CPLD family. The designs are
ABEL-HDL implementations of benchmarks suggested by the competitor, and are targeted at devices of the competitor’s choosing. ABEL compiler and fitter options were chosen to maximize design performance, per each vendor’s recommendations.
Magnitude Compare Benchmark
This benchmark contains a single 8-, 10-, or
12-bit magnitude comparator and is intended to measure the effect of routing resources and function block fan-in on the CPLD’s pinlocking performance. A typical design change involves the correction of an error in which one of the input data paths was ordered incorrectly.
The benchmark results in Figure 1 demonstrate that both the XC95108-15 and the ispLSI2096-80 were able to accommodate the design change without any impact on design performance. However, it should be noted that the XC95108-15 was faster overall than the other device.
Equality Compare Benchmark
This benchmark contains a single 8-, 10-, or 12-bit equality comparator and is intended to measure the effect of routing resources and function block fan-in on the CPLD’s pinlocking performance. A typical design change involves the correction of an error in which one of the input data paths was ordered incorrectly.
The benchmark results in Figure 2 demonstrate the superiority of the XC9500 CPLD architecture. Not only was the XC95108 able to accommodate the design changes without any impact on design performance, that level of performance was significantly higher than the competitor’s device. Vendor L’s device
Figure 1: Magnitude
Compare Performance
R
19
20
XC9500
Benchmarking
Continued from the previous page
Figure 2: Equality
Compare Performance used multi-level logic to implement the 8-bit equality compare; a 16-input, 16 product-term logic function that is implemented in a single pass in the XC9500 CPLD.
Vendor L’s routing resources were stressed while attempting to pinlock the 10-bit equality compare; a 45% performance degradation was incurred after the design iteration. While attempting to pinlock the 12-bit equality compare, the performance didn’t just degrade, the device completely failed to route.
Conclusions
These benchmarks reconfirm the superior pin-locking performance of the XC9500 CPLD family. The wide function-block fan-in enables pinlocking of wide high-speed logic functions while at the same time delivering higher performance than competitive devices.
Furthermore, because logic feedthroughs are not needed for routing, there is no performance degradation due to routing congestion. This timing consistency is as important as routing ability for maintaining pinlocked designs.
The XC9500 CPLD devices deliver high performance and feature the industry’s best pinlocking capability, eliminating the need for PCB modifications due to design changes. This feature not only shortens design cycles and decreases design costs but also facilitates the use of in-system programmability to upgrade or modify systems in the field.
◆
Trouble-Free Switching Between Clocks
A synchronously selecting between two clock sources can easily produce glitches that
While the SELECT input is stable (either
High or Low), the two control flip-flops are in cause unreliable system behavior. The circuit opposite states and one of the two clock diagrammed here avoids these problems.
inputs drives the clock output. When the
SELECT input changes, there is no immediate impact until after the next falling edge of the originally-selected clock source, which also resets its control flip-flop. The Output Clock signal will then stay Low until the next falling edge of the newly-selected clock. This edge will set its control flip-flop, causing this clock to drive the Output Clock. Thus, with this circuit, any switching between clock sources is delayed by holding the output Low from the time the first clock goes Low until the time the second clock is Low.
◆
Demultiplexing 200 MHz Data Streams
M odern serial data protocols (e.g.,
FireWire, SONET, ATM, T4) sometimes require clocks that are faster than maximum FPGA global clock speeds. To solve this problem, the incoming clock (200 MHz in the example below) can be used to demultiplex the incoming single data stream into two parallel data streams clocked at one-half the speed (100
MHz here).
The circuit diagrammed below avoids the set-up time of the XC3100A-09 FPGA’s IOB input flip-flop and the delay of the global clock distribution network. Incoming data and clock are both routed to nearby CLBs. The delay on the data path from pad to CLB function generator is 2.1 ns (worst case), while the delay on the clock path from pad to CLB input is 2.3 ns. The CLB register’s set-up time
(function generator input to CLB clock input) is 1.5 ns. The longest possible input pad-to-
CLB register set-up time is 2.1 + 1.5 - (0.7 x
2.3) = 2.0 ns. (This assumes 70% delay tracking; i.e., if one delay is at its worst-case value, the other delay cannot be shorter than 70% of its maximum value.)
The possibility of a pad-to-register hold time requirement is assessed by evaluating the opposite situation: (0.7 x 3.6) - 2.3 = 0.2 ns.
Since the result is a positive value, the pad-toregister set-up time will always be positive, so there is no hold time requirement.
The circuit also can be cascaded to demultiplex the incoming data stream into four parallel streams (for example, for storage in the slightly slower XC4000E distributed
RAM). Such a 1-to-4 demultiplexing structure uses just six CLBs.
The corresponding output multiplexing is more difficult, since the delay between clock input-to-output pad and clock-to-out in the
XC3100A-09 is greater than 5 ns. An external
ECL clocked multiplexer may be the most practical solution.
◆
FPGA
Highs
and
Lows Up in Space and Below the Surface
T he highest-flying Xilinx FPGAs are in instrumentation cards on-board the United dropped to a depth of more than 15,000 feet
(5,000 meters). They help measure important
States’ space shuttle, as well as the Russian
SOYUZ spacecraft and MIR space station. The instrumentation card contains two XC3042-70
PQ100C commercial-temperature devices in inexpensive plastic packages that have functioned properly in orbit for several years.
The FPGA depth record was set by a variety of XC3000 and XC4000 series devices used in oil exploration instruments that have parameters that may point to the existence of oil pockets. Used for days and weeks at a time, the devices have continued working at temperatures of up to 175° C (about 350° F ).
For future, deeper drillings, designers are now exploring the behavior of Xilinx devices at 200° C (the typical geothermal gradient is
30° C per 1,000 m).
◆
21
22
Using the HW-130 Programmer
I f you have had difficulty installing your
HW-130 Programmer, Xilinx Technical Support recommends this troubleshooting process.
First, before first connecting the HW-130 to the COM port of your PC (or after disconnecting it from the port), check to ensure that it powers up properly. The power-on LED indicator light located above the FAIL light should blink following power-on while the programmer performs a self-test, and then stop blinking and remain lit. If the power-on
LED does not blink initially, or the FAIL light goes on and stays on, the programmer is probably defective; contact Xilinx Customer
Service to obtain a replacement unit.
A typical installation and start-up of the programmer involves the following steps:
1
Insert the floppy disk and change to the
“a:\>“ (or “b:\>”) prompt.
2
Type “install” and follow the instructions on the screen.
3
After installation of the software, “cd” to the target directory.
4
Hook up the programmer to the serial port of your PC and power it up. Make sure the
FAIL LED is not flashing three or four seconds after power-on.
5
Type “hw130” to launch the application.
The software will search all COM ports for the programmer and negotiate the highest baud rate after doing a reset of the programmer. The power LED of the programmer will flash for about four seconds during the reset.
6
Once communication has been established, you can select a device and use the programmer.
Assuming that this installation process has been followed completely, but the HW-130 is still not working properly, one of the following procedures may solve the problem:
➤ If you are using the DOS version, make sure you are not running out of a DOS window in Windows 3.1, 95 or NT. The hw130 program only works in a DOS-only environment.
➤ Make sure there is not a “hw130.ini” file in the working directory. Delete it if there is one.
➤ Check that you are using a standard serial cable and/or 9-25 or 25-9 pin cable adapters. Null modem cables will not work.
➤ Make sure the minimum 470K of conventional memory needed to launch the program is available. Type “mem” from the DOS prompt, look for the line, “Largest executable program size ...Kbyte.” If it is less than 470K, unload some device drivers in the config.sys or autoexec.bat files and restart the PC (or run a memory optimization routine, such as “memmaker” provided with later DOS versions).
➤ Run “msd” (Microsoft diagnostics) from the
DOS prompt, type in “C” for COM ports.
Check that two COM ports are available
➤
(two 16550 UART chips). The additional port is required to support your mouse.
The other settings of the COM ports (like the baud rate, data bits, and so on) do not matter because the HW130 software initializes these settings. Make sure the address used is correct for the COM ports. Type in
“Q” from the main menu of msd for the
IRQ settings on the PC. Make sure IRQ3 points to COM2 and 4, and IRQ4 to COM1 and 3. The software assumes the following default addresses and IRQ settings on the
COM ports:
COM1 COM2 COM3 COM4
Address 03F8 02F8 03E8 02E8
IRQ 4 3 4 3
If all else fails, reboot the PC and enter the
CMOS setup. Search around for the COM ports and try swapping the COM ports (i.e.
use a different UART for the programmer).
Point COM1 to COM2 and COM2 to
COM1. If there is only one COM port, point it to COM1 instead of 2 (or vice versa). Exit and save the CMOS setup and try again.
◆
TECHNICAL QUESTIONS & ANSWERS
Q
What should be done with unused I/O pins in an XC9500
CPLD design?
XC9500 devices have internal pull-up resistors on all I/O pins. However, these resistors are active only during power-up, device configuration, in-system programming, and Intest. During normal operation, the pullup resistors are disabled.
Xilinx recommends that any unused I/O be tied to board ground.
The upcoming M1 software release supports “user-programmable grounds”. This feature ties unused I/O cells to the internal lead frame ground of the CPLD device.
CPLD
TECHNICAL SUPPORT RESOURCES
Need technical help right now?
Here’s where to start:
1. Find us on the Internet at www.xilinx.com
We update our “Answers” Web tool daily with the very latest application notes, data sheets, patches and solutions to your technical questions. Get immediate answers 24 hours per day!
If you don’t have access to the Web or can’t locate an answer via step #1, then...
2. Contact your nearest Customer Support Hotline
NORTH AMERICA SUPPORT
(Mon, Tues, Wed, Fri 6:30am-5pm
Thur 6:30am - 4:00pm Pacific Time)
Hotline: 800 255 7778 or 408 879 5199
Fax: 408 879 4442
BBS: 408 559 9327
Email: [email protected]
UNITED KINGDOM SUPPORT
(Mon, Tues, Wed, Thur 9:00am-12:00pm, 1:00-
5:30pm, Fri 9:00am-12:00pm, 1:00-3:30pm)
Hotline: (44) 1932 820821
Fax: (44) 1932 828522
Email: [email protected]
FRANCE SUPPORT
(Monday-Friday 9:30am-12:30pm, 2:00-5:30pm)
Hotline: (33) 1 3463 0100
Fax: (33) 1 3463 0959
Email: [email protected]
GERMANY SUPPORT
(Mon, Tues, Wed, Thur 8:00am-12:00pm, 1:00-
5:00pm, Fri 8:00am-12:00pm, 1:00pm-3:00pm)
Hotline: (49) 89 991 54930
Fax: (49) 89 904 4748
Email: [email protected]
JAPAN SUPPORT
(Mon, Tues, Thur, Fri 9:00am-5:00pm,
Wed 9:00am-4:00pm)
Hotline: (81) 3 3297 9163
FAX: (81) 3 3297 0067
Email: [email protected]
Need a software update, authorization code, or documentation update?
Contact Xilinx Customer Service in the U.S.: 800 624 4782
Europe: (44) 1932-349401 international: 408 559 7778, (ask for
Customer Service) ◆
23
COMPONENT AVAILABILITY CHART
24
64
68
120
132
156
160
164
175
176
191
196
208
223
225
228
240
44
84
100
144
256
299
304
352
411
432
475
559
560
PLASTIC LCC PC44
PLASTIC QFP PQ44
PLASTIC VQFP VQ44
CERAMIC LCC WC44
PLASTIC VQFP VQ64
PLASTIC LCC PC68
CERAMIC LCC WC68
PLASTIC LCC PC84
CERAMIC LCC WC84
CERAMIC PGA PG84
PLASTIC PQFP PQ100
PLASTIC TQFP TQ100
PLASTIC VQFP VQ100
TOP BRZ. CQFP CB100
CERAMIC PGA PG120
PLASTIC PGA PP132
CERAMIC PGA PG132
PLASTIC TQFP TQ144
CERAMIC PGA PG144
CERAMIC PGA PG156
PLASTIC PQFP PQ160
TOP BRZ. CQFP CB164
PLASTIC PGA PP175
CERAMIC PGA PG175
PLASTIC TQFP TQ176
CERAMIC PGA PG191
TOP BRZ. CQFP CB196
PLASTIC PQFP PQ208
HI-PERF QFP HQ208
CERAMIC PGA PG223
PLASTIC BGA BG225
TOP BRZ. CQFP CB228
PLASTIC PQFP PQ240
HI-PERF QFP HQ240
PLASTIC BGA BG256
CERAMIC PGA PG299
HI-PERF. QFP HQ304
SUPER BGA BG352
CERAMIC PGA PG411
SUPER BGA BG432
CERAMIC PGA PG475
CERAMIC PGA PG559
SUPER BGA BG560
◆
◆
◆ ◆
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◆ ◆ ◆ ◆ ❖
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◆
❖ ❖
❖ ❖
❖ ❖ ❖ ❖
❖ ❖ ❖ ❖
❖
❖ ❖
❖ ❖ ❖
❖ ❖
❖ ❖ ❖ ❖ ❖
❖
❖ ❖
❖ ❖ ❖
❖ ◆ ◆
❖ ◆ ◆ ❖
◆
❖
◆ ◆
FEBRUARY 1997
223
225
228
240
411
432
475
559
560
256
299
304
352
144
156
160
164
175
176
191
196
208
44
64
68
84
100
120
132
PLASTIC LCC PC44
PLASTIC QFP PQ44
PLASTIC VQFP VQ44
CERAMIC LCC WC44
PLASTIC VQFP VQ64
PLASTIC LCC PC68
CERAMIC LCC WC68
PLASTIC LCC PC84
CERAMIC LCC WC84
CERAMIC PGA PG84
PLASTIC PQFP PQ100
PLASTIC TQFP TQ100
PLASTIC VQFP VQ100
TOP BRZ. CQFP CB100
CERAMIC PGA PG120
PLASTIC PGA PP132
◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆
◆ ◆ ◆
CERAMIC PGA PG132
PLASTIC TQFP TQ144
CERAMIC PGA PG144
CERAMIC PGA PG156
PLASTIC PQFP PQ160
TOP BRZ. CQFP CB164
PLASTIC PGA PP175
CERAMIC PGA PG175
PLASTIC TQFP TQ176
CERAMIC PGA PG191
TOP BRZ. CQFP CB196
PLASTIC PQFP PQ208
HI-PERF QFP HQ208
CERAMIC PGA PG223
PLASTIC BGA BG225
TOP BRZ. CQFP CB228
◆
◆ ◆ ◆
◆
◆ PLASTIC PQFP PQ240
HI-PERF QFP HQ240
PLASTIC BGA BG256
CERAMIC PGA PG299
◆ ◆ ◆ ◆
◆ ◆
◆ ◆ ◆ ◆
◆ ◆
◆
◆ ◆
◆
◆
◆
◆ ◆
◆
◆
◆
◆
HI-PERF. QFP
PLASTIC BGA
HQ304
BG352
CERAMIC PGA PG411
PLASTIC BGA BG432
CERAMIC PGA PG475
CERAMIC PGA PG559
PLASTIC BGA BG560
◆ ◆ ◆ ◆ ◆
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❖ ❖
◆ = Product currently shipping or planned
❖ = New since last issue of XCell
25
26
P
ROGRAMMER
S
UPPORT
F
OR
X
ILINX
XC7200/XC7300 CPLDS — F
EBRUARY
1997
MANUFACTURER
ADVANTECH
ADVIN SYSTEMS
AMERICAN RELIANCE, INC.
B&C MICROSYSTEMS, INC.
BP MICROSYSTEMS
BYTEK
DATAMAN
DATA I/O
DEUS EX MACHINA ENGINEERING
ELECTRONIC ENGINEERING TOOLS
ELAN
HI-LO SYSTEMS RESEARCH
ICE TECHNOLOGY LTD
LEAP ELECTRONIC CO., LTD.
LOGICAL DEVICES
MICROPROSS
MQP ELECTRONICS
NEEDHAM’S ELECTRONICS
SMS
STAG
SUNRISE
SUNSHINE
SYSTEM GENERAL
TRIBAL MICROSYSTEMS
XELTEK
XILINX
MODEL
PC-UPROG
LABTOOL-48
PILOT-U40
PILOT-U84
SPECTRUM-48
Proteus
BP-1200
BP-2100
CHIPBURNER-40
DATAMAN-48
2900
3900/AutoSite
UniSite
XPGM
ALLMAX/ALLMAX+
MEGAMAX
6000 APS
All-03A
All-07
Micromaster 1000/E
Speedmaster 1000/E
Micromaster LV
Speedmaster LV
LEAPER-10
LP U4
ALLPRO-88
ALLPRO-88XR
ALLPRO-96
Chipmaster 2000
Chipmaster 6000
XPRO-1
ROM9000
SYSTEM 2000
PIN-MASTER 48
EMP20
EXPERT
OPTIMA
ECLIPSE
T-10 UDP
T-10 ULC
POWER-100
EXPRO-60/80
TURPRO-1/FX
MULTI-APRO
Flex-700
TUP-300
TUP-400
SUPERPRO
SUPERPRO II
SUPERPRO II/P
HW-130
7236A 7272A 7318 7336 7336Q 7354 7372 73108 73144
DISQUALIFIED
10.84B
10.86B
10.86B
10.84B
10.84B
10.84B
10.84B
10.86B
10.86B
10.84B
10.84B
10.84B
10.84B
10.84B
1Q97 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97
V3.15
V3.15
V1.30
V1.40
V1.1E
V3.09
V3.09
V1.1
V1.1
V1.1
V1.1
V3.2
V2.1
V3.15
V3.15
1.0a
V1.30
V1.40
V2.4U
V2.4U
V1.1E
V3.09
V3.09
V1.1
V1.1
V1.1
V1.1
V3.2
V2.1
V3.15
V3.15
1.0a
V1.30
V5.3
V5.3
V5.3
V1.40
V2.5
V2.1x
V3.09
V3.09
V1.1
V1.1
V1.1
V1.1
V3.2
V3.0
V3.18
V3.18
1.0a
V1.30
V5.3
V5.3
V5.3
V3.15
V3.15
V1.30
V5.3
V5.3
V5.3
V3.15
V3.15
1.0a
V1.30
V5.3
V5.3
V5.3
V1.40
V2.5
V2.1x
V3.09
V3.09
DISQUALIFIED
V3.09
V3.09
V3.09
V3.09
V3.15
V3.15
1.0a
V1.30
V5.3
V5.3
V3.15
V3.15
1.0a
V1.30
V5.3
V5.3
V1.40
V1.40
V1.40
V1.40
V2.4U
V2.4U
V2.4U
V2.4U
V1.1E
V1.1E
V1.1E
V1.1E
V1.1
V1.1
V1.1
V1.1
V3.2
V3.0
V1.1
V1.1
V1.1
V1.1
V3.2
V2.1
V1.1
V1.1
V1.1
V1.1
V3.2
V2.1
V3.09
V3.09
V3.1
V3.1
V3.1
V3.1
V3.2
V2.1
V3.09
V3.09
V1.1
V1.1
V1.1
V1.1
V3.2
V2.1
V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1
V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1 V2.9Rev1
6.4.26
6.4.26
6.4.26
6.4.26
6.4.26
6.4.26
6.4.26
6.4.26
V2.4U
V2.4U
V2.4U
V2.4U
V2.4U
V2.4U
V2.4U
V2.4U
V1.31A
V1.31A
V1.31A
V1.31A
V1.31A
V1.31A
V1.31A
V1.31A
DISQUALIFIED
Feb-97 Feb-97 Feb-97 Feb-97 Feb-97 Feb-97 Feb-97 Feb-97 Feb-97
V3.10
V3.10
V3.10
V3.10
V3.10
V3.10
DISQUALIFIED
DISQUALIFIED
V3.10
V3.10
6.4.26
6.4.26
6.12.11
6.12.11
6.4.26
6.4.26
6.4.26
6.4.26
V8.40
V8.40
V2.30
V3.02
V3.09
V3.09
V3.09
V8.40
V8.40
V2.30
V3.02
V3.09
V3.09
V3.09
V8.40
V8.40
V2.30
V3.02
V3.09
V3.09
V3.09
V8.40
V8.40
DISQUALIFIED
DISQUALIFIED
V8.40
V8.40
V2.30
V3.02
V2.30
V3.02
V2.30
V3.02
V3.09
V3.09
V3.09
V3.09
V3.09
V3.09
V3.09
V3.09
V3.09
V8.40
V8.40
V2.30
V3.02
V3.09
V3.09
V3.09
V8.40
V8.40
V2.30
V3.02
V3.09
6.8.9
V2.30
V3.02
2.4B
2.4B
V2.04
2.4B
2.4B
V2.04
2.4B
2.4B
V4.00
2.4B
2.4B
V4.00
2.4B
2.4B
V4.00
2.4B
2.4B
V4.00
2.4B
2.4B
V4.00
2.4B
2.4B
V4.00
1Q97
1.0a
V1.50
V1.1
V1.1
V1.1
V1.1
2.4B
2.4B
V4.00
DATA I/O
STAG
SYSTEM GENERAL
P
ROGRAMMER
S
UPPORT
F
OR
XC9500 CPLD
S
— F
EBRUARY
1997
MANUFACTURER
ADVANTECH
BP MICROSYSTEMS
HI-LO SYSTEMS RESEARCH
LOGICAL DEVICES
SMS
TRIBAL MICROSYSTEMS
XILINX
MODEL
LABTOOL-48
BP-1200
BP-2100
2900
3900/AutoSite
UniSite
All-07
ALLPRO-88
EXPERT
OPTIMA
ECLIPSE
TURPRO-1/FX
MULTI-APRO
Flex-700
HW-130*
9536
1Q97
V3.21
V3.21
BBS
BBS
BBS
Feb ‘97
Feb ‘97
1Q97
1Q97
Feb ‘97
Feb ‘97
Feb ‘97
Feb ‘97
V4.00
9536F
1Q97
V3.21
V3.21
BBS
BBS
BBS
Feb ‘97
Feb ‘97
1Q97
1Q97
Feb ‘97
Feb ‘97
Feb ‘97
Feb ‘97
V4.00
9572
1Q97
Feb ‘97
Feb ‘97
BBS
BBS
1Q97
1Q97
1Q97
1Q97
1Q97
1Q97
1Q97
1Q97
V4.00
9572F
1Q97
Feb ‘97
Feb ‘97
BBS
BBS
1Q97
1Q97
1Q97
1Q97
1Q97
1Q97
1Q97
1Q97
V4.00
95108 95108F 95216
1Q97
V3.21
V3.21
1Q97
V3.21
V3.21
BBS
BBS
Feb ‘97
Feb ‘97
1Q97
1Q97
Feb ‘97
Feb ‘97
Feb ‘97
Feb ‘97
V4.00
BBS
BBS
Feb ‘97
Feb ‘97
1Q97
1Q97
Feb ‘97
Feb ‘97
Feb ‘97
Feb ‘97
V4.00
V4.00
Changes since last issue are noted in color.
* NOTE: Reflects the version of the Host Software.
PROGRAMMER SUPPORT FOR XILINX XC1700 SERIAL PROMS - FEBRUARY 1997
MANUFACTURER
ADVANTECH
DEUS EX MACHINA
ELECTRONIC
ENGINEERING TOOLS
ELAN DIGITAL SYSTEMS
MODEL
PC-UPROG
LABTOOL-48
ADVIN
AMERICAN RELIANCE, iNC.
SPECTRUM-48
B&C MICROSYSTEMS INC.
PROTEUS-UP40
BP MICROSYSTEMS
PILOT-U24
PILOT-U28
PILOT-U32
PILOT-U40
PILOT-U84
PILOT-142
PILOT-143
PILOT-144
PILOT-145
BYTEK
DATAMAN
DATA I/O
CP-1128
EP-1140
BP-1200
BP-2100
135H-FT/U
MTK-1000
MTK-2000
MTK-4000
FIREMAN-8M
FIREMAN-8X
CHIPBURNER-40
DATAMAN-48
UniSite
2900
3900
AutoSite
ChipLab
2700
XPGM
ALLMAX/ALLMAX+ V2.4U
MEGAMAX V1.1E
3000-145
5000-145
6000 APS
XC1718D
XC1736D XC1718L XC17128D XC17128L
XC1765D
10.84B
10.84B
10.84B
10.84B
10.84B
10.84B
10.84B
10.84B
10.84B
3.7Q
V3.15
V3.15
8E
8E
8E
8E
8E
8E
1.0a
V1.30
V1.60
XC1765L
DISQUALIFIED
V3.15
V3.15
8E
8E
8E
8E
8E
8E
1.0a
10.84B
10.84B
10.84B
10.84B
10.84B
10.84B
10.84B
10.84B
10.84B
V3.15
V3.15
8E
8E
8E
8E
8E
8E
1.0a
V1.30
New algorithms in progress
V1.60
V2.4U
V1.1E
XC17256D XC17256L
3.7Q
V1.60
V2.4U
V1.1E
8E
8E
8E
8E
8E
8E
1.0a
V1.60
HI-LO SYSTEMS RESEARCH All-03A
All-07
ICE TECHNOLOGY LTD
LEAP ELECTRONICS
V3.19
V3.19
Micromaster 1000/E V3.17
Speedmaster 1000/E V3.17
Micromaster LV
LV40 Portable
Speedmaster LV
V3.17
V3.17
V3.17
LEAPER-10
LP U4
V2.0
V2.0
DISQUALIFIED
V3.19
V3.19
V3.19
V3.19
V3.17
V3.17
V3.17
V3.17
V3.17
V3.17
V3.17
V3.17
V3.17
V3.17
V2.0
V2.0
V3.19
V3.19
V3.17
V3.17
V3.17
V3.17
V3.17
MANUFACTURER MODEL
LINK COMPUTER GRAPHICS CLK-3100
LOGICAL DEVICES
MICRO PROSS
MQP ELECTRONICS
XC1718D
XC1736D XC1718L XC17128D XC17128L
XC1765D
V5.61
ALLPRO-40
ALLPRO-88
ALLPRO-88XR
V2.7
V2.7
ALLPRO-96 6.5.10
CHIPMASTER 2000 V2.4U
CHIPMASTER 6000 V1.31A
XPRO-1 SPROM.310
ROM 5000 B
ROM 3000 U
ROM9000
MODEL 200
SYSTEM 2000
PIN-MASTER 48
V1.94
V3.84
6.46
2.25
XC1765L
6.5.10
6.46
2.25
XC17256D XC17256L
V5.61
V2.7
V2.7
6.5.10
V2.4U
V1.31A
SPROM.310
V1.94
V3.84
6.46
2.25
6.5.10
NEEDHAM’S ELECTRONICS EMP20
RED SQUARE IQ-180
IQ-280
Uniwriter 40
Chipmaster 5000
SMS Expert
Optima
Multisyte
Sprint Plus48
STAG
V3.10
6.5.10
V3.10
DISQUALIFIED
DISQUALIFIED
DISQUALIFIED
DISQUALIFIED
DISQUALIFIED
DISQUALIFIED
DISQUALIFIED
DISQUALIFIED
6.5.10
6.5.10
6.5.10
SUNRISE
SUNSHINE
SYSTEM GENERAL
TRIBAL MICROSYSTEMS
XELTEK
XILINX
Eclipse
Quasar
T-10 UDP
T-10 ULC
POWER-100
EXPRO-60/80
TURPRO-1
TURPRO-1 F/X
TURPRO-1 T/X
APRO
MULTI-APRO
TUP-300
TUP-400
FLEX-700
SuperPRO
SuperPRO II
SuperPRO II/P
HW-112*
HW-130*
V8.40
V8.40
V2.26H
V2.26H
V1.24
V1.16
V3.19
V3.19
V3.19
2.4B
2.4B
V2.03
DISQUALIFIED
DISQUALIFIED
V2.26H
V2.26H
V1.16
V3.19
V3.19
V3.19
V8.40
V8.40
V2.26H
V2.26H
V1.16
V3.19
V3.19
V3.19
2.4B
2.4B
New algorithms in progress
V2.03
V2.03
V2.26H
V2.26H
V1.16
V3.19
V3.19
V3.19
V2.03
*NOTE: Reflects the version of the host software
Changes since last issue printed in color
C
OMPANY
N
AME
Aldec
P
RODUCT
N
AME
Active-CAD
Cadence
Mentor Graphics
Verilog
Concept
FPGA Designer
Synergy
Composer
Autologic
Design Architect
QuickSim II
QuickHDL
Galileo
Leonardo
OrCAD
Synario Design Automation ABEL
Synario
Synopsys FPGA Express
FPGA Compiler
VSS
Design Compiler
Viewlogic
Capture (Win)
Simulate (Win)
VST 386+ (DOS)
SDT 386+ (DOS)
PLD 386+ (DOS)
Capilano Computing
Compass Design
Automation
WorkView Office
ProSynthesis
ProSim
ProCapture
PowerView
Design Works
ASIC Navigator
X-Syn
QSim
Escalade
Exemplar Logic
IK Technology Co.
IKOS Systems
DesignBook
Galileo
Leonardo
I
SHIZUE
P
ROFESSIONALS
Voyager
Gemini
INCASES Engineering GmbH Theda
ISDATA LOG/iC Classic
LOG/iC2
Logic Modeling Corp.
(Synopsis Division)
Model Technology
Smart Model
LM1200
V-System/VHDL
Protel Technology Advanced Schematic
Advanced PLD
Quad Design Technology Motive
SimuCad Silos III
Sophia Sys & Tech
Summit Design Corp.
Vanguard
Visual HDL
Synplicity, Inc.
Synplify-Lite
Synplify
TopDown Design Solutions V-BAK
XILINX ALLIANCE-EDA COMPANIES & PRODUCTS - FEBRUARY 1997 - 1 OF 2
V
ERSION
F
UNCTION
D
ESIGN
K
IT
3
K
/ XC CPLD U
NI
4
K
5200 7
K
9
K
L
IB
2.2
2.4
2.1
9504
2.3
4.4
A.3-B.1
B.x
B.x
B.x
3.2.5
4.0.1
Schematic Entry, State Machine & HDL Included
Editor, FPGA Synthesis & Simulation
Simulation
Schematic Entry
Topdown FPGA Synthesis
FPGA Synthesis
Schematic Entry
Synthesis
Schematic Entry
Simulation
Simulation
Synthesis
Synthesis
Xilinx Front End
Xilinx Front End
Call Xilinx
Call Xilinx
Xilinx Front End
Xilinx Synthesis Lib.
Call Xilinx
Call Xilinx
Call Xilinx
Call Mentor
Call Mentor
✓
7.0
6.10
1.2
1.2
2.0
Schematic Entry
Simulation
Simulation
Schematic Entry
Synthesis
Call OrCAD
Call OrCAD
Call OrCAD
Call OrCAD
Call OrCAD
6.3
2.3
1.0
3.5
3.5
3.5
7.1.2/7.2
5.02
6.1
6.1
6.0
3.1
2.0
3.2
4.0.1WS
/
1.06
2.31
1.21
4.1
4.2
4.2
4.02PC
Synthesis, Simulation ABEL-XCPLD
Schematic Entry, Synthesis & Simulation SYRO-LCA, SYRO-XCPLD ✓
Synthesis
Synthesis
Simulation
Synthesis
Call Synopsis
Call Xilinx
Call Xilinx
Call Xilinx
✓
✓
✓
✓
Schem/Sim/Synth
Synthesis
Simulation, Timing Analysis
Schematic Entry
Schematic Entry/Sim
Schematic Entry
Synthesis
Simulation
Design Entry
Call Xilinx
Call Xilinx
Call Xilinx
Call Xilinx
Schem/Sim/Synth/Timing Analysis Call Xilinx
XD-1
Xilinx Design Kit
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Synthesis/Timing Analysis Simulation
Synthesis
Schematic Entry/Simulation
Simulation
Simulation
Design Entry
Synthesis
Synthesis Simulation
Simulation Models
Hardware Modeler
Included
Included
Xilinx Design Kit
Xilinx Tool Kit
Xilinx Tool Kit
Xilinx Kit
LCA-PP
Xilinx Mapper
In Smart Model Lib.
Xilinx Logic Module
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
4.4j (PC) /
3.2
3
4.6a (WS) Simulation
4.3
96.1
5.31
3.0
2.6b
2.6b
1.1
Schematic Entry
PLD/FPGA Design & Simulation
Timing Analysis
Schematic Entry & Simulation
Schematic Entry
Graphical Design Entry/Simulation/Debug
Synthesis
Synthesis
XNF to VHDL translator
Included
Included
XNF2MTV
Included
Xilinx I/F Kit
EDIF Interface
Xilinx Mapper included
XNF interface
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓ TBD
✓
✓
✓
✓
✓
✓
✓
7k
7k
7k
✓
✓
✓
✓
✓
4Q
✓
✓
✓
✓
9k
9k
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
7k
7k
7k
7k
✓
✓
7k
7k
7k
7k
7k
✓
✓
✓
7k
7k
✓ 7k,9k
7k,9k
✓
✓
✓
✓
✓
✓
✓
✓
7k
7k
✓
✓
7k
7k
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
PC
✓
PLATFORMS
S
UN
RS6000 HP7
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
XILINX ALLIANCE-EDA COMPANIES & PRODUCTS - FEBRUARY 1997 - 2 OF 2
C
OMPANY
N
AME
P
RODUCT
N
AME
TopDown Design Solutions V-BAK
V
EDA
D
ESIGN
A
UTOMATION
I
NC
Vulcan
Veribest Veribest VHDL
Veribest Verilog
VeriBest Simulator
DMM
VeriBest Synthesis
Synovation
PLDSyn
VerBest Design Capture
Accolade Design Automation Peak VHDL
Peak FPGA
ACEO Technology, Inc.
Acugen Software, Inc.
Asyn
Softwire
Gatran
Sharpeye
ATGEN
AAF-SIM
PROGBSDL
TESTBSDL
ALPS LSI Technologies Edway Design Systems
Aptix Corporation
Aster Ingenierie S.A.
Auspy Development Co.
Chronology Corporation
System Explorer
ASIC Explorer
XILLAS
APS
TimingDesigner
QuickBench
SmartViewer CINA-Computer
Integrated Network Analysis
Epsilon Design Systems
Flynn Systems
Logic Compressor
Fujitsu LSI
Harmonix Corporation
Logical Devices
MINC
Teradyne
Tokyo Electron Limited
Probe
FS-ATG
CKTSIM
FS-SIM
PROVERD
PARTHENON
Total Designer
Ulysa
PLDesigner-XL/PL-Synthesizer
Lasar
ViewCAD
Trans EDA Limited TransPRO
Visual Software Solutions Statecad
Zuken Tsutsuji
Zycad Paradigm RP
Paradigm XP
Items that have changed since the last issue (XCell 23) are in color.
The following entry was removed: MEMEC
V
ERSION
1.1
4.5
14.0
14.0
14.0
14.x
14.0
12.2
12.0
14.x
2.21
2.20
4.1
3.3
3.3
2.60
2.60
2.60
2.63
2.63
3.1
2.3
4.2
1.3.3
3.0
1.0
1.0e
3.0
3.0
3.0
3.0
2.3
4.7
1.0
3.3/3.2.2
6
1.2
1.2
3.0
F
UNCTION
XNF to VHDL translator
Simulation
Schematic Entry
Simulation
Simulation
Design Management
Synthesis
Synthesis
Design Entry Synthesis
Design Capture
Simulation
Synthesis
Synthesis
Multi-FPGA Partitioning
ASIC to FPGA Netlist Mapping
Testability Analysis
Automatic Test Generation
Fault Simulation
BSDL Customization
Boundary Scan ATG
Synthesis/Simlulation
System Emulation
ASIC Emulation
LASAR model generation
Multi-FPGA Partitioning
Timing Specification and Analysis
Visual Test Bench Generator
Schematic Generation
Synthesis optimization
Testability Analysis
Test Vector Generation
Logic Analysis
Simulation
Top-Down Design System
Synthesis
Simulation & Synthesis
VHDL Synthesis
Synthesis
Simulation
FLDL to XNF translator
Synthesis
Grph. Design Entry, Sim., Debug
Synthesis/Simulation
Rapid Prototyping
Gate-level Sim
D
ESIGN
K
IT
XNF interface
XILINX Tool Kit
Xilinx FPGA Design Kit
Xilinx FPGA Design Kit
Xilinx FPGA Design Kit
Xilinx FPGA Design Kit
Xilinx FPGA Design Kit
Xilinx FPGA Design Kit
Xilinx FPGA Design Kit
Xilinx Plus
Included
Included
Included
Included
AALCA interface
AALCA interface
AALCA interface
AALCA interface
AALCA interface
Axess 3.1
Axess 2.3
Worst Case Simulation
Included
Included
Included
XNF Interface
Xilinx Kit
Xilinx Kit
Xilinx Kit
Xilinx Kit
Included
Call Xilinx
Call Xilinx
Xilinx Design Module
Xilinx I/F Kit
XNFGEN
Xilinx Library
XNF Interface
Diamond: These partners have strong strategic relationships with Xilinx and have a direct impact on our releases. Typically, Xilinx is directly involved in the development and testing of the interface to XACTstep software for these products.
✓
✓
✓
✓
✓
3k,4k
✓
✓
✓
✓
✓
4k
✓
✓
3k,4k
✓
✓
2
K
/3
K
/ XC CPLD U
NI
4
K
5200 7
K
9
K
L
IB
✓
✓
✓
✓
4K
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
3k,4k
3k,4k
3k,4k ✓
3k,4k ✓
3k,4k ✓
3k,4k
✓
3k,4k ✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
7k
✓
7k
7k
7k
7k
7k
✓
✓
7k
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓ 7k,9k ✓
✓ 7k,9k ✓
7k
✓
✓
✓
✓
✓
✓
✓
✓
7k
7k
7k
7k
7k
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
PLATFORMS
PC S
UN
RS6000 HP7
✓ ✓ ✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓ ✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Ruby: These partners have a high degree of compatibility and have repeatedly shown themselves to be significant contributors to our users’ development solutions.
Emerald: Proven Xilinx compatibility
✓
✓
✓
✓
✓
30
XILINX ALLIANCE-EDA CONTACTS - FEBRUARY 1997
C
OMPANY
N
AME
Accolade Design Automation
ACEO Technology, Inc.
Acugen Software, Inc.
Aldec
ALPS LSI Technologies, Inc.
Alta Group
Aptix Corporation
Aster Ingenierie S.A.
Cadence
Capilano Computing
Chronology Corporation
CINA-Computer Integrated Network Analysis
Compass Design Automation
Epsilon Design Systems, Inc.
Escalade
Exemplar Logic
Flynn Systems
Fujitsu LSI
Harmonix Corporation
IK Technology Co.
IKOS Systems
INCASES Engineering GmbH
ISDATA
Logic Modeling Corp. (Synopsis Division)
Logical Devices
Memec Design Services
Mentor Graphics
MINC
Minelec
Model Technology
OrCAD
Protel Technology
Quad Design Technology, Inc.
SimuCad
Sophia Sys & Tech
Summit Design Corporation
Synario Design Automation
Synopsys
Synplicity, Inc.
Teradyne
Tokyo Electron Limited
TopDown Design Solutions
Trans EDA Limited
VEDA Design Automation Inc
Veribest
Viewlogic
Visual Software Solutions, Inc.
Zuken
Zycad
Luise Markham
Britta Sullivan
Richard Jones
Tom Tilbon
Ed Sinclair
Jacquelin Taylor
Lynn Fiance
Alisa Yaffa
Mike Jew
Shige Ohtani
Art Pisani
James Douglas
Kathie O’Toole
Mike O’Donohue
John Dube
Riky Escoto
Makato Ikeda
Charlene Locke
C
ONTACT
N
AME
Dave Pellerin
Ray Wei
Nancy Hudson
David Rinehart
David Blagden
Paul Ekas
Michel Courtney
Christopher Lotz
Ann Heilmann
Chris Dewhurst
MikeMcClure
Brad Ashmore
Marcia Murray
Cuong Do
Rod Dudzinski
Shubha Shukla
Matt Van Wagner
Masato Tsuru
Shigeaki Hakusui
Tsutomu Someya
Brad Roberts
Christian Kerscher
Ralph Remme
Marnie McCollow
Chip Willman
Maria Agular
Sam Picken
Kevin Bush
Marketing Department
Greg Seltzer
Mike Jingozian
(408) 243-8143
(805) 988-8250
(510) 487-9700
(408) 232-4764
(503) 643-9281
(206) 867-6257
(415) 694-4289
(415) 961-4962
(617) 422-3753
+81-3-334-08198
(603) 888-8811
+44-703-255118
(408) 496-4515
(303) 581-2330
(508) 480-0881
(800) 208-1051
+81-4-594-27787
(510) 623-4451
P
HONE
N
UMBER
(800) 470-2686
(510) 656-2189
(603) 881-8821
(702) 456-1222 x12
441489571562
(408) 523-4135
(408) 428-6226
+33-99537171
(408) 944-7016
(604) 522-6200
(206) 869-4227 x116
(415) 940-1723
(408) 474-5002
(408) 934-1536
(408) 654-1651
(510) 337-3741
(603) 598-4444
+81-4-4812-8043
(617) 935-8335
+81-3-3839-0606
(408) 366-8509
+49-89-839910
+49-72-1751087
(503) 531-2412
(303) 279-6868
(602) 491-4311
(503) 685-1298
(719) 590-1155
+32-02-4603175
(503) 526-5465
(503) 671-9500
E-
A
DDRESS [email protected]
Inquiries about the Xilinx Alliance Program can be e-mailed to [email protected]
Changes since last issue (XCell 23) printed in color.
XILINX RELEASED SOFTWARE STATUS - FEBRUARY 1997
P
RODUCT
K
EY
C
ATEGORY
CORE XEPLD
U * XABEL-CPLD
* XACT-CPLD
Mentor
E
E
U
U
U
OrCAD
Synopsys
Viewlogic
Viewlogic
Viewlogic
XABEL
XBLOX
Verilog
XC4000EX
Cadence
Mentor
Mentor
OrCAD
OrCAD
Synopsys
Synopsys
Viewlogic
Viewlogic
Viewlogic
Viewlogic/S
Viewlogic/S
Viewlogic/S
Viewllogic/S
3rd Party Alliance
3rd Party Alliance
3rd Party Alliance
Foundation Series
Foundation Series
Foundation Series
Foundation Series
LogiCore-PCI Slave
LogiCore-PCI Master
Evaluation
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P
RODUCT
D
ESCRIPTION
P
RODUCT
F
UNCTION
XC7K Support Core Implementation
XC7K, XC9500 Support Entry/Simulation/Core
XC7K, XC9500 Support Core + Interface
8.4=A.4
Interface and Libraries
Interface and Libraries
Interface and Libraries
PROcapture
PROsim
Interface and Libraries
Interface and Libraries
Interface and Libraries
Entry,Simulation,Lib, Optimizer
Module Generator & Optimizer
2K,3K,4K,4KE,5K Lib.
Models & XNF Translator
XC4000EX Support Core Implementation
SILICON SUPPORT
2K 3K 4K/E 5K 7K 9K
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ILINX
P
ART
R
EFERENCE
N
UMBER
DS-550-xxx
DS-571-PC1
DS-560-xxx
DS-344-xxx
DS-35-PC1
DS-401-xxx
DS-390-PC1
DS-290-PC1
DS-391-xxx
DS-371-xxx
DS-380-xxx
ES-VERILOG-xxx
PR-4EX-WS
DS-CDN-STD-xxx
DS-MN8-STD-xxx
DS-MN8-ADV-xxx
DS-OR-BAS-PC1
DS-OR-STD-PC1
DS-SY-STD-xxx
DS-SY-ADV-xxx
DS-VL-BAS-PC1
DS-VL-STD-xxx
DS-VL-ADV-xxx
DS-VLS-BAS-PC1
DS-VLS-STD-PC1
DS-VLS-EXT-PC1
DS-VLS-ADV-PC1
DS-3PA-BAS-xxx
DS-3PA-STD-xxx
DS-3PA-ADV-xxx
DS-FND-BAS-PC1
DS-FND-BSV-PC1
DS-FND-STD-PC1
DS-FND-STV-PC1
LC-DI-PCIS-C
LC-DI-PCIM-C
DS-EVAL-XXX-C
C
URRENT
V
ERSION BY
P
LATFORM
PC1
6.2
SN2
4.1.
X
HP7
9.01
5.2.1
5.2.1
6.0.1
6.1.2
6.0.1
6.0.1
5.2.1
6.0.1
5.2.1
6.0.1
5.2.1
5.2.1
6.0.1
6.0.1
6.0.1
5.2.1
5.2.1
5.2.1
5.2.1
5.2.1
1.00
5.2.1
5.2.1
5.2.1
1.00
pre-release pre-release
6.0.1
6.0.1
6.0.1
6.0.1
7.00
6.0.1
6.0.1
6.0.1
7.00
6.0.1
6.0.1
7.00
6.0.2
6.0.2
6.0.2
6.0.2
1.10
1.10
2.00
5.2.1
5.2.1
7.00
5.2.1
7.00
5.2.1
7.00
5.2.1
7.00
1.10
1.10
2.00
5.2.1
5.2.1
7.00
5.2.1
7.00
5.2.1
7.00
5.2.1
7.00
1.10
1.10
2.00
5.20
5.20
na
6.0
6.0
5.20
na
6.0
5.26.0
na
6.0
6.0
6.0
na na
5.2/6.0
na
7/96
7/96
7/96
7/96 na na
01/04 na
7/96
7/96 na
7/96
7/96
7/96 na
7/96
7/96 na
2/97
2/97
2/97
2/97 na na
4/96
7/96
7/96 na
7/96
7/96
7/96
7/96
7/96
7/96
7/96
7/96 na na
L
AST
P
REVIOUS
U
PDT
V
ERSION
N
OTES
/
C
OMP
R
ELEASE
F
EATURES
7/96
7/96
7/96
7/96
7/96
7/96
5.2/6.0
6.10
6.0
5.20
6.0
5.20
PC update by request only
New version w/Win 95 to 3.11, update by request
Support for SDT+, VST+ v1.2
DA1 platform remains at v5.2
Includes PRO Series 6.1
Includes PRO Series 6.1
5.2/6.0
6.0
6.0
5.2/6.0
5.2/6.0
na na
Now available on HP7
Sun and HP
Pre-release software available to pre-determined users
No AP1 update
Customer w/v6.0 will receive v6.0.1 update
Includes DS-401 v5.2
Includes DS-401 v5.2
Customer w/v6.0 will receive v6.0.1 update
DA1 platform remains at v6.0
Currently updating in-warranty cust. w/WVO
Currently updating in-warranty cust. w/WVO
Currently updating in-warranty cust. w/WVO
Customer w/v6.0 will receive v6.0.1 update
Includes 502/550/380
Includes 502/550/380 & Foundry
Includes support for XC4000E and XC9500
Includes support for XC4000E and XC9500
Includes support for XC4000E and XC9500
Includes support for XC4000E and XC9500
Requires signed license agreement
Requires signed license agreement
PC, Sun, HP kits with v5.2.1 and v6.0.1
KEY : N=New Product E= Engineering software for in-warranty users by request only U= Update by request only * = Check BBS or FTP site.
40
FAX RESPONSE FORM-XCELL 24 1Q97
Corporate
Headquarters
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Tel: 408-559-7778
Fax: 408-559-7114
Europe
Xilinx, Ltd.
Benchmark House
203 Brooklands Road
Weybridge
Surrey KT14 0RH
United Kingdom
Tel: 44-1-932-349401
Fax: 44-1-932-349499
Japan
Xilinx, KK
Daini-Nagaoka Bldg. 2F
2-8-5, Hatchobori,
Chuo-ku, Tokyo 104
Japan
Tel: 81-3-3297-9191
Fax: 81-3-3297-9189
Asia Pacific
Xilinx Asia Pacific
Unit 4312, Tower II
Metroplaza
Hing Fong Road
Kwai Fong, N.T.
Hong Kong
Tel: 852-2424-5200
Fax: 852-2494-7159
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From: ________________________________________ Date: ____________
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Table of contents
- 1 GENERAL
- 2 The Fawcett - Getting to the Core
- 3 Guest Editorial: The Defining Year
- 6 New Look, Content for WebLINX
- 7 Customer Success Story
- 8 Upcoming Events
- 8 New Product Literature
- 8 Financial Results
- 9 Technical Training Update
- 9 1997 Spring Seminar Series
- 10 PRODUCTS - COMPONENTS
- 10 XC4062XL Debuts
- 10 Faster XC4000E-1 FPGAs
- 11 Product Discontinuance Update
- 12 Xilinx Receives QML Cert.
- 13 XC5200 Breaks $4 Barrier
- 14 DEVELOPMENT SYSTEMS
- 14 XACTstep M1 Software Released
- 14 XABEL-CPLD for Windows 95
- 15 Foundation v6.0.2 Service Pack
- 15 ProSeries with Workview Office
- 16 OrCAD to Support Interface
- 16 DSP Module Generator
- 17 USB and PCMCIA AllianceCOREs
- 17 AllianceCORE Partners Chart
- 18 LogiCORE PCI Target
- 18 Virtual Computing XC6200 Kit
- 19 HINTS & ISSUES
- 19 XC9500 Benchmarks
- 20 Trouble-Free Clock Switching
- 21 Demultiplexing 200 MHz Data
- 21 FPGA Highs and Lows
- 22 Using the HW-130
- 23 Technical Questions & Answers
- 23 Technical Support Resources
- 24 Component Availability Chart
- 26 Programming Support Charts
- 28 Alliance Program Charts
- 31 Development Systems Chart
- 32 Fax Back Form