Agilent Technologies | 16800 Series | Specifications | Agilent Technologies 16800 Series Specifications

Agilent Technologies 16800 Series Specifications
Agilent 16800 Series
Portable Logic Analyzers
Data Sheet
Features and benefits
• 250 ps resolution (4 GHz)
timing zoom to find elusive timing
problems quickly, without double
probing
• 15” display, with available touch
screen, allows you to see more
data and navigate quickly
• View Scope—time-correlated
measurements and displays of your
logic analyzer and oscilloscope
data let you effectively track down
problems across the analog and
digital portions of your design
• Eight models with
34/68/102/136/204 channels, up
to 32 M memory depth and models
with a pattern generator provide
the measurement flexibility for any
budget
• Application support for every
aspect of today’s complex
designs—FPGA dynamic probe,
digital VSA (vector signal analysis)
and broad processor and bus
support
Quickly debug, validate, and optimize your digital
system—at a price that fits your budget.
Table of Contents
Selection Guide for 16800 Series Portable Logic Analyzers ........................................................................... 3
Logic Analysis for Tracking Real-time System Operation ............................................................................... 4
Agilent 16800 Series Logic Analyzer Specifications and Characteristics .................................................... 6
A Built-in Pattern Generator Gives You Digital Stimulus and Response in a Single Instrument ........... 11
Pattern Generator Specifications and Characteristics ................................................................................... 13
Unleash the Complementary Power of a Logic Analyzer and an Oscilloscope ......................................... 22
Get Instant Insights into your Design with Multiple Views and Analysis Tools ...................................... 23
16800 Series Instrument Characteristics ......................................................................................................... 25
16800 Series Interfaces ....................................................................................................................................... 27
16800 Series Physical Characteristics .............................................................................................................. 28
16800 Series Accessories ................................................................................................................................... 29
Ordering Information ............................................................................................................................................ 31
16800 Series Probing Options ............................................................................................................................ 32
Support, Services, and Assistance .................................................................................................................... 34
2
Selection Guide for 16800 Series Portable Logic Analyzers
Characteristic
16801A, 16821A 1
Logic analyzer channels
Pattern generator channels 1
High-speed timing zoom
Maximum timing sample rate
(Half/full ch)
Maximum state clock rate
34
48
4 GHz (250 ps) with 64 K depth
1.0 GHz (1.0 ns)/500 MHz (2.0 ns)
250 MHz with Option 250
Maximum state data rate
250 Mb/s with Option 250
16802A,
16822A 1
68
48
16803A,
16823A 1
16804A
102
136
48
N/A
4 GHz (250 ps) with 64 K depth
1.0 GHz (1.0 ns)/500 MHz (2.0 ns)
16806A
204
N/A
450 MHz with Option 500
250 MHz with Option 250
500 Mb/s with Option 500
250 Mb/s with Option 250
1 M with Option 001
4 M with Option 004
16 M with Option 016
32 M with Option 032
Single-ended
Yes
Maximum memory depth (samples) 1 M with Option 001
4 M with Option 004
16 M with Option 016
32 M with Option 032
Supported signal types
Single-ended
Automated threshold/sample
Yes
position
Simultaneous eye diagrams, all
channels
Probe compatibility
40-pin cable connector
40-pin cable connector
1. Pattern generator available with 16821A, 16822A and 16823A.
Choose from eight models to get the measurement capability for your specific application.
Probes are ordered separately. Please specify probes when ordering to ensure the correct connection between your logic
analyzer, pattern generator, and the device under test.
Characteristic
Maximum clock
Data channels
Memory depth in vectors
Logic levels supported
16821A, 16822A, 16823A
Half channel
Full channel
300 MHz
180 MHz
24
48
16 M
8M
5 V TTL, 3-state TTL, 3-state TTL/CMOS, 3-state 1.8 V, 3-state 2.5 V,
3-state 3.3 V, ECL, 5 V PECL, 3.3 V LVPECL, LVDS
Models with a built-in pattern generator give you more measurement flexibility.
3
Logic Analysis for Tracking Real-time System Operation
Agilent 16800 Series portable logic
analyzers offer the performance,
applications, and usability your digital
development team needs to quickly
debug, validate, and optimize your
digital system—at a price that fits
your budget.
The logic analyzer’s timing and state
acquisition gives you the power to:
• Accurately measure precise timing
relationships using 4 GHz (250 ps)
timing zoom with 64 K depth
• Find anomalies separated in time
with memory depths upgradeable
to 32 M
• Buy what you need today and
upgrade in the future. 16800 Series
logic analyzers come with independent upgrades for memory depth
and state speed
• Sample synchronous buses
accurately and confidently using
eye finder. Eye finder automatically adjusts threshold and setup
and hold to give you the highest
confidence in measurements on
high-speed buses
• Track problems from symptom
to root cause across several
measurement modes by viewing
time-correlated data in waveform/
chart, listing, inverse assembly,
source code, or compare display
Figure 1. With eight models to choose from, you can get a logic analyzer with
measurement capabilities that meet your needs.
• Set up triggers quickly and confidently with intuitive, simple, quick,
and advanced triggering. This
capability combines new trigger
functionality with an intuitive user
interface
• Access the signals that hold the
key to your system’s problems
with the industry’s widest range of
probing accessories with capacitive loading down to 0.7 pF
• Monitor and correlate multiple
buses with split analyzer capability,
which provides single and multibus
support (timing, state, timing/state
or state/state configurations)
4
Accurately measure precise
timing relationships
16800 Series logic analyzers let you
make accurate high-speed timing
measurements with 4 GHz (250 ps)
high-speed timing zoom. A parallel
acquisition architecture provides
high-speed timing measurements
simultaneously through the same
probe used for state or timing measurements. Timing zoom stays active
all the time with no tradeoffs. View
data at high resolution over longer
periods of time with 64 K-deep timing
zoom.
Logic Analysis for Tracking Real-time System Operation (continued)
Automate measurement setup
and quickly gain diagnostic
clues
16800 Series logic analyzers make it
easy for you to get up and running
quickly by automating your measurement setup process. In addition, the
logic analyzer’s setup/hold window
(or sampling position) and threshold
voltage settings are automatically
determined so you can capture data
on high-speed buses with the highest
accuracy. Auto Threshold and Sample
Position mode allow you to...
• Obtain accurate and reliable measurements
• Save time during measurement
setup
• Gain diagnostic clues and identifyproblem signals quickly
• Scan all signals and buses simultaneously or just a few
• View results as a composite display or as individual signals
• See skew between signals and
buses
• Find and fix inappropriate clock
thresholds
• Measure data valid windows
• Identify signal integrity problems
related to rise times, fall times,
data valid window widths
Figure 2. Identify problem signals quickly by viewing eye diagrams across all buses and
signals simultaneously.
Identify problem signals
over hundreds of channels
simultaneously
As timing and voltage margins
continue to shrink, confidence in
signal integrity becomes an increasingly vital requirement in the design
validation process. Eye scan lets you
acquire signal integrity information on
all the buses in your design, under a
wide variety of operating conditions,
in a matter of minutes. Identify
problem signals quickly for further
investigation with an oscilloscope.
Results can be viewed for each
individual signal or as a composite of
multiple signals or buses.
5
Extend the life of your
equipment
Easily upgrade your 16800 Series
logic analyzer. “Turn on” additional
memory depth and state speed when
you need more. Purchase the
capability you need now, then
upgrade as your needs evolve.
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
Channel count per measurement mode
16801A/16821A
16802A/16822A
16803A/16823A
16804A
16806A
State analysis 1
32 data + 2 clocks
64 data + 4 clocks
98 data + 4 clocks
Conventional timing
Transitional timing for
sample rates < 500 MHz
Transitional timing for
500 MHz sample rate
34
34
68
68
102
102
132 data +
4 clocks
136
136
200 data +
4 clocks
204
204
–
34
68
102
170
1. Unused clock channels can be used as data channels.
Timing zoom
(Simultaneous state and timing without double probing—All channels, all the time)
Timing analysis sample rate
Time interval accuracy
Within a pod pair
Between pod pairs
Memory depth
Trigger position
Minimum data pulse width
4 GHz (250 ps)
± (1.0 ns + 0.01% of time interval reading)
± (1.75 ns +0.01% of time interval reading)
64 K samples
Start, center, end, or user-defined
1 ns
Other
Voltage threshold
Threshold accuracy
–5 V to 5 V (10 mV increments)
± 50 mV + 1% of setting
6
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
(continued)
State (synchronous) analysis mode
Option 250
Option 500 3
(Available on 16802A, 16803A, 16804A,
16806A, 16822A and 16823A)
tWidth* 1
tSetup
tHold
tSample range 2
tSample adjustment resolution
Maximum state data rate on each channel
Memory depth 4
1.5 ns
0.5 tWidth
0.5 tWidth
–3.2 ns to +3.2 ns
80 ps typical
250 Mb/s
Option 001: 1 M samples
Option 004: 4 M samples
Option 016: 16 M samples
Option 032: 32 M samples
2 (1 for 16801A or 16821A)
4 (2 for 16801A or 16821A)
4 (2 for 16801A or 16821A)
4.0 ns
1 ns
1 ns
4.0 ns
1.5 ns
0.5 tWidth
0.5 tWidth
–3.2 ns to +3.2 ns
80 ps typical
500 Mb/s
Option 001: 1 M samples
Option 004: 4 M samples
Option 016: 16 M samples
Option 032: 32 M samples
1
1
N/A
2.0 ns
N/A
N/A
N/A
1.0 ns
1.0 ns
1.0 ns
2.0 ns
Number of independent analyzers 5
Number of clocks 6
Number of clock qualifiers 6
Minimum time between active clock edges *, 7
Minimum master-to-slave clock time
Minimum slave-to-master clock time
Minimum slave-to-slave clock time
Minimum state clock pulse width
• Single edge
• Multiple edge
*
Items marked with an asterisk (*) are specifications. All others are characteristics.
“Typical” represents the average or median value of the parameter based on measurements from a significant number of units.
1. Minimum eye width in system under test.
2. Sample positions are independently adjustable for each data channel input. A negative sample position causes the input to be synchronously sampled by that amount before each active clock edge. A positive sample position causes the input to be synchronously
sampled by that amount after each active clock edge. A sampling position of zero causes the input to be synchronously sampled
coincident with each clock edge.
3. Use of eye finder is recommended in 450 MHz and 500 Mb/s state mode.
4. In 250 Mb/s state mode, with all pods assigned, memory depth is half the maximum memory depth. With one pod pair (34 channels)
unassigned, the memory depth is full. One pod pair (34 channels) must remain unassigned for time tags in 500 Mb/s state mode.
5. Independent analyzers may be either state or timing. When the 500 Mb/s state mode is selected, only one analyzer may be used.
6. In the 250 Mb/s state mode, the total number of clocks and qualifiers is 4 (2 for 16801A or 16821A).
7. Tested with input signal Vh = +1.3 V, Vl = +0.7 V, threshold = +1.0 V, tr/tf = 180 ps ± 30 ps (10%, 90%).
tWidth
Individual
Data Channel
vHeight
Data Eye
tSetup tHold
vThreshold
OV
Sampling Position
tSample
Clock Channel
7
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
(continued)
State (synchronous) analysis mode
Option 250
Option 500
(Available on 16802A, 16803A, 16804A,
16806A, 16822A and 16823A)
Clock qualifier setup time
Clock qualifier hold time
Time tag resolution
Maximum time count between stored
states
Maximum trigger sequence speed
Maximum trigger sequence levels
Trigger sequence level branching
Trigger position
Trigger resources
500 ps
0
2 ns
32 days
N/A
N/A
1.5 ns
32 days
250 MHz
16
Arbitrary 4-way if/then/else
Start, center, end, or user-defined
• 16 patterns evaluated as =, =/, >, ≥, <, ≤
• 14 double-bounded ranges evaluated as
in range, not in range
• 1 timer for every 34 channels
• 2 global counters
• 1 occurrence counter per sequence level
• 4 flags
Arbitrary Boolean combinations
• Go To
• Trigger, send e-mail, and fill memory
• Trigger and Go To
• Store/don’t store sample
• Turn on/off default storing
• Timer start/stop/pause/resume
• Global counter increment/decrement/
reset
• Occurrence counter reset
• Flag set/clear
Default (global) and per sequence level
2E+24
2E+24
Smaller of 128 bits or maximum number of
channels
Smaller of 64 bits or maximum number of
channels
60 ns to 2199 seconds
2 ns
± (5 ns +0.01%)
60 ns
500 MHz
16
2-way if/then/else
Start, center, end, or user-defined
• 14 patterns evaluated as =, =/, >, ≥, <, ≤
• 7 double-bounded ranges evaluated as in
range, not in range
• 1 occurrence counter per sequence level
• 4 flags
Trigger resource conditions
Trigger actions
Store qualification
Maximum global counter
Maximum occurrence counter
Maximum pattern width
Maximum range width
Timers range
Timer resolution
Timer accuracy
Timer reset latency
8
Arbitrary Boolean combinations
• Go To
• Trigger and fill memory
Default (global)
N/A
2E+24
Smaller of 128 bits or maximum number of
channels
Smaller of 64 bits or maximum number of
channels
N/A
N/A
N/A
N/A
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
(continued)
Timing (asynchronous)
analysis mode
Conventional timing
Transitional timing 2
Sample rate on all channels
Sample rate in half channel mode
Number of independent analyzers 1
Sample period (half channel)
Minimum sample period (full channel)
Minimum data pulse width
Time interval accuracy
500 MHz
1 GHz
2 (1 for 16801A or 16821A)
1.0 ns
2.0 ns
1 sample period + 1.0 ns
± (1 sample period + 1.25 ns + 0.01% of time
interval reading)
Option 001: 1 M samples
Option 004: 4 M samples
Option 016: 16 M samples
Option 032: 32 M samples
Option 001: 2 M samples
Option 004: 8 M samples
Option 016: 32 M samples
Option 032: 64 M samples
250 MHz
16
Arbitrary 4-way if/then/else
Start, center, end, or user-defined
500 MHz
N/A
2 (1 for 16801A or 16821A)
N/A
2.0 ns
1 sample period + 1.0 ns
± (1 sample period + 1.25 ns + 0.01% of
time interval reading)
Option 001: 1 M samples
Option 004: 4 M samples
Option 016: 16 M samples
Option 032: 32 M samples
Memory depth in full channel mode
Memory depth in half channel mode
Maximum trigger sequence speed
Maximum trigger sequence levels
Trigger sequence level branching
Trigger position
N/A
250 MHz
16
Arbitrary 4-way if/then/else
Start, center, end, or user-defined
1. Independent analyzers may be either state or timing. When the 500 Mb/s state mode is selected, only one analyzer may be used.
2. Transitional timing speed and memory depth are halved unless a spare pod pair (34 channels) is unassigned.
9
Agilent 16800 Series Logic Analyzer Specifications and Characteristics
(continued)
Timing (asynchronous)
analysis mode
Conventional timing
Transitional timing
Trigger resources
• 16 patterns evaluated as =, =/, >, ≥, <, ≤
• 14 double-bounded ranges evaluated as
in range, not in range
• 3 edge/glitch
• 1 timer for every 34 channels (no timer
for 16801A or 16821A)
• 2 global counters
• 1 occurrence counter per sequence level
• 4 flags
Arbitrary Boolean combinations
• Go To
• Trigger, send e-mail, and fill memory
• Trigger and Go To
• Turn on/off default storing
• Timer start/stop/pause/resume
• Global counter increment/decrement/
reset
• Occurrence counter reset
• Flag set/clear
2E+24
2E+24
32 bits
Smaller of 128 bits or maximum number of
channels
60 ns to 2199 seconds
2 ns
± (5 ns +0.01%)
4.0 ns to 67 ms in 4.0 ns increments
8.0 ns to 67 ms in 4.0 ns increments
60 ns
• 15 patterns evaluated as =, =/, >, ≥, <, ≤
• 14 double-bounded ranges evaluated as in
range, not in range
• 3 edge/glitch
• 1 timer for every 34 channels (no timer for
16801A or 16821A)
• 2 global counters
• 1 occurrence counter per sequence level
• 4 flags
Arbitrary Boolean combinations
• Go To
• Trigger, send e-mail, and fill memory
• Trigger and Go To
• Turn on/off default storing
• Timer start/stop/pause/resume
• Global counter increment/decrement/
reset
• Occurrence counter reset
• Flag set/clear
2E+24
2E+24
32 bits
Smaller of 128 bits or maximum number of
channels
60 ns to 2199 seconds
2 ns
± (5 ns +0.01%)
4.0 ns to 67 ms in 4.0 ns increments
8.0 ns to 67 ms in 4.0 ns increments
60 ns
Trigger resource conditions
Trigger actions
Maximum global counter
Maximum occurrence counter
Maximum range width
Maximum pattern width
Timer value range
Timer resolution
Timer accuracy
Greater than duration
Less than duration
Timer reset latency
10
A Built-in Pattern Generator Gives You Digital Stimulus and Response in a
Single Instrument
Selected 16800 Series models
(16821A, 16822A and 16823A) also
include a 48-channel pattern generator to drive down risk early in product
development. With a pattern generator you can:
• Substitute for missing boards,
integrated circuits (ICs) or buses
instead of waiting for missing
pieces
• Write software to create
infrequently encountered test
conditions and verify that the code
works – before complete hardware
is available
• Generate patterns necessary to put
a circuit in a desired state, operate
the circuit at full speed or step the
circuit through a series of states
• Create a circuit initialization
sequence
Agilent 16800 Series portable logic
analyzers with a pattern generator
offer a variety of features that make
it easier for you to create digital
stimulus tests.
Vectors up to 48 bits wide
Vectors are defined as a “row” of
labeled data values, with each data
value from one to 48 bits wide. Each
vector is output on the rising edge of
the clock. Create stimulus patterns
for the widest buses in your system.
Figure 3. Models with a built-in pattern generator give you more measurement flexibility.
Depth up to 16 M vectors
With the pattern generator, you can
load and run up to 16 M vectors of
stimulus. Depth on this scale is most
useful when coupled with powerful
stimulus generated by electronic
design automation tools, such as
SynaptiCAD’s WaveFormer and
VeriLogger. These tools create stimulus using a combination of graphically
drawn signals, timing parameters
that constrain edges, clock signals,
and timing and Boolean equations for
describing complex signal behavior.
The stimulus also can be created
from design simulation waveforms.
The SynaptiCAD tools allow you to
convert .VCD files into .PGB files
directly, offering you an integrated
solution that saves you time.
Synchronized clock output
You can output data synchronized to
either an internal or external clock.
The external clock is input via a clock
pod, and has no minimum frequency
(other than a 2 ns minimum high
time).
The internal clock is selectable
between 1 MHz and 300 MHz in
1-MHz steps. A Clock Out signal is
available from the clock pod and can
be used as an edge strobe with a
variable delay of up to 8 ns.
11
Initialize (INIT) block for
repetitive runs
When running repetitively, the vectors in the initialize (init) sequence
are output only once, while the main
sequence is output as a continually repeating sequence. This “init”
sequence is very useful when the
circuit or subsystem needs to be initialized. The repetitive run capability
is especially helpful when operating
the pattern generator independent of
the logic analyzer.
“Send Arm out to…”
coordinates activity with the
logic analyzer
Verify how your system responds
to a specific stimulus sequence by
arming the logic analyzer from the
pattern generator. A “Send Arm out
to…” instruction acts as a trigger
arming event for the logic analyzer
or other test equipment to begin
measurements. Arm setup and trigger
setup of the logic analyzer determines
the action initiated by “Send Arm out
to… .”
A Built-in Pattern Generator Gives You Digital Stimulus and Response in a
Single Instrument (continued)
“Wait for External Event…” for
input pattern
Convenient data entry and
editing feature
The clock pod also accepts a 3-bit
input pattern. These inputs are levelsensed so that any number of “Wait
for External Event” instructions can
be inserted into a stimulus program.
Up to four pattern conditions can
be defined from the OR-ing of the
eight possible 3-bit input patterns. A
“Wait for External Event” also can
be defined to wait for an Arm. This
Arm signal can come from the logic
analyzer. “Wait for External Event…”
allows you to execute a specific
stimulus sequence only when the
defined external event occurs.
You can conveniently enter patterns
in hex, octal, binary, decimal, and
signed decimal (two’s complement)
bases. To simplify data entry, you
can view the data associated with an
individual label with multiple radixes.
Delete, Insert, and Copy commands
are provided for easy editing. Fast
and convenient Pattern Fills give
the programmer useful test patterns
with a few key strokes. Fixed, Count,
Rotate, Toggle, and Random patterns
are available to help you quickly create a test pattern, such as “walking
ones.” Pattern parameters, such as
step size and repeat frequency, can
be specified in the pattern setup.
Simplify creation of stimulus
programs with user-defined
macros and loops
User macros permit you to define a
pattern sequence once, then insert
the macro by name wherever it is
needed. Passing parameters to the
macro will allow you to create a more
generic macro. For each call to the
macro you can specify unique values
for the parameters.
Loops enable you to repeat a defined
block of vectors for a specified
number of times. Loops and macros
can be nested, except that a macro
cannot be nested within another
macro. At compile time, loops and
macros are expanded in memory to a
linear sequence.
ASCII input file format: your
design tool connection
The pattern generator supports an
ASCII file format to facilitate connectivity to other tools in your design
environment. Because the ASCII format does not support the instructions
listed earlier, they cannot be edited
into the ASCII file. User macros and
loops also are not supported, so the
vectors need to be fully expanded in
the ASCII file. Many design tools will
generate ASCII files and output the
vectors in this linear sequence. Data
must be in hex format, and each label
must represent a set of contiguous
output channels.
Configuration
The pattern generator operates with
the clock pods, data pods, and lead
sets described later in this document.
At least one clock pod and one data
pod must be selected to configure
a functional system. You can select
from a variety of pods to provide the
signal source needed for your logic
devices. The data pods, clock pods
and data cables use standard connectors. The electrical characteristics
of the data cables are described for
users with specialized applications
who want to avoid the use of a data
pod.
Direct connection to your
target system
You can connect the pattern generator pods directly to a standard
connector on your target system. Use
a 3M brand #2520 Series or similar
connector. The clock or data pods
will plug right in. Short, flat cable
jumpers can be used if the clearance
around the connector is limited.
Use a 3M #3365/20, or equivalent,
ribbon cable; a 3M #4620 Series or
equivalent connector on the pattern
generator pod end of the cable, and
a 3M #3421 Series or equivalent
connector at your target system end
of the cable.
Probing accessories
The probe tips of the Agilent 10474A,
10347A, 10498A, and E8142A lead
sets plug directly into any 0.1-inch
grid with 0.026-inch to 0.033-inch
diameter round pins or 0.025-inch
square pins. These probe tips work
with the Agilent 5090-4356 surface
mount grabbers and with the Agilent
5959-0288 through-hole grabbers,
providing compatibility with industry
standard pins.
12
Pattern Generator Specifications and Characteristics
(16821A, 16822A, and 16823A)
Pattern generator characteristics
Maximum memory depth
Number of output channels at > 180 MHz and ≤ 300 MHz clock
Number of output channels at ≤ 180 MHz clock
Number of different macros
Maximum number of lines in a macro
Maximum number of parameters in a macro
Maximum number of macro invocations
Maximum loop count in a repeat loop
Maximum number of repeat loop invocations
Maximum number of “Wait” event patterns
Number of input lines to define a pattern
Maximum width of a label
Maximum number of labels
Maximum number of vectors in all formats
Minimum number of vectors in binary format when loading into hardware
16 MVectors
24
48
Limited only by the pattern generator’s available
memory depth
1000
4
3
48 bits
Limited only by system memory
16 MVectors
4096
Lead set characteristics
Agilent 10474A 8-channel probe lead set 1
Agilent 10347A 8-channel probe lead set
Agilent 10498A 8-channel probe lead set 1
Agilent E8142A 8-channel probe lead set
Provides most cost effective lead set for clock and data pods. Grabbers are not included.
Lead wire length is 12 inches.
Provides 50 Ω coaxial lead set for unterminated signals, required for 10465A ECL Data
Pod (unterminated). Grabbers are not included.
Provides most cost effective lead set for clock and data pods. Grabbers are not included.
Lead wire length is 6 inches.
Provides lead set for LVDS clock and data pods. Grabbers are not included. Lead wire
length is 6 inches.
1. For all clock and data pods except 10465A unterminated ECL Data Pod and E8140A/E8141A clock and data pods.
13
Pattern Generator Specifications and Characteristics
(16821A, 16822A, and 16823A) (continued)
Data pod characteristics
Note: Data pod output parametrics depend on the output driver and the impedance load of the target system. Check the
device data book for the specific drivers listed for each pod.
Agilent 10461A TTL data pod
Output type
Maximum clock
Skew 1
Recommended lead set
ECL/TTL
10H125
10H125 with 100 Ω series
200 MHz
Typical < 2 ns; worst case = 4 ns
Agilent 10474A
Agilent 10462A 3-state TTL/CMOS data pod
Output type
3-state enable
Maximum clock
Skew 1
Recommended lead set
74ACT11244
Maximum clock
Skew 1
Recommended lead set
100 Ω
74ACT11244 with 100 Ω series;
10H125 on non 3-state channel 7 2
Negative true, 100 KΩ to GND,
enabled on no connect
100 MHz
Typical < 4 ns; worst case = 12 ns
Agilent 10474A
Agilent 10464A ECL data pod (terminated)
Output type
100 Ω
42 Ω
10H115
10H115 with 330 Ω pulldown,
47 Ω series
300 MHz
Typical < 1 ns; worst case = 2 ns
Agilent 10474A
348 Ω
– 5.2 V
1. Typical skew measurements made at pod connector with
approximately 10 pF/50 KΩ load to GND; worst case skew
numbers are a calculation of worst case conditions through
circuits. Both numbers apply to any channel within the
pattern generator.
2. Channel 7 on the 3-state pods has been brought out in parallel
as a non 3-state signal. By looping this output back into the
3-state enable line, the channel can be used as a 3-state
enable.
14
Pattern Generator Specifications and Characteristics
(16821A, 16822A, and 16823A) (continued)
Agilent 10465A ECL data pod (unterminated)
Output type
Maximum clock
Skew 1
Recommended lead set
10H115
10H115 (no termination)
300 MHz
Typical < 1 ns; worst case = 2 ns
Agilent 10347A
100 Ω
Agilent 10466A 3-state TTL/3.3 volt data pod
Output type
3-state enable
Maximum clock
Skew 1
Recommended lead set
74LVT244 with 100 Ω series;
10H125 on non 3-state channel 7 2
Negative true, 100 KΩ to GND,
enabled on no connect
200 MHz
Typical < 3 ns; worst case = 7 ns
Agilent 10474A
74LVT244
Agilent 10469A 5 volt PECL data pod
Output type
Maximum clock
Skew 1
Recommended lead set
100EL90
100EL90 (5 V) with 348 ohm pulldown
to ground and 42 ohm in series
300 MHz
Typical < 500 ps; worst case = 1 ns
Agilent 10498A
42 Ω
348 Ω
Agilent 10471A 3.3-volt LVPECL data pod
Output type
100LVEL90 (3.3 V) with 215 Ω
pulldown to ground and 42 Ω in
series
Maximum clock
300 MHz
Skew 1
Typical < 500 ps; worst case =
1 ns
Recommended lead
Agilent 10498A
set
100LVEL90
42 Ω
215 Ω
1. Typical skew measurements made at pod connector with
approximately 10 pF/50 KΩ load to GND; worst case skew
numbers are a calculation of worst case conditions through
circuits. Both numbers apply to any channel within the
pattern generator.
2. Channel 7 on the 3-state pods has been brought out in parallel
as a non 3-state signal. By looping this output back into the
3-state enable line, the channel can be used as a 3-state
enable.
15
Pattern Generator Specifications and Characteristics
(16821A, 16822A, and 16823A) (continued)
Agilent 10473A 3-state 2.5-volt data pod
Output type
3-state enable
Maximum clock
Skew 1
Recommended lead set
74AVC16244
74AVC16244
Negative true, 38 KΩ to GND,
enabled on no connect
300 MHz
Typical < 1.5 ns; worst case = 2 ns
Agilent 10498A
Agilent 10476A 3-state 1.8-volt data pod
Output type
3-state enable
Maximum clock
Skew 1
Recommended lead set
74AVC16244
74AVC16244
Negative true, 38 KΩ to GND,
enabled on no connect
300 MHz
Typical < 1.5 ns; worst case = 2 ns
Agilent 10498A
Agilent 10483A 3-state 3.3-volt data pod
Output type
3-state enable
Maximum clock
Skew 1
Recommended lead set
74AVC16244
74AVC16244
Negative true, 38 KΩ to GND,
enabled on no connect
300 MHz
Typical < 1.5 ns; worst case = 2 ns
Agilent 10498A
65LVDS389
ENABLE
Agilent E8141A LVDS data pod
Output type
3-state enable
Maximum clock
Skew
Recommended lead set
65LVDS389 (LVDS data lines)
10H125 (TTL non-3-state channel 7)
Positive true TTL; no
connect=enabled
300 MHz
Typical < 1 ns; worst case = 2 ns
E8142A
LVDS DATA OUT
10 KΩ
3.3 V
1. Typical skew measurements made at pod connector with
approximately 10 pF/50 KΩ load to GND; worst case skew
numbers are a calculation of worst case conditions through
circuits. Both numbers apply to any channel within the
pattern generator.
16
3-STATE IN TTL
Pattern Generator Specifications and Characteristics
(16821A, 16822A, and 16823A) (continued)
Data cable characteristics without a data pod
The pattern generator data cables without a data pod provide an ECL terminated
(1 KΩ to –5.2 V) differential signal (from a type 10E156 or 10E154 driver). These
are usable when received by a differential receiver, preferably with a 100 Ω
termination across the lines. These signals should not be used single ended due
to the slow fall time and shifted voltage threshold (they are not ECL compatible).
–3.25 V
470 Ω
10E156
Differential
Output
or
10E154
470 Ω
–3.25 V
Pattern generator cable pin outs
Data cable (Pod end)
Clock cable (Pod end)
17
Pattern Generator Specifications and Characteristics
(16821A, 16822A, and 16823A) (continued)
Clock cable characteristics without a clock pod
The pattern generator clock cables without a clock pod provide an ECL terminated (1 KΩ to –5.2 V) differential signal (from a type 10E164 driver). These are
usable when received by a differential receiver, preferably with a 100 Ω termination across the lines. These signals should not be used single ended due to the
slow fall time and shifted voltage threshold (they are not ECL compatible).
7
10E116
100 Ω
Clock in
8
11, 13, 15
10H125
100 Ω
Wait 1, 2, 3 IN
12, 14, 16
–3.25 V
215 Ω
Clock out
10E164
215 Ω
–3.25 V
18
Pattern Generator Specifications and Characteristics
(16821A, 16822A, and 16823A) (continued)
Clock pod characteristics
47 Ω
10460A TTL clock pod
CLKout
10H125
Clock output type
10H125 with 47 Ω series; true &
inverted
Clock output rate
100 MHz maximum
Clock out delay
Approximately 8 ns total in 14 steps
Clock input type
TTL – 10H124
Clock input rate
DC to 100 MHz
Pattern input type
TTL – 10H124 (no connect is logic 1)
Clock-in to clock-out
Approximately 30 ns
Pattern-in to recognition Approximately 15 ns + 1 clk period
Recommended lead set Agilent 10474A
10463A ECL clock pod
CLKin
CLKin
10H116
Clock output type
10H116 differential unterminated;
and differential with 330 Ω to –5.2 V
and 47 Ω series
Clock output rate
300 MHz maximum
Clock out delay
Approximately 8 ns total in 14 steps
Clock input type
ECL – 10H116 with 50 KΩ to –5.2 V
Clock input rate
DC to 300 MHz
Pattern input type
ECL – 10H116 with 50 KΩ
(no connect is logic 0)
Clock-in to clock-out
Approximately 30 ns
Pattern-in to recognition Approximately 15 ns + 1 clk period
Recommended lead set Agilent 10474A
VBB
50 kΩ
–5.2 V
–5.2 V
330 W
47 Ω
10H116
10468A 5-volt PECL clock pod
Clock output type
WAIT
10H124
100EL90
100EL90 (5 V) with 348 Ω pulldown
to ground and 42 Ω in series
42 Ω
CLKout
CLKout
348 Ω
Clock output rate
Clock out delay
Clock input type
Clock input rate
Pattern input type
300 MHz maximum
Approximately 8 ns total in 14 steps
100EL91 PECL (5 V), no termination
DC to 300 MHz
100EL91 PECL (5 V), no termination
(no connect is logic 0)
Clock-in to clock-out
Approximately 30 ns
Pattern-in to recognition Approximately 15 ns + 1 clk period
Recommended lead set Agilent 10498A
100EL91
19
CLKin
Pattern Generator Specifications and Characteristics
(16821A, 16822A, and 16823A) (continued)
10470A 3.3-volt LVPECL clock pod
Clock output type
Clock output rate
Clock out delay
Clock input type
Clock input rate
Pattern input type
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
100LVEL90
100LVEL90 (3.3 V) with 215 Ω
pulldown to ground and 42 Ω in
series
300 MHz maximum
Approximately 8 ns total in 14 steps
100LVEL91 LVPECL (3.3 V),
no termination
DC to 300 MHz
100LVEL91 LVPECL (3.3 V),
no termination (no connect is logic
0)
Approximately 30 ns
Approximately 15 ns + 1 clk period
Agilent 10498A
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
CLKin
100LVEL91
74AVC16244
74AVC16244
200 MHz maximum
Approximately 8 ns total in 14 steps
74AVC16244 (3.6 V max)
DC to 200 MHz
74AVC16244 (3.6 V max; no connect
is logic 0)
Approximately 30 ns
Approximately 15 ns + 1 clk period
Agilent 10498A
74AVC16244
10475A 1.8-volt clock pod
Clock output type
Clock output rate
Clock out delay
Clock input type
Clock input rate
Pattern input type
CLKout
215 Ω
10472A 2.5-volt clock pod
Clock output type
Clock output rate
Clock out delay
Clock input type
Clock input rate
Pattern input type
42 Ω
74AVC16244
74AVC16244
200 MHz maximum
Approximately 8 ns total in 14 steps
74AVC16244 (3.6 V max)
DC to 200 MHz
74AVC16244 (3.6 V max; no connect
is logic 0)
Approximately 30 ns
Approximately 15 ns + 1 clk period
Agilent 10498A
74AVC16244
20
CLKout
WAIT
CLKin
CLKout
WAIT
CLKin
Pattern Generator Specifications and Characteristics
(16821A, 16822A, and 16823A) (continued)
10477A 3.3-volt clock pod
Clock output type
Clock output rate
Clock out delay
Clock input type
Clock input rate
Pattern input type
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
CLKout
74AVC16244
74AVC16244
200 MHz maximum
Approximately 8 ns total in 14 steps
74AVC16244 (3.6 V max)
DC to 200 MHz
74AVC16244 (3.6 V max; no connect
is logic 0)
Approximately 30 ns
Approximately 15 ns + 1 clk period
Agilent 10498A
WAIT
74AVC16244
CLKin
E8140A LVDS clock pod
Clock output type
Clock output rate
Clock out delay
Clock input type
Clock input rate
Pattern input type
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
65LVDS179 (LVDS) and 10H125 (TTL)
200 MHz maximum (LVDS and TTL)
Approximately 8 ns total in 14 steps
65LVDS179 (LVDS with 100 Ω)
DC to 150 MHz (LVDS)
10H124 (TTL) (no connect = logic 1)
Approximately 30 ns
Approximately 15 ns + 1 clk period
Agilent 10498A
10H125
CLK OUT TTL
CLK OUT LVDS
65LBDS179
CLK IN LVDS
65LVDS179
100 Ω
CLK IN LVDS
10H124
21
WAIT IN TTL
Unleash the Complementary Power of a Logic Analyzer and an Oscilloscope
Seamless scope integration
with View Scope
Easily make time-correlated
measurements between Agilent
logic analyzers and oscilloscopes.
The time-correlated logic analyzer
and oscilloscope waveforms are
integrated into a single logic analyzer
waveform display for easy viewing
and analysis. You can also trigger the
oscilloscope from the logic analyzer
(or vice versa), automatically de-skew
the waveforms and maintain marker
tracking between the two instruments. Perform the following more
effectively:
• Validate signal integrity
• Track down problems caused by
signal integrity
• Validate correct operation of A/D
and D/A converters
• Validate correct logical and timing
relationships between the analog
and digital portions of a design
Connection
The Agilent logic analyzer and oscilloscope can be physically connected
with standard BNC and LAN connections. Two BNC cables are connected
for cross triggering, and the LAN
connection is used to transfer data
between the instruments. The View
Scope correlation software is standard in the logic analyzer’s application software version 3.50 or higher.
The View Scope software includes:
• Ability to import some or all of the
captured oscilloscope waveforms
Figure 4. View Scope seamlessly integrates your scope and logic analyzer waveforms into
a single display.
Feature
Benefit
Automated setup
Quickly get to your first measurement using the logic analyzer’s
Help wizard for easy setup, regardless of which supported
Agilent oscilloscope you connect to.
Instantly validate the logical and timing relationships between
the analog and digital portions of your design. View oscilloscope
and logic analyzer waveforms integrated into a single logic
analyzer waveform display.
Save time and gain confidence in measurement results with
measurements that are automatically de-skewed in time.
Integrated
waveform display
Automatic
measurement
de-skew
Cross trigger the
logic analyzer and
oscilloscope
Tracking markers
Start your debug approach from either the analog or digital
domain with the flexibility to trigger the oscilloscope from the
logic analyzer (or vice versa).
Precisely relate information on the oscilloscope’s display to the
corresponding point in time on the logic analyzer display with
tracking markers. The oscilloscope’s time markers automatically
track adjustments of the logic analyzer's global markers.
Table 1. Key features and benefits of integrating Agilent oscilloscope and logic analyzer
capabilities.
Compatibility
Agilent logic
analyzers
Agilent
oscilloscopes
16800 Series portable logic analyzers
16900 Series modular logic analysis systems
InfiniiVision 2000 X-Series, 3000 X-Series, 5000 Series,
6000 Series, 7000 Series
Infiniium 9000 Series, 90000A Series, 90000 X-Series,
90000 Q-Series
• Auto scaling of the scope waveforms for the best fit in the logic
analyzer display
22
Get Instant Insights into your Design with Multiple Views and Analysis Tools
Acquisition and analysis tools
provide rapid insight into your
toughest debug problems
You have unique measurement and
analysis needs. When you want to
understand what your target is doing
and why, you need acquisition and
analysis tools that rapidly consolidate
data into displays that provide insight
into your system’s behavior.
Figure 5. Perform in-depth time, frequency and modulation domain analysis on your
digital baseband and IF signals with Agilent’s 89600 Vector Signal Analysis software.
Optional analysis and automated measurement packages
B4655A FPGA dynamic probe
89601A-300 digital vector signal analysis,
hardware connectivity for logic analyzers
B4601C serial-to-parallel analysis package
B4606A advanced customization
environment—development and runtime
package
B4607A advanced customization
environment—runtime package
B4608A ASCII remote programming
interface
B4610A data import package
B4630A MATLAB® connectivity and
analysis package
Gain unprecedented visibility into your FPGA’s internal activity. Make incremental
real-time measurements in seconds without stopping the FPGA, changing the design or
modifying design timing. Quickly set up the logic analyzer with automatic pin mapping
and signal bus naming by leveraging work you did in your design environment.
www.agilent.com/find/fpga
Perform time-domain, spectrum, and modulation quality analysis on digital Baseband
and IF signals.
www.agilent.com/find/dvsa
Eliminate the tedious, time-consuming, and error-prone task of sifting through
thousands of analysis package serial bits by looking at long vertical columns of captured
1’s and 0’s. The B4601C serial-to-parallel analysis package is general-purpose software
that allows easy viewing and analysis of serial data.
Tailor your logic analyzer interface with a wide range of control, analysis and display
capabilities specific to your measurement application. Create integrated dialogs,
graphical displays and analysis functions to quickly manipulate measurement data into
a format that provides additional insight and answers.
www.agilent.com/find/logic-customview
Run the macros and graphical views created with a B4606A development package or
obtain and run a variety of commonly requested tools from Agilent and it's partners to
help customize your measurement environment.
Remotely control a 16900-, 16800-, 1680-, or 1690-Series logic analysis system by
issuing ASCII commands. This interface is designed to be as similar as possible to the
RPI on the 16700 Series logic analysis system, so that you can reuse existing programs.
Requires either B4606A or B4607A to be enabled. You can also use the B4606A to
customize and add RPI commands.
Use the logic analyzer GUI to view data obtained from tools other than a logic analyzer.
Make an easy connection to MATLAB and transfer your logic analyzer measurement
data for processing. Display the results on the logic analyzer in an XY scattergram chart.
23
Get Instant Insights into your Design with Multiple Views and Analysis Tools
(continued)
Save time analyzing your unique design with a turnkey setup
Agilent Technologies and our partners provide an extensive range of bus and
processor analysis probes. They provide non-intrusive, full-speed, real-time
analysis to accelerate your debugging process.
• Save time making bus- and processor-specific measurements with application
specific analysis probes that quickly and reliably connect to your device under
test
• Display processor mnemonics or bus cycle decode
• Get support for a comprehensive list of industry-standard processors and
buses
Available device support
Microprocessors/
microcontrollers
FPGAs
I/O buses
Memory buses
Serial buses
Graphics buses
AMD, Analog Devices,
ARM, AT&T, Dallas, DEC,
Freescale, GTE, IBM, IDT,
Infineon, Intel, LSI Logic,
McDonnell Douglas, MIPS,
Motorola, National, NEC,
PACE, PMC Sierra/QED,
Rockwell, Siemens,
Texas Instruments,
Toshiba, Zilog
Xilinx Kintex 7,
Virtex 7,
Virtex 6,
Spartan 6,
Virtex 5,
Virtex 4,
Altera Cyclone IV,
Stratix IV GX,
Arria II GX
PCI, PCI-X®,
PCI Express®,
Serial ATA
(SATA 1 and 2),
SCSI,
Serial Attached
SCSI (SAS),
HyperTransport
DDR1, DDR2,
PC-100/133,
GDDR3,
Fully Buffered
DIMM
(FB-DIMM),
Rambus
Fibre Channel,
I2C,
IEEE-1394,
Serial ATA
(SATA 1 and 2),
USB 2.0/1.1,
PCI Express,
RS-232,
CAN,
IEEE-488
AGP2x,
AGP4x,
AGP3.0,
PCI Express
24
16800 Series Instrument Characteristics
Standard data views
Waveform
Listing
Compare
Source code
Eye scan
Integrated display of data as digital waveforms, analog waveforms imported from an external
oscilloscope, and/or as a chart of a bus’ values over time
Displays data as a state listing
Compares data from different acquisitions and highlights differences
Displays time-correlated source code and inverse assembly simultaneously in a split display
Define the trigger event by simply clicking on a line of source code
Obtain source-code-level views of dynamically loaded software or code moved from ROM to RAM
during a boot-up sequence using address offsets
Requires access to source files via the LAN or instrument hard drive to provide source code correlation
Source correlation does not require any modification or recompilation of your source code
Displays eye diagrams across all buses and signals simultaneously, allowing you to identify problem
signals quickly
Data display
Numeric bases for data
display
Binary, hex, octal, decimal, signed decimal (two’s complement), ASCII, symbols, and processor
mnemonics
Symbolic support/object file format compatibility
Number of symbols/ranges
Object file formats
supported
ASCII
User defined symbols
Unlimited (limited only by amount of virtual memory available on 16800 Series logic analyzers)
IEEE-695, Aout, Omf86, Omf96, Omf386, Sysrof, ELF/DWARF1 1, ELF/DWARF2 1, ELF/Stabs1,
ELF/Stabs2, ELF/Mdebug Stabs, TICOFF/COFF, TICOFF/Stabs
GPA (general purpose ASCII)
Specify a mnemonic for a given bit pattern for a label or bus
Available data/file formats
ala
xml
csv
mfb
Contains information to reconstruct the display appearance, instrument settings, and trace data
(optional) that were present when the file was created
Extensible markup language for configuration portability and programmability
CSV (comma-separated values) format for transferring data to other applications like Microsoft® Excel
Export logic analyzer data for post-processing. Mfb data can be parsed using programming tools
Standard analysis tools
Filter/colorize
Find (next/previous)
Show, hide, or color certain samples in a trace for easier identification and analysis
Locate specific data in a captured trace
1. Supports C++ name de-mangling.
25
16800 Series Instrument Characteristics (continued)
16800 Series PC characteristics
Operating system
Processor
Chipset
System memory
Hard disk drive
Installed on hard drive
Microsoft Windows® 7 Embedded (64-bit)
Core 2 Duo, M890, 3.0 GHz microprocessor
Intel Q45
4 GB
500 GB
Operating system, latest revision of the logic and protocol application software, optional application
software ordered with the logic analyzer
16800 Series instrument controls
LCD display
Front-panel hot keys
Front-panel knob
Keyboard and mouse
Large 38.1-cm (15-in.) display makes is easy to view a large number of waveforms or states (Touch
screen available via Option 103)
Dedicated hot keys for selecting run mode and disabling touch screen (if ordered)
General-purpose knob adjusts viewing and measurement parameters
PS/2 keyboard and mouse (shipped standard)
16800 Series video display modes
Available touch-screen
display
External display
Size
Resolution
Simultaneous display capability
38.1 cm (15 in.) diagonal
1024 x 768
Front panel and external display can be used simultaneously at
1024 x 768 resolution
Supports up to four external monitors at up to 1600 x 1200 (with PCI video card)
Programmability
You can write programs to control the logic analyzer application from remote
computers on the local area network using COM or ASCII.
The COM automation server is part of the logic analyzer application. This software allows you to write programs to control the logic analyzer. All measurement functionality is controllable via the COM interface.
The B4608A Remote Programming Interface (RPI) lets you remotely control a
16800 Series logic analyzer by issuing ASCII commands to the TCP socket on
port 6500. This interface is designed to be as similar as possible to the RPI on
16700 Series logic analysis systems, so that you can reuse existing programs.
The remote programming interface works through the COM automation objects,
methods, and properties provided for controlling the logic analyzer application.
RPI commands are implemented as Visual Basic modules that execute COM
automation commands, translate their results, and return proper values for the
RPI. You can use the B4606A advanced customization environment to customize
and add RPI commands.
Logic analyzer
(16900/16800/1680)
or PC running Agilent
logic analyzer application
Computer with
Windows XP or Windows 7
Distributed COM
LAN connection
Figure 6. 16800 Series programming overview.
26
Instrument COM
automation server
16800 Series Interfaces
Peripheral interfaces
Display
Keyboard
Mouse
Serial
PCI card expansion slot
USB
15-pin XGA connector, DVI
PS/2
PS/2
9-pin D-sub
1 full profile
Six 2.0 ports, two in front, four in rear
Connectivity interfaces
LAN
Connector
10Base-T, 100Base-T, 1000Base-T
RJ-45
Interface with external instrumentation
Trigger or arm external devices or receive signals that can be used to arm measurement hardware within the logic analyzer with
Trigger In/Out
Trigger in
Input
Action taken
Input signal level
Threshold level
Minimum signal amplitude
Connector
Input resistance
Rising edge or falling edge
When received, the logic analyzer takes the actions described in the trigger sequence step
± 5 V max
Selectable: ECL, LVPECL, LVTTL, PECL, TTL
User defined (± 5 V in 50 mV increments)
200 mV
BNC
4 kΩ nominal
Trigger out
Trigger
Output signal
Threshold level
Signal load
Connector
Rising edge or falling edge. OR of selected events that cause Trigger Out (logic analyzer trigger or
flags)
VOH (output high level) 2.0 V min
VOL (output low level) 0.5 V max
Pulse width approx. 80 to 160 ns
LVTTL (3.3 V logic)
50 Ω (For good signal quality, the trigger out signal should be terminated in 50 Ω to ground)
BNC
27
16800 Series Physical Characteristics
Dimensions
443.23
(17.450)
Power
16801A
16802A
16803A
16804A
16806A
16821A
16822A
16823A
115/230 V, 48 to 66 Hz,
605 W max
115/230 V, 48 to 66 Hz,
605 W max
115/230 V, 48 to 66 Hz,
605 W max
115/230 V, 48 to 66 Hz,
775 W max
115/230 V, 48 to 66 Hz,
775 W max
115/230 V, 48 to 66 Hz,
775 W max
115/230 V, 48 to 66 Hz,
775 W max
115/230 V, 48 to 66 Hz,
775 W max
Weight
Max net
16801A
12.9 kg
(28.5 lbs)
13.2 kg
(28.9 lbs)
13.7 kg
(30.3 lbs)
14.2 kg
(31.3 lbs)
14.6 kg
(32.1 lbs)
14.2 kg
(31.2 lbs)
14.2 kg
(31.6 lbs)
14.5 kg
(32.0 lbs)
16802A
16803A
16804A
16806A
16821A
16822A
16823A
Max
shipping
19.7 kg
(43.5 lbs)
19.9 kg
(43.9 lbs)
20.5 kg
(45.3 lbs)
21.0 kg
(46.3 lbs)
21.4 kg
(47.1 lbs)
20.9 kg
(46.2 lbs)
21.1 kg
(46.6 lbs)
21.3 kg
(47.0 lbs)
330.32
(13.005)
Dimensions: mm (inches)
28.822
(11.347)
Figure 7. 16800 Series exterior dimensions.
15 inch built-in
color LCD display,
touch screen
available
General purpose knob
Run/stop keys
On/Off power switch
Touch screen on/off (if ordered)
Figure 8. 16800 Series front panel.
AC power
Trigger in
Trigger out
Mouse
Keyboard
Full profile PCI card
expansion slot
Clock in
10/100/1000 Base-T LAN
Serial port
2.0 USB ports (4)
External display port
Figure 9. 16800 Series back panel.
Instrument operating environment
Temperature 0º C to 50º C
(32º F to 122º F)
Altitude
To 2000 m (6,561 ft)
Humidity
8 to 80% relative
humidity at 40º C
(104º F)
Figure 10. 16800 Series side view.
28
16800 Series Accessories
Agilent 1184BZ testmobile
Weight
1181BZ
The Agilent 1181BZ testmobile gives
you a convenient means of organizing
and transporting your logic analysis
system mainframes and accessories.
The testmobile includes the following:
• Heavy-duty casters make moving
instruments easy
• Includes a steel buckle and nylon
strap to secure instruments to the
cart
Max net: 44.5 kg (98 lbs)
Optional accessories
35181E
35181HZ
35181J
35181KZ
35181M
Antistatic mat for work
surface
Testmobile printer/plotter
stand
Storage drawer, 3.5 inch
(89 mm)
Testmobile work surface
Testmobile drawer,
5.25 inch (133 mm)
• Total load capacity: 226.8 kg
(200 lbs)
Figure 12. Agilent 1181BZ testmobile cart
dimensions.
Figure 11. Agilent 1181BZ testmobile cart.
29
16800 Series Accessories (continued)
Rack accessories
Stationary shelf
This light-duty fixed shelf is designed to support 16800 Series logic analyzers.
The shelf can be used in all standard Agilent racks. The stationary shelf is
mounted securely into place using the supplied hardware and is designed to sit
at the bottom of the EIA increment. Features of the stationary shelf include:
• Snap-in design for easy installation
• Smooth edges
Sliding shelf
Figure 13. Sliding shelf installed in rack.
The sliding shelf provides a flat surface with full product accessibility. It can
be used in all Agilent racks to support 16800 Series logic analyzers. The shelf
and slides are preassembled for easy installation. Features of the sliding shelf
include:
• Snap-in design for easy installation
• Smooth edges
Consider purchasing the steel ballast (C2790AC) to use with the sliding shelf.
The ballast provides anti-tip capability when the shelf is extended.
Specifications
Material
Weight
Color
Length
Height
Width
Load capacity
EIA units
Contains
Figure 14. Stationary shelf (J1520AC).
J1520AC
J1526AC
Cold-rolled steel
8 kg (17.6 lbs)
Quartz gray
678 mm (26.7 in)
44 mm (1.73 in)
444 mm (17.5 in)
68 kg (150 lbs)
1
1 stationary shelf
2 rear brackets
Mounting hardware
Cold-rolled steel
9.9 kg (22 lbs)
Quartz gray
723.9 mm (28.5 in)
44.5 mm (1.75 in)
482.6 mm (19 in)
Capacity 68 kg (150 lbs)
2
1 sliding shelf
2 rear brackets
1 cable strap
Mounting hardware
30
Figure 15. Sliding shelf (J1526AC).
Ordering Information
Each 16800 Series portable logic analyzer comes with one PS/2 keyboard, one PS/2 mouse, accessory pouch, power
cord and 1-year warranty standard.
Selecting a logic analyzer to meet your application and budget is as easy as 1, 2, 3.
1
Choose measurement
capability
Logic analyzer
Logic analyzer with 48-channel pattern
generator
2
Choose the channel count
34 channels
68 channels
102 channels
136 channels
204 channels
16801A
16821A
16802A
16822A
16803A
16823A
16804A
–
16806A
–
3
Choose the memory depth and state speed
Memory depth (samples)
State speeds
1 M: <Model number>-001
4 M: <Model number>-004
16 M: <Model number>-016
32 M: <Model number>-032
250 MHz: <Model number>-250
450 MHz: <Model number>-500 1
1. Applies to 68, 102, 136 and 204 channel models.
Additional 16800 Series options
Agilent product or option number
Description
Ordering information
16800A-103 1
16800A-109 2
E5862A
Add touch screen
External removable hard drive
Additional external hard drive
Must be ordered at time of purchase
Must be ordered at time of purchase
1. Option 16800A-102, which provides a “Front panel with 15 inch display” is automatically included as part of the base product and is
a no charge option. If you select Option 16800A-103, the “non-touch screen” 15 inch display that would normally ship in the logic
analyzer is replaced by a “touch screen” 15 inch display.
2. Option 16800A-101, which provides a “Standard internal hard drive for 16800 series logic analyzers”, is automatically included as part
of the base product and is a no charge option. If you select Option 16800A-109, the hard drive that would normally ship internal to the
logic analyzer is shipped in an external enclosure.
All models of 16800 family portable logic analyzers come automatically with the no charge option 16800A-111 which
provides a “Standard Configuration”.
31
16800 Series Probing Options
16800 Series logic analyzer probes
Logic analyzer probes are ordered separately. Please specify
probes when ordering to ensure the correct connection between
your logic analyzer and the device under test.
General-purpose flying lead
• 17-ch E5383A
Connector probes
• Mictor: 34-ch E5346A
• Samtec: 34-ch E5385A
Connectorless probes
• 34-ch E5394A soft touch
• 17-ch E5396A soft touch
• 34-ch E5404A pro-series soft touch
Pattern generator clock and data pods
For models with a pattern generator, order at least one clock pod
and at least one data pod for every 8 output channels.
TTL/CMOS
• 16720A-011 TTL clock pod and lead set
• 16720A-012 3-state TTL/3.3-V data pod and lead set
• 16720A-013 3-state TTL/CMOS data pod and lead set
• 16720A-014 TTL data pod and lead set
2.5 V
• 16720A-015 2.5-V clock pod and lead set
• 16720A-016 2.5-V data pod and lead set
3.3 V
• 16720A-017 3.3-V clock pod and lead set
• 16720A-018 3.3-V 3-state data pod and lead set
ECL
• 16720A-021 ECL clock pod and lead set
• 16720A-022 ECL data pod and lead set
• 16720A-023 ECL unterminated data pod and lead set
5 V PECL
• 16720A-031 5-V PECL clock pod and lead set
• 16720A-032 5-V PECL data pod and lead set
LVPECL
• 16720A-033 LVPECL clock pod and lead set
• 16720A-034 LVPECL data pod and lead set
1.8 V
• 16720A-041 1.8-V clock pod and lead set
• 16720A-042 1.8-V data pod and lead set
LVDS
• 16720A-051 LVDS clock pod and lead set
• 16720A-052 LVDS data pod and lead set
32
16800 Series Probing Options (continued)
Upgrade memory depth or state speed after purchase
Logic analyzer channels
Logic analyzer models
After purchase upgrade models
Memory depth (samples)
34
16801A, 16821A
E5876A
State speed
68
102
136
16802A, 16822A 16803A, 16823A
16804A
E5877A
E5878A
E5879A
4 M: <Model number>-004
16 M: <Model number>-016
32 M: <Model number>-032
450 MHz: <Model number>-500 1
204
16806A
E5880A
1. Applies to 68, 102, 136 and 204 channel models.
Related literature
Publication title
Publication type
Publication number
Agilent Technologies 16800 Series Logic Analyzers
Considerations When Selecting a Logic Analyzer
Agilent Technologies 16900 Series Logic Analysis Systems
Agilent Technologies Measurement Modules for the 16900 Series
Agilent Technologies B4655A FPGA Dynamic Probe
Probing Solutions for Agilent Technologies Logic Analyzers
Color brochure
Application note
Color brochure
Data sheet
Data sheet
Catalog
5989-5062EN
5989-5138EN
5989-0420EN
5989-0422EN
5989-0423EN
5968-4632E
33
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Published in USA, February 3, 2014
5989-5063EN
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