Micross RetailPlus Datasheet MYX28F00AM29EWH

Micross RetailPlus Datasheet MYX28F00AM29EWH
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
1Gb - 64M x 16 Parallel NOR Flash Embedded Memory
Features
• Software protection
• Tin Lead Ball metallurgy Sn63Pb37
ƒƒ Volatile protection
• Supply voltage
ƒƒ Nonvolatile protection
ƒƒ VCC = 2.7–3.6V (program, erase, read)
ƒƒ Password protection
ƒƒ VCCQ = 1.65–VCC (I/O buffers)
ƒƒ Password access
• Extended memory block
• Asynchronous random/page read
ƒƒ 128-word (256-byte) block for permanent, secure
identification
ƒƒ Page size: 16 words or 32 bytes
ƒƒ Page access: 25ns
ƒƒ Programmed or locked at the factory or by the
customer
ƒƒ Random access: 100ns (Fortified BGA)
• Buffer program: 512-word program buffer
• Low power consumption: Standby mode
• Program time
• JESD47-compliant
ƒƒ 0.88μs per byte (1.14 MB/s) TYP when using full
512-word buffer size in buffer program
ƒƒ 100,000 minimum ERASE cycles per block
ƒƒ Data retention: 20 years (TYP)
• Memory organization
• 65nm multilevel cell (MLC) process technology
ƒƒ Uniform blocks: 128-Kbytes or 64-Kwords each
• Green package (Halogen-free)
• Program/erase controller
ƒƒ Embedded byte (x8)/word (x16) program algorithms
• Program/erase suspend and resume capability
OptionsMarking
ƒƒ Read from another block during a PROGRAM
SUSPEND operation
• Configuration
ƒƒ Read or program another block during an ERASE
SUSPEND operation
ƒƒ 64 Meg x 16
• FBGA package (Sn63/Pb37)
• BLANK CHECK operation to verify an erased block
ƒƒ 64-ball FBGA (13mm x 11mm)
• Unlock bypass, block erase, chip erase, and write to
buffer capability
00A
BG
PC
• Operating temperature
ƒƒ Industrial (–40°C ≤ TC ≤ +85°C)
ƒƒ Fast buffered/batch programming
IT
ƒƒ Fast block/chip erase
• VPP/WP# pin protection
• Protects first or last block regardless of block protection
settings
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
1
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
Contents
1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
5
12
12.1
5.2
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.3
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.4
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7
8
9
10
11
Block Protection Command Definitions
Address-Data Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 20
14
Protection Operations . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.1
Data Polling Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2
Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
BLANK CHECK Commands . . . . . . . . . . . . . . . . . . . . . 19
13
Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1
BLANK CHECK Operation . . . . . . . . . . . . . . . . . . . . . . . 19
15
14.1
LOCK REGISTER Commands . . . . . . . . . . . . . . . . . . . . 23
14.2
PASSWORD PROTECTION Commands . . . . . . . . . . . . . 23
14.3
NONVOLATILE PROTECTION Commands . . . . . . . . . . . 23
14.4
NONVOLATILE PROTECTION BIT LOCK BIT Commands . 24
14.5
VOLATILE PROTECTION Commands . . . . . . . . . . . . . . . 24
14.6
EXTENDED MEMORY BLOCK Commands . . . . . . . . . . . 24
14.7
EXIT PROTECTION Command . . . . . . . . . . . . . . . . . . . 24
Device Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
15.1
Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 25
15.2
Software Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Standard Command Definitions
Address-Data Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.3
Volatile Protection Mode . . . . . . . . . . . . . . . . . . . . . . . 26
15.4
Nonvolatile Protection Mode . . . . . . . . . . . . . . . . . . . . 26
READ and AUTO SELECT Operations . . . . . . . . . . . . . . 14
15.5
Password Protection Mode . . . . . . . . . . . . . . . . . . . . . 27
8.1
READ/RESET Command . . . . . . . . . . . . . . . . . . . . . . . 14
15.6
Password Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2
READ CFI Command . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16
Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . 27
8.3
AUTO SELECT Command . . . . . . . . . . . . . . . . . . . . . . 15
17
Power-Up and Reset Characteristics . . . . . . . . . . . . . 28
18
Absolute Ratings and Operating Conditions . . . . . . . . 30
Bypass Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9.1
UNLOCK BYPASS Command . . . . . . . . . . . . . . . . . . . . 15
9.2
UNLOCK BYPASS RESET Command . . . . . . . . . . . . . . . 16
19
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
20
Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 34
10.1
PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . 16
21
Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 37
10.2
UNLOCK BYPASS PROGRAM Command . . . . . . . . . . . . 16
10.3
WRITE TO BUFFER PROGRAM Command . . . . . . . . . . . 16
22
Accelerated Program, Data Polling/Toggle
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.4
UNLOCK BYPASS WRITE TO BUFFER PROGRAM
Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
23
Program/Erase Characteristics . . . . . . . . . . . . . . . . . . 48
10.5
WRITE TO BUFFER PROGRAM CONFIRM Command . . . 17
24
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.6
BUFFERED PROGRAM ABORT AND RESET Command . . 17
10.7
PROGRAM SUSPEND Command . . . . . . . . . . . . . . . . . 17
25
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.8
PROGRAM RESUME Command . . . . . . . . . . . . . . . . . . 18
Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11.1
CHIP ERASE Command . . . . . . . . . . . . . . . . . . . . . . . . 18
11.2
UNLOCK BYPASS CHIP ERASE Command . . . . . . . . . . . 18
11.3
BLOCK ERASE Command . . . . . . . . . . . . . . . . . . . . . . 18
11.4
UNLOCK BYPASS BLOCK ERASE Command . . . . . . . . . 18
11.5
ERASE SUSPEND Command . . . . . . . . . . . . . . . . . . . . 19
11.6
ERASE RESUME Command . . . . . . . . . . . . . . . . . . . . . 19
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
2
Form #: CSI-D-685 Document 003
1Gb Parallel
NORFlash
Flash
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
Parallel NOR
General Description
MYX28F00AM29EWH*
General Description
1
*Advanced information. Subject to change without notice.
The device is an asynchronous, uniform block, parallel NOR Flash memory device.
READ, ERASE, and PROGRAM operations are performed using a single low-voltage supply. Upon power-up, the device defaults to read array mode.
General Description
The device
is main
an asynchronous,
uniform
block,
NOR
Flashthat
memory
ERASE, and
The
memory array
is divided
intoparallel
uniform
blocks
can bedevice.
erased READ,
independently operations
so that valid
can be using
preserved
while
old data is
purged.
PROGRAM
PROGRAM
aredata
performed
a single
low-voltage
supply.
Upon
power-up,and
theERASE
device defaults
commands
to read array
mode. are written to the command interface of the memory. An on-chip program/
erase controller simplifies the process of programming or erasing the memory by taking
of allarray
special
operations
requiredblocks
to update
the memory
The end
a valid data
The main care
memory
is divided
into uniform
that can
be erasedcontents.
independently
so of
that
PROGRAM
or
ERASE
operation
can
be
detected
and
any
error
condition
can
be
identican be preserved while old data is purged. PROGRAM and ERASE commands are written to the command
fied. The command set required to control the device is consistent with JEDEC standinterface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing
ards.
the memory by taking care of all special operations required to update the memory contents. The end of a
CE#,
OE#, and
WE# control
bus operation
of the
device and
a simple
PROGRAM
or ERASE
operation
can bethe
detected
and any error
condition
can enable
be identified.
Theconcommand set
nection to most microprocessors, often without additional logic.
required to control the device is consistent with JEDEC standards.
The device supports asynchronous random read and page read from all blocks of the
CE#, OE#,
and ItWE#
control the
operation
of the
device
enablethroughput
a simple connection
to most
array.
also features
an bus
internal
program
buffer
that and
improves
by programming 512
words
via one
command
microprocessors,
often
without
additional
logic. sequence. A 128-word extended memory block overlaps addresses with array block 0. Users can program this additional space and then
The deviceprotect
supports
asynchronous
and page The
read device
from allalso
blocks
of the different
array. It also
features
it to
permanentlyrandom
secureread
the contents.
features
levels
of an
hardware
and
software
protection
to by
secure
blocks from
modification.
internal program
buffer
that
improves
throughput
programming
512unwanted
words via one
command sequence. A
128-wordRefer
extended
memory block
overlaps
with array
block
0. Users
program
to TN-13-30,
System
Designaddresses
Considerations
with
Micron
Flashcan
Memory,
forthis
de-additional
space andtails
then
to permanently
secure
thesignals.
contents. The device also features different levels of
onprotect
systemitdesign
and V CC and
V CCQ
hardware and software protection to secure blocks from unwanted modification.
Figure 1: Logic Diagram
Figure 1: Logic Diagram
VCC
VCCQ
VPP/WP#
15
A[MAX:0]
DQ[14:0]
DQ15/A-1
WE#
CE#
OE#
RY/BY#
RST#
BYTE#
VSS
MYX28F00AM29EWH
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf
- Rev. C 9/14 EN
Revision
1.0 - 11/14/2014
8
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
2
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
Signal Assignments
Signal Assignments
Figure 5: 64-Ball
Fortified
BGA
Figure
2: 64-Ball
Fortified BGA
6
7
8
A7 RY/BY# WE#
A9
A13
RFU
A4
A17 VPP/WP# RST#
A8
A12
A22
RFU
A2
A6
A18
A21
A10
A14
A23
RFU
A1
A5
A20
A19
A11
A15 VCCQ
RFU
A0
D0
D2
D5
D7
A16
VCCQ CE#
D8
D10
D12
D14 BYTE# A24
RFU
OE#
D9
D11
VCC
D13 D15/A-1 A25
RFU
VSS
D1
D3
D4
D6
1
2
RFU
A3
A26
3
4
5
A
B
C
D
E
VSS
F
G
H
VSS
RFU
Top view – ball side down
1. A-1 is the least significant address bit in x8 mode.
2. A23 is valid for 256Mb and above; otherwise, it is RFU.
1. A-1 is the least
significant
bit and
in x8above;
mode.otherwise, it is RFU.
3. A24
is valid address
for 512Mb
validabove;
for 1Gb
and above;
it is RFU.
2. A25 is valid4.forA25
1Gbisand
otherwise,
it isotherwise,
RFU.
5.
A26
is
valid
for
2Gb
only;
otherwise
it
is
RFU.
3. A26 is valid for 2Gb only; otherwise it is RFU.
Notes:Notes:
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
4
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
3
Signal Descriptions
The signal description table below is a comprehensive list of signals for this device family. All signals listed may
not be supported on this device. See Signal Assignments for information specific to this device.
Table 1: Signal Descriptions
Name
Type
Description
A[MAX:0]
Input
Address: Selects the cells in the array to access during READ operations. During WRITE operations, they control the commands sent to the
command interface of the program/erase controller.
CE#
Input
Chip enable: Activates the device, enabling READ and WRITE operations to be performed. When CE# is HIGH, the device goes to standby and
data outputs are High-Z.
OE#
Input
Output enable: Active LOW input. OE# LOW enables the data output buffers during READ cycles. When OE# is HIGH, data outputs are High-Z.
WE#
Input
Write enable: Controls WRITE operations to the device. Address is latched on the falling edge of WE# and data is latched on the rising edge.
VPP/WP#
Input
VPP/Write Protect: Provides WRITE PROTECT function and VPPH function. These functions protect the lowest or highest block and enable the
device to enter unlock bypass mode, respectively. (Refer to Hardware Protection and Bypass Operations for details.)
BYTE#
Input
Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is LOW, the device is in x8 mode; when HIGH, the
device is in x16 mode. Under byte configuration, BYTE# should not be toggled during any WRITE operation. Caution: This pin cannot be floated.
RST#
Input
Reset: Applies a hardware reset to the device control logic and places it in standby, which is achieved by holding RST# LOW for at least tPLPH.
After RST# goes HIGH, the device is ready for READ and WRITE operations (after tPHEL or tPHWL, whichever occurs last).
DQ[7:0]
I/O
Data I/O: Outputs the data stored at the selected address during a READ operation. During WRITE operations, they represent the commands sent
to the command interface of the internal state machine.
DQ[14:8]
I/O
Data I/O: Outputs the data stored at the selected address during a READ operation when BYTE# is HIGH. When BYTE# is LOW, these pins are not
used and are High-Z. During WRITE operations, these bits are not used. When reading the data polling register, these bits should be ignored.
DQ15/A-1
I/O
Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as data I/O, together with DQ[14:8]. When the device
operates in x8 bus mode, this pin behaves as the least significant bit of the address. Except where stated explicitly otherwise, DQ15 = data I/O
(x16 mode); A-1 = address input (x8 mode).
Output
Ready busy: Open-drain output that can be used to identify when the device is performing a PROGRAM or ERASE operation. During PROGRAM
or ERASE operations, RY/BY# is LOW, and is High-Z during read mode, auto select mode, and erase suspend mode. The use of an open-drain
output enables the RY/BY# pins from several devices to be connected to a single pull-up resistor to VCCQ. A low value will then indicate that one
(or more) of the devices is (are) busy. A 10K Ohm or bigger resistor is recommended as pull-up resistor to achieve 0.1V VOL.
VCC
Supply
Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations. The device is disabled when VCC ≤ VLKO. If the program/
erase controller is programming or erasing during this time, then the operation aborts and the contents being altered will be invalid.
A 0.1μF and 0.01µF capacitor should be connected between VCC and VSS to decouple the current surges from the power supply. The PCB track
widths must be sufficient to carry the currents required during PROGRAM and ERASE operations (see DC Characteristics).
VCCQ
Supply
I/O supply voltage: Provides the power supply to the I/O pins and enables all outputs to be powered independently from VCC. A 0.1μF and
0.01µF capacitor should be connected between VCCQ and VSS to decouple the current surges from the power supply.
VSS
Supply
Ground: All VSS pins must be connected to the system ground.
RFU
—
Reserved for future use: Reserved by Micross for future device functionality and enhancement. These should be treated in the same way as a
DNU signal.
DNU
—
Do not use: Do not connect to any other signal, or power supply; must be left floating.
NC
—
No connect: No internal connection; can be driven or floated.
RY/BY#
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
5
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
4
Memory Organization
4.1
Memory Configuration
The main memory array is divided into 128KB or 64KW uniform blocks.
Table 2: Blocks [1023:0]
Block
Block Size
1023
128KB
Address Range (x8)
Start
End
7FE 0000h
7FF FFFFh
⋮
⋮
511
Block Size
Address Range (x16)
Start
End
3FF 0000h
7FF FFFFh
⋮
⋮
⋮
3FE 0000h
3FF FFFFh
1FF 0000h
1FF FFFFh
⋮
⋮
⋮
⋮
⋮
255
1FE 0000h
1FF FFFFh
0FF 0000h
0FF FFFFh
⋮
⋮
⋮
⋮
⋮
127
0FE 0000h
0FF FFFFh
07F0000h
07F FFFFh
⋮
⋮
⋮
⋮
⋮
63
07E 0000h
07F FFFFh
03F 0000h
03F FFFFh
⋮
⋮
⋮
⋮
⋮
8
000 0000h
001 FFFFh
000 0000h
000 FFFFh
64KW
Note:
1. 1Gb device = Blocks 0–1023
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
6
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
5
Bus Operations
Table 3: Bus Operations
Notes 1 and 2 apply to entire table.
8-Bit Mode
VPP/
WE# RST#
WP#
Operation
CE#
OE#
READ
L
L
H
H
WRITE
L
H
L
STANDBY
H
X
OUTPUT
DISABLE
L
RESET
X
16-Bit Mode
A[MAX:0],
DQ15/A-1
DQ[14:8]
DQ[7:0]
A[MAX:0]
DQ15/A-1,
DQ[14:0]
X
Cell address
High-Z
Data output
Cell address
Data output
H
H3
Command
address
High-Z
Data input4
Command
address
Data input4
X
H
X
X
High-Z
High-Z
X
High-Z
H
H
H
X
X
High-Z
High-Z
X
High-Z
X
X
L
X
X
High-Z
High-Z
X
High-Z
Notes:
1. Typical glitches of less than 3ns on CE#, OE#, WE#, and RST# are ignored by the device and do not
affect bus operations.
2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
3. If WP# is LOW, then the highest or the lowest block remains protected, depending on line item.
4. Data input is required when issuing a command sequence or when performing data polling or block
protection.
5.1
Read
Bus READ operations read from the memory cells, registers, or CFI space. To accelerate the READ operation,
the memory array can be read in page mode where data is internally read and stored in a page buffer.
Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 bus mode and A[3:0] plus
DQ15/A-1 in x8 bus mode. The extended memory blocks and CFI area do not support page read mode.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
7
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
A valid bus READ operation involves setting the desired address on the address inputs, taking CE# and OE#
LOW, and holding WE# HIGH. The data I/Os will output the value. If CE# goes HIGH and returns LOW for a
subsequent access, a random read access is perform and tACC or tCE is required. (See AC Characteristics for
details about when the output becomes valid.)
5.2
Write
Bus WRITE operations write to the command interface. A valid bus WRITE operation begins by setting the
desired address on the address inputs. The address inputs are latched by the command interface on the falling
edge of CE# or WE#, whichever occurs last. The data I/Os are latched by the command interface on the rising
edge of CE# or WE#, whichever occurs first. OE# must remain HIGH during the entire bus WRITE operation
(See AC Characteristics for timing requirement details).
5.3
Standby
Driving CE# HIGH in read mode causes the device to enter standby and data I/Os to be High-Z (See DC
Characteristics).
During PROGRAM or ERASE operations, the device will continue to use the program/erase supply current
(ICC3) until the operation completes. When CE# is HIGH, the device cannot be placed into standby mode during
a PROGRAM/ERASE operation.
5.4
Output Disable
Data I/Os are High-Z when OE# is HIGH.
5.5
Reset
During reset mode the device is deselected and the outputs are High-Z. The device is in reset mode when
RST# is LOW. The power consumption is reduced to the standby level, independently from CE#, OE#, or WE#
inputs.
When RST# is HIGH, a time of tPHEL is required before a READ operation can access the device, and a delay
of tPHWL is required before a write sequence can be initiated.
After this wake-up interval, normal operation is restored, the device defaults to read array mode, and the data
polling register is reset.
If RST# is driven LOW during a PROGRAM/ERASE operation or any other operation that requires writing to
the device, the operation will abort within tPLRH, and memory contents at the aborted block or address are no
longer valid.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
8
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
6
Registers
6.1
Data Polling Register
Table 4: Data Polling Register Bit Definitions
Note 1 applies to entire table.
Bit
Name
Settings
Description
Notes
DQ7
Data polling
bit
0 or 1,
depending
on operations
Monitors whether the program/erase controller has successfully completed its
operation, or has responded to an ERASE SUSPEND operation.
DQ6
Toggle bit
Toggles: 0 to
1; 1 to 0; and
so on
Monitors whether the program, erase, or blank check controller has successfully
completed its operations, or has responded to an ERASE SUSPEND operation.
During a PROGRAM / ERASE / BLANK CHECK operation, DQ6 toggles from 0 to
1, 1 to 0, and so on, with each successive READ operation from any address.
3, 4, 5
DQ5
Error bit
0 = Success
1 = Failure
Identifies errors detected by the program/erase controller. DQ5 is set to 1 when
a PROGRAM, BLOCK ERASE, or CHIP ERASE operation fails to write the correct
data to the memory, or when a BLANK CHECK operation fails.
4, 6
DQ3
Erase timer
bit
0 = Erase not
in progress
1 = Erase in
progress
Identifies the start of program/erase controller operation during a BLOCK ERASE
command. Before the program/erase controller starts, this bit set to 0, and
additional blocks to be erased can be written to the command interface.
4
DQ2
Alternative
toggle bit
Toggles: 0 to
1; 1 to 0; and
so on
During CHIP ERASE, BLOCK ERASE, and ERASE SUSPEND operations, DQ2
toggles from 0 to 1, 1 to 0, and so on, with each successive READ operation
from addresses within the blocks being erased.
DQ1
Buffered
program
abort bit
1 = Abort
2, 4
3, 4
Indicates a BUFFER PROGRAM operation abort. The BUFFERED PROGRAM
ABORT and RESET command must be issued to return the device to read mode
(see WRITE TO BUFFER PROGRAM command).
Notes:
1. The data polling register can be read during PROGRAM, ERASE, or ERASE SUSPEND operations; the
READ operation outputs data on DQ[7:0].
2. For a PROGRAM operation in progress, DQ7 outputs the complement of the bit being programmed.
For a BUFFER PROGRAM operation, DQ7 outputs the complement of the bit for the last word being
programmed in the write buffer. For a READ operation from the address previously programmed
successfully, DQ7 outputs existing DQ7 data. For a READ operation from addresses with blocks to be
erased while an ERASE SUSPEND operation is in progress, DQ7 outputs 0; upon successful completion
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of the ERASE SUSPEND operation, DQ7 outputs 1. For an ERASE operation in progress, DQ7 outputs 0;
upon ERASE operation’s successful completion, DQ7 outputs 1.
3. After successful completion of a PROGRAM, ERASE, or BLANK CHECK operation, the device returns to
read mode.
4. During erase suspend mode, READ operations to addresses within blocks not being erased output
memory array data as if in read mode. A protected block is treated the same as a block not being erased.
See the Toggle Flowchart for more information.
5. During erase suspend mode, DQ6 toggles when addressing a cell within a block being erased. The
toggling stops when the program/erase controller has suspended the ERASE operation. See the Toggle
Flowchart for more information.
6. When DQ5 is set to 1, a READ/RESET (F0h) command must be issued before any subsequent
command.
Table 5: Operations and Corresponding Bit Settings
Note 1 applies to entire table.
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
PROGRAM
Any address
DQ7#
Toggle
0
–
–
0
0
BLANK CHECK
Any address
1
Toggle
0
–
–
0
0
CHIP ERASE
Any address
0
Toggle
0
1
Toggle
–
0
BLOCK ERASE
before time-out
Erasing block
0
Toggle
0
0
Toggle
–
0
Non-erasing block
0
Toggle
0
0
No toggle
–
0
Erasing block
0
Toggle
0
1
Toggle
–
0
Non-erasing block
0
Toggle
0
1
No toggle
–
0
BLOCK ERASE
PROGRAM SUSPEND
ERASE SUSPEND
DQ1 RY/BY# Notes
Programming block
Invalid operation
High-Z
Nonprogramming block
Outputs memory array data as if in read mode
High-Z
1
Erasing block
No Toggle
0
–
Toggle
–
Outputs memory array data as if in read mode
Non-erasing block
2
High-Z
High-Z
PROGRAM during ERASE
SUSPEND
Erasing block
DQ7#
Toggle
0
–
Toggle
–
0
2
Non-erasing block
DQ7#
Toggle
0
–
No Toggle
BUFFERED PROGRAM ABORT
Any address
DQ7#
Toggle
0
–
–
–
0
2
1
High-Z
PROGRAM Error
Any address
DQ7#
Toggle
1
–
–
–
High-Z
ERASE Error
Any address
0
Toggle
1
1
Toggle
–
High-Z
BLANK CHECK Error
Any address
0
Toggle
1
1
Toggle
–
High-Z
2
Notes:
1. Unspecified data bits should be ignored.
2. DQ7# for buffer program is related to the last address location loaded.
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6.2
Lock Register
Table 6: Lock Register Bit Definitions
Note 1 applies to entire table.
Bit
Name
Settings
Description
Notes
DQ2
Password
protection
mode lock
bit
0 = Password protection mode enabled;
1 = Password protection mode disabled
(Default)
Places the device permanently in
password protection mode.
2
DQ1
Nonvolatile
protection
mode lock
bit
0 = Nonvolatile protection mode enabled
with password protection mode permanently
disabled; 1 = Nonvolatile protection mode
enabled (Default)
Places the device in nonvolatile protection mode with
password protection mode permanently disabled. When
shipped from the factory, the device will operate in nonvolatile
protection mode, and the memory blocks are unprotected.
2
DQ0
Extended
memory
block
protection
bit
0 = Protected
1 = Unprotected (Default)
If the device is shipped with the extended memory block
unlocked, the block can be protected by setting this bit to 0.
The extended memory block protection status can be read in
auto select mode by issuing an AUTO SELECT command.
Notes:
1. The lock register is a 16-bit, one-time programmable register. DQ[15:3] are reserved and are set to a
default value of 1.
2. The password protection mode lock bit and nonvolatile protection mode lock bit cannot both be
programmed to 0. Any attempt to program one while the other is programmed causes the operation
to abort, and the device returns to read mode. The device is shipped from the factory with the default
setting.
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7
Standard Command Definitions – Address-Data Cycles
Table 7: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit
Note 1 applies to entire table.
Address and Data Cycles
Command and
Code/Subcode
Bus
Size
1st
A
2nd
D
A
3rd
D
A
4th
D
A
5th
D
A
6th
D
A
Notes
D
READ and AUTO SELECT Operations
x8
READ/RESET (F0h)
x16
READ CFI (98h)
AUTO SELECT (90h)
X
F0
AAA
AA
X
F0
555
AA
x8
AAA
x16
555
x8
AAA
x16
555
2
555
55
X
F0
2AA
55
X
F0
98
AA
555
2AA
55
AAA
555
90
4, 5
Note 3 Note 3
BYPASS Operations
UNLOCK BYPASS (20h)
UNLOCK BYPASS RESET
(90h/00h)
x8
AAA
x16
555
x8
x16
X
AA
90
555
2AA
X
55
AAA
555
20
0
PROGRAM Operations
PROGRAM (A0h)
UNLOCK BYPASS
PROGRAM (A0h)
WRITE TO BUFFER
PROGRAM (25h)
UNLOCK BYPASS WRITE TO
BUFFER PROGRAM (25h)
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x8
AAA
x16
555
x8
x16
X
x8
AAA
x16
555
x8
x16
BAd
AA
A0
AA
25
555
2AA
PA
555
2AA
BAd
55
AAA
555
A0
PA
PD
PD
6
55
BAd
25
N
PA
PD
BAd
N
PA
PD
7, 8, 9
6
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Address and Data Cycles
Command and
Code/Subcode
Bus
Size
1st
A
D
29
WRITE TO BUFFER PROGRAM
CONFIRM (29h)
x8
x16
BAd
BUFFERED PROGRAM
ABORT and RESET (F0h)
x8
AAA
x16
555
PROGRAM SUSPEND (B0h)
PROGRAM RESUME (30h)
x8
x16
x8
x16
2nd
AA
X
B0
X
30
A
3rd
D
4th
A
D
A
5th
D
A
6th
D
A
Notes
D
7
555
2AA
55
AAA
555
F0
ERASE Operations
CHIP ERASE (80/10h)
UNLOCK BYPASS
CHIP ERASE (80/10h)
BLOCK ERASE (80/30h)
UNLOCK BYPASS BLOCK
ERASE (80/30h)
ERASE SUSPEND (B0h)
ERASE RESUME (30h)
x8
AAA
x16
555
x8
x16
X
x8
AAA
x16
555
x8
x16
x8
x16
x8
x16
AA
80
AA
X
80
X
B0
X
30
555
2AA
X
555
2AA
BAd
55
AAA
555
80
AAA
555
AA
555
2AA
55
AAA
555
10
6
10
55
AAA
555
80
AAA
555
AA
555
2AA
55
BAd
30
30
10
6
BLANK CHECK Operations
BLANK CHECK
SETUP (EB/76h)
BLANK CHECK CONFIRM
and READ (29h)
x8
AAA
x16
555
x8
x16
BAd
AA
555
2AA
55
BAd
EB
BAd
76
BAd
0
BAd
0
29
Notes:
1. A = Address; D = Data; X = “Don’t Care;” BAd = Any address in the block; N + 1 = number of words
(x16)/bytes (x8) to be programmed; PA = Program address; PD = Program data; Gray shading = Not
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applicable. All values in the table are hexadecimal. Some commands require both a command code and
subcode. For the 2Gb device, the set-up command must be issued for each selected die.
2. A full three-cycle RESET command sequence must be used to reset the device in the event of a buffered
program abort error (DQ1 = 1).
3. These cells represent READ cycles (versus WRITE cycles for the others).
4. AUTO SELECT enables the device to read the manufacturer code, device code, block protection status,
and extended memory block protection indicator.
5. AUTO SELECT addresses and data are specified in the Electronic Signature table and the Extended
Memory Block Protection table.
6. For any UNLOCK BYPASS ERASE/PROGRAM command, the first two UNLOCK cycles are unnecessary.
7. BAd must be the same as the address loaded during the WRITE TO BUFFER PROGRAM 3rd and 4th
cycles.
8. WRITE TO BUFFER PROGRAM operation: maximum cycles = 261 (x8) and 517 (x16). UNLOCK BYPASS
WRITE TO BUFFER PROGRAM operation: maximum cycles = 259 (x8), 515 (x16). WRITE TO BUFFER
PROGRAM operation: N + 1 = number of words (x16)/bytes (x8) to be programmed; maximum buffer size
= 256 bytes (x8) and 1024 bytes (x16).
9. For x8, A[MAX:7] address pins should remain unchanged while A[6:0] and A-1 pins are used to select a
byte within the N + 1 byte page. For x16, A[MAX:9] address pins should remain unchanged while A[8:0]
pins are used to select a word within the N+1 word page.
10. BLOCK ERASE address cycles can extend beyond six address-data cycles, depending on the number of
blocks to erase.
8
READ and AUTO SELECT Operations
8.1
READ/RESET Command
The READ/RESET (F0h) command returns the device to read mode and resets the errors in the data polling
register. One or three bus WRITE operations can be used to issue the READ/RESET command. Note: A full
three-cycle RESET command sequence must be used to reset the device in the event of a buffered program
abort error (DQ1 = 1).
8.2
READ CFI Command
The READ CFI (98h) command puts the device in read CFI mode and is only valid when the device is in read
array or auto select mode. One bus WRITE cycle is required to issue the command.
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8.3
AUTO SELECT Command
At power-up or after a hardware reset, the device is in read mode. It can then be put in auto select mode by
issuing an AUTO SELECT (90h) command. Auto select mode enables the following device information to be
read:
• Electronic signature, which includes manufacturer and device code information.
• Block protection, which includes the block protection status and extended memory block protection
indicator.
The device cannot enter auto select mode when a PROGRAM or ERASE operation is in progress (RY/BY#
LOW). However, auto select mode can be entered if the PROGRAM or ERASE operation has been suspended
by issuing a PROGRAM SUSPEND or ERASE SUSPEND command.
Auto select mode is exited by performing a reset. The device returns to read mode unless it entered auto select
mode after an ERASE SUSPEND or PROGRAM SUSPEND command, in which case it returns to erase or
program suspend mode.
9
Bypass Operations
9.1
UNLOCK BYPASS Command
The UNLOCK BYPASS (20h) command is used to place the device in unlock bypass mode. Three bus WRITE
operations are required to issue the UNLOCK BYPASS command.
When the device enters unlock bypass mode, the two initial UNLOCK cycles required for a standard PROGRAM
or ERASE operation are not needed, thus enabling faster total program or erase time.
The UNLOCK BYPASS command is used in conjunction with UNLOCK BYPASS PROGRAM or UNLOCK
BYPASS ERASE commands to program or erase the device faster than with standard PROGRAM or ERASE
commands. When the cycle time to the device is long, considerable time savings can be gained by using these
commands. When in unlock bypass mode, only the following commands are valid:
• The UNLOCK BYPASS PROGRAM command can be issued to program addresses within the device.
• The UNLOCK BYPASS BLOCK ERASE command can then be issued to erase one or more memory
blocks.
• The UNLOCK BYPASS CHIP ERASE command can be issued to erase the whole memory array.
• The UNLOCK BYPASS WRITE TO BUFFER PROGRAM command can be issued to speed up the
programming operation.
• The UNLOCK BYPASS RESET command can be issued to return the device to read mode.
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9.2
UNLOCK BYPASS RESET Command
The UNLOCK BYPASS RESET (90/00h) command is used to return to read/reset mode from unlock bypass
mode. Two bus WRITE operations are required to issue the UNLOCK BYPASS RESET command. The READ/
RESET command does not exit from unlock bypass mode.
10
Program Operations
10.1
PROGRAM Command
The PROGRAM (A0h) command can be used to program a value to one address in the memory array. The
command requires four bus WRITE operations, and the final WRITE operation latches the address and data in
the internal state machine and starts the program/erase controller. After programming has started, bus READ
operations output the data polling register content.
10.2
UNLOCK BYPASS PROGRAM Command
When the device is in unlock bypass mode, the UNLOCK BYPASS PROGRAM (A0h) command can be used
to program one address in the memory array. The command requires two bus WRITE operations instead
of four required by a standard PROGRAM command; the final WRITE operation latches the address and
data and starts the program/erase controller (The standard PROGRAM command requires four bus WRITE
operations). The PROGRAM operation using the UNLOCK BYPASS PROGRAM command behaves identically
to the PROGRAM operation using the PROGRAM command. The operation cannot be aborted. A bus READ
operation to the memory outputs the data polling register.
10.3
WRITE TO BUFFER PROGRAM Command
The WRITE TO BUFFER PROGRAM (25h) command makes use of the program buffer to speed up
programming and dramatically reduces system programming time compared to the standard non-buffered
PROGRAM command. 256Mb through 2Gb devices support a 512-word maximum program buffer.
10.4
UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command
When the device is in unlock bypass mode, the UNLOCK BYPASS WRITE TO BUFFER (25h) command can
be used to program the device in fast program mode. The command requires two bus WRITE operations fewer
than the standard WRITE TO BUFFER PROGRAM command.
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10.5
WRITE TO BUFFER PROGRAM CONFIRM Command
The WRITE TO BUFFER PROGRAM CONFIRM (29h) command is used to confirm a WRITE TO BUFFER
PROGRAM command and to program the n + 1 words/bytes loaded in the program buffer by this command.
10.6
BUFFERED PROGRAM ABORT AND RESET Command
A BUFFERED PROGRAM ABORT AND RESET (F0h) command must be issued to reset the device to read
mode when the BUFFER PROGRAM operation is aborted. The buffer programming sequence can be aborted
in the following ways:
• Load a value that is greater than the page buffer size during the number of locations to program in the
WRITE TO BUFFER PROGRAM command.
• Write to an address in a different block than the one specified during the WRITE BUFFER LOAD
command.
• Write an address/data pair to a different write buffer page than the one selected by the starting
address during the program buffer data loading stage of the operation.
• Write data other than the CONFIRM command after the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DQ7# (for the last address location loaded), DQ6 =
toggle, and DQ5 = 0 (all of which are data polling register bits). A BUFFERED PROGRAM ABORT and RESET
command sequence must be written to reset the device for the next operation.
Note: The full three-cycle BUFFERED PROGRAM ABORT and RESET command sequence is required when
using buffer programming features in unlock bypass mode.
10.7
PROGRAM SUSPEND Command
The PROGRAM SUSPEND (B0h) command can be used to interrupt a program operation so that data can be
read from another block. When the PROGRAM SUSPEND command is issued during a program operation,
the device suspends the operation within the program suspend latency time and updates the data polling
register bits.
After the program operation has been suspended, data can be read from any address. However, data is invalid
when read from an address where a program operation has been suspended.
The PROGRAM SUSPEND command may also be issued during a PROGRAM operation while an erase is
suspended. In this case, data may be read from any address not in erase suspend or program suspend mode.
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10.8
PROGRAM RESUME Command
The PROGRAM RESUME (30h) command must be issued to exit a program suspend mode and resume a
PROGRAM operation. The controller can use DQ7 or DQ6 data polling bits to determine the status of the
PROGRAM operation. After a PROGRAM RESUME command is issued, subsequent PROGRAM RESUME
commands are ignored. Another PROGRAM SUSPEND command can be issued after the device has
resumed programming.
11
Erase Operations
11.1
CHIP ERASE Command
The CHIP ERASE (80/10h) command erases the entire chip. Six bus WRITE operations are required to issue
the command and start the program/erase controller.
Protected blocks are not erased. If all blocks are protected, the data remains unchanged. No error is reported
when protected blocks are not erased.
During the CHIP ERASE operation, the device ignores all other commands, including ERASE SUSPEND. It
is not possible to abort the operation. All bus READ operations during CHIP ERASE output the data polling
register on the data I/Os.
11.2
UNLOCK BYPASS CHIP ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS CHIP ERASE (80/10h) command can be
used to erase all memory blocks at one time. The command requires only two bus WRITE operations instead
of six using the standard CHIP ERASE command. The final bus WRITE operation starts the program/erase
controller.
11.3
BLOCK ERASE Command
The BLOCK ERASE (80/30h) command erases a list of one or more blocks. It sets all bits in the selected,
unprotected blocks to 1. All previous, selected, unprotected blocks data in the selected blocks is lost.
11.4
UNLOCK BYPASS BLOCK ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS BLOCK ERASE (80/30h) command can
be used to erase one or more memory blocks at a time. The command requires two bus WRITE operations
instead of six using the standard BLOCK ERASE command. The final bus WRITE operation latches the address
of the block and starts the program/erase controller.
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To erase multiple blocks (after the first two bus WRITE operations have selected the first block in the list), each
additional block in the list can be selected by repeating the second bus WRITE operation using the address of
the additional block.
11.5
ERASE SUSPEND Command
The ERASE SUSPEND (B0h) command temporarily suspends a BLOCK ERASE operation. One bus WRITE
operation is required to issue the command. The block address is “Don’t Care.”
11.6
ERASE RESUME Command
The ERASE RESUME (30h) command restarts the program/erase controller after an ERASE
SUSPEND operation.
The device must be in read array mode before the RESUME command will be accepted. An erase can be
suspended and resumed more than once.
12
BLANK CHECK Operation
12.1
BLANK CHECK Commands
Two commands are required to execute a BLANK CHECK operation: BLANK CHECK SETUP (EB/76h) and
BLANK CHECK CONFIRM AND READ (29h).
The BLANK CHECK operation determines whether a specified block is blank (that is, completely erased). It can
also be used to determine whether a previous ERASE operation was successful, including ERASE operations
that might have been interrupted by power loss.
The BLANK CHECK operation checks for cells that are programmed or over-erased. If it finds any, it returns a
failure status, indicating that the block is not blank. If it returns a passing status, the block is guaranteed blank
(all 1s) and is ready to program.
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13
Block Protection Command Definitions – Address-Data Cycles
Table 8: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit
Notes 1 and 2 apply to entire table.
Command and
Code/Subcode
Bus
Size
1st
A
D
Address and Data Cycles
2nd
3rd
4th
A
D
A
D
A
D
…
nth
A
Notes
D
LOCK REGISTER Commands
ENTER LOCK REGISTER
COMMAND SET (40h)
PROGRAM LOCK
REGISTER (A0h)
READ LOCK REGISTER
EXIT LOCK REGISTER
(90h/00h)
x8
x16
x8
x16
x8
x16
x8
x16
AAA
555
AA
AA
555
2AA
55
55
X
A0
X
Data
X
Data
X
90
AAA
555
40
3
5
4, 5, 6
X
00
3
PASSWORD PROTECTION Commands
ENTER PASSWORD
PROTECTION COMMAND
SET (60h)
PROGRAM PASSWORD
(A0h)
READ PASSWORD
UNLOCK PASSWORD
(25h/03h)
EXIT PASSWORD
PROTECTION (90h/00h)
x8
AAA
AA
555
55
AAA
x16
555
AA
2AA
55
555
X
A0
PWAn
PWDn
00
00
PWD0
PWD0
01
01
PWD1
PWD1
2
2
PWD2
PWD2
3
3
PWD3
…
PWD3
7
00
25
00
3
00
PWD0
01
PWD1 …
00
X
90
X
0
x8
x16
x8
x16
x8
x16
x8
x16
60
3
7
PWD 7 4, 6, 8,
9
29
8, 10
3
NONVOLATILE PROTECTION Commands
ENTER NONVOLATILE
PROTECTION COMMAND
SET (C0h)
x8
AAA
AA
555
55
AAA
x16
555
AA
2AA
55
555
X
A0
BAd
00
BAd
READ
(DQ0)
X
80
x8
PROGRAM NONVOLATILE
PROTECTION BIT (A0h)
x16
READ NONVOLATILE
PROTECTION BIT STATUS
x8
x16
CLEAR ALL NONVOLATILE
PROTECTION BITS
(80h/30h)
x8
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x16
C0
3
11
4, 6, 11
00
30
12
20
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*Advanced information. Subject to change without notice.
Command and
Code/Subcode
Bus
Size
1st
A
2nd
D
A
Address and Data Cycles
3rd
4th
D
A
D
A
D
…
nth
A
Notes
D
NONVOLATILE PROTECTION BIT LOCK BIT Commands
ENTER NONVOLATILE
x8
PROTECTION BIT LOCK BIT
x16
COMMAND SET (50h)
PROGRAM NONVOLATILE
PROTECTION BIT
LOCK BIT (A0h)
READ NONVOLATILE
PROTECTION BIT LOCK
BIT STATUS
x8
x16
x8
x16
EXIT NONVOLATILE
x8
PROTECTION BIT LOCK BIT
x16
(90h/00h)
AAA
AA
555
55
AAA
555
AA
2AA
55
555
X
A0
X
00
X
READ
(DQ0)
X
90
50
3
4, 6,
11
X
00
3
VOLATILE PROTECTION Commands
ENTER VOLATILE
PROTECTION COMMAND
SET (E0h)
PROGRAM VOLATILE
PROTECTION BIT (A0h)
READ VOLATILE
PROTECTION BIT STATUS
CLEAR VOLATILE
PROTECTION BIT (A0h)
EXIT VOLATILE
PROTECTION (90h/00h)
x8
AAA
AA
555
55
AAA
x16
555
AA
2AA
55
555
X
A0
BAd
00
BAd
READ
(DQ0)
X
A0
BAd
01
11
X
90
X
00
3
x8
x16
x8
x16
x8
x16
x8
x16
E0
3
11
4, 6
EXTENDED MEMORY BLOCK Operations
ENTER EXTENDED
MEMORY BLOCK (88h)
PROGRAM EXTENDED
MEMORY BLOCK (A0h)
READ EXTENDED
MEMORY BLOCK
EXIT EXTENDED MEMORY
BLOCK (90h/00h)
x8
x16
x8
x16
x8
x16
x8
x16
AAA
555
AAA
555
AA
AA
Word
address
data
AAA
555
AA
555
2AA
555
2AA
555
2AA
55
55
55
AAA
555
AAA
555
555
88
A0
Word
address
data
90
X
00
Notes:
1. Key: A = Address and D = Data; X = “Don’t Care;” BAd = Any address in the block; PWDn = Password
bytes, n = 0 to 7 (×8)/words 0 to 3 (×16); PWAn = Password address, n = 0 to 7 (×8)/0 to 3 (×16);
PWDn = Password words, n = 0 to 3 (×16); PWAn = Password address, n = 0 to 3(×16);Gray = Not
applicable. All values in the table are hexadecimal.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
21
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
2. DQ[15:8] are “Don’t Care” during UNLOCK and COMMAND cycles. A[MAX:16] are “Don’t Care” during
UNLOCK and COMMAND cycles, unless an address is required.
3. The ENTER command sequence must be issued prior to any operation. It disables READ and WRITE
operations from and to block 0. READ and WRITE operations from and to any other block are allowed.
Also, when an ENTER COMMAND SET command is issued, an EXIT COMMAND SET command must
be issued to return the device to READ mode.
4. READ REGISTER/PASSWORD commands have no command code; CE# and OE# are driven LOW and
data is read according to a specified address.
5. Data = Lock register content.
6. All address cycles shown for this command are READ cycles.
7. Only one portion of the password can be programmed or read by each PROGRAM PASSWORD
command.
8. Each portion of the password can be entered or read in any order as long as the entire 64-bit password is
entered or read.
9. For the x8 READ PASSWORD command, the nth (and final) address cycle equals the 8th address cycle.
From the 5th to the 8th address cycle, the values for each address and data pair continue the pattern
shown in the table as follows: for x8, address and data = 04 and PWD4; 05 and PWD5; 06 and PWD6;
07 and PWD7.
10. For the x8 UNLOCK PASSWORD command, the nth (and final) address cycle equals the 11th address
cycle. From the 5th to the 10th address cycle, the values for each address and data pair continue the
pattern shown in the table as follows: address and data = 02 and PWD2; 03 and PWD3; 04 and PWD4;
05 and PWD5; 06 and PWD6; 07 and PWD7.
For the x16 UNLOCK PASSWORD command, the nth (and final) address cycle equals the 7th address
cycle. For the 5th and 6th address cycles, the values for the address and data pair continue the pattern
shown in the table as follows: address and data = 02 and PWD2; 03 and PWD3.
11. Both nonvolatile and volatile protection bit settings are as follows: Protected state = 00; Unprotected
state = 01.
12. The CLEAR ALL NONVOLATILE PROTECTION BITS command programs all nonvolatile protection bits
before erasure. This prevents over-erasure of previously cleared nonvolatile protection bits.
14
Protection Operations
Blocks can be protected individually against accidental PROGRAM, or ERASE operations on both 8-bit and
16-bit configurations.
Memory block and extended memory block protection is configured through the lock register (see Lock
Register section).
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
22
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
14.1
LOCK REGISTER Commands
After the ENTER LOCK REGISTER COMMAND SET (40h) command has been issued, all bus READ or
PROGRAM operations can be issued to the lock register. The PROGRAM LOCK REGISTER (A0h) command
allows the lock register to be configured.
The programmed data can then be checked with a READ LOCK REGISTER command by driving CE# and
OE# LOW with the appropriate address data on the address bus.
14.2
PASSWORD PROTECTION Commands
After the ENTER PASSWORD PROTECTION COMMAND SET (60h) command has been issued, the
commands related to password protection mode can be issued to the device. The PROGRAM PASSWORD
(A0h) command is used to program the 64-bit password used in the password protection mode.
The READ PASSWORD command is used to verify the password used in password protection mode.
The UNLOCK PASSWORD (25/03h) command is used to clear the nonvolatile protection bit lock bit, allowing
the nonvolatile protection bits to be modified. The UNLOCK PASSWORD command must be issued, along
with the correct password, and requires a 1μs delay between successive UNLOCK PASSWORD commands
in order to prevent hackers from cracking the password by trying all possible 64-bit combinations. If this delay
does not occur, the latest command will be ignored. Approximately 1μs is required for unlocking the device
after the valid 64-bit password has been provided.
14.3
NONVOLATILE PROTECTION Commands
After the ENTER NONVOLATILE PROTECTION COMMAND SET (C0h) command has been issued, the
commands related to nonvolatile protection mode can be issued to the device.
A block can be protected from program or erase by issuing a PROGRAM NONVOLATILE PROTECTION BIT
(A0h) command, along with the block address. This command sets the nonvolatile protection bit to 0 for a
given block.
The status of a nonvolatile protection bit for a given block or group of blocks can be read by issuing a READ
NONVOLATILE MODIFY PROTECTION BIT command, along with the block address.
The nonvolatile protection bits are erased simultaneously by issuing a CLEAR ALL NONVOLATILE PROTECTION
BITS (80/30h) command. No specific block address is required. If the nonvolatile protection bit lock bit is set to
0, the command fails.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
23
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
14.4
NONVOLATILE PROTECTION BIT LOCK BIT Commands
After the ENTER NONVOLATILE PROTECTION BIT LOCK BIT COMMAND SET (50h) command has been
issued, the commands that allow the nonvolatile protection bit lock bit to be set can be issued to the device.
The PROGRAM NONVOLATILE PROTECTION BIT LOCK BIT (A0h) command is used to set the nonvolatile
protection bit lock bit to 0, thus locking the nonvolatile protection bits and preventing them from being modified.
The READ NONVOLATILE PROTECTION BIT LOCK BIT STATUS command is used to read the status of the
nonvolatile protection bit lock bit.
14.5
VOLATILE PROTECTION Commands
After the ENTER VOLATILE PROTECTION COMMAND SET (E0h) command has been issued, commands
related to the volatile protection mode can be issued to the device.
The PROGRAM VOLATILE PROTECTION BIT (A0h) command individually sets a volatile protection bit to 0 for a
given block. If the nonvolatile protection bit for the same block is set, the block is locked regardless of the value
of the volatile protection bit. (See the Block Protection Status table.)
The status of a volatile protection bit for a given block can be read by issuing a READ VOLATILE PROTECTION
BIT STATUS command along with the block address.
The CLEAR VOLATILE PROTECTION BIT (A0h) command individually clears (sets to 1) the volatile protection
bit for a given block. If the nonvolatile protection bit for the same block is set, the block is locked regardless of
the value of the volatile protection bit. (See the Block Protection Status table.)
14.6
EXTENDED MEMORY BLOCK Commands
The device has one extra 128-word extended memory block that can be accessed only by the ENTER
EXTENDED MEMORY BLOCK (88h) command. The extended memory block is 128 words (x16) or 256 bytes
(x8). It is used as a security block to provide a permanent 128-bit security identification number or to store
additional information.
14.7
EXIT PROTECTION Command
The EXIT PROTECTION COMMAND SET (90/00h) command is used to exit the lock register, password
protection, nonvolatile protection, volatile protection, and nonvolatile protection bit lock bit command set
modes and return the device to read mode.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
24
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
15
Device Protection
15.1
Hardware Protection
The VPP/WP# function provides a hardware method of protecting either the highest/lowest block. When
VPP/WP# is LOW, PROGRAM and ERASE operations on either of these block options is ignored to provide
protection. When VPP/WP# is HIGH, the device reverts to the previous protection status for the highest/lowest
block. PROGRAM and ERASE operations can modify the data in either of these block options unless block
protection is enabled.
Note: Micross highly recommends driving VPP/WP# HIGH or LOW. If a system needs to float the VPP/WP# pin,
without a pull-up/pull-down resistor and no capacitor, then an internal pull-up resistor is enabled.
Table 9: VPP/WP# Functions
VPP/WP# Settings
15.2
Function
VIL
Highest/lowest block is protected; for a 2Gb device, both the highest and the lowest blocks are hardware-protected
(block 0 and block 2047).
VIH
Highest/lowest block or the top/bottom two blocks are unprotected unless software protection is activated.
Software Protection
Four software protection modes are available:
• Volatile protection
• Nonvolatile protection
• Password protection
• Password access
The device is shipped with all blocks unprotected. On first use, the device defaults to the nonvolatile protection
mode but can be activated in either the nonvolatile protection or password protection mode.
The desired protection mode is activated by setting either the nonvolatile protection mode lock bit or the
password protection mode lock bit of the lock register. Both bits are one-time-programmable and nonvolatile;
therefore, after the protection mode has been activated, it cannot be changed, and the device is set permanently
to operate in the selected protection mode. It is recommended that the desired software protection mode be
activated when first programming the device.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
25
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
For the lowest and highest blocks, a higher level of block protection can be achieved by locking the blocks
using nonvolatile protection mode and holding VPP/WP# LOW. Blocks with volatile protection and nonvolatile
protection can coexist within the memory array. If the user attempts to program or erase a protected block, the
device ignores the command and returns to read mode.
The block protection status can be read by performing a read electronic signature or by issuing an AUTO
SELECT command.
15.3
Volatile Protection Mode
Volatile protection enables the software application to protect blocks against inadvertent change and can be
disabled when changes are needed. Volatile protection bits are unique for each block and can be individually
modified. Volatile protection bits control the protection scheme only for unprotected blocks whose nonvolatile
protection bits are cleared to 1. Issuing a PROGRAM VOLATILE PROTECTION BIT or CLEAR VOLATILE
PROTECTION BIT command sets to 0 or clears to 1 the volatile protection bits and places the associated
blocks in the protected (0) or unprotected (1) state, respectively. The volatile protection bit can be set or cleared
as often as needed.
When the device is first shipped, or after a power-up or hardware reset, the volatile protection bits default to 1
(unprotected).
15.4
Nonvolatile Protection Mode
A nonvolatile protection bit is assigned to each block. Each of these bits can be set for protection individually by
issuing a PROGRAM NONVOLATILE PROTECTION BIT command. Also, each device has one global volatile
bit called the nonvolatile protection bit lock bit; it can be set to protect all nonvolatile protection bits at once. This
global bit must be set to 0 only after all nonvolatile protection bits are configured to the desired settings. When
set to 0, the nonvolatile protection bit lock bit prevents changes to the state of the nonvolatile protection bits.
When cleared to 1, the nonvolatile protection bits can be set and cleared using the PROGRAM NONVOLATILE
PROTECTION BIT and CLEAR ALL NONVOLATILE PROTECTION BITS commands, respectively.
No software command unlocks the nonvolatile protection bit lock bit unless the device is in password protection
mode; in nonvolatile protection mode, the nonvolatile protection bit lock bit can be cleared only by taking the
device through a hardware reset or power-up.
Nonvolatile protection bits status cannot be changed through a hardware reset or a power-down/power-up
sequence. Nonvolatile protection bits cannot be cleared individually; they must be cleared all at once using a
CLEAR ALL NONVOLATILE PROTECTION BITS command.
If one of the nonvolatile protection bits needs to be cleared (unprotected), additional steps are required: First,
the nonvolatile protection bit lock bit must be cleared to 1, using either a power-cycle or hardware reset. Then,
the nonvolatile protection bits can be changed to reflect the desired settings. Finally, the nonvolatile protection
bit lock bit must be set to 0 to lock the nonvolatile protection bits. The device now will operate normally.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
26
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
To achieve the best protection, the PROGRAM NONVOLATILE PROTECTION LOCK BIT command should be
executed early in the boot code, and the boot code should be protected by holding VPP/WP# LOW.
Nonvolatile protection bits and volatile protection bits have the same function when VPP/WP# is HIGH or when
VPP/WP# is at the voltage for program acceleration (VPPH).
15.5
Password Protection Mode
The password protection mode provides a higher level of security than the nonvolatile protection mode by
requiring a 64-bit password to unlock the nonvolatile protection bit lock bit. In addition to this password
requirement, the nonvolatile protection bit lock bit is set to 0 after power-up and reset to maintain the device in
password protection mode.
Executing the UNLOCK PASSWORD command by entering the correct password clears the nonvolatile
protection bit lock bit, enabling the block nonvolatile protection bits to be modified. If the password provided is
incorrect, the nonvolatile protection bit lock bit remains locked, and the state of the nonvolatile protection bits
cannot be modified.
Note: There is no means to verify the password after password protection mode is enabled. If the password is
lost after enabling the password protection mode, there is no way to clear the nonvolatile protection bit lock bit.
15.6
Password Access
Password access is a security enhancement that protects information stored in the main array blocks by
preventing content alteration or reads until a valid 64-bit password is received. Password access may be
combined with nonvolatile and/or volatile protection to create a multi-tiered solution.
16
Common Flash Interface
The common Flash interface (CFI) is a JEDEC-approved, standardized data structure that can be read from
the Flash memory device. It allows a system’s software to query the device to determine various electrical and
timing parameters, density information, and functions supported by the memory. The system can interface
easily with the device, enabling the software to upgrade itself when necessary.
When the READ CFI command is issued, the device enters CFI query mode and the data structure is read from
memory. The query data is always presented on the lowest order data outputs (DQ[7:0]), and the other data
outputs (DQ[15:8]) are set to 0.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
27
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
17
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
Parallel
*Advanced information.
Subject toNOR
change Flash
without notice.
Power-Up and Reset Characteristics
Power-Up and Reset Characteristics
Power-Up and Reset Characteristics
Table 10:
Power-Up Specifications
Table 22: Power-Up
Specifications
Symbol
Parameter
Symbol
Legacy
Parameter
Legacy –
VCC HIGH to VCCQ HIGH
RST#to V
VCC HIGH to rising edge Vof HIGH
CC
CCQ HIGH
VCCQ HIGH to rising edge of RST#
VCC HIGHLOW
to rising edge of RST#
RST# HIGH to chip enable
–
tVCS
RST# HIGH to write enable LOW
VCCQ HIGH to rising edge of RST#
tVCS
tVIOS
tRH
–
tVIOS
JEDEC
tVCHVCQH
JEDEC
tVCHPH
tVCHVCQH
tVCQHPH
tVCHPHt
PHEL
tPHWL
tVCQHPH
Min Min
Unit
Unit
0
0
300
0
300 50
0
150
µs
µs µs
µs
µs ns
µs
ns
Notes
Notes
1
2, 31
2, 3
2, 3
2, 3
Notes: 1. VCC should attain VCC,min from VSS simultaneously with or prior to applying VCCQ, VPP
t
t
RST# HIGH to chipduring
enable LOW
ns
power up. VCCRHshould attain PHEL
VSS during power50down.
2. If RST# is not stable for tVCS or tVIOS, the device will not allow any READ or WRITE opertPHWL
RST# HIGH to writeations,
enable LOW
– reset is required.
150
ns
and a hardware
3. Power supply transitions should only occur when RST# is LOW.
Figure 14: Power-Up
Timing
Figure 3:
Power-Up Timing
tVCHVCQH
VCC
VSS
VCCQ
VSSQ
tRH
CE#
tVIOS
RST#
tVCS
WE#
tPHWL
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
28
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
256Mb, 512Mb, 1Gb, 2Gb:
3V Embedded
Parallel
NOR Flash
Power-Up
and
Reset
Characteristics
*Advanced
information.
to change without notice.
Power-Up
and
ResetSubject
Characteristics
Table 11: Reset AC Specifications
Table 23: Reset AC Specifications
Table 23: Reset AC Specifications
Symbol
Symbol
Symbol
Legacy
JEDEC
Condition/Parameter
Legacy
JEDEC
Min
Condition/Parameter
Legacy
JEDEC
Min
t
t
tREADY
tPLRH–
READY
PLRH
RST# LOW to read
mode
during
program
or
RST#
LOWduring
to read mode
during or
program
or erase
tREADY
tPLRH
–
RST# LOW to read
mode
program
erase
t
t
erase
RST# pulse width
RPt
PLPH
tRP
RST# pulse width
PLPH
100
tRP
tPLPH
RST# pulse width
tRH
tPHEL, 100
tPHGL
RST#
HIGH
to
CE#
LOW,
OE#
LOW
t
t
t
RH
PHEL, PHGL
50
RST# HIGH to CE# LOW, OE# LOW
tRH
tPHEL, tPHGL
50
RST# HIGH to CE# LOW, OE# LOW
t
RST# LOW
to standby
mode
during
read mode t RPD
– 10
–
RST# LOW to standby
mode
during
read
mode
tRPD –
RPD
10
RST# LOW to standby mode during read mode
RST# LOW to standby
mode
during program
or
50
RST# LOW
to standby
during program
or erase
RST# LOW to standby
mode
duringmode
program
or
50
erase
tRB
tRHEL, tRHGL
erase
RY/BY# HIGH to CE# LOW, OE# LOW
tRB
tRHEL, tRHGL
0
RY/BY# HIGH to CE# LOW, OE# LOW
t
t
t
RB
RHEL, RHGL
0
RY/BY# HIGH to CE# LOW, OE# LOW
Note: 1. Sampled only; not 100% tested.
1. only;
Sampled
only; not
100% tested.
Note 1:Note:
Sampled
not 100%
tested.
Condition/Parameter
Min
Max
Max
32
– 32
Max
100
–
–
50 –
–
10 –
–
50 ––
–
0
–
–
–
Unit
Notes
Unit
Notes
Unit
Notes
µs µs
1
32 µs
1 1
–
–
–
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
ns
µs
1
1
1
µs
ns
1
1
1
Figure 15: Reset AC Timing – No PROGRAM/ERASE Operation in Progress
Figure 15: Reset
AC4:Timing
– No
PROGRAM/ERASE
Operation
in Progress
Figure
Reset AC
Timing
– No PROGRAM/ERASE
Operation
in Progress
RY/BY#
RY/BY#
CE#, OE#
CE#, OE#
tRH
tRH
RST#
RST#
tRP
tRP
Figure 16: Reset AC Timing During PROGRAM/ERASE Operation
Figure 16: Reset AC Timing During PROGRAM/ERASE Operation
Figure 5: Reset AC Timing During PROGRAM/ERASE Operation
tREADY
tREADY
RY/BY#
RY/BY#
tRB
tRB
CE#, OE#
CE#, OE#
tRH
tRH
RST#
RST#
tRP
tRP
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf
PDF:
09005aef849b4b09 - Rev. C 9/14 EN
m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
29
55
55
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Form
#:without
CSI-D-685
Document 003
2012 Micron
Technology,
Inc. All
rights
reserved.
Micron Technology, Inc. reserves the right to©change
products
or specifications
notice.
© 2012 Micron Technology, Inc. All rights reserved.
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
18
Absolute Ratings and Operating Conditions
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions outside those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may adversely affect reliability.
Table 12: Absolute Maximum/Minimum Ratings
Parameter
Symbol
Min
Max
Unit
Notes
Temperature under bias
TBIAS
–50
125
°C
Storage temperature
TSTG
–65
150
°C
Supply voltage
VCC
–2
VCC + 2
V
1, 2
Input/output supply voltage
VCCQ
–2
VCCQ + 2
V
1, 2
Program voltage
VPPH
–0.6
14.5
V
3
Notes:
1. During signal transitions, minimum voltage may undershoot to −2V for periods less than 20ns.
2. During signal transitions, maximum voltage may overshoot to VCC + 2V for periods less than 20ns.
3. VPPH must not remain at 12V for more than 80 hours cumulative.
Table 13: Operating Conditions
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
Parameter
Symbol
Min
Max
Unit
Supply voltage
VCC
2.7
3.6
V
Input/output supply voltage (VCCQ ≤ VCC)
VCCQ
1.65
3.6
V
Program voltage
VPP
–2.0
12.5
V
Ambient operating temperature
TA
–40
85
°C
Load capacitance
CL
Input rise and fall times
–
Input pulse voltages
–
0 to VCCQ
V
Input and output timing reference voltages
–
VCCQ/2
V
30
–
pF
10
ns
30
Form #: CSI-D-685 Document 003
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
ParallelNOR
NOR Flash
1Gb Parallel
Flash
Absolute
Ratings
and
Operating
Conditions
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
MYX28F00AM29EWH*
Absolute Ratings and
Operating Conditions
Figure 17: AC Measurement Load Circuit
*Advanced information. Subject to change without notice.
Figure 17: AC Measurement Load Circuit
Figure 6: AC Measurement Load Circuit
VCCQ
VCCQ
VCC
VCC
25kΩ
25kΩ
Device
under
Device
test
under
test
CL
CL
0.1µF
0.1µF
Note:
1. CL includes jig capacitance.
Note:
1. CL includes jig capacitance.
25kΩ
25kΩ
Figure 18: AC Measurement I/O Waveform
Figure 18: ACFigure
Measurement
I/O Waveform
7: AC Measurement
I/O Waveform
VCCQ
VCCQ
VCCQ/2
VCCQ/2
0V
0V
Table 26: Input/Output Capacitance
Table 26: Input/Output Capacitance
Parameter
Symbol
Table
Input/Output
Capacitance
Input capacitance
for 14:
256Mb
and 512Mb
CIN
Parameter
Symbol
Input capacitance for 256Mb
1Gb
and 512Mb
Input capacitance for 2Gb
1Gb Parameter
CIN
Symbol
Output
capacitance
Input capacitance
forcapacitance
2Gb
Input
for 256Mb and 512Mb COUT
Output capacitance
Input capacitance for 1Gb
COUT
CIN
Test Condition
Min
Max
Unit
TestVCondition
IN = 0V
3
Min
8
Max
pF
Unit
VIN = 0V
4
3
9
8
Test Condition
PDF: 09005aef849b4b09
MYX28F00AM29EWH
m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
Revision
1.0 - 11/14/2014
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
COUT
31
57
3
8
6
8 18
6
9
3
VOUT = 0V
VIN = 0V
4
VOUT = 0V
57
Max18
9
VOUT = 0V
Input capacitance for 2Gb
Output capacitance
Min 84
3
pF
Unit
pF
pF
pF
pF
pF
8
18
pF
3
6
pF
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
19
DC Characteristics
Table 15: DC Current Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Notes
Input leakage current
ILI
0V ≤ VIN ≤ VCC
–
–
±1
µA
1
Output leakage current
ILO
0V ≤ VOUT ≤ VCC
–
–
±1
µA
CE# = VIL, OE# = VIH, f = 5 MHz
–
26
31
mA
CE# = VIL, OE# = VIH, f = 13 MHz
–
12
16
mA
–
65
210
µA
–
70
225
µA
–
75
240
µA
–
150
480
µA
VPP/WP# = VIL or VIH
–
35
50
mA
VPP/WP# = VPPH
–
35
50
mA
–
0.2
5
µA
–
2
15
µA
VCC read
current
Random read
Page read
ICC1
256Mb
VCC standby
current
512Mb
1Gb
ICC2
CE# = VCCQ ±0.2V,
RST# = VCCQ ±0.2V
2Gb
VCC program/erase/
blank check current
Read
Program/ erase
controller active
IPP1
VPP/WP# ≤ VCC
Reset
IPP2
RST# = VSS ±0.2V
–
0.2
5
µA
PROGRAM
operation ongoing
IPP3
VPP/WP# = 12V ±5%
–
0.05
0.10
mA
VPP/WP# = VCC
–
0.05
0.10
mA
ERASE operation
ongoing
IPP4
VPP/WP# = 12V ±5%
–
0.05
0.10
mA
VPP/WP# = VCC
–
0.05
0.10
mA
Standby
VPP current
ICC3
2
Notes:
1. The maximum input leakage current is ±5μA on the VPP/WP# pin.
2. Sampled only; not 100% tested.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
32
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
Table 16: DC Voltage Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input LOW voltage
VIL
VCC ≥ 2.7V
–0.5
-
0.8
V
Input HIGH voltage
VIH
VCC ≥ 2.7V
0.7VCCQ
-
VCCQ + 0.4
V
Output LOW voltage
VOL
IOL = 100μA,
VCC = VCC,min,
VCCQ = VCCQ,min
0.85VCCQ
-
0.15VCCQ
V
Output HIGH voltage
VOH
IOH = 100μA,
VCC = VCC,min,
VCCQ = VCCQ,min
Voltage for VPP/WP# program acceleration
VPPH
-
11.5
-
Program/erase lockout supply voltage
VLKO
-
2.3
-
-
Notes
V
12.5
V
V
1
Note:
1. Sampled only; not 100% tested.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
33
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
20
Read AC Characteristics
Table 17: Read AC Characteristics
Parameter
Symbol
Condition
Legacy
JEDEC
Address valid to next address valid
tRC
tAVAV
CE# = VIL, OE# = VIL
Address valid to output valid
tACC
tAVQV
CE# = VIL, OE# = VIL
Address valid to output valid (page)
tPAGE
tAVQV1
CE# = VIL, OE# = VIL
CE# LOW to output transition
CE# LOW to output valid
tLZ
tCE
tELQX
tELQV
OE# = VIL
OE# = VIL
OE# LOW to output transition
tOLZ
tGLQX
CE# = VIL
OE# LOW to output valid
tOE
tGLQV
CE# = VIL
CE# HIGH to output High-Z
tHZ
tEHQZ
OE# = VIL
OE# HIGH to output High-Z
tDF
tGHQZ
CE# = VIL
tEHQX,
CE# HIGH, OE# HIGH, or address
transition to output transition
tOH
tGHQX,
tAXQX
–
CE# LOW to BYTE# LOW
tELFL
tELBL
–
CE# LOW to BYTE# HIGH
tELFH
tELBH
–
BYTE# LOW to output valid
tFLQV
tBLQV
–
BYTE# HIGH to output valid
tFHQV
tBHQV
–
Package
Min
Max
Unit Notes
Fortified BGA
100
–
ns
TSOP
110
–
ns
Fortified BGA
–
100
ns
TSOP
–
110
ns
Fortified BGA
–
25
ns
TSOP
–
25
ns
Fortified BGA
0
–
ns
1
1
TSOP
0
–
ns
Fortified BGA
–
100
ns
TSOP
–
110
ns
Fortified BGA
0
–
ns
1
TSOP
0
–
ns
1
Fortified BGA
–
25
ns
TSOP
–
25
ns
Fortified BGA
–
20
ns
1
TSOP
–
20
ns
1
Fortified BGA
–
15
ns
1
TSOP
–
15
ns
1
Fortified BGA
0
–
ns
TSOP
0
–
ns
Fortified BGA
–
10
ns
TSOP
–
10
ns
Fortified BGA
–
10
ns
TSOP
–
10
ns
Fortified BGA
–
1
µs
TSOP
–
1
µs
Fortified BGA
–
1
µs
TSOP
–
1
µs
Note:
1. Sampled only; not 100% tested.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
34
Form #: CSI-D-685 Document 003
1Gb Parallel
Flash
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
ParallelNOR
NOR Flash
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
NOR Flash
Read Parallel
AC Characteristics
MYX28F00AM29EWH*
Read AC Characteristics
*Advanced information. Subject to change without notice.
Figure 19: Random Read AC Timing (8-Bit Mode)
Figure 19: Random Read AC Timing (8-Bit Mode)
Figure 8: Random Read AC Timing (8-Bit Mode)
tRC
tRC
A[MAX:0]/A-1
A[MAX:0]/A-1
Valid
Valid
tACC
tOH
tACC
CE#
CE#
OE#
OE#
tOH
tCE
tOH
tCE
tLZ
tOH
tHZ
tLZ
tHZ
tOLZ
tOH
tOLZ
tOE
tOH
tDF
tOE
tDF
DQ[7:0]
DQ[7:0]
Valid
Valid
BYTE#
BYTE#
tELFL
tELFL
Figure 20: Random Read AC Timing (16-Bit Mode)
Figure 20: Random Read AC Timing (16-Bit Mode)
Figure 9: Random Read AC Timing (16-Bit Mode)
tRC
tRC
A[MAX:0]
A[MAX:0]
Valid
Valid
tACC
tOH
tACC
CE#
CE#
tOH
tCE
tOH
tCE
tLZ
tOH
tHZ
tLZ
OE#
OE#
tHZ
tOLZ
tOH
tOLZ
tOE
tOH
tDF
tOE
tDF
DQ[15:0]
DQ[15:0]
Valid
Valid
BYTE#
BYTE#
tELFH
tELFH
MYX28F00AM29EWH
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf
- Rev. C 9/14 EN
Revision
1.0 - 11/14/2014
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
61
35
61
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
256Mb,
Parallel
MYX28F00AM29EWH*
256Mb,512Mb,
512Mb,1Gb,
1Gb,2Gb:
2Gb:3V
3VEmbedded
Embedded
ParallelNOR
NORFlash
Flash
Read AC Characteristics
Read AC Characteristics
*Advanced information. Subject to change without notice.
Figure 21: BYTE# Transition Read AC Timing
Figure
21: BYTE#
Transition
AC Timing
Figure
10: BYTE#
Transition
Read ACRead
Timing
A[MAX:0]
A[MAX:0]
Valid
Valid
A–1
A–1
Valid
Valid
tACC
tACC
tOH
tOH
BYTE#
BYTE#
tFHQV
tFHQV
DQ[7:0]
DQ[7:0]
Data-out
Data-out
tBLQX
tBLQX
1
DQ[15:8]
DQ[15:8]
High-Z 1
High-Z
Data-out
Data-out
Figure
22:
Page
Read
AC Timing
Figure
11:
Page
Read
AC Timing
Figure
22: Page
Read
AC Timing
A[MAX:4]
A[MAX:4]
Valid
Valid
A[3:0]
A[3:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tACC
tACC
CE#
CE#
tCE
tOH
tOH
tCE
tHZ
tHZ
OE#
OE#
tOE
tOE
DQ[15:0]
DQ[15:0]
tPAGE
tPAGE
Valid
Valid
Valid
Valid
tOH
tOH
tDF
tDF
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1. Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 bus
Note:Note:
Note: 1. Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 bus
mode and A[3:0] plus DQ15/A−1 in x8 bus mode.
and
in x8bybus
mode.inputs A[3:0] in x16 bus mode and A[3:0]
1. Page size is 16mode
words
(32A[3:0]
bytes)plus
andDQ15/A−1
is addressed
address
plus DQ15/A−1 in x8 bus mode.
MYX28F00AM29EWH
Revision
1.0 - 11/14/2014
PDF: 09005aef849b4b09
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf
- Rev. C 9/14 EN
m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
36
62
62
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Micron Technology, Inc. reserves the right
to change
products
or specifications
without
notice.
© 2012
Micron
Technology,
Inc. All rights
reserved.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
21
Write AC Characteristics
Table 18: WE#-Controlled Write AC Characteristics
Parameter
Symbol
Legacy
JEDEC
Address valid to next address valid
tWC
tAVAV
CE# LOW to WE# LOW
tCS
tELWL
tWP
tWLWH
Input valid to WE# HIGH
tDS
tDVWH
WE# HIGH to input transition
tDH
tWHDX
WE# HIGH to CE# HIGH
tCH
tWHEH
WE# HIGH to WE# LOW
tWPH
tWHWL
Address valid to WE# LOW
tAS
tAVWL
WE# LOW to address transition
tAH
tWLAX
OE# HIGH to WE# LOW
–
tGHWL
WE# HIGH to OE# LOW
tOEH
tWHGL
Program/erase valid to RY/BY# LOW
tBUSY
tWHRL
VCC HIGH to CE# LOW
tVCS
tVCHEL
tWHWH1
tWHWH1
WE# LOW to WE# HIGH
WRITE TO BUFFER PROGRAM
opera- tion (512 words)
PROGRAM operation
(single word or byte)
Package
Min
Typ
Max
Unit
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
Fortified BGA
TSOP
100
110
0
0
35
35
30
30
0
0
0
0
20
20
0
0
45
45
0
0
0
0
–
–
300
300
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
900
900
210
210
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
30
30
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
Notes
1
1
2
2
Notes:
1. The user’s write timing must comply with this specification. Any violation of this write timing specification
may result in permanent damage to the NOR Flash device.
2. Sampled only; not 100% tested.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
37
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
Parallel NOR Flash
Write AC Characteristics
*Advanced information. Subject to change without notice.
Figure 23: WE#-Controlled
Program Program
AC Timing
(8-Bit Mode)
Figure 12: WE#-Controlled
AC Timing
(8-Bit Mode)
3rd Cycle
4th Cycle
Data Polling
READ Cycle
tWC
A[MAX:0]/A-1
tWC
AAAh
PA
PA
tAS
tAH
tCH
tCS
tCE
CE#
tGHWL
tOE
OE#
tWP
tWPH
WE#
tWHWH1
tDS
DQ[7:0]
A0h
PD
DQ7#
tDF
DOUT
tOH
DOUT
tDH
1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the data polling register bit and by a READ
operation
that outputs
the data (DOUT
) programmed
by the previous
PROGRAMcommand
comOnly the third and
fourth cycles
of the PROGRAM
command
are represented.
The PROGRAM
mand.
is followed by checking of the data polling register bit and by a READ operation that outputs the data
2. PA is the address of the memory location to be programmed. PD is the data to be pro(DOUT) programmed
by the previous PROGRAM command.
grammed.
PA is the address
ofisthe
location
to be
programmed.
PD is the data
be(See
programmed.
3. DQ7
thememory
complement
of the
data
bit being programmed
to to
DQ7
Data Polling Bit
[DQ7]). of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]).
DQ7 is the complement
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
Notes: Notes:
1.
2.
3.
4.
Characteristics, and CE#-Controlled Write AC Characteristics.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
38
64
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
Parallel NOR Flash
Write AC Characteristics
*Advanced information. Subject to change without notice.
Figure 24: WE#-Controlled
Program Program
AC Timing
(16-Bit(16-Bit
Mode)
Figure 13: WE#-Controlled
AC Timing
Mode)
3rd Cycle
4th Cycle
Data Polling
tWC
READ Cycle
tWC
A[MAX:0]
555h
PA
tAS
PA
tAH
tCH
tCS
tCE
CE#
tGHWL
tOE
OE#
tWP
tWPH
WE#
tWHWH1
tDS
DQ[15:0]
A0h
PD
DQ7#
tDF
DOUT
tOH
DOUT
tDH
1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the data polling register bit and by a READ
Only the third and
fourth cycles
of the PROGRAM
command
are represented.
The PROGRAM
operation
that outputs
the data (DOUT
) programmed
by the previous
PROGRAMcommand
command.
is followed by checking of the data polling register bit and by a READ operation that outputs the data
2. PA is the
of thePROGRAM
memory location
to be programmed. PD is the data to be pro(DOUT) programmed
byaddress
the previous
command.
grammed.
PA is the address
ofisthe
location
to be
programmed.
PD is the data
be(See
programmed.
3. DQ7
thememory
complement
of the
data
bit being programmed
to to
DQ7
Data Polling Bit
[DQ7]). of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]).
DQ7 is the complement
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
See the following
tables for timing details: Read AC Characteristics, WE#-Controlled Write AC
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
Notes: Notes:
1.
2.
3.
4.
Characteristics, and CE#-Controlled Write AC Characteristics.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
39
65
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
Table 19: CE#-Controlled Write AC Characteristics
Parameter
Symbol
Legacy
JEDEC
Address valid to next address valid
tWC
tAVAV
WE# LOW to CE# LOW
tWS
tWLEL
CE# LOW to CE# HIGH
tCP
tELEH
Input valid to CE# HIGH
tDS
tDVEH
CE# HIGH to input transition
tDH
tEHDX
CE# HIGH to WE# HIGH
tWH
tEHWH
CE# HIGH to CE# LOW
tCPH
tEHEL
Address valid to CE# LOW
tAS
tAVEL
CE# LOW to address transition
tAH
tELAX
OE# HIGH to CE# LOW
–
tGHEL
WRITE TO BUFFER PROGRAM
operation (512 words)
tWHWH1
tWHWH1
PROGRAM operation
(single word or byte)
Package
Min
Typ
Max
Unit
Notes
Fortified BGA
100
–
–
ns
TSOP
110
–
–
ns
Fortified BGA
0
–
–
ns
TSOP
0
–
–
ns
Fortified BGA
35
–
–
ns
TSOP
35
–
–
ns
Fortified BGA
30
–
–
ns
1
TSOP
30
–
–
ns
1
Fortified BGA
0
–
–
ns
TSOP
0
–
–
ns
Fortified BGA
0
–
–
ns
TSOP
0
–
–
ns
Fortified BGA
20
–
–
ns
TSOP
20
–
–
ns
Fortified BGA
0
–
–
ns
TSOP
0
–
–
ns
Fortified BGA
45
–
–
ns
TSOP
45
–
–
ns
Fortified BGA
0
–
–
ns
TSOP
0
–
–
ns
Fortified BGA
–
900
–
µs
TSOP
–
900
–
µs
Fortified BGA
–
210
–
µs
TSOP
–
210
–
µs
Note:
1. The user’s write timing must comply with this specification. Any violation of this write timing specification
may result in permanent damage to the NOR Flash device.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
40
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
Parallel NOR Flash
Write AC Characteristics
*Advanced information. Subject to change without notice.
Figure 25: CE#-Controlled
Program AC
Timing
(8-Bit Mode)
Figure 14: CE#-Controlled
Program
AC Timing
(8-Bit Mode)
3rd Cycle
4th Cycle
AAAh
PA
Data Polling
tWC
A[MAX:0]/A-1
tAS
PA
tAH
tWH
tWS
WE#
tGHEL
OE#
tCP
tCPH
CE#
tWHWH1
tDS
DQ[7:0]
A0h
PD
DQ7#
DOUT
tDH
Notes: Notes:
1.
2.
3.
4.
1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the data polling register bit.
Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command
2. PA is the address of the memory location to be programmed. PD is the data to be prois followed by checking
of the data polling register bit.
grammed.
PA is the address
ofisthe
location
to be
programmed.
PD is the data
be(See
programmed.
3. DQ7
thememory
complement
of the
data
bit being programmed
to to
DQ7
Data Polling Bit
[DQ7]).
DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
See the following
tables
timing details:
Read
AC Characteristics,
WE#-Controlled
Write
AC for
Characteristics,
and
CE#-Controlled
Write AC
Characteristics.Write AC
Characteristics, and CE#-Controlled Write AC Characteristics.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
41
67
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
Parallel NOR Flash
Write AC Characteristics
*Advanced information. Subject to change without notice.
Figure 26: CE#-Controlled
Program AC
Timing
(16-Bit(16-Bit
Mode)
Figure 15: CE#-Controlled
Program
AC Timing
Mode)
3rd Cycle
4th Cycle
Data Polling
555h
PA
PA
tWC
A[MAX:0]
tAS
tAH
tWH
tWS
WE#
tGHEL
OE#
tCP
tCPH
CE#
tWHWH1
tDS
DQ[15:0]
A0h
PD
DQ7#
DOUT
tDH
Notes: Notes:
1.
2.
3.
4.
1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the data polling register bit.
Only the third
and
fourth cycles of the PROGRAM command are represented. The PROGRAM command
2. PA is the address of the memory location to be programmed. PD is the data to be prois followed by checking
of the data polling register bit.
grammed.
3.
DQ7
is
the
complement
of the
data
bit being programmed
to to
DQ7
Data Polling Bit
PA is the address of the memory
location
to be
programmed.
PD is the data
be(See
programmed.
[DQ7]).
DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit [DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
See the following
tables
timing details:
Read
AC Characteristics,
WE#-Controlled
Write
AC for
Characteristics,
and
CE#-Controlled
Write AC
Characteristics.Write AC
Characteristics, and CE#-Controlled Write AC Characteristics.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
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42
68
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
Parallel NOR Flash
Write AC Characteristics
*Advanced information. Subject to change without notice.
Figure 27: Chip/Block
AC Timing
Figure 16: Erase
Chip/Block
Erase AC(8-Bit
TimingMode)
(8-Bit Mode)
tWC
A[MAX:0]/
A–1
AAAh
555h
tAS
AAAh
AAAh
AAAh
BAh1
555h
tAH
tCH
tCS
CE#
tGHWL
OE#
tWP
tWPH
WE#
tDS
DQ[7:0]
AAh
55h
80h
AAh
55h
10h/
30h
tDH
1. For a CHIP ERASE command, the address is 555h, and the data is 10h; for a BLOCK ERASE
command, the address is BAd, and the data is 30h.
BAd is
the block the
address.
1. For a CHIP 2.
ERASE
command,
address is 555h, and the data is 10h; for a BLOCK ERASE command,
3.
See
the
following
tables
the address is BAd, and the data is 30h.for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
Notes:
Notes:
2. BAd is the block address.
3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC
Characteristics, and CE#-Controlled Write AC Characteristics.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
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m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
43
69
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
Parallel NOR Flash
Write AC Characteristics
*Advanced information. Subject to change without notice.
Figure 28: Chip/Block
AC Timing
Figure 17: Erase
Chip/Block
Erase AC(16-Bit
Timing Mode)
(16-Bit Mode)
tWC
A[MAX:0]
555h
2AAh
tAS
555h
555h
2AAh
555h
BAh1
tAH
tCH
tCS
CE#
tGHWL
OE#
tWP
tWPH
WE#
tDS
DQ[15:0]
AAh
55h
80h
AAh
55h
10h/
30h
tDH
1. For a CHIP ERASE command, the address is 555h, and the data is 10h; for a BLOCK ERASE
command, the address is BAd, and the data is 30h.
1. For a CHIP 2.
ERASE
command,
address is 555h, and the data is 10h; for a BLOCK ERASE command,
BAd is
the block the
address.
the address3.is BAd,
and
the
data
is
30h.for timing details: Read AC Characteristics, WE#-Controlled
See the following tables
Write
AC
Characteristics,
and CE#-Controlled Write AC Characteristics.
2. BAd is the block address.
Notes: Notes:
3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled Write AC
Characteristics, and CE#-Controlled Write AC Characteristics.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
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m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
44
70
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
22
Accelerated Program, Data Polling/Toggle AC Characteristics
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
Accelerated
DataToggle
Polling/Toggle
AC Characteristics
Table 20: Accelerated
Program andProgram,
Data Polling/Data
AC Characteristics
Accelerated Program, Data Polling/Toggle
AC Characteristics
Symbol
Parameter
Min
Legacy
JEDEC
Table 32: Accelerated Program and Data Polling/Data Toggle AC Characteristics
tVHVPP
VPP/WP# rising or falling time
–
Address setup time to CE# or OE# LOW
tASO
250
Address hold time from OE# or CE# HIGH
VPP/WP# rising or falling time
CE# HIGH time
Address setup time to CE# or OE# LOW
WE# HIGH
logHIGH
(toggle and data polling)
Address hold time from
OE#toorOE#
CE#
Symbol
tAXGL
15
Legacy
JEDEC
tAHT
tGHAX, tEHAX
0
tVHVPP
–
tEPH
tEHEL2
tASO
tAXGL 30
tOEHt
tWHGL2
tGHAX, tEHAX
20
AHT
CE# HIGH time
tOPHtEPH
Parameter
OE# HIGH time
tOEH
WE# HIGH to OE# log (toggle
and data
Program/erase
valid topolling)
RY/BY# LOW
tBUSY
OE# HIGH time
tOPH
Program/erase valid to RY/BY# LOW
tBUSY
Note:
tGHGL2
tWHRL
tEHEL2
tWHGL2
tGHGL2
Max
Unit
–
ns
0
–
–
ns
Unit
ns
ns
ns
ns
ns
ns
20
30
–
–
ns
ns
–
20
90
–
tWHRL
–
Min
250
15
–
–
Max
–
–
20
–
ns
ns
ns
–
90
ns
1. Sampled only; not 100% tested.
Note:
1. Sampled only; not 100% tested.
Figure 29: Accelerated Program AC Timing
Figure 18: Accelerated Program AC Timing
VPP/WP#
VPPH
VIL or VIH
tVHVPP
tVHVPP
Figure 30: Data Polling AC Timing
tCH
tCE
tHZ/tDF
CE#
tOE
tOPH
OE#
tOEH
WE#
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
DQ7
Data
DQ7#
DQ[6:0]
Data
Output flag
45
DQ7#
Valid DQ7
Data
Output flag
Valid
DQ[6:0] Data
tBUSY
Form #: CSI-D-685 Document 003
Figure 29: Accelerated Program AC Timing
VPPH
VPP/WP#
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
VHVPP
VIL or VIH
tVHVPP
t
*Advanced information. Subject to change without notice.
Figure 30: Data Polling AC Timing
Figure 19: Data Polling AC Timing
tCH
tCE
tHZ/tDF
CE#
tOE
tOPH
OE#
tOEH
WE#
DQ7
Data
DQ7#
DQ7#
Valid DQ7
Data
DQ[6:0]
Data
Output flag
Output flag
Valid
DQ[6:0] Data
tBUSY
RY/BY#
Notes:
1. DQ7 returns a valid data bit when the PROGRAM or ERASE command has completed.
Notes:
Micron
Technology,
Inc. reserves the right
products or specifications without notice.
1. DQ7 returns a valid data bit when the PROGRAM
or
ERASE
command
hasto change
completed.
71
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m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
© 2012 Micron Technology, Inc. All rights reserved.
2. See the following tables for timing details: Read AC Characteristics, Accelerated Program and Data
Polling/Data Toggle AC Characteristics.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
46
Form #: CSI-D-685 Document 003
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
1Gb Parallel
NOR Flash
Accelerated Program, Data Polling/Toggle
AC Characteristics
MYX28F00AM29EWH*
2. See the following tables for timing details: Read AC Characteristics, Accelerated Program and Data Polling/Data Toggle AC Characteristics.
*Advanced information. Subject to change without notice.
Figure 20: Toggle/Alternative
Toggle
Bit Polling
AC Timing
Figure 31: Toggle/Alternative
Toggle Bit
Polling
AC Timing
A[MAX:0]/
A–1
tAHT
tASO
CE#
tOEH
tAHT
tASO
WE#
tOPH
tEPH
tOPH
OE#
tDH
DQ6/DQ2
tOE
Data
Toggle
tCE
Toggle
Toggle
Stop
toggling
Output
Valid
tBUSY
RY/BY#
1. DQ6 stops toggling when the PROGRAM or ERASE command has completed. DQ2 stops
toggling when the CHIP ERASE or BLOCK ERASE command has completed.
Notes:
2. See the following tables for timing details: Read AC Characteristics, Accelerated Pro1. DQ7 returns a gram
valid data
bit when
the PROGRAM
command has completed.
and Data
Polling/Data
Toggle or
ACERASE
Characteristics.
Notes:
2. See the following tables for timing details: Read AC Characteristics, Accelerated Program and Data
Polling/Data Toggle AC Characteristics.
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. C 9/14 EN
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
72
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
47
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
23
Program/Erase Characteristics
Table 21: Program/Erase Characteristics
Notes 1 and 2 apply to the entire table.
Parameter
Block erase (128KB)
Erase suspend latency time
Block erase timeout
Single-byte program
Byte program
Byte write to buffer
program
Effective write to buffer
program per byte
Single-word program
Word write to buffer
program
Word program
Effective write to buffer
program per word
Program suspend latency time
Blank check
Set nonvolatile protection bit time
Clear nonvolatile protection bit time
PROGRAM/ERASE cycles (per block)
Erase to suspend
Buffer Size
Byte
Word
Min
Typ
Max
Unit
Notes
–
–
–
–
64
128
256
64
128
256
–
32
64
128
256
512
32
64
128
256
512
–
–
–
–
–
–
–
–
–
–
64
128
256
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
32
64
128
256
512
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
100,000
–
0.8
27
–
210
270
310
375
4.22
2.42
1.46
210
270
310
375
505
900
8.44
4.84
2.93
1.97
1.76
27
3.2
210
0.8
–
500
4
37
50
456
716
900
1140
11.2
7
4.45
456
716
900
1140
1690
3016
22.4
14.1
8.9
6.6
5.89
37
–
456
4
–
–
s
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
µs
s
cycles
µs
3
Notes:
1. Typical values measured at room temperature and nominal voltages.
2. Typical and maximum values are sampled, but not 100% tested.
3. Erase to suspend is the typical time between an initial BLOCK ERASE or ERASE RESUME command and
a subsequent ERASE SUSPEND command. Violating the specification repeatedly during any particular
block erase may cause erase failures.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
48
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
24
*Advanced information. Subject to change without notice.
256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded
Parallel NOR Flash
Package Dimensions
Package Dimensions
Figure 33: 64-Ball Fortified BGA – 11mm x 13mm
Figure 21: 64-Ball Fortified BGA – 11mm x 13mm
0.80 TYP
Seating
plane
0.10
64X
8
7
6 5
4 3 2 1
3.00
TYP
A
B
C
13.00 ±0.10
D
7.00 TYP
E
F
G
H
1.00
TYP
1.00
TYP
0.60 ±0.05
2.00 TYP
1.40 MAX
0.48 ±0.05
7.00 TYP
11.00 ±0.10
Notes:
Notes:
1. All dimensions are in millimeters.
2. Only 2Gb (1Gb/1Gb) has A1 mark at the bottom.
1. All dimensions are in millimeters.
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
49
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
25
Ordering Information
Table 22: Ordering Information
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
Part Number
Device Grade
MYX28F00AM29EWHBG-ITRL
Industrial
50
Form #: CSI-D-685 Document 003
1Gb Parallel NOR Flash
MYX28F00AM29EWH*
*Advanced information. Subject to change without notice.
Document Title
1Gb - 64M x 16 Parallel NOR Flash Embedded Memory
Revision History
Revision #
History
Release Date
Status
1.0
Initial release
November 14, 2014
Preliminary
MYX28F00AM29EWH
Revision 1.0 - 11/14/2014
51
Form #: CSI-D-685 Document 003
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