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Analog Digital Lab
ST2613
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Operating Manual
Ver 1.1
94-101, Electronic Complex Pardeshipura,
Indore- 452010, India
Tel : 91-731- 2570301/02, 4211100
Fax: 91- 731- 2555643
email : [email protected]
Website : www.scientech.bz
Toll free : 1800-103-5050
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An ISO 9001 : 2000 company
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Analog Digital Lab
ST2613
Table of Contents
1.
Introduction
6
2.
Features
7
3.
Technical Specifications
8
4.
Functional Block Description
9
5.
Operating Instruction & Panel Control Description
10
6.
Experiments
Experiment 1
Study of Half Wave Rectifier
11
•
Experiment 2
Study of Full Wave Rectifier
15
•
Experiment 3
Study of Zener Diode as a Voltage Regulator
21
•
Experiment 4
Study of Transistor series Voltage Regulator
27
•
Experiment 5
Study of Transistor shunt Voltage Regulator
33
•
Experiment 6
Study of Low Pass Filter
37
•
Experiment 7
Study of High Pass Filter
46
•
Experiment 8
Study of Band Pass Filter
52
•
Experiment 9
Study of Active Notch Filter
•
Experiment 10
Study of CE configuration of NPN transistor
65
•
Experiment 11
Study of CB configuration of NPN transistor
75
•
Experiment 12
Study of CC configuration of NPN transistor
85
•
Experiment 13
Study of CE Amplifier circuit
96
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Experiment 14
Study of Gain Characteristics of a Noninverting Amplifier
104
•
Experiment 15
Study of Voltage Follower Configuration
112
•
Experiment 16
To study Op Amp in Inverting Configuration
115
•
Experiment 17
Study of operations of Wheatstone Bridge
120
•
Experiment 18
Study of the operations of De Sauty’s Bridge
125
•
Experiment 19
Study and observation of Op-Amp as a Wien Bridge Oscillator
131
•
Experiment 20
Study of and observe Op-Amp as a Phase Shift Oscillator
136
•
Experiment 21
Study of Operation of Logic Gates
141
•
Experiment 22
Study of Binary Adder
156
•
Experiment 23
Study of 2 Bit Binary Subtracter
163
•
Experiment 24
Study of Binary to Gray code conversion
167
•
Experiment 25
Study of Gray code to Binary code conversion
172
•
Experiment 26
Study of Binary to Excess-3 code conversion
177
•
Experiment 27
Study of characteristics of various types of Flip-Flops
182
•
Experiment 28
Study of Crystal Oscillator
197
•
Experiment 29
Study 4 of Bit Binary Up-Down Counter
•
Experiment 30
Study of Johnson Counter
•
Experiment 31
Study of 4 Bit serial in parallel out Shift Register
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Experiment 32
Study of 8 to 3 Line Encoder
211
•
Experiment 33
Study of 3 to 8 Line Decoder
214
•
Experiment 34
Study of Multiplexer and De-multiplexer circuit
218
•
Experiment 35
Study of Pulse Stretcher circuit
224
•
•
Experiment 36
Study of Method of Interfacing CMOS logic family
with TTL logic family
226
7.
Electronic Graphical Symbol used in circuit diagrams
228
8.
Data Sheet
231
9.
Warranty
244
10.
List of Accessories
244
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Introduction
Designed a circuit and now developing it? Lets get those bare minimum articulate
needed; an Oscilloscope, a Function Generator and also a Power Supply. Only if you
are lucky enough to need just those three bulky heavy duty things; in other case there
may be a pulse generator, may be some logic generators and detectors are also one of
the things. You have to arrange all of these!
ST2613 Analog-Digital Lab is designed to fulfill requirement of doing experiments
of analog and digital electronics in a single trainer.
This makes it easy to design, experiment with, and test circuitry without etching and
soldering PCB. Students explore a wide variety of electronic concepts simply by
sticking components into the breadboard. All connections and controls are clearly
marked and conveniently located. It is very useful in analog and digital electronics
laboratories for performing experiments in colleges and universities. It is also useful
in testing and making projects related to electronics.
Analog Digital Lab comprises of following blocks :
DC Power Supply
•
AC Power Supply
•
Sine/Square/TTL Generator
•
8 Bit Data Switches
•
Speaker
•
Logic Probe
•
Potentiometers
•
8 Bit LED Display
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Features
•
Self Contained and easy to operate
•
Functional blocks indicted on board mimic
•
On board DC and AC power supply
•
On board Sine/Square /TTL generator
•
On board 8 Bit Data Switches and 8 Bit LED display
•
On board Logic Probe, Speaker and Potentiometers
•
Solderless Breadboard
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Technical Specifications
DC Power Supplies
:
+ 5V; 1A (Fixed)
+ 15V; 1A (Fixed)
– 15V; 1A (Fixed)
+ 15V; 200mA (Variable)
– 15V; 200mA (Variable)
AC Supply
:
5V- 0V- 5V, 10V- 0V- 10V can be used as 5V,
10V, 15V, 20V & also as center tap.
Breadboard
:
172.5mm x 128.5mm.
Test Points
:
1685
Sine/Square/TTL Generator :
Frequency range 10Hz to 1MHz in 4 steps and
Variable within the steps
Output
Sine wave
:
: 15Vpp
Square Wave : 10Vpp
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TTL
: 5V
:
0.1Hz
Data Switches
:
8 in Nos (Toggle switches for High/Low TTL
levels)
LED Display
on
Fixed TTL (Clock)
8 in Nos (for High/Low TTL levels indication)
:
Logic level indicator for TTL (7Seg.)
:
6 in Nos. (100Ω to 47KΩ)
:
8 ohms for audio use.
:
230V ± 10%; 50Hz
Power Consumption
:
8 VA
Dimensions (mm)
:
W325 x H90 x D255
Weight
:
4Kgs. (Approximately).
Logic Probe
Potentiometers
Speaker
Power Supply
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Functional Block Description
DC Power supply :
This block provides fixed DC output of +5V, +15V, –15V at 1A and variable DC
output from 0V to +15V and 0V to –15V at 200mA
AC Power Supply :
This block provides 10V- 5V- 0V- 5V- 10V AC at 200mA. It can be configured to get
5V- 0V- 5V, 10V- 0V- 10V, 10V- 0V, 5V- 0V, 15V- 0V, 20V- 0V AC.
Sine\Square\TTL Generator :
This block generates Sine, Square, TTL waveform of frequency range 10 Hz to
1MHz. Amplitude of sine wave can be varied from xyz to 15V and square wave from
xyz to 10V. Fixed 0.1 Hz TTL clock is also available.
8 Bit Data Switches :
8 bit data switches are provided to give input to digital ICs. Logic 1 is +5V and logic
0 is GND. LED indication is given for logic 1.
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Speaker :
Audio output (20 Hz to 20 KHz) can be given to the speaker to see the amplifier
response.
Logic Probe :
Logic High = 2V to 5V
Logic 0 = 0V to 0.4V.
Potentiometer :
on
Logic probe is provided to display logic levels of TTL family. The inputs to the probe
will be output from TTL ICs.
8 Bit LED Display :
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Potentiometers of 100Ω, 1K, 4K7, 10K, 20K, 47K is provided as variable resistances.
The Display is provided to indicate high and low levels. For voltages between 1 to
5volts, LEDs will glow red and for voltages less than 1V LEDs will not glow.
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Operating Instruction and Panel Control Description
Analog Digital Lab is provided with external DC power supply. Connect PS1, PS2
connectors of the Analog Digital Lab Power supply to Analog-Digital lab on the
indicated position. When power switch of the supply is turned ON, the power switch
will lit indicating that supply is ON. Three fixed regulated DC power supply of +5V,
+15V, -15V of 1A each is provided. Two variable DC power supply of +15V and 15V are given. When +15V and –15V potentiometer of DC power supply are in their
fully clockwise position, full voltage +15V and –15V is obtained. +15V and –15V
potentiometers can be varied to get variable positive and negative supply from 0 to
+15V and 0 to –15V. Fine potentiometer of Sine/Square/TTL generator is used for
fine setting of frequency of waveforms. Amplitude Potentiometer is used to vary
amplitude of sine, square wave.
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Range switch is used to select frequency from 10Hz to 1MHz in variable steps.
Sine/Square switch is used to select waveform at output Socket. High\Low switch is
used to select TTL frequency range. Switch at position High will select variable TTL
clock from 10 Hz to 1MHz at TTL socket. Frequency can be varied with Range
switch. At Low position a fixed TTL clock of 0.1 Hz is obtained at TTL socket.
Potentiometers of 100Ω, 1K, 4K7, 10K, 20K and 47K are provided to vary
resistances. Pull up resistance of 1K (between +5V and output) is required with open
collector output ICs. Electronic Graphical Symbols, lead details of transistor and pin
diagrams of ICs are given at the end of manual.
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Experiment 1
Objective :
Study of Half Wave Rectifier
Equipments Needed :
Component
Quantity
1.
Resistance 1 K
1
2.
Diode 1N4007
1
3.
Capacitor 47µF
1
Rectifier is an electronic device that converts alternating current into direct current. A
rectifier changes AC into DC by eliminating the negative half-cycles of the alternating
voltage, so it provides a one way path for electric current i.e. conduction takes place
in one direction only. It is in this way that a rectifier converts an alternating current
into unidirectional current.
Rectifier can be classified into two categories :
Half-Wave Rectifier
2.
Full-Wave Rectifier
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1.
Half Wave Rectifier :
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Half wave rectifier conducts only on positive half cycles of input voltages i.e. it uses
one half cycles of AC input voltages to produce DC output .On the other hand, a fullwave rectifier conducts on both the half cycles of input AC voltage to produce DC
output. So a full wave rectifier circuit can supply more DC output more than the
equivalent Half-Wave Rectifier.
A Half Wave Rectifier employs a single diode as shown in figure below:
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Figure 1
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During the positive half cycle of the input voltage diode conducts, so a short circuit
equivalence of the ideal diode will result in an output signal which is an exact replica
of the input signal. For the negative half cycle of the applied signal, diode is in the off
state with an open circuit equivalent, which results in the absence of a path for the
charge to flow, so a zero voltage appears for the negative half cycle of input voltage.
Vdc = 0.318Vm
Limitation of Half wave Rectifier :
The AC power delivers only half the time, hence output is low.
Peak inverse voltage :
The maximum reverse-bias potential that can be applied to a diode before entering the
Zener region is called peak inverse voltage or peak reverse voltage.
Half wave Rectifier PIV rating ≥ Vm
Rectification efficiency :
The ratio of DC output power to the AC power input in a rectifier is known as
rectification efficiency.
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η = DC output power
AC input power
Efficiency of Half wave rectifier :
on
Pdc =I2dc× RL= {Im/ п} 2× RL
Pac=I2rms (rf+ RL), Irms =Im/2
rf is diode resistance
η = Pdc / Pac =0.406/ (1+ rf / RL) ………….……. (1)
Ripple factor :
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The ratio of r.m.s. value of AC component to the DC component in the rectifier output
is known as ripple factor. The smaller the ripple factor, the lesser the effective AC
component and hence more effective is the rectifier.
Ripple factor = r.m.s. value of AC component
Value of DC component
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Mathematical analysis
Ripple Factor= √ (Irms / Idc) 2-1
Half wave rectification :
Irms =Im/2
;
Idc=Im/ п
Putting values in equation 3 we get
Ripple Factor=1.21
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……………………………
(2)
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Filter circuit :
The output of a rectifier has a pulsating character i.e. it contains AC and DC
components. However, in electronic circuits, we need a DC voltage that is constant
value. So a filter circuit is installed at the rectifier output .The filter circuit filters out
the AC components from the rectifier output and allows only the DC component to
reach the load .Thus a constant DC voltage appears across the load.
Circuit diagram :
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Procedure :
Figure 2
Make connections as shown in the figure 2.
2.
Connect 10 V and 0 V AC terminals from AC Power supply to terminals 1 and
2.
3.
Disconnect capacitor C from the circuit.
4.
Switch ON the instrument.
5.
Connect terminals 3 and 4 to oscilloscope and observe output.
6.
Now connect capacitor C at its place and observe output on oscilloscope.
7.
Press AC/DC switch of oscilloscope i.e. keep your oscilloscope in DC mode to
see DC voltage.
8.
Press AC/DC switch again i.e. put the oscilloscope in AC mode again and
observe ripple.
9.
Decrease load resistance and observe ripple.
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Observation :
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1.
1.
Capacitor is used as a filter to smoothen Pulsating DC (positive peaks).
2.
When load current increases, amplitude of ripple increases.
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Observation Table :
S. No.
Vout
Output voltage
of Rectifier
(volt)
Vout’
Output voltage of
Filter (volt)
Efficiency
of Rectifier
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Results :
VIN
Input voltage
(volt)
Output voltage Vo =…………………………………..
2.
Efficiency (using equation 1) = ………………………………
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Experiment 2
Objective :
Study of Full Wave Rectifier
1.
Conventional Full wave rectifier
2.
Bridge Rectifier
Equipments Needed :
Component
Quantity
1.
Resistors 1K
1
2.
Diodes 1N4007
4
3.
Capacitor 47µF
1
Full Wave Rectifier :
The DC level obtained from a sinusoidal input can be improved to 100% using a
process called full wave rectification.
A full wave rectifier can be classified into two categories :
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a.
Center-Tapped full wave rectifier
b.
Full-wave Bridge Network
Center-Tapped Full Wave Rectifier :
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Center-Tapped full wave rectifier requires two diodes and a center-tapped
transformer. The circuit diagram is shown in figure 3.
Figure 3
During the positive portion of input signal diode D1 conducts so there exists a short
circuit equivalent across D1 and open circuit equivalent across D2 and the output
voltage appears across load resistor RL. During the negative portion of input voltage
the roles of the diodes are reversed but maintaining the same polarity for the voltage
across the load resistor RL. The net effect is the same output as that appearing for full
wave rectifier with same DC level.
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Limitations of Center Tap Full wave Rectifier :
1.
It is difficult to locate center tap on the secondary winding.
2.
The DC output is small as each diode utilizes only one-half of the transformer
secondary winding.
3.
The diode must have high peak inverse voltage.
Full Wave Bridge Network :
Bridge network requires four diodes for its operation. The circuit diagram is shown in
figure 4.
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Figure 4
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During the period 0 to t/2 diodes D2 and D3 are conducting while diodes D1 and D4
are in off state, so for the ideal diodes the load voltage Vo =Vi. For the negative
portion of the input voltage diodes D1 and D4 are conducting resulting in positive
pulse across load resistor RL.
Vdc=0.636Vm
Advantages of Bridge Rectifier :
The need for center tapped transformer is eliminated.
2.
The output is twice that of center-tap circuit for the same secondary voltage.
3.
The PIV is one half that of the center-tap circuit.
Disadvantages of Bridge Rectifier :
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1.
1.
It requires four diodes.
2.
As during each half cycle of AC input diodes that conduct, are in series
,therefore the voltage drop in the internal resistance of the rectifying unit will be
twice as great as in the center circuit .This is objectionable when secondary
voltage is small.
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Important parameters for rectifier circuits :
Peak inverse voltage :
The maximum reverse-bias potential that can be applied to a diode before entering the
Zener region is called peak inverse voltage or peak reverse voltage.
Center tap Full wave Rectifier PIV rating ≥ 2Vm
Full wave Bridge Rectifier PIV rating ≥ Vm
Rectification efficiency :
The ratio of DC output power to the AC power input in a rectifier is known as
rectification efficiency.
η=
ac output power
dc input power
Efficiency of Full wave rectifier (Center tap and Bridge Rectifiers) :
Idc=2Im/ п, Pdc =I2dc× RL= {2Im/ п} 2× RL
Irms =Im/√2, Pac=I2rms (rf+ RL)
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η = Pdc / Pac = 0.812/ (1+ rf / RL) …………..…….……… (1)
Ripple factor :
on
The ratio of r.m.s. value of AC component to the DC component in the rectifier output
is known as ripple factor. The smaller the ripple factor, the lesser the effective AC
component and hence more effective is the rectifier.
Ripple factor =
Mathematical analysis
r.m.s. value of ac component
value of dc component
Full wave rectification :
Irms =Im/√2
;
Idc=2Im/ п
Putting values in equation 3 we get
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Ripple Factor= √ (Irms / Idc ) 2-1 ……………………………………………. .…. (2)
Ripple Factor=0.48
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Comparison of Rectifiers :
S. No.
Particulars
Half -wave
Center -tap
Bridge type
1.
No. of diodes
1
2
4
2.
Transformer
necessary
no
yes
no
3.
Max. efficiency
40.6%
81.2%
81.2%
4.
Ripple factor
1.21
0.48
0.48
5.
Output frequency
fin
2 fin
2 fin
6.
Peak inverse voltage
Vm
2Vm
Vm
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Filter circuit :
Circuit diagram :
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The output of a rectifier has a pulsating character i.e. it contains AC and DC
components. However, in electronic circuits, we need a DC voltage that is constant
value. So a filter circuit is installed at the rectifier output. The filter circuit filters out
the AC components from the rectifier output and allows only the DC component to
appear at the load .Thus a constant DC voltage appears across the load.
Center-Tapped Full Wave Rectifier
Figure 5
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Full Wave Bridge Network
Figure 6
Procedure :
Make connection as shown in the figure 5.
2.
Connect 10V - 0V -10V AC terminals from AC Power supply to terminals 1, 2
and 3.
3.
Disconnect capacitor C from the circuit.
4.
Switch ON the instrument.
5.
Connect terminals 4 and 5 to oscilloscope and observe output.
6.
Now connect capacitor C at its place and observe output on oscilloscope.
7.
Press AC/DC switch of oscilloscope i.e. keep your oscilloscope in DC mode to
see DC voltage.
8.
Press AC/DC switch again i.e. put the oscilloscope in AC mode again and
observe ripple.
9.
Decrease load resistance and observe ripple.
10.
Repeat above steps for bridge rectifier as shown in figure 6. (Take supplies 10
V-0V).
Observation :
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1.
Capacitor is used as a filter to smoothen Pulsating DC (positive peaks).
2.
When load current increases, amplitude of ripple increases.
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Observation Table :
S. No.
Vout
Output voltage
of Rectifier
(volt)
Vout’
Output voltage of
Filter (volt)
Efficiency
of Rectifier
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Results :
VIN
Input voltage
(volt)
Output voltage Vo =…………………………………..
2.
Efficiency (using equation) = ………………………………
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Experiment 3
Objective :
Study of Zener Diode as a Voltage Regulator
Equipments Needed :
Component
1.
Resistance 52Ω 1W
2.
Potentiometer
3.
Quantity
1
1K
1
100K
1
Zener Diode 5.6V
1
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Voltage regulation is a measure of a circuit's ability to maintain a constant output
voltage even when either input voltage or load current varies. A zener diode, when
working in the break down region, can serve as a voltage regulator. In figure 7, Vin is
the input voltage whose variations are to be regulated. The load resistance across
which a constant voltage Vout is required, is connected in parallel with the Zener
diode. When potential difference across the diode is greater than VZ, it conducts and
draws relatively large current through the series resistance R. The total current I
passing through R equal the sum of diode current and load current i.e.
I = IZ + IL.
on
It will be seen that under all conditions, Vout = VZ.
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Figure 7
Case 1 : Variable input voltage Vin and fixed load resistance RL.
In this case, when input voltage Vin is increased slightly keeping load resistance RL
constant. It will increase I. This increase in I will be absorbed by the Zener diode
without affecting IL. This increase in Vin will be dropped across R thereby keeping
Vout constant.
Conversely, if supply voltage Vin falls, the diode takes a smaller current and voltage
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drop across R is reduced, thus again keeping Vout constant.
Hence, when Vin changes, I and IR drop change in such a way as to keep Vout (= VZ)
constant.
For fixed value of RL, the voltage Vin must be sufficiently large to turn the Zener
diode 'ON'. The minimum turn-on voltage Vin (min) is determined by
Vin (min) = (RL + R) VZ / RL
The maximum value of Vin is limited by the maximum Zener current IZM . Since
IZM = IR - IL, IRmax = IZM + IL
Since IL if fixed at VZ/RL and IZM is the maximum value of Iz, the maximum Vin is
defined by
Vin (max) = IRmax R + Vz
Case 2 : Fixed input voltage Vin and variable Load resistance RL.
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In this case Vin is fixed but RL hence IL is changed. When IL increases, diode current
IZ decreases thereby keeping I and hence IR drop constant. In this way Vout remains
unaffected. When IL decreases, diode current IZ increases thereby keeping I and hence
IR drop constant. In this way again Vout remains unchanged.
on
Due to the offset voltage Vz, there is a specific range of resistor values (and therefore
load current) which will ensure that the Zener is in the 'on' state. Too small a load
resistance RL will result in a voltage VL across the load resistor less than VZ and the
Zener device will be in the 'off’ state.
To determine the minimum load resistance that will turn the Zener diode ‘on’ is given
by
RLmin = RVz / (Vin – VZ)
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Any load resistance value greater than the RL obtained from above equation will
ensure that the zener diode is in the 'on' state and the diode can be replaced by its VZ
source equivalent.
Similarly maximum load resistance is given by
RLmax = VZ / ILmin
Where
Note :
1.
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ILmin = IR - IZM
IR = VR / R,
VR = Vin - VZ
Regulated output voltage might be slightly higher than the expected voltage due
to tolerance of Zener diode.
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Circuit diagram :
Figure 8
Procedure For Case I :
Make connections as shown in the figure 8.
2.
Connect + 10V supply from DC power supply block to 1 and 2.
3.
Connect voltmeter across terminal 3 and ground to measure input voltage.
4.
Connect ohmmeter across terminal 5 and ground to measure load resistance.
5.
Vary potentiometer P2 and set the value of resistance between terminal 5 and
ground to 2K.
6.
Connect terminal 4 and 5.
7.
Connect voltmeter 2 across terminal 5 and ground to measure output voltage.
8.
Switch ON the supply.
9.
Vary the Input voltage with the potentiometer P1 in steps between 6V to 8V and
measure the corresponding values of output voltage.
Observations :
1.
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1.
In first case when input voltage is varied keeping load resistance constant (2K),
regulated 5.6V across load is obtained.
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Observation Table 1 :
Input
voltage Vin
1.
6.0V
2.
6.5V
3.
7.0V
4.
7.5V
5.
8.0 V
6.
8.5V
7.
8.
Output voltage Vout (volt)
at constant Load resistance = 2K
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S. No.
9.0V
9.5V
on
Calculations :
Determine the range of input voltage when load resistance is fixed while the input
voltage is variable, by using formula, Minimum turn-on voltage Vin (min) is
RL is the fixed value of load resistance
R is the series resistance
VZ is the Zener breakdown voltage
In the circuit used RL = l K, R = 51Ω, Vz = 5.6 V
Maximum value of input voltage Vi (max) is given by
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Vin (min) = (RL + R) VZ / RL
Where
Vin (max) = IRmax R + V z
Where
IRmax = IZM + IL
IZM = IR - IL,
IL = VZ / RL
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In the circuit used VZ = 5.6V, R = 51Ω, IZM = 65mA, RL = 1K
Results :
1.
Theoretically the range of input voltage obtained is :
Vin (min) = ______________
Vin (max) = ______________
2.
The result of Experiment 3 reveals that for the network of figure 8 with a fixed
load resistance RL, the output voltage will remain fixed at 5.6 V for a range of
input voltage that extends from ___________ to______________.
Procedure For Case 2 :
Make connections as shown in the figure 8.
2.
Connect + 10V supply from DC power supply block to 1 and 2.
3.
Connect voltmeter across terminal 3 and ground to measure input voltage.
4.
Connect ohmmeter across terminal 5 and ground to measure load resistance.
5.
Vary potentiometer P2 and set the value of resistance between terminal 5 and
ground to 10 K.
6.
Connect terminal 4 and 5.
7.
Connect voltmeter 2 across terminal 5 and ground to measure output voltage.
8.
Switch ON the supply.
9.
Check the output.
10.
Disconnect terminal 4 and 5.
11.
Connect ohmmeter between terminal 5 and ground.
12.
Set the potentiometer P2 so that the value of resistance between terminal 5 and
ground is maximum.
13.
Connect terminal 4 and 5.
14.
Adjust input voltage V1 equal to 9V with the potentiometer P1.
15.
Vary the load resistance RL with the potentiometer P2 from its maximum value
to minimum value and measure the output voltage across terminal 5 and ground.
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Observations :
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1.
In Second case when load resistance is varied keeping input voltage constant (9V),
regulated 5.6V across load is obtained.
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Observation Table 2 :
Load
Resistance RL
1.
100Ω
2.
200Ω
3.
300Ω
4.
400Ω
5.
500Ω
6.
600Ω
7.
700Ω
8.
800Ω
9
900Ω
10.
1.0K
11.
12.
Output voltage Vout(volt) at constant Input
voltage Vin = 9volt
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S. No.
2.0K
3.0K
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Calculations :
Determine the range of load resistance for case second i.e. when input voltage is fixed
while the load resistance is variable, by using formula, Minimum load resistance
RLmin = RVz / (Vin - Vz)
Where
R is the resistance in series, Vz is the Zener breakdown voltage Vin is the fixed input
voltage applied
In the circuits used Vz = 5.6V, R = 51Ω, Vin = 10V
Maximum load resistance
RLmax = Vz / ILmin
where
ILmin = IR - IZM, IR = VR / R, VR = Vin - VZ
In the circuit used Vz = 5.6V, R = 51Ω, IZM = 65mA
Results :
1.
Theoretically the range of Load resistance obtained is
RLmin =
___________
RLmax =
___________
2.
The result of Experiment 2 reveals that for the network of figure 8 with a fixed
input voltage Vin the output voltage will remain fixed at 5.6V for a range of load
resistance that extends from
_______ to _______.
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Experiment 4
Objective :
Study of Transistor series Voltage Regulator
Equipments Needed :
Component
1.
2.
Quantity
Resistor
200 ohm
1
100 ohm
1
Potentiometer
1K
1
100K
1
3.
NPN Transistor STN 3904 1
4.
Zener Diode 5.6V
1
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Circuits that maintain power supply voltages or current output within specified limits,
or tolerances are called Regulators. They are designated as DC voltage or DC current
Regulators, depending on their specific application.
su
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Voltage Regulator circuits are additions to basic power supply circuits, which are
made up of rectifier and filter sections as shown in figure 9. The purpose of the
voltage regulator is to provide an output voltage with little or no variation. Regulator
circuits sense changes in output voltages and compensate for the changes.
Figure 9
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There are two types of voltage regulators. Basic voltage regulators are classified as
either Series or Shunt, depending on the location or position of the regulating
element(s) in relation to the circuit load resistance. Figure 10 illustrates these two
basic types of voltage regulators. Broken lines have been used in the figure 10 to
highlight the difference between the Series and Shunt Regulators.
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Figure 10
The schematic shown in figure 10 (B) is a series regulator. It is called series regulator
because the regulating device is connected in series with the load resistance. Figure 10
(B) illustrates the principle of series voltage regulation. From the figure 10 it is clear
that the regulator is in series with the load resistance (RL) and that the fixed resistor
(RS) is in series with the load resistance. You already know the voltage drop across
affixed resistor remains constant unless the current flowing through it varies
(increases or decreases).
su
The schematic for a typical series voltage regulator is shown in figure 11. Notice that
this regulator has an NPN transistor 2N3904 in place of the variable resistor found in
figure 10 (B).
Because the total load current passes through this transistor, it is sometimes called as
‘‘pass transistor’’. Other components, which make up the circuit, are the current
limiting resistor of 200Ω and the Zener diode of 5.6V
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Figure 11
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Recall that a Zener diode is a diode that block current until a specified voltage is
applied. Remember also that the applied voltage is called breakdown, or Zener
voltage. When the Zener voltage is reached, the Zener diode conducts from its anode
to its cathode (with the direction of the arrow).
Circuit Operation :
on
In this voltage regulator, Transistor has a constant voltage applied to its base. This
voltage is often called the Reference Voltage. As the change in the circuit output
voltage occur, they are sensed at the emitter of the transistor producing a
corresponding change in the forward bias of the transistor. In other words, transistor
compensates by increasing or decreasing its resistance in order to change the circuit
voltage division.
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Case 1 : When the input voltage is constant while Load varies.
Here NPN Transistor used in series controls the amount of the input voltage that gets
to the output and zener diode provides the reference voltage. The zener establishes the
value of the base voltage for transistor. Keep in mind the polarities of different
voltages, they are related by the equation
Therefore
VBE = VZ − VL
Kirchoff's voltage law
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VL + VBE − V z = 0
Here VZ is fixed
The output voltage across load will equal to the zener voltage minus a 0.7-volt drop
across the forward biased base-emitter junction of transistor, or 4.9V (5.6 − 0.7).
When current demand is increased by decreasing RL, VL tends to decrease. It will
increase VBE because VZ is fixed. This will increase forward bias of the transistor
thereby increasing its level of conduction. This will lead to decrease in the collectoremitter resistance of the transistor which will slightly increase the input current to
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compensate the decrease in RL so that VL = ILRL will remain at constant value.
Case 2 : When the input voltage varies while Load remains constant.
When the input voltage increases, output voltage across the transistor increases
momentarily. This momentarily deviation or variation, from the required regulated
output voltage of 4.9volts is a result of a rise in the input voltage. Since the base
voltage of transistor is held at 5.6V by zener, that's why the forward bias of transistor
decreases. Because this bias voltage is less than the normal 0.7volts, the resistance of
transistor increases, thereby increasing the voltage drop across the transistor.
This voltage drop restores the output voltage to the required regulated voltage of
4.9V.
Note :
1.
Regulated output voltage might be slightly higher than the expected voltage due
to tolerance of Zener diode.
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Circuit diagram :
Voltage Regulator
Figure 12
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Procedure :
1. Make connections as shown in the figure 12.
Connect + 10V supply from DC power supply block to 1 and 2.
3.
Connect voltmeter 1 across terminal 3 and ground to measure input voltage.
4.
Connect ohmmeter 2 across terminal 6 and ground to measure output voltage.
5.
Vary potentiometer P2 and set the value of resistance between terminal 6 and
ground to 500 ohm.
6.
Connect terminal 5 and 6.
7.
Switch ON the supply.
8.
Connect voltmeter between terminal 6 and ground.
9.
Vary the input voltage with the potentiometer P1 in steps between 6.5V to 9.5V
and measure the corresponding values of output.
10.
Measure voltage VBE between terminals 4 and 5, terminal 4 and ground (zener
voltage) at every step.
11.
Disconnect terminal 5 and 6.
12.
Set the potentiometer P2 so that the value of resistance between terminal 6 and
ground is 100 ohm (minimum).
13.
Connect terminal 5 and 6.
14.
Adjust input voltage V1 equal to 9V with the potentiometer P1.
15.
Vary the load resistance RL with potentiometer P2 from its minimum value to
maximum value and measure output voltage.
16.
Measure the zener voltage between terminals 4 and ground, voltage VBE across
terminals 4 and 5 at every step.
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Observation Table :
Sr.
No.
Load
Resistance
RL
1.
Full Load (1.1K)
2.
1KΩ
3.
800Ω
5.
Forward
bias
voltage
VBE
Output voltage
Vout at constant
Input voltage
Vin = 9volt
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4.
Voltage
Across
Zener
VZ
600Ω
400Ω
200Ω
7.
No Load
Observations :
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6.
In first case when input voltage is varied keeping load resistance constant
(500Ω), regulated output voltage equal to 4.9V between the points 6 and ground
is obtained.
2.
In second case when load resistance is varied keeping input voltage constant
(9V), Regulated Voltage of 4.9V across load resistance RL is obtained.
3.
Output voltage across load is always equal to the difference of zener voltage and
VBE of the NPN transistor.
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Experiment 5
Objective :
Study of Transistor Shunt Voltage Regulator
Equipments Needed :
Component
1.
Quantity
Resistance
200 ohm
1
52 ohm (lW)
1
2.
Potentiometer 1K
2
3.
NPN transistor STN 3904
1
4.
Zener diode 5.6V
1
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The schematic drawing in the figure 13 is a Shunt Regulator. It is called as shunt
regulator because the regulating device is connected in shunt or in parallel with the
load resistance. Figure 13 illustrates the principle of shunt voltage regulation. From
the figure 13 it is clear that the regulator is in shunt with the load resistance (RL). In a
shunt voltage regulator, as shown in figure 13, Output voltage regulation is
determined by parallel resistance of the regulating device, the Load resistance (RL),
and the series resistor Rs. If the load resistance RL increases/decreases, the regulating
device decreases/increases its resistance to compensate for the change.
Since AB is in parallel, across VL, we have
VL −VZ −VBE = 0 or VBE = VL −VZ
Also VL = VZ + VBE
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Figure 13
The schematic for a typical shunt voltage regulator is shown in figure 14. It employs
the NPN transistor in shunt configuration in place of the variable resistor found in
figure 13.
(Kirchoff's Voltage Law)
i.e. The output voltage is close to the sum of the voltage across Zener and the voltage
at the base-emitter junction of transistor.
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Figure 14
Note : Regulated output voltage might be slightly higher than the expected voltage
due to tolerance of Zener diode.
Circuit Operation :
Case 1 : When input voltage is constant while Load varies.
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Since VZ is fixed, any decrease or increase in VL will have a corresponding effect on
VBE. Suppose, VL decreases, then as seen from the above relation VBE also decreases.
As a result, IB decreases, hence IC (= βIB) decreases, thereby decreasing I and hence
VR (=IR). Consequently, VL increases because at all times
Vin = VR + VL or VL = Vin - VR
on
From the above description it is concluded that when by any reason VL decreases VR
also decreases thereby keeping VL constant.
Similarly, when by any reason VL increases VR also increases thereby keeping VL
constant.
Case 2 : When input voltage varies while Load remains constant.
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When the input voltage increases, output voltage across the transistor increases
momentarily. This momentarily deviation or variation, from the required regulated
output voltage of 6.3volts is a result of a rise in the input voltage. This increases
forward bias of transistor. Recall that the voltage drop across Zener remains constant
at 5.6V. Since the output voltage is composed of the Zener voltage and the baseemitter voltage, the output voltage momentarily increases. At this time, the increase in
the forward bias of transistor lowers the resistance of the transistor allowing more
current to flow through it. Since this current must also pass through R, there is also an
increase in the voltage drop across this resistor. Due to increase in this voltage drop
across R, voltage across VL remains close to the required regulated value of output
voltage.
Similarly, when input voltage decreases, forward bias of transistor also decreases.
This decrease in bias voltage increases the resistance of transistor allowing less
current to flow through it. Since this current must pass through resistor R, there is also
decrease in the voltage drop across this resistor. This drop in voltage across R
maintains output voltage close to the required regulated value.
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Circuit diagram :
Transistor Shunt Voltage Regulator
Figure 15
Procedure :
Make connections as shown in the figure 15.
2.
Connect + 10V supply from DC power supply block to 1 and 2.
3.
4.
5.
Connect voltmeter 1 across terminal 3 and ground to measure input voltage.
Connect voltmeter 2 across terminal 7 and ground to measure output voltage.
Vary potentiometer P2 and set the resistance between point 7 and ground to 400
ohm.
Connect terminal 6 and 7.
Switch ON the supply.
Connect a voltmeter between terminal 7 and ground.
Vary the input voltage with potentiometer P1 in steps between 7V to 10V and
measure the corresponding values of voltmeter 2.
Also measure the zener voltage between terminals 4 and 5 and VBE between the
terminals 5 and ground at every step.
11.
12.
16.
Disconnect terminal 6 and 7.
Set the potentiometer P2 so that the value of resistance between terminal 7 and
ground will be 200 ohm.
Connect terminal 6 and 7.
Adjust input voltage V1 equal to 9V with the potentiometer P1.
Vary the load resistance RL with the potentiometer P2 from its minimum to
maximum value and measure the corresponding values of output voltage in
voltmeter 2.
Measure zener voltage between terminals 4 and 5 and voltage VBE between the
terminals 5 and ground at every step.
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15.
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7.
8.
9.
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Observation Table :
Sr.
No.
Load
Resistance
RL
1.
Full Load (1.1K)
2.
1KΩ
3.
800Ω
4.
600Ω
6.
Forward
bias
voltage
VBE
Output voltage
Vout at constant
Input voltage
Vin = 9 volt
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5.
Voltage
Across
Zener
VZ
400Ω
200Ω
Observations :
on
No Load
7.
In first case when input voltage is varied keeping load resistance constant (400
ohm), regulated output voltage equal to 6.3V is obtained across terminal 7 and
ground, which is equal to sum of zener voltage and voltage VBE of the NPN
transistor.
2.
In second case when load resistance is varied keeping input voltage constant
(9V), regulated voltage same as that of first case is obtained across load resistor
RL.
3.
Output voltage across load is always equal to the sum of the zener voltage and
VBE of the NPN transistor.
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Experiment 6
Objective :
Study of Low Pass Filter
Equipments Needed :
Component
Quantity
1.
Resistors 10K
2
2.
Pot 100K
1
3.
Capacitor 0.01uF
1
4.
IC741
1
Filter :
on
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A network designed to attenuate certain frequency but passes another frequency
without attenuation is called filter. A filter circuit thus posses at least one pass band,
which is a band of frequency in which the output is approximately equal to the input
(attenuation is zero) and an attenuation band in which output is zero (attenuation is
infinite). The frequencies which separate the various pass and attenuation band are
called the cutoff frequencies or the frequency at which output becomes 0.707 of input
is called cutoff frequency. Thus a filter can define as a device that passes electric
signals at certain frequencies or frequency ranges while preventing the passage of
others. A Filter do not ideally transmit all the signal under the pass band with out
attenuation and complete suppress the signal in attenuation (or, stop band) with a
sharp cutoff profile due to absorption, reflection and other losses, this results as loss
of signal power.
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Filter circuits are used in a wide variety of applications. In voice frequency telegraphy
and multi-channel communication, band-pass filters are used in the audio frequency
range (0 KHz to 20 KHz) for modems and speech processing. High-frequency bandpass filters (several hundred MHz) are used for channel selection in telephone central
offices. Data acquisition systems usually require anti-aliasing low-pass filters as well
as low-pass noise filters in their preceding signal conditioning stages. System power
supplies often use band-rejection filters to suppress the 50Hz line frequency and high
frequency transients. In audio amplifier, filters are used to reduce harmonics
distortion and voice rejection. In regulated power supply filters are used to provide
smooth DC output from an AC input, filters are also used to study particular band of
frequencies. Different instruments may be protected using filter circuit.
In addition, there are filters that do not filter any frequencies of a complex input
signal, but just add a linear phase shift to each frequency component, thus
contributing to a constant Time delay. These are called all-pass filters. At high
frequencies (> 1 MHz), all of these filters usually consist of passive components.
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Filters are termed as :
1.
Passive Filters
2.
Active Filters
According to their component characteristics
Passive filters : These are mainly network using inductors (L), resistors (R) and
capacitors (C). They are then called LRC filters. Passive filters consist of impedance
arrangement in series and parallel, two basic arrangements are T and ∏ section most
commonly used. This filter has series impedance Z1 and shunt impedance Z2 T and ∏
filters are 3-pole filter; their frequency response is shown in figure 16.
on
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Figure 16
1.
Depending upon the relation between the arm impedance i.e. series arm
impedance Z1 and shunt arm impedance Z2 :
a.
Constant K-derived Filter or Prototype Filter.
b.
M-derived filter
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The classification theory employed on passive filter was based on image parameter
theory which in turn based on the filter characteristics and performance. Passive
Filter may be classified according to the following categories :
Identifying their frequency characteristics, the filter differentiated as:
a.
Low Pass Filter (LPF)
b.
High Pass Filter (HPF)
c.
Band Pass Filter (BPF)
d.
Band Stop Filter (BSF)
e.
All Pass Filter (APF)
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Active filters : are circuits that use an operational amplifier (op-amp) as the active
device in combination with some resistors and capacitors to provide an LRC-like filter
performance at low frequencies.There are two principal reasons for the use of active
filters. The first is that the amplifier powering the filter can be used to shape the
filter's response, e.g., how quickly and how steeply it moves from its passband into its
stopband. (To do this passively, one must use inductors, which tend to pick up
surrounding electromagnetic signals and are often quite physically large.) The second
is that the amplifier powering the filter can be used to buffer the filter from the
electronic components it drives. This is often necessary so that they do not affect the
filter's actions.
However, the active filter requires high grade technology for selected component and
achieves the desired characteristics and control. One more drawback of active filter is
that the selectivity and cutoff frequency become a function of gain, and at very low
frequencies, the stability of active filter is inferior to that of passive component.
Active filters consist of the three main filter optimizations
Butterworth,
ii.
Tschebyscheff and
iii.
Bessel,
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i.
followed by five sections describing the most common active filter applications :
Low Pass Filter (LPF)
c.
High Pass Filter (HPF)
d.
Band Pass Filter (BPF)
e.
Band Stop Filter (BSF)
f.
All Pass Filter (APF)
on
b.
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The gain and phase response of a low-pass filter can be optimized to satisfy one of the
following three criteria :
Maximum passband flatness
2.
An immediate passband-to-stopband transition
3.
A linear phase response.
4.
The Butterworth coefficients, optimizing the passband for maximum flatness.
5.
The Tschebyscheff coefficients, sharpening the transition from passband into the
stopband.
6.
The Bessel coefficients, liberalizing the phase response up to fC(cutoff
frequency)
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Comparison of Gain Responses of Fourth-Order Low-Pass Filters
Figure 17
Low Pass Filter :
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This filter passes low frequency but attenuates (or reduces) frequencies higher than
the cut-off frequecy. The actual amount of attenuation for each frequency varies from
filter to filter. It is sometimes called as high-cut filter, or treble cut filter when used in
audio applications. An ideal Low-Pass Filter completely eliminates all frequencies
above the cut-off frequecy while passing those below unchanged. The transition
region present in practical filters does not exist.
Idea Frequency Response of Low Pass Filter
Figure 18
However, this filter is not realizable for practical, real signals because the sinc
function extends to infinity. Hence there will be some tranisiton time in low pass
filter.
One simple electrical circuit that will serve as a low-pass filter consists of a resistor
in series with a load, and a capacitor in parallel with the load. The capacitor exhibits
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reactance, and blocks low-frequency signals, causing them to go through the load
instead.
RC combination for Low Pass Filter
Figure 19
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At higher frequencies the reactance drops, and the capacitor effectively functions as a
short circuit. The combination of resistance and capacitance gives you the time
constant of the filter τ = RC (represented by the Greek letter tau). The break
frequency, also called the turnover frequency or cutoff frequency (in hertz), is
determined by the time constant: The Low cutoff frequency of this configuration is
1 1
ωc = =
t RC
fc =
on
1
1
=
2π t 2π RC ……………………(1)
A First order Low Pass Filter :
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Figure 20
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Vin =Input signal Voltage
Vout = Output signal Voltage
AF = 1 + RF / R1 = pass band gain of filter =2
f = frequency of input signal
fH = 1/2πRC = high cut off frequency, 3- dB frequency, corner frequency Operation
of low pass filter using equation
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on
The ideal Low Pass Filter has a constant gain AF from 0 to high cut off frequency (fH)
at fH the gain is 0.707 * Af. And after fH it decreases at a constant rate with an increase
in frequency i.e. when input frequency is increased tenfold (one decade), the voltage
gain is divided by 10.
Gain (dB) = 20 log | Vout / Vin |
i.e. Gain Roll off rate is −20dB / decade.
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Output amplitude vs frequency
Figure 21
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Circuit diagram :
Figure 22
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Procedure :
Low Pass Filter
Make connections as shown in the figure 22.
2.
Connect + 12V to pin no 7 and -12V to pin no 4 of IC741. See IC pin diagram
shown in figure 22.
3.
Set the potentiometer at 15.9K.
4.
Connect a sine wave of amplitude 1Vpp, 100Hz from Sin/Square/TTL
Generator block to the Vin input of low pass filter as shown in the figure.
5.
Switch ON the instrument.
6.
Observe the Vout output on the oscilloscope. A sine wave of 2Vpp of
corresponding frequency is observed on oscilloscope, since the gain of low pass
filter is 2.
7.
Vary the frequency of input signal and observe Vout on oscilloscope.
8.
Note the output voltage at different frequencies and draw the graph.
9.
Switch Off the instrument.
10.
Assume any frequencies you want, to be the cutoff frequency of the filter.
11.
Calculate the value of R for that frequency.
12.
Set the pot resistance at calculated value by rotating the pot shaft.
13.
Repeat the above steps from 4 to 9.
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Note :
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1.
1.
Chose a frequency for which the value of R will be within the range of Pot
resistance you are using.
2.
TL741 have low slew rate thus after 250 KHz it starts giving faulty or
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unpredictable results. Hence to avoid confusion do not use the frequency above
200 KHz.
Observation Table :
S. No.
Input
frequency
(Hz)
100
2
200
3
500
4
1K
5
5K
6
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1
7
15K
8
20K
9
25K
10
30K
11
35K
12
40K
13
45K
14
50K
Vout
Gain =
(Vout / Vin)
dB Gain =
20 x log (Gain)
10K
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Calculations :
1. Cut-off frequency fH = 1/2πRC =
2. Value of R
=
3. Pass band gain of Low pass filter AF = 1 + RF / R1 = 2
4. Output Voltage Vout = AF x VIN = 2 x VIN
5. Gain at 3 dB frequency fH = 0.707 * AF ;Vout = 0.707 x 2 x VIN
6. Roll off rate = −20dB/decade
Observation :
At high cutoff frequency of 1 KHz output voltage (Vout) of Low Pass Filter reduces to
0.707 times of mid band value when R =15.9K.
Conclusion :
The frequency response plot of the output amplitude is same as shown in figure
21.
2.
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1.
A very small difference between calculated and measured cut-off frequency.
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Experiment 7
Objective :
Study of High Pass Filter
Equipments Needed :
Component
Quantity
1.
Resistors 10K
2
2.
Pot 100K
1
3.
Capacitor 0.01µF
1
4.
IC741
1
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High Pass Filter : It is a filter that passes high frequencies well, but attenuates (or
reduces) frequencies lower than the cutoff frequency. The actual amount of
attenuation for each frequency varies from filter to filter. It is sometimes called a lowcut filter; the terms bass-cut filter or rumble filter are also used in audio applications.
A high-pass filter is the opposite of a low-pass filter, and a bandpass filter is a
combination of a high-pass and a low-pass. It is useful as a filter to block any
unwanted low frequency components of a complex signal while passing the higher
frequencies. Of course, the meanings of 'low' and 'high' frequencies are relative to the
cutoff frequency chosen by the filter designer.
Idea Frequency Response of High Pass Filter
Figure 23
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The simplest electronic high-pass filter consists of a capacitor in series with the signal
path in conjunction with a resistor in parallel with the signal path. The resistance
times the capacitance (R×C) is the time constant (τ); it is inversely proportional to the
cutoff frequency, at which the output power is half the input (−3dB):
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RC combination for High Pass Filter
Figure 24
It is a frequency selective circuit, which passes signals of frequencies above its low
cut off frequency (fL) and attenuates signals of frequencies below fL.
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High Pass Filter
Vin = Input signal Voltage
Vout = Output signal Voltage
Vout
− Gain of filter as a function of frequency
Vin
AF = 1 + RF / R1 = pass band gain of filter
f = frequency of input signal
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Equation of High pass filter is
Figure 25
fL = 1/2 π RC = Low cut off frequency, –3dB frequency, corner frequency
Operation of high pass filters using equation.
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In ideal high pass filter, when f < fL gain is increased at a constant rate has a constant
rate with an increase in frequency. At fL the gain is 0.707*AF. And above fL it has
constant gain of AF. Below fL when input frequency is increased tenfold (one decade),
the voltage gain is multiplied by 10.
Gain (dB) = 20 log | Vout / Vin |
i.e. Gain Roll off rate is −20dB / decade.
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Real frequency response of High Pass Filter
Figure 26
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Such a filter can be used to direct high frequencies to a tweeter speaker while
blocking bass signals which can interfere with or damage the speaker. A low-pass
filter, using a coil instead of a capacitor, can simultaneously be used to direct low
frequencies to the woofer. High-pass and low-pass filters are also used in digital
image processing to perform transformations in the frequency domain. Most highpass filters have zero gain (-inf dB) at DC. Such a high-pass filter with very low
cutoff frequency can be used to block DC from a signal that is undesired in that signal
(and pass nearly everything else). These are sometimes called DC blocking filters.
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Circuit diagram :
High Pass Filter
Figure 27
Procedure :
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Make connections as shown in the figure 27.
2.
Connect +12V to pin no 7 and -12V to pin no 4 of IC741. See IC pin diagram
shown in figure 27.
3.
Set the potentiometer at 15.9K.
4.
Connect a sine wave of amplitude 1Vpp, 10Hz from Sin/Square/TTL Generator
to the Vin input of high pass filter as shown in the figure.
5.
Switch ON the instrument.
6.
Observe the Vout output on the oscilloscope. A sine wave of 2Vpp of
corresponding frequency is observed on oscilloscope, since the gain of high pass
filter is 2.
7.
Vary the frequency of input signal and observe Vout on oscilloscope.
8.
Note the output voltage at different frequency and draw the graph.
9.
Switch Off the instrument.
10.
Assume any frequency you want to be the cutoff frequency of the filter.
11.
Calculate the value of R for that frequency.
12.
Set the pot resistance at calculated value by rotating the pot shaft.
13.
Repeat the above steps from 4 to 9.
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Note :
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1.
1.
Chose a frequency for which the value of R will be within the range of Pot
resistance you are using.
2.
TL741 have low slew rate thus after 250 KHz it starts giving faulty results.
Hence to avoid confusion do not use the frequency above 200 KHz.
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Observation Table :
S. No.
Input
frequency
(Hz)
1
100
2
200
3
500
4
1K
5
5K
7
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8
20K
9
25K
10
30K
11
35K
12
40K
13
45K
14
50K
6
Vout
Gain =
(Vout / Vin)
dB Gain =
20 x log (Gain)
10K
15K
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Calculations :
1.
Cut-off frequency fL = 1/2πRC =
2.
Value of R
3.
Pass band gain of High pass filter AF = 1 + RF / R1 = 2
4.
Output Voltage Vout = AF x VIN = 2 x VIN
5.
Gain at 3 dB frequency fH = 0.707 * AF ; Vout = 0.707 x 2 x VIN
6.
Roll off rate = −20 dB /decade
=
Observation :
At Low cutoff frequency of 1 KHz output voltage (Vout) of low pass filter reduces to
0.707 times of mid band value when R =15.9K
Conclusion :
The frequency response plot of the output amplitude is same as shown in figure
26.
2.
A very small difference between calculated and measured cut-off frequency
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Experiment 8
Objective :
Study of Band Pass Filter
Equipments Needed :
Component
Quantity
1.
Resistors 10K
4
2.
Pot 100K
2
3.
Capacitor 0.0lµF
1
4.
Capacitor 0.047µF
1
5.
IC741
2
Band Pass Filter :
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Band pass filter are designed mathematically to respond to design frequencies while
rejecting all other out of band frequencies. A band pass filter can be designed to filter
a particular band, or spread, or frequencies from a wider range of mixed signals by
combining the properties of low pass and high pass filter. The series combination of
these two filter only allow passage of those frequency which are neither too high nor
too low.
Idea Frequency Response of Band Pass Filter
Figure 28
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An ideal filter will have a completely flat pass-band (with no gain and attenuation
through out) and would completely attenuate all frequency outside pass-band. In
practice, no band-pass filter is ideal. The filter doesn’t attenuate all frequencies
outside the desired frequency range completely; in particular there is region just
outside the intended pass-band where frequencies are attenuated, but not rejected.
This is known as the filter roll-off, and is usually expressed in dB of attenuation per
decade of frequency.
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Second order Band Pass Filter frequency response
Figure 29
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Generally the design of a filter seeks to make the roll-off as narrow as possible,
however as the roll-off is made narrower, the pass band is no longer flat; it begins to
ripple. This effect is particularly pronounced at the edge of the pass-band, an effect
known as Gibbs phenomenon. Between the lower cut-off and fL higher cut-off fH of a
frequency band is the resonant frequency, at which the gain of the filter is maximum.
The bandwidth of the filter is simply the difference between fL and fH. A Wide Bandpass filter is formed by cascading a High pass filter and Low pass filter.
If the High-Pass Filter and Low-Pass Filter are of the first order then the Band-Pass
Filter will have a roll off rate of -20 dB /decade.
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First order Band Pass Filter
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Figure 30
If the High-pass filter and Low-pass filter are of the first order then the Band-pass
filter will have a roll off rate of -20 dB/decade.
A01
= Pass band gain of High pass section
= 1 + RF / R
fL
= Low cut off frequency
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……………. (1)
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= 1/2 π R1C1
A02
……………. (2)
= Pass band gain of Low pass section
= 1 + RF / R
fH
…………. (3)
= High cutoff frequency
= 1/2 π R2C2
…………. (4)
The voltage gain magnitude of wide band pass filter is the product of gains of low
pass sections (ALP) and high pass section (AHP)
Where the
Total Band pass gain A0 = A01 x A02
…………. (5)
What if we take the value of resistance and capacitance same for both of the high pass
and low pass circuit? Will they show no output? No, when we take value of resistance
and capacitance equal for RC combination of both low and high pass filter the, then
the ratio of higher and lower cut-off frequency becomes four.
i.e.
fH = 4.fL
…………. (6)
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Bandwidth of a Filter :
Bandwidth is defined as the band of frequency over which the amplifier gain is
constant.
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Figure 31
Bandwidth (B) = f2 – f1
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The f1 and f2 points are also known as Half Power Points. The half power points are
the points at which the signal amplitude has dropped to .707 percent of the maximum
signal amplitude. Any frequency below the f1 or above the f2 point is not considered
a usable output from the amplifier. The bandwidth of the amplifier is the difference
between the f1 and f2 points.
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Circuit diagram :
Figure 32
7.
10.
11.
13.
14.
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12.
Observe the Vout output on the oscilloscope. Nothing will appear at the output on
oscilloscope.
Increase the frequency of input signal and you will start seeing the output.
Increase the frequency and note the output amplitude with the increment in the
frequency
Voltage gain for First order Low pass and high pass filter will be 2 so the output
will be equal to; Vout = 0.707 x 2 x 2 x VIN;.
Note the first frequency for which there is 3 dB gain, this frequency is known as
Lower cut off frequency, fL; or the frequency at which, output voltage Vout =
2.828 x VIN.
Increase the frequency and you will see that after some time the output
amplitude become constant for a particular range of frequency
As you further increase the frequency the output amplitude start decreasing
hence note the frequency for which 3 dB gain appears second time; known as
upper cut-off frequency, fH; or the frequency at which, output voltage Vout =
0.707× 2×Vin.
Plot the frequency response plot of output.
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8.
9.
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Procedure :
1. Make connections as shown in the figure 32.
2. Connect + 12V to pin no 7 and -12V to pin no 4 of IC741. See IC pin diagram
shown in figure 32.
3. Set the potentiometer P1 at 6.7K.
4. Set the potentiometer P2 at 3.184K.
5. Connect a sine wave of amplitude 1Vpp, 10Hz from Sin/Square/TTL Generator
to the Vin input of band pass filter as shown in the figure.
6. Switch ON the instrument.
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15.
Determine the difference between measured and calculated lower and higher
cut-off frequencies.
16.
Calculate the value of resistance for any cut-off frequency between 1 KHz to 10
KHz by using given capacitance value.
17.
Repeat the above step form 3 to15 for new cut-off frequencies.
18.
Perform the same procedure at different Cutoff frequencies shown below.
19.
Value of upper & lower cutoff for different values of resistance P2 & P1
respectively.
Capacitance
C1(uF)
fL
(Hz)
Resistance
P2 (Ω)
Capacitance
C2 (uF)
fH
(Hz)
17K
0.047
200
800
0.01
20K
6.7K
0.047
500
3184
0.01
5K
0.047
1K
1.59K
0.01
10K
3.38K
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Calculations :
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Resistance
P1(Ω)
Higher cut-off frequency fH = 1/2π R1C1
2.
Lower cut-off frequency fL = 1/ 2 πR2C2
3.
If , R1C1 = R2C2 = RC then fH = 4.fL
4.
Value of R1 =
5.
Value of R2 =
6.
Pass band gain of Low pass filter AFL = 1 + RF / R1 = 2
7.
Pass band gain of High pass filter AFH = 1 + RF / R1 = 2
8.
Total gain AF = AFL x AFH = 4
9.
Gain at 3 dB frequency fH = 0.707 x AF ;Vout = 0.707 x 2 x VIN
10.
Roll off rate = −20 dB /decade
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Observation table :
S. No.
Input
frequency
(Hz)
100Hz
2
200Hz
3
500Hz
4
1KHz
5
5KHz
6
10KHz
7
15KHz
8
20KHz
9
10
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1
Vout
25KHz
30K
35KHz
12
40KHz
13
45KHz
14
50KHz
15
100KHz
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Observation Graph :
Output Amplitude vs Frequency
Figure 33
Observations :
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At low cutoff frequency of 500Hz and high cutoff frequency of 5 KHz, the output
voltage of band pass filter decreases to 0.707 times of mid band value.
Conclusion :
Lower cutoff frequency = ............................
2.
Higher cutoff frequency = ...............................
3.
3 dB Bandwidth = ............................................
4.
The frequency response plot of the output amplitude is same as shown in figure
33.
5.
A very small difference between calculated and measured frequencies.
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Experiment 9
Objective :
Study of Active Notch Filter
Equipments Needed :
Component
Quantity
1.
Resistors 16K
2
2.
Resistor 8K
1
3.
Capacitor 0.0lµF
4
4.
IC741
1
.
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Notch filter : A passive notch filter using only resistors and capacitors is shown in
figure 34. It is actually a combination of two filters in parallel, the upper one
comprising two resistors and capacitor, is the low pass filter and the lower one
comprising two capacitors and a resistor, and is high pass filter. The stop bands of
both the filter are overlapping. This makes it useful to reject a narrow band of
frequency. The reason it is called “twin-T” should be obvious.
Twin T
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Figure 34
The notch frequency occurs where the capacitive reactance equals the resistance (Xc
= R) and if the values are close, the attenuation can be very high and the notch
frequency virtually eliminated.
1
2πRC
…………. (1)
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The frequency of minimum gain (Notch frequency) is f0 =
The largest problem with this filter is that the input resistance is low at high
frequencies, being approximately R/4. Also the insertion loss of the filter will depend
on the load that is connected to the output, so the resistors should be of much lower
value than the load for minimal loss. Also the passive twin-T network has a relatively
low figure of merit Q. To overcome all these short comings Op-Amp is used in the
circuit as voltage follower as shown in figure 35.
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Circuit diagram :
Figure 36
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Figure 35
The junction of R/2 and 2C, which is normally connected to ground, is bootstrapped
to the output of the follower. Because the output of the follower is very low
impedance, neither the depth nor the frequency of the notch change; however, the Q is
raised in proportion to the amount of signal fed back to R/2 and 2C. The frequency
response of the Notch filter if as shown in figure 36.
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Active Notch Filter
Figure 37
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Procedure :
To observe the working of a Notch filter
1.
Calculate the notch frequency for Notch Filter by using the given value of
resistance and capacitance in Eq 1.
2.
Make the passive filter as shown in figure 37.
3.
To make a 2C configuration join two 0.01µf capacitor in parallel
4.
Connect the IC741 pin no. 4 to negative supply (-12V). and pin no. 7 to positive
supply (+12V)
5.
Connect pin no.3 of Op amp to output of passive filter
6.
Connect pin no. 2 & pin no.6 of Op amp.
7.
Connect the Oscilloscope CH I at output pin no.6 and ground ‘GND’.
8.
Now connect the input signal by function generator at the input terminal of
filter.
9.
Keep the function generator frequency at 10Hz, 1VPP
10.
Increase the frequency and note the output amplitude with the increment in the
frequency.
11.
Voltage gain for second order band pass filter will be 1 one so the output will be
equal to Vout = Vin.
12.
Note the frequency at which the output voltage is zero or negligible.
13.
Plot the frequency response plot of output.
14.
Determine the difference between measured and calculated Notch frequency.
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Observation table :
S. No.
Input frequency (Hz)
100Hz
2
200Hz
3
500Hz
4
1KHz (fL)
5
5KHz
6
10KHz
7
15KHz
8
9
11
25KHz
30KHz
35KHz
40KHz
13
45KHz
14
50KHz
Calculations :
Notch frequency fN = 1/2π RC
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1
Vout
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Output amplitude vs frequency
Figure 38
Conclusion :
The frequency response plot of the output amplitude is same as shown in figure
38.
2.
A very small difference between calculated and measured frequencies.
3.
At the Notch frequency the output voltage is zero or very low in milli volts.
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Experiment 10
Objective :
Study of Common Emitter Characteristics of NPN transistor
i.
Input Characteristics
ii.
Output Characteristics
iii.
Constant current transfer Characteristics
Equipments Needed :
Component
1.
Quantity
Resistance
5K
1
100 ohm
1
2.
Potentiometers 1K
2
3.
Transistor NPN BC548
1
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Transistor characteristics are the curves, which represent relationship between
different DC currents and voltages of a transistor. These are helpful in studying the
operation of a transistor when connected in a circuit. The three important
characteristics of a transistor are:
on
1.
Input characteristic.
2.
Output characteristic.
3.
Constant current transfer characteristic.
Input Characteristic :
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In common emitter configuration, it is the curve plotted between the input current (IB)
verses input voltage (VBE) for various constant values of output voltage (VCE).
The approximated plot for input characteristic is shown in figure 39. This
characteristic reveal that for fixed value of output voltage VCE, as the base to emitter
voltage increases, the emitter current increases in a manner that closely resembles the
diode characteristics.
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Input Characteristics
Figure 39
Output Characteristic :
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This is the curve plotted between the output current IC versus output voltage VCE for
various constant values of input current IB.
The output characteristic has three basic region of interest as indicated in figure 40 the
active region, cutoff region and saturation region.
on
In active region the collector base junction is reverse biased while the base emitter
junction if forward biased. This region is normally employed for linear (undistorted)
amplifier.
In cutoff region the collector base junction and base emitter junction of the transistor
both are reverse biased. In this region transistor acts as an ‘Off’ switch.
In saturation region the collector base junction and base emitter junction of the
transistor both are forward biased. In this region transistor acts as an ‘On’ switch.
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Output Characteristics
Figure 40
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Constant Current Transfer Characteristics :
This is the curve plotted between output collector current IC versus input base current
IB for constant value of output voltage VCE.
The approximated plot for this characteristic is shown in figure 41.
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Transfer Characteristics
Figure 41
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Circuit diagram :
Common Emitter Configuration
Figure 42
Procedure :
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To plot input characteristics proceed as follows :
1.
Make connections as shown in the figure 42.
2.
Connect +5V DC from DC power supply to terminals 1 and 2.
3.
Connect + 10V DC from DC power supply to terminals 3, 4.
4.
Switch ON the instrument.
5.
Set both potentiometers such that VCE and VBE equals to 0V.
6.
Vary potentiometer P2 and set a value of output voltage VCE at some constant
value (1V, 3V)
7.
Vary the potentiometer P1 so as to increase the value of input voltage VBE from
zero to 0.9V in step and measure the corresponding values of input current IB for
different constant value of output voltage VCE in an observation Table 1.
8.
Rotate potentiometer P1 fully in CCW direction.
9.
Repeat the procedure from step 6 for different sets of output voltage VCE.
10.
Plot a curve between input voltage VBE and input current IB as shown in
figure 39 using suitable scale with the help of observation Table l. This curve is
the required Input Characteristic.
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Observation Table 1 :
S. No.
Input
voltage
VBE
0.0V
2.
0.1V
3.
0.2V
4.
0.3V
5.
VCE = 1V
VCE = 3V
VCE =5V
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1.
Input current IB(µA) at constant value of
output voltage
0.4V
7.
0.6V
8.
0.7V
9.
0.8V
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To plot output characteristics proceed as follows :
1.
Switch OFF the instrument.
2.
Rotate both the potentiometer P1 and P2 fully in CCW (counter clockwise
direction).
3.
Connect voltmeter between terminal 6 and ground to measure output voltage
VCE.
4.
Connect one Ammeter between terminal 2 and 3 to measure input current
IB(µA) and other Ammeter between terminal4 and 5 to measure output current
IC(mA).
5.
Switch ON the instrument.
6.
Vary potentiometer P1 and set a value of input current IB at some constant value
(0µA, 10µA …..100µA)
7.
Vary the potentiometer P2 so as to increase the value of output voltage VCE from
zero to maximum value in step and measure the corresponding values of output
current IC for different constant value of input current IB in an observation
table2.
8.
Rotate potentiometer P2 fully in CCW direction.
9.
Repeat the procedure from step 6 for different sets of input current IB.
10.
Plot a curve between output voltage VCE and output current IC as shown in
figure 40 using suitable scale with the help of observation table2. This curve is
the required output characteristic.
Results :
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Output resistance Rout= _________
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Observation Table 2 :
S. No.
Output
voltage
VCE
Output current IC (mA) at constant value of
input current
IB = 0µA
0.0V
2.
0.5V
3.
1.0V
4.
2.0V
5.
3.0V
6.
4.0V
7.
5.0V
8.
6.0V
9.
7.0V
10.
8.0V
IB =20µA
IB =30µA
IB(µA)
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1.
IB =10µA
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To plot constant current transfer characteristics proceed as follows :
1.
Switch Off the instrument.
2.
Rotate both the potentiometer P1 and P2 fully in CCW (counter clockwise
direction).
3.
Connect voltmeter between terminal 6 and ground to measure output voltage
VCE.
4.
Connect one Ammeter between terminal 2 and 3 to measure input current IB
(µA) and other Ammeter between terminal 4 and 5 to measure output current IC
(mA).
5.
Switch ON the instrument.
6.
Vary potentiometer P2 and set a value of output voltage VCE at maximum value.
7.
Vary the potentiometer P1 so as to increase the value of input current IB from
zero to 10mA in step and measure the corresponding values of output current IC
in an observation Table 3.
8.
Plot a curve between output current IC and input current IB as shown in figure 41
using suitable scale with the help of observation Table 3. This curve is the
required Transfer Characteristic.
Results :
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Current Gain βac = ___________
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Observation Table 3 :
1.
00.0µA
2.
10.0µA
3.
20.0µA
4.
30.0µA
5.
40.0µA
50.0µA
60.0µA
8.
70.0µA
9.
80.0µA
10.
90.0µA
11.
100.0µA
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6.
Output current IC (mA) at
constant output voltage
VCE = max
-c
S. No.
Input
current
IB (µA)
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Calculations :
1.
Input resistance : It is the ratio of change in the input voltage VBE to change in
the input current IB at constant value of output voltage VCE or it is the reciprocal
of the slope obtained from the input characteristic.
Mathematically :
Rin =
ΔVBE
1
1
=
=
Slope from Input characteristic ΔIB / ΔVBE ΔIB at constant VCE
To calculate input resistance determine the slope from the input characteristic
curve obtained from observation Table 1. Reciprocal of this slope will give the
required input resistance.
2.
Output resistance : It is the ratio of change in the output voltage VCE to change
in the output current IC at constant value of input current IB or it is the reciprocal
of the slope obtained from the output characteristic.
Mathematically :
1
1
ΔVCE
=
=
Slope from Input characteristic ΔIC/ΔVCE ΔIC at constant IB
-c
RIn =
3.
on
To calculate output resistance determine the slope from the output characteristic
curve obtained from observation Table 2. Reciprocal of this slope will give the
required output resistance.
Current gain : It is the ratio of change in the output current IC to change in the
input current IB at constant value of output voltage VCE or it is the slope
obtained from the constant current transfer characteristic. It is denoted by βac.
Mathematically :
∆IC
su
βac = Slope of constant current transfer characteristic =
∆IB
To calculate current gain, determine the slope from the constant current transfer
characteristic curve obtained from observation Table 3. This slope is the
required current gain.
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Experiment 11
Objective :
Study of Common Base Characteristics of NPN transistor
i.
Input Characteristics
ii.
Output Characteristics
iii.
Constant current transfer Characteristics
Equipments Needed :
Component
Quantity
1.
Resistance 51 ohm 1W
2
2.
Potentiometers 1K
2
3.
Transistor NPN BC548
1
-c
As we already know that Transistor characteristics are the curves, which represent
relationship between different DC currents and voltages of a transistor. Previously we
have seen the input and output behavior when emitter was common, but what happen
when instead of emitter any other terminal i.e. base or collector is used as common.
Will the input output and current transfer characteristic be the same? or there will be
some change in it?
These are helpful in studying the operation of a transistor when connected in a circuit.
The three important characteristics of a transistor are:
on
1.
Input characteristic.
2.
Output characteristic.
3.
Constant current transfer characteristic.
Input Characteristic :
su
In common base configuration, it is the curve plotted between the input current (IE)
verses input voltage (VBE) for various constant values of output voltage (VCB).
The approximated plot for input characteristic is shown in figure 43. This
characteristic reveal that for fixed value of output voltage VCB, as the base to emitter
voltage increases, the emitter current increases in a manner that closely resembles the
diode characteristics.
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Input Characteristics
Output Characteristic
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Figure 43
Output Characteristic :
This is the curve plotted between the output current IC versus output voltage VCB for
various constant values of input current IE.
The output characteristic has three basic region of interest as indicated in figure 44 the
active region, cutoff region and saturation region.
In active region the collector base junction is reverse biased while the base emitter
junction if forward biased. This region is normally employed for linear (undistorted)
amplifier.
In cutoff region the collector base junction and base emitter junction of the transistor
both are reverse biased. In this region transistor acts as an OFF switch.
In saturation region the collector base junction and base emitter junction of the
transistor both are forward biased. In this region transistor acts as an ON switch.
Figure 44
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Constant current transfer Characteristic :
This is the curve plotted between output collector current IC versus input emitter
current IE for constant value of output voltage VCB.
The approximated plot for this characteristic is shown in figure 45.
-c
Transfer Characteristics
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Figure 45
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Circuit diagram :
Common Base Configuration
Figure 46
Procedure :
To plot output characteristics proceed as follows :
1.
Make connections as shown in the figure 46.
2.
Connect -5V DC from DC power supply to terminals 1, 2.
3.
Connect + 10V DC from DC power supply block to terminals 3, 4.
4.
Switch ON the instrument.
5.
Set both potentiometers such that VCB and VBE equal to 0V.
6.
Vary potentiometer P2 and set a value of output voltage VCB at some constant
value (1V, 2V…).
7.
Vary the potentiometer P1 so as to increase the value of input voltage VBE from
zero to 0.9V in step and measure the corresponding values of input current IE for
different constant values of output voltage VCB in an observation Table 1.
8.
Rotate potentiometer P1 fully in CCW direction.
9.
Repeat the procedure from step 6 for different sets of output voltage VCB.
10.
Plot a curve between input voltage; VBE and input current; IE as shown in figure
43 using suitable scale with the help of observation Table l. This curve is the
required input characteristic.
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Observation Table 1 : Input characteristics
S. No.
Input
voltage
VBE
1.
0.0V
2.
0.1V
4.
VCB = 1V
VCB = 3V
VCB =5V
-c
3.
Input current IE(mA) at constant value of
output voltage
0.2V
0.3V
0.5V
7.
0.6V
8.
0.7V
9.
0.8V
10.
0.9V
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0.4V
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5.
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To plot output characteristics proceed as follows :
1.
Switch OFF the instrument.
2.
Rotate both the potentiometer P1 and P2 fully in CCW (counterclockwise
direction).
3.
Connect voltmeter between terminal 6 and ground to measure output voltage
VCB.
4.
Connect one Ammeter between terminal 2 and 3 to measure input current
IE(mA) and other Ammeter between terminal 4 and 5 to measure output current
IC(mA).
5.
Switch ON the instrument.
6.
Vary potentiometer P1 and set a value of input current IE at some constant value
(0mA, 1mA).
7.
Vary the potentiometer P2 so as to increase the value of output voltage VCB from
-1V to maximum value in step and measure the corresponding values of output
current IC for different constant values of input current IE in an observation
Table2.
8.
Rotate potentiometer P2 fully in CCW direction.
9.
Repeat the procedure from step 6 for different sets of input current IE.
10.
Plot a curve between output voltage; VCB and output current IC as shown in
figure 44 using suitable scale with the help of observation Table 2. This curve is
the required output characteristic.
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Observation Table 2 :
S. No.
Input
voltage
VCB
Input current IC (mA) at constant value of
input voltage
IE = 0mA IE = 1mA
1.
-1.0V
2.
0.0V
3.
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4.
IE = 2mA
IE = 3mA
IE = 4mA
0.5V
1.0V
3.0V
7.
4.0V
8.
5.0V
9.
6.0V
10.
7.0V
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2.0V
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5.
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To plot constant current transfer characteristics proceed as follows :
1.
Switch OFF the instrument.
2.
Rotate both the potentiometer P1 and P2 fully in CCW (counter clockwise
direction).
3.
Connect voltmeter between terminal 6 and ground to measure output voltage
VCB.
4.
Connect one Ammeter between terminal 2 and 3 to measure input current IE
(mA) and other Ammeter between terminal 4 and 5 to measure output current IC
(mA).
5.
Switch ON the instrument.
6.
Vary potentiometer P2 and set a value of output voltage VCB at maximum value.
7.
Vary the potentiometer P1 so as to increase the value of input current IE from
zero to 10mA in step and measure the corresponding values of output current IC
in an observation Table 3.
8.
Plot a curve between output current IC and input current IE as shown in figure 45
using suitable scale with the help of observation Table 3. This curve is the
required Transfer characteristic.
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Observation Table 3 :
S. No.
Input current Output current IC (mA) at constant output
IE(mA)
voltage VCB = 10V
1.
0.0mA
2.
1.0mA
3.
2.0mA
6.
7.
3.0mA
4.0mA
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4.
5.0mA
6.0mA
9.
8.0mA
10.
9.0mA
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Calculations :
1.
Input resistance : It is the ratio of change in the input voltage VBE to change in
the input current IE at constant value of output voltage VCB or it is the reciprocal
of the slope obtained from the input characteristic.
Mathematically :
RIn =
1
1
ΔVBE
=
=
Slope from Input characteristic ΔIE/ΔVBE ΔIE at const VCB
To calculate input resistance determine the slope from the input characteristic
curve obtained from observation Table 1. Reciprocal of this slope will give the
required input resistance.
2.
Output resistance : It is the ratio of change in the output voltage VCB to change
in the output current IC at constant value of input current IE or it is the reciprocal
of the slope obtained from the output characteristic.
Mathematically :
1
1
ΔVCB
=
=
Slope from Input characteristic ΔIC/ΔVCB ΔIC at constant IE
-c
Rout =
3.
on
To calculate output resistance determine the slope from the output characteristic
curve obtained from observation Table 2. Reciprocal of this slope will give the
required output resistance.
Current gain : It is the ratio of change in the output current IC to change in the
input current IE at constant value of output voltage VCB or it is the slope
obtained from the constant current transfer characteristic. It is denoted by αac
su
Mathematically :
αac = Slope of constant current transfer characteristic =
ΔIc
ΔIE
Results :
Input resistance Rin = ___________
Output resistance Rout ________ =
Current Gain αac = ___________
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To calculate current gain, determine the slope from the constant current transfer
characteristic curve obtained from observation Table 3. This slope is the
required current gain.
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Experiment 12
Objective :
Study of Common Collector Characteristics of NPN transistor
i.
Input Characteristics
ii.
Output Characteristics
iii.
Constant current transfer Characteristics
Equipments Needed :
Component
Quantity
1.
Resistance 51 ohm 1W
2
2.
Potentiometers 1K
2
3.
Transistor NPN BC548
1
-c
We have seen what happen when an Emitter or a base terminal become common but
what happen when we connect transistor in common collector configuration? What
will be transistor’s characteristics in that configuration? Transistor characteristics are
the curves, which represent relationship between different DC currents and voltages
of a transistor. These are helpful in studying the operation of a transistor when
connected in a circuit. The three important characteristics of a transistor are
Input characteristic.
2.
Output characteristic.
3.
Constant current transfer characteristic.
Input Characteristic :
on
1.
In common emitter configuration, it is the curve plotted between the input current (IB)
verses input voltage (VCB) for various constant values of output voltage (VCE).
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This characteristic reveals that for fixed value of output voltage VCE, It is quite
different from CB and CE configuration. This difference is due to the fact that input
voltage VCB is largely determined by the value of VCE. As the collector to base voltage
increases, VBE is reduced thereby reducing IB. The approximated plot for input
characteristic is shown in figure 47.
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Input Characteristics
Figure 47
Output Characteristic :
This is the curve plotted between the output current IE versus output voltage VCE for
various constant values of input current IB.
-c
The output characteristic has three basic region of interest as indicated in figure 48 the
active region, cutoff region and saturation region.
on
In active region the collector base junction is reverse biased while the base emitter
junction if forward biased. This region is normally employed for linear (undistorted)
amplifier.
In cutoff region the collector base junction and base emitter junction of the transistor
both are reverse biased. In this region transistor acts as an ‘Off’
In saturation region the collector base junction and base emitter junction of the
transistor both are forward biased. In this region transistor acts as an ‘On’ switch.
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Output Characteristics
Figure 48
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Constant current transfer Characteristic :
This is the curve plotted between output emitter current IE versus input base current IB
for constant value of output voltage VCE.
The approximated plot for this characteristic is shown in figure 49.
-c
on
Transfer Characteristics
Figure 49
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Circuit diagram :
on
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Common Collector Configuration
Figure 50
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Procedure :
To plot Input Characteristics proceed as follows :
1.
Make connections as shown in the figure 50.
2.
Connect +5V DC from DC power supply to terminals 1 and 2.
3.
Connect + 10V DC from DC power supply to terminals 3, 4.
4.
Rotate both the potentiometer P1 and P2 fully in CCW (counter clockwise
direction).
5.
Connect Ammeter between terminal 2 and 3 to measure input base current IB
(µA).
6.
Short or connect a 2mm patch cord between terminal 4 and 5.
7.
Connect one voltmeter between terminal 1 and ground to measure input voltage
VCB and another voltmeter between terminal 6 and ground to measure output
voltage VCE.
8.
Switch ON the instrument.
9.
Vary potentiometer P2 and set a value of output voltage VCE at some constant
value (4.5V, 5V, 5.5)
10.
Vary the potentiometer P1 so as to increase the value of input voltage VCB in
step and measure the corresponding values of input current IB for different
constant values of output voltage VCE in an Observation Table 1.
11.
Rotate potentiometer P1 fully in CCW direction.
12.
Repeat the procedure from step 9 for different sets of output voltage VCE.
13.
Plot a curve between input voltage VCB and input current IB as shown in figure
47 using suitable scale with the help of observation Table l. This curve is the
required Input Characteristic.
Results :
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Input resistance Rin = ___________
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Observation Table 1 :
Input
S. No.
1.
0.0V
2.
0.1V
3.
0.2V
4.
0.3V
VCE = 4.5V
VCE = 5V
VCE =5.5V
-c
6.
output voltage
voltage
VCB
5.
Input current IB(µA) at constant value of
0.4V
0.5V
8.
0.7V
9.
0.8V
10.
0.9V
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0.6V
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7.
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To plot Output Characteristics proceed as follows :
1.
Switch OFF the instrument.
2.
Rotate both the potentiometer P1 and P2 fully in CCW (counter clockwise
direction).
3.
Connect voltmeter between terminal 6 and ground to measure output voltage
VCE.
4.
Connect one Ammeter between terminal 2 and 3 to measure input current
IB(µA) and another Ammeter between terminal 4 and 5 to measure output
current IE(mA).
5.
Switch ON the instrument.
6.
Vary potentiometer P1 and set a value of input current IB at some constant value
(0µA, i.e. input open circuit/remove ammeter between terminal2 and 3, 10µA,
20µA)
7.
Vary the potentiometer P2 so as to increase the value of output voltage VCE from
zero to maximum value in step and measure the corresponding values of output
current IE for different constant value of input current IB in an observation
table.2.
8.
Rotate potentiometer P2 fully in CCW direction.
9.
Repeat the procedure from step 6 for different sets of input current IB.
10.
Plot a curve between output voltage VCE and output current IE as shown in figure
48 using suitable scale with the help of observation table 2. This curve is the
required Output Characteristic.
Results :
on
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Output resistance Rout ________ =
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Observation Table 2 :
S. No.
Output
voltage
VCE
Output current IE (mA) at constant value of
input voltage
IB = 0µA
(open)
0.0V
2.
0.5V
3.
1.0V
4.
2.0V
5.
3.0V
6.
4.0V
7.
5.0V
8.
6.0V
9.
7.0V
IB =20µA
IB =30µA
IB =40µA
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1.
IB =10µA
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To plot Constant Current Transfer Characteristics proceed as follows :
1.
Switch OFF the instrument.
2.
Rotate both the potentiometer P1 and P2 fully in CCW (counter clockwise
direction).
3.
Connect voltmeter between terminal 6 and ground to measure output voltage
VCE.
4.
Connect one Ammeter between terminal 2 and 3 to measure input current IB
(µA) and other Ammeter between terminal 4 and 5 to measure output current IE
(mA).
5.
Switch ON the instrument.
6.
Vary potentiometer P2 and set a value of output voltage VCE at constant value of
3 V.
7.
Vary the potentiometer P1 so as to increase the value of input current IB in step
and measure the corresponding values of output current IE in an observation
Table 3.
8.
Plot a curve between output current IE and input current IB as shown in figure 49
using suitable scale with the help of observation Table 3. This curve is the
required Transfer Characteristic.
Results :
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Current Gain ϒac = ___________
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Observation Table 3 :
S. No.
Input
current
IB (µA)
Output current IE (mA) at
constant output voltage
VCE = 3V
1.
2.
3.
5.
7.
8.
9.
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4.
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Calculations :
1.
Input resistance : It is the ratio of change in the input voltage VCB to change in
the input current IB at constant value of output voltage VCE or it is the reciprocal
of the slope obtained from the input characteristic.
Mathematically :
To calculate input resistance determine the slope from the input characteristic
curve obtained from observation Table 1.
Reciprocal of this slope will give the required input resistance.
2.
Output resistance : It is the ratio of change in the output voltage VCE to change
in the output current ICat constant value of input current IB or it is the reciprocal
of the slope obtained from the output characteristic.
-c
Mathematically :
3.
on
To calculate output resistance determine the slope from the output characteristic
curve obtained from observation Table 2. Reciprocal of this slope will give the
required output resistance.
Current gain : It is the ratio of change in the output current IE to change in the
input current IB at constant value of output voltage VCE or it is the slope
obtained from the constant current transfer characteristic. It is denoted by ϒac
su
Mathematically :
ϒac = Slope of constant current transfer characteristic =
ΔI E
ΔIB
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To calculate current gain, determine the slope from the constant current transfer
characteristic curve obtained from observation Table 3. This slope is the
required current gain.
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Experiment 13
Objective :
Study of Common Emitter Amplifier
Equipments Needed :
Component
1.
2.
Resistance
511 ohms
1
4.7K ohms
1
10K ohms
1
100K ohms
1
Capacitor
1 µF
2
22 µF
1
Transistor NPN BC547
1
-c
3.
Quantity
Amplification is the process of increasing the strength of signal. An Amplifier is a
device that provides amplification (the increase in current, voltage or power of signal)
without appreciably altering the original signal.
on
Bipolar transistors are frequently used as amplifiers. A bipolar transistor is a current
amplifier, having three terminals Emitter, Base, Collector. A small current into base
controls a large current flow from the collector to emitter. The large current flow is
independent of voltage across the transistor from collector to emitter this makes it
possible to obtain a large amplification of voltage by taking the output voltage from a
resistor in series with the collector.
Transistor can be used as an Amplifier in three configurations:
Common Base
2.
Common Emitter
3.
Common Collector
Common Emitter configured :
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1.
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In this arrangement, the input signal is applied between base and emitter and the
output is taken from the collector to emitter shown in figure 51.
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Figure 51
Transistor as an Amplifier in CE Configuration :
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The conditions for which transistor works as an amplifier are:
1.
Emitter Base junction is always forward biased.
2.
Collector Base junction is always reverse biased.
on
To achieve this, a DC voltage VBB is applied in the input circuit in addition to signal
shown in figure 51. This voltage is known as bias voltage and its magnitude is such
that it always keeps the input circuit forward biased regardless the polarity of signal.
Current relations in CE configurations
su
The input circuit has low resistance, therefore a small change in signal voltage causes
an appreciable change in emitter current, this causes almost same change in collector
current due to transistor action. The collector current is flowing through high load
resistance Rc produces a large voltage across it, thus a weak signal applied in the
input circuit appears in the amplified form in collector circuit.
IE = IC + IB
IC = α IE +ICEO
Where,
IC = Collector current
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IC= βIB
ICEO = current through collector to emitter when base is open.
β = common emitter DC current gain. β ranges between 20 - 300.
Voltage Gain :
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The ratio of Output Voltage (VO) to the input voltage (Vin) is known as voltage
amplification or voltage gain of amplifier.
Voltage Gain (AV) = VO / Vin
Operation of Common Emitter amplifier :
In order to get faithful amplification, the transistor is properly DC biased. The
purpose of DC biasing is to obtain a certain DC collector current (IC) at a certain DC
collector voltage (VCE). These values of current and voltage are called operating point
(Quiescent point). To obtain DC operating point some biasing methods are used
called biasing circuits. These biasing arrangements should be such as to operate the
transistor in Active region.
The Most commonly used Biasing circuits is voltage divider method. In this method
two resistances R1 and R2 are connected across the supply voltage VCC and provide
proper biasing. A voltage divider formed by R1 and R2, and the voltage drop across R2
forward biases the base emitter junction this causes the base current and hence
collector current flows in zero signal condition. Resistance RE provides stabilization.
R1 + R2
R1 + R2
VTH
= VBE + VE
VTH
= VBE + IERE
IE
= (VTH – VBE) / RE
IE is approximately equal to IC.
IC
= (V2 – VBE) / RE
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Vth : = VCC × R2
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Rth : = R1 ⋅ R2
Figure 52
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VCE
= VCC – IC (RC + RE)
This method is widely used because operating point of transistor can be made almost
independent of beta (β) and provides good stabilization of operating point.
If this circuit is used to amplify AC voltages, some more components must be added
to it.
Coupling Capacitors (C1) :
They are used to pass AC input signal and block the DC voltage from the preceding
circuit. This prevents DC in the circuitry on the left of coupling capacitor from
affecting the bias on transistor. The Coupling Capacitor also blocks the bias of
transistor from reaching the input signal source. It is also called Blocking Capacitor.
Bypass Capacitors (C3) :
It bypasses all the AC current from the emitter to the ground. If the capacitor CE is not
added in the circuit, the AC voltage developed across RE will affect the input AC
voltage, such a feedback is reduced by putting the capacitor C3.
Load Resistance (RO) :
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It represents the load resistance is connected at the output. The input to the amplifier
is a sine wave that varies a few millivolts. It is introduced into the circuit by the
coupling capacitor and is applied between the base and emitter with proper biasing
circuit. As the input signal goes positive, the voltage across the emitter-base junction
becomes more positive. This in effect increases forward bias, which causes base
current to increase at the same rate as that of the input sine wave. Emitter and
collector currents also increase but much more than the base current. With an increase
in collector current, more voltage is developed across RC. Since the voltage across RC
and the voltage across transistor (collector to emitter) must add up to VCC, an increase
in voltage across RC results in an equal decrease in voltage across transistor.
Therefore, the output voltage from the amplifier, taken at the collector of transistor
with respect to the emitter, is a negative alternation of voltage that is larger than the
input, but has the same sine wave characteristics.
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During the negative alternation of the input, the input signal opposes the forward bias.
This action decreases base current, which results in a decrease in both emitter and
collector currents. The decrease in current through RC decreases its voltage drop and
causes the voltage across the transistor to rise along with the output voltage.
Therefore, the output for the negative alternation of the input is a positive alternation
of voltage that is larger than the input but has the same sine wave characteristics.
By examining both input and output signals for one complete alternation of the input,
we can see that the output of the amplifier is an exact reproduction of the input except
for the reversal in polarity and the increased amplitude (a few millivolts as compared
to a few volts).
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Figure 53
Input and Output Waveforms of Common Emitter Amplifier with load resistance
1KΩ.
Operating Parameters of Common Emitter Amplifier :
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Voltage Gain :
It is the ratio of output voltage (V out) obtained to input voltage (V in).
Av = Vout / Vin
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Input Impedance :
Figure 54
It is the ratio of Input voltage (Vin) to Input Current (Ii).
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Zin = Vin / Ii
To measure the input impedance a known resistor (Rs) is placed in series before the
input coupling capacitor and the impedance can be calculated using the equation.
Zin = Rs / (Av/Av’-1)
Where,
Av = voltage gain without the resistor (Rs)
Av’= voltage gain with the resistor (Rs)
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Output Impedance :
It is the ratio of Output voltage (Vout) to Output Current (Io).
Zout = Vout /Io
To measure the Output impedance a known resistor (Rs) is placed from output to
ground and the output impedance can be calculated using the equation.
Zout = (Av /Av’-1) * Rs
Where,
Av = voltage gain without the resistor (Rs)
Av’ = voltage gain with the resistor (Rs)
Current Gain :
It is the ratio of Output current (Io) to Input current (Ii).
Ai = Io / Ii
The Current gain could be calculated using the equation
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Ai = - Av * Zin / RL
Characteristics of Common Emitter Amplifier :
It produces phase reversal of input signal i.e., input and output signals are 180°
out of phase with each other.
2.
It has very high voltage gain.
3.
It has moderately low input impedance.
4.
It has moderately large output impedance.
5.
It has high current gain (β).
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Type of Amplifier Circuit
Characteristic
Common
Base
Common
Emitter
Common
Collector
Phase reversal
No
Yes
No
Voltage Gain
High
Highest
Nearly Unity
Input Impedance
Lowest
Moderate
Highest
Output Impedance
Highest
Moderate
Lowest
Current Gain
Nearly unity
High (β)
Highest (β+ 1)
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Circuit diagram :
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Common Emitter Amplifier
Figure 55
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Procedure :
Make Connections as shown in the figure 55.
2.
Connect +9V DC from DC power supply to terminal 1.
3.
Switch ON the instrument.
4.
Connect a sine wave of amplitude 20mVpp, 1 KHz from Sin/Square/TTL
Generator to the Vin of common emitter amplifier as shown in the figure 55
5.
Observe the Vout on the oscilloscope. A sine wave of 1Vpp of corresponding
frequency is observed on oscilloscope.
6.
Repeat steps 4 and 5 for Vin equal to 25mV.
7.
Calculate voltage gain = Vout / Vin.
8.
Decrease input frequency till the output falls to 0.707V. This is low Cutoff
frequency (FL).
9.
Increase the input frequency till the output falls to 0.707V. This is high Cutoff
frequency (FH).
10.
Calculate Bandwidth= FH - FL
Result :
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1.
Operating Point of the Common emitter amplifier
IC = ________ mA
VCE = ___________V
on
Voltage gain of the amplifier AV = __________
Input impedance of amplifier Zin = __________
Output Impedance of amplifier Zout = ________
Current gain of amplifier Ai = _____________
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Voltage gain reduces as load resistance is connected to circuit.
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Experiment 14
Objective :
Study of observe the gain characteristics of an Op - amp based Noninverting
Amplifier
Equipments Needed :
1.
Resistors 10K
2
2.
Pot 100K
1
3.
IC741
1
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The operational amplifier (op - amp) was designed to perform mathematical
operations. Although now superseded by the digital computer, op - amps are a
common feature of modern analog electronics. The op amp is constructed from
several transistor stages, which commonly include a differential-input stage, an
intermediate-gain stage and a push-pull output stage. The differential amplifier
consists of a matched pair of bipolar transistors or FETs. The push-pull amplifier
transmits a large current to the load and hence has small output impedance. At first
the op amps are named as Ideal Op - Amp due to the salient parameters of the op amp
are assumed to be perfect. There is no such thing as an ideal op amp, but present day
op amps come so close to ideal that Ideal Op - Amp analysis approaches actual
analysis. Op - amps depart from the ideal in two ways.
First, DC parameters such as input offset voltage are large enough to cause
departure from the ideal. The ideal assumes that input offset voltage is zero.
2.
Second, the op - amp gain is assumed to be infinite, hence it drives the output
voltage to any value to satisfy the input conditions. This assumes that the op amp output voltage can achieve any value. In reality, saturation occurs when the
output voltage comes close to a power supply rail, but reality does not negate the
assumption, it only bounds it. Also, implicit in the infinite gain assumption is
the need for zero input signals. The gain drives the output voltage until the
voltage between the input leads (the error voltage) is zero.
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1.
This assumption simplifies the analysis, thus it clears the path for insight. Although
the ideal op - amp analysis makes use of perfect parameters, the analysis is often valid
because some op - amps approach perfection.
Negative feedback Amplifier :
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An output is fed back to the input either directly or via some network is called
feedback network, if the signal fed back is of opposite polarity or out of phase by
180° with respect to the input signal, the feedback is called negative feedback.
Negative feed back is also know as Degenerative Feedback because when it is used it
reduces or Degenerates the output voltage amplitude and in turn reduces the voltage
gain. Hence the question arises; why use negative feed back? The negative feed back
is used to stabilize the gain, increases the bandwidth and changes in input output
resistances. Other benefits of negative feedback include a decrease in harmonics or
nonlinear distortion and reduction in the effect of input offset voltage at the output. It
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also reduces the effect of variations in temperature and supply voltages on the output.
An op - amp that uses feedback is called as feedback amplifier. It is also referred as
closed loop amplifier because the feedback forms a closed loop between input and
output. A feedback amplifier consist of two part : an op amp and a feedback circuit. A
feedback circuit can take any form whatsoever, depending on the intended application
of the amplifier. The block diagram of feedback amplifier is shown in figure 56.
Block diagram of Feedback Amplifier
Figure 56
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A closed loop diagram can be represented by using two blocks, one for an op - amp
(A) and another for a feedback circuit (β).There are four way to connect these two
blocks. These Connections are classified accordingly whether the voltage or current is
fed back to the input in series or in parallel. The classifications are as follows :
Voltage-Series Feedback
2.
Voltage-Shunt Feedback
3.
Current-Series Feedback
4.
Current-Shunt Feedback
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1.
The Voltage Series and Voltage Shunt Feedback are important because they are
commonly used.
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Voltage-Series Feedback :
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In Voltage Series Feedback Voltage is fed back in series. You all maybe asking, why
use a voltage series feedback? As we all know the gain of all op - amps decreases as
frequency increases, and the decreasing gain results in decreasing accuracy as the
ideal op - amp assumption breaks down. In most real op - amps the open loop gain
starts to decrease before 10Hz, so an understanding of feedback is required to predict
the closed loop performance of the op amp. Therefore in other words we can say that
the voltage series feedback is require for a stable gain over a particular frequency
range. A voltage series feedback also increases the input impedance of op - amp, it
decreases the output impedance and the output offset voltage. But for all this benefits
we have to pay the price as decrease in op - amp gain. A Non inverting Amplifier is
widely used implementation of Voltage series feedback.
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Block diagram of Voltage Series Feedback
Figure 57
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The Non-inverting amplifier is an amplifier in which the output signal is in phase
with input signal with some amplification. The noninverting configuration of a opamp is shown in figure 57. An input voltage VIN drives the noninverting input. The
input voltage is amplified to produce the in-phase output voltage. Part of output
voltage is fed back to the input through a voltage divider. The voltage across the RF is
the feedback voltage applied to the inverting input terminal. The feedback is almost
equal to the input voltage. Because of the high open-loop voltage gain, the difference
between the voltage appearing at noninverting terminal (lets say V1) and the voltage
appearing at inverting terminal (lets say V2) is very small. Since the feedback opposes
the input voltage, it is negative feedback.
Op Amp in Noninverting configuration
Figure 58
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How the negative gain does stabilize the overall voltage gain? If the open-loop
voltage gain AOL increases for any reason, the output voltage will increase and
feedback more voltage in inverting input terminal. This opposing feedback voltage
reduces the net input voltage : V1 - V2. Therefore, even though the AOL increase the
V1 - V2 decreases and the final output increases much less than it would without the
negative feedback and hence the there is a very slight increases in the output voltage.
The Closed Loop Voltage Gain (ACL):
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The noninverting op - amp has the input signal connected to its noninverting input
(figure 58), thus its input source observes infinite impedance. There is no input offset
voltage because VOS = VE = 0, hence the negative input must be at the same voltage as
the positive input. The op amp output drives current into RF until the negative input is
at the voltage, VIN. This action causes VIN to appear across RG. The voltage divider
rule is used to calculate Vin; Vout is the input to the voltage divider, and VIN is the
output of the voltage divider. Since no current can flow into either of op - amp lead,
use of the voltage divider rule is allowed in an amplifier in which the output signal is
in phase with input signal with some amplification. The noninverting configuration of
an op - amp is shown in figure 58. An input voltage VIN drives the noninverting input.
The input voltage is amplified to produce the in-phase output voltage. Part of output
voltage is fedback to the input through a voltage divider. Hence
………………………. (1)
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………………………. (2)
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The function of RF is to protect the inverting input from an over voltage to limit the
current through the input ESD (electro-static discharge) structure (typically < 1mA),
and it can have almost any value (20K is often used). RF can never be let out of the
circuit in a current feedback amplifier design because RF determines stability in
current feedback amplifiers.
Notice that the gain equation in equation 1, the gain is only a function of the feedback
and gain resistors; therefore the feedback has accomplished its function of making the
gain independent of the op amp parameters. The gain is adjusted by varying the ratio
of the resistors. The impedance level does not set the gain; the ratio of RF/RG does.
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Circuit diagram :
Non Inverting Amplifier
Figure 59
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Procedure :
1. Make connections as shown in the figure 59.
2. Connect + 12V to pin no 7 and -12V to pin no 4 of IC741. See IC pin diagram.
3. Set the potentiometer ‘P1’ at 10K.
4. Connect a sine wave of amplitude 1Vpp, 1 KHz from Sin/Square/TTL
Generator block to the Vin input of noninverting terminal of op amp as shown in
the figure.
5. Observe the function generator output at Oscilloscope’s CH II.
6. Keep your Oscilloscope on dual mode; this enables you to see waveform from
both channels of oscilloscope.
7. Switch ON the instrument.
8. Observe the output waveform at pin no. 6 of IC741 and ground, on oscilloscope
CH I.
9. Note the amplitude of the output waveform and calculate the gain at given
frequency.
10. Verify the difference between calculated closed loop gain ACL and measured
closed loop gain ACL’= Vout / Vin.
11. Increase the value of Pot P1, 20 KΩ and then increase it with the margin of
10KΩ.
12. Increase the frequency by the margin of 1 KHz up to 10 KHz and measure the
gain for every frequency.
13. Repeat the above steps from 4 to 10.
Note : TL741 have low slew rate thus after 250 KHz it starts giving faulty or
unpredictable results. Hence to avoid confusion do not use the frequency above
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200 KHz.
Calculation :
Gain of Amplifier =
where
ACL = 1+ RF/ R1
RF = Resistance of Pot P1 =
R1 =
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Observation table :
S.
No.
Frequency
(KHz)
RF
(in
KΩ)
R1
(in KΩ)
ACL = 1 +
RF/R1
ACL’ =
Vout / Vin
(Calculated)
Measured
Phase Shift
Between
Input and
Output
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Conclusion :
1.
Increase in resistive value of Pot gives higher amplification i.e. output is
dependent on the value of feedback resistors.
2.
The closed loop gain does not vary with the variation in frequency i.e. output is
independent on the value of frequency.
3.
The value of ACL and ACL’ is same.
4.
0° phase shift occurs between input and output. i.e. input and output are in same
phase.
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Experiment 15
Objective :
Study of Voltage Follower Configuration
Equipments Needed :
Components
Quantity
1.
IC741
1
2.
Resistor 10K
2
Voltage follower :
+Vp
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A noninverting amplifier which is configured for unity gain is called a voltage
follower because the output is equal and in phase with the input. Therefore, in the
voltage follower output follows the input. Although it is similar to discrete emitter
follower, the voltage follower is preferred because it has much higher input resistance
and the output amplitude is exactly equal to the input (or, close enough to satisfy any
application). To obtain a voltage follower from a noninverting amplifier RG becomes
open and RF becomes short. The resulting circuit may appear deceptively simple, the
circuit is very close to ideal one because the negative feedback is maximum due to the
feedback resistor is value as zero and all output is fed back to the inverting input and
due to virtual short between the op- amps input, the output voltage equal to input
voltage. Figure 60 shows the circuit of voltage follower.
+Vp
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Voltage Follower
That means closed loop gain (ACL) should be one,
ACL = 1+ RF/ R1
Thus
RF = 0 (no resistance, i.e. short)
R1 = ∞ (infinite resistance, i.e. open)
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Vout = VIN
Figure 60
………………….….. (3)
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Furthermore, the maximum negative feedback produces closed-loop input impedance
that is much higher than the open-loop impedance and output impedance is much
lesser than the open-loop impedance. Therefore a voltage follower is almost perfect
method for converting a high impedance source into a low impedance source. A
voltage follower provides maximum bandwidth and another advantage of voltage
follower is low output offset error due to no amplification of input errors. Since the
ACL = 1, the total output error voltage equals the worst-case sum of the input error.
Voltage follower is also called noninverting buffer because, when placed between two
networks, it removes the loading on the first network.
Circuit diagram :
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Voltage Follower
Procedure :
Figure 61
Connect the circuit as shown in the figure 61.
1.
Connect the on board function generator at pin no. 3 of IC741.
2.
Connect pin no. 2 & 6 i.e. short them.
3.
Connect the positive power supply (+12V) at IC741 pin no.7 & negative power
supply (-12V) at IC741 pin no.4.
4.
Set the 1V, 1 KHz input sinusoidal signal of function generator and observe the
input at oscilloscope CH II.
5.
Observe the output waveform at pin no. 6 and ground, on oscilloscope CH I.
6.
Observe the output signal’s amplitude, wave shape and its phase difference with
the input signal.
7.
Increase the input amplitude with the margin of 1V.
8.
Repeat the above steps from 3 to 4.
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Observation Table :
S. No.
Input voltage
(VIN)
Output voltage (Vout)
Phase shift (φ)
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Conclusion : The input and output signals have same amplitude and are in same
phase i.e. zero phase difference.
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Experiment 16
Objective :
Study of Op- amp gain in Voltage Shunt Feedback Configuration i.e. Inverting
configured
Equipments Needed :
Component required :
Quantity
1.
Resistors 10K
2
2.
Pot 100K
1
3.
IC741
1
Voltage-Shunt Feedback :
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Voltage shunt feedback is another form of negative feedback and it is commonly used
as voltage series feed back. Voltage series feedback is also known as Trans resistance
feed back. The voltage shunt feed back has no effect on input impedance, although it
decreases the output impedance and offset voltage of an op amp. It also increases the
operating frequency of an op amp, that means it provide constant gain over a
particular bandwidth. Characteristics of voltage shunt feedback amplifier is :
Low to medium input impedance.
b.
Minimum gain is zero.
c.
Noisy than the voltage series configuration, as the noise gain is always more
than the signal gain.
on
a.
The main difference between the voltage series and voltage shunt amplifier is in
voltage series feedback the voltage is fed back in voltage form whilst in the voltage
shunt feed back input is taken as current and the output is voltage. Hence the voltage
shunt feedback is used as current to voltage converter. An Inverting Amplifier is
widely used implementation of Voltage shunt feedback.
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Block diagram of Voltage Shunt Feedback
Figure 62
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The Inverting amplifier :
The inverting amplifier is an amplifier in which the output signal is out of phase with
input signal, i.e. input and output signal has the phase shift of 180° with some
amplification. The inverting configuration of a op amp is shown in figure 63.
Op Amp in Inverting configuration
Figure 63
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An input voltage VIN drives the inverting input through the resistance RG. This
produce an inverting input voltage of VE. The input voltage is amplified by the open
loop voltage gain to produce an inverting output voltage. The output voltage is fed
back to the input through the resistor RF. This results in a negative feedback because
the output is 180° out of phase with the input, in other words any changes in VE
produced by the input voltage are opposed by the output signal.
Again the same question arises. How the negative gain does stabilize the overall
voltage gain? If the open-loop voltage gain AOL increases for any reason, the output
voltage will increase and feedback more voltage in inverting input terminal. This
opposing feedback voltage reduces VE. Therefore, even though the AOL increase the
VE decreases and the final output increases much less than it would without the
negative feedback and hence the there is a slight increase in the output voltage.
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The Closed loop voltage gain (ACL) :
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The noninverting input of the inverting op amp circuit is grounded. One assumption
made is that the input error voltage is zero, so the feedback keeps inverting the input
of the op - amp at a virtual ground (not actual ground but acting like ground). The
current flowing in the input leads is assumed to be zero, hence the current flowing
through RG equals the current flowing through RF. Using Kirchoff’s law, we write
equation 1; and the minus sign is inserted because this is the inverting input.
Algebraic manipulation gives the equation 1.
………………….(1)
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Notice that the gain is only a function of the feedback and gain resistors, so the
feedback has accomplished its function of making the gain independent of the op amp
parameters. The actual resistor values are determined by the impedance levels that the
designer wants to establish. Hence, the impedance level does not set the gain; the ratio
of RF/RG does. One final note; the output signal is the input signal amplified and
inverted. The circuit input impedance is set by RG because the inverting input is held
at a virtual ground.
Note : A virtual ground is not some point connected to the ground with a piece of
wire, it is different. A virtual ground is like a half of a ground because it is short for a
voltage and open for the current. I.e. current and voltage both are zero. This kind of
ground is widely used shortcut for analyzing an amplifier. The concept of virtual
ground is based on an ideal op amp. When an op- amp is idea, it has infinite openloop voltage gain and infinite input resistance. Due to infinite resistance properties
we assume that no current is flowing in the op-amp and current is zero. And due to
infinite gain property the current at RF and RG should be equal and it only happen
when voltage at inverting terminal is zero.
Circuit diagram :
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Voltage Shunt Feed back Configuration
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Figure 64
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Procedure :
Set the value of Potentiometer P at 10KΩ.
1.
Calculate the closed-loop gain ACL by using the equation 1.
2.
Connect a 10K resistance to pin no. 2 and function generator
3.
Connect the on board function generator at the Vin.
4.
Connect the Pot P between IC741 pin no. 2 & 6
5.
Connect a 10K resistance to IC741 pin no. 3 and ground the next end of
resistance.
6.
Connect the positive power supply (+12V) at IC741 pin no.7 & negative power
supply (-12V) at IC741 pin no.4.
7.
Set the 1V, 1 KHz input sinusoidal signal of function generator and observe the
input at oscilloscope CH II.
8.
Observe the output waveform between pin no. 6 and ground, on oscilloscope
CH I.
9.
Note the amplitude and phase of the output waveform and calculate the gain at
given frequency.
10.
Verify the difference between calculated closed loop gain ACL and measured
closed loop gain ACL’= Vout / VIN.
11.
Increase the value of Pot P2 with the margin of 5KΩ.
12.
Repeat the above steps from 2 to10.
13.
Increase the frequency by the margin of 1 KHz up to 10 KHz and measure the
gain for every frequency.
14.
Repeat the above steps from 2 to 12.
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Observation table :
S.
No.
Frequency
(KHz)
RF (in
KΩ)
R1 (in
KΩ)
ACL = - RF/R1
(Calculated)
ACL’= Vout
/VIN
(Measured)
Phase
shift
(φ)
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Conclusion :
The closed loop gain does not vary with the variation in frequency it is
dependent on the value of feedback resistors.
2.
The value of ACL and ACL’ is same.
3.
The output voltage and input voltage has 180° phase shift.
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Experiment 17
Objective :
Study of operation of Wheatstone Bridge and measuring the value of unknown
resistance
Equipments Needed :
1.
Resistors 10K
2
2.
Resistor 5K
1
3.
Pot 47K
1
Bridges are amongst the most accurate types of measuring devices used in the
measurement of impedance. In addition, bridges are also used to measure DC
resistance, capacitance, and inductance. Certain types of bridges are more suitable for
measuring a specific characteristic, such as capacitance or inductance.
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Wheatstone bridge : A very important device used in the measurement of medium
resistances is the Wheatstone bridge. Wheatstone bridge has-been in use longer than
almost any electrical measuring instrument. It is still an accurate and reliable
instrument and is extensively used in industry. The Wheatstone bridge is an
instrument for making comparison instruments and operates upon a null indication
principle. This means the indication is independent of the calibration of the null
indicating instrument or any of its characteristics. For this reason, very high degrees
of accuracy can be achieved using Wheatstone bridge. Accuracy of 0.1% is quite
common with a Wheatstone bridge as opposed to accuracies of 3% to 5% with
ordinary ohmmeter for measurement of medium resistances. The Wheatstone bridge
is well suited also for the measurement of small changes of a resistance and therefore,
is also suitable to measure the resistance change in a strain gauge. It is commonly
known that the strain gauge transforms strain applied to it into a proportional change
of resistance. It is widely used across industry even today.
The basic circuit of a Wheatstone bridge is shown below. It has four resistive arms,
consisting of resistances R1, R2, R3 and R4 together with a source of Emf (a battery)
and a null detector, usually a galvanometer G or other sensitive current meter.
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Since there is a current in each of the arms ‘abc’ and ‘adc’ of the circuit, there is a
potential drop (IR) in the direction of the current. That is, the point a is at a higher
potential than the point ‘b’ and likewise ‘b’ is at a higher potential than the point ‘c’
Note therefore, that both the points ‘b’ and‘d’ are at potentials lower than that of a and
higher than that of ‘c’ But the potentials of these two points ‘b’ and‘d’ are not
necessarily equal.
Consider the arm ‘bd’ containing the galvanometer G. The current in this arm would
be from ‘b’ to‘d’ if ‘b’ is at a higher potential than‘d’. It would be from‘d’ to ‘b’ if‘d’
is at a higher potential than ‘b’.
In the event that the potential of the point ‘b’ is exactly equal to that of the point d,
there will be no current in the arm ‘‘bd’’ and the galvanometer would indicate this
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lack of current. In this particular case, the Wheatstone bridge is said to be balanced.
This condition is obtained only if the ratio of the resistances R1 and R2 happens to be
equal to the ratio of the resistances R3 and R4.
Thus whenever a circuit is connected as in the figure above, one of the four
resistances R1, R2, R3 or R4 being unknown, and at least one of the other three
resistances being a variable resistance, the required condition of
R1 / R2 = R3 / R4 …….……………… equation 1
can be attained by altering the value of the variable resistor. Once the galvanometer
indicates a zero deflection, if the values of the other resistances are known then the
value of one unknown resistance can be calculated from the above condition.
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Wheatstone Bridge
Figure 65
From Kirchhoff's first law applied to the point ‘b’ we have,
I1 = IG + I2........................................................ equation 2
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Similarly, for the point d, we have,
I4 = IG + I3......................................................... equation 3
Applying Kirchhoff's second law to the network abd,
I1R1 + IGRG - I3R3 = 0........................................ equation 4
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Likewise, for the network bcd, we have,
I4R4 + IGRG - I2R2 = 0......................................... equation 5
If the bridge is balanced, then we have,
If IG = 0
then,
I1 = I2
and I3 = I4
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If ,
IG = 0
Then equation 4 states
I1R1 = I3R3 …………………………….. (6)
Similarly, from circuit bcd, we have,
I2R2 = I4R4……………………..………. (7)
Dividing eq 6 by eq 7, we get
I1R1 / I2R2 = I3R3 / I4R4
This is called the balance condition of the bridge. If this condition is satisfied then the
galvanometer gives no deflection.
Sensitivity of Wheatstone bridge :
It is frequently desirable to know the galvanometer response to be expected in a
bridge which is slightly unbalanced so that a current flow in the galvanometer branch
of the bridge network. This may be used for:
Selecting a galvanometer with which a given unbalance may be observed in a
specified bridge arrangement,
2.
Determining the minimum unbalance which can be observed with a given
galvanometer in the specified bridge arrangement, and
3.
Determining the deflection to be expected for a given unbalance.
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1.
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The sensitivity to unbalance can be computed by solving the bridge circuit for a small
unbalance. Assume that the bridge is balanced when the branch resistances are R1, R2,
R3 and R4 so that R1 / R2 = R3 / R4. Suppose the resistance R2 is changed to R2 + ∆ R
creating an unbalance. This will to cause an Emf (e) to appear across the
galvanometer branch. With galvanometer branch open, the voltage drop between
points ‘b’ and ‘c’ is
Where
E = Emf of battery
Similarly,
Ecd=I4 (R4) =E R4 / (R3+ R4)
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Ebc = I2 (R2 + ∆ R) = E (R2 + ∆ R)/ (R1+R2 + ∆ R),
Therefore the voltage difference between points ‘b’ and‘d’ is:
e = Ebc - Ecd
= E [(R2 + ∆ R)/ (R1+R2 + ∆ R) - R4 / (R3+ R4)]. ……. equation 8
For balanced condition:
I1R1= I3 R4 and I2 R2 = I4 R4 ……………… equation 9
For galvanometer current to be zero, the following condition also exist:
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I1= I2=E/ (R1+R2) ……………… …… equation 10
I3=I4=E/ (R3+R4)………………..……. equation 11
Combining the equation we obtain:
R2 / (R1+R2) = R4/ (R3+R4)
Substituting the values in eq(8)
e = E [(R2 + ∆ R)/ (R1+R2 + ∆ R) - R2 / (R1+R2)]
= E [R1∆ R/ {(R1+R2)2+∆ R (R1+R2)}]
As ∆R (R1+R2) << (R1+R2)2
=E [R1∆ R/ (R1+R2)2]………….……… equation 12
Let Sv be the voltage sensitivity of galvanometer.
Therefore, deflection of galvanometer is :
θ= Sv e= Sv E [R1∆ R/ (R1+R2)2]
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The bridge sensitivity SB is defined as the deflection of the galvanometer per unit
fractional change in unknown resistance.
Bridge sensitivity SB = θ/ (∆ R /R2)
= Sv E [R1/ (R1+R2)2] ………….………. equation 13
Note :
on
The sensitivity of the bridge is dependent upon bridge voltage, bridge parameters and
the voltage sensitivity of the galvanometer. Sensitivity is maximum for bridges with
equal arms.
If current sensitivity is given instead of voltage sensitivity, voltage sensitivity can be
calculated by the following formula:
Where
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Sv = Si / (Ro+G)
Ro is the thevenin equivalent of the bridge
Ro= {R1R3/ (R1 + R3) +R2R4 / (R2 +R4)}
G resistance of the galvanometer circuit.
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Si is the current sensitivity of the galvanometer.
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Circuit diagram :
Wheatstone Bridge
Figure 66
Procedure :
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Connect the circuit diagram as shown in the figure 66.
2.
Measure the value of resistance R1, R2 and R3 with the help of multimeter
3.
Calculate the value of R UNKNOWN as shown in equation 1.
4.
Connect the Supply voltage at ‘a’ and ‘b’ terminal of bridge.
5.
Connect positive terminal of galvanometer to ‘c’ terminal and negative terminal
of galvanometer to‘d’.
6.
Vary Runknown till the galvanometer gives the null deflection for accurate null
deflection fine tuning pot is given on the board.
7.
Measure the value of Runknown with help of multimeter and verify that the value
of Runknown as calculated by the equation and measured by multimeter are same.
8.
Repeat the process for different values of resistance R1, R2 and R3.
Result :
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1.
The value of Runknown resistance is = …………………..
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Experiment 18
Objective :
Measuring the value of unknown capacitance with the help of De Sauty’s Bridge
Equipments Needed :
Component
Quantity
1.
Capacitor 0.1µF
7
2.
Capacitor 0.47µF
1
3.
Resistor 1K
2
4.
Potentiometer 10K
5
5.
Resistor 221E
1
6.
IC741
1
7.
IC386
1
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Bridge circuits are extensively used for measuring component value such as R, C and
L. It has four arms consisting of resistor or inductor or capacitor, which form a closed
circuit. A DC or AC source applied to two opposite junction and a null detector
connected to the other two junctions. The bridge circuits work as a pair of twocomponent voltage dividers connected across same source voltage, with a null
detector connected between them to indicate a condition of ‘balance’ at zero volts.
Bridges can be classified in two types: DC bridges and AC bridges. DC bridges are
used in measurement of unknown resistance and it is excited by DC source and
galvanometers are used for null detection.
su
AC bridges or Alternating Current bridges consist of four arms, an AC source of
excitation and a balance detector. In an AC bridge each arm has impedance and the
detector is sensitive towards the slightest change in arm impedance. The usefulness of
AC bridge is not restricted to the measurement of unknown impedance and associated
parameter like inductance, capacitance, storage factor loss and dissipation factor.
Detectors most commonly used for AC bridges are
1.
Head phones
2.
Vibration galvanometers
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These circuits find other application in communication system and complex
electronics circuits such as phase shifting, providing feed back path for oscillator and
amplifiers and filtering out undesirable signals. For measurement at low frequencies
power line may act as the source of the supply to bridge circuits and for higher
frequencies electronics oscillators are used as bridge source supplies. Oscillators have
advantage that frequency is constant easily adjustable and determinable with accuracy
the waveform is much closed to a sine wave and there power output is sufficient for
most bridge measurement.
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3.
Tunable amplifiers detectors
Headphones are widely used as detectors at frequencies of 250Hz and up to 3 or 4
KHz. They are most sensitive detectors for this range when working at a single
frequency a tuned detector normally gives the greatest sensitivity and discrimination
against harmonics in the supply. Vibration galvanometers are extremely useful for
power and low audio frequency ranges. Vibration galvanometers are manufactured to
work at various frequencies ranging from 5Hz to 1000Hz but are most commonly
used below 200Hz as below this frequency they are more sensitive that the head
phones.
Tunable amplifiers detectors are the most versatile of the detectors. The transistors
amplifiers can be tuned electrically and thus can be made to respond to a narrow
bandwidth at the bridge frequency. The output of the amplifier is fed to a pointer type
instrument this detector can be used, over a frequency range of 10Hz to 100 KHz.
General equation for bridge balance :
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Basic AC bridge circuit is shown below the four arm of the bridge are impedance Z1,
Z2, Z3, Z4.The condition for balance of bridge require that there should be no current
through the detector. This requires that the potential difference between points ‘b’
and‘d’ should be zero. This will be the case when the voltage drop from ‘a’ to ‘b’
equals the voltage drop from ‘a’ to‘d’, both in magnitude and phase. In complex
notation, we can thus write :
E1 = E2
Also at balance,
on
I1Z1 =I2Z2
I1=I3 =E/Z1+Z2
I2=I4=E/Z2+Z4
Substituting the equation.
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We get
Z1Z4 =Z2Z3
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Equation states that the product of impedances of one pair opposite arms must equal
the product of impedance of the other pair of opposite arms in complex notation. This
means that both magnitude and phase angle of the impedance must be taken into
account.
Two conditions must be satisfied simultaneously when balancing the AC bridge
The first condition is that the magnitude of impedances satisfies the relationship:
Z1 Z4 = Z2Z3
 Z1

Z
 2
  Z3
=
 Z
  4




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The impedance of the arm is vector complex quantities that posses phase angles. It is
thus necessary to adjust both the magnitude and phase angles to achieve balance, i.e.
the bridge must be balanced for both the reactance and the resistive component.
The second condition is that the phase angles of impedance satisfy the relationship:
(θ1 + θ 4 ) = (θ 2 + θ3 )
The phase angles are positive for inductive impedance and negative for capacitance
impedance.
De Sauty’s Bridge :
This Bridge is the simplest method of comparing capacitance and to determine
unknown capacitance. Figure 67 shows the basic De Sauty’s bridge circuit
configuration.
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De Sauty’ Bridge
Figure 67
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Its first and second arms are consisting of capacitor and third and fourth arm are
consisting of pure resistive elements. The balance can be obtained by varying the
resistance in either third or fourth arm.
Cx = capacitor with unknown capacitance,
C2 = standard capacitor,
At balance,
(1/ jωCx) R4 = (1/ jωC2). R3
Cx = C2. R4/ R3
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R3, R4 = non-inductive resistance.
……………. (1)
But it is impossible to obtain balance if both capacitors are not free from dielectric
loss, in order to make measurement perfect resistor R1 and R2 are connected in series
with Cx and C2 respectively. rx and r2 are ESR of Cx and C2 respectively and
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representing the loss component of the two capacitors.
Thus at balance,
(R1 + rx + 1/ jωCx). R4 = (R2 + r2+1/ jωC2). R3
Cx /C2 = (R2 + r2) / (R1 + rx) = R4/ R3
Or,
rx = [(R2 + r2). R3 – R1 R4] / R4
……………. (2)
The Dissipation factor for the capacitor is :
D = tanδ = ω.Cx.rx
……………. (3)
To determine the difference in dissipation
D1 – D2 = tanδ1– tanδ2 = ωCx.rx – ωC2r2
D1 – D2 = ωC2rR2 – ω CxR1
∴ Cx = C2. R4/ R3
D1 – D2 = ωC2 (R2 – R1. R4 /R3)
..............(4)
Therefore if the dissipation factor of one of the capacitor is known, the dissipation
factor for other can be determine
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This method does not give accurate results for dissipation factor since its value
depends on different quantities R1, R4, R3 and R2. Thus the dissipation factor cannot
be determined accurately.
Circuit diagram :
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De Sauty’ Bridge
Figure 68
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Procedure :
Connect +/–12V DC power supply and ground at their indicated position from
external source or ST2612 Analog lab.
1.
Connect function generator probes at Vin terminals i.e. between ‘a’ and ‘c’
terminal.
2.
Set the 5Vpp, 1 KHz input sinusoidal signal of function generator.
3.
Switch ON the power supply.
4.
You will hear the Buzz of speaker. This is the imbalance condition.
5.
Rotate the potentiometer to find a condition where null or minimum sound is
generated.
6.
Switch OFF the power supply and function generator.
7.
Take the reading of potentiometer resistance at ‘b’ and ‘c ’.
8.
Calculate the value of capacitance Cx1 and its resistance rx1.
9.
Calculate the value of dissipation factor and difference in dissipation factor for
both capacitor Cx1 and C2.
10.
.Repeat the above step from 4 to 10 for different values of unknown capacitance.
Calculation :
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Measured value of R3 is. ………. Ω
Calculate the value of Cx by the formula :
Cx = C2. R4/ R3
Calculate the values of rx by the formula :
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rx = [(R2 + r2). R3 – R1 R4] / R4
Calculate the value of dissipation factor by the formula :
D = tanδ = ω.Cx.rx
Calculate the value of difference in dissipation factor by the formula:
D1 – D2 = ωC2 (R2 – R1. R4 /R3)
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Observation table :
S.No
.
Cx =
C2. R4/R3
(calculated)
rx
(calculated)
(Ω)
D=
ω.Cx.rx
D1– D2
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Result :
R3
(measured)
(Ω)
The capacitance for Cx ……=…………
The rx ……….. = ………….
The dissipation factor Dx ………. = ………….
And the deference in dissipation factor of Cx …….. and C2 =………
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Note :
The capacitance for Cx1 = .....................and rx1 is in range of..............
The capacitance for Cx3 = .......................and rx3 is in range of ..............
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Experiment 19
Objective :
Study and observation of Op-Amp as a Wien Bridge Oscillator and
determination of its gain factor for a smooth sine wave.
Equipments Needed :
Component
1. Resistance 10K
2. Capacitor 10nF
3. Pot 10K
4. Resistance 2K
5. IC741
Oscillator :
Quantity
2
2
1
1
1
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Oscillators are circuits that produce periodic waveforms without input other than
perhaps a trigger. They generally use some form of active device, lamp, or crystal,
surrounded by passive devices such as resistors, capacitors, and inductors, to generate
the output.
There are two main classes of oscillator: Relaxation and Sinusoidal. Relaxation
oscillators generate the triangular, saw tooth and other non sinusoidal waveforms.
Sinusoidal oscillators consist of amplifiers with external components used to generate
oscillation, or crystals that internally generate the oscillation. The focus here is on
sine wave oscillators, created using operational amplifiers Op-Amps. Sine wave
oscillators are used as references or test waveforms by many circuits.
An oscillator is a type of feedback amplifier in which part of the output is fed back to
the input via a feedback circuit. If the signal fed back is of proper magnitude and
phase, the circuit produces alternating currents or voltages. To find the requirement of
oscillator consider the block diagram in figure 69, this block diagram looks identical
to the feed back amplifier. However the input voltage VIN is zero. Also the feedback is
positive because most oscillators use positive feedback. Finally, the closed-loop gain
of the amplifier is denoted as AV rather then AF.
Block diagram of Oscillator
Figure 69
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AvB =1
AvB =1 0° or 360°
Using the above equation the relationship obtain is
Vd =Vf + Vin
Vo =Avvd
Vf = Bvo
…….………. (1)
Two requirements for oscillation are :
1.
The magnitude of the loop gain AVB must be at least 1.
2.
The total phase shift of the loop gain AvB must be equal to 0° or 360°. If the
amplifier causes a phase shift of 180°, the feedback circuit must provide an
additional phase shift of 180° so that the total phase shift around the loop is
360°.
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The type of wave form generated by an oscillator is depends on the components used
in circuits and hence the waveform generated can be any thing from Sine, Square, or
triangular. The frequency of the oscillation is also determined by the component in
feedback circuit.
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But still the question arises; what is the need of oscillator? And where do we use
them? Lets go to the start again .First, what is the oscillator? It is a device that works
on oscillation. Well, what is that? It is the movement of two things that work on the
energy flow they receive. An oscillating fan, clock and transmitters work by working
on the energy. In the example of a clock, pendulum, the oscillator keeps time for us
accurately based on the principals of oscillation. This is a simple type of oscillator.
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Do you still think you have not used an oscillator in your lifetime? If so, think again.
They are in most computers, clocks of all sorts, as well as in watches, metal detectors,
radios of all powers and uses, as well as many mechanical devices. The oscillator is
one of the most important instruments in our life because it helps us to tell time
accurately. The work of oscillator is does not ends here, but they are used in a variety
of ways throughout our lives. For example, you will find them located not only in
clocks but also in electronic devices of all types. For example, audio frequency
equipment has them as well as wireless receivers and transmitters as well. You will
find them in a sensitive amplifier or you will find them in signals that are used and
sent out. Their uses are unlimited.
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Wien Bridge Oscillator :
The Wien Bridge is one of the simplest and best known oscillators and is used
extensively in circuits for audio applications. Figure 70 shows the basic Wien Bridge
circuit configuration. On the positive side, this circuit has only a few components and
good frequency stability.
Because of its simplicity and stability, it is the most commonly used audio-frequency
oscillator. The Wien Bridge circuit is connected between the amplifier input terminals
and the output terminal. The bridge has a series RC network in one arm and a parallel
RC network in the adjoining arm. In the remaining two arms of the bridge, resistor R1
and Rf are connected.
The phase angle criterion for oscillation is that the total phase shift around the circuit
must be 0°. This condition occurs only when the bridge is balanced, that is at
resonance. The frequency of oscillation FO is exactly the resonant frequency of the
balanced Wien Bridge and is given by
Here FO is the frequency generated by Wien bridge oscillator,
= 1/2 π RC
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FO
= 0.159 / RC
…………… (2)
on
Assuming that the resistors are equal in the value, and the capacitors are equal in the
value in the reactive leg of the Wien Bridge. At this frequency the gain required for
sustained oscillation is given by
Av = 1/β = 3
That is,
…………… (3)
1+ Rf / R1 = 3
Or
Rf = 2R1
…………… (4)
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Wien-Bridge Circuit Schematic
Figure 70
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Circuit diagram :
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Wien Bridge Oscillator
on
Procedure :
Figure 71
To generate the sine wave by Wien bridge Oscillator.
1.
Calculate the value of frequency for given value of R & C by equation 2.
2.
Connect the Circuit as shown in the figure 71.
3.
Take precaution while connecting the supply to IC741 i.e. connect positive
supply (+12V) to pin no. 7 of IC and negative supply (-12V) to pin no. 4 of
IC741
4.
Rotate the potentiometer and set it at twice the value of R i.e. RF = 2 K if R
=1K.
5.
Connect the oscilloscope CH I probe at ‘Vout’ and ground to observe the output
Vout.
6.
If the output shows some distortion or imperfection vary the pot P till the perfect
wave occurs.
7.
Note the output frequency and verify it with measured output frequency.
8.
Now check the potentiometer resistance the value of RF should be twice of the
resistance R.
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9.
Calculate the gain of oscillator and verify it by using equation 3.
10.
Calculate the value of R for the frequency of 10 KHz, change the component.
11.
Repeat the above steps form 4 to 10.
Observation table :
S. No.
R
Frequency
(Calculated)
Output
voltage
Vout
Output
frequency
fOUT
(measured)
RF
Feed back
resistance
Gain
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on
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Conclusion :
The output is a perfect sine wave and the frequency varies with the variation in
the combination of RC.
2.
Value of RF; Feed back resistance is twice of the R1.hence the gain of the bridge
is 3.
3.
Output voltage is equal to VSAT = VSUPPLY -10%
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Experiment 20
Objective :
Study and observation of Op-Amp as a Phase Shift Oscillator and determination
of its phase shift at every RC combination
Equipments Needed :
Component
Quantity
1.
Resistance 10K
3
2.
Capacitor 10nF
3
3.
Pot 2.2M
1
4.
Resistance 50K
1
5.
IC741
1
Phase Shift Oscillator :
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The phase shift oscillator produces positive feedback by using an inverting amplifier
and adding another 180° of phase shift with the three high-pass filter circuits. It
produces this 180° phase shift for only one frequency.
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First question that comes into out mind is how dose this signal generate? The
operation of the RC Phase Shift Oscillator can be explained as follows. The starting
voltage is provided by noise, which is produced due to random motion of electrons in
resistors used in the circuit. The noise voltage contains almost all the sinusoidal
frequencies. This low amplitude noise voltage gets amplified and appears at the
output terminals. The amplified noise drives the feedback network which is the phase
shift network. Because of this the feedback voltage is maximum at a particular
frequency, which in turn represents the frequency of oscillation. Furthermore, the
phase shift required for positive feedback is correct at this frequency only. The
voltage gain of the amplifier with positive feedback is given by the above equation we
can see that if Aβ =1 A f = ∞ The gain becomes infinity means that there is output
without any input. i.e. the amplifier becomes an oscillator. This condition Aβ =1 is
known as the Barkhausen criterion of oscillation. Thus the output contains only a
single sinusoidal frequency. In the beginning, as the oscillator is switched on, the loop
gain A is greater than unity. The oscillations build up. Once a suitable level is
reached the gain of the amplifier decreases, and the value of the loop gain decreases to
unity. So the constant level oscillations are maintained. Satisfying the above
conditions of oscillation the value of R and C for the phase shift network is selected
such that each RC combination produces a phase shift of 60°. Thus the total phase
shift produced by the three RC networks is 180°. Therefore at the specific frequency o
the total phase shift from the base of the transistor around the circuit and back to the
base is 360° thereby satisfying Barkhausen criterion. The mathematics for calculating
the oscillation frequency and oscillation criteria for this circuit are surprisingly
complex, due to each R-C stage loading the previous ones. The calculations are
greatly simplified by setting all the resistors (except the negative feedback resistor)
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and all the capacitors to the same values. In the diagram, if R1 = R2 = R3 = R, and C1
= C2 = C3 = C, then:
foscillation =
1
2π RC 6
………..…….…………..(1)
1
In order that Aβ < 1
29
it is required that the amplifier gain Aβ > 29 for oscillator operation. Figure 72
At this frequency, the feedback factor of the network is β =
And for
β=
1
29
A = 29
Hence
Rfeedback = 29R
Figure 72
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shows a phase shift oscillator, which consists of an Op-Amp as the amplifying stage
and three RC cascaded networks as the feedback voltage from the output back to the
input of the amplifier. The Op-Amp is used in the inverting mode; therefore, any
signal that appears at the inverting terminal is shifted by 180° at the output. An
additional 180° phase shift required for oscillation is provided by the cascaded RC
networks. Thus the total phase shift around the loop is 360° (or 0°). The most
common way of achieving this kind of filter is using 3 cascaded resistor-capacitor
filters, which produce no phase shift at one end of the frequency scale, and a phase
shift of 270° at the other end
......................... (2)
..........................(3)
A phase-shift oscillator can be built with one Op-Amp is shown above the normal
assumption is that the phase shift sections are independent of each other. Then
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Equation is written
AB = A [l / RCs + 1]3
The loop phase is -180° when the phase shift of each section is -60° and this occurs
when ω = 1.732 / 2πRC because the tangent of 60° = 1.732. The oscillation frequency
with the component values shown in figure 73 is slightly different than the calculated
oscillation frequency. These discrepancies are partially due to the component
variations, but the biggest contributing factor is the incorrect assumption that the RC
section does not load each other. This circuit configuration was very popular when
active components were large and expensive, but now Op-Amps are inexpensive and
small and come four in a package, so the single Op-Amp phase-shift oscillator is
losing popularity.
Circuit diagram :
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Phase Shift Oscillator
Figure 73
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Procedure :
To observe the working of Phase Shift Oscillator
1.
Calculate the value of frequency for given value of R & C by equation 1.
2.
Connect the Circuit as shown in the circuit diagram.
3.
Take precaution while connecting the supply to IC741 i.e. connect positive
supply (+12V) to pin no. 7 of IC and negative supply (-12V) to pin no. 4 of
IC741
4.
Connect the CR combination as shown in figure 73.
5.
Rotate the potentiometer and set it at 29 times of the value of R i.e. RF = 290K
if R =10K.
6.
Connect the oscilloscope CH I probe at terminal 1 or ‘Vout’ and ground to
observe the output Vout.
7.
If the output shows some distortion or imperfection vary the pot P till the
perfect wave occurs.
8.
Note the output frequency and verify it with measured output frequency.
9.
Connect the Oscilloscope CH II probe at terminal 2 to observe the phase shift
between output and 1st RC combination output, V1OUT.
10.
Disconnect the Oscilloscope CH II probe and connect it terminal 3 to observe
the phase shift between output and 2nd RC combination V2OUT.
11.
Now connect the CH II probe and connect it to terminal 4 and observe the
output wave form at 3rd RC combination, V3OUT.
12.
Check the phase difference between all these terminals, by connecting them
with Oscilloscope CH I and CH II respectively.
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Note : To measure the phase shift take only one pair of node and antinode of the
signal, count the blocks it take, (you can also decrease the frequency for more
blocks), divide the 360 by number of blocks. That will give you the estimation of how
much degree are there in one block. It is to make your calculation easy.
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Observation Table :
S. No.
Frequency
Phase shift
Φ
(Vout - V1out)
Phase
shift
Φ
(Vout –
V2out)
Phase
shift
Φ
(Vout –
V3out)
Phase
shift
Φ
(V1out –
V2out)
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Conclusion :
RC
The phase shift between is Vout - V1OUT = 60°.
2.
The phase shift between is Vout – V2OUT = 120°
3.
The phase shift between is Vout – v3out = 180°, but the output V3out will be just a
spike.
4.
The phase shift between is V1out – V2out = 60°.
5.
The value of the feedback resistance is 29 times higher then that of R8, thus the
value of gain is 29.
6.
Output voltage is equal to Vsat = Vsupply -10%
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Experiment 21
Objective :
Study of operation of Logic Gates
Equipments Needed :
Components
Quantity
1.
IC7408 2 input AND Gate.
1
2.
IC7432 2 input OR Gate.
1
3.
IC7400 2 input NAND Gate.
1
4.
IC7402 2 input NOR Gate
1
5.
IC74136 2 input EX-OR Gate
1
6.
IC7404 NOT Gate.
1
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Logic Gate is a digital circuit with one or more input but only one output. AND, OR,
NAND, NOR, NOT, EX-OR Gates are some examples of Logic Gates. Each Gate has
one or two binary input variable designated by X & Y and one binary output variable
Z. The logic diagram and Truth Table of Logic Gates is shown in experiment section.
OR Gate : The OR gate has two or more than two inputs and one output. This
operation is represented by a plus sign e.g. X +Y= Z is read X or Y is equal to Z
meaning that Z=1 if X=1 or if Y=1 or if both X=1 & Y=l. If both X=0 & Y=0
then Z=0.The output voltage of OR Gate is high if any or all of the input
voltages are high that is +5 V or 1 (TTL level is used). Logic equation is Z = X
+ Y (X & Y are inputs & Z is output.)
2.
AND Gate : It has two or more than two inputs. This operation is represented
by a dot or by absence of an operator eg. X.Y=Z or XY=Z is read X AND Y is
equal to Z. The logical operation AND is interpreted to mean that Z=l if and
only if X=l and Y=l otherwise Z=0
3.
NOT Gate : It has one input and one output. This operation is represented by
prime (bar). For example X= Z is read X not equal to Z" meaning that Z is what
X is not. In other words if X=l, then Z=0 but if X= 0 then Z=l.
4.
NAND Gate : It has two inputs & one output. NAND function is compliment of
AND function. The bubble on output represents inversion after AND ing. The
logic equation is Z = (X.Y)'. The output is high if any of the input is low.
5.
NOR Gate : It has two or more than two inputs and one output. The NOR
function is complement of OR function .The output is low if any input is high.
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6.
EX-OR Gate : Exclusive OR Gate has two inputs and one output. The output is
high if and only if the two inputs i.e. X & Y are different ie. If X=l & Y=0 or
X=0 & Y=l otherwise output will be low.
The logic equation is XY' + X'Y = X⊕Y=Z.
Note : Refer Truth Tables and logic diagrams shown in experiment section.
Logic Diagrams and IC Pin diagrams :
on
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Figure 74
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OR Gate :
Truth table :
(Logic 1 = +5V & Logic 0 = GND)
X
Y
Z
0
0
0
0
1
1
1
0
1
1
1
.
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1
Circuit Diagram :
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Figure 75
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Procedure :
OR Gate
1.
Connect +5V to pin no. 14 of IC7432 and connect ground to pin no.7 (Refer IC
pin diagram as shown in the figure 75)
2.
Connect the input terminal or input pin of IC7432 (pin no. 1 & 2) with any two
of the 8 bit data switches.
3.
Connect output of OR Gate i.e. pin no. 3 to input of logic probe or 8 bit LED
display.
4.
Apply 0 (0V) to pin no. 1 and 2 of IC7432 shown in the figure 75 as per Truth
Table.
5.
Observe the output coming at 8 bit LED display or Logic probe.
6.
If the output is 0 (0V) the LED will not glow or if you have connected the Logic
probe it will display “L” for low.
7.
Apply 0 to pin no. 1 (0V) and 1 to pin no. 2 (5V) and observe the output.
8.
LED should glow or Logic probe will show “H” for high output
9.
Apply 1 to pin no. 1 (5V) and 0 to pin no. 2 (0V) and observe the output.
10.
LED should glow or Logic probe will show “H” for high output
11.
Apply 1 to pin no. 1 (5V) and 1 to pin no. 2 (5V) and observe the output.
12.
LED should glow or Logic probe will show “H” for high output
13.
Note all the output coming for these combinations of input and verify it by the
truth table.
Observation Table :
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Input1
Input 2
Output
X
Y
Z
0
0
1
1
0
1
1
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AND Gate :
Figure 76
Logic diagram & Truth table :
(Logic 1 = +5 V & Logic 0 = GND)
Y
Z
0
0
0
0
1
0
1
0
0
1
1
1
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Circuit diagram :
X
Figure 77
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Procedure :
AND Gate
1.
Connect +5V to pin no. 14 of IC 7408 and connect ground to pin no.7. (refer IC
pin diagram as shown in figure 77)
2.
Connect the input terminal or input pin of IC 7408 (pin no. 1 & 2) with any two
of the 8 bit data switches
3.
Connect output of AND Gate i.e. pin no. 3 to input of logic probe or 8 bit LED
display.
4.
Apply 0 (0V) to pin no. 1 and 2 of IC7408 shown in the figure 77 as per Truth
Table.
5.
Observe the output coming at 8 bit LED display or Logic probe.
6.
If the output is 0 (0V) the LED will not glow or if you have connected the Logic
probe it will display “L” for low.
7.
Apply 0 to pin no. 1 (0V) and 1 to pin no. 2 (5V) and observe the output.
8.
LED shouldn’t glow or Logic probe will show “L” for high output
9.
Apply 1 to pin no. 1 (5V) and 0 to pin no. 2 (0V) and observe the output.
10.
LED shouldn’t glow or Logic probe will show “L” for high output
11.
Apply 1 to pin no. 1 (5V) and 1 to pin no. 2 (5V) and observe the output.
12.
LED should glow or Logic probe will show “H” for high output
13.
Note all the output coming for these combinations of input and verify it by the
truth table.
Observation Table :
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Input1
Input 2
Output
X
Y
Z
0
0
1
1
0
1
1
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NOT Gate :
Figure 78
Logic diagram & Truth table :
(Logic 1 = +5V & Logic 0 = GND)
X
Z
0
1
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1
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Circuit diagram :
0
Figure 79
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Procedure :
Not Gate
1.
Connect +5V to pin no. 14 of IC7404 and connect ground to pin no.7. (refer IC
pin diagram as shown in the figure 79)
2.
Connect the input terminal or input pin of IC7404 (pin no.1) with any one of the
8 bit data switch
3.
Connect output of NOT Gate i.e. pin no. 2 to input of logic probe or 8 bit LED
display.
4.
Apply 0 (0V) to pin no.1 of IC 7404 shown in the figure 79 as per Truth Table.
5.
Observe the output coming at 8 bit LED display or Logic probe.
6.
The output is 1 (5V) so the LED will glow or if you have connected the Logic
probe it will display “H” for High.
7.
Apply 1 to pin no. 1 (5V) and observe the output.
8.
LED shouldn’t glow or Logic probe will show “L” for high output
9.
Note all the output coming for these combinations of input and verify it by the
truth table.
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Observation Table :
X
0
1
Z
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NOR Gate :
Figure 80
Logic diagram & Truth table :
(Logic 1 = +5V & Logic 0 = GND)
Y
Z
0
0
1
0
1
0
1
0
0
1
1
0
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Circuit diagram :
X
Figure 81
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Procedure :
NOR Gate
1.
Connect +5 V to pin no. 14 of IC7402 and connect ground to pin no.7. (refer IC
pin diagram as shown in the figure 81)
2.
Connect the input terminal or input pin of IC7402 (pin no. 2 & 3) with any two
of the 8 bit data switches
3.
Connect output of NOR Gate i.e. pin no. 1 to input of logic probe or 8 bit LED
display.
4.
Apply 0 (0V) to pin no. 2 and 3 of IC7408 shown in the figure 81 as per Truth
Table.
5.
Observe the output coming at 8 bit LED display or Logic probe.
6.
If the output is 1 (5V) the LED will not glow or if you have connected the Logic
probe it will display “H” for High.
7.
Apply 0 to pin no. 2 (0V) and 1 to pin no. 3 (5V) and observe the output.
8.
LED shouldn’t glow or Logic probe will show “L” for Low output
9.
Apply 1 to pin no. 2 (5V) and 0 to pin no. 3 (0V) and observe the output.
10.
LED shouldn’t glow or Logic probe will show “L” for Low output
11.
Apply 1 to pin no. 2 (5V) and 1 to pin no. 3 (5V) and observe the output.
12.
LED shouldn’t glow or Logic probe will show “L” for Low output
13.
Note all the output coming for these combinations of input and verify it by the
truth table.
Observation Table :
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Input1
Input2
Output
X
Y
Z
0
0
1
1
0
1
1
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NAND Gate :
Figure 82
Logic diagram & Truth table :
(Logic 1 = +5V & Logic 0 = GND)
Y
Z
0
0
1
0
1
1
1
0
1
1
1
0
Circuit diagram :
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X
Figure 83
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Procedure :
NAND Gate
1.
Connect +5V to pin no. 14 of IC7400 and connect ground to pin no.7. (refer IC
pin diagram as shown in the figure 83)
2.
Connect the input terminal or input pin of IC7400 (pin no. 1 & 2) with any two
of the 8 bit data switches
3.
Connect output of NAND Gate i.e. pin no. 3 to input of logic probe or 8 bit LED
display.
4.
Apply 0 (0V) to pin no. 1 and 2 of IC 7400 shown in the figure 83 as per Truth
Table.
5.
Observe the output coming at 8 bit LED display or Logic probe.
6.
If the output is 1 (5V) the LED will glow or if you have connected the Logic
probe it will display “H” for High and if output is 0 the LED will not glow or if
connected the logic probe it will display “L”.
7.
Apply 0 to pin no. 1 (0V) and 1 to pin no. 2 (5V) and observe the output.
8.
LED should glow or Logic probe will show “H” for high output
9.
Apply 1 to pin no. 1 (5V) and 0 to pin no 2 (0V) and observe the output.
10.
LED should glow or Logic probe will show “H” for high output
11.
Apply 1 to pin no. 1 (5V) and 1 to pin no. 2 (5V) and observe the output.
12.
LED shouldn’t glow or Logic probe will show “L” for low output
13.
Note all the output coming for these combinations of input and verify it by the
truth table.
Observation Table :
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Input2
Output
X
Y
Z
0
0
0
1
1
0
1
1
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EX-OR Gate :
Figure 84
Logic diagram & Truth table :
(Logic 1 = +5 V & Logic 0 = GND)
0
1
1
0
0
1
1
0
1
1
0
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X
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Circuit diagram :
Figure 85
Procedure :
EX-OR Gate
1.
Connect +5V to pin no. 14 of IC74136 and connect ground to pin no.7. (refer IC
pin diagram as shown in the figure 85 )
2.
Connect the input terminal or input pin of IC74136 (pin no. 1 & 2) with any two
of the 8 bit data switches
3.
Connect output of EX-OR Gate i.e. pin no. 3 to input of logic probe or 8 bit
LED display.
4.
Apply 0 (0V) to pin no. 1 and 2 of IC7400 shown in the figure 85 as per Truth
Table.
5.
Observe the output coming at 8 bit LED display or Logic probe.
6.
If the output is 0 (0V) the LED won’t glow or if you have connected the Logic
probe it will display “L” for low output.
7.
Apply 0 to pin no. 1 (0V) and 1 to pin no. 2 (5V) and observe the output.
8.
LED should glow or Logic probe will show “H” for high output
9.
Apply 1 to pin no. 1 (5V) and 0 to pin no 2 (0V) and observe the output.
10.
LED should glow or Logic probe will show “H” for high output
11.
Apply 1 to pin no. 1 (5V) and 1 to pin no. 2 (5V) and observe the output.
12.
LED shouldn’t glow or Logic probe will show “L” for low output
13.
Note all the output coming for these combinations of input and verify it by the
truth table.
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Observation table :
Input1
Input2
Output
X
Y
Z
0
0
0
1
1
0
1
1
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Experiment 22
Objective :
Study of Binary Adders.
A.
Half Adder
B.
Full Adder
Equipments Needed :
Components
Quantity
1.
IC7408 2 input AND Gate.
1
2.
IC74136 2 input EX-OR Gate.
1
Half Adder :
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The combinational circuit that performs the addition of two bits is called a Half
Adder. This circuit has two binary inputs and two binary outputs. The input variable
X, Y designate the augends and addend bits, the output variables Sh, Ch produces the
sum and carry. The logic diagram and Truth Table are shown in experiment section.
The Boolean equation is
Sh = X’.Y +X.Y’= X⊕Y
Ch = X.Y
Logic diagram :
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Figure 86
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Truth Table : (Logic 1 =+5V, Logic 0 = GND)
Input 1
Input 2
Carry
Sum
X
Y
C
S
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
Circuit diagram :
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Figure 87
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Procedure :
Make connections as shown in the figure 87.
2.
Connect +5V to pin no. 14 and ground to pin no.7 of IC7408 and IC74136. (See
IC Pin diagram as shown in the figure 87)
3.
Connect the input terminal or input pin of IC7408 (pin no. 1 & 2) with input pin
of IC74136 (pin no 1 & 2 ) and now connect them with any two of the 8 bit data
switches
4.
Connect output of EX-OR Gate i.e. pin no. 3 to input of logic probe or 8 bit
LED display.
5.
This will give the output for Summation.
6.
Connect output of AND Gate i.e. pin no. 3 to input of logic probe or 8 bit LED
display.
7.
This will give the output for carry
8.
Apply 0 (0V) to pin no. 1 and 2 of IC74136 (same will apply at the IC7408)
shown in figure as per Truth Table.
9.
Observe the output coming at 8 bit LED display or Logic probe.
10.
If the output is 0 (0V) the LED will not glow or if you have connected the Logic
probe it will display “L” for low output
11.
Apply the 01, 10, 11 combination to pin no. 1 and pin no. 2 respectively and
observe the output.
12.
LED should glow or Logic probe will show “H” if the output is 1 or (5V high
output)
13.
Note all the output coming for these combinations of input and verify it by the
truth table.
Input 2
X
Y
0
0
0
1
1
0
1
1
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Carry
Sum
C
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Observation Table :
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Full Adder :
The circuit that performs the addition of three bits (two significant bits and a previous
carry) is called a full adder. It consists of three inputs X, Y, Z. Two of the input
variable, denoted by X and Y, represents the two significant bits to be added. The
third input, Z, represents the carry from the previous lower significant position. The
output Sf gives the value of the least significant bit of sum and Cf gives the output
carry. The logic diagram for 3-bit full adder is shown in experiment section. The
Boolean equation is
Sf = X’Y’Z + X’YZ’+ XY’Z’+ XYZ
Cf = X.Y + X.Z +Y.Z
Equipments Needed :
Component
Quantity
1.
IC7408 2 input AND Gate
1
2.
IC7432 2 input OR Gate
1
3.
IC74136 2 input EX-OR Gate
1
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Logic diagram :
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Figure 88
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Truth Table : (Logic 1 =+5 V, Logic 0 = GND)
Input 2
Input 3
Output
Carry
Sum
X
Y
Ci
Co
S
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
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Input 1
Circuit diagram :
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Figure 89
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Procedure :
Make connections as shown in the figure 89.
2.
Connect +5V to pin no. 14 and ground to pin no.7 of IC7408, IC7432 and IC
74136. (See IC Pin diagram as shown in the figure 89)
3.
For Input1 and Input2 i.e. X&Y; connect the input terminal or input pin of IC
74136 (pin no. 1 & 2) with any two of the 8 bit data switches.
4.
Also connect the same pins with input pin of IC7408 (pin no 1 & 2) for first
carry.
5.
The output of first sum will come at IC74136 pin no.3 feed this output back to
IC74136 input (pin no. 4) for second summation.
6.
Also connect it with AND Gate’s pin no.4 for carry input of second carry
generator
7.
For Input 3 i.e. Ci; connect an 8 bit data switch with IC74136 input (pin no. 5).
8.
Also connect it with AND gates pin no. 5 for carry input of second carry
generator
9.
Connect output of EX-OR Gate (IC74136) i.e. pin no. 6 to input of logic probe
or 8 bit LED display.
10.
This will give the output for Full adder.
11.
Second carry will appear at out put ( pin no. 6) of AND gate
12.
To Get a full carry connect the IC7408 pin no. 3 & 6 with the input terminal of
IC7432 (pin no. 1 & pin no.2 respectively)
13.
Connect the output terminal of IC7432 (pin no. 3) at input of logic probe or 8
bit LED display.
14.
This will give the output for Full carry
15.
Apply 0 (0V) to pin no. 1, 2 and 5 of IC74136 shown in the figure 89 as per
Truth Table.
16.
Observe the output coming at 8 bit LED display or Logic probe.
17.
If the output is 0 (0V) the LED will not glow or if you have connected the Logic
probe it will display “L” for low output
18.
LED should glow or Logic probe will show “H” if the output is 1 or (5V high
output)
19.
Apply the all other combination given in truth to pin no.1, pin no.2 and pin no.5
respectively and observe the output.
20.
Note all the output coming for these combinations of input and verify it by the
truth table.
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Observation Table :
Input 1
Input 2
Input 3
Output
Carry
Sum
X
Y
Ci
Co
S
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
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1
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Experiment 23
Objective :
Study of 2 Bit Binary Subtracter (Half Subtracter)
Equipments Needed :
Component
Quantity
1.
IC74136 2 input EX-OR Gate.
1
2.
IC7408 2 input AND Gate
1
3.
IC7404 NOT Gate.
1
Half subtracter : A half subtracter is a combinational circuit that subtracts two bits
and produces their difference. It has two inputs X, Y. X is minuend and Y is
subtrahend. The output bits are designated by Bh, Dh. Dh is difference bit and Bh is
borrow bit (generates the binary signal that informs the next stage that a 1 has been
borrowed). The logic diagram and Truth Table for 2 bit half subtracter is shown in
experiment section.
The Logic equation is
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Dh = X’Y+XY’= X⊕Y
Bh = X.Y
Logic diagram :
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Figure 90
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Truth Table : (Logic 1 =+5 V, Logic 0 = Gnd)
Input 1
Input 2
Borrow
Difference
X
Y
B
D
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
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Figure 91
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Circuit diagram :
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Procedure :
Make connections as shown in the figure 91.
2.
Connect +5V to pin no. 14 and ground to pin no.7 of IC7408, IC7404 and IC
74136. (See IC Pin diagram as shown in the figure 91.)
3.
Connect the input terminal or input pin of IC 74136 (pin no. 1 & 2) with any
two of the 8 bit data switches for Input 1 and Input 2 respectively
4.
Connect output of EX-OR Gate i.e. pin no. 3 of IC 74136 to input of logic
probe or 8 bit LED display.
5.
This will give the output for Difference.
6.
Also connect the Input1 at the input pin no.1 of AND Gate IC7408 for
‘Borrow’ input1.
7.
Connect the Input2 with NOT Gate IC7404 pin no.1. Connect the output of
inverted signal i.e. IC7404’s pin no. 2 with AND Gate pin no. 2.
8.
Connect output of AND Gate i.e. pin no. 3 to input of logic probe or 8 bit LED
display.
9.
This will give the output for ‘Borrow.’
10.
Apply 0 (0V) to pin no. 1 and 2 of IC74136 (same will apply at the IC7408
and IC7404 input pins respectively) shown in the figure 91 as per Truth Table.
11.
Observe the output coming at 8 bit LED display or Logic probe.
12.
If the output is 0 (0V) the LED will not glow or if you have connected the
Logic probe it will display “L” for low output
13.
LED should glow or Logic probe will show “H” if the output is 1 or (5V high
output)
14.
Apply the 01, 10, 11 combination to pin no. 1and pin no. 2 respectively and
observe the output.
15.
Note all the output coming for these combinations of input and verify it by the
truth table.
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Observation Table :
Input 1
Input 2
Borrow
Difference
X
Y
B
D
0
0
0
1
1
0
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1
1
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Experiment 24
Objective :
Study of Binary to Gray Code conversion
Equipments Needed :
Components
1.
Quantity
IC 74136 2 input EX-OR Gate
1
Code Conversion :
The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital system. It is
sometimes necessary to use the output of one system as the input to another. A
conversion circuit must be inserted between the two systems if each uses different
codes for the same information. Thus, a code converter is a circuit that makes the two
systems compatible even though each uses a different binary code.
on
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The binary number system is a system that uses only the digits 0 & 1 as codes. To
represent a group of 2 n distinct element in a binary code requires a minimum of n bits.
This is because it is possible to arrange n bits in 2n distinct ways. Although the
minimum number of bits required to code 2n distinct quantities is n, there is no
maximum number of bits that may be used for binary code. For example, a group of
four distinct quantities can be represented by a two bit code, with each quantity
assigned one of the following bit combinations: 00, 01, 10, and 11. A group of eight
elements requires a three bit code, with each element assigned to one and only one of
the following 000, 001, 010, 011, 100, 101, 110, and 111. (Refer table).
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Gray code (reflected code) : Gray code is shown in Table. Number in the gray code
changes by only one bit as it proceeds from one number to the next. For example in
going from decimal 7 to 8, the gray code number changes from 0100 to 1100; these
number differ only in MSB. So it is with the entire gray code; every number differs by
only one bit from the preceding number. The logic diagram for binary code to gray
code converter and gray code to binary code converter is shown in figure 92.
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Table.
Gray Code
Binary
0
0000
0000
1
0001
0001
2
0011
0010
3
0010
0011
4
0110
0100
5
0111
0101
6
0101
0110
7
0100
0111
8
1100
1000
9
1101
1001
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Decimal
The logic equations for Binary to gray code conversion :
G0 = B0 ⊕ B1
G1 = B1 ⊕ B2
G2 = B2 ⊕ B3
Logic diagram :
Binary to Gray Code
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G3 = B3
Figure 92
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Truth Table :
(Logic 1 = +5V & Logic 0= GND)
Decimal
B3
B2
B1
B0
Decimal
G3
G2
G1
G1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
2
0
0
1
0
2
0
0
1
1
3
0
0
1
1
3
0
0
1
0
4
0
1
0
0
4
0
1
1
0
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5
1
0
1
5
0
1
1
1
0
1
1
0
6
0
1
0
1
7
0
1
8
1
0
9
1
0
10
1
11
6
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0
1
7
0
1
0
0
0
0
8
1
1
0
0
0
1
9
1
1
0
1
0
1
0
1
0
1
1
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
14
15
1
1
1
1
15
10
1
1
1
1
11
1
1
1
0
12
1
0
1
0
13
1
0
1
1
1
0
0
1
1
0
0
0
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Circuit diagram :
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Procedure :
Figure 93
Make connections as shown in the figure 93.
2.
Connect +5V to pin no. 14 and ground to pin no.7 of IC74136.
3.
For B0 : Connect 8 bit data switch with IC74136 pin no. 1
4.
For G0 : Connect LED no. ‘0’ of 8 bit LED display with IC74136 pin no. 3
5.
For B1 : Connect 8 bit data switch with IC74136 pin no.4 also connect this to
IC74136 pin no.2
6.
For G1 : Connect LED no. ‘1’ of 8 bit LED display with IC74136 pin no. 6
7.
For B2 : Connect 8 bit data switch with IC74136 pin no.9 also connect this to
IC74136 pin no.5
8.
For G2 : Connect LED no. ‘2’ of 8 bit LED display with IC74136 pin no. 8
9.
For B3 : Connect 8 bit data switch with IC74136 pin no.10
10.
For G3 : Also Connect B3 directly with LED no.3 of 8 Bit LED display
11.
Apply any of the given combination as per Truth Table.
12.
Observe the output coming at 8 bit LED display for G0 to G3.
13.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow
14.
Note all the output coming for these combinations of input and verify it by the
truth table.
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Observation table :
B3
B2
B1
B0
Decimal
0
0
0
0
0
0
1
0
0
0
1
1
2
0
0
1
0
2
3
0
0
1
1
3
4
0
1
0
0
4
5
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
8
1
0
0
0
8
9
1
0
0
1
9
10
1
0
1
0
10
11
1
0
1
1
12
1
1
0
0
13
1
1
0
1
14
1
1
1
0
14
15
1
1
1
1
15
6
G3
G2
G1
G1
11
12
13
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Decimal
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Experiment 25
Objective :
Study of Gray code to Binary code conversions
Equipments Needed :
Component
1.
Quantity
IC74136 2 input EX-OR Gate
1
Gray to binary code conversion :
What happen when we have Gray code and want to convert it in binary codes? Will
the same method work? No! There is another way to convert the Gray code to binary
codes.
Equations for conversions
B0 = G3 ⊕ G2 ⊕ G1 ⊕ G0
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B1 = G3 ⊕ G2 ⊕ G1
B2 = G3 ⊕ G2
B3 = G3
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Gray to Binary Code
Figure 94
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Truth Table : (Logic 1 =+5V, Logic 0 = GND)
Gray Code
Binary Code
G2
G1
G0
B3
B2
B1
B0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
0
0
0
1
0
1
1
0
1
1
1
1
0
0
1
1
0
1
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G3
1
1
0
1
1
1
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Circuit diagram :
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Procedure :
Figure 95
Make connections as shown in the figure 95.
2.
Connect +5V to pin no. 14 and ground to pin no.7 of IC74136.
3.
For G0 : Connect 8 bit data switch with IC74136 pin no. 1
4.
For B0 : Connect LED no. ‘0’ of 8 bit LED display with IC74136 pin no. 3
5.
For G1 : Connect 8 bit data switch with IC74136 pin no.4
6.
For B1 : Connect LED no. ‘1’ of 8 bit LED display with IC74136 pin no. 6 also
connect this with IC74136 pin no. 2
7.
For G2 : Connect 8 bit data switch with IC74136 pin no.9
8.
For B2 : Connect LED no. ‘2’ of 8 bit LED display with IC74136 pin no. 8 also
connect this with IC74136 pin no.5
9.
For G3 : Connect 8 bit data switch with IC74136 pin no.10
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10.
For B3 : Also Connect B3 directly with LED no.3 of 8 Bit LED display
11.
Apply any of the given combination as per Truth Table.
12.
Observe the output coming at 8 bit LED display for G0 to G3.
13.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow
14.
Note all the output coming for these combinations of input and verify it by the
truth table.
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Observation table :
Gray Code
Binary Code
G2
G1
G0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
0
B3
B2
B1
B0
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G3
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Experiment 26
Objective :
Study of Binary to Excess -3 Code conversion
Equipments Needed :
Components
Quantity
1.
IC7432 2 input OR Gate.
1
2.
IC7408 2 input AND Gate
1
3.
IC7404 Not Gate
1
Code Conversion :
The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital system. It is
sometimes necessary to use the output of one system as the input to another. A
conversion circuit must be inserted between the two systems if each uses different
code for the same information. Thus, a code converter is a circuit that makes the two
systems compatible even though each uses a different binary code.
-c
BCD is an abbreviation for Binary-Coded Decimal. Binary codes for decimal digits
require a minimum of four bits. The BCD code expresses each digit in a decimal
number by its nibble equivalent. Weights are assigned to binary bits according to their
positions. The weights in the BCD codes are 8, 4, 2, and 1.
on
For example, the bit assignment 0110 can be interpreted by the weights to represent
the decimal digit 6 because 0 × 8 + 1 × 4 + 1 × 2 + 0 × l = 6. Table1 shows BCD code.
The excess-3 code is an important 4-bit code used with BCD numbers. To convert any
decimal number in to its excess-3 form, add 3 to each decimal digit, and then convert
the sum to a BCD number. To convert decimal 5 to an excess-3 number, first add 3 to
decimal digit:
su
5
+3
8
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Now, convert the sum to BCD form
8 = 1000
So, 1000 in the excess-3 code stands for decimal 5.
To convert BCD to Excess-3, add 0011 to BCD code. Refer figure 1 and table 1
equations for Logic Diagram shown in experiment section.
E0 = B0’ (’ represents complement)
E1 = B0.B1+ (B0+Bl) ’
E2 = B2’ (B0+B1) + B2 (B0+B1) ’
E3 = B3+B2 (B0+B1)
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Table 1 :
BCD
Excess-3
0
0000
0011
1
0001
0100
2
0010
0101
3
0011
0110
4
0100
0111
5
0101
1000
6
0110
1001
7
0111
1010
8
1000
1011
9
1001
1100
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Decimal
Logic diagram :
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Figure 96
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Table 2 :
Decimal
B3
B2
B1
B0
E3
E2
E1
E0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
1
0
0
2
0
0
1
0
0
1
0
1
3
0
0
1
1
0
1
1
0
5
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4
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
0
8
1
0
0
9
1
0
0
0
1
0
1
1
1
1
1
0
0
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6
Table 2
B3, B2, B1, B0 are Binary codes (B0 is LSB)
E3, E2, E1, E0 are Excess-3 code (E0 is LSB)
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Circuit diagram :
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Procedure :
Figure 97
Make connection as shown in the figure 97. (Refer pin diagram of ICs as shown
in the figure 97)
2.
Connect +5V to pin no. 14 and ground to pin no. 7 of ICs.
3.
Connect 0 (0V) to binary inputs B3 B2 B1 B0 as per Truth Table.
4.
Switch ON the instrument.
5.
Observe outputs on 8 bits LED display.
6.
Repeat steps 3, 5 for other input combinations.
7.
Verify Truth Table.
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Truth Table : (Logic 1 =+5V, Logic 0 = Gnd)
B2
B1
B0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
1
1
0
0
E3
E2
El
E0
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B3
0
1
1
0
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0
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Experiment 27
Objective :
Study of Characteristics of various types of Flip-Flops
Equipments Needed :
Component
Quantity
1.
IC7408 2 input AND Gate
2
2.
IC7411 3 input AND Gate
2
3.
IC7400 2 input NAND Gate
2
4.
IC7402 2 input NOR Gate
2
Flip-flops are binary cells capable of storing one bit of information. A Flip-flop has
two outputs, one for the normal value and one for complement value of the bit stored
in it. A flip-flop circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit) until directed by an input signal to switch states.
Clocked RS Flip-flop :
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Clocked RS Flip-flop is shown in the figure 98, it consists of two NOR Gates and two
AND Gates. The input is S and R are set and reset input and output Q and Q' are
normal and complement output. The input CP is input for giving clock pulse. Flipflop will change state only when CP goes from 0 to 1.
R-S Flip-flop
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The output of two AND Gates remain at 0 as long as the clock pulse CP is 0,
regardless of the S and R input values. When the clock pulse goes to logic high level
i.e. 1, information from the S and R is allowed to reach the basic flip-flop. The set
state is reached with S = 1, R = 0, and CP = 1. (for set state, Q = 1 and for reset state,
Q = O ) To change to the clear state, the inputs must be S = 0, R = 1, CP = 1. With
both S = 1 and R = 1, the occurrence of a clock pulse causes both outputs to
momentarily go to 0. When the pulse is removed, the state of flip-flop is
indeterminate, i.e., either state may result, depending on whether the set or the reset
input of the basic flip-flop remains an 1 longer before the transition to 0 at the end of
the pulse. The characteristics table is shown in experiment section along with logic
diagram.
Figure 98
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Truth Table for R-S Flip-flop :
(Q=Present State, Q (t+1) = Next state)
CP
Q
S
R
Q (t +1)
0 →1
0
0
0
0
0 →1
0
0
1
0
0 →1
0
1
0
1
0 →1
0
1
1
Indeterminate
0 →1
1
0
0
1
0 →1
1
0
1
0
1
1
0
1
1
1
1
Indeterminate
Transition
0 →1
Circuit diagram :
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0 →1
Figure 99
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Procedure :
Make connections as shown in the figure 99.
2.
Connect +5V to pin no. 14 and ground to pin no.7 of IC7408 & IC7402.
3.
For R : Connect 8 bit data switch with I C7408 pin no. 1
4.
For S : Connect 8 bit data switch with IC7408 pin no.5
5.
For Clock : Short the IC7408 pin no 2 & 4 and connect them to ‘TTL output’
socket for clock pulses.
6.
Connect the IC7408 pin no.3 with IC7402’s pin no. 2
7.
Connect IC7402 pin no.3 with pin no. 4 of IC 7402.
8.
Now connect LED no. ‘0’ of 8 bit LED display with IC7402 pin no. 4 For Q’
9.
Connect the IC7408 pin no.6 with IC7402 pin no.6
10.
Connect IC7402 pin no.5 with pin no.1 of IC 7402.
11.
Now connect LED no. ‘1’ of 8 bit LED display with IC7402 pin no.1 For Q
12.
Apply any of the given combination as per Truth Table.
13.
Observe the output coming at 8 bit LED display for Q and Q’
14.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow
15.
Note all the output coming for these combinations of input and verify it by the
truth table.
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1.
Note : Q and Q’ are the same conventions.
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Observation Table :
Truth Table : (Logic 1 =+5 V, Logic 0 = GND)
Clocked RS Flip Flop
Input1
Input2
Next State
Q(t)
S
R
Q( t +1)
0
0
0
0
0
0
1
0
0
1
0
1
1
1
Indeterminate
0
0
1
0
1
1
1
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Present state
0
1
0
1
0
1
1
1
Indeterminate
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D Flip-flop :
The logic symbol and characteristics table for D flip-flop is shown in figure 100. It
has only one data input (D) and clock input (CP). The outputs are labeled Q and Q’.
The data (0 or 1) at the input 0 is delayed one clock pulse from getting to output Q.
SD and CD are active low input (Negative edge trigger) to set and reset the flip-flop
i.e. these inputs will be effective when logic 0 is applied. A D Flip flop is a bistable
circuit whose 0 input is transferred to the output after a clock pulse is received.
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Pin configuration of D Flip-flop
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Figure 100
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D Flip-flop
Figure 101
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As long as the clock input is at 0, Gates 3, 4 have a 1 in their outputs, regardless of the
value of the other inputs. The D input is sampled during the occurrence of a clock
pulse (CP=1). If it is 1, the output of Gate 3 goes to 0, switching the flip-flop to the set
state (unless it was already set). If it is a 0 the output of Gate 4 goes to 0, switching
the flip-flop to the clear state.
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Truth table of D Flip Flop :
Q
D
Q( t + 1)
1→ 0
0
0
0
1→ 0
0
1
1
1→ 0
1
0
0
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CP
1
1
Transition
1
1→ 0
Circuit diagram :
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Figure 102
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Procedure :
1.
Make connections as shown in the figure 102.
2.
Connect +5V to pin no. 5 and ground to pin no.12 of IC7475.
3.
For D : Connect 8 bit data switch with I C7475 pin no.2
4.
For Clock : Connect the IC7475 pin no.4 or 13 to ‘TTL output’ socket for clock
pulses.
5.
Now connect LED no. ‘0’ of 8 bit LED display with IC7475 pin no. 1 For Q’
6.
Now connect LED no. ‘1’ of 8 bit LED display with IC7475 pin no.16 For Q
7.
Apply any of the given combination as per Truth Table.
8.
Observe the output coming at 8 bit LED display for Q and Q’
9.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow
10.
Note all the output coming for these combinations of input and verify it by the
truth table.
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Observation table :
Q(t)
0
Input
Next state
D
Q (t +l)
on
Present state
0
1
0
1
1
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J-K Flip-flop :
A J-K flip-flop is refinement of R-S flip-flop in that the indeterminate state of the RS
type is defined in the JK type. Inputs J, K is used to set and clear the flip-flop. When
both J, K are high simultaneously, the flip-flop switches to its complement state, that
is, if Q = 1, it switches to Q= 0, and vice versa. A CP signal which remains a 1 (While
J=K = 1) after the outputs have been complemented once will cause repeated and
continuous transitions of the output. To avoid this undesirable operation, the clock
pulse must have a time duration which is shorter than the propagation through the
flip-flop.
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J-K Flip-flop
Figure 103
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The JK flip-flop shown above behaves like an R-S flip-flop, except when both J and
K are 1, the clock pulse is transmitted through one AND Gates only- the one whose
input is connected to the flip-flop output which is presently 1. Thus, if Q = 1, the
output of the upper AND Gate become 1 upon application of a clock pulse, and the
flip-flop is cleared. If Q = 0, the output of lower AND Gate becomes a 1 and the flipflop is set. In either case, the output state of the flip-flop is complemented.
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Pin configuration of J-K Flip-flop
Figure 104
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Truth table of J-K Flip Flop :
CP
Q
J
K
Q (t +1)
1→ 0
0
0
0
0
1→ 0
0
0
1
0
1→ 0
0
1
0
1
1→ 0
0
1
1
1
1→ 0
1
0
0
1
1→ 0
1
0
1
0
1→ 0
1
1
0
1
1→ 0
1
1
1
0
Transition
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Circuit diagram :
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Figure 105
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Procedure :
Make connections as shown in the figure 105.
2.
Connect +5V to pin no.2, 3 and 5 (PRE, CLR and Vcc respectively) and ground
to pin no.13 of IC7476.
3.
For J : Connect 8 bit data switch with I C7476 pin no.4
4.
For Clock : Connect the IC7476 pin no.1 to ‘TTL output’ socket for clock
pulses.
5.
For K : Connect 8 bit data switch with I C7476 pin no.16
6.
Now connect LED no. ‘0’ of 8 bit LED display with IC7476 pin no. 14 For Q’
7.
Now connect LED no. ‘1’ of 8 bit LED display with IC7476 pin no.15 For Q
8.
Apply any of the given combination as per Truth Table.
9.
Observe the output coming at 8 bit LED display for Q to Q’.
10.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow
11.
Note all the output coming for these combinations of input and verify it by the
truth table.
-c
1.
Observation table :
Q(t)
0
Input
J
K
0
0
0
1
0
1
0
1
1
0
1
0
1
1
1
0
1
1
1
Q (t+ 1)
0
1
0
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Next State
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0
Input
on
Present state
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T Flip-flop :
The flip-flop is a single input version of the JK flip-flop .As shown in the figure 106;
the T flip-flop is obtained from a JK type if both inputs are tied together. The
designation T shows ability of flip-flop to toggle. Regardless of the present state of
the flip-flop, it assumes the complement state when the clock pulse occurs while input
T is logic 1.
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Figure 106
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T Flip-Flop
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Truth table of T Flip Flop :
CP Transition
Q
T
Q(t +1)
1→ 0
0
0
0
1→ 0
0
1
1
1→ 0
1
0
1
1→ 0
1
1
0
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Circuit diagram :
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Figure 107
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Procedure :
Make connections as shown in the figure 107.
2.
Connect +5V to pin no.2, 3 and 5 (PRE, CLR and Vcc respectively) and ground
to pin no.13 of IC7476.
3.
For T : Connect 8 bit data switch with IC7476 pin no.4 & also with pin no.16
4.
For Clock : Connect the IC7476 pin no.1 to ‘TTL output’ socket for clock
pulses.
5.
Now connect LED no. ‘0’ of 8 bit LED display with IC7476 pin no. 14 For Q’
6.
Now connect LED no. ‘1’ of 8 bit LED display with IC7476 pin no.15 For Q
7.
Apply any of the given combination as per Truth Table.
8.
Observe the output coming at 8 bit LED display for Q to Q’.
9.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED
will glow
10.
Note all the output coming for these combinations of input and verify it by the
truth table.
-c
1.
Observation table :
Truth Table : (Logic 1 =+5V, Logic 0 = GND)
Q(t)
on
Present state
Input
Next state
T
Q ( t+ 1)
0
1
1
0
1
1
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Experiment 28
Objective :
Study of Crystal Oscillator
Equipments Needed :
Components
Quantity
1.
Resistance 330 ohm
3
2.
Crystal 1MHz
1
3.
Capacitor
4.
0.01µFD
1
100 pF
1
IC7404 Hex Inverter
1
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A crystal oscillator is an electronic circuit that uses the mechanical resonance of a
vibrating crystal of piezoelectric material to create an electrical signal with a very
precise frequency. This frequency is commonly used to keep track of time (as in
quartz wristwatches), to provide a stable clock signal for digital integrated circuits,
and to stabilize frequencies for radio transmitters.
Using an amplifier and feedback, it is an especially accurate form of an electronic
oscillator. The crystal used therein is sometimes called a "timing crystal". On
schematic diagrams a crystal is labeled Y.
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Figure 108
The crystal oscillator circuit sustains oscillation by taking a voltage signal from the
quartz resonator, amplifying it, and feeding it back to the resonator. The rate of
expansion and contraction of the quartz is the resonant frequency, and is determined
by the cut and size of the crystal.
A regular timing crystal contains two electrically conductive plates, with a slice or
tuning fork of quartz crystal sandwiched between them. During startup, the circuit
around the crystal applies a random noise AC signal to it, and purely by chance, a tiny
fraction of the noise will be at the resonant frequency of the crystal. The crystal will
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therefore start oscillating in synchrony with that signal. As the oscillator amplifies the
signals coming out of the crystal, the crystal's frequency will become stronger,
eventually dominating the output of the oscillator. Natural resistance in the circuit and
in the quartz crystal filter out all the unwanted frequencies.
One of the most important traits of quartz crystal oscillators is that they can exhibit
very low phase noise. In other words, the signal they produce is a pure tone. This
makes them particularly useful in telecommunications where stable signals are needed
and in scientific equipment where very precise time references are needed.
The output frequency of a quartz oscillator is either the fundamental resonance or a
multiple of the resonance, called an overtone frequency.
A typical Q for a quartz oscillator ranges from 104 to 106. The maximum Q for a high
stability quartz oscillator can be estimated as Q = 1.6 × 107/f, where f is the resonance
frequency in Megahertz.
-c
Environmental changes of temperature, humidity, pressure and vibration can change
the resonant frequency of a quartz crystal, but there are several designs that reduce
these environmental effects. These include the TCXO, MCXO, and OCXO (defined
below). These designs (particularly the OCXO) often produce devices with excellent
short-term stability. The limitations in short-term stability are mainly to noise from
electronic components in the oscillator circuits. Long term stability is limited by aging
of the crystal.
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Due to aging and environmental factors such as temperature and vibration, it is hard
to keep even the best quartz oscillators within one part in 10−10 of their nominal
frequency without constant adjustment. For this reason, atomic oscillators are used for
applications that require better long-term stability and accuracy. Care must be taken to
use only one crystal oscillator source when designing circuits to avoid subtle failure
modes of metastability in electronics. If this is not possible, the number of distinct
crystal oscillators, PLLs, and their associated clock domains should be rigorously
minimized, through techniques such as using a subdivision of an existing clock
instead of a new crystal source. Each new distinct crystal source needs to be
rigorously justified.
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Logic diagram :
-c
Procedure :
Figure 109
Make connections as shown in the figure 109.
2.
Connect +5V to pin no. 14 and connect ground to pin no. 7 of IC7404. (Refer
pin diagram of ICs as shown in the figure 109)
3.
Switch ON the instrument.
4.
Observe oscillator output on oscilloscope.
5.
Measure the frequency.
6.
Compare with frequency of crystal.
Observation and Result :
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1.
Crystal oscillator frequency depends solely on crystal dimensions and independent of
any other parameter.
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Experiment 29
Objective :
Study of 4 bit Binary Up Down Counter
Equipments Needed :
Components
Quantity
1.
IC74107 2 input JK flip flop
2
2.
IC7408 2 input AND Gate
2
3.
IC7432 2 input OR Gate.
1
Counter : Almost any complex digital system contains several counters. A counter’s
job is the obvious one of counting events or periods of time or putting events into
sequence. Counters also do not so obvious jobs such as dividing frequency,
addressing, and serving as memory units.
-c
A counter is probably one of the most useful and versatile subsystems in a digital
system. A counter driven by a clock can be used to count the number of clock cycles.
Since the clock pulses occur at known intervals, the counter can be used as an
instrument for measuring time and therefore period or frequency.
There are basically two different types of counters :
1.
Synchronous, and
2.
Asynchronous.
on
The Asynchronous or Ripple counter is simple and straightforward in operation and
construction and usually requires a minimum of hardware. Each flip-flop is triggered
by the previous flip-flop, and thus the counter has a cumulative settling time. In other
words, the clock pulse (CP) inputs of all flip-flops (except the first) are triggered not
by the incoming pulses but rather by the transition that occurs in other flip-flops.
Counter such as these are also known as Serial Counters.
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The asynchronous counter is the simplest to build, but there is a limit to its highest
operating frequency. As each flip-flop has delay time and in an asynchronous counter
these delay times are additive, and the total ‘settling’ time for the counter is
approximately the delay time times the total number of flip-flops. Further more there
is a possibility of glitches occurring at the output of decoding gates used with these
counters. Both of these problems can be overcome by the use of a synchronous or
parallel counter.
Up Down counter is a combination of up counter and down counter, counting in
straight binary sequence. There is an up-down selector. If this value is kept high,
counter increments binary value and if the value is low, then counter starts
decrementing the count.
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Up Counter :
Down Counter :
A3
A2
A1
A4
A3
A2
Al
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
1
1
1
0
0
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
1
1
1
0
0
0
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
-c
A4
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
1
0
0
on
0
0
0
1
1
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
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Logic diagram :
-c
Procedure :
Figure 110
Make connections as shown in the figure 110.
2.
Connect +5V to pin no.14 and ground to pin no. 7 of ICs. (Refer pin diagram of
ICs as shown in the figure 110)
3.
Connect +5V to the UP terminal of Counter and ground to DOWN terminal.
4.
Connect data switch (D7) output to clock input CP of flip-flop.
5.
Keep D7 at logic 1 position. Switch ON the instrument.
6.
Connect ground to clear input of flip flop and disconnect.
7.
Connect +5V to clear input.
8.
Make D7 0 and then 1 to give high to low transition pulse.
9.
Observe outputs on 8 bit LED display.
10.
Repeat step 9, 10 times and observe change in output. It will follow sequence as
shown in Truth Table for UP counter.
11.
Instead of connecting data switch D7 to clock input to give manual pulses, low
frequency clock of 0.1Hz can be given from Sine/Square /TTL generator to
observe continuous output.
12.
Connect + 5V to DOWN terminal and ground to UP terminal.
13.
Repeat above steps for counter to count down. Verify Truth Table.
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Observation table :
Up Counter :
S. No
A4
A3
A2
Down Counter :
A1
S. No
1
2
2
3
3
4
4
5
5
6
6
7
7
8
9
11
12
A2
Al
8
9
14
15
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12
13
14
15
16
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10
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1
A4
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Experiment 30
Objective :
Study of Johnson Counter
Equipments Needed :
Components
Quantity
1.
IC 7474 D flip flop
2
2.
IC 7408 2 input AND Gate
2
Johnson Counter :
A Johnson counter is one of the simplest examples of a synchronous counter i.e. a
counter in which all the outputs change simultaneously. A Johnson counter is
generally used to produce moving light displays. It differs from a ripple counter in
that
it is based on a clocked D latch
•
all the clock inputs are fed from the same clock
•
the NOT Q output of the final latch is used as the input to the first
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•
An example of a Johnson counter is shown in the figure 111.
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Figure 111
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If all the inputs start at 0 then all the outputs Q will be 0, but the NOT Q from the
third D latch will be 1. Thus the input to the first latch will now be 1 and on the first
negative clock pulse the output of the first D latch will change to 1. This now makes
the input to the second latch 1, and its output will now change to 1 on the second
clock pulse, making the input to the third latch 1. The third latch will therefore have
an output of 1 on the third clock pulse at which time the NOT Q output (and the input
to the first latch) will become 0. At this point the 0's propagate through the sequence
on successive clock pulses. The timing diagram looks as shown in the figure 112.
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Figure 112
-c
The sequence of numbers given by the outputs is also shown. Although there is a
cycle of 6 numbers they do not represent a binary counting sequence. A Johnson
counter is also known as a ring counter.
Logic diagram :
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Figure 113
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Truth Table : (Logic 1 =+5V, Logic 0 = Gnd)
Flip flop
output A
B
C
E
AND Gate
required for output
1
0
0
0
0
A'E'
2
1
0
0
0
AB'
3
1
1
0
0
BC'
4
1
1
1
0
CE'
5
1
1
1
1
AE
6
0
1
1
1
A'B
7
0
0
1
1
B'C
0
1
C'E
8
Procedure :
-c
S. No.
0
0
on
Make connections as shown in the figure 113.
2.
Connect +5V to pin no. 14 and ground to pin no. 7of ICs.
3.
Connect data switch (D7) output to clock input CP of flip-flop.
4.
Keep D7 at logic 0 position.
5.
Switch ON the instrument.
6.
Connect ground to clear input of flip flop and disconnect it.
7.
Connect +5V to clear and set input of flip-flop.
8.
Make D7; 1 and then 0 to give low to high transition pulse.
9.
Observe outputs on 8 bits LED display.
10.
Repeat step 8, 7 times and observe change in output. It will follow sequence as
shown in Truth Table.
11.
Verify Truth Table.
12.
AND and NOT Gates can be used to make product terms of last column and can
be observed on 8 bits LED display to know when a particular combination
occurs.
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Observation table :
S. No.
Flip flop
output A
1
0
2
1
3
1
4
1
6
C
E
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5
B
1
0
0
8
0
9
0
Result :
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on
7
Johnson counter gives 2K distinguishable states with k flip-flop.
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Experiment 31
Objective :
Study of 4 Bit Serial in Parallel out Shift Register
Equipments Needed :
Components
1.
Quantity
IC7475 D flip flop
1
A register is a group of binary storage cells suitable for holding binary information. A
group of flip-flops constitute a register, since each flip-flop is a binary cell capable of
storing one bit of information. An n-bit register has a group of n flip-flops and is
capable of storing any binary information containing n bits. In addition to the flipflops, a register may have combinational gates that perform certain data processing
tasks like when and how new information is transferred in to the register.
-c
A register capable of shifting its binary information either to the right or to the left is
called a shift register. The logical configuration of a shift register consists of a chain
of flip-flops connected in cascade, with the output of one flip-flop connected to the
input of next flip-flop. All flip-flops receive a common clock pulse, which causes the
shift from one stage to the next.
on
4 bit serial in -parallel out shift register is shown in the figure 114. The Q output of a
given flip-flop is connected to the D input of the flip-flop at its right. Each clock pulse
shifts the contents of the register one bit position to the right. The serial input
determines what goes into the leftmost flip-flop during the shift. The serial output is
taken from the output of rightmost flip-flop prior to the application of pulse. The
register shifts its contents with every clock during the positive edge of the pulse
transition.
There are parallel outputs Q0-Q3 with Q3 as LSB. MC is active high clock input i.e.
data will shift to right on positive edge of clock pulse.
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MR is master reset input (active low i.e. negative edge trigger) to flip-flops to reset or
clear output Q0-Q3 globally.
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Logic diagram :
Figure 114
Truth Table :
(Logic 1 = +5V & Logic 0= GND)
MR
1
Input
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0
MC
Q0
Q1
Q2
Q3
1
1 or 0
0
0
0
0
0→ 1
1
1
0
0
0
1
0→ 1
1
0→ 1
0
0
1
0
0
1
1
0
1
0
0
0 → 1 = transition from logic 1 to logic 0
(Positive Edge trigger)
0
1
0
1
Table 1
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1
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Procedure :
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Observe output of each flip-flop on 8 bits LED display. It will be as indicated in
table.
Apply any of the given combination as per Truth Table.
Observe the output coming at 8 bit LED display for Shift register output XYZ
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11.
12.
Make connections as shown in the figure 114.
Connect +5V to pin no. 14 and ground to pin no. 7 of IC7474. (Refer to pin
diagram of ICs as shown in the figure 114)
Keep D7 at logic 0 position.
Switch ON the instrument.
Clear all flip-flops by applying ground to clear input of flip-flops.
Connect +5V to clear and set input of flip-flop.
Apply +5V to serial input SI of shift register.
Connect data switch (D7) output to clock input CP of flip-flop.
Make D7 1 and then 0 to give low to high transition pulse.
Trigger flip-flops four times by repeating step 8.
13.
on
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow
14. Note all the output coming for these combinations of input and verify it by the
truth table.
Observation table :
Truth Table : (Logic 1 =+5V, Logic 0 = GND)
S. No.
Input
1 or 0
2
1
3
0
4
1
5
0
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Q2
Q3
B
C
D
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Q0
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Experiment 32
Objective :
Study of 8 to 3 Line Encoder
Equipments Needed :
Component
1.
Quantity
IC7432 2 input OR Gate
3
An encoder is a device used to change a signal (such as a bitstream) or data into a
code. The code may serve any of a number of purposes such as compressing
information for transmission or storage, encrypting or adding redundancies to the
input code, or translating from one code to another. This is usually done by means of
a programmed algorithm, especially if any part is digital, while most analog encoding
is done with analog circuitry.
Discrete quantities of information are represented in digital systems with binary
codes. 2n distinct elements can be represented by a binary code of n bits. An encoder
has 2 n input lines and n output lines. The output lines generate the binary code for the
2n input variables.
-c
Figure 115 shows 8 to 3 line encoder. It consists of eight inputs D0-D7, and three
outputs X, Y, Z that generates the corresponding binary number. X is MSB.
It is constructed with OR gates whose inputs can be determined from the truth table.
Logic diagram :
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The encoder in figure 115; assumes that only one input line can be equal to 1 at any
time. The circuit has eight inputs and could have 28 = 256 possible input
combinations. Only eight of these combinations have been considered. The other
input combinations are don't-care conditions.
Figure 115
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Truth Table : (Logic 1 =+5V, Logic 0 = GND)
D0
D1
D2
D3
D4
D5
D6
D7
x
y
Z
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
Procedure :
(Use three 2 input OR Gate in place of one 4 input OR Gate.)
-c
Make connections as shown in the figure 115.
2.
Connect +5V to pin no. 14 and ground to pin no. 7 of IC7432. (Refer to pin
diagram of ICs as shown in the figure 115)
3.
Connect input data switches to 1(+5V) or 0 (0V) to encoder circuit as shown in
the figure 115 as per Truth Table.
4.
Switch ON the instrument.
5.
Connect the output pins to 8 bits LED display.
6.
Apply any of the given combination as per Truth Table.
7.
Observe the output coming at 8 bit LED display for Shift register Endcoder
8.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow
9.
Note all the output coming for these combinations of input and verify it by the
truth table.
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Observation table :
Truth Table : (Logic 1 =+5V, Logic 0 = GND)
S. No
D1
D2
D3
D4
D5
D6
D7
1
1
0
0
0
0
0
0
0
2
0
1
0
0
0
0
0
0
3
0
0
1
0
0
0
0
0
4
0
0
0
0
5
0
0
-c
D0
0
0
6
0
0
7
0
8
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
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0
z
1
0
0
0
1
0
0
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Experiment 33
Objective :
Study of 3 to 8 Line Decoder
Equipments Needed :
Components
Quantity
1.
IC7411 3 input AND Gate.
3
2.
IC7404 Inverter.
1
A decoder is a device which does the reverse of an encoder, decoding the encoding so
that the original information can be retrieved. The same method used to encode is
usually just reversed in order to decode.
In digital electronics this would mean that a decoder is a multiple-input, multipleoutput logic circuit that converts coded inputs into coded outputs, where the input and
output codes are different. e.g. n-to-2n, BCD decoders.
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Enable inputs must be on for the decoder to function, otherwise its outputs assume a
single "disabled" output code word. Decoding is necessary in applications such as
data multiplexing, 7 segment display and memory address decoding.
The simplest decoder circuit would be an AND gate because the output of an AND
gate is "High" (1) only when all its inputs are "High".
Example: A 3-to-8 Line Single Bit Decoder
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A slightly more complex decoder would be the n-to-2n type binary decoders. These
type of decoders are combinational circuits that convert binary information from 'n'
coded inputs to a maximum of 2n unique outputs. We say a maximum of 2n outputs
because in case the 'n' bit coded information has unused bit combinations, the decoder
may have less than 2 n outputs. We can have 2-to-4 decoder, 3-to-8 decoder or 4-to-16
decoder. We can form a 3-to-8 decoder from two 2-to-4 decoders (with enable
signals).
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Logic diagram :
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Figure 116
Truth Table : (Logic 1 =+5V, Logic 0 = GND)
y
z
D0
Dl
D2
D3
D4
D5
D6
D7
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
1
0
1
0
0
0
1
0
1
1
1
1
1
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0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
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1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
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Procedure :
1.
Make connections as shown in the figure 116.
2.
Connect +5V to pin no. 14 and ground to pin no. 7 of IC7404 and IC7411.
(Refer to pin diagram of ICs as shown in the figure 116)
3.
Connect 8 bit data switch with input pins
4.
Now connect LED no. ‘0’ to LED no. ‘8’ of 8 bit LED display with output pin.
5.
Apply any of the given combination as per Truth Table.
6.
Observe the output coming at 8 bit LED display For Decoder
7.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow
8.
Note all the output coming for these combinations of input and verify it by the
truth table.
9.
Repeat step no. 3 and 8 for other inputs.
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Observation table :
Truth Table : (Logic 1 =+5V, Logic 0 = GND)
S.
No
y
z
1
0
0
0
2
0
0
1
3
0
1
0
4
0
5
D0
Dl
D2
D3
D4
D5
D6
D7
1
0
0
6
1
0
1
7
1
1
0
8
1
1
1
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Experiment 34
Objective :
Study of Multiplexer and De-multiplexer circuit
Components required :
Component
Quantity
1.
IC7411 3 input AND Gate.
2
2.
IC7432 2 Input OR Gate.
1
3.
IC7404 NOT Gate.
1
Multiplexing is defined as the process of feeding several independent signals to a
common load, one at a time. The device or switching circuitry used to select and
connect one of these several signals to the load at any one time is known as a
multiplexer.
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Multiplexing means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single
output line. The selection of a particular input line is controlled by a set of selection
lines. There are 2n input lines and n selection lines whose bit combinations determine
which input is selected.
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A 4 to 1 Line Multiplexer is shown in figure 117. Each of the four input lines, D0 to
D3 is applied to one input of an AND gate. Selection lines S1, S0 are decoded to
select a particular AND gate. When S1, S0 = 10. The AND gate associated with input
D2 has two of its inputs equal to 1 and third input connected to D2. The other three
AND gates have at least one input equal to 0, which makes their output equal to 0.
The OR-gate output is now equal to the value of D2, thus providing a path from the
selected input to the output. A multiplexer is also called a data selector, since it selects
one of many inputs and steers the binary information to the output line. Whenever any
input is selected which is in form of clock pulse all other inputs should be at zero
level i.e. logic 0.
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A demultiplexer is a circuit that receives information on a single line and transmits
this information on one of 2n possible output lines. The selection of a specific output
line is controlled by the bit values of n selection lines. 1 to 4 Line Demultiplexer is
shown in figure 2 the single input variable D has a path to all four outputs, but the
input information is directed to only one of the output lines, as specified by the binary
value of the two selection lines S1 and S0. If the selection lines S1, S0 = 1, 0 output
D2 will be same as the input value D, provided D =0 while all other outputs are
maintained at 1. For D=1. All outputs are at high level. Clock pulse given to D input
can be obtained at output lines through selection lines S1 S0.
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The reverse function of multiplexing, known as demultiplexing, pertains to the
process of feeding several independent loads with signals coming from a common
signal source, one at a time. A device used for demultiplexing is known as a
demultiplexer.
Multiplexing and demultiplexing, therefore, allow the efficient use of common
circuits to feed a common load with signals from several signal sources and to feed
several loads from a single, common signal source, respectively.
In digital circuits, the term 'multiplexing' is also sometimes used to refer to the
process of encoding, which is basically the generation of a digital code to indicate
which of several input lines is active. An encoder or multiplexer is therefore a digital
IC that outputs a digital code based on which of its several digital inputs is enabled.
On the other hand, the term 'demultiplexing' in digital electronics is also used to refer
to 'decoding', which is the process of activating one of several mutually-exclusive
output lines, based on the digital code present at the binary-weighted inputs of the
decoding circuit, or decoder. A decoder or demultiplexer is therefore a digital IC that
accepts a digital code consisting of two or more bits at its inputs, and activates or
enables one of its several digital output lines depending on the value of the code.
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Multiplexing and demultiplexing are used in digital electronics to allow several chips
to share common signal buses. In demultiplexers, for instance, the output lines may be
used to enable memory chips that share a common data bus, ensuring that only one
memory chip is enabled at a time in order to prevent data clashes between the chips.
4 To 1 Line Multiplexer
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Logic diagram :
Figure 117
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Truth Table : (Logic 1 =+5V, Logic 0 = Gnd)
Selection line 1
(A)
Selection
line 2 (B)
Input
Selected (E)
0
0
I1
0
1
I2
1
0
I3
1
1
I4
Procedure :
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Make connections as shown in the figure 117.
2.
Connect + 5V to pin no. 14 and ground to pin no.7 of ICs. (Refer to pin diagram
of ICs as shown in the figure 117).
3.
Apply inputs 1 or 0 to input lines 11, 12, 13, 14 by connecting input lines with
data switches.
4.
Connect 0 to selection lines ‘A’ and ‘B’ as shown in Truth Table that is either
connected with ground or connected data switch while keeping them at 0 level.
5.
Switch ON the instrument.
6.
Connect the output pin at 8 bit LED display or logic probe.
7.
Observe outputs on 8 bits LED display or logic probe. (If input applied is TTL
pulse then CRO can be used to view waveforms at output).
8.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow.
9.
Note all the output coming for these combinations of input and verify it by the
truth table.
10.
Repeat step 4 for other selection line combination i.e. 01, 10 and 11
respectively.
11.
Follow above steps and prove Truth Table.
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Observation Table :
S. No Input Input Input Input Selection Selection
at I1 at I2 at I3 at I4 line 1 (A) line 2 (B)
Input
Selected
(E)
0
0
I1
2
0
1
I2
3
1
0
I3
1
1
I4
4
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1
Output
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1 To 4 Line De-multiplexer:
Equipments Needed :
Component
Quantity
1.
IC7404 NOT Gate
1
2.
IC74LS11 NAND Gate
2
Logic diagram :
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Figure 118
Input
Selection Selection
line
line
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Truth Table : (Logic 1 =+5V, Logic 0 = GND)
Output
Line
Output
Line
Output
Line
Output
Line
D0
Dl
D2
D3
S0
S1
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
1
0
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Procedure :
Make connections as shown in the figure 118.
2.
Connect + 5V to pin no. 14 and ground to pin no.7 of ICs. (Refer to pin diagram
of ICs as shown in the figure 118)
3.
Apply inputs 1 or 0 to input E.
4.
Connect 0 to selection lines S1 and S0 as shown in Truth Table.
5.
Switch ON the instrument.
6.
Observe outputs on 8 bits LED display or logic probe.
7.
If input applied is TTL pulse then CRO can be used to view waveforms at
output.
8.
Apply any of the given combination as per Truth Table.
9.
If the output is 0 (0V) the LED will not glow or if the output is 1 (5V) LED will
glow
10.
Note all the output coming for these combinations of input and verify it by the
truth table.
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1.
Observation table :
Input
Selection
line
Output
Line
Output
Line
on
S.
No
Selection
line
E
S0
1
0
0
2
0
0
1
3
0
1
0
4
0
1
1
D0
Output
Line
D2
D3
Dl
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Output
Line
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Experiment 35
Objective :
Study of Pulse Stretcher circuit
Equipments Needed :
Components
Quantity
1.
IC7400 2 input NAND Gate
2
2.
Capacitors 0.01 MF
1
0.022 MF
1
0.033 MF
1
3.
Resistance 5600Ω
2
Logic diagram :
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Procedure :
Figure 119
Make connections as shown in the figure 119. (Refer pin diagram of ICs)
2.
Switch ON the instrument.
3.
Set range switch of Sine/Square /TTL to 10 KHz position and adjust it approx
10 KHz with the help of fine potentiometer. Set TTL frequency selection switch
to High position. Connect TTL output to the pins 1, 2 of 7400.
4.
Apply same pulse to ext trigger input of CRO for triggering time base.
5.
See the output waveform on CRO.
6.
Change value of capacitor C and observe the change in width.
7.
Follow the above steps and complete table shown.
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Observation table :
Capacitance
1
0MF
2
0.001MF
3
0.022MF
4
0.033MF
Pulse width at terminal 6
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Result :
Sr. No.
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The width of output at pin 6 of IC 7400 is longer than that at 1 because it takes
capacitor C time to charge up to the threshold voltage of Gate 2.
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Experiment 36
Objective :
Study of method of Interfacing CMOS Logic family with TTL Logic family
Introduction :
The CMOS logic family can be operated at the same power supply voltage as TTL but
with a sacrifice in speed. To operate the CMOS family at its maximum speed requires
operation with Vdd equal to 15V. To interface with TTL requires a level shifting
device. CMOS logic elements can easily drive other CMOS elements because of their
high input resistance. However, most CMOS logic elements cannot provide the
current required by a single load of the medium-power TTL series. To satisfy this
current requirement requires high current CMOS buffer element.
Equipments Needed :
Component
Quantity
IC7404 NOT Gate
1
2.
IC7402 NOR Gate
1
3.
IC4050 CMOS Buffer
1
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1.
Logic diagram :
0 (ground) to pin 7
7402 VDD = + 15volts to pin 14
Vss = 0 (ground) to pin 7
4050 Vcc = + 5volts to pin 1 (note pin number)
Vss = 0 (ground) to pin 8
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7404 Vcc = +5volts to pin 14
Figure 120
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Procedure :
1.
Make connections as shown in the figure 120.(Refer pin diagram of ICs)
2.
Connect +5V to pin no. 14 and ground to pin no. 7 of IC7404.
3.
Connect + 15V to pin no. 14 and ground to pin no. 7 of IC7402.
4.
Connect +5V to pin no. 1 and ground to pin no. 8.of IC4050.
5.
View and sketch the waveform at
a.
7404 pin 2
b.
7402 pin 1
c.
7402 pin 3
d.
4050 pin 2
e.
7404 pin 4
Result :
CMOS to TTL interface circuit is studied.
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Electronic Graphical Symbols Used In Circuit Diagrams
Photo Diode
Varicap Diode
LED
Zener Diode
Electrolytic
TRIAC
Variable
Trimmer
Fixed
Capacitor
Capacitor
Capacitor
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Battery
DIAC
SCR
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Capacitor
Diode
Resistor
Potentiometer
Fuse
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Inverting Amp
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Operational Amp (Op-Amp)
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Thermistor
Thermocouple
Speaker
Head Phone
PNP Transistor
NPN Transistor
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N Channel FET
P Channel FET
Dual Gate MOSFET
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Fig. 121
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UJT
Single Gate MOSFET
Micro phone
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Lead Details of Transistors and ICs
BC546/547/548/549/550
2N2369
2N3904
IC741
Fig. 122
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Fig. 123
Diode
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Fig. 124
Diode
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Figure 124
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Data Sheet
General Description :
The 74HC/HCT04 are high-speed Si-gate CMOS devices and are pin compatible with
low power schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard number 7A. The 74HC/HCT04 provides six inverting buffers.
Pin out diagram :
(Pin 14 = Vcc = + 5V)
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Function Table :
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General Description :
The 74HC/HCT00 are high-speed Si-gate CMOS devices and are pin compatible with
low power schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard number 7A. The 74HC/HCT00 provides 2-input NAND function.
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Function Table :
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General Description :
The 74HC/HCT32 are high-speed Si-gate CMOS devices and are pin compatible with
low power schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard number 7A. The 74HC/HCT32 provides 2-input OR function.
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Function Table :
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General Description :
The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with
low power schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard number 7A. The 74HC/HCT08 provides 2-input AND function.
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Function Table :
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General Description :
This device contains four independent gates each of which performs the logic NOR
function.
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Function Table :
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Function Table :
L = Low voltage level
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H = High voltage level
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Note : Pull up resistance of 1K is required in open collector ICs to get output.
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Warranty
1.
We guarantee the product against all manufacturing defects for 24 months from
the date of sale by us or through our dealers. Consumables like dry cell etc. are
not covered under warranty.
2.
The guarantee will become void, if
a)
The product is not operated as per the instruction given in the operating
manual.
b)
The agreed payment terms and other conditions of sale are not followed.
c)
The customer resells the instrument to another party.
d)
Any attempt is made to service and modify the instrument.
3.
The non-working of the product is to be communicated to us immediately giving
full details of the complaints and defects noticed specifically mentioning the
type, serial number of the product and date of purchase etc.
4.
The repair work will be carried out, provided the product is dispatched securely
packed and insured. The transportation charges shall be borne by the customer.
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List of Accessories
Bread Board............................................................................................2 Nos.
2.
Connecting Wire.....................................................................................20 Nos.
3.
2mm to 1mm Patch Cord ........................................................................8 Nos.
4.
2mm to 2mm Patch Cord 16”..................................................................8 Nos.
5.
Mains Cord .............................................................................................1 No
6.
Analog –Digital Lab PS ..........................................................................1 No.
7.
e- Manual ...............................................................................................1 No
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Optional Accessories :
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1.
Ready to use experiment boards (covering device characteristics and study of various
circuits) with wired components and schematic drawn on top, compatible to use
with Analog Lab ST2612.
Updated 14-05-2008
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