Cyclone III LS Device Data Sheet

Cyclone III LS Device Data Sheet
2. Cyclone III LS Device Datasheet
July 2012
CIII52002-1.4
CIII52002-1.4
This chapter describes the electric characteristics, switching characteristics, and I/O
timing for Cyclone® III LS devices. A glossary is also included for your reference.
Electrical Characteristics
The following sections provide information about the absolute maximum ratings,
recommended operating conditions, DC characteristics, and other specifications for
Cyclone III LS devices.
Operating Conditions
When Cyclone III LS devices are implemented in a system, they are rated according to
a set of defined parameters. To maintain the highest possible performance and
reliability of Cyclone III LS devices, you must consider the operating requirements in
this chapter. Cyclone III LS devices are offered in commercial and industrial grades.
Commercial devices are offered in –7 (fastest) and –8 speed grades. Industrial devices
are offered only in –7 speed grade.
1
In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades—commercial with a “C” prefix; industrial with an “I” prefix. For
example, commercial devices are described as C7 and C8 per respective speed grades.
Industrial devices are described as I7.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for
Cyclone III LS devices. The values are based on experiments conducted with the
device and theoretical modeling of breakdown and damage mechanisms. The
functional operation of the device is not implied at these conditions. Table 2–1 lists the
absolute maximum ratings for Cyclone III LS devices.
1
Conditions beyond those listed in Table 2–1 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device. All parameters representing
voltages are measured with respect to ground.
Table 2–1. Cyclone III LS Devices Absolute Maximum Ratings (1)
Symbol
Parameter
(Part 1 of 2)
Min
Max
Unit
VCCINT
Supply voltage for internal logic
–0.5
1.8
V
VCCIO
Supply voltage for output buffers
–0.5
3.9
V
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone III Device Handbook
Volume 2
July 2012
Subscribe
2–2
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Table 2–1. Cyclone III LS Devices Absolute Maximum Ratings (1)
Symbol
Parameter
(Part 2 of 2)
Min
Max
Unit
VCCA
Supply (analog) voltage for PLL regulator
–0.5
3.75
V
VCCD_PLL
Supply (digital) voltage for PLL
–0.5
1.8
V
VCCBAT (2)
Battery back-up power supply for design
security volatile key register
–0.5
3.75
V
VI
DC input voltage
–0.5
3.95
V
IOUT
DC output current, per pin
–25
40
mA
VESDHBM
Electrostatic discharge voltage using the human
body model
—
±2000
V
VESDCDM
Electrostatic discharge voltage using the
charged device model
—
±500
V
TSTG
Storage temperature
–65
150
°C
TJ
Operating junction temperature
–40
125
°C
Notes to Table 2–1:
(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the
power supply.
(2) VCCBAT is tied to Power-on reset (POR). If the VCCBAT is below 1.2 V, the device will not power up.
Maximum Allowed Overshoot or Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Table 2–2 and
undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods
shorter than 20 ns.
Table 2–2 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage over the lifetime of the device. The maximum
allowed overshoot duration is specified as percentage of high-time over the lifetime of
the device.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
1
2–3
A DC signal is equivalent to 100% of the duty cycle. For example, a signal that
overshoots to 4.2 V can only be at 4.2 V for 10.74% over the lifetime of the device; for a
device lifetime of 10 years, this is equivalent to 10.74% of ten years, which is 12.89
months.
Table 2–2. Cyclone III LS Devices Maximum Allowed Overshoot During Transitions over a 10-Year
Time Frame
Symbol
Vi
Parameter
AC Input
Voltage
Condition
Overshoot Duration as % of High Time
Unit
VI = 3.95 V
100
%
VI = 4.0 V
95.67
%
VI = 4.05 V
55.24
%
VI = 4.10 V
31.97
%
VI = 4.15 V
18.52
%
VI = 4.20 V
10.74
%
VI = 4.25 V
6.23
%
VI = 4.30 V
3.62
%
VI = 4.35 V
2.1
%
VI = 4.40 V
1.22
%
VI = 4.45 V
0.71
%
VI = 4.50 V
0.41
%
VI = 4.60 V
0.14
%
VI = 4.70 V
0.047
%
Figure 2–1 shows the methodology to determine the overshoot duration. In this
example, overshoot voltage is shown in red and is present on the input pin of the
Cyclone III LS device at over 4.1 V but below 4.2 V. From Table 2–1, for an overshoot
of 4.1 V, the percentage of high time for the overshoot can be as high as 31.97% over a
10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This
10-year period assumes the device is always turned on with 100% I/O toggle rate and
50% duty cycle signal. For lower I/O toggle rates and situations in which the device is
in an idle state, lifetimes are increased.
Figure 2–1. Cyclone III LS Devices Overshoot Duration
4.2 V
4.1 V
3.3 V
ΔT
T
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–4
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Cyclone III LS devices.
The steady-state voltage and current values expected from Cyclone III LS devices are
provided in Table 2–3. All supplies must be strictly monotonic without plateaus.
Table 2–3. Cyclone III LS Devices Recommended Operating Conditions (1),
Symbol
Conditions
Min
Typ
Max
Unit
Supply voltage for internal logic
—
1.15
1.2
1.25
V
Supply voltage for output buffers, 3.3-V
operation
—
3.135
3.3
3.465
V
Supply voltage for output buffers, 3.0-V
operation
—
2.85
3.0
3.15
V
Supply voltage for output buffers, 2.5-V
operation
—
2.375
2.5
2.625
V
Supply voltage for output buffers, 1.8-V
operation
—
1.71
1.8
1.89
V
Supply voltage for output buffers, 1.5-V
operation
—
1.425
1.5
1.575
V
Supply voltage for output buffers, 1.2-V
operation
—
1.14
1.2
1.26
V
Supply (analog) voltage for PLL regulator
—
2.375
2.5
2.625
V
Supply (digital) voltage for PLL
—
1.15
1.2
1.25
V
VCCBAT (4)
Battery back-up power supply for design
security volatile key register
—
1.2
3.0
3.3
V
VI
Input voltage
—
–0.5
—
3.6
V
VO
Output voltage
—
0
—
VCCIO
V
TJ
Operating junction temperature
For commercial use
0
—
85
°C
For industrial use
–40
—
100
°C
50 µs
—
50 ms
—
50 µs
—
3 ms
—
—
—
10
mA
VCCINT
VCCIO
VCCA
(3)
(3), (7)
(3)
VCCD_PLL
(3)
Parameter
(2)
tRAMP
Power supply ramptime
IDiode
Magnitude of DC current across
PCI-clamp diode when enabled
Standard POR
Fast POR
(5)
(6)
—
Notes to Table 2–3:
(1) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when you do not use phase
locked-loops [PLLs}), and must be powered up and powered down at the same time.
(2) VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead.
(3) VCC must rise monotonically.
(4) VCCBAT is tied to POR. If the VCCBAT is below 1.2 V, the device will not power up.
(5) POR time for Standard POR ranges from 50 to 200 ms. Each individual power supply must reach the recommended operating range within
50 ms.
(6) POR time for Fast POR ranges from 3 to 9 ms. Each individual power supply must reach the recommended operating range within 3 ms.
(7) All input buffers are powered by the VCCIO supply.
DC Characteristics
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)
tolerance, and bus hold specifications for Cyclone III LS devices.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
2–5
Supply Current
Supply current is the current the device draws after the device is configured with no
inputs or outputs toggling and no activity in the device. Use the Excel-based Early
Power Estimator (EPE) to get the supply current estimates for your design because
these currents vary largely with the resources you use. Table 2–4 lists the I/O pin
leakage current for Cyclone III LS devices.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Table 2–4. Cyclone III LS Devices I/O Pin Leakage Current (1),
Symbol
Parameter
Conditions
(2)
Min
Typ
Max
Unit
II
Input Pin Leakage Current VI = VCCIOMAX to 0 V
–10
—
10
A
IOZ
Tri-stated I/O Pin Leakage
Current
–10
—
10
A
VO = VCCIOMAX to 0
V
Notes to Table 2–4:
(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all
VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).
(2) The 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be
observed when the diode is on.
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 2–5 lists the bus hold specifications for Cyclone III LS devices. Also listed are the
input pin capacitances and OCT tolerance specifications.
Table 2–5. Cyclone III LS Devices Bus Hold Parameters (1)
VCCIO (V)
Parameter
Condition
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold
low,
sustaining
current
VIN > VIL
(maximum)
8
—
12
—
30
—
50
—
70
—
70
—
A
Bus-hold
high,
sustaining
current
VIN < VIL
(minimum)
–8
—
–12
—
–30
—
–50
—
–70
—
–70
—
A
Bus-hold
low,
overdrive
current
0 V < VIN <
VCCIO
—
125
—
175
—
200
—
300
—
500
—
500
A
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–6
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Table 2–5. Cyclone III LS Devices Bus Hold Parameters (1)
VCCIO (V)
Parameter
Bus-hold
high,
overdrive
current
Condition
0 V < VIN <
VCCIO
Bus-hold
trip point
—
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
—
–125
—
–175
—
–200
—
–300
—
–500
—
–500
A
0.3
0.9
1.07
0.7
1.7
0.8
2.0
0.8
2.0
V
0.375 1.125 0.68
Note to Table 2–5:
(1) Bus-hold trip points are based on calculated input voltages from the JEDEC standard.
OCT Specifications
Table 2–6 lists the variation of OCT without calibration across process, temperature,
and voltage (PVT).
Table 2–6. Cyclone III LS Devices Series OCT without Calibration Specifications
Resistance Tolerance
Description
Series OCT without
calibration
VCCIO (V)
Unit
Commercial Max
Industrial Max
3.0
±30
±40
%
2.5
±30
±40
%
1.8
±40
±50
%
1.5
±50
±50
%
1.2
±50
±50
%
OCT calibration is automatically performed at device power-up for OCT enabled
I/Os.
Table 2–7 lists the OCT calibration accuracy at device power-up.
Table 2–7. Cyclone III LS Devices Series OCT with Calibration at Device Power-Up Specifications
Calibration Accuracy
Description
Series Termination with
power-up calibration
VCCIO (V)
Unit
Commercial Max
Industrial Max
3.0
±10
±10
%
2.5
±10
±10
%
1.8
±10
±10
%
1.5
±10
±10
%
1.2
±10
±10
%
OCT resistance may vary with the variation of temperature and voltage after
power-up calibration. Use Table 2–8 and Equation 2–1 to determine the final OCT
resistance considering the variations after power-up calibration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
2–7
Table 2–8 lists the percentage change of the OCT resistance with voltage and
temperature.
Table 2–8. Cyclone III LS Devices OCT Variation After Calibration at Device Power-Up (1)
Nominal Voltage
dR/dT (%/°C)
dR/dV (%/mV)
3.0
0.262
–0.026
2.5
0.234
–0.039
1.8
0.219
–0.086
1.5
0.199
–0.136
1.2
0.161
–0.288
Note to Table 2–8:
(1) Use this table to calculate the final OCT resistance with the variation of temperature and voltage.
Equation 2–1.
(1), (2), (3), (4), (5), (6)
RV = (V2 – V1) × 1000 × dR/dV –––––
RT = (T2 – T1) × dR/dT –––––
For Rx < 0; MFx = 1/ (|Rx|/100 + 1) –––––
For Rx > 0; MFx = Rx/100 + 1 –––––
(7)
(8)
(9)
(10)
MF = MFV × MFT –––––
(11)
Rfinal = Rinitial × MF –––––
(12)
Notes to Equation 2–1:
(1) T2 is the final temperature.
(2) T1 is the initial temperature.
(3) MF is multiplication factor.
(4) Rfinal is final resistance.
(5) Rinitial is initial resistance.
(6) Subscript × refers to both V and T.
(7) RV is variation of resistance with voltage.
(8) RT is variation of resistance with temperature.
(9) dR/dT is the percentage change of resistance with temperature.
(10) dR/dV is the percentage change of resistance with voltage.
(11) V2 is final voltage.
(12) V1 is the initial voltage.
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–8
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Example 2–1 shows you how to calculate the change of 50  I/O impedance from
25°C at 3.0 V to 85°C at 3.15 V.
Example 2–1.
RV = (3.15 – 3) × 1000 × –0.026 = –3.83
RT = (85 – 25) × 0.262 = 15.72
Because RV is negative,
MFV = 1 / (3.83/100 + 1) = 0.963
Because RT is positive,
MFT = 15.72/100 + 1 = 1.157
MF = 0.963 × 1.157 = 1.114
Rfinal = 50 × 1.114 = 55.71 
Pin Capacitance
Table 2–9 lists the pin capacitance for Cyclone III LS devices.
Table 2–9. Cyclone III LS Devices Pin Capacitance
Symbol
Parameter
Typical –
QFP
Typical –
FBGA
Unit
CIOTB
Input capacitance on top/bottom I/O pins
7
6
pF
CIOLR
Input capacitance on left/right I/O pins
7
5
pF
CLVDSLR
Input capacitance on left/right I/O pins with true LVDS
output
8
7
pF
Input capacitance on left/right dual-purpose VREF pin
when used as VREF or user I/O pin
21
21
pF
(1)
Input capacitance on top/bottom dual-purpose VREF
pin when used as VREF or user I/O pin
23
23
pF
CCLKTB
Input capacitance on top/bottom dedicated clock input
pins
7
6
pF
CCLKLR
Input capacitance on left/right dedicated clock input
pins
6
5
pF
CVREFLR
(1)
CVREFTB
Note to Table 2–9:
(1) When you use the VREF pin as a regular input or output, you can expect a reduced performance of toggle rate and
tCO due to higher pin capacitance.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
2–9
Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 2–10 lists the weak pull-up and pull-down resistor values for Cyclone III LS
devices.
Table 2–10. Cyclone III LS Devices Internal Weak Pull-Up Weak and Pull-Down Resistor (1)
Symbol
R_PU
R_PD
Parameter
Value of I/O pin pull-up resistor before
and during configuration, as well as
user mode if the programmable
pull-up resistor option is enabled
Value of I/O pin pull-down resistor
before and during configuration
Conditions
Min
Typ
Max
Unit
VCCIO = 3.3 V ± 5%
(2), (3)
7
25
41
k
VCCIO = 3.0 V ± 5%
(2), (3)
7
28
47
k
VCCIO = 2.5 V ± 5%
(2), (3)
8
35
61
k
VCCIO = 1.8 V ± 5%
(2), (3)
10
57
108
k
VCCIO = 1.5 V ± 5%
(2), (3)
13
82
163
k
VCCIO = 1.2 V ± 5%
(2), (3)
19
143
351
k
VCCIO = 3.3 V ± 5%
(4)
6
19
30
k
VCCIO = 3.0 V ± 5%
(4)
6
22
36
k
VCCIO = 2.5 V ± 5%
(4)
6
25
43
k
VCCIO = 1.8 V ± 5%
(4)
7
35
71
k
VCCIO = 1.5 V ± 5%
(4)
8
50
112
k
Notes to Table 2–10:
(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available
for JTAG TCK.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(3) R_PU = (VCCIO – VI)/IR_PU
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = VCC + 5% – 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = 0 V;
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.
(4) R_PD = VI/IR_PD
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = VCC – 5%;
Maximum condition: 125°C; VCCIO = VCC – 5%, VI = VCC – 5%; in which VI refers to the input voltage at the I/O pin.
Hot Socketing
Table 2–11 lists the hot-socketing specifications for Cyclone III LS devices.
Table 2–11. Cyclone III Devices LS Hot-Socketing Specifications
Symbol
Parameter
Maximum
IIOPIN(DC)
DC current per I/O pin
300 A
IIOPIN(AC)
AC current per I/O pin
8 mA
(1)
Note to Table 2–11:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is I/O pin
capacitance and dv/dt is the slew rate.
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–10
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
Schmitt Trigger Input
Cyclone III LS devices support Schmitt trigger input on TDI, TMS, TCK, nSTATUS,
nCONFIG, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces
hysteresis to the input signal for improved noise immunity, especially for signals with
a slow edge rate. Table 2–12 lists the hysteresis specifications across supported VCCIO
range for Schmitt trigger inputs in Cyclone III LS devices.
Table 2–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III LS Devices
Symbol
Parameter
Hysteresis for Schmitt trigger
input
VSCHMITT
Conditions
Minimum
Typical
Maximum
Unit
VCCIO = 3.3 V
200
—
—
mV
VCCIO = 2.5 V
200
—
—
mV
VCCIO = 1.8 V
140
—
—
mV
VCCIO = 1.5 V
110
—
—
mV
I/O Standard Specifications
The following tables list input voltage sensitivities (VIH and VIL), output voltage
(VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O
standards supported by Cyclone III LS devices.
Table 2–13 through Table 2–18 provide Cyclone III LS devices I/O standard
specifications.
Table 2–13. Cyclone III LS Devices Single-Ended I/O Standard Specifications (1)
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
IOH
(mA)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
IOL
(mA)
3.135
3.3
3.465
—
0.8
1.7
3.6
0.45
2.4
4
–4
3.135
3.3
3.465
—
0.8
1.7
3.6
0.2
VCCIO – 0.2
2
–2
2.85
3.0
3.15
–0.3
0.8
1.7
VCCIO + 0.3
0.45
2.4
4
–4
2.85
3.0
3.15
–0.3
0.8
1.7
VCCIO + 0.3
0.2
VCCIO – 0.2
0.1
–0.1
2.5-V LVTTL and
LVCMOS (2)
2.375
2.5
2.625
–0.3
0.7
1.7
3.6
0.4
2.0
1
–1
1.8-V LVTTL and
LVCMOS
1.71
1.8
1.89
–0.3
0.35 *
VCCIO
0.65 *
VCCIO
2.25
0.45
VCCIO –
0.45
2
–2
1.5-V LVCMOS
1.425
1.5
1.575
–0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO + 0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
–2
1.2-V LVCMOS
1.14
1.2
1.26
–0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO + 0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
–2
PCI
2.85
3.0
3.15
—
0.30*
VCCIO
0.50*
VCCIO
VCCIO + 0.3 0.1 * VCCIO
0.9 * VCCIO
1.5
–0.5
PCI-X
2.85
3.0
3.15
—
0.35*
VCCIO
0.50*
VCCIO
VCCIO + 0.3 0.1 * VCCIO
0.9 * VCCIO
1.5
–0.5
I/O Standard
3.3-V LVTTL
(2)
3.3-V LVCMOS
3.0-V LVTTL
(2)
(2)
3.0-V LVCMOS
(2)
Notes to Table 2–13:
(1) AC load CL = 10 pF.
(2) For more information about interfacing Cyclone III LS devices with 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS I/O standards,
refer to AN 447: Interfacing Cyclone III and Cyclone iV Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
2–11
Table 2–14. Cyclone III LS Devices Single-Ended SSTL and HSTL I/O Reference Voltage Specifications (4)
I/O
Standard
VCCIO (V)
VREF (V)
VTT (V)
(3)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-2
Class I, II
2.375
2.5
2.625
1.19
1.25
1.31
VREF –
0.04
VREF
VREF +
0.04
SSTL-18
Class I, II
1.7
1.8
1.9
0.833
0.9
0.969
VREF –
0.04
VREF
VREF +
0.04
HSTL-18
Class I, II
1.71
1.8
1.89
0.85
0.9
0.95
0.85
0.9
0.95
HSTL-15
Class I, II
1.425
1.5
1.575
0.71
0.75
0.79
0.71
0.75
0.79
0.48 * VCCIO
HSTL-12
Class I, II
(1)
1.14
1.2
1.26
0.47 * VCCIO
(2)
0.5 * VCCIO
(1)
0.52 * VCCIO
(1)
0.5 *
VCCIO
—
0.5 * VCCIO
(2)
0.53 * VCCIO
(2)
—
Notes to Table 2–14:
(1) The value shown refers to the DC input reference voltage, VREF(DC).
(2) The value shown refers to the AC input reference voltage, VREF(AC).
(3) VTT of the transmitting device must track VREF of the receiving device.
(4) For an explanation of the terms used in Table 2–14, refer to “Glossary” on page 2–26.
Table 2–15. Cyclone III LS Devices Single-Ended SSTL and HSTL I/O Standards Signal Specifications
I/O
Standard
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
IOL
(mA)
IOH
(mA)
Min
Max
Min
Max
Min
Max
Min
Max
Max
Min
SSTL-2
Class I
—
VREF –
0.18
VREF +
0.18
—
—
VREF –
0.35
VREF +
0.35
—
VTT –
0.57
VTT +
0.57
8.1
–8.1
SSTL-2
Class II
—
VREF –
0.18
VREF +
0.18
—
—
VREF –
0.35
VREF +
0.35
—
VTT –
0.76
VTT +
0.76
16.4
–16.4
SSTL-18
Class I
—
VREF –
0.125
VREF +
0.125
—
—
VREF –
0.25
VREF +
0.25
—
VTT –
0.475
VTT +
0.475
6.7
–6.7
SSTL-18
Class II
—
VREF –
0.125
VREF +
0.125
—
—
VREF –
0.25
VREF +
0.25
—
0.28
VCCIO –
0.28
13.4
–13.4
HSTL-18
Class I
—
VREF –
0.1
VREF +
0.1
—
—
VREF –
0.2
VREF +
0.2
—
0.4
VCCIO –
0.4
8
–8
HSTL-18
Class II
—
VREF –
0.1
VREF +
0.1
—
—
VREF –
0.2
VREF +
0.2
—
0.4
VCCIO –
0.4
16
–16
HSTL-15
Class I
—
VREF –
0.1
VREF +
0.1
—
—
VREF –
0.2
VREF +
0.2
—
0.4
VCCIO –
0.4
8
–8
HSTL-15
Class II
—
VREF –
0.1
VREF +
0.1
—
—
VREF –
0.2
VREF +
0.2
—
0.4
VCCIO –
0.4
16
–16
HSTL-12
Class I
–0.15
VREF –
0.08
VREF +
0.08
VCCIO + 0.15 –0.24
VREF –
0.15
VREF +
0.15
VCCIO +
0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
8
–8
HSTL-12
Class II
–0.15
VREF –
0.08
VREF +
0.08
VCCIO + 0.15 –0.24
VREF –
0.15
VREF +
0.15
VCCIO +
0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
14
–14
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–12
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
f For more information about receiver input and transmitter output waveforms, and for
other differential I/O standards, refer to the High-Speed Differential Interfaces in
Cyclone III Devices chapter.
Table 2–16. Cyclone III LS Devices Differential SSTL I/O Standard Specifications (1)
I/O Standard
SSTL-2
Class I, II
SSTL-18
Class I, II
VSwing(DC)
(V)
VCCIO (V)
Min
Typ
Max
2.375
2.5
2.625 0.36 VCCIO VCCIO/2 – 0.2
1.7
1.8
Min
1.90
VSwing(AC)
(V)
VX(AC) (V)
Max
Min
VCCIO/2 –
0.175
0.25 VCCIO
Typ
Max
—
VCCIO/2
+ 0.2
—
VCCIO/2
+ 0.175
VOX(AC) (V)
Min Max
0.7
VCCI
0.5
VCCI
O
O
Min
Typ
Max
VCCIO/2 –
0.125
—
VCCIO/2
+ 0.125
VCCIO/2 –
0.125
—
VCCIO/2
+ 0.125
Note to Table 2–16:
(1) Differential SSTL requires a VREF input.
Table 2–17. Cyclone III LS Devices Differential HSTL I/O Standard Specifications (1)
VCCIO (V)
I/O Standard
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-18
Class I, II
1.71
1.8
1.89
0.2
—
0.85
—
0.95
0.85
—
0.95
0.4
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.2
—
0.71
—
0.79
0.71
—
0.79
0.4
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.16
VCCIO
0.48 *
VCCIO
—
0.52 *
VCCIO
0.48 *
VCCIO
—
0.52 *
VCCIO
0.3
0.48 *
VCCIO
Note to Table 2–17:
(1) Differential HSTL requires a VREF input.
Table 2–18. Differential I/O Standard Specifications (1) (Part 1 of 2)
I/O
Standard
LVPECL
(Row
I/Os) (3)
LVPECL
(Column
I/Os) (3)
LVDS
(Row
I/Os)
VCCIO (V)
Min
2.375
2.375
2.375
Typ
2.5
2.5
2.5
Cyclone III Device Handbook
Volume 2
VID (mV)
Max
2.625
2.625
2.625
VICM (V)
Min Max Min
100
100
100
—
—
—
Condition
VOD (mV)
Max Min Typ
0
DMAX500 Mbps
1.85
0.5
500 Mbps  DMAX
 700 Mbps
1.85
1
DMAX > 700 Mbps
1.6
0
DMAX 500 Mbps
1.85
0.5
500 Mbps  DMAX
700 Mbps
1.85
1
DMAX > 700 Mbps
1.6
0
(2)
VOS (V)
(2)
Max
Min
Typ
Max
—
—
—
—
—
—
—
—
—
—
—
—
DMAX 500 Mbps
1.85
0.5
500 Mbps  DMAX
 700 Mbps
1.85 247
—
600
1
DMAX > 700 Mbps
1.6
1.125 1.25 1.375
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Electrical Characteristics
2–13
Table 2–18. Differential I/O Standard Specifications (1) (Part 2 of 2)
I/O
Standard
LVDS
(Column
I/Os)
VCCIO (V)
Min
2.375
VID (mV)
Typ
2.5
Max
2.625
VICM (V)
Min Max Min
100
—
Condition
VOD (mV)
(2)
Max Min Typ
0
DMAX  500 Mbps
1.85
0.5
500 Mbps  DMAX
 700 Mbps
1.85 247
1
DMAX > 700 Mbps
1.6
VOS (V)
Max
—
600
Min
Typ
(2)
Max
1.125 1.25 1.35
BLVDS
(Row
I/Os) (4)
2.375
2.5
2.625
100 —
—
—
—
—
—
—
—
—
—
BLVDS
(Column
I/Os) (4)
2.375
2.5
2.625
100 —
—
—
—
—
—
—
—
—
—
mini-LVDS
2.375
(Row
I/Os) (5)
2.5
2.625
—
—
—
—
—
300
—
600
1.0
1.2
1.4
mini-LVDS
2.375
(Column
I/Os) (5)
2.5
2.625
—
—
—
—
—
300
—
600
1.0
1.2
1.4
RSDS
(Row
I/Os) (5)
2.375
2.5
2.625
—
—
—
—
—
100 200
600
0.5
1.2
1.5
RSDS
(Column
I/Os) (5)
2.375
2.5
2.625
—
—
—
—
—
100 200
600
0.5
1.2
1.5
PPDS
(Row
I/Os) (5)
2.375
2.5
2.625
—
—
—
—
—
100 200
600
0.5
1.2
1.4
PPDS
(Column
I/Os) (5)
2.375
2.5
2.625
—
—
—
—
—
100 200
600
0.5
1.2
1.4
Notes to Table 2–18:
(1) For an explanation of the terms used in Table 2–18, refer to “Transmitter Output Waveform” in “Glossary” on page 2–26.
(2) RL range: 90  RL  110  .
(3) The LVPECL input standard is only supported at clock input. The output standard is not supported.
(4) There is no fixed VICM, VOD , and VOS specification for BLVDS. They are dependent on the system topology.
(5) Mini-LVDS, RSDS, and PPDS standards are only supported at output pins of Cyclone III LS devices.
Power Consumption
Use the following methods to estimate power for your design:
July 2012
■
The Excel-based EPE
■
The Quartus II® PowerPlay power analyzer feature
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–14
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Use the interactive Excel-based EPE before designing your device to get a magnitude
estimate of the device power. The Quartus II PowerPlay power analyzer provides
better quality estimates based on the specifics of the design after place-and-route is
complete. The PowerPlay power analyzer can apply a combination of user-entered,
simulation-derived, and estimated signal activities which, combined with detailed
circuit models, can yield very accurate power estimates.
f For more information about power estimation tools, refer to the Early Power Estimator
User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II
Handbook.
Switching Characteristics
This section describes performance characteristics of the core and periphery blocks for
Cyclone III LS devices.
Core Performance Specifications
Table 2–19 through Table 2–25 describe the core performance specifications for
Cyclone III LS devices.
Clock Tree Specifications
Table 2–19 lists the clock tree specifications for Cyclone III LS devices.
Table 2–19. Cyclone III LS Devices Clock Tree Performance
Performance
Device
Unit
C7
C8
I7
EP3CLS70
437.5
402
437.5
MHz
EP3CLS100
437.5
402
437.5
MHz
EP3CLS150
437.5
402
437.5
MHz
EP3CLS200
437.5
402
437.5
MHz
PLL Specifications
Table 2–20 lists the PLL specifications for Cyclone III LS devices when operating in
the commercial junction temperature range (0°C to 85°C) and the industrial junction
temperature range (-40°C to 100°C). For more information about the PLL block, refer
to “PLL Block” in “Glossary” on page 2–26.
Table 2–20. Cyclone III LS Devices PLL Specifications (4) (Part 1 of 2)
Symbol
fIN
(1)
fINPFD
fVCO
(6)
fINDUTY
tINJITTER_CCJ
(5)
Cyclone III Device Handbook
Volume 2
Parameter
Min
Typ
Max
Unit
Input clock frequency
5
—
450
MHz
PFD input frequency
5
—
325
MHz
PLL internal VCO operating range
600
—
1300
MHz
Input clock duty cycle
40
—
60
%
Input clock cycle-to-cycle jitter for FINPFD  100 MHz
—
—
0.15
UI
Input clock cycle-to-cycle jitter for FINPFD < 100 MHz
—
—
±750
ps
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
2–15
Table 2–20. Cyclone III LS Devices PLL Specifications (4) (Part 2 of 2)
Symbol
Parameter
fOUT_EXT (external clock
output) (1)
PLL output frequency
Min
Typ
Max
Unit
—
—
450
MHz
PLL output frequency (–7 speed grade)
—
—
450
MHz
PLL output frequency (–8 speed grade)
—
—
402.5
MHz
tOUTDUTY
Duty cycle for external clock output (when set to
50%)
45
50
55
%
tLOCK
Time required to lock from end of device
configuration
—
—
1
ms
tDLOCK
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
—
—
1
ms
Dedicated clock output period jitter FOUT  100 MHz
—
—
300
ps
FOUT < 100 MHz
—
—
30
mUI
Dedicated clock output cycle-to-cycle jitter
FOUT  100 MHz
—
—
300
ps
FOUT < 100 MHz
—
—
30
mUI
Regular I/O period jitter FOUT  100 MHz
—
—
650
ps
FOUT < 100 MHz
—
—
75
mUI
fOUT (to global clock)
tOUTJITTER_PERIOD_DEDCLK
tOUTJITTER_CCJ_DEDCLK
tOUTJITTER_PERIOD_IO
(3)
(3)
(3)
Regular I/O cycle-to-cycle jitter FOUT  100 MHz
—
—
650
ps
FOUT < 100 MHz
—
—
75
mUI
tPLL_PSERR
Accuracy of PLL phase shift
—
—
±50
ps
tARESET
Minimum pulse width on areset signal.
10
—
—
ns
tCONFIGPLL
Time required to reconfigure scan chains for PLLs
—
—
scanclk
cycles
fSCANCLK
scanclk frequency
—
100
MHz
tOUTJITTER_CCJ_IO
(3)
3.5
(2)
—
Notes to Table 2–20:
(1) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) With 100-MHz scanclk frequency.
(3) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
(4) VCCD_PLL must be connected to VCCINT through the decoupling capacitor and ferrite bead.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less
than 200 ps.
(6) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–16
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Embedded Multiplier Specifications
Table 2–21 lists the embedded multiplier specifications for Cyclone III LS devices.
Table 2–21. Cyclone III LS Devices Embedded Multiplier Specifications
EP3CLS70, EP3CLS100,
EP3CLS150, and EP3CLS200
Performance
Resources Used
Mode
Unit
Number of Multipliers
C7 and I7
C8
9 × 9-bit multiplier
1
300
260
MHz
18 × 18-bit multiplier
1
250
200
MHz
Memory Block Specifications
Table 2–22 lists the M9K memory block and logic element (LE) specifications for
Cyclone III LS devices.
Table 2–22. Cyclone III LS Devices Memory Block Performance Specifications
EP3CLS70, EP3CLS100,
EP3CLS150, and EP3CLS200
Performance
Resources Used
Memory
M9K Block
Mode
Unit
LEs
M9K
Memory
C7 and I7
C8
FIFO 256 × 36
47
1
274
238
MHz
Single-port 256 × 36
0
1
274
238
MHz
Simple dual-port 256 × 36 CLK
0
1
274
238
MHz
True dual port 512 × 18 single CLK
0
1
274
238
MHz
Configuration and JTAG Specifications
Table 2–23 lists the configuration mode specifications for Cyclone III LS devices.
Table 2–23. Cyclone III LS Devices Configuration Mode Specifications
DCLK fMAX
Unit
Passive Serial (PS)
133
MHz
Fast Passive Parallel (FPP)
100
MHz
Programming Mode
Table 2–24 lists the active configuration mode specifications for Cyclone III LS
devices.
Table 2–24. Cyclone III LS Devices Active Configuration Mode Specifications
Programming Mode
Active Serial (AS)
Cyclone III Device Handbook
Volume 2
DCLK Range
Unit
20 to 40
MHz
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
2–17
Table 2–25 lists the JTAG timing parameters and values for Cyclone III LS devices.
Table 2–25. Cyclone III LS Devices JTAG Timing Parameters (1)
Symbol
Parameter
Min
Max
Unit
tJCP
TCK clock period
40
—
ns
tJCH
TCK clock high time
20
—
ns
tJCL
TCK clock low time
20
—
ns
tJPSU_TDI
JTAG port setup time for TDI
2
—
ns
tJPSU_TMS JTAG port setup time for TMS
3
—
ns
tJPH
JTAG port hold time
10
—
ns
tJPCO
JTAG port clock to output (2)
tJPZX
—
16
ns
output (2)
—
15
ns
impedance (2)
—
15
ns
JTAG port high impedance to valid
tJPXZ
JTAG port valid output to high
tJSSU
Capture register setup time
5
—
ns
tJSH
Capture register hold time
10
—
ns
tJSCO
Update register clock to output
—
25
ns
tJSZX
Update register high impedance to valid output
—
25
ns
tJSXZ
Update register valid output to high impedance
—
25
ns
Notes to Table 2–25:
(1) For more information, refer to “JTAG Waveform” in “Glossary” on page 2–26.
(2) The specification shown is for the 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For the 1.8-V
LVTTL/LVCMOS and the 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Periphery Performance
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several systems interfacing, for example, the high-speed
I/O interface, external memory interface, and PCI/PCI-X bus interface. I/O using
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using
general purpose I/O standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are
capable of typical 200 MHz interfacing frequency with 10 pF load.
1
July 2012
Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–18
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
High-Speed I/O Specification
Table 2–26 through Table 2–31 list the high-speed I/O timing for Cyclone III LS
devices. For more information about the definitions of high-speed timing
specifications, refer to “Glossary” on page 2–26.
Table 2–26. Cyclone III LS Devices RSDS Transmitter Timing Specification (1),
(2)
C7 and I7
Symbol
C8
Modes
Unit
Min
Typ
Max
Min
Typ
Max
×10
5
—
155.5
5
—
155.5
MHz
×8
5
—
155.5
5
—
155.5
MHz
×7
5
—
155.5
5
—
155.5
MHz
×4
5
—
155.5
5
—
155.5
MHz
×2
5
—
155.5
5
—
155.5
MHz
×1
5
—
311
5
—
311
MHz
×10
100
—
311
100
—
311
Mbps
×8
80
—
311
80
—
311
Mbps
×7
70
—
311
70
—
311
Mbps
×4
40
—
311
40
—
311
Mbps
×2
20
—
311
20
—
311
Mbps
×1
10
—
311
10
—
311
Mbps
tDUTY
—
45
—
55
45
—
55
%
TCCS
—
—
—
200
—
—
200
ps
Output jitter
(peak to peak)
—
—
—
500
—
—
550
ps
—
500
—
—
500
—
ps
—
500
—
—
500
—
ps
—
—
1
—
—
1
ms
fHSCLK
(input clock
frequency)
Device operation
in Mbps
20 – 80%,
tRISE
CLOAD = 5 pF
20 – 80%,
tFALL
tLOCK
CLOAD = 5 pF
(3)
—
Notes to Table 2–26:
(1) Applicable for true RSDS and Emulated RSDS with three-resistor network transmitters.
(2) True RSDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS with three-resistor network
transmitter is supported at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
2–19
Table 2–27. Cyclone III LS Devices Emulated RSDS with One-Resistor Network Transmitter Timing
Specifications (1)
C7 and I7
Symbol
C8
Modes
Unit
Min
Typ
Max
Min
Typ
Max
×10
5
—
85
5
—
85
MHz
×8
5
—
85
5
—
85
MHz
×7
5
—
85
5
—
85
MHz
×4
5
—
85
5
—
85
MHz
×2
5
—
85
5
—
85
MHz
×1
5
—
170
5
—
170
MHz
×10
100
—
170
100
—
170
Mbps
×8
80
—
170
80
—
170
Mbps
×7
70
—
170
70
—
170
Mbps
×4
40
—
170
40
—
170
Mbps
×2
20
—
170
20
—
170
Mbps
×1
10
—
170
10
—
170
Mbps
tDUTY
—
45
—
55
45
—
55
%
TCCS
—
—
—
200
—
—
200
ps
Output jitter
(peak to
peak)
—
—
—
500
—
—
550
ps
—
500
—
—
500
—
ps
—
500
—
—
500
—
ps
—
—
1
—
—
1
ms
fHSCLK (input
clock
frequency)
Device
operation in
Mbps
20 – 80%,
tRISE
CLOAD = 5 pF
20 – 80%,
tFALL
CLOAD = 5 pF
tLOCK
(2)
—
Notes to Table 2–27:
(1) Emulated RSDS with one-resistor network transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification (1),
C7 and I7
Symbol
fHSCLK (input
clock frequency)
July 2012
Altera Corporation
(2)
(Part 1 of 2)
C8
Modes
Unit
Min
Typ
Max
Min
Typ
Max
×10
5
—
155.5
5
—
155.5
MHz
×8
5
—
155.5
5
—
155.5
MHz
×7
5
—
155.5
5
—
155.5
MHz
×4
5
—
155.5
5
—
155.5
MHz
×2
5
—
155.5
5
—
155.5
MHz
×1
5
—
311
5
—
311
MHz
Cyclone III Device Handbook
Volume 2
2–20
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification (1),
C7 and I7
Symbol
(2)
(Part 2 of 2)
C8
Modes
Unit
Min
Typ
Max
Min
Typ
Max
×10
100
—
311
100
—
311
Mbps
×8
80
—
311
80
—
311
Mbps
×7
70
—
311
70
—
311
Mbps
×4
40
—
311
40
—
311
Mbps
×2
20
—
311
20
—
311
Mbps
×1
10
—
311
10
—
311
Mbps
tDUTY
—
45
—
55
45
—
55
%
TCCS
—
—
—
200
—
—
200
ps
Output jitter
(peak to peak)
—
—
—
500
—
—
550
ps
—
500
—
—
500
—
ps
—
500
—
—
500
—
ps
—
—
1
—
—
1
ms
Device operation
in Mbps
20 – 80%,
tRISE
CLOAD = 5 pF
20 – 80%,
tFALL
tLOCK
CLOAD = 5 pF
(3)
—
Notes to Table 2–28:
(1) Applicable for true and emulated mini-LVDS with three-resistor network transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS with three-resistor
network transmitter is supported at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
2–21
Table 2–29. Cyclone III LS Devices True LVDS Transmitter Timing Specifications (1)
C7 and I7
Symbol
fHSCLK (input
clock frequency)
C8
Modes
Unit
Min
Max
Min
Max
×10
5
370
5
320
MHz
×8
5
370
5
320
MHz
×7
5
370
5
320
MHz
×4
5
370
5
320
MHz
×2
5
370
5
320
MHz
×1
5
402.5
5
402.5
MHz
×10
100
740
100
640
Mbps
×8
80
740
80
640
Mbps
×7
70
740
70
640
Mbps
×4
40
740
40
640
Mbps
×2
20
740
20
640
Mbps
×1
10
402.5
10
402.5
Mbps
tDUTY
—
45
55
45
55
%
TCCS
—
—
200
—
200
ps
Output jitter
(peak to peak)
—
—
500
—
550
ps
—
—
1
—
1
ms
HSIODR
tLOCK
(2)
Notes to Table 2–29:
(1) True LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6).
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter
Timing Specifications (1) (Part 1 of 2)
C7 and I7
Symbol
fHSCLK (input
clock frequency)
HSIODR
tDUTY
July 2012
Altera Corporation
C8
Modes
Unit
Min
Max
Min
Max
×10
5
320
5
275
MHz
×8
5
320
5
275
MHz
×7
5
320
5
275
MHz
×4
5
320
5
275
MHz
×2
5
320
5
275
MHz
×1
5
402.5
5
402.5
MHz
×10
100
640
100
550
Mbps
×8
80
640
80
550
Mbps
×7
70
640
70
550
Mbps
×4
40
640
40
550
Mbps
×2
20
640
20
550
Mbps
×1
10
402.5
10
402.5
Mbps
—
45
55
45
55
%
Cyclone III Device Handbook
Volume 2
2–22
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter
Timing Specifications (1) (Part 2 of 2)
C7 and I7
Symbol
C8
Modes
Unit
Min
Max
Min
Max
TCCS
—
—
200
—
200
ps
Output jitter
(peak to peak)
—
—
500
—
550
ps
—
—
1
—
1
ms
tLOCK
(2)
Notes to Table 2–30:
(1) Emulated LVDS with three-resistor network transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–31. Cyclone III LS Devices LVDS Receiver Timing Specifications (1)
C7 and I7
Symbol
C8
Modes
Unit
Min
Max
Min
Max
×10
5
370
5
320
MHz
×8
5
370
5
320
MHz
×7
5
370
5
320
MHz
×4
5
370
5
320
MHz
×2
5
370
5
320
MHz
×1
5
402.5
5
402.5
MHz
×10
100
740
100
640
Mbps
×8
80
740
80
640
Mbps
×7
70
740
70
640
Mbps
×4
40
740
40
640
Mbps
×2
20
740
20
640
Mbps
×1
10
402.5
10
402.5
Mbps
SW
—
—
400
—
400
%
Input jitter
tolerance
—
—
500
—
550
ps
—
—
1
—
1
ps
fHSCLK (input
clock frequency)
HSIODR
tLOCK
(2)
Notes to Table 2–31:
(1) True LVDS receiver is supported at all banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
External Memory Interface Specifications
Cyclone III LS devices support external memory interfaces up to 200 MHz. The
external memory interfaces for Cyclone III LS devices are auto-calibrating and easy to
implement.
Table 2–32 and Table 2–33 list the external memory interface specifications for
Cyclone III LS devices and are useful when performing memory interface timing
analysis.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
2–23
f For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to Literature: External Memory Interfaces.
Table 2–32. FPGA Sampling Window (SW) Requirement—Read Side (1)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory Standard
Setup
Hold
Setup
Hold
Setup
Hold
770
715
985
930
C7
DDR2 SDRAM
705
650
DDR SDRAM
675
620
795
740
970
915
QDRII SRAM
900
845
910
855
1085
1030
C8
DDR2 SDRAM
785
720
930
870
1115
1055
DDR SDRAM
800
740
915
855
1185
1125
QDRII SRAM
1050
990
1065
1005
1210
1150
855
800
1040
985
I7
DDR2 SDRAM
765
710
DDR SDRAM
745
690
880
825
1000
945
QDRII SRAM
945
890
955
900
1130
1075
Note to Table 2–32:
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Table 2–33. Cyclone III LS Devices Transmitter Channel-to-Channel Skew (TCCS)—Write Side (1) (Part 1 of 2)
Column I/Os (ps)
Memory Standard
Row I/Os (ps)
Wraparound Mode (ps)
I/O Standard
Lead
Lag
Lead
Lag
Lead
Lag
C7
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I
915
410
915
410
1015
510
SSTL-18 Class II
1025
545
1025
545
1125
645
SSTL-2 Class I
880
340
880
340
980
440
SSTL-2 Class II
1010
380
1010
380
1010
480
1.8-V HSTL Class I
910
450
910
450
1010
550
1.8-V HSTL Class II
1010
570
1010
570
1110
670
C8
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
July 2012
SSTL-18 Class I
1040
440
1040
440
1140
540
SSTL-18 Class II
1180
600
1180
600
1280
700
SSTL-2 Class I
1010
360
1010
360
1110
460
SSTL-2 Class II
1160
410
1160
410
1260
510
1.8-V HSTL Class I
1040
490
1040
490
1140
590
1.8-V HSTL Class II
1190
630
1190
630
1290
730
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–24
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
Table 2–33. Cyclone III LS Devices Transmitter Channel-to-Channel Skew (TCCS)—Write Side (1) (Part 2 of 2)
Column I/Os (ps)
Memory Standard
Row I/Os (ps)
Wraparound Mode (ps)
I/O Standard
Lead
Lag
Lead
Lag
Lead
Lag
I7
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I
961
431
961
431
1061
531
SSTL-18 Class II
1076
572
1076
572
1176
672
SSTL-2 Class I
924
357
924
357
1024
457
SSTL-2 Class II
1061
399
1061
399
1161
499
1.8-V HSTL Class I
956
473
956
473
1056
573
1.8-V HSTL Class II
1061
599
1061
599
1161
699
Note to Table 2–33:
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
Table 2–34 lists the Cyclone III LS devices memory ouput clock jitter specifications.
Table 2–34. Cyclone III LS Devices Memory Output Clock Jitter Specifications (1),
Parameter
Symbol
(2)
Min
Max
Unit
Clock period jitter
tJIT (per)
–125
125
ps
Cycle-to-cycle period jitter
tJIT (cc)
–200
200
ps
Duty cycle jitter
tJIT (duty)
–150
150
ps
Notes to Table 2–34:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
Duty Cycle Distortion Specification
Table 2–35 lists the worst case duty cycle distortion for Cyclone III LS devices.
Table 2–35. Duty Cycle Distortion on Cyclone III LS Devices I/O Pins (1),
C7, I7
(2)
C8
Symbol
Output Duty Cycle
Unit
Min
Max
Min
Max
45
55
45
55
%
Notes to Table 2–35:
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and I/O element
(IOE) driving the dedicated and general purpose I/O pins.
(2) Cyclone III LS devices meet the DCD specifications at the maximum output toggle rate for each combination of
the I/O standard and current strength.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Switching Characteristics
2–25
OCT Calibration Timing Specification
Table 2–36 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone III LS devices.
Table 2–36. Cyclone III LS Devices Timing Specification for Series OCT with Calibration at Device
Power-Up (1)
Symbol
Description
Duration of series OCT with
calibration at device power-up
tOCTCAL
Maximum
Unit
20
µs
Note to Table 2–36:
(1) OCT calibration takes place after device configuration, before entering user mode.
IOE Programmable Delay
Table 2–37 and Table 2–38 list the IOE programmable delay for Cyclone III LS devices.
Table 2–37. Cyclone III LS Devices IOE Programmable Delay on the Column Pins
(1), (2)
Max Offset
Parameter
Paths Affected
Number
of
setting
Min
Offset
Fast Corner
I7
C7
Slow Corner
C7
C8
Unit
I7
Input delay from the pin to the
internal cells
Pad to I/O
dataout to core
7
0
1.211 1.314 2.339 2.416 2.397
ns
Input delay from the pin to the
input register
Pad to I/O input
register
8
0
1.203 1.307 2.387 2.540 2.430
ns
Delay from the output register to
the output pin
I/O output
register to pad
2
0
0.518 0.559 1.065 1.151 1.082
ns
Input delay from the
dual-purpose clock pin to the
fan-out destinations
Pad to global
clock network
12
0
0.533
ns
0.56
1.077 1.182 1.087
Notes to Table 2–37:
(1) The incremental values for the settings are generally linear. For the exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers refer to the 0 setting available in the Quartus II software.
Table 2–38. Cyclone III LS Devices IOE Programmable Delay on Row Pins (1),
(2)
Max Offset
Parameter
Paths Affected
Number
of
setting
Min
Offset
Fast Corner
I7
C7
Slow Corner
C7
C8
Unit
I7
Input delay from the pin to the
internal cells
Pad to I/O
dataout to core
7
0
1.209 1.314 2.352 2.514 2.432
ns
Input delay from the pin to the
input register
Pad to I/O input
register
8
0
1.207 1.312 2.402 2.558 2.447
ns
Delay from the output register to
the output pin
I/O output
register to pad
2
0
0.549 0.595 1.135 1.226 1.151
ns
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–26
Chapter 2: Cyclone III LS Device Datasheet
I/O Timing
Table 2–38. Cyclone III LS Devices IOE Programmable Delay on Row Pins (1),
(2)
Max Offset
Parameter
Paths Affected
Input delay from the
dual-purpose clock pin to the
fan-out destinations
Pad to global
clock network
Number
of
setting
12
Min
Offset
Fast Corner
0
Slow Corner
Unit
I7
C7
C7
C8
I7
0.52
0.54
1.052
1.16
1.061
ns
Notes to Table 2–38:
(1) The incremental values for the settings are generally linear. For the exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers refer to the 0 setting available in the Quartus II software.
I/O Timing
DirectDrive technology and MultiTrack interconnect ensure predictable performance,
accurate simulation, and accurate timing analysis across all Cyclone III LS device
densities and speed grades.
Use the following methods to determine I/O timing:
■
The Excel-based I/O timing
■
The Quartus II Timing Analyzer
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used before designing the FPGA to get a timing
budget estimation as part of the link timing analysis. The Quartus II Timing Analyzer
provides a more accurate and precise I/O timing data based on the specifics of the
design after place-and-route is complete.
f For more information about the Excel-based I/O timing spreadsheet, refer to the
Cyclone III Devices Literature page on the Altera website.
All specifications are representative of worst-case supply voltage and junction
temperature conditions. Altera characterizes timing delays at the worst-case process,
minimum voltage, and maximum temperature for input register setup time (tSU) and
hold time (tH).
f For more information about timing delay from the FPGA output to the receiving
device for system-timing analysis, refer to AN 366: Understanding I/O Output Timing
for Altera Devices.
Glossary
Table 2–39 lists the glossary for this chapter.
Table 2–39. Glossary (Part 1 of 6)
Letter
Term
Definitions
A
—
—
B
—
—
C
—
—
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Glossary
2–27
Table 2–39. Glossary (Part 2 of 6)
Letter
Term
Definitions
D
—
—
E
—
—
F
fHSCLK
High-speed I/O Block: High-speed receiver and transmitter input and output clock frequency.
GCLK
Input pin directly to the global clock network.
GCLK PLL
Input pin to the global clock network through the PLL.
H
HSIODR
High-speed I/O Block: Maximum and minimum LVDS data transfer rate (HSIODR = 1/TUI).
I
Input Waveforms
for the SSTL
Differential I/O
Standard
G
VIH
VSWING
VREF
VIL
TMS
TDI
t JCP
t JCH
t JPSU_TDI
t JPSU_TMS
t JCL
t JPH
TCK
J
JTAG Waveform
tJPZX
t JPXZ
t JPCO
TDO
tJSSU
Signal
to be
Captured
tJSZX
t JSH
t JSCO
t JSXZ
Signal
to be
Driven
K
—
—
L
—
—
M
—
—
N
—
—
O
—
—
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–28
Chapter 2: Cyclone III LS Device Datasheet
Glossary
Table 2–39. Glossary (Part 3 of 6)
Letter
Term
Definitions
The following block diagram highlights the PLL specification parameters.
CLKOUT Pins
Switchover
fOUT _EXT
CLK
fIN
N
fINPFD
PFD
CP
LF
VCO fVCO
Counters
C0..C4
Core Clock
P
PLL Block
fOUT
GCLK
Phase tap
M
Key
Reconfigurable in User Mode
Q
—
RL
—
Receiver differential input discrete resistor (external to the Cyclone III LS device)
Receiver Input Waveform for LVDS and LVPECL Differential Standards
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
R
Ground
Receiver Input
Waveform
Differential Input Waveform
VID
0V
VID
p -n
RSKM (Receiver
input skew
margin)
Cyclone III Device Handbook
Volume 2
High-speed I/O Block: The total margin left after accounting for the sampling window and
TCCS. RSKM = (TUI – SW – TCCS) / 2
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Glossary
2–29
Table 2–39. Glossary (Part 4 of 6)
Letter
Term
Definitions
VCCIO
VOH
VIH (AC )
VIH(DC)
VREF
VIL(DC)
VIL(AC )
S
Single-ended
Voltage
referenced I/O
Standard
VOL
VSS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values.
■
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications.
■
The DC values indicate the voltage levels at which the final logic state of the receiver is
unambiguously defined.
After the receiver input crosses the AC value, the receiver changes to the new logic state. The
new logic state is then maintained as long as the input stays beyond the DC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing.
T
July 2012
SW (Sampling
Window)
High-speed I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling
window.
tC
High-speed receiver and transmitter input and output clock period.
TCCS (Channelto-channel-skew)
High-speed I/O Block: The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS measurement.
tcin
Delay from the clock pad to the I/O input register.
tCO
Delay from the clock pad to the I/O output.
tcout
Delay from the clock pad to the I/O output register.
tDUTY
High-speed I/O Block: Duty cycle on the high-speed transmitter output clock.
tFALL
Signal high-to-low transition time (80 to 20%).
tH
Input register hold time.
Timing Unit
Interval (TUI)
High-speed I/O block: The timing budget allowed for skew, propagation delays, and the data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER
Period jitter on the PLL clock input.
tOUTJITTER_DEDCLK
Period jitter on the dedicated clock output driven by a PLL.
tOUTJITTER_IO
Period jitter on the general purpose I/O driven by a PLL.
tpllcin
Delay from the PLL inclk pad to the I/O input register.
tpllcout
Delay from the PLL inclk pad to the I/O output register.
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–30
Chapter 2: Cyclone III LS Device Datasheet
Glossary
Table 2–39. Glossary (Part 5 of 6)
Letter
Term
Definitions
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS, and RSDS differential I/O
standards
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
Vos
Transmitter
Output Waveform
Ground
Differential Waveform (Mathematical Function of Positive & Negative Channel)
VOD
0V
VOD
p − n (1)
Signal low-to-high transition time (20–80%).
tRISE
tSU
U
Input register setup time.
—
Cyclone III Device Handbook
Volume 2
—
July 2012 Altera Corporation
Chapter 2: Cyclone III LS Device Datasheet
Glossary
2–31
Table 2–39. Glossary (Part 6 of 6)
Letter
Term
Definitions
VCM(DC)
DC common mode input voltage.
VDIF(AC)
AC differential Input Voltage—The minimum AC input differential voltage required for
switching.
VDIF(DC)
DC differential Input Voltage—The minimum DC input differential voltage required for
switching.
VICM
Input Common Mode Voltage—The common mode of the differential signal at the receiver.
VID
Input differential Voltage Swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VIH
Voltage Input High—The minimum positive voltage applied to the input that is accepted by
the device as a logic high.
VIH(AC)
High-level AC input voltage.
VIH(DC)
High-level DC input voltage.
VIL
Voltage Input Low—The maximum positive voltage applied to the input that is accepted by
the device as a logic low.
VIL (AC)
Low-level AC input voltage.
VIL (DC)
Low-level DC input voltage.
VIN
DC input voltage.
VOCM
Output Common Mode Voltage—The common mode of the differential signal at the
transmitter.
VOD
Output differential Voltage Swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter. VOD = VOH – VOL.
VOH
Voltage Output High—The maximum positive voltage from an output that the device
considers will be accepted as the minimum positive high level.
VOL
Voltage Output Low—The maximum positive voltage from an output that the device considers
will be accepted as the maximum positive low level.
VOS
Output offset voltage—VOS = (VOH + VOL) / 2.
VOX (AC)
AC differential Output cross point voltage—The voltage at which the differential output signals
must cross.
VREF
Reference voltage for the SSTL and HSTL I/O standards.
VREF (AC)
AC input reference voltage for the SSTL and HSTL I/O standards. VREF(AC) = VREF(DC) + noise.
The peak-to-peak AC noise on VREF must not exceed 2% of VREF(DC).
VREF (DC)
DC input reference voltage for the SSTL and HSTL I/O standards.
VSWING (AC)
AC differential Input Voltage—AC Input differential voltage required for switching. Refer to
Input Waveforms for the SSTL Differential I/O Standard.
VSWING (DC)
DC differential Input Voltage—DC Input differential voltage required for switching. Refer to
Input Waveforms for the SSTL Differential I/O Standard.
VTT
Termination voltage for the SSTL and HSTL I/O standards.
VX (AC)
AC differential Input cross point Voltage—The voltage at which the differential input signals
must cross.
V
W
—
—
X
—
—
Y
—
—
Z
—
—
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
2–32
Chapter 2: Cyclone III LS Device Datasheet
Document Revision History
Document Revision History
Table 2–40 lists the revision history for this document.
Table 2–40. Document Revision History
Date
Version
July 2012
December 2011
1.4
1.3
Changes
■
Updated minimum fHSCLK value to 5 MHz.
■
Updated absolute maximum TJ to 125 °C in Table 2–1.
■
Finalized all preliminary information.
■
Updated “Supply Current” on page 2–5, “Periphery Performance” on page 2–17, and
“External Memory Interface Specifications” on page 2–22.
■
Updated Table 2–1, Table 2–3, Table 2–13, Table 2–16, Table 2–17, Table 2–20, and
Table 2–25.
■
Updated Table 2–19 through Table 2–34, Table 2–37, and Table 2–38.
December 2009
1.2
■
Updated the “Periphery Performance” on page 2–17 section.
■
Minor changes to the text.
July 2009
1.1
Minor edit to the hyperlinks.
June 2009
1.0
Initial release.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement