32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash S29CD032J S29CD016J

32/16 Mbit, 2.6/3.3 V,  Dual Boot, Simultaneous Read/Write, Burst Flash S29CD032J S29CD016J

S29CD032J

S29CD016J

S29CL032J

S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot,

Simultaneous Read/Write, Burst Flash

General Description

The Spansion S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process technology. These burstmode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks, using separate data and address pins. These products can operate up to 75 MHz (32 Mb) or 66 MHz (16 Mb), and use a single V

CC of 2.5V to 2.75V (S29CD-J) or 3.0V to 3.6V (S29CL-J) that make them ideal for today’s demanding automotive applications.

Distinctive Characteristics

 Single 2.6V (S29CD-J) or 3.3V (S29CL-J) for read/program/erase

 110 nm Floating Gate Technology

 Simultaneous Read/Write operation with zero latency

 x32 Data Bus

 Dual Boot Sector Configuration (top and bottom)

 Flexible Sector Architecture

– CD016J and CL016J: Eight 2k Double word, Thirty 16k Double word, and Eight 2k Double Word sectors

– CD032J and CL032J: Eight 2k Double word, Sixty-two 16k

Double Word, and Eight 2k Double Word sectors

 VersatileI/O™ control (1.65V to 3.6V)

 Programmable Burst Interface

– Linear for 2, 4, and 8 double word burst with wrap around

 Secured Silicon Sector that can be either factory or customer locked

 20 year data retention (typical)

 Cycling Endurance: 1 million write cycles per sector (typical)

 Command set compatible with JEDEC (JC42.4) standard

 Supports Common Flash Interface (CFI)

 Extended Temperature range

 Persistent and Password methods of Advanced Sector Protection

 Unlock Bypass program command to reduce programming time

 ACC input pin to reduce factory programming time

 Data Polling bits indicate program and erase operation completion

 Hardware (WP#) protection of two outermost sectors in the large bank

 Ready/Busy (RY/BY#) output indicates data available to system

 Suspend and Resume commands for Program and Erase Operation

 Offered Packages

– 80-pin PQFP

– 80-ball Fortified BGA (13 x 11 mm and 11 x 9mm versions)

– Pb-free package option available

– Known Good Die

Performance Characteristics

Speed Option (MHz)

Read Access Times

75

(32 Mb only)

Max Asynch. Access Time, ns (t

ACC

)

Max Synch. Burst Access, ns (t

BACC

)

Min Initial Clock Delay (clock cycles)

Max CE# Access Time, ns (t

CE

)

Max OE# Access time, ns (t

OE

)

54

8

5

54

20

66

54

8

5

54

20

56

54

8

5

54

20

40

54

8

4

54

20

Current Consumption (Max values)

Continuous Burst Read @ 75 MHz

Program

Erase

Standby Mode

90 mA

50 mA

50 mA

60 µA

Typical Program and Erase Times

Double Word Programming

Sector Erase

18 µs

1.0 s

Notice for the 32Mb S29CD-J and S29CL-J devices only:

Please refer to the application note “Recommended Mode of Operation for Spansion

®

110 nm S29CD032J/S29CL032J Flash

Memory” publication number S29CD-CL032J_Recommend_AN for programming best practices.

Cypress Semiconductor Corporation

• 198 Champion Court

Document Number: 002-00948 Rev. *A

• San Jose

,

CA 95134-1709 • 408-943-2600

Revised December 16, 2015

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Contents

1.

Ordering Information ................................................... 3

1.1

Valid Combinations ........................................................ 4

2.

Input/Output Descriptions and Logic Symbols......... 5

3.

Block Diagram.............................................................. 6

4.

Block Diagram of Simultaneous Read/Write Circuit. 7

5.

Physical Dimensions/Connection Diagrams............. 8

5.1

80-Pin PQFP Connection Diagram ................................ 8

5.2

PQR080–80-Lead Plastic Quad Flat Package Physical Dimensions........................................................................ 9

5.3

80-Ball Fortified BGA Connection Diagrams................ 10

5.4

Special Package Handling Instructions........................ 10

5.5

LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm)

Physical Dimensions.................................................... 11

5.6

LAD080–80-ball Fortified Ball Grid Array (11 x 9 mm)

Physical Dimensions.................................................... 12

6.

Additional Resources ................................................ 13

6.1

Application Notes ......................................................... 13

6.2

Specification Bulletins .................................................. 13

6.3

Hardware and Software Support.................................. 13

6.4

Contacting Spansion.................................................... 13

7.

Product Overview ...................................................... 14

7.1

Memory Map ................................................................ 14

8.

Device Operations ..................................................... 19

8.1

Device Operation Table ............................................... 19

8.2

Asynchronous Read..................................................... 20

8.3

Hardware Reset (RESET#).......................................... 20

8.4

Synchronous (Burst) Read Mode and Configuration

Register........................................................................ 21

8.5

Autoselect .................................................................... 25

8.6

VersatileI/O (V

IO

) Control............................................. 26

8.7

Program/Erase Operations .......................................... 26

8.8

Write Operation Status................................................. 31

8.9

Reset Command .......................................................... 37

9.

Advanced Sector Protection/Unprotection ............. 37

9.1

Advanced Sector Protection Overview ........................ 39

9.2

Persistent Protection Bits............................................. 39

9.3

Persistent Protection Bit Lock Bit................................. 41

9.4

Dynamic Protection Bits............................................... 41

9.5

Password Protection Method ....................................... 42

9.6

Hardware Data Protection Methods............................. 43

10.

Secured Silicon Sector Flash Memory Region ....... 44

10.1 Secured Silicon Sector Protection Bit .......................... 45

10.2 Secured Silicon Sector Entry and Exit Commands...... 45

11.

Electronic Marking..................................................... 45

12.

Power Conservation Modes...................................... 45

12.1 Standby Mode.............................................................. 45

12.2 Automatic Sleep Mode................................................. 46

12.3 Hardware RESET# Input Operation............................. 46

12.4 Output Disable (OE#)................................................... 46

13.

Electrical Specifications............................................. 47

13.1 Absolute Maximum Ratings .......................................... 47

14.

Operating Ranges ....................................................... 48

15.

DC Characteristics...................................................... 48

15.1 Zero Power Flash.......................................................... 49

16.

Test Conditions ........................................................... 50

17.

Test Specifications ..................................................... 50

17.1 Switching Waveforms ................................................... 50

18.

AC Characteristics...................................................... 51

18.1 V

CC

and V

IO

Power-up.................................................. 51

18.2 Asynchronous Operations............................................. 52

18.3 Synchronous Operations .............................................. 54

18.4 Hardware Reset (RESET#)........................................... 56

18.5 Write Protect (WP#) ...................................................... 57

18.6 Erase/Program Operations ........................................... 57

18.7 Alternate CE# Controlled Erase/Program Operations .. 64

18.8 Erase and Programming Performance ......................... 66

18.9 PQFP and Fortified BGA Pin Capacitance ................... 66

19.

Appendix 1 .................................................................. 67

19.1 Common Flash Memory Interface (CFI) ....................... 67

20.

Appendix 2 .................................................................. 71

20.1 Command Definitions.................................................... 71

21.

Revision History.......................................................... 73

Document Number: 002-00948 Rev. *A Page 2 of 86

1.

Ordering Information

The order number (Valid Combination) is formed by the following:

S29CD032J

S29CL032J 0 J F A I 0 0 0

Packing Type

0 = Tray, FBGA: 180 per tray, min. 10 trays per box

Tray, PQFP: 66 per tray, min. 10 trays per box

2 = 7” Tape and Reel, FBGA: 400 per reel

3 = 13” Tape and Reel, FBGA: 1600 per reel

13” Tape and Reel, PQFP: 500 per reel

Boot Sector Option (16th Character)

0 = Top Boot with Simultaneous Operation

1 = Bottom Boot with Simultaneous Operation

2 = Top Boot without Simultaneous Operation

3 = Bottom Boot without Simultaneous Operation

Autoselect ID Option (15th Character)

0 = 7E, 08, 01/00 Autoselect ID

1 = 7E, 36, 01/00 Autoselect ID

0 = 7E, 46, 01/00 Autoselect ID

0 = 7E, 09, 01/00 Autoselect ID

0 = 7E, 49, 01/00 Autoselect ID

Temperature Range

I = Industrial (–40°C to +85°C)

M = Extended (–40°C to +125°C)

S29CD016J only

S29CL016J only

S29CD032J only

S29CL032J only

Material Set

A = Standard

F = Pb-free Option

Package Type

Q = Plastic Quad Flat Package (PQFP)

F = Fortified Ball Grid Array, 1.0 mm pitch package, 13 x 11 mm package

B = Fortified Ball Grid Array, 1.0 mm pitch package, 11 x 9 mm package

Clock Frequency (11th Character)

M = 56 MHz

Initial Burst Access Delay (10th Character)

0 = 5-1-1-1, 6-1-1-1, and above

Device Number/Description

S29CD032J/S29CD016J (2.5 volt-only), S29CL032J/S29CL016J (3.3 volt-only)

32 or 16 Megabit (1M or 512k x 32-Bit) CMOS Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory

Manufactured on 110 nm floating gate technology

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document Number: 002-00948 Rev. *A Page 3 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

1.1

Valid Combinations

Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Device

Number

S29CD016J

S29CL016J

S29CD032J

S29CL032J

Initial Burst

Access Delay

0, 1

0

0, 1

0

0, 1

0

0, 1

0

Clock

Frequency

J

M, P

J

M, P

J

M, P

B, F

Q

B, F

Q

B, F

Q

B, F

S29CD-J/CL-J Valid Combinations

Package

Type

Q

Material

Set

Temperature

Range

B, F

Q

B, F

Q

A, F I, M

Q

R

B, F

Autoselect ID

Option

0, 1

0

J

M, P

R

Q

B, F

Q

B, F

Q

B, F

Boot Sector

Option

0, 1, 2, 3

0, 2, 3

0, 3

0, 2, 3

0, 3

0, 2, 3

0, 3

0, 2, 3

Packing

Type

0, 3

0, 2, 3

0, 3

0, 2, 3

0, 3

0, 1 (2)

2, 3

0, 1 (2)

2, 3

0, 3

0, 2, 3

0, 1, 2, 3

0, 3

0, 2, 3

0, 3

0, 2, 3

0, 1 (2)

2, 3

0, 1 (2)

2, 3

0, 3

0, 2, 3

Notes:

1. The ordering part number that appears on BGA packages omits the leading “S29”.

2. Contact factory for availability.

Document Number: 002-00948 Rev. *A Page 4 of 86

2.

Input/Output Descriptions and Logic Symbols

Table identifies the input and output package connections provided on the device.

Symbol Type

A19-A0

DQ31-DQ0

CE#

OE#

WE#

V

CC

V

IO

V

SS

NC

RY/BY#

CLK

ADV#

IND#

WAIT#

WP#

ACC

RESET#

Input

I/O

Input

Input

Input

Supply

Supply

Supply

No Connect

Output

Input

Input

Output

Output

Input

Input

Input

Description

Address lines for S29CD-J and S29CL-J (A18-A0 for 16 Mb and A19-A0 for 32 Mb).

A9 supports 12V autoselect input.

Data input/output

Chip Enable. This signal is asynchronous relative to CLK for the burst mode.

Output Enable. This signal is asynchronous relative to CLK for the burst mode.

Write Enable

Device Power Supply. This signal is asynchronous relative to CLK for the burst mode.

VersatileI/O

TM

Input.

Ground

Not connected internally

Ready/Busy output and open drain which require a external pull up resistor.

When RY/BY# = V

OH

, the device is ready to accept read operations and commands.

When RY/BY# = V

OL

, the device is either executing an embedded algorithm or the device is executing a hardware reset operation.

Clock Input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency.

Load Burst Address input. Indicates that the valid address is present on the address inputs.

End of burst indicator for finite bursts only. IND is low when the last word in the burst sequence is at the data outputs.

Provides data valid feedback only when the burst length is set to continuous.

Write Protect Input. At V

IL sectors of the large bank.

, disables program and erase functions in two outermost

Acceleration input. At V

HH

, accelerates erasing and programming. When not used for acceleration, ACC = V

SS

or V

CC

.

Hardware Reset.

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document Number: 002-00948 Rev. *A Page 5 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

3.

Block Diagram

V

CC

V

SS

WE#

RESET#

ACC

WP#

State

Control

Command

Register

CE#

OE#

PGM Voltage

Generator

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

V

IO

DQ max

DQ0

Input/Output

Buffers

Data

Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

ADV#

CLK

Amax-A0

V

CC

Detector

Timer

Burst

State

Control

IND/

WAIT#

Burst

Address

Counter

Amax-A0

Note

Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0.

Document Number: 002-00948 Rev. *A Page 6 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

4.

Block Diagram of Simultaneous Read/Write Circuit

OE#

V

CC

V

SS

A max

–A0

Upper Bank Address

Upper Bank

A max

–A0

RESET#

WE#

CE#

ADV#

DQ max

–DQ0

STATE

CONTROL

&

COMMAND

REGISTER

X-Decoder

Status

Control

X-Decoder

Lower Bank

A max

–A0

Lower Bank Address

DQ max

–DQ0

Document Number: 002-00948 Rev. *A Page 7 of 86

5.

Physical Dimensions/Connection Diagrams

5.1

80-Pin PQFP Connection Diagram

DQ25

DQ26

DQ27

V

IO

V

SS

DQ28

DQ29

DQ30

DQ31

DQ16

DQ17

DQ18

DQ19

V

IO

V

SS

DQ20

DQ21

DQ22

DQ23

DQ24

NC

A0

A1

A2

13

14

15

16

9

10

11

12

17

18

19

20

7

8

5

6

3

4

1

2

21

22

23

24

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

64

63

62

61

60

59

58

80-Pin PQFP

53

52

51

50

57

56

55

54

49

48

47

46

45

44

43

42

41

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

DQ6

DQ5

DQ4

V

SS

V

IO

DQ3

DQ2

DQ1

DQ0

DQ15

DQ14

DQ13

DQ12

V

SS

V

IO

DQ11

DQ10

DQ9

DQ8

DQ7

A19

A18

A17

A16

Notes

1. On 16 Mb device, pin 44 (A19) is NC.

2. Pin 69 (RY/BY#) is Open Drain and requires an external pull-up resistor.

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document Number: 002-00948 Rev. *A Page 8 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

5.2

PQR080–80-Lead Plastic Quad Flat Package Physical Dimensions

PIN S

6

3

D

D1

D3

-A-

PIN ONE I.D.

PIN R

0˚MIN.

0.30 ± 0.05 R

-B-

E3

E1

3

E

6

GAGE

PLANE

0.25

L

0.20 MIN. FLAT SHOULDER

TYP.

A

0˚-7˚

TYP.

b a a a M

C A B

S D S

DETAIL X

4

SEE NOTE 3

PIN P

-D-

SEE DETAIL X e BASIC

PIN Q b c

SECTION S-S

A1

A2

S

S

A

-A-

2

-C-

SEATING PLANE ccc

C

R

S ccc

L

P

Q

E

E1

E3 aaa

D

D1

D3 e

PACKAGE

JEDEC

SYMBOL

A b c

A1

A2

17.00

13.90

--

--

23.00

19.90

--

---

0.25

2.70

0.30

0.15

MIN

--

PQR 080

MO-108(B)CB-1

NOM

--

MAX

3.35

--

2.80

--

--

--

2.90

0.45

0.23

17.20

14.00

12.0

0.80

23.20

20.00

18.40

0.20

17.40

14.10

--

--

23.40

20.10

--

---

0.73

0.10

0.88

24

40

64

80

1.03

NOTES

SEE NOTE 4

SEE NOTE 3

REFERENCE

BASIC, SEE NOTE 7

SEE NOTE 3

REFERENCE

NOTES:

1.

ALL DIMENSIONS AND TOLERANCES CONFORM TO

ANSI Y14.5M-1982.

2.

DATUM PLANE -A- IS LOCATED AT THE MOLD PARTING LINE

AND IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE

THE LEAD EXITS THE PLASTIC BODY.

3.

DIMENSIONS "D1" AND "E1" DO NOT INCLUD MOLD PROTRUSION.

ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE.

DIMENSIONS "D1" AND "E1" INCLUDE MOLD MISMATCH AND

ARE DETERMINED AT DATUM PLANE -A-

4.

DIMENSION "B" DOES NOT INCLUDE DAMBAR PROTRUSION.

5.

CONTROLLING DIMENSIONS: MILLIMETER.

6.

DIMENSIONS "D" AND "E" ARE MEASURED FROM BOTH

INNERMOST AND OUTERMOST POINTS.

7.

DEVIATION FROM LEAD-TIP TRUE POSITION SHALL BE WITHIN

±0.0076 mm FOR PITCH > 0.5 mm AND WITHIN ±0.04 FOR

PITCH < 0.5 mm.

8.

LEAD COPLANARITY SHALL BE WITHIN: (REFER TO 06-500)

1 - 0.10 mm FOR DEVICES WITH LEAD PITCH OF 0.65 - 0.80 mm

2 - 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm.

COPLANARITY IS MEASURED PER SPECIFICATION 06-500.

9.

HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE

WITHIN ±0.0085".

Document Number: 002-00948 Rev. *A

3213\38.4C

Page 9 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

5.3

80-Ball Fortified BGA Connection Diagrams

A6

A6

A5

V

SS

A4

ACC

A8

A2

A7

A3

A3

V

CC

A2

A14

A1

A15

B6

A5

B5

A8

B4

A9

B8

A1

B7

A4

B3

A12

B2

A13

B1

A16

C6

A7

C5

NC

C4

A10

C8

A0

C7

NC

C3

A11

C2

A18

C1

A17

D8

DQ29

D7

DQ30

D6

DQ31

D5

NC

D4

NC

D3

A19

D2

DQ0

D1

DQ3

E8

V

IO

E7

DQ26

E6

DQ28

E5

DQ27

E4

DQ1

E3

DQ2

E2

DQ4

E1

V

IO

F8

V

SS

F7

DQ24

F6

DQ25

F5

RY/BY#

G5

DQ22

F4

DQ5

G4

DQ9

F3

DQ6

F2

DQ7

F1

V

SS

G3

DQ10

G2

DQ8

G1

V

IO

G8

V

IO

G7

DQ23

G6

DQ21

H5

DQ17

H4

WP#

H3

DQ11

H2

DQ12

H1

DQ13

H8

DQ20

J8

DQ16

K8

NC

H7

DQ18

J7

IND/WAIT#

K7

NC

H6

DQ19

J6

OE#

K6

WE#

J5

CE#

J4

NC

J3

ADV#

J2

DQ14

K2

RESET#

J1

DQ15

K1

V

IO

K5

V

CC

K4

V

SS

K3

CLK

Notes

1. On 16 Mb device, ball D3 (A19) is NC.

2. Ball F5 (RY/BY#) is Open Drain and requires an external pull-up resistor.

5.4

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.

Document Number: 002-00948 Rev. *A Page 10 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

5.5

LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) Physical Dimensions

0.20

2X

C

D A

D1 eD

A1

CORNER

1.00±0.5

A

A2

A1

E eE

K J H G F E D C B A

8

7

6

5

4

3

2

1

SE

7

E1

φ

0.50

A1 CORNER ID.

(INK OR LASER)

TOP VIEW

SIDE VIEW

SEATING PLANE

C

B

0.20

2X

C

0.25

C

6

NX

φ b

φ

0.25 M

φ

0.10

M

C

C

A B

SD

7

BOTTOM VIEW

0.15 C

A1

CORNER

SYMBOL

A

A1

A2

D

E

D1

E1

MD

ME

N

φ b eD eE

SD/SE

PACKAGE

JEDEC

MIN

--

0.40

0.60

0.50

LAA 080

N/A

13.00 x 11.00 mm

PACKAGE

NOM

--

--

--

13.00 BSC.

11.00 BSC.

9.00 BSC.

7.00 BSC.

10

8

80

0.60

1.00 BSC.

1.00 BSC.

0.50 BSC

MAX

1.40

--

--

0.70

NOTE

PROFILE HEIGHT

STANDOFF

BODY THICKNESS

BODY SIZE

BODY SIZE

MATRIX FOOTPRINT

MATRIX FOOTPRINT

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

BALL DIAMETER

BALL PITCH - D DIRECTION

BALL PITCH - E DIRECTION

SOLDER BALL PLACEMENT

NOTES:

1.

DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

2.

ALL DIMENSIONS ARE IN MILLIMETERS.

3.

BALL POSITION DESIGNATION PER JESD 95-1, SPP-010

(EXCEPT AS NOTED).

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

5.

SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"

DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX

SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF

SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER

OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D

OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW , SD OR SE = e/2

8.

N/A

9.

"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

3214\38.12C

Document Number: 002-00948 Rev. *A Page 11 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

5.6

LAD080–80-ball Fortified Ball Grid Array (11 x 9 mm) Physical Dimensions

JEDEC N/A

D X E 11.00 mm x 9.00 mm

PACKAGE

SYMBOL MIN NOM MAX

A --- --- 1.40 PROFILE

NOTE

A1 0.35 0.45 0.55 BALL

D

E

D1

E1

MD

ME

10

8

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

b eE eD

SD / SE

0.55 0.65

0.50 BSC

0.75 BALL DIAMETER

SOLDER BALL PLACEMENT

NOTES:

1. DIMENSIONING AND TOLERANCING METHODS PER

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JEP95, SECTION

SPP-010.

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE

DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE

DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS

FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

g1064 \ f16-038.12 \ 01.31.12

Document Number: 002-00948 Rev. *A Page 12 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

6.

Additional Resources

Visit www.spansion.com

to obtain the following related documents:

6.1

Application Notes

The following is a list of application notes related to this product. All Spansion application notes are available at http:// www.spansion.com/Support/TechnicalDocuments/Pages/ApplicationNotes.aspx

 Using the Operation Status Bits in AMD Devices

 Understanding Page Mode Flash Memory Devices

 Common Flash Interface Version 1.4 Vendor Specific Extensions

6.2

Specification Bulletins

Contact your local sales office for details.

6.3

Hardware and Software Support

Downloads and related information on Flash device support is available at http://www.spansion.com/SUPPORT/Pages/Support.aspx

 Spansion low-level drivers

 Enhanced Flash drivers

 Flash file system

Downloads and related information on simulation modeling and CAD modeling support is available at http://www.spansion.com/Support/Pages/SimulationModels.aspx

VHDL and Verilog

 IBIS

 ORCAD

6.4

Contacting Spansion

Obtain the latest list of company locations and contact information on our web site at http://www.spansion.com/About/Pages/Locations.aspx

Document Number: 002-00948 Rev. *A Page 13 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

7.

Product Overview

The S29CD-J and S29CL-J families consist of 32 Mb and 16 Mb, 2.6 volt-only (CD-J) or 3.3 volt-only (CL-J), simultaneous read/ write, dual boot burst mode Flash devices optimized for today's automotive designs.

These devices are organized in 1,048,576 double words (32 Mb) or 524,288 double words (16 Mb) and are capable of linear burst read (2, 4, or 8 double words) with wraparound. (Note that 1 double word = 32 bits.) These products also offer single word programming with program/erase suspend and resume functionality. Additional features include:

 Advanced Sector Protection methods for protecting sectors as required.

 256 bytes of Secured Silicon area for storing customer or factory secured information. The Secured Silicon Sector is One-Time

Programmable.

 Electronic marking.

7.1

Memory Map

The S29CD-J and S29CL-J devices consist of two banks organized as shown in Table ,

Table ,

Table and

Table

.

Document Number: 002-00948 Rev. *A Page 14 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

S29CD016J/CL016J (Top Boot) Sector and Memory Address Map

Sector

SA0

(Note 1)

Sector

Group

SG0

SA1 SG1

SA2 SG2

SA3

SA4

SG3

SG4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SG5

SG6

SG7

SG8

SG9

x32 Address

Range (A18:A0)

00000h–007FFh

00800h–00FFFh

01000h–017FFh

01800h–01FFFh

02000h–027FFh

02800h–02FFFh

03000h–037FFh

03800h–03FFFh

04000h–07FFFh

08000h–0BFFFh

0C000h–0FFFFh

10000h–13FFFh

14000h–17FFFh

18000h–1BFFFh

1C000h–1FFFFh

Sector Size

(KDwords)

2

2

2

2

2

2

2

2

16

16

16

16

16

16

16

Sector

SA15

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

(Note 3)

SA45

(Note 3)

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

Notes

1. Secured Silicon Sector overlays this sector when enabled.

2. The bank address is determined by A18 and A17. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1.

3. This sector has the additional WP# pin sector protection feature.

Sector

Group

SG10

SG11

SG12

SG13

SG14

SG15

SG16

SG17

SG18

SG19

SG20

SG21

SG22

SG23

x32 Address Range

(A18:A0)

Sector Size

(KDwords)

20000h–23FFFh

24000h–27FFFh

28000h–2BFFFh

2C000h–2FFFFh

30000h–33FFFh

34000h–37FFFh

38000h–3BFFFh

3C000h–3FFFFh

40000h–43FFFh

44000h–47FFFh

48000h–4BFFFh

4C000h–4FFFFh

50000h–53FFFh

54000h–57FFFh

58000h–5BFFFh

5C000h–5FFFFh

60000h–63FFFh

64000h–67FFFh

68000h–6BFFFh

6C000h–6FFFFh

70000h–73FFFh

74000h–77FFFh

78000h–7BFFFh

7C000h–7C7FFh

7C800h–7CFFFh

7D000h–7D7FFh

7D800h–7DFFFh

7E000h–7E7FFh

7E800h–7EFFFh

7F000h–7F7FFh

16

16

16

2

2

16

16

16

16

2

2

2

2

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

2

7F800h–7FFFFh 2

Document Number: 002-00948 Rev. *A Page 15 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

S29CD016J/CL016J (Bottom Boot) Sector and Memory Address Map

Sector

SA0

SA1

(Note 1)

(Note 1)

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

Sector

Group

SG0

SG1

SG2

SG3

SG4

SG5

SG6

SG7

SG8

SG9

x32 Address

Range (A18:A0)

00000h–007FFh

00800h–00FFFh

01000h–017FFh

01800h–01FFFh

02000h–027FFh

02800h–02FFFh

03000h–037FFh

03800h–03FFFh

04000h–07FFFh

08000h–0BFFFh

0C000h–0FFFFh

10000h–13FFFh

14000h–17FFFh

18000h–1BFFFh

1C000h–1FFFFh

Sector Size

(KDwords)

2

2

2

2

2

2

2

2

16

16

16

16

16

16

16

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SG10

SG11

SG12

SG13

20000h–23FFFh

24000h–27FFFh

28000h–2BFFFh

2C000h–2FFFFh

30000h–33FFFh

34000h–37FFFh

38000h–3BFFFh

3C000h–3FFFFh

40000h–43FFFh

44000h–47FFFh

48000h–4BFFFh

4C000h–4FFFFh

50000h–53FFFh

54000h–57FFFh

58000h–5BFFFh

5C000h–5FFFFh

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

Notes

1. This sector has the additional WP# pin sector protection feature.

2. The bank address is determined by A18 and A17. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1.

3. Secured Silicon Sector overlays this sector when enabled.

Sector

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

(Note 3)

Sector

Group

SG14

SG15

SG23

SG16

SG17

SG18

SG19

SG20

SG21

SG22

x32

Address Range

(A18:A0)

60000h–63FFFh

64000h–67FFFh

68000h–6BFFFh

6C000h–6FFFFh

70000h–73FFFh

74000h–77FFFh

78000h–7BFFFh

7C000h–7C7FFh

7C800h–7CFFFh

7D000h–7D7FFh

7D800h–7DFFFh

7E000h–7E7FFh

7E800h–7EFFFh

7F000h–7F7FFh

2

2

2

2

16

2

2

2

Sector Size

(KDwords)

16

16

16

16

16

16

7F800h–7FFFFh 2

Document Number: 002-00948 Rev. *A Page 16 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

S29CD032J/CL032J (Top Boot) Sector and Memory Address Map

Sector

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA0

(Note 1)

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

Sector

Group x32 Address Range

(A19:A0)

Bank 0 (Note 2)

SG0

SG1

SG2

SG3

00000h–007FFh

00800h–00FFFh

01000h–017FFh

01800h–01FFFh

SG4

SG5

SG6

SG7

SG8

02000h–027FFh

02800h–02FFFh

03000h–037FFh

03800h–03FFFh

04000h–07FFFh

08000h–0BFFFh

0C000h–0FFFFh

10000h–13FFFh

SG9

SG10

SG11

SG12

14000h–17FFFh

18000h–1BFFFh

1C000h–1FFFFh

20000h–23FFFh

24000h–27FFFh

28000h–2BFFFh

2C000h–2FFFFh

30000h–33FFFh

34000h–37FFFh

38000h–3BFFFh

3C000h–3FFFFh

Bank 1 (Note 2)

40000h–43FFFh

44000h–47FFFh

48000h–4BFFFh

4C000h–4FFFFh

SG13

SG14

SG15

50000h–53FFFh

54000h–57FFFh

58000h–5BFFFh

5C000h–5FFFFh

60000h–63FFFh

64000h–67FFFh

68000h–6BFFFh

6C000h–6FFFFh

70000h–73FFFh

74000h–77FFFh

78000h–7BFFFh

7C000h–7FFFFh

Sector Size

(KDwords)

2

2

2

2

2

2

2

2

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

Sector

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA71

SA72

SA73

SA74

SA75

SA76 (Note 3)

SA77 (Note 3)

Notes

1. Secured Silicon Sector overlays this sector when enabled.

2. The bank address is determined by A19 and A18. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1.

3. This sector has the additional WP# pin sector protection feature.

SG24

SG25

SG26

SG27

SG28

SG29

SG30

SG31

Sector

Group x32 Address Range

(A19:A0)

Bank 1 continued

(Note 2)

SG16

80000h–83FFFh

84000h–87FFFh

88000h–8BFFFh

8C000h–8FFFFh

SG17

SG18

90000h–93FFFh

94000h–97FFFh

98000h–9BFFFh

9C000h–9FFFFh

A0000h–A3FFFh

A4000h–A7FFFh

A8000h–ABFFFh

AC000h–AFFFFh

SG19

SG20

SG21

SG22

B0000h–B3FFFh

B4000h–B7FFFh

B8000h–BBFFFh

BC000h–BFFFFh

C0000h–C3FFFh

C4000h–C7FFFh

C8000h–CBFFFh

CC000h–CFFFFh

D0000h–D3FFFh

D4000h–D7FFFh

D8000h–DBFFFh

DC000h–DFFFFh

E0000h–E3FFFh

E4000h–E7FFFh

E8000h–EBFFFh

EC000h–EFFFFh

SG23

F0000h–F3FFFh

F4000h–F7FFFh

F8000h–FBFFFh

FC000h–FC7FFh

FC800h–FCFFFh

FD000h–FD7FFh

FD800h–FDFFFh

FE000h–FE7FFh

FE800h–FEFFFh

FF000h–FF7FFh

FF800h–FFFFFh

Sector Size

(KDwords)

16

16

16

2

16

16

16

16

16

16

16

16

16

16

16

16

2

2

2

2

2

2

2

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

Document Number: 002-00948 Rev. *A Page 17 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

SA20

SA21

SA22

SA23

SA24

SA25

SA14

SA15

SA16

SA17

SA18

SA19

SA0 (Note 3)

SA1 (Note 3)

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA26

SA27

SA28

SA29

SA30

SA31

S29CD032J/CL032J (Bottom Boot) Sector and Memory Address Map

Sector

Sector

Group x32 Address Range

(A19:A0)

Bank 0

(Note 2)

SG0

SG1

SG2

00000h–007FFh

00800h–00FFFh

01000h–017FFh

SG3

SG4

SG5

SG6

SG7

01800h–01FFFh

02000h–027FFh

02800h–02FFFh

03000h–037FFh

03800h–03FFFh

04000h–07FFFh

SG8

SG9

SG10

08000h–0BFFFh

0C000h–0FFFFh

10000h–13FFFh

14000h–17FFFh

18000h–1BFFFh

1C000h–1FFFFh

20000h–23FFFh

24000h–27FFFh

28000h–2BFFFh

2C000h–2FFFFh

30000h–33FFFh

SG11

SG12

SG13

SG14

SG15

34000h–37FFFh

38000h–3BFFFh

3C000h–3FFFFh

40000h–43FFFh

44000h–47FFFh

48000h–4BFFFh

4C000h–4FFFFh

50000h–53FFFh

54000h–57FFFh

58000h–5BFFFh

5C000h–5FFFFh

60000h–63FFFh

64000h–67FFFh

68000h–6BFFFh

6C000h–6FFFFh

70000h–73FFFh

74000h–77FFFh

78000h–7BFFFh

7C000h–7FFFFh

Sector Size

(KDwords)

16

16

16

16

16

16

16

16

16

16

16

16

16

16

16

2

2

16

16

16

2

2

2

2

2

2

16

16

16

16

16

16

16

16

16

16

16

16

16

Sector

SA45

SA46

SA47

SA48

SA49

SA50

SA39

SA40

SA41

SA42

SA43

SA44

SA51

SA52

SA53

SA54

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

(Note 1)

SA61

SA62

SA63

SA64

SA65

SA66

SA55

SA56

SA57

SA58

SA59

SA60

SG24

SG25

SG26

SG27

SG28

SG29

SG30

SG31

Sector

Group x32 Address Range

(A19:A0)

Bank 0 continued (Note 2)

Sector Size

(KDwords)

SG16

80000h–83FFFh

84000h–87FFFh

88000h–8BFFFh

8C000h–8FFFFh

90000h–93FFFh

94000h–97FFFh

SG17

16

16

16

16

16

16

SG18

98000h–9BFFFh

9C000h–9FFFFh

A0000h–A3FFFh

A4000h–A7FFFh

A8000h–ABFFFh

AC000h–AFFFFh

16

16

16

16

16

16

16

16

16

16

B0000h–B3FFFh

B4000h–B7FFFh

SG19

B8000h–BBFFFh

BC000h–BFFFFh

Bank 1

(Note 2)

SG20

C0000h–C3FFFh

C4000h–C7FFFh

C8000h–CBFFFh

SG21

CC000h–CFFFFh

D0000h–D3FFFh

D4000h–D7FFFh

D8000h–DBFFFh

DC000h–DFFFFh

E0000h–E3FFFh

SG22

16

16

16

16

16

16

16

16

16

16

16

16

SG23

E4000h–E7FFFh

E8000h–EBFFFh

EC000h–EFFFFh

F0000h–F3FFFh

F4000h–F7FFFh

F8000h–FBFFFh

FC000h–FC7FFh

FC800h–FCFFFh

FD000h–FD7FFh

FD800h–FDFFFh

FE000h–FE7FFh

FE800h–FEFFFh

FF000h–FF7FFh

FF800h–FFFFFh

2

2

2

2

2

2

2

2

16

16

16

Document Number: 002-00948 Rev. *A Page 18 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Notes

1. This sector has the additional WP# pin sector protection feature.

2. The bank address is determined by A19 and A18. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1.

3. The Secured Silicon Sector overlays this sector when enabled.

8.

Device Operations

This section describes the read, program, erase, simultaneous read/write operations, and reset features of the Flash devices.

Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command register (see

Table

). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine; the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command in order to return the device to the reading array data mode.

8.1

Device Operation Table

The device must be set up appropriately for each operation. Table describes the required state of each control pin for any particular

operation.

Device Bus Operation

Operation CE# OE# WE# RESET#

Read L

Asynchronous Write L

L

H

H

L

H

H

Synchronous Write L H L H

Standby (CE#)

Output Disable

Reset

H

L

X

X

H

X

X

H

X

H

H

L

PPB Protection Status (Note 2) L L H H

CLK

X

X

H

X

X

X

ADV#

X

X

X

X

X

X

Addresses

A

IN

A

IN

A

IN

X

High-Z

X

Sector Address,

A9 = V

ID

,

A7 – A0 = 02h

Data

(DQ0–DQ31)

D

OUT

D

IN

D

IN

High-Z

High-Z

High-Z

00000001h, (protected)

A6 = H

00000000h (unprotect)

A6 = L

Burst Read Operations

Load Starting Burst Address

Advance Burst to next address with appropriate Data presented on the Data bus

L

L

X

L

H

H

H

H H

A

IN

X

X

Burst Data Out

High-Z Terminate Current Burst Read Cycle H X H H X X

Terminate Current Burst

Read Cycle with RESET#

Terminate Current Burst Read Cycle;

Start New Burst Read Cycle

X

L

X

H

H

H

L

H

X X

A

X

IN

Legend

L = Logic Low = V

IL

, H = Logic High = V

IH

, X = Don’t care.

Notes

1. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block.

2. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB.

High-Z

X

Document Number: 002-00948 Rev. *A Page 19 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

8.2

Asynchronous Read

All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs.

The internal state machine is set for asynchronously reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.

The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and should be used for device selection (CE# must be set to V

IL

to read data). OE# is the output control and should be used to gate data to the output pins if the device is selected (OE# must be set to V

IL

in order to read data). WE# should remain at V

IH

(when reading data).

Address access time (t

ACC

) is equal to the delay from stable addresses to valid output data. The chip enable access time (t

CE

) is the delay from the stable addresses and stable CE# to valid data at the output pins. The output enable access time (t

OE

) is the delay t from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least a period of t

ACC

-

OE

and CE# has been asserted for at least t

CE

-t

OE

time). Figure 8.1

shows the timing diagram of an asynchronous read operation.

Figure 8.1 Asynchronous Read Operation

CE#

CLK

ADV#

Addresses

Address 0 Address 1

Data D0

Address 2

D1

Address 3

D2 D3 D3

OE#

WE#

V

IH

IND/WAIT#

Float

V

OH

Note

Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.

Float

Refer to

Asynchronous Operations on page 52

for timing specifications and to

Figure 18.2, Conventional Read Operations Timings on page 52

for another timing diagram. I

CC1

in the DC Characteristics table represents the active current specification for reading array data.

8.3

Hardware Reset (RESET#)

The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic “0” on this input forces the device out of any mode that is currently executing back to the reset state. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the device. To avoid a potential bus contention during a system reset, the device is isolated from the DQ data bus by tristating the data outputs for the duration of the RESET pulse. All data outputs are “don’t care” during the reset operation.

If RESET# is asserted during a program or erase operation, the RY/BY# output remains low until the reset operation is internally complete. The RY/BY# pin can be used to determine when the reset operation is complete. Since the device offers simultaneous read/write operation, the host system may read a bank after a period of t

READY2

, if the bank was in the read/reset mode at the time

Document Number: 002-00948 Rev. *A Page 20 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

RESET# was asserted. If one of the banks was in the middle of either a program or erase operation when RESET# was asserted, the user must wait a period of t

READY before accessing that bank.

Asserting RESET# during a program or erase operation leaves erroneous data stored in the address locations being operated on at the time of device reset. These locations need updating after the reset operation is complete. See

Hardware Reset (RESET#) on page 56 for timing specifications.

Asserting RESET# active during V

CC

and V

IO

power-up is required to guarantee proper device initialization until V

CC

and V

IO

have

reached their steady state voltages. See

V

CC

and V

IO

Power-up on page 51 .

8.4

Synchronous (Burst) Read Mode and Configuration Register

When a series of adjacent addresses need to be read from the device, the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. After an initial access time required for the data from the first address location, subsequent data is output synchronized to a clock input provided by the system.

The device offers a linear method of burst read operation which is discussed in

2-, 4-, 8- Double Word Linear Burst Operation on page 22 .

Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set in order to enable the burst read mode. Other Configuration Register settings include the number of wait states to insert before the initial word (t

IACC

) of each burst access and when RDY indicates that data is ready to be read. Prior to entering the burst mode, the system first determines the configuration register settings (and read the current register settings if desired via the Read

Configuration Register command sequence), then write the configuration register command sequence. See Configuration Register on page 24

, and Table on page 71 for further details. Once the configuration register is written to enable burst mode operation, all

subsequent reads from the array are returned using the burst mode protocols.

Figure 8.2 Synchronous/Asynchronous State Diagram

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(D15 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(D15 = 1)

Synchronous Read

Mode Only

The device outputs the initial word subject to the following operational conditions:

 t

IACC

specification: The time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs.

 Configuration register setting CR13-CR10: The total number of clock cycles (wait states) that occur before valid data appears on the device outputs. The effect is that t

IACC

is lengthened.

Document Number: 002-00948 Rev. *A Page 21 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Like the main memory access, the Secured Silicon Sector memory is accessed with the same burst or asynchronous timing as defined in the Configuration Register. However, the user must recognize burst operations past the 256 byte Secured Silicon boundary returns invalid data.

Burst read operations occur only to the main flash memory arrays. The Configuration Register and protection bits are treated as single cycle reads, even when burst mode is enabled. Read operations to these locations results in the data remaining valid while

OE# is at V

IL

, regardless of the number of CLK cycles applied to the device.

8.4.1

2-, 4-, 8- Double Word Linear Burst Operation

In a linear burst read operation, a fixed number of words (2, 4, or 8 double words) are read from consecutive addresses that are

determined by the group within which the starting address falls. Note that 1 double word = 32 bits. See Table for all valid burst

output sequences.

The IND/WAIT# signal, or End of Burst Indicator signal, transitions active (V

IL

) during the last transfer of data in a linear burst read before a wrap around. This transition indicates that the system should initiate another ADV# to start the next burst access. If the system continues to clock the device, the next access wraps around to the starting address of the previous burst access. The IND/

WAIT# signal is floating when not active.

32-Bit Linear and Burst Data Order

Data Transfer Sequence

Two Linear Data Transfers

Four Linear Data Transfers

Eight Linear Data Transfers

Output Data Sequence

(Initial Access Address)

0-1 (A0 = 0)

1-0 (A0 = 1)

0-1-2-3 (A1-A0 = 00)

1-2-3-0 (A1-A0 = 01)

2-3-0-1 (A1-A0 = 10)

3-0-1-2 (A1-A0 = 11)

0-1-2-3-4-5-6-7 (A2-A0 = 000)

1-2-3-4-5-6-7-0 (A2-A0 = 001)

2-3-4-5-6-7-0-1 (A2-A0 = 010)

3-4-5-6-7-0-1-2 (A2-A0 = 011)

4-5-6-7-0-1-2-3 (A2-A0 = 100)

5-6-7-0-1-2-3-4 (A2-A0 = 101)

6-7-0-1-2-3-4-5 (A2-A0 = 110)

7-0-1-2-3-4-5-6 (A2-A0 = 111)

Notes

1. The default configuration in the Control Register for Bit 6 is “1,” indicating that the device delivers data on the rising edge of the CLK signal.

2. The device is capable of holding data for one CLK cycle.

3. If RESET# is asserted low during a burst access, the burst access is immediately terminated and the device defaults back to asynchronous read mode. When this happens, the DQ data bus signal floats and the Configuration Register contents are reset to their default conditions.

4. CE# must meet the required burst read setup times for burst cycle initiation. If CE# is taken to V

IH

at any time during the burst linear or burst cycle, the device immediately exits the burst sequence and floats the DQ bus signal.

5. Restarting a burst cycle is accomplished by taking CE# and ADV# to V

IL

.

6. A burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge, whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear burst sequence, the previous address is discarded and subsequent burst transfers are invalid. A new burst is initiated when ADV# transitions back to V

IH

before a clock edge.

7. The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De-asserting the OE# pin to V

IH

during a burst operation floats the data bus, but the device continues to operate internally as if the burst sequence continues until the linear burst is complete. The OE# pin does not halt the burst sequence,

The DQ bus remains in the float state until OE# is taken to V

IL

.

8. Halting the burst sequence is accomplished by either taking CE# to V

IH

or re-issuing a new ADV# pulse.

The IND/WAIT# signal is controlled by the OE# signal. If OE# is at V

IH

, the IND/WAIT# signal floats and is not driven. If OE# is at

V

IL

, the IND/ WAIT# signal is driven at V

IH

until it transitions to V

IL

, indicating the end of the burst sequence. Table lists the valid combinations of the Configuration Register bits that impact the IND/WAIT# timing. See Figure 8.3

for the IND/WAIT# timing diagram.

Document Number: 002-00948 Rev. *A Page 22 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Valid Configuration Register Bit Definition for IND/WAIT#

CR9

(DOC)

0

0

CR8

(WC)

0

1

CR6

(CC)

1

1

Definition

IND/WAIT# = V

IL

for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge

IND/WAIT# = V

IL

for 1-CLK cycle, Active on second to last transfer, Driven on rising

CLK edge

Figure 8.3 End of Burst Indicator (IND/WAIT#) Timing for Linear 4 Double Word Burst Operation

V

IH

CE#

V

IL

CLK

ADV#

Addresses

Data

Address 1

3 Clock Delay

Address 1 Latched

Address 2

Invalid D1 D2 D3

OE#

D0

IND/WAIT#

Note

Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst, output on rising CLK edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around.

8.4.2

Initial Burst Access Delay

Initial Burst Access Delay is defined as the number of clock cycles that must elapse from the first valid clock edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid. Burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge, whichever comes first. The Initial Burst

Access Delay is determined in the Configuration Register (CR13-CR10). Refer to Table for the initial access delay configurations

under CR13-CR10. See Figure 8.4

for the Initial Burst Delay Control timing diagram.

Note that the Initial Access Delay for a burst access has no effect on asynchronous read operations.

Burst Initial Access Delay

0

0

0

0

CR13

0

0

0

1

1

1

1

CR12

0

0

0

1

1

0

0

CR11

0

1

1

0

1

0

1

CR10

1

0

1

Initial Burst Access (CLK cycles)

3

4

5

8

9

6

7

Document Number: 002-00948 Rev. *A Page 23 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

1st CLK

Figure 8.4 Initial Burst Delay Control

2nd CLK 3rd CLK 4th CLK 5th CLK

CLK

ADV#

Address 1 Latched

Addresses

Valid Address

DQ31-DQ0

3

DQ31-DQ0

4

Three CLK Delay

Four CLK Delay

D0 D1

D0

Five CLK Delay

DQ31-DQ0

5

Notes

1. Burst access starts with a rising CLK edge and when ADV# is active.

2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.

3. CR [13-10] = 1 or three clock cycles.

4. CR [13-10] = 2 or four clock cycles.

5. CR [13-10] = 3 or five clock cycles.

D2

D1

D0

D3

D2

D1

D4

D3

D2

8.4.3

Configuration Register

The configuration register sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the

device defaults to the asynchronous read mode and the configuration register settings are in their default state. (See Table for the

default Configuration Register settings.) The host system determines the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence before attempting burst operations. The configuration register is not reset after deasserting CE#.

The Configuration Register does not occupy any addressable memory location, but rather, is accessed by the Configuration

Register commands. The Configuration Register is readable at any time, however, writing the Configuration Register is restricted to times when the Embedded Algorithm™ is not active. If the user attempts to write the Configuration Register while the Embedded

Algorithm is active, the write operation is ignored and the contents of the Configuration Register remain unchanged.

The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read operation, DQ31–DQ16 returns all zeroes. Also, the Configuration Register reads operate the same as the Autoselect command reads. When the command is issued, the bank address is latched along with the command. Read operations to the bank that was specified during the Configuration

Register read command return Configuration Register contents. Read operations to the other bank return flash memory data. Either bank address is permitted when writing the Configuration Register read command.

The configuration register can be read with a four-cycle command sequence. See Command Definitions on page 71

for sequence details.

Table describes the Configuration Register settings.

Document Number: 002-00948 Rev. *A Page 24 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Configuration Register

Configuration Register

CR15 = Read Mode (RM)

0 = Synchronous Burst Reads Enabled

1 = Asynchronous Reads Enabled (Default)

CR14 = Reserved for Future Enhancements

These bits are reserved for future use. Set these bits to 0.

CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0)

0000 = 2 CLK cycle initial burst access delay

0001 = 3 CLK cycle initial burst access delay

0010 = 4 CLK cycle initial burst access delay

0011 = 5 CLK cycle initial burst access delay

CR9 = Data Output Configuration (DOC)

0 = Hold Data for 1-CLK cycle—Default

1 = Reserved

0100 = 6 CLK cycle initial burst access delay

0101 = 7 CLK cycle initial burst access delay

0110 = 8 CLK cycle initial burst access delay

0111 = 9 CLK cycle initial burst access delay—Default

CR8 = IND/WAIT# Configuration (WC)

0 = IND/WAIT# Asserted During Delay—Default

1 = IND/WAIT# Asserted One Data Cycle Before Delay

CR7 = Burst Sequence (BS)

0 = Reserved

1 = Linear Burst Order—Default

CR6 = Clock Configuration (CC)

0 = Reserved

1 = Burst Starts and Data Output on Rising Clock Edge—Default

CR5–CR3 = Reserved For Future Enhancements (R)

These bits are reserved for future use. Set these bits to 0.

CR2–CR0 = Burst Length (BL2–BL0)

000 = Reserved, burst accesses disabled (asynchronous reads only)

001 = 64 bit (8-byte) Burst Data Transfer - x32 Linear

010 = 128 bit (16-byte) Burst Data Transfer - x32 Linear

011 = 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default)

100 = Reserved, burst accesses disabled (asynchronous reads only)

101 = Reserved, burst accesses disabled (asynchronous reads only)

110 = Reserved, burst accesses disabled (asynchronous reads only)

Configuration Register After Device Reset

CR15

RM

1

CR14

Reserve

0

CR13

IAD3

0

CR12

IAD2

1

CR11

IAD1

1

CR10

IAD0

1

CR9

DOC

0

CR8

Reserve

0

CR7

BS

1

CR6

CC

1

CR5

Reserve

0

CR4

Reserve

0

CR3

Reserve

0

CR2

BL2

1

CR1

BL1

0

CR0

BL0

0

8.5

Autoselect

The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be

Document Number: 002-00948 Rev. *A Page 25 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V

ID

on address pin A9. Ad-dress pins A6, A1, and A0 must be as shown in

Table

. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order

address bits. Table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the

programming equipment may then read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the command. This method does not require VID. See

Command Definitions on page 71

for details on using the autoselect mode. Autoselect mode can be used in either synchronous (Burst) mode or asynchronous (Non Burst) mode.

The system must write the reset command to exit the autoselect mode and return to reading the array data. See

Table

for command sequence details.

S29CD-J and S29CL-J Flash Family Autoselect Codes (High Voltage Method)

Description

Manufacturer ID: Spansion

Read Cycle 1

Read Cycle 2

Read Cycle 3

PPB Protection Status

CE# OE# WE#

L

L

L

L

H

H

A19 to

A11 A10 A9 A8 A7 A6

A5 to

A4 A3 A2 A1 A0

X

X

X V

ID

X V

ID

X X L X X X L L

X L L X L L L H

L

L

L

L

L

L

H

H

H

X

X

SA

X

X

X

V

V

V

ID

ID

ID

X

X

X

L

L

L

L

L

L

L

L

L

H

H

L

H

H

L

H

H

H

L

H

L

DQ7 to DQ0

0001h

007Eh

08h or 36h for CD016J

46h for CL016J

09h for CD032J

49h for CL032J

0000h

Top Boot Option

0001h

Bottom Boot Option

0000h (unprotected)

0001h (protected)

Legend

L = Logic Low = V

IL

, H = Logic High = V

IH

, SA = Sector Address, X = Don’t care.

Note

The autoselect codes can also be accessed in-system via command sequences. See Table .

8.6

VersatileI/O (V

IO

) Control

The VersatileI/O (V

IO

) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the V

IO

pin. The output voltage generated on the device is determined based on the V

IO

level. For the 2.6 V (CD-J), a V

IO

of 1.65 V–3.6 V (CD032J has a V

IO

of 1.65 V to 2.75 V) allows the device to interface with I/Os lower than 2.5 V. For a 3.3 V V

CC

(CL-J), a V

IO

of 1.65 V–3.60 V allows the device to interface with I/Os lower than 3.0 V.

8.7

Program/Erase Operations

These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase operation, devices must be set up appropriately as outlined in the

configuration register ( Table on page 25 ). During a synchronous write operation, to write a command or command sequence

(including programming data to the device and erasing sectors of memory), the system must drive ADV# and CE# to V

IL

, and OE# to

V

IH

when providing an address to the device, and drive WE# and CE# to V

IL

, and OE# to V

IH

when writing commands or programming data.

Document Number: 002-00948 Rev. *A Page 26 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

8.7.1

Programming

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program setup command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses

and verifies the programmed cell margin. Command Definitions on page 71

shows the address and data requirements for the program command sequence.

Note the following:

 When the Embedded Program algorithm is complete, the device returns to the read mode and address are no longer latched. An address change is required to begin reading valid array data.

 The system can determine the status of the program operation by using DQ7, DQ6 or RY/BY#. Refer to

Write Operation Status on page 31 for information on these status bits.

 A “0” cannot be programmed back to a “1.” Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data#

Polling algorithm to indicate the operation was successful. A succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.”

 Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend command.

 A hardware reset immediately terminates the program operation; the program command sequence should be re-initiated once the device has returned to the read mode, to ensure data integrity.

 For the 32Mb S29CD-J and S29CL-J devices only:

Please refer to the application note “Recommended Mode of Operation for Spansion

®

110 nm S29CD032J/S29CL032J Flash

Memory” publication number S29CD-CL032J_Recommend_AN for programming best practices.

Figure 8.5 Program Operation

START

Write Program

Command Sequence

Note

See

Table and

Table

for program command sequence.

Data Poll from System

Embedded

Program algorithm

in progress

Increment Address

Verify Data?

Yes

No

Last Address?

Yes

Programming

Completed

No

Document Number: 002-00948 Rev. *A Page 27 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

8.7.2

Sector Erase

The sector erase function erases one or more sectors in the memory array. (See Table , Memory Array Command Definitions (x32

Mode) on page 71

and Figure 8.6, Erase Operation on page 29 .) The device does not require the system to preprogram prior to

erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all-zero data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of no less than 80 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 µs. Any sector erase address and command following the exceeded time-out (80 µs) may or may not be accepted. A time-out of 80 µs from the rising edge of the last WE# (or CE#) initiates the execution of the Sector Erase command(s). If another falling edge of the WE#

(or CE#) occurs within the 80 µs time-out window, the timer is reset. Any command other than Erase Suspend during the time-out period will be interpreted as an additional sector to erase. The device does not decode the data bus, but latches the address. (See

S29CD016J Sector Erase Time-Out Functionality Application Note for further information.). The system can monitor DQ3 to

determine if the sector erase timer has timed out (See DQ3: Sector Erase Timer on page 36 .) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading array data; addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to

Write Operation

Status on page 31

for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be re-initiated once that bank has returned to reading array data, in order to ensure data integrity.

Figure 8.6 on page 29 illustrates the algorithm for the erase operation. Refer to

Program/Erase Operations on page 26

for parameters and timing diagrams.

8.7.3

Chip Erase

Chip erase is a six-bus cycle operation as indicated by Command Definitions on page 71

. The Chip Erase command is used to erase the entire flash memory contents of the chip by issuing a single command. However, chip erase does not erase protected sectors.

This command invokes the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The

Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all-zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not required to provide any controls or

timings during these operations. Command Definitions on page 71

in the appendix shows the address and data requirements for the chip erase command sequence.

When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6 or the RY/BY#. Refer to

Write Operation Status on page 31 for information on these status bits.

Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.

Document Number: 002-00948 Rev. *A Page 28 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Figure 8.6 Erase Operation

START

Write Erase

Command Sequence

Data Poll from System

Embedded

Erase algorithm in progress

No

Data = FFh?

Yes

Erasure Completed

Notes

1. See

Command Definitions on page 71

for erase command sequence.

2. See

DQ3: Sector Erase Timer on page 36 for more information.

8.7.4

Erase Suspend / Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum 80-µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation.

When the Erase Suspend command is written after the 80-µs time-out period has expired and during the sector erase operation, the device takes 20 µs maximum to suspend the erase operation.

After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector that is not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Note that when the device is in the Erase Suspend mode, the Reset command is not required for read operations and is ignored.

Further nesting of erase operation is not permitted. Reading at any address within erase suspended sectors produces status information on DQ7-DQ0. The system can use DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-

suspended. Refer to Table on page 35 for information on these status bits.

A read operation from the erase-suspended bank returns polling data during the first 8 µs after the erase suspend command is issued; read operations thereafter return array data. Read operations from the other bank return array data with no latency.

After an erase-suspended program operation is complete, the bank returns to the erase-suspend read mode. The system can determine the status of the program operation using the DQ7, DQ6, and/or RY/BY# status bits, just as in the standard program operation.

To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erasesuspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase

Suspend command can be written after the chip has resumed erasing.

The following are the allowable operations when Erase Suspend is issued under certain conditions:

Document Number: 002-00948 Rev. *A Page 29 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

For the Busy Sectors, the host system may

 Read status

 Write the Erase Resume command

For the Non Busy Sectors, the system may

 Read data

 Program data or write the Suspend/Resume Erase command

8.7.5

Program Suspend/Program Resume Commands

The Program Suspend command allows the system to interrupt an embedded programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation and updates the status bits.

After the programming operation has been suspended, the system can read array data from any non-suspended sector. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region. The

Sector Erase and Program Resume Command is ignored if the Secured Silicon sector is enabled.

After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7, DQ6, and/or RY/BY# status bits, just as in the standard program operation. See

Write Operation

Status on page 31

for more information.

The system must write the Program Resume command in order to exit the Program Suspend mode, and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming.

The following are the allowable operations when Program Suspend is issued under certain conditions:

 For the Busy Sectors, the host system may write the Program Resume command

 For the Non Busy Sectors, the system may read data

8.7.6

Accelerated Program Operations

Accelerated programming is enabled through the ACC function. This method is faster than the standard program command sequences.

The device offers accelerated program operations through the ACC pin. When the system asserts V

HH

(12V) on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence to do accelerated programming. The device uses the higher voltage on the ACC pin to accelerate the operation. Any sector that is being protected with the WP# pin is still protected during accelerated program. Removing V

HH

from the ACC input, upon completion of the embedded program operation, returns the device to normal operation.

Notes

 In this mode, the write protection function is bypassed unless the PPB Lock Bit = 1.

 The ACC pin must not be at V

HH

for operations other than accelerated programming or device damage may result.

 The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

 The Accelerated Program command is not permitted if the Secured Silicon sector is enabled.

Document Number: 002-00948 Rev. *A Page 30 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

8.7.7

Unlock Bypass

The device features an Unlock Bypass mode to facilitate faster programming, erasing (Chip Erase), as well as CFI commands. Once the device enters the Unlock Bypass mode, only two write cycles are required to program or erase data, instead of the normal four cycles for program or 6 cycles for erase. This results in faster total programming/erasing time.

Command Definitions on page 71

shows the requirements for the unlock bypass command sequences.

During the unlock bypass mode only the Read, Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence, which returns the device to read mode.

Notes

1. The Unlock Bypass Command is ignored if the Secured Silicon sector is enabled.

2. Unlike the standard program or erase commands, there is no Unlock Bypass Program/Erase Suspend or Program/Erase

Resume command.

8.7.8

Simultaneous Read/Write

The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing in another bank of memory.

The Simultaneous Read/Write feature can be used to perform the following:

 Programming in one bank, while reading in the other bank

 Erasing in one bank, while reading in the other bank

 Programming a PPB, while reading data from the large bank or status from the small bank

 Erasing a PPB, while reading data from the large bank or status from the small bank

 Any of the above situations while in the Secured Silicon Sector Mode

The Simultaneous R/W feature can not be performed during the following modes:

 CFI Mode

 Password Program operation

 Password Verify operation

As an alternative to using the Simultaneous Read/Write feature, the user may also suspend an erase or program operation to read in another location within the same bank (except for the sector being erased).

Restrictions

The Simultaneous Read/Write function is tested by executing an embedded operation in the small (busy) bank while performing other operations in the big (non-busy) bank. However, the opposite case is neither tested nor valid. That is, it is not tested by executing an embedded operation in the big (busy) bank while performing other operations in the small (non-busy) bank.

8.8

Write Operation Status

The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ7, DQ6, DQ2, DQ5, DQ3, and RY/BY#.

Document Number: 002-00948 Rev. *A Page 31 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

8.8.1

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that Data# Polling returns invalid data for the address being programmed or erased.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7.

If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode without programming the sector. If an erase address falls within a protected sector, Toggle BIT (DQ6) is active for

150 s, then the device returns to the read mode without erasing the sector. Please note that Data# polling (DQ7) may give misleading status when an attempt is made to program or erase a protected sector.

During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete

Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7.

In asynchronous mode, just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on

DQ7-D00 appears on successive read cycles.

See the following for more information:

Table , Write Operation Status on page 37

shows the outputs for Data# Polling on DQ7.

Figure 8.7, Data# Polling Algorithm on page 33

shows the Data# Polling timing diagram.

Document Number: 002-00948 Rev. *A Page 32 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Figure 8.7 Data# Polling Algorithm

START

Read DQ7–DQ0

Addr = VA

No

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

Yes

DQ7 = Data?

No

FAIL

PASS

Notes

1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5

Document Number: 002-00948 Rev. *A Page 33 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

8.8.2

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, two immediate consecutive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. For asynchronous mode, either OE# or CE# can be used to control the read cycles. For synchronous mode, the rising edge of ADV# is used or the rising edge of clock while ADV# is Low.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete.

See

Figure 18.12, Toggle Bit Timings (During Embedded Algorithms) on page 61

for additional information.

8.8.3

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded

Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system performs two consecutive reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to

Table

to compare outputs for

DQ2 and DQ6. See

DQ6: Toggle Bit I on page 34

for additional information.

8.8.4

Reading Toggle Bits DQ6/DQ2

Whenever the system initially begins reading toggle bit status, it must perform two consecutive reads of DQ7-DQ0 in a row in order to determine whether a toggle bit is toggling. Typically, the system notes and stores the value of the toggle bit after the first read.

After the second read, the system compares the new value of the toggle bit with the first. If the toggle bit is not toggling, the device completes the program or erases operation. The system can read array data on DQ7-DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also notes whether the value of DQ5 is high (see the section on DQ5). If it is, the system then determines again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device had not completed the operation successfully, and the system writes the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to

Figure 8.8

for more on the Toggle Bit Algorithm.

Document Number: 002-00948 Rev. *A Page 34 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

DQ6 and DQ2 Indications

If device is

programming, actively erasing, erase suspended, programming in erase suspend,

and the system reads

at any address, at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at an address within sectors selected for erasure, at an address within sectors not selected for erasure, at any address,

then DQ6

toggles, toggles, toggles,

and DQ2

does not toggle.

also toggles.

does not toggle does not toggle, returns array data, toggles, toggles.

returns array data. The system can read from any sector not selected for erasure.

is not applicable.

Figure 8.8 Toggle Bit Algorithm

START

(Note 1)

Read Byte

(DQ0-DQ7)

Address = VA

Read Byte

(DQ0-DQ7)

Address = VA

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Byte Twice

(DQ0-DQ7)

Adrdess = VA

DQ6 = Toggle?

Yes

FAIL

Notes

1. Read toggle bit with two immediately consecutive reads to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1.

Document Number: 002-00948 Rev. *A

(Notes

1 , 2

)

No

PASS

Page 35 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

8.8.5

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.

The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1.

Under both these conditions, the system issues the reset command to return the device to reading array data.

8.8.6

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See

Sector Erase on page 28 for more details.

After the sector erase command is written, the system reads the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, then reads DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands.

To ensure the command has been accepted, the system software check the status of DQ3 prior to and following each sub-sequent

sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table shows

the status of DQ3 relative to the other status bits.

8.8.7

RY/BY#: Ready/Busy#

The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or have been completed. If the output of RY/BY# is low, the device is busy with either a program, erase, or reset operation. If the output is floating, the device is ready to accept any read/write or erase operation. When the RY/BY# pin is low, the device will not accept any additional program or erase commands with the exception of the Erase suspend command. If the device has entered Erase Suspend mode, the RY/BY# output is floating. For programming, the RY/BY# is valid (RY/BY# = 0) after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/BY# is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the RY/BY# is also valid after the rising edge of the sixth WE# pulse.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t

READY

(during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is floating), the reset operation is completed in a time of t

READY

(not during Embedded Algorithms). The system can read data t

RH

after the RESET# pin returns to V

IH

.

Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V

CC

. An external pull-up resistor is required to take RY/BY# to a V

IH

level since the output is an open drain.

Table shows the outputs for RY/BY#, DQ7, DQ6, DQ5, DQ3 and DQ2.

Figure 18.2

,

Figure 18.6

, Figure 18.8

and Figure 18.9

show

RY/BY# for read, reset, program, and erase operations, respectively.

Document Number: 002-00948 Rev. *A Page 36 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Write Operation Status

Standard

Mode

Erase

Suspend

Mode

Operation

Embedded Program Algorithm

Embedded Erase Algorithm

Reading within Erase

Suspended Sector

Reading within Non-Erase

Suspended Sector

Erase-Suspend-Program

DQ7

(Note 2)

DQ7#

0

1

Data

DQ6

Toggle

Toggle

No toggle

Data

DQ5

(Note 1)

DQ3

0

0

0

Data

N/A

Data

DQ2

(Note 2)

N/A No toggle

1 Toggle

Toggle

Data

RY/BY#

0

0

1

1

DQ7# Toggle 0 N/A N/A 0

Notes

1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See

DQ5: Exceeded Timing Limits on page 36 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. See DQ7: Data# Polling on page 32

and

DQ2: Toggle Bit II on page 34

for further details.

8.9

Reset Command

Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command.

The reset command may be written between the cycles in an erase command sequence before erasing begins. This resets the device to the read mode. However, once erasure begins, the device ignores the reset commands until the operation is complete.

The reset command may be written between the cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. However, once programming begins, the device ignores the reset commands until the operation is complete.

The reset command may be written between the cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to exit the autoselect mode and return to the read mode.

If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode or erasesuspend-read-mode if the device was in Erase Suspend. When the reset command is written, before the embedded operation starts, the device requires t

RR

before it returns to the read or erase-suspend-read mode.

Reset Command Timing

Parameter

t

RR

Description

Reset Command to Read Mode or Erase-Suspend-Read Mode

Max.

250

Unit

ns

9.

Advanced Sector Protection/Unprotection

The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in

Figure 9.1

.

Document Number: 002-00948 Rev. *A Page 37 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Hardware Methods

Figure 9.1 Advanced Sector Protection/Unprotection

Software Methods

WP# = V

IL

(Two outermost sectors locked in large bank)

Password Method

Persistent Method

64-bit Password

(One Time Protect)

Memory Array

Sector Group 0

Sector Group 1

Sector Group 2

Sector Group N-2

Sector Group N-1

Sector Group N

4

4. N = 23 for S29CD016J/CL016J,

31 for S29CD032J/CL032J.

PPB Lock Bit

1,2,3

0 = PPBs Unlocked

1 = PPBs Locked

Persistent

Protection Bit

(PPB)

5,6

PPB 0

PPB 1

PPB 2

1. Bit is volatile, and defaults to “0” on reset.

2. Programming to “1” locks all PPBs to their current state.

3. Once programmed to “1”, requires hardware reset to unlock.

Dynamic

Protection Bit

(DYB)

7,8,9

DYB 0

DYB 1

DYB 2

PPB N-2

PPB N-1

PPB N

5. PPBs programmed individually, but cleared collectively.

6. 0 = Sector Group Unprotected;

1 = Sector Group Protected

DYB N-2

DYB N-1

DYB N

7. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is “0”

(unprotected).

8. Volatile Bits.

9. 0 = Sector Group Unprotected;

1 = Sector Group Protected

Document Number: 002-00948 Rev. *A Page 38 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

9.1

Advanced Sector Protection Overview

As shipped from the factory, all devices default to the persistent mode when power is applied, and all sector groups are unprotected.

The device programmer or host system must then choose which sector group protection method to use. Programming (setting to “0”) any one of the following two one-time programmable, non-volatile bits locks the device permanently in that mode:

 Persistent Protection Mode Lock Bit

 Password Protection Mode Lock Bit

After selecting a sector group protection method, each sector group can operate in any of the following three states:

1. Persistently Locked. A sector group is protected and cannot be changed.

2. Dynamically locked. The selected sector groups are protected and can be altered via software commands.

3. Unlocked. The sector groups are unprotected and can be erased and/or programmed.

These states are controlled by the bit types described in sections

Persistent Protection Bits on page 39

to

Hardware Data Protection

Methods on page 43 .

Notes

1. If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit.

The user must be sure that the password is correct when the Password Mode Locking Bit is set, as there is no means to verify the password afterwards.

2. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts.

3. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password

Mode is permanently disabled.

4. It is important that the mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is impossible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection

Mode.

5. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without modifying the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs, after which the device returns to read mode without having erased the protected sector.

6. For the command sequence required for programming the lock register bits, refer to Command Definitions on page 71

.

9.2

Persistent Protection Bits

The Persistent Protection Bits are unique and nonvolatile. A single Persistent Protection Bit is assigned to a maximum for four sectors (see the sector address tables for specific sector protection groupings). All eight-Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility.

Notes

1. Each PPB is individually programmed and all are erased in parallel. There are no means for individually erasing a specific

PPB and no specific sector address is required for this operation.

2. If a PPB requires erasure, all of the sector PPBs must first be programmed prior to PPB erasing. It is the responsibility of the user to perform the preprogramming operation. Otherwise, an already erased sector PPB has the potential of being over-erased. There is no hardware mechanism to prevent sector PPB over-erasure.

3. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB.

9.2.1

Programming PPB

The PPB Program Command is used to program, or set, a given PPB. The first three cycles in the PPB Program Command are standard unlock cycles. The fourth cycle in the PPB Program Command executes the pulse which programs the specified PPB. The

Document Number: 002-00948 Rev. *A Page 39 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

user must wait either 100 µs or until DQ6 stops toggling before executing the fifth cycle, which is the read verify portion of the PPB

Program Command. The sixth cycle outputs the status of the PPB Program operation.

In the event that the program PPB operation was not successful, the user can loop directly to the fourth cycle of the PPB Program

Command to perform the program pulse and read verification again. After four unsuccessful loops through the program pulse and read verification cycles the PPB programming operation should be considered a failure.

Figure 9.2 PPB Program Operation

Write 0xAA to 0x555

Write 0x55 to 0x2AA

Write 0x60 to 0x555

Write 0x68 to SG+WP

Either poll DQ6 in the small bank and wait for it to stop toggling OR wait 100

μs

Write 0x48 to SG+WP

Read from SG+WP

Note: Reads from the small bank at this point return the status of the operation, not read array data.

NO

5th attempt?

YES

Error

NO

DQ0 = 1?

YES

Done

9.2.2

Erasing PPB

The All PPB Erase command is used to erase all the PPBs in bulk. There are no means for individually erasing a specific PPB. The first three cycles of the PPB Erase command are standard unlock cycles. The fourth cycle executes the erase pulse to all the PPBs.

The user must wait either 20 ms or until DQ6 stops toggling before executing the fifth cycle, which is the read verify portion of the

PPB Erase Command. The sixth cycle outputs the status of the PPB Erase operation.

In the event that the erase PPB operation was not successful, the user can loop directly to the fourth cycle of the All PPB Erase

Command to perform the erase pulse and read verification again. After four unsuccessful loops through the erase pulse and read verification cycles, the PPB erasing operation should be considered a failure.

Note

 All PPB must be preprogrammed prior to issuing the All PPB Erase Command.

Document Number: 002-00948 Rev. *A Page 40 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Figure 9.3 PPB Erase Operation

Write 0xAA to 0x555

Write 0x55 to 0x2AA

Write 0x60 to 0x555

Write 0x60 to WP

Either poll DQ6 in the small bank and wait for it to stop toggling OR wait 20 ms

Write 0x40 to WP

Read from WP

Note: Reads from the small bank at this point return the status of the operation, not read array data.

NO

NO

5th attempt?

YES

Error

DQ0 = 0?

YES

Done

9.3

Persistent Protection Bit Lock Bit

The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set to “1”, it locks all PPBs; when set to “0”, it allows the PPBs to be changed. There is only one PPB Lock Bit per device.

Notes

1. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit.

2. The PPB Lock Bit must be set only after all PPBs are configured to the desired settings.

9.4

Dynamic Protection Bits

A Dynamic Protection Bit (DYB) is volatile and unique for each sector group and can be individually modified. DYBs only control the protection scheme for unprotected sector groups that have their PPBs set to “0”. By issuing the DYB Set or Clear command sequences, the DYBS are set or cleared, thus placing each sector group in the protected or unprotected state respectively. This feature allows software to easily protect sector groups against inadvertent changes, yet does not prevent the easy removal of protection when changes are needed.

Notes

1. The DYBs can be set or cleared as often as needed with the DYB Write Command.

2. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the PPBs are changeable. The DYB are also always cleared after a power-up or reset.

3. It is possible to have sector groups that are persistently locked with sector groups that are left in the dynamic state.

Document Number: 002-00948 Rev. *A Page 41 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

4. The DYB Set or Clear commands for the dynamic sector groups signify the protected or unprotected state of the sector groups respectively. However, if there is a need to change the status of the persistently locked sector groups, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again.

Sector Protection Schemes

0

1

1

1

1

DYB

0

0

0

1

0

0

1

1

PPB

0

0

1

PPB Lock

0

1

0

1

1

0

0

1

Sector State

Unprotected—PPB and DYB are changeable

Unprotected—PPB not changeable, DYB is changeable

Protected—PPB and DYB are changeable

Protected—PPB not changeable, DYB is changeable

9.5

Password Protection Method

The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a

64-bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power-up and reset, the PPB

Lock Bit is set “1” in order to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.

Notes

1. There is no special addressing order required for programming the password. Once the password is written and verified, the Password Mode Locking Bit must be set in order to prevent access.

2. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out with the cell as a “0”. (This is an OTP area).

3. The password is all “1”s when shipped from the factory.

4. When the password is undergoing programming, Simultaneous Read/Write operation is disabled. Read operations to any memory location returns the programming status. Once programming is complete, the user must issue a Read/Reset command to return the device to normal operation.

5. All 64-bit password combinations are valid as a password.

6. There is no means to read, program or erase the password is after it is set.

7. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming.

8. The Password Mode Lock Bit is not erasable.

9. The exact password must be entered in order for the unlocking function to occur.

10. There is a built-in 2-µs delay for each password check. This delay is intended to stop any efforts to run a program that tries all possible combinations in order to crack the password.

Document Number: 002-00948 Rev. *A Page 42 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

9.6

Hardware Data Protection Methods

The device offers several methods of data protection by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describe these methods.

9.6.1

WP# Method

The Write Protect feature provides a hardware method of protecting the two outermost sectors of the large bank.

If the system asserts V

IL

on the WP# pin, the device disables program and erase functions in the two “outermost” boot sectors (8-

Kbyte sectors) in the large bank. If the system asserts V

IH

on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected.

Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result.

The WP# pin must be held stable during a command sequence execution

9.6.2

Low V

CC

Write Inhibit

When V

CC

is less than V

LKO

, the device does not accept any write cycles. This protects data during V

CC

power-up and power-down.

The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until V

CC

is greater than V

LKO

. The system must provide the proper signals to the control inputs to prevent unintentional writes when V

CC

is greater than V

LKO

.

9.6.3

Write Pulse “Glitch Protection”

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

9.6.4

Power-Up Write Inhibit

If WE# = CE# = RESET# = V

IL

and OE# = V

IH

during power-up, the device does not accept commands on the rising edge of WE#.

The internal state machine is automatically reset to the read mode on power-up.

9.6.5

V

CC

and V

IO

Power-up And Power-down Sequencing

The device imposes no restrictions on V

CC

and V

IO

power-up or power-down sequencing. Asserting RESET# to V

IL

is required during the entire V

CC

and V

IO

power sequence until the respective supplies reach the operating voltages. Once V

CC

and V

IO

attain the operating voltages, deassertion of RESET# to V

IH

is permitted. Refer to timing in

V

CC

and V

IO

Power-up on page 51 .

9.6.6

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V

IL

, CE# = V

IH

, or WE# = V

IH

. To initiate a write cycle, CE# and WE# must be a logical zero (V

IL

) while OE# is a logical one (V

IH

).

Document Number: 002-00948 Rev. *A Page 43 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

10. Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic

Serial Number (ESN). The Secured Silicon Sector is a 256-byte flash memory area that is either programmable at the customer, or

by Spansion at the request of the customer. See Table for the Secured Silicon Sector address ranges.

All Secured Silicon reads outside of the 256-byte address range return invalid data.

Secured Silicon Sector Addresses

Ordering Option

Top Boot

Bottom Boot

Sector Size (Bytes)

256

256

Address Range

00000h-0003Fh (16 Mb and 32 Mb)

FFFC0h–FFFFFh (32 Mb)

7FFC0h–7FFFFh (16 Mb)

The device allows Simultaneous Read/Write operation while the Secured Silicon Sector is enabled. However, several restrictions are associated with Simultaneous Read/Write operation and device operation when the Secured Silicon Sector is enabled:

1. The Secured Silicon Sector is not available for reading while the Password Unlock, any PPB program/erase operation, or

Password programming are in progress. Reading to any location in the small bank will return the status of these operations until these operations have completed execution.

2. Programming the DYB associated with the overlaid boot-block sector results in the DYB NOT being updated. This occurs only when the Secured Silicon sector is not enabled.

3. Reading the DYB associated with the overlaid boot-block sector when the PPB Lock/DYB Verify command is issued, causes the read command to return invalid data. This function occurs only when the Secured Silicon Sector is not enabled.

4. All commands are available for execution when the Secured Silicon Sector is enabled, except the following: a. Any Unlock Bypass command b. CFI c. Accelerated Program d. Program and Sector Erase Suspend e. Program and Sector Erase Resume

Issuing the above commands while the Secured Silicon Sector is enabled results in the command being ignored.

5. It is valid to execute the Sector Erase command on any sector other than the Secured Silicon Sector when the Secured

Silicon Sector is enabled. However, it is not possible to erase the Secured Silicon Sector using the Sector Erase

Command, as it is a one-time programmable (OTP) area that can not be erased.

6. Executing the Chip Erase command is permitted when the Secured Silicon Sector is enabled. The Chip Erase command erases all sectors in the memory array, except for sector 0 in top-boot block configuration, or sector 45 in bottom-boot block configuration. The Secured Silicon Sector is a one-time programmable memory area that cannot be erased.

7. Executing the Secured Silicon Sector Entry command during program or erase suspend mode is allowed. The Sector

Erase/Program Resume command is disabled when the Secured Silicon sector is enabled; the user cannot resume programming of the memory array until the Exit Secured Silicon Sector command is written.

8. Address range 00040h–007FFh for the top bootblock, and FF00h–FFF7Fh return invalid data when addressed with the

Secured Silicon sector enabled.

9. The Secured Silicon Sector Entry command is allowed when the device is in either program or erase suspend modes. If the Secured Silicon sector is enabled, the program or erase suspend command is ignored. This prevents resuming either programming or erasure on the Secured Silicon sector if the overlayed sector was undergoing programming or erasure.

The host system must ensure that the device resume any suspended program or erase operation after exiting the

Secured Silicon sector.

Document Number: 002-00948 Rev. *A Page 44 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

10.1

Secured Silicon Sector Protection Bit

The Secured Silicon Sector can be shipped unprotected, allowing customers to utilize that sector in any manner they choose.

Please note the following:

 The Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Secured Silicon

Sector Protection Bit must be used with caution as once locked, there is no procedure available for unlocking the Secured Silicon

Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.

 Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return the device to the memory array.

10.2

Secured Silicon Sector Entry and Exit Commands

The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured

Silicon Sector command sequence. See the Table , Memory Array Command Definitions (x32 Mode) on page 71

and Table , Sector

Protection Command Definitions (x32 Mode) on page 72

for address and data requirements for both command sequences.

The Secured Silicon Sector Entry Command allows the following commands to be executed

 Read Secured Silicon areas

 Program Secured Silicon Sector (only once)

After the system has written the Enter Secured Silicon Sector command sequence, it can read the Secured Silicon Sector by using the addresses listed in

Table , Secured Silicon Sector Addresses on page 44 . This mode of operation continues until the system

issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device.

11. Electronic Marking

Electronic marking has been programmed into the device, prior to shipment from Spansion, to ensure traceability of individual products. The electronic marking is stored and locked within a one-time programmable region. Detailed information on Electronic

Marking will be provided in a data sheet supplement.

12. Power Conservation Modes

12.1

Standby Mode

When the system is not reading or writing to the device, it can place the device in standby mode. In this mode, current consumption is greatly reduced, and outputs are placed in a high impedance state, independent of OE# input. The device enters CMOS standby mode when the CE# and RESET# inputs are both held at

V

CC

± 10%. The device requires standard access time (t

CE

) for read access before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed.

I

CC5

in DC Characteristic, CMOS Compatible on page 48

represents the standby current specification.

Document Number: 002-00948 Rev. *A Page 45 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Caution

Entering standby mode via the RESET# pin also resets the device to read mode and floats the data I/O pins. Furthermore, entering

I

CC7

during a program or erase operation leaves erroneous data in the address locations being operated on at the time of the

RESET# pulse. These locations require updating after the device resumes standard operations. See

Hardware RESET# Input

Operation on page 46

for further discussion of the RESET# pin and its functions.

12.2

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. While in sleep mode, output data is latched and always available to the system.

While in asynchronous mode, the device automatically enables this mode when addresses remain stable for t

ACC

+ 60 ns. Standard address access timings provide new data when addresses are changed. While in synchronous mode, the device automatically enables this mode when either the first active CLK level is greater than t

ACC

or the CLK runs slower than 5 MHz. A new burst operation is required to provide new data.

I

CC8

in DC Characteristic, CMOS Compatible on page 48

represents the automatic sleep mode current specification.

12.3

Hardware RESET# Input Operation

The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. Any operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, in order to ensure data integrity.

When RESET# is held at V

SS

±0.2 V, the device draws CMOS standby current (I

CC4

). If RESET# is held at V

IL

but not within V

SS

±0.2 V, the standby current is greater.

RESET# may be tied to the system reset circuitry, thus a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset operation is internally complete. This action requires between 1 µs and 7 µs for either Chip Erase or Sector Erase. The RY/BY# pin can be used to determine whether the reset operation is complete. Otherwise, allow for the maximum reset time of 11 µs.

If RESET# is asserted when a program or erase operation is not executing (RY/BY# = 1), the reset operation completes within 500 ns. The Simultaneous Read/Write feature of this device allows the user to read a bank after 500 ns if the bank is in the read/reset mode at the time RESET# is asserted. If one of the banks is in the middle of either a program or erase operation when RESET# is asserted, the user must wait 11 µs before accessing that bank.

Asserting RESET# active during V

CC

and V

IO

power up is required to guarantee proper device initialization until V reached steady state voltages.

CC

and V

IO

have

12.4

Output Disable (OE#)

When the OE# input is at V

IH

, output from the device is disabled. The outputs are placed in the high impedance state.

Document Number: 002-00948 Rev. *A Page 46 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

13. Electrical Specifications

13.1

Absolute Maximum Ratings

Absolute Maximum Ratings

Storage Temperature, Plastic Packages

Ambient Temperature with Power Applied

V

CC

, V

IO

(Note 1) for 2.6 V devices (S29CD-J)

V

CC

, V

IO

(Note 1) for 3.3 V devices (S29CL-J)

ACC, A9, and RESET# (Note 2)

Address, Data, Control Signals

Parameter

(Note 1)

(with the exception of CLK)

All other pins

(Note 1)

Rating

–65 °C to +150 °C

–65 °C to +145 °C

–0.5V to +3.6V

–0.5V to +3.6V

–0.5V to +13.0V

–0.5V to +3.6V (CL016J)

–0.5V to +2.75V (CD016J)

–0.5V to +3.6V (CL032J)

–0.5V to +2.75V (CD032J)

200 mA

Output Short Circuit Current

(Note 3)

Notes

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot V

SS

to –2.0V for periods of up to 20 ns. See Figure 13.2

.

Maximum DC voltage on output and I/O pins is 3.6V. During voltage transitions output pins may overshoot to V

CC

+ 2.0V for periods up to 20 ns. See Figure 13.2

.

2. Minimum DC input voltage on pins ACC, A9, and RESET# is -0.5V. During voltage transitions, A9 and RESET# may overshoot

V

SS

to –2.0V for periods of up to 20 ns. See

Figure 13.1

. Maximum DC input voltage on pin A9 is +13.0V which may overshoot to 14.0V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

4. Stresses above those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 13.1 Maximum Negative Overshoot Waveform

20 ns 20 ns

+0.8 V

–0.5 V

–2 V

20 ns

Figure 13.2 Maximum Positive Overshoot Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V

20 ns 20 ns

Document Number: 002-00948 Rev. *A Page 47 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

14. Operating Ranges

Operating Ranges

Parameter

Industrial Devices

Ambient Temperature (T

A

)

Extended Devices

V

V

CC

IO

Supply Voltages

Supply Voltages

V

CC

for 2.6V regulated voltage range (S29CD-J devices)

V

CC

for 3.3V regulated voltage range (S29CL-J devices)

V

IO

(S29CD-J devices)

V

IO

(S29CL-J devices)

Note

Operating ranges define those limits between which the functionality of the device is guaranteed.

Range

–40°C to +85°C

–40°C to +125°C

2.50V to 2.75V

3.00V to 3.60V

1.65V to 2.75V

1.65V to 3.6V

15. DC Characteristics

I

CC3

I

CC4

I

CC5

I

CC6

I

CC7

I

CC8

I

ACC

V

IL

V

IH

V

ILCLK

V

IHCLK

V

IHCLK

V

ID

V

OL

I

OLRB

V

HH

V

OH

V

LKO

DC Characteristic, CMOS Compatible

Parameter Description

I

LI

I

LIWP

I

LIT

I

LO

Input Load Current

WP# Input Load Current

A9, ACC Input Load Current

Output Leakage Current

I

CCB

I

CC1

V

CC

Active Burst Read Current

(1)

V

CC

Active Asynchronous

Read Current

(1)

V

CC

Active Program Current

(

2 , 3 , 4

)

V

CC

Active Erase Current (

2 , 3 , 4

)

V

CC

Standby Current (CMOS)

V

CC

Active Current

(Read While Write) (3)

V

CC

Reset Current

Automatic Sleep Mode Current

V

ACC

Acceleration Current

Input Low Voltage

Input High Voltage

CLK Input Low Voltage

CLK Input High Voltage (CD-J)

CLK Input High Voltage (CL-J)

Voltage for Autoselect

Output Low Voltage

RY/BY#, Output Low Current

Accelerated (ACC pin) High Voltage

Output High Voltage

Low V

CC

Lock-Out Voltage (3)

Test Conditions

V

IN

= V

SS

to V

IO

, V

IO

= V

IO max

V

IN

= V

SS

to V

IO

, V

IO

= V

IO max

V

CC

= V

CCmax

; A9 = 12.5V

V

OUT

= V

SS

to V

CC

, V

CC

= V

CC max

CE# = V

Word

IL

, OE# = V

IL

, 8 Double

S29CD-J

S29CL-J

CE# = V

IL

, OE# = V

IL

1 MHz

Min Typ

45

65

Max

1.0

–25

35

1.0

55

90

10

CE# = V

IL

, OE# = V

IH

, ACC = V

IH

CE# = V

IL

, OE# = V

IH

, ACC = V

IH

V

CC

= V

CC max

, CE# = V

CC

 0.3V

40

20

50

50

60

CE# = V

IL

, OE# = V

IL

30 90

RESET# = V

IL

V

IH

= V

CC

0.3 V, V

IL

= V

SS

0.3V

ACC = V

HH

60

60

20

–0.5

0.7 x V

–0.2

IO

0.3 x V

IO

V

CC

0.3 x V

IO

2.75

0.7 x V

CC

0.7 x V

CC

3.6

I

I

V

CC

= 2.5V

11.5

12.5

I

OL

= 4.0 mA, V

CC

= V

CC min

0.45

V

OL

= 0.4V

8

OH

OH

= –2.0 mA, V

CC

= –100 µA, V

CC

= V

CC min

= V

CC min

0.85 x V

CC

V

IO

–0.1

1.6

2.0

mA mA

µA mA

V

V mA

V

V

V

V

V

V

V

µA

µA mA

V

Unit

µA

µA

µA

µA mA mA mA

Document Number: 002-00948 Rev. *A Page 48 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Notes

1. The I

CC

current listed includes both the DC operating current and the frequency dependent component.

2. I

CC

active while Embedded Erase or Embedded Program is in progress.

3. Not 100% tested.

4. Maximum I

CC

specifications are tested with V

CC

= V

CCmax

.

15.1

Zero Power Flash

Figure 15.1 I

CC1

Current vs. Time (Showing Active and Automatic Sleep Currents)

Note

Addresses are switching at 1 MHz

4

3

2

1

0

0 500 1000 1500 2000

Time in ns

2500 3000 3500 4000

Figure 15.2 Typical I

CC1

vs. Frequency

5

4

3

2

1

0

1 2 4

2.7 V

5 3

Frequency in MHz

Document Number: 002-00948 Rev. *A Page 49 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

16. Test Conditions

Figure 16.1 Test Setup

Device

Under

Test

C

L

17. Test Specifications

Test Specifications

Test Condition

Output Load

Output Load Capacitance, C

L

(including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

Input timing measurement reference levels

Output timing measurement reference levels

Key to Switching Waveforms

Waveform

All Options

1 TTL gate

30

5

0.0V – V

IO

V

IO

/2

V

IO

/2

Unit

pF ns

V

V

V

Inputs Outputs

Don’t Care, Any Change Permitted

Does Not Apply

Steady

Changing from H to L

Changing from L to H

Changing, State Unknown

Center Line is High Impedance State (High-Z)

17.1

Switching Waveforms

V

IO

V

SS

Figure 17.1 Input Waveforms and Measurement Levels

Input V

IO

/2 V Measurement Level V

IO

/2 V Output

Document Number: 002-00948 Rev. *A Page 50 of 86

18. AC Characteristics

18.1

V

CC

and V

IO

Power-up

V

CC

and V

IO

Power-up

Parameter

t

VCS t

VIOS t

RSTH

Description

V

CC

Setup Time

V

IO

Setup Time

RESET# Low Hold Time

Test Setup

Min

Min

Min

Figure 18.1 V

CC

and V

IO

Power-up Diagram

Speed

50

50

50 t

VCS

Unit

µs

µs

µs

V

CC t

VIOS

V

IOP t

RSTH

RESET#

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document Number: 002-00948 Rev. *A Page 51 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

18.2

Asynchronous Operations

Asynchronous Read Operations

Parameter

JEDEC Std.

t

AVAV t

RC t

AVQV t

ELQV t

GLQV t

EHQZ t t t t

ACC

CE

OE

DF

Description

Read Cycle Time (Note 1)

Address to Output Delay

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

(Note 1)

t

GHQZ t

DF

Output Enable to Output High-Z (Note 1)

t

AXQX t

OEH t

OH

Output Enable Hold Time

(Note 1)

Read

Toggle and

Data# Polling

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First (Note 1)

Notes

1. Not 100% tested.

2. See

Figure 16.1

and Table

for test specifications.

3. TOE during Read Array.

Test Setup

Min

CE# = V

IL

OE# = V

IL

OE# = V

IL

Max

Max

Max

Max

Min

Max

Min

Min

Min

75 MHz

0R

Speed Options

66 MHz

0P

54

56 MHz

0M

40 MHz

0J/1J Unit

ns ns 54

54

20

10 ns ns ns

2

10

0 ns ns ns

10 ns

2 ns

Addresses

Figure 18.2 Conventional Read Operations Timings t

RC t

ACC

Addresses Stable

CE# t

DF t

OE

OE# t

OEH

WE# t

CE t

OH

High Z High Z

Outputs

Output Valid

RESET#

RY/BY#

0 V

Document Number: 002-00948 Rev. *A Page 52 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Figure 18.3 Asynchronous Command Write Timing

CLK

ADV#

CE#

Addresses

Data

WE#

OE#

IND/WAIT# t t

CS t

WC

Stable Address

AS t

CH t

AH

Valid Data t

DS t

DH t

WEH t

OEP

Notes

1. All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register.

2. Refer to Table for write timing parameters.

Document Number: 002-00948 Rev. *A Page 53 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

18.3

Synchronous Operations

Burst Mode for 32 Mb and 16 Mb

Parameter

JEDEC

t t

DF

EHQZ

Description

Std.

t

BACC t

ADVCS t

ADVCH t

ADVP t t t t t t t t t t t

BDH

INDS

INDH

IACC t t

CLK

CR

CF

CLKH

CLKL t

OE

OEZ

CEZ

CES

AAVS t

AAVH

Burst Access Time Valid Clock to Output Delay

ADV# Setup Time to Rising Edge of CLK

ADV# Hold Time from Rising Edge of CLK

ADV# Pulse Width

Valid Data Hold from CLK

CLK to Valid IND/WAIT#

(Note 2)

IND/WAIT# Hold from CLK

CLK to Valid Data Out, Initial Burst Access

CLK Period

CLK Rise Time

CLK Fall Time

CLK Low Time

(Note 2)

(Note 2)

CLK High Time

(Note 3)

(Note 3)

(Note 2)

(Note 2)

Output Enable to Output Valid

Output Enable to Output High-Z (Note 2)

16 Mb

32 Mb

Max

Min

Max

Max

Max

Min

Min

Max

Min

Max

Max

Min

Min

Min

Min

Min

Max

Min

Chip Enable to Output High-Z

(Note 2)

CE# Setup Time to Clock

Max

Min

ADV# Falling Edge to Address Valid

(Note 1)

Max

Address Hold Time from Rising Edge of ADV# Min t

RSTZ t

WADVH1 t

WADVH2 t

WADVS

RESET# Low to Output High-Z

(Note 2)

ADV# Falling Edge to WE# Falling Edge

ADV# Rising Edge to WE# Rising Edge

WE# Rising Edge Setup to ADV# Falling Edge

Notes

1.

Using the max t

AAVS

and min t

ADVCS

specs together will result in incorrect data output.

2. Not 100% tested

3. Recommended 50% Duty Cycle

Max

Min

Min

Min

75 MHz,

0R

8

7.5

2

0

2

48

13.3

6.65

6.65

2

7.5

7.5

4

Speed Options

66 MHz,

0P

8

6

1.5

56 MHz,

0M

8

8.5

2

0

9.5

3

0

8

2

54

15.15

3

54

17.85

60

3

3

6.8

6.8

8.0

8.0

20

2

10

10

4

3

15

15

5

6.5

40 MHz,

0J/1J

8

10.5

3

0

3

54

25

11.25

11.25

3

17

17

6

7.5

10

1

0

10

11.75

15 17 ns ns ns

CLK cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Unit

ns ns ns ns ns ns

Document Number: 002-00948 Rev. *A Page 54 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

CE#

CLK

ADV# t

ADVCS

Figure 18.4 Burst Mode Read (x32 Mode) t

CES

Addresses t

AAVH

Aa t

BDH t

BACC

Data t

AAVS t

IACC

Da t

OE

Da+1 Da+2

OE#

Da + 3

IND# t

INDS t

CEZ

Da + 7 t

OEZ t

INDH

Figure 18.5 Synchronous Command Write/Read Timing

CE#

t

CES

CLK

t

ADVCS t

ADVP

ADV#

Addresses

Valid Address t

AS

Valid Address t

ADVCH

Valid Address t

WC t

EHQZ

Data

Data In

Data Out t

WADVH2 t

DF t

WADVH1 t

OE

OE#

t

DH t

DS t

WP

WE#

10 ns t

WADVS

IND/WAIT#

Note

All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register.

Document Number: 002-00948 Rev. *A Page 55 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

18.4

Hardware Reset (RESET#)

Hardware Reset (RESET#)

Parameter

JEDEC Std.

t

READY t

READY2 t

RP t

RH t

RPD t

RB t

READY3

Description

RESET# Pin Low (During embedded Algorithms) to Read or Write

(See Note)

Test Setup

Max

RESET# Pin Low (Not during embedded Algorithms) to Read or

Write (See Note)

Min

RESET# Pulse Width

RESET# High time Before Read

(See Note)

RESET# Low to Standby Mode

RY/BY # Recovery Time

RESET # Active for Bank NOT Executing Algorithm

Min

Min

Min

Min

Min

All Speed

Options

11

500

500

20

0

500

Unit

µs ns ns

50 ns

µs ns ns

Note

Not 100% tested.

Figure 18.6 RESET# Timings

RY/BY#

CE#, OE#

RESET# t

RH t

RP t

READY2

Reset Timing to Bank NOT Executing Embedded Algorithm

Reset Timing to Bank Executing Embedded Algorithm t

READY

RY/BY# t

RB

CE#, OE#

RESET# t

RP

Document Number: 002-00948 Rev. *A Page 56 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

18.5

Write Protect (WP#)

Data

WE#

WP#

RY/BY#

Figure 18.7 WP# Timing t

WPWS

Program/Erase Command t

DH t

WP t

DS

Valid WP# t

BUSY

18.6

Erase/Program Operations

Erase/Program Operations

Parameter

JEDEC Std.

t

AVAX t

AVWL t

WLAX t

DVWH t

WHDX t

WC t

AS t

AH t

DS t

DH

Write Cycle Time (Note 1)

Address Setup Time

Description

Address Hold Time from WE# Falling Edge

Data Setup to WE# Rising Edge t

GHWL t

WEH

Data Hold from WE# Rising Edge

Read Recovery Time Before Write

(OE# High to WE# Low, WE# Hold Time)

(Note 1)

t t t t t t

ELWL

WHEH

WLWH

WHWL

WHWH1

WHWH2 t

OEP t

CS t

CH t

WP t

WPH t

WHWH1 t

WHWH2 t

VCS t

RB t

BUSY t

WPWS t

WPRH

OE# Pulse Width

CE# Setup Time

CE# Hold Time

WE# Width

Write Pulse Width High

Programming Operation

Sector Erase Operation

V

CC

Setup Time

(Note 1)

(Note 1)

(Note 2)

(Note 2)

Recovery Time from RY/BY#

, Double-Word

(Note 1)

RY/BY# Delay After WE# Rising Edge

WP# Setup to WE# Rising Edge with Command

WP# Hold after RY/BY# Rising Edge

(Note 1)

(Note 1)

(Note 1)

Notes

1. Not 100% tested.

2. See

Command Definitions on page 71

for more information.

3. Program Erase Parameters are the same, regardless of Synchronous or Asynchronous mode.

Min

Min

Min

Min

Min

Min

Min

Typ

Typ

Min

Min

Min

Min

Min

Min

Max

Min

Max

0

30

9

0.5

50

16

0

0

25

0

90

20

2

All Speed

Options

60

0

11.75

18

2

Unit

ns ns ns ns ns ns ns

µs sec.

µs ns ns ns ns ns ns ns ns t

WPRH

Document Number: 002-00948 Rev. *A Page 57 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Figure 18.8 Program Operation Timings

Program Command Sequence (last two cycles) t

WC t

AS

555h PA

Read Status Data (last two cycles)

PA PA Addresses

CE#

OE# t

CH t

AH

WE# t

CS t

WP t

DS t

DH

A0h t

WPH

Data

RY/BY#

V

CC t

VCS

Note

PA = program address, PD = program data, D

OUT

is the true data at the program address.

PD t

DH t

BUSY t

WHWH1

Status

D

OUT t

RB

Document Number: 002-00948 Rev. *A Page 58 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Addresses

Figure 18.9 Chip/Sector Erase Operation Timings

Erase Command Sequence (last two cycles) t

WC

2AAh t

AS

SA

555h for chip erase

Read Status Data

VA

VA

CE#

OE# t

CH t

AH t

WP

WE# t

CS t

WPH t

WHWH2 t

DS t

DH t

DH

Data

30h

10 for Chip Erase t

BUSY

RY/BY# t

VCS

V

CC

Note

SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 31

).

In

Progress

Complete t

RB

Document Number: 002-00948 Rev. *A Page 59 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Addresses

CE# t

WC

Valid PA t

AH

Figure 18.10 Back-to-back Cycle Timings t

RC

Valid RA t

WC

Valid PA t

ACC t

CE t

OE t

CPH t

WC

Valid PA t

CP

OE# t

OEH t

GHWL t

WP t

WPH

WE#

Data t

WPH t

DS

Valid

In t

DH t

OH

Valid

Out t

DF

Valid

In

Valid

In t

SR/W

WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles

Addresses

CE#

OE#

WE#

DQ7

Figure 18.11 Data# Polling Timings (During Embedded Algorithms) t

ACC t

CE t

RC

VA VA t

CH t

OE t

OEH t

DF t

OH

Complement Complement

True

Data

Status Data Status Data True t

BUSY

RY/BY#

Note

VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

t

WC

VA

Valid Data

Valid Data

High Z

High Z

Document Number: 002-00948 Rev. *A Page 60 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Addresses

Figure 18.12 Toggle Bit Timings (During Embedded Algorithms) t

ACC t

CE t

RC

VA VA VA VA

CE# t

CH t

OE

OE#

WE#

DQ6/DQ2 t

OEH

High Z t

DF t

OH

Valid Status

(first read)

Valid Status

(second read)

Valid Status

(stops toggling)

Valid Data t

BUSY

RY/BY#

Note

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

Document Number: 002-00948 Rev. *A Page 61 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

WE#

Figure 18.13 DQ2 vs. DQ6 for Erase/Erase Suspend Operations

Enter Embedded

Erasing

Erase

Erase

Suspend

Erase Suspend

Read

Enter Erase

Suspend Program

Erase Suspend

Program

Erase Suspend

Read

Erase

Resume

Erase

DQ6

Erase

Complete

DQ2

Note

The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.

Figure 18.14 Synchronous Data Polling Timing/Toggle Bit Timings

CE#

CLK

ADV#

Addresses

V A

V A

OE#

Data t

OE t

OE

Status Data

Status Data

RDY

Notes

1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling.

3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data.

4. Data polling requires burst access time delay.

Document Number: 002-00948 Rev. *A Page 62 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Figure 18.15 Sector Protect/Unprotect Timing Diagram

RESET#

V

IH

SA, A6,

A1, A0

Data

1 µs

Valid*

Sector Protect/Unprotect

60h 60h/68h**

Sector Protect: 150 µs

Sector Unprotect: 15 ms

Valid*

Verify

40h/48h***

CE#

WE#

OE#

Notes

* Valid address for sector protect: A[7:0] = 3Ah. Valid address for sector unprotect: A[7:0] = 3Ah.

** Command for sector protect is 68h. Command for sector unprotect is 60h.

*** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h.

Valid*

Status

Document Number: 002-00948 Rev. *A Page 63 of 86

18.7

Alternate CE# Controlled Erase/Program Operations

Alternate CE# Controlled Erase/Program Operations

t t t t t t

Parameter

JEDEC

t

AVAV t

AVEL t

ELAX t

DVEH

EHDX

GHEL

WLEL

EHWH

ELEH t

EHEL t

WHWH1

WHWH2

Std.

t

WC t

AS t

AH t

DS t

DH t

GHEL t

WS t

WH t

WP t

CP t

CPH t

WHWH1 t

WHWH2 t

WCKS

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

16 Mb

Data Hold Time

32 Mb

Read Recovery Time Before Write (OE# High to WE# Low)

WE# Setup Time

WE# Hold Time

WE# Width

CE# Pulse Width

CE# Pulse Width High

Programming Operation

Sector Erase Operation

Description

(Note 2)

(Note 2)

WE# Rising Edge Setup to CLK Rising Edge

Notes

1. Not 100% tested.

2. See

Command Definitions on page 71

for more information.

Double-Word

Min

Min

Min

Min

Min

Min

Min

Typ

Typ

Min

Min

Min

Min

Min

Min

All Speed

Options

65

0

5

0

0

45

35

2

30

9

0.5

5

0

25

20 ns ns ns ns ns ns ns

µs sec ns

Unit

ns ns ns ns ns

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document Number: 002-00948 Rev. *A Page 64 of 86

Figure 18.16 Alternate CE# Controlled Write Operation Timings

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Addresses

Data# Polling

PA t

AS t

WC t

WH t

AH

WE# t

WP t

GHEL t

WPH

OE# t

CP t

WHWH1 or 2

CE# t

WS t

CPH t

DS t

DH t

BUSY

Data

DQ7# D

OUT t

RH A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D

OUT

= data written to the device.

2. Figure indicates the last two bus cycles of the command sequence.

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document Number: 002-00948 Rev. *A Page 65 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

18.8

Erase and Programming Performance

Erase and Programming Performance

Chip Erase Time

Parameter

Sector Erase Time

Double Word Program Time

Accelerated Double Word Program Time

Accelerated Chip Program Time

Chip Program Time, x32

(Note 3)

Typ

(Note 1)

0.5

16 Mb = 23

32 Mb = 46

8

8

16 Mb = 5

32 Mb = 10

16 Mb = 12

32 Mb = 24

Max

(Note 2)

5

16 Mb = 230

32 Mb = 460

130

130

16 Mb = 50

32 Mb = 100

16 Mb = 120

32 Mb = 240

Unit

s s

µs

µs s s

Excludes 00h programming prior to erasure

(Note 4)

Comments

Excludes system level overhead

(Note 5)

Notes

1. Typical program and erase times assume the following conditions: 25°C, 2.5V V

CC

, 100K cycles. Additionally, programming typicals assume checkerboard pattern.

2. Under worst case conditions of 145°C, V

CC

= 2.5V, 1M cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

and Table for further information on

command definitions.

6. PPBs have a program/erase cycle endurance of 100 cycles.

7. Guaranteed cycles per sector is 100K minimum.

18.9

PQFP and Fortified BGA Pin Capacitance

PQFP and Fortified BGA Pin Capacitance

Parameter Symbol

C

IN

C

OUT

C

IN2

Notes

1. Sampled, not 100% tested.

2. Test conditions T

A

= 25°C, f = 1.0 MHz.

Parameter Description

Input Capacitance

Output Capacitance

Control Pin Capacitance

Test Setup

V

IN

= 0

V

OUT

= 0

V

IN

= 0

Typ

6

8.5

7.5

Max

7.5

12

9

Unit

pF pF pF

Document Number: 002-00948 Rev. *A Page 66 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

19. Appendix 1

19.1

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be deviceindependent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses

given in Table -

Table . In order to terminate reading CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in

Table

-

Table

. The system must write the reset command to return the device to the autoselect mode.

For further information, please refer to the CFI Specification and CFI Publication 100. Contact a Spansion representative for copies of these documents.

CFI Query Identification String

Addresses

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

Data

0051h

0052h

0059h

0002h

0000h

0040h

0000h

0000h

0000h

0000h

0000h

Description

Query Unique ASCII string QRY

Primary OEM Command Set

Address for Primary Extended Table

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

Document Number: 002-00948 Rev. *A Page 67 of 86

CFI System Interface String

Addresses

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0000h

0004h

0000h

0009h

0000h

0005h

0000h

0007h

0000h

Data

(see description)

(see description)

Description

V

CC

Min. (write/erase)

DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt

0025h = S29CD-J devices

0030h = S29CL-J devices

V

CC

Max. (write/erase)

DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt

0027h = S29CD-J devices

0036h = S29CL-J devices

V

PP

Min. voltage (00h = no V

PP

pin present)

V

PP

Max. voltage (00h = no V

PP

pin present)

Typical timeout per single word/doubleword program 2

N

µs

Typical timeout for Min. size buffer program 2

N

µs (00h = not supported)

Typical timeout per individual block erase 2

N

ms

Typical timeout for full chip erase 2

N

ms (00h = not supported)

Max. timeout for word/doubleword program 2

N times typical

Max. timeout for buffer write 2

N times typical

Max. timeout per individual block erase 2

N

times typical

Max. timeout for full chip erase 2

N

times typical (00h = not supported)

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document Number: 002-00948 Rev. *A Page 68 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

Device Geometry Definition

Addresses Data

27h

28h

29h

(see description)

0003h

0000h

0000h

0000h

0003h

0007h

0000h

0020h

0000h

(See description)

0000h

0000h

0001h

0007h

0000h

0020h

0000h

0000h

0000h

0000h

0000h

Description

Device Size = 2

N

byte

0015h = 16 Mb device

0016h = 32 Mb device

Flash Device Interface description (for complete description, please refer to CFI publication 100)

0000 = x8-only asynchronous interface

0001 = x16-only asynchronous interface

0002 = supports x8 and x16 via BYTE# with asynchronous interface

0003 = x 32-only asynchronous interface

0005 = supports x16 and x32 via WORD# with asynchronous interface

Max. number of byte in multi-byte program = 2

N

(00h = not supported)

Number of Erase Block Regions within device

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

Address 31h data:

001Dh = 16 Mb device

003Dh = 32 Mb device

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

CFI Primary Vendor-Specific Extended Query (Sheet 1 of 2)

Addresses

40h

41h

42h

43h

44h

Data

0050h

0052h

0049h

0031h

0033h

Query-unique ASCII string PRI

45h

46h

000Ch

0002h

Description

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

Address Sensitive Unlock (DQ1, DQ0)

00 = Required, 01 = Not Required

Silicon Revision Number (DQ5–DQ2)

0000 = CS49

0001 = CS59

0010 = CS99

0011 = CS69

0100 = CS119

Erase Suspend (1 byte)

00 = Not Supported

01 = To Read Only

02 = To Read and Write

Document Number: 002-00948 Rev. *A Page 69 of 86

CFI Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Addresses

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

Data

0001h

51h 0000h

57h

58h

59h

5Ah

5Bh

0000h

0006h

0037h

0001h

0000h

00B5h

00C5h

0001h

0001h

0002h

0017h

0037h

0000h

0000h

Description

Sector Protect (1 byte)

00 = Not Supported, X = Number of sectors in per group

Temporary Sector Unprotect

00h = Not Supported, 01h = Supported

Sector Protect/Unprotect scheme (1 byte)

01 =29F040 mode, 02 = 29F016 mode

03 = 29F400 mode, 04 = 29LV800 mode

05 = 29BDS640 mode (Software Command Locking)

06 = BDD160 mode (New Sector Protect)

07 = 29LV800 + PDL128 (New Sector Protect) mode

Simultaneous Read/Write (1 byte)

00h = Not Supported, X = Number of sectors in all banks except Bank 1

Burst Mode Type

00h = Not Supported, 01h = Supported

Page Mode Type

00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)

ACC (Acceleration) Supply Maximum

00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)

Top/Bottom Boot Sector Flag (1 byte)

00h = Uniform device, no WP# control,

01h = 8 x 8 Kb sectors at top and bottom with WP# control

02h = Bottom boot device

03h = Top boot device

04h = Uniform, Bottom WP# Protect

05h = Uniform, Top WP# Protect

If the number of erase block regions = 1, then ignore this field

Program Suspend

00 = Not Supported

01 = Supported

Write Buffer Size

2

(N+1)

word(s)

Bank Organization (1 byte)

00 = If data at 4Ah is zero

XX = Number of banks

Bank 1 Region Information (1 byte)

XX = Number of Sectors in Bank 1

Bank 2 Region Information (1 byte)

XX = Number of Sectors in Bank 2

Bank 3 Region Information (1 byte)

XX = Number of Sectors in Bank 3

Bank 4 Region Information (1 byte)

XX = Number of Sectors in Bank 4

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document Number: 002-00948 Rev. *A Page 70 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

20. Appendix 2

20.1

Command Definitions

Memory Array Command Definitions (x32 Mode)

(

Command (Notes)

Read ( 5 )

Reset ( 6

)

Autoselect

7 )

Manufacturer ID

Device ID (

8 )

Program

Chip Erase

Sector Erase

Program/Erase Suspend (

9 )

Program/Erase Resume ( 10

)

CFI Query ( 11 , 12 )

Accelerated Program ( 13

)

Configuration Register Verify ( 12

)

Configuration Register Write ( 14

)

Unlock Bypass Entry (

15

)

Unlock Bypass Program ( 15 )

Unlock Bypass Erase ( 15

)

Unlock Bypass CFI (

11 , 15

)

Unlock Bypass Reset ( 15

)

1

1

4

6

4

6

6

1

1

1

2

3

4

3

2

2

1

2

XX

XX

XX

XX

XX

555

555

555

First Second

Addr Data Addr Data

RA

XXX

RD

F0

555

555

555

555

AA

AA

AA

AA

2AA

2AA

2AA

2AA

2AA 555

BA

BA

55

AA

B0

30

98

55

55

55

55

55

A0

AA

AA

AA

A0

80

98

90

PA

2AA

2AA

2AA

PA

XX

XX

PD

55

55

55

PD

10

00

BA+555

555

555

Legend

BA = Bank Address. The set of addresses that comprise a bank. The system may write any address within a bank to identify that bank for a command.

PA = Program Address (Amax–A0). Addresses latch on the falling edge of the

WE# or CE# pulse, whichever happens later.

PD = Program Data (DQmax–DQ0) written to location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.

Bus Cycles (Notes 1

4 )

Third

Addr Data

Fourth

Addr Data

555

555

555

555

555

90

90

A0

80

80

C6

D0

20

BA+X00

BA+X01

PA

555

555

BA+XX

XX

01

7E

PD

AA

AA

RD

WD

RA = Read Address (Amax–A0).

Addr

2AA

2AA

Fifth

BA+X0E

Data

09

55

55

Addr

BA+X0F

555

SA

RD = Read Data. Data DQmax–DQ0 at address location RA.

Sixth

Data

00/01

10

30

SA = Sector Address. The set of addresses that comprise a sector. The system may write any address within a sector to identify that sector for a command.

WD = Write Data. See “Configuration Register” definition for specific write data.

Data latched on rising edge of WE#.

X = Don’t care

Notes

1. See

Table

for description of bus operations.

2. All values are in hexadecimal.

8. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates ordering option 00, 01h indicates ordering option 01.

3. Shaded cells in table denote read cycles. All other cycles are write operations.

9. The system may read and program in non-erasing sectors when in the

Program/Erase Suspend mode. The Program/Erase Suspend command is valid only during a sector erase operation, and requires the bank address.

4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.

10. The Program/Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

5. No unlock or command cycles required when bank is reading array data.

11. Command is valid when device is ready to read array data.

12. Asynchronous read operations.

6. The Reset command is required to return to the read mode (or to the erasesuspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information).

13. ACC must be at V

ID

14. Command is ignored during any Embedded Program, Embedded Erase, or

Suspend operation.

during the entire operation of this command.

7. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID or

device ID information. See Autoselect on page 25

for more information.

15. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return to the read mode.

Document Number: 002-00948 Rev. *A Page 71 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Sector Protection Command Definitions (x32 Mode)

Command (Notes)

Reset

Secured Silicon Sector Entry

Secured Silicon Sector Exit

Secured Silicon Protection

Bit Program ( 5

,

6 )

Secured Silicon Protection Bit

Status

Password Program ( 5 , 7 , 8

)

Password Verify

Password Unlock (

7 , 8

)

PPB Program ( 5 , 6 )

All PPB Erase (

5 , 9 , 10 )

PPB Status (

11 , 12

)

PPB Lock Bit Set

PPB Lock Bit Status

DYB Write (

DYB Erase (

7

DYB Status (

7

)

)

12

)

PPMLB Program (

PPMLB Status (

5

)

SPMLB Program (

SPMLB Status (

5

)

5

5

,

,

6

6

)

)

1

3

4

6

6

3

4

6

4

5

6

4

4

4

4

4

6

6

6

6

XXX

555

555

555

555

555

555

555

555

555

555

555

555

555

555

555

555

555

555

555

First

Addr Data Addr Data

F0

AA

AA

AA

AA

AA

AA

AA

AA

AA

AA

AA

AA

AA

AA

AA

AA

AA

AA

Second

2AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

AA 2AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

2AA

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

Addr

555

555

555

555

555

555

555

555

555

BA+555

555

BA+555

555

555

BA+555

555

555

555

555

Third

Bus Cycles (Notes

1 – 4

)

Data

88

90

60

60

38

C8

28

60

60

90

78

58

48

48

58

60

60

60

60

Addr

XX

OW

OW

SG+WP

WP

SA

PL

PL

SL

SL

SA

SA

SA

Fourth

PWA[0-1]

PWA[0-1]

PWA[0-1]

SA+X02

Data

00

68

RD(0)

PWD[0-1]

PWD[0-1]

PWD[0-1]

68

60

00/01

RD(1)

X1

X0

RD(0)

68

RD(0)

68

RD(0)

Addr

OW

SG+WP

WP

PL

SL

Fifth

Data

48

48

40

48

48

OW

WP

PL

SL

Sixth

Addr

SG+WP

Data

RD(0)

RD(0)

RD(0)

RD(0)

RD(0)

Legend

DYB = Dynamic Protection Bit

OW = Address (A5–A0) is (011X10).

PPB = Persistent Protection Bit

PWA = Password Address. A0 selects between the low and high 32-bit portions of the 64-bit Password

PWD = Password Data. Must be written over two cycles.

PL = Password Protection Mode Lock Address (A5–A0) is (001X10)

RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1, if unprotected, DQ0 = 0.

RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0.

SA = Sector Address. The set of addresses that comprise a sector. The system may write any address within a sector to identify that sector for a command.

SG = Sector Group Address

BA = Bank Address. The set of addresses that comprise a bank. The system may write any address within a bank to identify that bank for a command.

SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)

WP = PPB Address (A5–A0) is (111010)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

Notes

1. See

Table

for description of bus operations.

2. All values are in hexadecimal.

6. The fourth cycle programs the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully programmed. If

DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again.

8. The entire four bus-cycle sequence must be entered for each portion of the password.

3. Shaded cells in table denote read cycles. All other cycles are write operations.

9. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again.

4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares.

10. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs.

5. The reset command returns the device to reading the array.

11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set.

12. The status of additional PPBs and DYBs may be read (following the fourth cycle) without reissuing the entire command sequence.

7. Data is latched on the rising edge of WE#.

Document Number: 002-00948 Rev. *A Page 72 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

21. Revision History

Spansion Publication Number: S29CD-J_CL-J_00

Section

Revision A0 (March 1, 2005)

Initial release.

Description

Revision A1 (April 15, 2005)

Ordering Information and Valid

Combinations tables

Revision A2 (January 20, 2006)

Updated to include lead Pb-free options.

Ordering Information

Input/Output Descriptions

Additional Resources

Memory Address Map

Simultaneous Read/Write Operation

Advanced Sector Protection/

Unprotection

Electronic Marking

Added “Contact factory” for 75 MHz. Modified Ordering Options for Characters 15 and 16 to reflect autoselect ID and top/bottom boot. Changed “N” for Extended Temperature Range to “M”.

Removed Logic Symbol Diagrams.

Added section.

Changed “Bank 2” to “Bank 1”.

Removed Ordering Options Table (Tables 3 and 4).

Added Advanced Sector Protection/Unprotection figure. Added figures for PPB Erase and Program

Algorithm.

Added in Electronic Marking section.

Absolute Maximum Ratings

Modified V

CC

Ratings to reflect 2.6 V and 3.6 V devices. Modified V

CC

Ratings to reflect 16 Mb and

32 Mb devices.

AC Characteristics

Asynchronous Read Operation

Added Note “t

OE

during Read Array”.

Changed values of t

AVAV

, t

AVQV

, t

ELQV

, t

GLQV

in table.

Conventional Read Operation Timings Moved t

DF

line to 90% on the high-Z output in figure.

Added t

AAVS

and t

AAVH

timing parameters to table. Changed t

Removed the following timing parameters:

CH

to t

CLKH

. Changed t

CL

to t

CLKL

.

Burst Mode Read for 32 Mb and 16 Mb

• t

DS

(Data Setup to WE# Rising Edge)

• t

DH

(Data Hold from WE# Rising Edge)

• t

AS

(Address Setup to Falling Edge of WE#)

• t

AH

(Address Hold from Falling Edge of WE#)

• t

CS

(CE# Setup Time)

• t

CH

(CE# Hold Time)

• t

ACS

(Address Setup Time to CLK)

• t

ACH

(Address Hold Time from ADV# Rising Edge of CLK while ADV# is Low)

Added the following timing parameters:

Burst Mode Read (x32 Mode)

• t

AAVS

• t

DVCH

• t

INDS

• t

INDH

Asynchronous Command Write Timing In figure, changed t

OEH

to t

WEH

; changed t

WPH

to t

OEP

.

Synchronous Command Write/Read

Timing

Removed t

WADVH

and t

WCKS

from figure.

WP# Timing

Erase/Program Operations

In figure, changed t

CH

to t

BUSY

In table, added Note 3: Program/Erase parameters are the same regardless of synchronous or asynchronous mode. Added t

OEP

(OE# High Pulse)

Alternative CE# Controlled Erase/

Program Operations

Removed t

OES

from table. Added t

WADVS

and t

WCKS

Appendix 2: Command Definitions

Revision B0 (June 12, 2006)

Removed “or when device is in autoselect mode” from Note 14.

Document Number: 002-00948 Rev. *A Page 73 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Section

Global

Distinctive Characteristics

Performance Characteristics

Ordering Information

Input/Output Descriptions and Logic

Symbols

Physical Dimensions/Connection

Diagrams

Additional Resources

Hardware Reset (RESET#)

Autoselect

Erase Suspend / Erase Resume

Commands

Program Suspend / Program Resume

Commands

Description

Changed document status to Preliminary.

Changed cycling endurance from typical to guaranteed.

Updated Max Asynch. Access Time, Max CE# Access Time, and Max OE# Access time in table.

Updated additional ordering options in designator breakout table. Updated valid combination tables.

Changed RY/BY# description.

Changed note on connection diagrams.

Updated contact information.

Added section.

Updated third and fourth paragraphs in section. Updated Autoselect Codes table.

Modified second paragraph. Replaced allowable operations table with bulleted list.

Replaced allowable operations table with bulleted list.

Reset Command

Secured Silicon Sector Flash Memory

Region

Absolute Maximum Ratings

Operating Ranges

Added section.

Modified Secured Silicon Sector Addresses table.

Modified V

CC

and V

IO

ratings. Modified Note 1.

Modified specification titles and descriptions (no specification value changes).

DC Characteristics, CMOS Compatible table

Burst Mode Read for 32 Mb and 16 Mb table

Modified I

CCB

specification. Deleted Note 5. Added Note 3 references to table.

Modified t

ADVCS specifications.

, t

CLKH

, t

CLKL

, t

AAVS

specifications. Added t

RSTZ

, t

Added Notes 2 and 3, and note references to table.

WADVH1

, and t

WADVH2

Synchronous Command Write/Read

Timing figure

Added t

WADVH1

and t

WADVH2

to figure. Deleted t

ACS

and t

ACH

from figure.

Hardware Reset (RESET#) Added table to section.

Erase/Program Operations table Added note references. Deleted t

OEP specification.

Erase and Programming Performance Changed Double Word Program Time specification.

Common Flash Memory Interface (CFI)

CFI System Interface String table: Changed description and data for addresses 1Bh and 1Ch.

Device Geometry Definition table: Changed description and data for address 27h.

Revision B1 (September 27, 2006)

Global

Distinctive Characteristics

Performance Characteristics

Data sheet format reorganized.

Changed cycling endurance specification to typical.

Changed t

BACC

specifications for 66 MHz, 56 MHz, 40 MHz speed options.

Added quantities to packing type descriptions, restructured table for easier reference.

Ordering Information

S29CD-J and S29CL-J Flash Family

Autoselect Codes (High Voltage

Method)

DQ6 and DQ2 Indications

Section 8.9, Reset Command

In table, modified description of read cycle 3 DQ7–DQ0.

In table, corrected third column heading

Added table.

Section 13.1, Absolute Maximum

Ratings

Deleted OE# from section.

Table 18.3, Burst Mode Read for 32 Mb and 16 Mb

Burst Mode Read (x32 Mode)

In table, changed t specifications for t

ADVCS

, t

AAVH

.

BDH

specifications. Modified description for t

IACC

. Deleted minimum

In figure, modified period for t

IACC

in drawing.

Revision B2 (March 7, 2007)

Distinctive Characteristics Corrected number of 16K sectors in 16 Mb devices. Modified read access times table.

Document Number: 002-00948 Rev. *A Page 74 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Section

Ordering Information

Description

Changed boot sector option part number designators. Changed valid combinations. Modified 10th character option descriptions.

Deleted WORD# input.

Block Diagram

2-, 4-, 8- Double Word Linear Burst

Operation

Sector Erase

Advanced Sector Protection/

Unprotection

DC Characteristics

Test Specifications

Asynchronous Operations

Synchronous Operations

Erase/Program Operations

Latchup Characteristics

Common Flash Memory Interface (CFI)

In 32- Bit Linear and Burst Data Order table, deleted reference to WORD# input.

Modified second paragraph; added reference to application note.

Modified Advanced Sector Protection/Unprotection figure and notes. In some subsections, changed

“sector” to “sector group”.

Changed I

CCB

test conditions and I

CC1

maximum specification.

Changed C

L

.

Asynchronous Command Write Timing figure: Added note.

Asynchronous Read Operations table: Changed t

RC

, t

ACC

, t

CE

for 75 MHz device.

Burst Mode Read for 32 Mb and 16 Mb table: Changed t

INDS

, t

CLKL

, t

AAVH

, and t

WADVH1 specifications.

Burst Mode Read figure: Modified period lengths for several specifications.

Added t

WEH

and t

OEP

specifications to table.

Deleted section.

CFI System Interface String table: Modified description of address 1Bh.

CFI Primary Vendor-Specific Extended Query table: Modified data at address 45h.

Revision B3 (March 30, 2009)

Global

Distinctive Characteristics

Removed “Preliminary”

Changed all instances of V

CCQ

to V

IO

Removed “or without” (wrap around) from Programmable Burst Interface bullet

Performance Characteristics

Ordering Information

Input/Output Descriptions and Logic

Symbols

Block Diagram

Added notice to refer to programming best practices application note for 32 Mb devices.

Added S29CL032J to valid OPN diagram.

Corrected valid combinations table.

Subscript CC for V

CC

, IO for V

IO

, SS for V

SS

in table.

Changed type for V

IO

to “Supply”

Changed type for V

SS

to “Supply”

Removed DQmax-DQ0 label from inputs to Burst Address Counter and Address Latch.

Removed Amax-A0 label from I/O Buffers.

Table: S29CD016J/CL016J (Top Boot)

Sector and Memory Address Map

Changed Note 2 to refer to Bank 0 and 1 instead of Bank 1 and 2.

Table: 32-Bit Linear and Burst Data

Order

Removed “x16”

Removed “A0:A-1” from Output Data Sequence column for Four Linear Data Transfers.

Removed “A1:A-1” from Output Data Sequence column for Eight Linear Data Transfers.

Added notice to refer to programming best practices application note for 32 Mb devices.

Programming

Table: DC Characteristic, CMOS

Compatible

Changed Max I

CCB

for S29CL-J to 90 mA.

Table: Burst Mode for 32 Mb and 16 Mb

Corrected values for t

BDH

with separate values for 16Mb and 32Mb.

Added t

WADVS

parameter to table.

Figure: Synchronous Command Write/

Read Timing

Added timing definition for t

WADVS

.

Table: Erase/Program Operations

Figure: Program Operation Timings

Appended “from WE# Rising Edge” to t

AH

description.

Changed t

AH

Min to 11.75 ns.

Updated timing diagram to reflect new t

AH

value.

Document Number: 002-00948 Rev. *A Page 75 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Section

Figure: Chip/Sector Erase Operation

Timings

Table: Alternate CE# Controlled Erase/

Program Operations

Product Overview

Table: Device Bus Operation

Accelerated Program and Erase

Operations

Unlock Bypass

Simultaneous Read/Write

VCC and VIO Power-up And Powerdown Sequencing

Standby Mode

Figure: Test Setup

Table: Alternate CE# Controlled Erase/

Program Operations

Table: Memory Array Command

Definitions (x32 Mode)

Revision B4 (October 30, 2009)

Updated timing diagram to reflect new t

AH

value.

Removed t

WADVS

parameter.

Removed “or without”.

Description

Changed “X” to “H” under CLK column for CE# row.

Removed all mention of accelerated erase.

Removed mention of unlock bypass sector erase.

Added in warning to indicate restrictions on Simultaneous Read/Write conditions.

Added reference to timing section.

Changed Vcc ± 0.2V to Vcc ± 10%.

Removed Note “Diodes are IN3064 or equivalent”.

Corrected values for t

DH

with separate values for 16 Mb and 32 Mb.

Cleaned up Notes.

Absolute Maximum Ratings

DC Characteristics

Synchronous Operation

Hardware Reset (RESET#)

Corrected Address, Data, Control Signals identifiers to correctly distinguish different ratings between CL016L, CL032J, CD016J, and CD032J.

Added line item to distinguish V

IHCLK

value differences between CL-J and CD-J.

Corrected Figure “Burst Mode Read (x32 Mode)” to reflect max linear burst length of 8 double words instead of 32.

Corrected Table “Burst Initial Access Delay”: changed t

READY2

, t

RP

, and t

READY3 instead of Max.

set up to Min

Corrected Figure “RESET# Timings” to add t

READY2 embedded algorithm.

to timing diagram for bank not executing

Revision B5 (May 25, 2011)

Physical Dimensions/Connection

Diagrams

Revision B6 (March 15, 2012)

Global

Additional Resources

Revision History

Revision B7 (October 11, 2012)

On the 80-ball Fortified BGA Connection Diagram, corrected the K1 pin name from V

Added LAD080 Fortified BGA package option and drawing.

Updated relevant application note links.

Corrected heading for May 25, 2011 edits from revision B4 to B5.

CCQ

to V

IO

.

Valid Combinations

Asynchronous Operations

Erase/Program Operations

Updated Valid Combinations table to add clarity and make explicit which offerings require a customer to “contact factory for availability”.

In Figure 18.3, “Asynchronous Command Write Timing”, corrected the t

WC

measurement to be of the Stable Address period, not the Valid Data period.

In Table 18.5, “Erase/Program Operations”, corrected JEDEC symbol t

AVAV

to t

AVAX

.

In Table 18.5, merged redundant rows t

GHWL

and t

WEH

.

In Figures 18.8 “Program Operation Timings” and 18.9 “Chip/Sector Erase Operation Timings”, corrected t

AH

measurement to be from the falling edge of WE#.

Document Number: 002-00948 Rev. *A Page 76 of 86

Document History Page

Document Title:S29CD032J, S29CD016J, S29CL032J, S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash

Document Number: 002-00948

Rev.

ECN No.

Orig. of

Change

Submission

Date

Description of Change

**

** -

RYSU

RYSU

03/01/2005 A0:Initial release

04/15/2005

A1:Ordering Information and Valid Combinations tables

Updated to include lead Pb-free options.

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document Number: 002-00948 Rev. *A Page 77 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document History Page (Continued)

Document Title:S29CD032J, S29CD016J, S29CL032J, S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash

Document Number: 002-00948

Rev.

**

ECN No.

-

Orig. of

Change

RYSU

Submission

Date

01/20/2006

Description of Change

Ordering Information

Added “Contact factory” for 75 MHz. Modified Ordering Options for

Characters 15 and 16 to reflect autoselect ID and top/bottom boot. Changed “N” for Extended Temperature

Range to “M”.

Input/Output Descriptions Removed Logic Symbol Diagrams.

Additional Resources Added section.

Memory Address Map Changed “Bank 2” to “Bank 1”.

Simultaneous Read/Write Operation Removed Ordering Options Table

(Tables 3 and 4).

Advanced Sector Protection/Unprotection

Added Advanced Sector Protection/Unprotection figure. Added figures for

PPB Erase and Program

Algorithm.

Electronic Marking Added in Electronic Marking section.

Absolute Maximum Ratings

Modified VCC Ratings to reflect 2.6 V and 3.6 V devices. Modified VCC

Ratings to reflect 16 Mb and

32 Mb devices.

AC Characteristics Added Note “tOE during Read Array”.

Asynchronous Read Operation Changed values of tAVAV, tAVQV, tELQV, tGLQV in table.

Conventional Read Operation Timings Moved tDF line to 90% on the high-Z output in figure.

Burst Mode Read for 32 Mb and 16 Mb

Added tAAVS and tAAVH timing parameters to table. Changed tCH to tCLKH. Changed tCL to tCLKL.

Removed the following timing parameters:

• tDS (Data Setup to WE# Rising Edge)

• tDH (Data Hold from WE# Rising Edge)

• tAS (Address Setup to Falling Edge of WE#)

• tAH (Address Hold from Falling Edge of WE#)

• tCS (CE# Setup Time)

• tCH (CE# Hold Time)

• tACS (Address Setup Time to CLK)

• tACH (Address Hold Time from ADV# Rising Edge of CLK while ADV# is

Low)

Burst Mode Read (x32 Mode)

Added the following timing parameters:

• tAAVS

• tDVCH

• tINDS

• tINDH

Document Number: 002-00948 Rev. *A Page 78 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document History Page (Continued)

Document Title:S29CD032J, S29CD016J, S29CL032J, S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash

Document Number: 002-00948

Rev.

**

ECN No.

-

Orig. of

Change

RYSU

Submission

Date

01/20/2006

Description of Change

Asynchronous Command Write Timing In figure, changed tOEH to tWEH; changed tWPH to tOEP.

Synchronous Command Write/Read Timing

Removed tWADVH and tWCKS from figure.

WP# Timing In figure, changed tCH to tBUSY

Erase/Program Operations

In table, added Note 3: Program/Erase parameters are the same regardless of synchronous or asynchronous mode. Added tOEP (OE# High Pulse)

Alternative CE# Controlled Erase/Program Operations

Removed tOES from table. Added tWADVS and tWCKS

Appendix 2: Command Definitions Removed “or when device is in autoselect mode” from Note 14.

Document Number: 002-00948 Rev. *A Page 79 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document History Page (Continued)

Document Title:S29CD032J, S29CD016J, S29CL032J, S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash

Document Number: 002-00948

Rev.

**

ECN No.

-

Orig. of

Change

RYSU

Submission

Date

06/12/2006

Description of Change

Global Changed document status to Preliminary.

Distinctive Characteristics Changed cycling endurance from typical to guaranteed.

Performance Characteristics Updated Max Asynch. Access Time, Max

CE# Access Time, and Max OE# Access time in table.

Ordering Information Updated additional ordering options in designator breakout table. Updated valid combination tables.

Input/Output Descriptions and Logic Symbols

Changed RY/BY# description.

Physical Dimensions/Connection Diagrams

Changed note on connection diagrams.

Additional Resources Updated contact information.

Hardware Reset (RESET#) Added section.

Autoselect Updated third and fourth paragraphs in section. Updated

Autoselect Codes table.

Erase Suspend / Erase Resume Commands

Modified second paragraph. Replaced allowable operations table with bulleted list.

Program Suspend / Program Resume Commands

Replaced allowable operations table with bulleted list.

Reset Command Added section.

Secured Silicon Sector Flash Memory Region

Modified Secured Silicon Sector Addresses table.

Absolute Maximum Ratings Modified VCC and VIO ratings. Modified

Note 1.

Operating Ranges Modified specification titles and descriptions (no specification value changes).

DC Characteristics, CMOS Compatible table

Modified ICCB specification. Deleted Note 5. Added Note 3 references to table.

Burst Mode Read for 32 Mb and 16 Mb table

Modified tADVCS, tCLKH, tCLKL, tAAVS specifications. Added tRSTZ, tWADVH1, and tWADVH2 specifications. Added Notes 2 and 3, and note references to table.

Synchronous Command Write/Read Timing figure

Added tWADVH1 and tWADVH2 to figure. Deleted tACS and tACH from figure.

Hardware Reset (RESET#) Added table to section.

Erase/Program Operations table Added note references. Deleted tOEP specification.

Erase and Programming Performance Changed Double Word Program

Time specification.

Document Number: 002-00948 Rev. *A Page 80 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document History Page (Continued)

Document Title:S29CD032J, S29CD016J, S29CL032J, S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash

Document Number: 002-00948

Rev.

**

ECN No.

-

Orig. of

Change

RYSU

Submission

Date

06/12/2006

Description of Change

Common Flash Memory Interface (CFI)

CFI System Interface String table: Changed description and data for addresses 1Bh and 1Ch.

Device Geometry Definition table: Changed description and data for address

27h.

** RYSU 09/27/2006

Global Data sheet format reorganized.

Distinctive Characteristics Changed cycling endurance specification to typical.

Performance Characteristics Changed tBACC specifications for 66 MHz,

56 MHz, 40 MHz speed options.

Ordering Information Added quantities to packing type descriptions, restructured table for easier reference.

S29CD-J and S29CL-J Flash Family Autoselect Codes (High Voltage

Method)

In table, modified description of read cycle 3 DQ7–DQ0.

DQ6 and DQ2 Indications In table, corrected third column heading

Section 8.9, Reset Command Added table.

Section 13.1, Absolute Maximum Ratings

Deleted OE# from section.

Table 18.3, Burst Mode Read for 32 Mb and 16 Mb

In table, changed tADVCS, tBDH specifications. Modified description for tIACC. Deleted minimum specifications for tAAVH.

Burst Mode Read (x32 Mode) In figure, modified period for tIACC in drawing.

Document Number: 002-00948 Rev. *A Page 81 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document History Page (Continued)

Document Title:S29CD032J, S29CD016J, S29CL032J, S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash

Document Number: 002-00948

Rev.

**

ECN No.

-

Orig. of

Change

RYSU

Submission

Date

03/07/2007

Description of Change

Distinctive Characteristics Corrected number of 16K sectors in 16 Mb devices. Modified read access times table.

Ordering Information

Changed boot sector option part number designators. Changed valid combinations. Modified 10th character option descriptions.

Block Diagram Deleted WORD# input.

2-, 4-, 8- Double Word Linear Burst Operation

In 32- Bit Linear and Burst Data Order table, deleted reference to WORD# input.

Sector Erase Modified second paragraph; added reference to application note.

Advanced Sector Protection/ Unprotection

Modified Advanced Sector Protection/Unprotection figure and notes. In some subsections, changed

“sector” to “sector group”.

DC Characteristics Changed ICCB test conditions and ICC1 maximum specification.

Test Specifications Changed CL.

Asynchronous Operations

Asynchronous Command Write Timing figure: Added note.

Asynchronous Read Operations table: Changed tRC, tACC, tCE for 75

MHz device.

Synchronous Operations

Burst Mode Read for 32 Mb and 16 Mb table: Changed tINDS, tCLKL, tAAVH, and tWADVH1 specifications.

Burst Mode Read figure: Modified period lengths for several specifications.

Erase/Program Operations Added tWEH and tOEP specifications to table.

Latchup Characteristics Deleted section.

Common Flash Memory Interface (CFI)

CFI System Interface String table: Modified description of address 1Bh.

CFI Primary Vendor-Specific Extended Query table: Modified data at address 45h.

Document Number: 002-00948 Rev. *A Page 82 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document History Page (Continued)

Document Title:S29CD032J, S29CD016J, S29CL032J, S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash

Document Number: 002-00948

Rev.

**

ECN No.

-

Orig. of

Change

RYSU

Submission

Date

03/30/2009

Description of Change

Global

Removed “Preliminary”

Changed all instances of VCCQ to VIO

Distinctive Characteristics Removed “or without” (wrap around) from

Programmable Burst Interface bullet

Performance Characteristics Added notice to refer to programming best practices application note for 32 Mb devices.

Ordering Information

Added S29CL032J to valid OPN diagram.

Corrected valid combinations table.

Input/Output Descriptions and Logic Symbols

Subscript CC for VCC, IO for VIO, SS for VSS in table.

Changed type for VIO to “Supply”

Changed type for VSS to “Supply”

Block Diagram

Removed DQmax-DQ0 label from inputs to Burst Address Counter and

Address Latch.

Removed Amax-A0 label from I/O Buffers.

Table: S29CD016J/CL016J (Top Boot) Sector and Memory Address

Map

Changed Note 2 to refer to Bank 0 and 1 instead of Bank 1 and 2.

Table: 32-Bit Linear and Burst Data Order

Removed “x16”

Removed “A0:A-1” from Output Data Sequence column for Four Linear

Data Transfers.

Removed “A1:A-1” from Output Data Sequence column for Eight Linear Data

Transfers.

Programming Added notice to refer to programming best practices application note for 32 Mb devices.

Table: DC Characteristic, CMOS Compatible

Changed Max ICCB for S29CL-J to 90 mA.

Table: Burst Mode for 32 Mb and 16 Mb

Corrected values for tBDH with separate values for 16Mb and 32Mb.

Added tWADVS parameter to table.

Figure: Synchronous Command Write/ Read Timing

Added timing definition for tWADVS.

Table: Erase/Program Operations

Appended “from WE# Rising Edge” to tAH description.

Changed tAH Min to 11.75 ns.

Figure: Program Operation Timings Updated timing diagram to reflect new tAH value.

Figure: Chip/Sector Erase Operation Timings

Updated timing diagram to reflect new tAH value.

Document Number: 002-00948 Rev. *A Page 83 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document History Page (Continued)

Document Title:S29CD032J, S29CD016J, S29CL032J, S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash

Document Number: 002-00948

Rev.

**

ECN No.

-

Orig. of

Change

RYSU

Submission

Date

03/30/2009

Description of Change

Table: Alternate CE# Controlled Erase/Program Operations

Removed tWADVS parameter.

Product Overview Removed “or without”.

Table: Device Bus Operation Changed “X” to “H” under CLK column for

CE# row.

Accelerated Program and Erase Operations

Removed all mention of accelerated erase.

Unlock Bypass Removed mention of unlock bypass sector erase.

Simultaneous Read/Write Added in warning to indicate restrictions on Simultaneous Read/Write conditions.

VCC and VIO Power-up And Powerdown Sequencing

Added reference to timing section.

Standby Mode Changed Vcc ± 0.2V to Vcc ± 10%.

Figure: Test Setup Removed Note “Diodes are IN3064 or equivalent”.

Table: Alternate CE# Controlled Erase/Program Operations

Corrected values for tDH with separate values for 16 Mb and 32 Mb.

Table: Memory Array Command Definitions (x32 Mode)

Cleaned up Notes.

** RYSU 10/30/2009

Absolute Maximum Ratings

Corrected Address, Data, Control Signals identifiers to correctly distinguish different ratings between CL016L, CL032J, CD016J, and CD032J.

DC Characteristics Added line item to distinguish VIHCLK value differences between CL-J and CD-J.

Synchronous Operation

Corrected Figure “Burst Mode Read (x32 Mode)” to reflect max linear burst length of 8 double words instead of 32.

Hardware Reset (RESET#)

Corrected Table “Burst Initial Access Delay”: changed tREADY2, tRP, and tREADY3 set up to Min instead of Max.

Corrected Figure “RESET# Timings” to add tREADY2 to timing diagram for bank not executing embedded algorithm.

** RYSU 05/25/2011

Physical Dimensions/Connection Diagrams

On the 80-ball Fortified BGA Connection Diagram, corrected the K1 pin name from VCCQ to VIO.

** RYSU 03/15/2012

Global Added LAD080 Fortified BGA package option and drawing.

Additional Resources Updated relevant application note links.

Revision History Corrected heading for May 25, 2011 edits from revision

B4 to B5.

Document Number: 002-00948 Rev. *A Page 84 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Document History Page (Continued)

Document Title:S29CD032J, S29CD016J, S29CL032J, S29CL016J

32/16 Mbit, 2.6/3.3 V, Dual Boot, Simultaneous Read/Write, Burst Flash

Document Number: 002-00948

Rev.

**

ECN No.

-

Orig. of

Change

RYSU

Submission

Date

10/11/2012

Description of Change

Valid Combinations

Updated Valid Combinations table to add clarity and make explicit which offerings require a customer to “contact factory for availability”.

Asynchronous Operations

In Figure 18.3, “Asynchronous Command Write Timing”, corrected the tWC measurement to be of the Stable Address period, not the Valid Data period.

Erase/Program Operations

In Table 18.5, “Erase/Program Operations”, corrected JEDEC symbol tAVAV to tAVAX.

In Table 18.5, merged redundant rows tGHWL and tWEH.

In Figures 18.8 “Program Operation Timings” and 18.9 “Chip/Sector Erase

Operation Timings”, corrected tAH measurement to be from the falling edge of WE#.

*A 5048814 RYSU 12/16/2015 Updated to Cypress template

Document Number: 002-00948 Rev. *A Page 85 of 86

S29CD032J

S29CD016J

S29CL032J

S29CL016J

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations .

Products

Automotive..................................cypress.com/go/automotive

Clocks & Buffers ................................

cypress.com/go/clocks

Interface......................................... cypress.com/go/interface

Lighting & Power Control ............ cypress.com/go/powerpsoc

Memory........................................... cypress.com/go/memory

PSoC ....................................................cypress.com/go/psoc

Touch Sensing .................................... cypress.com/go/touch

USB Controllers ....................................cypress.com/go/USB

Wireless/RF .................................... cypress.com/go/wireless

PSoC

®

Solutions

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community

Community | Forums | Blogs | Video | Training

Technical Support

cypress.com/go/support

© Cypress Semiconductor Corporation, 2005-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 002-00948 Rev. *A Revised December 16, 2015 Page 86 of 86

Cypress

®

, Spansion

®

, MirrorBit

®

, MirrorBit

®

Eclipse™, ORNAND™, EcoRAM™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress

Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement

Table of contents