WL18xxMOD WiLink™ 8 Single-Band Combo Module – Wi-Fi Bluetooth ®

WL18xxMOD WiLink™ 8 Single-Band Combo Module – Wi-Fi Bluetooth ®

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WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

WL18xxMOD WiLink™ 8 Single-Band Combo Module –

Wi-Fi

®

, Bluetooth

®

, and Bluetooth Low Energy (BLE)

1 Device Overview

1

1.1

Features

General

– Integrates RF, Power Amplifiers (PAs), Clock,

RF Switches, Filters, Passives, and Power

Management

– Quick Hardware Design With TI Module

Collateral and Reference Designs

– Operating Temperature: –20°C to 70°C

– Small Form Factor: 13.3 × 13.4 × 2 mm

– 100-Pin MOC Package

– FCC, IC, ETSI/CE, and TELEC Certified With

Chip Antennas

Wi-Fi

– WLAN Baseband Processor and RF Transceiver

Support of IEEE Std 802.11a, 802.11b, 802.11g, and 802.11n

– 20- and 40-MHz SISO and 20-MHz 2 x 2 MIMO at 2.4 GHz for High Throughput: 80 Mbps

(TCP), 100 Mbps (UDP)

– 2.4-GHz MRC Support for Extended Range

– Fully Calibrated: Production Calibration Not

Required

– 4-Bit SDIO Host Interface Support

– Wi-Fi Direct Concurrent Operation

(Multichannel, Multirole)

Bluetooth and BLE (WL183xMOD Only)

Bluetooth 4.1 and CSA2 Support

– Host Controller Interface (HCI) Transport for

Bluetooth Over UART

– Dedicated Audio Processor Support of SBC

Encoding + A2DP

– Dual-Mode Bluetooth and BLE

– Bluetopia + LE Certified Stack Provided by TI

Key Benefits

– Reduces Design Overhead

– Differentiated Use-Cases by Configuring WiLink

8 Simultaneously in Two Roles (STA and AP) to

Connect Directly With Other Wi-Fi Devices on

Different RF Channel (Wi-Fi Networks)

– Best-in-Class Wi-Fi With High-Performance

Audio and Video Streaming Reference

Applications With Up to 1.4X the Range Versus a Single Antenna

– Different Provisioning Methods for In-Home

Devices Connectivity to Wi-Fi in One Step

– Lowest Wi-Fi Power Consumption in Connected

Idle (< 800 µA)

– Configurable Wake on WLAN Filters to Only

Wake Up the System

– Wi-Fi-Bluetooth Single Antenna Coexistence

1.2

Applications

• Internet of Things

• Multimedia

• Home Electronics

• Home Appliances and White Goods

• Industrial and Home Automation

• Smart Gateway and Metering

• Video Conferencing

• Video Camera and Security

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

www.ti.com

1.3

Description

The certified WiLink 8 module from TI offers high throughput and extended range along with Wi-Fi and

Bluetooth coexistence (WL1835MOD only) in a power-optimized design. The WL18x5MOD device is a

2.4-GHz module, two antenna solution. The device is FCC, IC, ETSI/CE, and TELEC certified for AP and client. TI offers drivers for high-level operating systems such as Linux

®

, Android™, WinCE, and RTOS.

WL1801MOD

WL1805MOD

ORDER NUMBER

WL1831MOD

WL1835MOD space

1.4

Functional Block Diagram

Device Information

PACKAGE

MOC (100)

MOC (100)

MOC (100)

MOC (100)

Figure 1-1

shows a functional block diagram of the WL1835 variant.

BODY SIZE

13.3 mm × 13.4 mm × 2 mm

13.3 mm × 13.4 mm × 2 mm

13.3 mm × 13.4 mm × 2 mm

13.3 mm × 13.4 mm × 2 mm

32kHz

RFTST

OSC

BT

:

UART

WLAN: SDIO

WRF2

WRF1 bg1

F

VIO

BT

F

bg2

26M XTAL

VBAT

COEX I/F

Figure 1-1. WL1835 Functional Block Diagram

space

2

Device Overview

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WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

Table of Contents

1 Device Overview

.........................................

1

1.1

Features

..............................................

1

1.2

Applications

...........................................

1

1.3

Description

............................................

2

1.4

Functional Block Diagram

............................

2

2 Revision History

.........................................

3

3 Device Comparison

.....................................

4

4 Terminal Configuration and Functions

..............

5

4.1

Pin Description

5 Specifications

.......................................

7

..........................................

10

5.1

Absolute Maximum Ratings

.........................

10

5.2

Handling Ratings

....................................

10

5.3

Power-On Hours (POH)

.............................

10

5.4

Recommended Operating Conditions

...............

10

5.5

External Digital Slow Clock Requirements

..........

11

5.6

Thermal Characteristics

.............................

11

5.7

WLAN Performance

.................................

12

5.8

Bluetooth Performance

..............................

14

5.9

Bluetooth LE Performance

..........................

16

5.10

Bluetooth-BLE Dynamic Currents

...................

17

5.11

Bluetooth LE Currents

..............................

18

5.12

Timing and Switching Characteristics

...............

18

6 Detailed Description

6.1

WLAN

...................................

26

...............................................

27

6.2

Bluetooth

6.3

BLE

............................................

27

..................................................

28

6.4

WiLink 8 Module Markings

..........................

28

6.5

Test Grades

.........................................

29

7 Applications and Implementation

...................

30

7.1

Application Information

..............................

30

8 Device and Documentation Support

...............

35

8.1

Device Support

......................................

35

8.2

Related Links

........................................

35

8.3

Community Resources

..............................

35

8.4

Trademarks

..........................................

35

8.5

Electrostatic Discharge Caution

.....................

36

8.6

Glossary

.............................................

36

9 Mechanical Packaging and Orderable

Information

..............................................

37

9.1

TI Module Mechanical Outline

......................

37

9.2

Packaging Information

..............................

38

2 Revision History

Changes from Revision I (August 2014) to Revision J Page

• Changed

Section 1.1

, Features

.....................................................................................................

1

• Changed

Section 1.2

, Applications

.................................................................................................

1

• Changed organization of

Section 9

, Mechanical Packaging and Orderable Information

.................................

37

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Revision History

3

WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

www.ti.com

3 Device Comparison

The TI WiLink 8 module offers four footprint-compatible 2.4-GHz variants providing stand-alone and

Bluetooth combo connectivity.

Table 3-1

compares the features of the module variants.

Table 3-1. TI WiLink 8 Module Variants

DEVICE

WL1835MOD

WL1831MOD

WL1805MOD

WL1801MOD

WLAN 2.4-GHZ SISO

(1)

WLAN 2.4-GHZ MIMO

(1)

WLAN 2.4-GHZ MRC

(1) SISO: single input, single output; MIMO: multiple input, multiple output; MRC: maximum ratio combining.

(1)

BLUETOOTH

4

Device Comparison

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WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

4 Terminal Configuration and Functions

Figure 4-1

shows the pin assignments for the 100-pin MOC package.

2G4_ANT1_WB

GND

GND

GND

GND

GPIO1

GPIO2

GPIO4

GND

GND

RESERVED2

RESERVED1

GND

GND

2G4_ANT2_W

PIN 17 - GND

GND GND

GND

GND GND

GND

GND GND GND

GND GND GND

GND

GND

GND

GND

GND

GND

GND GND GND

GND

GND

GND

GND GND

GND

GND GND GND

GND GND GND

GND

GND GND

PIN 49 - GND

BT_HCI_RTS

BT_HCI_CTS

BT_HCI_TX

BT_HCI_RX

GND

GND

BT_AUD_IN

BT_AUD_OUT

BT_AUD_FSYNC

GND

BT_AUD_CLK

GND

RESERVED3

GND

RESERVED

Figure 4-1. 100-Pin MOC Package (Bottom View)

Copyright © 2013–2014, Texas Instruments Incorporated

Terminal Configuration and Functions

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5

WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

Figure 4-2

shows the outline of the 100-pin MOC package.

www.ti.com

NOTE: 1. Module size: 13.4 x 13.3 mm

NOTE: 2. Pad size: 0.75 x 0.40 mm

NOTE: 3. Pitch: 0.7 mm

Figure 4-2. Outline of 100-Pin MOC Package

Figure 4-3

shows the outline of the recommended PCB pattern for the 100-pin MOC package.

Figure 4-3. Outline of Recommended PCB Pattern for 100-Pin MOC Package

6

Terminal Configuration and Functions

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SWRS152J – JULY 2013 – REVISED OCTOBER 2014

4.1

Pin Description

Table 4-1

describes the module pins.

PIN NAME PIN

Table 4-1. Pin Description

TYPE/ SHUTDOWN AFTER VOLTAG

DIR STATE POWER

UP

(1)

E LEVEL

CONNECTIVITY

(2)

1801 1805 1831 1835

Clocks and Reset SIgnals

WL_SDIO_CLK_1V8 8 I Hi-Z Hi-Z 1.8 V v v v v

EXT_32K

WLAN_EN

BT_EN

36

40

41

ANA

I

I PD

PD

PD

PD

1.8 V

1.8 V v v x v v x v v v v v v

DESCRIPTION

WLAN SDIO clock.

Must be driven by the host.

Input sleep clock:

32.768 kHz

Mode setting: high = enable

Mode setting: high = enable

Power-Management Signals

VIO_IN 38 POW PD PD 1.8 V v v v v

VBAT_IN

VBAT_IN

46

47

POW

POW

VBAT

VBAT v v v v v v v v

Connect to 1.8-V external VIO

Power supply input,

2.9 to 4.8 V

Power supply input,

2.9 to 4.8 V

TI Reserved

GPIO11 2 I/O PD PD 1.8 V v v v v

GPIO9

GPIO10

GPIO12

RESERVED1

RESERVED2

GPIO4

RESERVED3

RESERVED

3

4

5

21

22

25

62

64

I/O

I/O

I/O

I

I

I/O

O

GND

PD

PU

PU

PD

PD

PD

PD

PD

PU

PU

PD

PD

PD

PD

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

– v v v x x v x v v v v x x v x v v v v x x v x v v v v x x v x v

Reserved for future use. NC if not used.

Reserved for future use. NC if not used.

Reserved for future use. NC if not used.

Reserved for future use. NC if not used.

Reserved for future use. NC if not used.

Reserved for future use. NC if not used.

Reserved for future use. NC if not used.

Reserved for future use. NC if not used.

Reserved for future use. NC if not used.

WLAN Functional Block: Int Signals

WL_SDIO_CMD_1V8 6 I/O Hi-Z Hi-Z 1.8 V v v v v

WL_SDIO_D0_1V8

WL_SDIO_D1_1V8

WL_SDIO_D2_1V8

10

11

12

I/O

I/O

IO

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

1.8 V

1.8 V

1.8 V v v v v v v v v v v v v

WLAN SDIO command in

(3)

WLAN SDIO data bit

0

(3)

WLAN SDIO data bit

1

(3)

WLAN SDIO data bit

2

(3)

(1) PU = pullup; PD = pulldown.

(2) v = connect; x = no connect.

(3) Host must provide PU using a 10-K resistor for all non-CLK SDIO signals.

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Terminal Configuration and Functions

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PIN NAME

WL_SDIO_D3_1V8

WL_IRQ_1V8

GPIO2

2G4_ANT2_W

GPIO1

PIN

13

14

26

18

27

Table 4-1. Pin Description (continued)

TYPE/ SHUTDOWN AFTER VOLTAG

DIR STATE POWER

UP

(1)

E LEVEL

CONNECTIVITY

(2)

1801 1805 1831 1835

I/O Hi-Z PU 1.8 V v v v v

O

I/O

ANA

I/O

2G4_ANT1_WB

WL_UART_DBG

32

42

ANA

O

Bluetooth Functional Block: Int Signals

BT_UART_DBG 43 O

PD

PD

PD

PU

PU

0

PD

PD

PU

PU

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V v v v v x v x v v v v v v x v v v v x v v v v v v v v v

DESCRIPTION

WLAN SDIO data bit

3. Changes state to

PU at WL_EN or

BT_EN assertion for card detects. Later disabled by software during initialization.

(1)

SDIO available, interrupt out. Active high. (For

WL_RS232_TX/RX pullup is at power up.) Set to rising edge (active high) on power up. The Wi-Fi interrupt line can be configured by the driver according to the IRQ configuration

(polarity/level/edge).

WL_RS232_RX

(when WLAN_IRQ =

1 at power up)

2.4G ant2 TX, RX

WL_RS232_TX

(when WLAN_IRQ =

1 at power up)

2.4G ant1 TX, RX

Option: WLAN logger

BT_HCI_RTS_1V8

BT_HCI_CTS_1V8

BT_HCI_TX_1V8

BT_HCI_RX_1V8

BT_AUD_IN

BT_AUD_OUT

BT_AUD_FSYNC

BT_AUD_CLK

50

51

52

53

56

57

58

60

O

I

O

I

I

O

I/O

I/O

PU

PU

PU

PU

PD

PD

PD

PD

PU

PU

PU

PU

PD

PD

PD

PD

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V

1.8 V x x x x x x x x x x x x x x x x v v v v v v v v v v v v v v v v

Option: Bluetooth logger

UART RTS to host.

NC if not used.

UART CTS from host. NC if not used.

UART TX to host. NC if not used.

UART RX from host.

NC if not used.

Bluetooth PCM/I2S bus. Data in. NC if not used.

Bluetooth PCM/I2S bus. Data out. NC if not used.

Bluetooth PCM/I2S bus. Frame sync. NC if not used.

Bluetooth PCM/I2S bus. NC if not used.

8

Terminal Configuration and Functions

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PIN NAME

Ground Pins

GND

WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

PIN

Table 4-1. Pin Description (continued)

TYPE/ SHUTDOWN AFTER VOLTAG

DIR STATE POWER

UP

(1)

E LEVEL

CONNECTIVITY

(2)

1801 1805 1831 1835

1, 7, 9,

15, 16,

17, 19,

20, 23,

24, 28,

29, 30,

31, 33,

34, 35,

37, 39,

44, 45,

48, 49,

54, 55,

59, 61,

63, G1-

G36

GND – v v v v

DESCRIPTION

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5 Specifications

5.1

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

VBAT

VIO

Input voltage to analog pins

PARAMETER

Input voltage limits (CLK_IN)

Input voltage to all other pins

Operating ambient temperature range

VALUE

4.8

(2)

–0.5 to 2.1

–0.5 to 2.1

–0.5 to VDD_IO

–0.5 to (VDD_IO + 0.5 V)

–20 to +70

(3)

UNIT

V

V

V

V

V

°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) 4.8 V cumulative to 2.33 years, including charging dips and peaks

(3) Operating free-air temperature range at which the device can operate reliably for 15K cumulative active TX power-on hours (assuming a maximum junction temperature of (T j

) of 125°C).

Section 5.3

, Power-On Hours (POH), describes the correlation between T the WL18xx system, a control mechanism automatically ensures T j

< 125°C. Whenever T j j and PoH. In approaches the threshold, this mechanism controls the transmitter patterns.

5.2

Handling Ratings

T stg

ESD stress voltage

(1)

Storage temperature range

Human body model (HBM)

(2)

Charged device model (CDM)

(3)

MIN

–40

–1000

–250

MAX

+85

+1000

+250

UNIT

°C

V

(1) ESD measures device sensitivity and immunity to damage caused by electrostatic discharges into the device.

(2) The level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible, if necessary precautions are taken. Pins listed as 1000 V can actually have higher performance.

(3) The level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible, if necessary precautions are taken. Pins listed as 250 V can actually have higher performance.

5.3

Power-On Hours (POH)

OPERATING JUNCTION TEMPERATURE (°C)

125

120

115

110

105

POH

15,000

20,000

27,000

37,000

50,000

5.4

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

VBAT

(1)

V

IH

V

IL

VIH_EN

DC supply range for all modes

1.8-V I/O ring power supply voltage

I/O high-level input voltage

I/O low-level input voltage

Enable inputs high-level input voltage

MIN

2.9

1.62

0.65 x

VDD_IO

0

1.365

NOM MAX UNIT

4.8

1.95

V

V

VDD_IO

0.35 ×

VDD_IO

VDD_IO

V

V

V

(1) 4.8 V is applicable only for 2.3 years (30% of the time). Otherwise, maximum VBAT must not exceed 4.3 V.

10

Specifications

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SWRS152J – JULY 2013 – REVISED OCTOBER 2014

Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

VIL_EN Enable inputs low-level input voltage

High-level output voltage V

OH

@ 4 mA

V

T r

T

T f

OL r

,T f

Maximum power dissipation

Low-level output voltage

Input transitions time T r

10% to 90% (digital I/O)

,T f

(2) from

Output rise time from 10% to

90% (digital pins)

(2)

Output fall time from 10% to

90% (digital pins)

(2)

Ambient operating temperature

WLAN operation

Bluetooth operation

@ 4 mA

C

C

L

L

< 25 pF

< 25 pF

(2) Applies to all digital lines except SDIO, UART, I2C, PCM and slow clock lines

MIN

0

VDD_IO

–0.45

0

1

–20

NOM MAX UNIT

0.4

V

VDD_IO

0.45

10

5.3

4.9

70

2.8

0.2

V

V ns ns ns

ºC

W

5.5

External Digital Slow Clock Requirements

The supported digital slow clock is 32.768 kHz digital (square wave). All core functions share a single input.

PARAMETER CONDITION

Input slow clock frequency

Input slow clock accuracy (Initial + WLAN, Bluetooth temp + aging)

Input transition time T r

,T f

90%)

(10% to

Frequency input duty cycle

Input voltage limits Square wave, DCcoupled

Input impedance

Input capacitance

SYMBOL

T r

,T f

Vih

Vil

MIN

15

0.65 x VDD_IO

0

1

TYP

32768

50

MAX

±250

200

85

VDD_IO

0.35 x VDD_IO

5

UNIT

Hz ppm ns

%

V peak

M Ω pF

5.6

Thermal Characteristics

AIR FLOW

DESCRIPTION NAME

θ

JC

θ

JB

θ

JA

φ

JB

Junction to case

Junction to board

Junction to free air

(2)

Junction to board

(1) °C/W = degrees Celsius per watt

(2) According to the JEDEC EIA/JESD 51 document

FCBGA (°C/W)

(1)

12.7

13.6

20.5

8.7

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Specifications

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WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

5.7

WLAN Performance

All RF and performance numbers are aligned to the module pin.

5.7.1

WLAN 2.4-GHz Receiver Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER CONDITION MIN

2400 Operation frequency range

Sensitivity: 20-MHz bandwidth. At < 10%

PER limit

Max Input Level At < 10% PER limit

Adjacent channel rejection: Sensitivity level

+3 dB for OFDM; Sensitivity level +6 dB for

11b

2400 to 2480

1 Mbps DSSS

2 Mbps DSSS

5.5 Mbps CCK

11 Mbps CCK

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

MCS0 MM 4K

MCS1 MM 4K

MCS2 MM 4K

MCS3 MM 4K

MCS4 MM 4K

MCS5 MM 4K

MCS6 MM 4K

MCS7 MM 4K

MCS0 MM 4K 40 MHz

MCS7 MM 4K 40 MHz

MCS0 MM 4K MRC

MCS7 MM 4K MRC

MCS13 MM 4K

MCS14 MM 4K

MCS15 MM 4K

OFDM (11g/n)

DSSS

2 Mbps DSSS

11 Mbps CCK

54 Mbps OFDM

–19

–4

42.7

37.9

2.0

TYP

–80.7

–76.5

–74.9

–90.4

–87.6

–85.9

–82.8

–79.4

–75.2

–73.5

–96.3

–93.2

–90.6

–87.9

–92.0

–90.4

–89.5

–87.2

–84.1

–72.4

–86.7

–67.0

–92.7

–75.2

–73.7

–72.3

–71.0

–9

–0

www.ti.com

MAX

2480

UNIT

MHz dBm dBm dBm dB dB dB

12

Specifications

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5.7.2

WLAN 2.4-GHz Transmitter Power

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Output Power:

Maximum RMS output power measured at 1 dB from IEEE spectral mask or EVM

(1)

Operation frequency range

Return loss

Reference input impedance

CONDITION

1 Mbps DSSS

2 Mbps DSSS

5.5 Mbps CCK

11 Mbps CCK

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

MCS0 MM

MCS1 MM

MCS2 MM

MCS3 MM

MCS4 MM

MCS5 MM

MCS6 MM

MCS7 MM

(2)

MCS0 MM 40 MHz

MCS7 MM 40 MHz

MCS12 (WL18x5)

MCS13 (WL18x5)

MCS14 (WL18x5)

MCS15 (WL18x5)

MIN TYP

–10.0

50.0

MAX

RF_IO2_BG_WL pin 2.4-GHz SISO

17.3

17.3

17.3

17.3

17.1

17.1

17.1

17.1

16.1

16.1

16.1

15.3

14.6

16.2

15.3

14.6

13.8

16.1

13.8

12.6

14.8

11.3

2G4_ANT2_W + 2G4_ANT1_WB 2.4-GHz MIMO

18.5

17.4

14.5

13.4

2G4_ANT2_W + 2G4_ANT1_WB Pins

2412 2484

(1) Regulatory constraints limit TI module output power to the following:

• Channels 1, 11, 13 @ OFDM legacy and HT 20-MHz rates: 14 dBm

• Channels 1, 11, 13 @ HT 40-MHz lower primary rates: 12 dBm

• Channel 7 @ HT 40-MHz lower primary rates: 12 dBm

• Channel 5 @ HT 40-MHz upper primary rates: 12 dBm

(2) To ensure compliance with the EVM conditions specified in the PHY chapter of IEEE Std 802.11™ – 2012:

• MCS7 20 MHz channel 12 output power is 2 dB lower than the typical value.

• MCS7 20 MHz channel 8 output power is 1 dB lower than the typical value.

UNIT

dBm dBm

MHz dB

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5.7.3

WLAN Currents

Receiver

SPECIFICATION ITEMS

Low-power mode (LPM) 2.4-GHz RX SISO20 single chain

Transmitter

2.4 GHz RX search SISO20

2.4-GHz RX search MIMO20

2.4-GHz RX search SISO40

2.4-GHz RX 20 M SISO 11 CCK

2.4-GHz RX 20 M SISO 6 OFDM

2.4-GHz RX 20 M SISO MCS7

2.4-GHz RX 20 M MRC 1 DSSS

2.4-GHz RX 20 M MRC 6 OFDM

2.4-GHz RX 20 M MRC 54 OFDM

2.4-GHz RX 40 MHz MCS7

2.4-GHz TX 20 M SISO 6 OFDM 15.4 dBm

2.4-GHz TX 20 M SISO 11 CCK 15.4 dBm

2.4-GHz TX 20 M SISO 54 OFDM 12.7 dBm

2.4-GHz TX 20 M SISO MCS7 11.2 dBm

2.4-GHz TX 20 M MIMO MCS15 11.2 dBm

2.4-GHz TX 40 M SISO MCS7 8.2 dBm space

5.8

Bluetooth Performance

All RF and performance numbers are aligned to the module pin.

5.8.1

Bluetooth BR, EDR Receiver Characteristics—In-Band Signals

over operating free-air temperature range (unless otherwise noted)

PARAMETER CONDITION MIN

2402 Bluetooth BR, EDR operation frequency range

Bluetooth BR, EDR channel spacing

Bluetooth BR, EDR input impedance

Bluetooth BR, EDR sensitivity

(1) dirty TX on

BR, BER = 0.1%

EDR2, BER = 0.01%

EDR3, BER = 0.01%

Bluetooth EDR BER floor at EDR2 sensitivity + 10 dB

Dirty TX off (for 1,600,000 bits)

EDR3

Bluetooth BR, EDR maximum BR, BER = 0.1% usable input power

EDR2, BER = 0.1%

EDR3, BER = 0.1%

Bluetooth BR intermodulation Level of interferers for n = 3, 4, and 5

1e-6

1e-6

–5.0

–15.0

–15.0

–36.0

TYP

1

50

–92.2

–91.7

–84.7

–30.0

TYP (AVG) – 25°C

49

54

74

59

56

61

65

74

81

85

77

285

273

247

238

420

243

MAX

2480 mA mA mA mA mA mA mA

UNITS

mA mA mA mA mA mA mA mA mA mA

UNIT

MHz

MHz

Ω dBm dBm dBm dBm dBm dBm dBm

(1) Sensitivity degradation up to –3 dB may occur due to fast clock harmonics with dirty TX on.

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PARAMETER

Bluetooth BR, EDR C/I performance

Numbers show wanted signal-to-interfering-signal ratio. Smaller numbers indicate better C/I performances (Image frequency = –1 MHz)

BR, co-channel

EDR, co-channel

CONDITION

BR, adjacent ±1 MHz

EDR, adjacent ±1 MHz,

(image)

BR, adjacent +2 MHz

EDR, adjacent +2 MHz

WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

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EDR2

EDR3

EDR2

EDR3

MIN TYP

EDR2

EDR3

BR, adjacent –2 MHz

EDR, adjacent –2 MHz EDR2

EDR3

BR, adjacent ≥Ι±3Ι MHz

EDR, adjacent ≥Ι±3Ι MHz EDR2

EDR3

Bluetooth BR, EDR RF return loss

–10.0

5.8.2

Bluetooth Transmitter, BR

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN

BR RF output power

(1)

BR gain control range

BR power control step

BR adjacent channel power |M-N| = 2

BR adjacent channel power |M-N| > 2

VBAT ≥ 3 V

VBAT < 3 V

TYP

12.7

7.2

30.0

5.0

–43.0

–48.0

(1) Values reflect maximum power. Reduced power is available using a vendor-specific (VS) command.

5.8.3

Bluetooth Transmitter, EDR

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN

EDR output power

(1)

VBAT ≥ 3 V

VBAT < 3 V

EDR relative power

EDR gain control range

EDR power control step

EDR adjacent channel power |M-N| = 1

EDR adjacent channel power |M-N| = 2

EDR adjacent channel power |M-N| > 2

TYP

7.2

5.2

30

5

–36

–30

–42

(1) Values reflect default maximum power. Max power can be changed using a VS command.

MAX

10

12

20

–3.0

–3.0

2.0

–33.0

–33.0

–28.0

–20.0

–20.0

–13.0

–42.0

–42.0

–36.0

MAX

MAX UNIT

dBm dB dB dB dBc dBm dBm

UNIT

dBm dBm dB dB dBm dBm dB dB dB dB dB

UNIT

dB dB dB dB dB dB dB dB dB dB dB

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5.8.4

Bluetooth Modulation, BR

over operating free-air temperature range (unless otherwise noted)

CHARACTERISTICS CONDITION

(1)

BR –20 dB bandwidth

BR modulation characteristics

BR carrier frequency drift

BR drift rate

BR initial carrier frequency tolerance

(2)

∆f1avg Mod data = 4 1s, 4

0s:

111100001111...

∆f2max ≥ limit for Mod data = at least 99.9% of all Δf2max

1010101...

∆f2avg, ∆f1avg

One slot packet

Three and five slot packet lfk+5 – fkl , k =

0 …. max f0–fTX

(1) Performance values reflect maximum power.

(2) Numbers include XTAL frequency drift over temperature and aging.

5.8.5

Bluetooth Modulation, EDR

over operating free-air temperature range (unless otherwise noted)

PARAMETER

(1)

CONDITION MIN

EDR carrier frequency stability

EDR initial carrier frequency tolerance

(2)

EDR RMS DEVM

–5

±75

EDR 99% DEVM

EDR peak DEVM

EDR2

EDR3

EDR2

EDR3

EDR2

EDR3

(1) Performance values reflect maximum power.

(2) Numbers include XTAL frequency drift over temperature and aging.

MIN

145

120

85

–25

–35

±75

5.9

Bluetooth LE Performance

All RF and performance numbers are aligned to the module pin.

5.9.1

Bluetooth LE Receiver Characteristics – In-Band Signals

over operating free-air temperature range (unless otherwise noted)

PARAMETER CONDITION

(1)

MIN

Bluetooth LE operation frequency range 2402

Bluetooth LE channel spacing

Bluetooth LE input impedance

Bluetooth LE sensitivity

(2)

Dirty TX on

Bluetooth LE maximum usable input power

Bluetooth LE intermodulation characteristics Level of interferers.

For n = 3, 4, 5

–5

–36

TYP

4

4

9

9

TYP

2

50

–92.2

–30

TYP

925

160

130

88

10

30

20

25

18

MAX

5

±75

15

MAX

2480

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25

35

15

±75

MAX

995

170

UNIT

kHz kHz kHz

% kHz kHz kHz/50 µs kHz

UNIT

MHz

MHz

Ω dBm dBm dBm

%

%

%

%

%

UNIT

kHz kHz

%

(1) BER of 0.1% corresponds to PER of 30.8% for a minimum of 1500 transmitted packets, according to the Bluetooth LE test specification.

(2) Sensitivity degradation of up to –3 dB can occur due to fast clock harmonics.

16

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PARAMETER

Bluetooth LE C/I performance.

Note: Numbers show wanted signal-tointerfering-signal ratio. Smaller numbers indicate better C/I performance.

Image = –1 MHz

CONDITION

(1)

LE, co-channel

LE, adjacent ±1 MHz

LE, adjacent +2 MHz

LE, adjacent –2 MHz

LE, adjacent ≥ |±3|MHz

MIN TYP MAX

12

0

–38

–15

–40

UNIT

dB

5.9.2

Bluetooth LE Transmitter Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Bluetooth LE RF output power

(1)

Bluetooth LE adjacent channel power |M-N| = 2

Bluetooth LE adjacent channel power |M-N| > 2

VBAT ≥ 3 V

VBAT < 3 V

MIN TYP

10.0

7.2

–51.0

–54.0

MAX UNIT

dBm dBm dBm dBm

(1) To reduce the maximum BLE power, use a VS command. The optional extra margin is offered to compensate for design losses, such as trace and filter losses, and to achieve the maximum allowed output power at system level.

5.9.3

Bluetooth LE Modulation Characteristics

over operating free-air temperature range (unless otherwise noted)

CHARACTERISTICS CONDITION

(1)

Bluetooth LE modulation characteristics

∆f1avg Mod data = 4 1s, 4 0s:

111100001111...

Mod data = 1010101...

∆f2max ≥ limit for at least 99.9% of all

Δf2max

∆f2avg, ∆f1avg

Bluetooth LE carrier frequency lf0 – fnl , n = 2,3 …. K drift

Bluetooth LE drift rate lf1 – f0l and lfn – fn-5l ,n = 6,7…. K

LE initial carrier frequency tolerance

(2) fn – fTX

(1) Performance values reflect maximum power.

(2) Numbers include XTAL frequency drift over temperature and aging.

MIN

240

195

85

–25

±75

TYP

250

215

90

MAX

260

25

15

±75

UNIT

kHz kHz

% kHz kHz/50 µs kHz

5.10 Bluetooth-BLE Dynamic Currents

Current is measured at output power as follows:

• BR at 12.7 dBm

• EDR at 7.2 dBm space

BR voice HV3 + sniff

USE CASE

EDR voice 2-EV3 no retransmission + sniff

Sniff 1 attempt 1.28 s

EDR A2DP EDR2 (master). SBC high quality – 345 Kbs

EDR A2DP EDR2 (master). MP3 high quality – 192 Kbs

Full throughput ACL RX: RX-2DH5

(3) (4)

Full throughput BR ACL TX: TX-DH5

(4)

Full throughput EDR ACL TX: TX-2DH5

(4)

(1) (2)

TYP

11.6

5.9

178.0

10.4

7.5

18.0

50.0

33.0

(1) The role of Bluetooth in all scenarios except A2DP is slave.

(2) CL1P5 PA is connected to VBAT, 3.7 V.

(3) ACL RX has the same current in all modulations.

(4) Full throughput assumes data transfer in one direction.

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UNIT

mA mA

µA mA mA mA mA mA

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USE CASE

(1) (2)

Page scan or inquiry scan (scan interval is 1.28 s or 11.25 ms, respectively)

Page scan and inquiry scan (scan interval is 1.28 s and 2.56 s, respectively)

TYP

253.0

332.0

5.11 Bluetooth LE Currents

All current measured at output power of 7.2 dBm

USE CASE

(1)

Advertising, not connectable

(2)

Advertising, discoverable

(2)

Scanning

(3)

Connected, master role, 1.28-s connect interval

(4)

Connected, slave role, 1.28-s connect interval

(4)

(1) CL1p% PA is connected to VBAT, 3.7 V.

(2) Advertising in all three channels, 1.28-s advertising interval, 15 bytes advertise data

(3) Listening to a single frequency per window, 1.28-s scan interval, 11.25-ms scan window

(4) Zero slave connection latency, empty TX and RX LL packets

TYP

131

143

266

124

132

UNIT

µA

µA

www.ti.com

UNIT

µA

µA

µA

µA

µA

5.12 Timing and Switching Characteristics

5.12.1 Power Management

5.12.1.1 Block Diagram – Internal DC2DCs

The device incorporates three internal DC2DCs (switched-mode power supplies) to provide efficient internal supplies, derived from V

BAT

.

WL18xx TOP LEVEL

VIO_IN

VIO

VBAT

VBAT

VBAT_IN_MAIN_DC2DC

VBAT_IN_PA_DC2DC

VBAT

MAIN_DC2DC_OUT

LDO_IN_DIG

SW

FB

Main DC2DC

1.8V

PA

DC2DC

SW

PA_DC2DC_OUT

FB

2.2–2.7 V

FB_IN_PA_DC2DC

DIG_DC2DC_OUT

VDD_DIG

SW

1V

FB

Digital DC2DC

Figure 5-1. Internal DC2DCs

5.12.2 Power-Up and Shut-Down States

The correct power-up and shut-down sequences must be followed to avoid damage to the device.

While V

BAT or V

IO or both are deasserted, no signals should be driven to the device. The only exception is the slow clock that is a fail-safe I/O.

While V

BAT

, V

IO

, and slow clock are fed to the device, but WL_EN is deasserted (low), the device is in

SHUTDOWN state. In SHUTDOWN state all functional blocks, internal DC2DCs, clocks, and LDOs are disabled.

To perform the correct power-up sequence, assert (high) WL_EN. The internal DC2DCs, LDOs, and clock start to ramp and stabilize. Stable slow clock, V signals.

IO

, and V

BAT are prerequisites to the assertion of one of the enable

18

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To perform the correct shut-down sequence, deassert (low) WL_EN while all the supplies to the device (V

BAT

,

V

IO

, and slow clock) are still stable and available. The supplies to the chip (V

BAT after both enable signals are deasserted (low).

and V

IO

) can be deasserted only

Figure 5-2

shows the general power scheme for the module, including the powerdown sequence.

VBAT

1

VIO

5 5

SCLK (32 KHz)

>10 µs 2 >10 µs 4

WL EN

3 t

•

60 µs t

NOTE: 1. Either VBAT or VIO can come up first.

NOTE: 2. VBAT and VIO supplies and slow clock (SCLK), must be stable prior to EN being asserted and at all times

NOTE: when the EN is active.

NOTE: 3. At least 60 µs is required between two successive device enables. The device is assumed to be in

NOTE: shutdown state during that period, meaning all enables to the device are LOW for that minimum duration.

NOTE: 4. EN must be deasserted at least 10 µs before VBAT or VIO supply can be lowered. (Order of supply turn off

NOTE: after EN shutdown is immaterial)

NOTE: 5. SCLK - Fail safe I/O

Figure 5-2. Power-Up System

5.12.3 Chip Top-level Power-Up Sequence

VBAT / VIO input

SLOWCLK input

WL_EN input

Main 1V8 DC2DC

DIG DC2DC

SRAM LDO

Top RESETZ

TCXO_CLK_REQ output

4.5msec delay

Internal power stable = 5mS

Figure 5-3. Chip Top-Level Power-Up Sequence

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5.12.4 WLAN Power-Up Sequence

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VBAT / VIO input

SLOWCLK input

WL_EN input

TCXO_CLK_REQ output

TXCO_LDO output

TCXO input

SDIO_CLK input

Indicates completion of FW download and Internal initialization

WLAN_IRQ output

NLCP

Wake-up time

Indicates completion of FW download and Internal initialization

WLAN_IRQ output

MCP

Wake-up time

Host configures device to reverse WLAN_IRQ polarity

Figure 5-4. WLAN Power-Up Sequence

5.12.5 Bluetooth-BLE Power-Up Sequence

Figure 5-5

shows the Bluetooth-BLE power-up sequence.

NLCP: trigger at rising edge

MCP: trigger at low level

20

Specifications

Figure 5-5. Bluetooth/BLE Power-Up Sequence

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5.12.6 WLAN SDIO Transport Layer

The SDIO is the host interface for WLAN. The interface between the host and the WL18xx module uses an SDIO interface and supports a maximum clock rate of 50 MHz.

The device SDIO also supports the following features of the SDIO V3 specification:

• 4-bit data bus

• Synchronous and asynchronous in-band interrupt

• Default and high-speed (HS, 50 MHz) timing

• Sleep and wake commands

5.12.6.1 SDIO Timing Specifications

Figure 5-6

and

Figure 5-7

show the SDIO switching characteristics over recommended operating conditions and with the default rate for input and output.

V

DD

Clock Input

V

SS

V

DD

Data Input

V

SS t

V

THL

IH

Not Valid

V

IL t t

WL

ISU

V

IH t

WH

V

IL

V

IH

Valid

V

IL

V

IH

V

IL t

TLH t

IH

V

IH

Not Valid

Figure 5-6. SDIO Default Input Timing

V

DD

Clock Input

V

SS t

THL

V

IH

V

IL t

WL

V

IL

V

IH t

WH

V

IH t

TLH

V

DD t

ODLY(max) t

ODLY(min)

Data Output

Not Valid

V

OH

V

OL

Valid

V

OH

V

OL

Not Valid

V

SS

Figure 5-7. SDIO Default Output Timing

Table 5-1

lists the SDIO default timing characteristics.

Table 5-1. SDIO Default Timing Characteristics

(1)

f clock

DC t

TLH t

THL t

ISU t

IH t

ODLY

C l

PARAMETER

Clock frequency, CLK

Low, high duty cycle

Rise time, CLK

Fall time, CLK

(2)

Setup time, input valid before CLK ↑

Hold time, input valid after CLK ↑

Delay time, CLK ↓ to output valid

Capacitive load on outputs

MIN

0.0

40.0

3.0

2.0

7.0

MAX

26.0

60.0

10.0

10.0

10.0

15.0

(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.

(2) Parameter values reflect maximum clock frequency.

ns ns ns ns pF

UNIT

MHz

% ns

Specifications

21

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5.12.6.2 SDIO Switching Characteristics – High Rate

Figure 5-8

and

Figure 5-9

show the parameters for maximum clock frequency.

V

DD

Clock Input

V

SS

V

DD

Data Input

V

SS t

V

THL

IH

Not Valid

V

IL t

WL t

V

IL

ISU t

WH

V

IH

50% V

DD t

TLH t

IH

V

IH

V

IL

Valid

V

IH

V

IL

V

IH

Not Valid

Figure 5-8. SDIO HS Input Timing

V

DD

Clock Input

50% V

DD t

THL

V

IH t

WL t

WH

V

IH

50% V

DD

V

IL

V

IL

V

SS t

TLH f clock

DC t

TLH t

THL t

ISU t

IH t

ODLY

C l

V

DD t

ODLY(max)

Data Output

Not Valid

V

OH

V

OL

Valid

V

OH

V

OL

V

SS

Figure 5-9. SDIO HS Output Timing

Table 5-2

lists the SDIO high-rate timing characteristics.

t

OH(min)

Not Valid

Table 5-2. SDIO HS Timing Characteristics

PARAMETER

Clock frequency, CLK

Low, high duty cycle

Rise time, CLK

Fall time, CLK

Setup time, input valid before CLK ↑

Hold time, input valid after CLK ↑

Delay time, CLK ↑ to output valid

Capacitive load on outputs

MIN

0.0

40.0

3.0

2.0

7.0

MAX

52.0

60.0

3.0

3.0

10.0

10.0

V

IH ns ns ns ns pF

UNIT

MHz

% ns

5.12.7 HCI UART Shared Transport Layers for All Functional Blocks (Except WLAN)

The device incorporates a UART module dedicated to the Bluetooth shared-transport, host controller interface

(HCI) transport layer. The HCI interface transports commands, events, and ACL between the Bluetooth device and its host using HCI data packets acting as a shared transport for all functional blocks except WLAN.

space

WLAN

WLAN HS SDIO

SHARED HCI FOR ALL FUNCTIONAL BLOCKS EXCEPT WLAN BLUETOOTH VOICE-AUDIO

Over UART Bluetooth PCM

22

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The HCI UART supports most baud rates (including all PC rates) for all fast-clock frequencies up to a maximum of 4 Mbps. After power up, the baud rate is set for 115.2 kbps, regardless of the fast-clock frequency. The baud rate can then be changed using a VS command. The device responds with a Command Complete Event (still at

115.2 kbps), after which the baud rate change occurs.

HCI hardware includes the following features:

• Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions

• Receiver-transmitter underflow detection

• CTS, RTS hardware flow control

• 4 wire (H4)

Table 5-3

lists the UART default settings.

Table 5-3. UART Default Setting

PARAMETER VALUE

Bit rate

Data length

Stop bit

Parity

115.2 kbps

8 bits

1

None

5.12.7.1 UART 4-Wire Interface – H4

The interface includes four signals:

• TXD

• RXD

• CTS

• RTS

Flow control between the host and the device is byte-wise by hardware.

When the UART RX buffer of the device passes the flow-control threshold, the buffer sets the UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high, the device stops transmitting on the interface. If HCI_CTS is set high in the middle of transmitting a byte, the device finishes transmitting the byte and stops the transmission.

Figure 5-10

shows the UART timing.

Figure 5-10. UART Timing Diagram

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Table 5-4

lists the UART timing characteristics.

PARAMETER

Baud rate

Baud rate accuracy per byte

Baud rate accuracy per bit

CTS low to TX_DATA on

CTS high to TX_DATA off

CTS high pulse width

RTS low to RX_DATA on

RTS high to RX_DATA off

Figure 5-11

shows the UART data frame.

Table 5-4. UART Timing Characteristics

CONDITION SYMBOL

Receive-transmit

Receive-transmit

MIN

37.5

–2.5

–12.5

0.0

Hardware flow control

Interrupt set to 1/4 FIFO t3 t4 t6 t1 t2

1.0

0.0

TX STR tb

D0 D1 D2 Dn PAR

TYP

2.0

2.0

MAX

4364

+1.5

+12.5

1.0

16.0

STP

STR-Start bit; D0..Dn - Data bits (LSB first); PAR - Parity bit (if used); STP - Stop bit

Figure 5-11. UART Data Frame

5.12.8 Bluetooth Codec-PCM (Audio) Timing Specifications

Figure 5-12

shows the Bluetooth codec-PCM (audio) timing diagram.

UNIT

Kbps

%

%

µs

Byte

Bit

µs

Bytes

Figure 5-12. Bluetooth Codec-PCM (Audio) Master Timing Diagram

24

Specifications

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Table 5-5

lists the Bluetooth codec-PCM master timing characteristics.

PARAMETER

Cycle time

High or low pulse width

AUD_IN setup time

AUD_IN hold time

AUD_OUT propagation time

FSYNC_OUT propagation time

Capacitive loading on outputs

Table 5-5. Bluetooth Codec-PCM Master Timing Characteristics

SYMBOL

T clk

T s t is t ih t op t op

C l

MIN

162.76 (6.144 MHz)

35% of T clk min

10.6

0

0

0

MAX

15625 (64 kHz)

15

15

40

Table 5-6

lists the Bluetooth codec-PCM slave timing characteristics.

PARAMETER

Cycle time

High or low pulse width

AUD_IN setup time

AUD_IN hold time

AUD_FSYNC setup time

AUD_FSYNC hold time

AUD_OUT propagation time

Capacitive loading on outputs

Table 5-6. Bluetooth Codec-PCM Slave Timing Characteristics

MAX SYMBOL

T clk

T w t is t ih t is t ih t op

C l

MIN

81.38 (12.266 MHz)

35% of T clk min

5

0

5

0

0 19

40

UNIT

ns pF

UNIT

ns pF

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6 Detailed Description

The WiLink 8 module is a self-contained connectivity solution based on WiLink 8 connectivity. As the eighth-generation connectivity combo chip from TI, the WiLink 8 module is based on proven technology.

Table 6-1

through

Table 6-3

list performance parameters along with shutdown and sleep currents.

Table 6-1. WLAN Performance Parameters

Maximum TX power

Minimum sensitivity

Sleep current

Connected IDLE

WLAN

(1)

RX search

RX current (SISO20)

TX current (SISO20)

(2)

Maximum peak current consumption during calibration

(3)

SPECIFICATION (TYP)

17.3 dBm

–96.3 dBm

160 µA

750 µA

54 mA

65 mA

238 mA

850 mA

CONDITIONS

1 Mbps DSSS

1 Mbps DSSS

Leakage, firmware retained

No traffic IDLE connect

Search (SISO20)

MCS7, 2.4 GHz

MCS7, 2.4 GHz, +11.2 dBm

(1) System design power scheme must comply with both peak and average TX bursts.

(2) WLAN maximum VBAT current draw of 725 mA with MIMO continues burst configuration.

(3) Peak current VBAT can hit 850 mA during device calibration.

• At wakeup, the WiLink 8 module performs the entire calibration sequence at the center of the 2.4-GHz band.

• Once a link is established, calibration is performed periodically (every 5 minutes) on the specific channel tuned.

• The maximum VBAT value is based on peak calibration consumption with a 30% margin.

BLUETOOTH

Maximum TX power

Minimum sensitivity

Sniff

Page or inquiry

A2DP

Table 6-2. Bluetooth Performance Parameters

SPECIFICATION (TYP)

12.7 dBm

–92.2 dBm

178 µA

253 µA

7.5 mA

CONDITIONS

GFSK

GFSK

1 attempt, 1.28 s (+4 dBm)

1.28-s interrupt, 11.25-ms scan window (+4 dBm)

MP3 high quality 192 kbps (+4 dBm)

PARAMETER

Shutdown mode

All functions shut down

WLAN sleep mode

Bluetooth sleep mode

Table 6-3. Shutdown and Sleep Currents

POWER SUPPLY CURRENT

VBAT

VIO

VBAT

VBAT

TYP

10

2

160

110

UNIT

µA

µA

µA

µA

26

Detailed Description

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Figure 6-1

shows a high-level view of the WL1835MOD variant.

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

Figure 6-1. WL1835MOD High-Level System Diagram

6.1

WLAN

The device supports the following WLAN features:

• Integrated 2.4-GHz power amplifiers (PAs) for a complete WLAN solution

• Baseband processor: IEEE Std 802.11b/g and IEEE Std 802.11n data rates with 20- or 40-MHz SISO and 20-MHz MIMO

• Fully calibrated system (production calibration not required)

• Medium access controller (MAC)

– Embedded ARM

® central processing unit (CPU)

– Hardware-based encryption-decryption using 64-, 128-, and 256-bit WEP, TKIP, or AES keys

– Requirements for Wi-Fi-protected access (WPA and WPA2.0) and IEEE Std 802.11i (includes hardware-accelerated Advanced Encryption Standard [AES])

• New advanced coexistence scheme with Bluetooth and BLE

• 2.4-GHz radio

– Internal LNA and PA

– IEEE Std 802.11b, 802.11g, and 802.11n

• 4-bit SDIO host interface, including high speed (HS) and V3 modes

6.2

Bluetooth

The device supports the following Bluetooth features:

Bluetooth 4.0 as well as CSA2

• Concurrent operation and built-in coexisting and prioritization handling of Bluetooth, BLE, audio processing, and WLAN

• Dedicated audio processor supporting on-chip SBC encoding + A2DP

– Assisted A2DP (A3DP): SBC encoding implemented internally

– Assisted WB-speech (AWBS): modified SBC codec implemented internally

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6.3

BLE

The device supports the following BLE features:

Bluetooth 4.0 BLE dual-mode standard

• All roles and role combinations, mandatory as well as optional

• Up to 10 BLE connections

• Independent LE buffering allowing many multiple connections with no affect on BR-EDR performance

6.4

WiLink 8 Module Markings

Figure 6-2

shows the markings for the TI WiLink 8 module.

Model: WL18 MODGB

Test Grade:&&

FCC ID: Z64

-

WL18SBMOD

IC: 451I

-

WL18SBMOD

LTC: YYWW SSF

R 201-135370

Figure 6-2. WiLink 8 Module Markings

Table 6-4

describes the WiLink 8 module markings.

MARKING

WL18 MODGB

&&

Z64-WL18SBMOD

451I-WL18SBMOD

YYWWSSF

201-135370

Table 6-4. Description of WiLink 8 Module Markings

DESCRIPTION

Model

Test grade (for more information, see

Section 6.5

, Test Grades)

FCC ID: single modular FCC grant ID

IC: single modular IC grant ID

LTC (lot trace code):

• YY = year (for example, 12 = 2012)

• WW = week

• SS = serial number (01 to 99) matching manufacturer lot number

• F = Reserved for internal use

R: single modular TELEC grant ID

CE

TELEC compliance mark

CE compliance mark

28

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6.5

Test Grades

To minimize delivery time, TI may ship the device ordered or an equivalent device currently available that contains at least the functions of the part ordered. From all aspects, this device will behave exactly the same as the part ordered. For example, if a customer orders device WL1801MOD, the part shipped can be marked with a test grade of 37, 07 (see

Table 6-5

).

MARK 1

0&

3&

MARK 2

&1

&5

Table 6-5. Test Grade Markings

WLAN

Tested

Tested

WLAN 2.4 GHz

Tested

Tested

BLUETOOTH

Tested

MIMO 2.4 GHz

Tested

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7 Applications and Implementation

7.1

Application Information

7.1.1

Typical Application – WL1835MOD Reference Design

Figure 7-1

shows the TI WL1835MOD reference design.

BT_EN

WLAN_EN

WLAN/BT Enable Control.

Connect to Host GPIO.

Reserved for DBG

TP1 TP2

VBAT_IN

VIO_IN

EXT_32K

www.ti.com

BT_HCI_RTS_1V8

BT_HCI_CTS_1V8

BT_HCI_TX_1V8

BT_HCI_RX_1V8

Connect to Host HCI Interface.

BT_AUD_IN

BT_AUD_OUT

BT_AUD_FSYNC

BT_AUD_CLK

Connect to Host BT PCM Bus.

TP8

G25

G26

G27

G28

G29

G30

G19

G20

G21

G22

G23

G24

G31

G32

G33

G34

G35

G36

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

49

GND

50

BT_HCI_RTS

51

BT_HCI_CTS

52

BT_HCI_TX

53

BT_HCI_RX

54

55

GND

56

BT_AUD_IN

57

BT_AUD_OUT

58

BT_AUD_FSYNC

59

GND

60

BT_AUD_CLK

61

GND

62

GND

RESERVED3

63

GND

64

GND

U1

(X)WL1835MOD

E-13.4X13.3-N100_0.75-TOP

32

2G4_ANT1_WB

31

GND

GND

GND

28

GND

27

GPIO_1

GND

26

GPIO_2

GPIO_4

25

24

GND

23

22

RESERVED2

29

21

RESERVED1

30

20

GND

19

GND

18

2G4_ANT2_W

17

GND

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

G17

G18

G1

G2

G3

G4

G5

G6

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

TP6

TP7

C4

10pF

CAP1005

WL_RS232_TX_1V8 TP3

WL_RS232_RX_1V8

TP5

TP4

For Debug only

C8

10pF

CAP1005

L1

1.1nH

IND1005

L2

1.1nH

IND1005

C15

8pF

CAP1005

ANT1

ANT016008LCD2442MA1

ANT-N3-1.6X0.8MM

A

FEED

2.4G

5G

C6

2pF

CAP1005

C7

NU_2.4pF

CAP1005

The value of antenna matching components is for TMDXWL1835COM8T

C17

8pF

CAP1005

ANT2

ANT016008LCD2442MA1

ANT-N3-1.6X0.8MM

A

FEED

2.4G

5G

C10

2pF

CAP1005

C11

NU_3pF

CAP1005

The value of antenna matching components is for TMDXWL1835COM8T

TP10 TP11 TP12 TP13

VIO_IN

R13

NU

RES1005

For Debug only

WL_IRQ_1V8

WL_SDIO_D3_1V8

WL_SDIO_D2_1V8

WL_SDIO_D1_1V8

WL_SDIO_D0_1V8

WL_SDIO_CLK_1V8

WL_SDIO_CMD_1V8

Connect to Host SDIO Interface.

Figure 7-1. TI Module Reference Schematics

Table 7-1

lists the bill materials (BOM).

DESCRIPTION

TI WL 1835 WiFi/BT Module

ANT/Chip/2.4, 5 GHz/Peak Gain >

5 dBi

IND 0402/1.2 nH/±0.3/0.12

Ω/300 mA

CAP 0402/2.0 pF/50 V/C0G/±0.25 pF

CAP 0402/8.2 pF/50 V/NPO/±0.5 pF

CAP 0402/10 pF/50 V/NPO/±5%

RES 0402/10K/±5% (debug only)

Table 7-1. Bill of Materials

PART NUMBER

(X)WL1835MOD

ANT016008LCD2442MA1

PACKAGE

13.4 x 13.3 x 2.0mm

1.6 mm x 0.8 mm

Hl1005-1C1N2SMT

C1005C0G1H020C

0402N8R2D500

0402N100J500LT

WR04X103 JTL

0402

0402

0402

0402

0402

REFERENCE QTY MFR

U1 1 TI

ANT1, ANT2 2 TDK

L1, L2

C8, C10

C15, C17

C4, C6

R13

2

2

1

2

2

ACX

Walsin

Walsin

Walsin

Walsin

30

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7.1.2

Design Recommendations

This section describes the layout recommendations for the (X)WL1835 module, RF trace, and antenna.

Table 7-2

summarizes the layout recommendations.

Table 7-2. Layout Recommendations Summary

ITEM

3

4

5

6

1

2

DESCRIPTION

Thermal

The proximity of ground vias must be close to the pad.

Signal traces must not be run underneath the module on the layer where the module is mounted.

Have a complete ground pour in layer 2 for thermal dissipation.

Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.

Increase the ground pour in the first layer and have all of the traces from the first layer on the inner layers, if possible.

Signal traces can be run on a third layer under the solid ground layer, which is below the module mounting layer.

7

8

RF Trace and Antenna Routing

The RF trace antenna feed must be as short as possible beyond the ground reference. At this point, the trace starts to radiate.

The RF trace bends must be gradual with an approximate maximum bend of 45 degrees with trace mitered. RF traces must not have sharp corners.

9 RF traces must have via stitching on the ground plane beside the RF trace on both sides.

10 RF traces must have constant impedance (microstrip transmission line).

11 For best results, the RF trace ground layer must be the ground layer immediately below the RF trace. The ground layer must be solid.

12 There must be no traces or ground under the antenna section.

13 RF traces must be as short as possible. The antenna, RF traces, and modules must be on the edge of the PCB product. The proximity of the antenna to the enclosure and the enclosure material must also be considered.

Supply and IF

14 The power trace for VBAT must be at least 40-mil wide.

15 The 1.8-V trace must be at least 18-mil wide.

16 Make VBAT traces as wide as possible to ensure reduced inductance and trace resistance.

17 If possible, shield VBAT traces with ground above, below, and beside the traces.

18 SDIO signals traces (CLK, CMD, D0, D1, D2, and D3) must be routed in parallel to each other and as short as possible (less than

12 cm). In addition, every trace length must be the same as the others. There should be enough space between traces – greater than 1.5 times the trace width or ground – to ensure signal quality, especially for the SDIO_CLK trace. Remember to keep these traces away from the other digital or analog signal traces. TI recommends adding ground shielding around these buses.

19 SDIO and digital clock signals are a source of noise. Keep the traces of these signals as short as possible. If possible, maintain a clearance around them.

7.1.3

RF Trace and Antenna Layout Recommendations

Figure 7-2

shows the location of the antenna on the WL1835MODCOM8 board as well as the RF trace routing from the (X)WL1835 module (TI reference design). The TDK chip multilayer antennas are mounted on the board with a specific layout and matching circuit for the radiation test conducted in FCC, CE, and

IC certifications.

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Antennas are orthogonal to each other.

Antennas distance is Higher than half wavelength.

76.00mm

www.ti.com

No sharp corners.

Constant 50 OHM control impedance RF Trace.

Antenna placement on the edge of the board.

Figure 7-2. Location of Antenna and RF Trace Routing on the TMDXWL1835MODCOM8T Board

Follow these RF trace routing recommendations:

• RF traces must have 50Ω impedance.

• RF traces must not have sharp corners.

• RF traces must have via stitching on the ground plane beside the RF trace on both sides.

• RF traces must be as short as possible. The antenna, RF traces, and module must be on the edge of the PCB product in consideration of the product enclosure material and proximity.

7.1.4

Module Layout Recommendations

Figure 7-3

shows layer 1 and layer 2 of the TI module layout:

Layer 1

Layer 2 (Solid GND)

32

Figure 7-3. TI Module Layout

Follow these module layout recommendations:

• Ensure a solid ground plane and ground vias under the module for stable system and thermal dissipation.

Applications and Implementation

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• Do not run signal traces underneath the module on a layer where the module is mounted.

• Signal traces can be run on a third layer under the solid ground layer and beneath the module mounting.

• Run the host interfaces with ground on the adjacent layer to improve the return path.

• TI recommends routing the signals as short as possible to the host.

7.1.5

Thermal Board Recommendations

The TI module uses µvias for layers 1 through 6 with full copper filling, providing heat flow all the way to the module ground pads.

TI recommends using one big ground pad under the module with vias all the way to connect the pad to all ground layers (see

Figure 7-4 ).

Module

COM8 Board

Figure 7-4. Block of Ground Pads on Bottom Side of Package

Figure 7-5

shows via array patterns, which are applied wherever possible to connect all of the layers to the TI module central or main ground pads.

Figure 7-5. Via Array Patterns

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7.1.6

Baking and SMT Recommendations

7.1.6.1

Baking Recommendations

Follow these baking guidelines for the WiLink 8 module:

• Follow MSL level 3 to perform the baking process.

• After the bag is open, devices subjected to reflow solder or other high temperature processes must be mounted within 168 hours of factory conditions (< 30°C/60% RH) or stored at <10% RH.

• if the Humidity Indicator Card reads >10%, devices require baking before being mounted.

• If baking is required, bake devices for 8 hours at 125 °C.

7.1.6.2

SMT Recommendations

Figure 7-6

shows the recommended reflow profile for the WiLink 8 module.

Temp

(degC)

D3

D2

T3

D1

T1 T2

Meating Preheat Soldering Cooling

Time

(SeC)

Figure 7-6. Reflow Profile for the WiLink 8 Module

Table 7-3

lists the temperature values for the profile shown in

Figure 7-6

.

ITEM

Preheat

Soldering

Peak temperature

Table 7-3. Temperature Values for Reflow Profile

TEMPERATURE (°C)

D1 to approximately D2: 140 to 200

D2: 220

D3: 250 max

TIME (s)

T1: 80 to approximately 120

T2: 60 ±10

T3: 10

34

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8 Device and Documentation Support

8.1

Device Support

8.1.1

Development Support

For a complete listing of development-support tools, visit the Texas Instruments WL18xx Wiki . For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

8.1.2

Device Support Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices.

X Experimental, preproduction, sample or prototype device. Device may not meet all product qualification conditions and may not fully comply with TI specifications. Experimental/Prototype devices are shipped against the following disclaimer:

“This product is still in development and is intended for internal evaluation purposes.” Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of fitness for a specific purpose, of this device.

null Device is qualified and released to production. TI’s standard warranty applies to production devices.

8.2

Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

PARTS

WL1801MOD

WL1805MOD

WL1831MOD

WL1835MOD

PRODUCT FOLDER

Click here

Click here

Click here

Click here

Table 8-1. Related Links

SAMPLE & BUY

Click here

Click here

Click here

Click here

TECHNICAL

DOCUMENTS

Click here

Click here

Click here

Click here

TOOLS &

SOFTWARE

Click here

Click here

Click here

Click here

SUPPORT &

COMMUNITY

Click here

Click here

Click here

Click here

8.3

Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use .

TI E2E™ Online Community

TI's Engineer-to-Engineer (E2E) Community.

Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

TI Embedded Processors Wiki

Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

8.4

Trademarks

WiLink, E2E are trademarks of Texas Instruments.

ARM is a registered trademark of ARM Physical IP, Inc.

Bluetooth is a registered trademark of Bluetooth SIG, Inc..

Android is a trademark of Google Inc.

IEEE Std 802.11 is a trademark of IEEE.

Linux is a registered trademark of Linus Torvalds.

Wi-Fi is a registered trademark of Wi-Fi Alliance.

All other trademarks are the property of their respective owners.

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8.5

Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.6

Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

36

Device and Documentation Support

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9 Mechanical Packaging and Orderable Information

9.1

TI Module Mechanical Outline

Figure 9-1

shows the mechanical outline for the device.

Figure 9-1. TI Module Mechanical Outline

Table 9-1

lists the dimensions for the mechanical outline of the device.

MARKING

L (body size)

W (body size)

T (thickness) a1 a2 a3 b1 b2 b3 c1

Table 9-1. Dimensions for TI Module Mechanical Outline

MIN (mm) NOM (mm) MAX (mm)

13.20

13.30

13.40

13.30

1.90

13.40

13.50

2.00

0.30

0.60

0.65

0.40

0.70

0.75

0.50

0.80

0.85

0.20

0.65

1.20

0.20

0.30

0.75

1.30

0.30

0.40

0.85

1.40

0.40

MARKING

c2 c3 d1 d2 e1 e2 e3 e4 e5 e6

MIN (mm) NOM (mm) MAX (mm)

0.65

0.75

0.85

1.15

0.90

1.25

1.00

1.35

1.10

0.90

1.30

1.30

1.00

1.40

1.40

1.10

1.50

1.50

1.15

1.20

1.00

1.00

1.25

1.30

1.10

1.10

1.35

1.40

1.20

1.20

Copyright © 2013–2014, Texas Instruments Incorporated

Mechanical Packaging and Orderable Information

Submit Documentation Feedback

Product Folder Links:

WL1801MOD WL1805MOD WL1831MOD WL1835MOD

37

WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD

SWRS152J – JULY 2013 – REVISED OCTOBER 2014

www.ti.com

9.2

Packaging Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

38

Mechanical Packaging and Orderable Information

Copyright © 2013–2014, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Links:

WL1801MOD WL1805MOD WL1831MOD WL1835MOD

PACKAGE OPTION ADDENDUM

www.ti.com

3-Sep-2014

PACKAGING INFORMATION

Orderable Device

WL1801MODGBMOCR

WL1801MODGBMOCT

WL1805MODGBMOCR

WL1805MODGBMOCT

WL1831MODGBMOCR

WL1831MODGBMOCT

WL1835MODGBMOCR

Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

100 1200

ACTIVE 100 250

ACTIVE

ACTIVE

100 1200

100 250

ACTIVE

ACTIVE

ACTIVE

100 1200

100 250

100 1200

Eco Plan

(2)

TBD

TBD

TBD

TBD

TBD

TBD

TBD

Lead/Ball Finish

(6)

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI

MSL Peak Temp

(3)

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI

Call TI

Op Temp (°C)

-20 to 70

-20 to 70

-20 to 70

-20 to 70

-20 to 70

-20 to 70

-20 to 70

Device Marking

(4/5)

WL1835MODGBMOCT ACTIVE 100 250 TBD Call TI Call TI -20 to 70

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

3-Sep-2014

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

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DSP

Clocks and Timers

Interface

Logic

Power Mgmt

Microcontrollers

RFID

OMAP Applications Processors

Wireless Connectivity www.ti.com/audio amplifier.ti.com

dataconverter.ti.com

www.dlp.com

dsp.ti.com

www.ti.com/clocks interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

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