Interfacing iMX6x to S29GL

Interfacing iMX6x to S29GL
Interfacing i.MX6x to S29GL-S MirrorBit®
Flash
Application Note
1. Abstract
The Freescale™ i.MX multi-media processors and Spansion® S29GL MirrorBit® flash technology are used
extensively in today's embedded applications. Both Freescale and Spansion continue optimizing their
respective portfolios to enable your next design to be the state of the art solution for applications in
automotive, consumer, industrial, and networking. This document highlights key i.MX6x processor / S29GL-S
flash device features and outlines an example case illustrating the hardware and configuration consideration
when interfacing an i.MX6x to the S29GL-S.
2. Overview and Background
2.1
Introduction
The initial discussion provides a very brief overview of the Freescale i.MX6x single, dual, and quad-core
multimedia processor and the Spansion S29GL MirrorBit Eclipse™ flash family. These initial comments will be
followed with additional information concerning the seamless interface between i.MX6x and the S29GL-S
flash and a simple case study of the i.MX6 / S29GL-S read performance capabilities.
2.2
Freescale i.MX6x Multimedia Processor
Freescale highlights the iMX family as a versatile platform for multimedia and display applications, which uses
an ARM®-based processor offering both performance and integration to enable next-generation smart
devices. The i.MX6x provides scalable multi-core platform solutions ranging from single, dual, and quad-core
families based on the ARM Cortex™-A9. The i.MX6x feature set enables next-generation consumer,
industrial, and automotive applications by combining the powerful processing capabilities of the ARM
Cortex-A9 with enhanced 2D / 3D graphics, as well as high-definition video. The i.MX6x provides a new level
of multimedia performance and is enabling the next generation user experience. Figure 2.1 shows the i.MX6x
high level block diagram. The i.MX6x external memory controller provides the ability to connect to a wide
variety of memory devices. The external memory controller includes multi-mode DDR controller, Raw NAND
flash controller, and the WEIM-PSRAM / NOR-flash interfaces.
Publication Number Interfacing_iMX6x_to_S29GL-S_AN
Revision 01
Issue Date July 9, 2013
A pplication
Note
Figure 2.1 i.MX6x Block Diagram
Digital
Audio
LP-DDR2/DDR3
532 MHz (DDR1066)
NOR Flash
PSRAM
Battery Ctrl
Device
1 / 2 LCD
Displays
CSI2/MIPI
LDB
HDMI
HDMI 1.4
Display
MIPI
Display
DSI/MIPI
GPMI
External
Memory I/F
Internal
RAM
(272 kB)
WEIM
Image Processing
Subsystem
2x IPUv3H
Boot
ROM
(96 kB)
Smart DMA
(SDMA)
TPIU
CTIs
2xCAN i/f
SJC
Shared Peripherals
SSI (3)
Security
CAAM
(16 kB Ram)
eCSPI (5)
5xFast-UART
ESAI
SPDIF Rx/Tx
ASRC
uSDHC (4)
MMC / SD
eMMC / eSD
MMC / SD
SDXC
AUDMUX
Video
Proc. Unit
(VPU + Cache)
Fuse Box
2D Graphics
Proc. Unit
(GPU2D)
GPS
Timers/Control
OpenVG 1.1
Proc. Unit
(GPU VG)
WDOG (2)
GPT
EPIT (2)
OTG PHY1
2xHSIC
PHY
Host PHY2
WLAN
OSC32K
PTM's CTI'S
3D Graphics
Proc. Unit
(GPU3D)
Temp Monitor
SRC
XTALOSC
AP Peripherals
1MB L2 cache
SCU, Timer
CSU
Bluetooth
Crystals and
Clock sources
CCM
L1 I/D Cache
Timer, Wdog
SNVS
(sRTC)
Audio,
Power
Mngmnt.
Clock and Reset
PLL (5)
GPC
ARM Cortex A9
MPCore Platform
4x A9-Core
Debug
DAP
SPBA
PCIe Bus
1 / 2 LVDS
(WUXGA+)
Application Processor
Domain (AP)
MMDC
SATA II
3.0Gbps
4x Camera
Parall / MIPI
A X I and A HB Swit ch Fabric
Raw / ONFI 2.2
Nand-Flash
JTAG
USB OTG
(IEEE1149.6)
(dev/host)
2
I C(3)
PWM (4)
Modem IC
OCOTP
IOMUXC
KPP
GPIO
CAN(2)
Keypad
1-Gbps ENET
MLB 150
DTCP
HSI/MIPI
USB OTG +
3 HS Ports
Ethernet
1-Gbit
10 / 100 M
MLB/Most
Network
This application note focuses on the i.MX6x External Interface Module (EIM), which provides flexible
asynchronous and synchronous access to a wide range of external peripherals such as SRAM and PSRAM
NOR flash. The i.MX6x uses a similar EIM configuration as offered on the previous generation i.MX53. Note
the i.MX6x system bus is faster (2x 64-bit at 532 MHz) compared to the i.MX53, which uses a
64-bit at 200 MHz. It should be noted the EIM and the NAND flash controller share data bus pins in order to
reduce the total number of EXTMC I/O.
External Interface Module Features:
 Up to six chip selects for external devices
 Programmable Data Port Size (x8, x16, and x32)
 Programmable Wait-State Generator: read and write accesses
 Configurable Chip Select 0 base address
 28-bit address bus: 256 Mbyte (2 Gigabit)
 Access Modes: asynchronous, page, burst, multiplexed /non-multiplexed
 Page size options: 2, 4, 8, 16, or 32 words
 EIM Main Clock: maximum frequency 133 MHz
 Supports Boot from external device using CS0
A high level block diagram for the i.MX6x EIM is shown in Figure 2.2.
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Figure 2.2 i.MX6x EIM Block Diagram
IPP_DO_STROBE
IPP_DO_CS_B[5:0]
AXI
controls
IPP_DO_WE_B
LPMD
IPP_DO_OE_B
AXI
Interface
LPACK
Output
Control
IPP_DO_BE_B[3:0]
EIM_GRANT
IPP_DO_ADV_B
EIM_BUSY
Synchronous
Core
Asynchronous
Core
IPP_OBE_DATA_DIR[3:0]
IPP_CBE_MADDR_DIR[1:0]
CONFIGURATION
IPI_EIM_INT
EIM_BOOT[2:0]
IPP_IND_RDY_INT
IPP_DO_CRE_S
Config.
Registers
IPG_CLK_S
IPP_DO_CRE
IPS
Interface
IPS CONTROLS
ACLK
IPP_DO_BCLK
GATED CLOCKS
BCLK
Generation
Clock
Gating
AXI_ADDR[31:0]
Addr
Path
IPP_DO_ADDR_OUT[27:0]
READ_BIGEND,WRITE_BIGEND
IPP_DO_DATA_MADDR[31:0]
IPP_MUXED_DATA_IN[15:0]
WDATA[31:0]
IPP_IND_READ_DATA[31:0]
Data
Path
IPP_IND_WAIT_B
RDATA[31:0]
IPP_IND_FB_BCLK
IPP_IND_DTACK
2.3
Spansion S29GL MirrorBit NOR Flash Family
The Spansion S29GL MirrorBit flash family is the industry's leading price-performance NOR flash memory
technology for embedded applications. The S29GL MirrorBit technology enables designers to create
innovative, state of the art, cost-effective solutions. This product family offers densities from 32 Mb (4 MB) to
2 Gb (256 MB), supporting 3.3V or 1.8V interface voltages, long term reliable data integrity, high performance
Page Read / Write Buffer programming, and long term product support. The S29GL also features a universal
package footprint across device densities for both BGA and TSOP packages. These features can be
leveraged to use varying flash densities across a customer's product line to minimize NRE development cost
and time-to-market.
The latest S29GL-S family integrates Spansion's MirrorBit Eclipse architecture. The Eclipse architecture
enables high bandwidth programming up to 1.5 MB/s. This programming BW is more than 10x faster
compared to the previous generation. The S29GL-S MirrorBit Eclipse also further enhances the Page Read
access times, enabling read BW up to 96 MB/s. These features along with sustaining expected NOR
reliability and continuing cost reductions trends make these devices ideal for today's embedded applications
solutions requiring state of the art read / program performance.
Figure 2.3 shows a typical block diagram for an S29GL Asynchronous / Page MirrorBit flash.
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Note
Figure 2.3 S29GL Asynchronous / Page Mode Block Diagram
DQ15–DQ0
RY/BY#
VCC
Sector Switches
VSS
VIO (VCC Q)
Erase Voltage
Generator
RESET#
WE#
WP#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
OE#
VCC Detector
Timer
S29GL-S
01G
512
256
128
A25 – A0
A24 – A0
A23 – A0
A22 – A0
Address Latch
Chip Enable
Output Enable
Logic
CE#
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
3. i.MX6x and S29GL Interface Considerations
This section considers the interface requirements for an i.MX6x and S29GL128S. Reference the i.MX6x and
S29GL technical documentation to determine the best interface/setup options for specific application
requirements.
3.1
Hardware Interface
As stated earlier, the i.MX6x offers non-multiplexed and multiplex options to support asynchronous and page
read accesses to external peripherals. This section highlights options for interfacing the i.MX6x and
S29GL128S to support asynchronous and page read accesses.
3.1.1
High Level i.MX6x / S29GL-S Interface
Figure 3.1 shows the signal interface from the i.MX6x to an S29GL-S NOR flash.
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Figure 3.1 Interface Diagram for i.MX6x to S29GL-S
EIM_DA[15:0]
A[15:0]
EIM_A[25:16]
A[25:16]
EIM_D [31:16]
D[15:0]
(1)
EIM_CS0
CS#
EIM_OE#
OE#
EIM_RW#
WE#
EIM_GPIO
RY/BY#
WP#
EIM_GPIO
(2)
iMX6x
Power on Reset
3V3
VIO Supply
Ground
Reset#
VCC
VIO
VSS
S29GL-S
Notes:
1. CS0 required for boot.
2. RESET should be connected to same system reset driving the i.MX6x.
3.1.2
Interface Diagram for i.MX6x to S29GL-S
The i.MX6x EMI I/O interface power supply should be set up according to external memory requirements.
Reference the i.MX6x data sheet for additional details.
3.2
i.MX6x / S29GL-S Read Performance Considerations
Embedded applications require fast read performance to enable high speed data transfers from flash to
support fast start-up requirements or transfers of data from NVM to DRAM. The following highlights a case
study of the read performance that can be obtained when interfacing the i.MX6 to a S29GL-S flash.
Example: i.M6 EIM / S29GL-S Functionality
After the power is turned on a system can:
1. Start execution from S29GL-S / Initialize the i.MX6x
2. Copies the flash code to main memory (DDRx)
3. i.MX6 initiates execution from DDR
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A pplication
Note
Figure 3.2 Example Boot-Up Process
1
uC
Flash
2
DDR
3
3.2.1
i.MX6x and S29GL-S Access Highlights
 i.MX6x provides a seamless non-multiplexed address data bus interface to the S29GL-S flash
 i.MX6x and S29GL-S support asynchronous or page mode read access capability
The cache line size should match the flash page size.
3.2.2
i.MX6x Read Access
 Asynchronous Access: single word
 Read Page Access: 2, 4, 8, 16, or 32 words
 EIM Main Clock: default frequency 133 MHz
 Flexible read and write access timing
3.2.3
i.MX6 Clocking
 EIM (NOR flash memory controller) clock is 133 MHz by default
– Clock adjustable for individual memory timing requirements
 Two examples clock setting to access S29GL-S:
– Configuration 1: Optimal Read Performance / Reduced Timing Margins
EMI clock frequency: 120 MHz (8.3 ns per clock tick)
EMI settings for tACC: 91.7 ns (11 clock ticks of 8.3 ns)
EMI settings for tPACC: 16.7 ns (2 clock ticks of 8.3 ns)
– Configuration 2: Good Read Performance / Improved Timing Margins
EMI clock frequency: 133 MHz (7.5 ns per clock tick)
EMI settings for tACC: 97.5 ns (13 clock ticks of 7.5 ns)
EMI settings for tPACC: 22.5 ns (3 clock ticks of 7.5 ns)
Note that these register settings are not guaranteed by Spansion.
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Figure 3.3 i.MX6 Configuration Register Settings
3.2.4
Register Name
Configuration 1
Configuration 2
EIM_CS0GCR1
0x10020281
0x10020281
EIM_CS0GCR2
0x00000001
0x00000001
EIM_CS0RCR1
0x0b020000
0x0d020000
EIM_CS0RCR2
0x00008000
0x00009000
S29GL-S Read Access
 Initial Access: tIACC options from 90 ns to 120 ns page
 Read Access
 Page Size: 16 words and tPACC options from 15 ns to 30 ns
Figure 3.4 and Table 3.1 illustrate the general S29GL128S with 90 ns initial access and 15 ns page read
access characteristics.
Figure 3.4 S29GL-S Asynchronous / Page Read Access
tACC
Amax-A4
A3-A0
tCE
CE#
tOE
OE#
tPACC
DQ15-DQ0
Note:
1. Word Configuration: Toggle A0, A1, A2, and A3.
Table 3.1 S29GL128S90 Access Characteristics
3.2.5
Parameter Description
Value
Asynchronous Access: (tACC)
90 ns
Page Access (tPACC)
15 ns
Read Page Size
16 words (32 bytes)
Read Access Algorithms / Performance Results
 Access algorithms options: optimize flash data transfer to DRAM
– Simple load/store instructions: non-optimal performance
– Memcpy() OS / DMA routines: provides better performance
– Cached access typical provides better performance than uncached
– Data Cache benefits read-only situations:
i.e. boot loaders and other read only requirements
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Note
Table 3.2 Performance Results: i.MX6 / S29GL-S SABRE Solo Platform
Software Algorithm
Configuration 1
Configuration 2
memcpy() cached
80.4 MB/s
65.5 MB/s
memcpy() uncached
59.9 MB/s
53.1 MB/s
DMA with Polling
36.6 MB/s
33.0 MB/s
DMA with Interrupts
35.9 MB/s
32.0 MB/s
Key take away: Memcpy() outperforms DMA.
4. Conclusion
This document highlights key i.MX6x and S29GL-S device features and outlines an example case illustrating
the hardware and configuration consideration when interfacing these devices in your next design. The
examples show cases how both Freescale's and Spansion's product optimizations enable embedded system
solutions supporting faster read and programming capabilities. Freescale's new i.MX6x and Spansion's latest
S29GL-S flash continue to enable state of the art embedded design innovations and solutions.
5. Support
Freescale and Spansion each offer extensive support for their product portfolios.
Freescale offers i.MX6x product documentation and product reference designs that provide a functional
hardware platform and software solution for engineers to develop with the i.MX6x processor family.
http://www.freescale.com/webapp/sps/site/overview.jsp?code=IMX6X_SERIES
Spansion has substantial development collateral including data sheets, application notes, software drivers,
simulation models, hardware development tools, and other support items. They can be found at:
http://www.spansion.com/Support/Pages/Support.aspx
An example software tool offering is the Spansion FFS™. The Spansion Flash File System enables faster read
and write system performance for Spansion flash memory. This is another case of how Spansion is providing
solutions to our customers to optimize system performance. By using Spansion FFS, software engineers can
extract the full value of Spansion NOR flash memory and tune products to offer a better user experience and
ensure very high levels of performance and reliability.
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6. Revision History
Section
Description
Revision 01 (July 9, 2013)
Initial release
July 9, 2013
Interfacing i.MX6x to S29GL-S MirrorBit® Flash
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A pplication
Note
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
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any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
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the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2013 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, and
combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used
are for informational purposes only and may be trademarks of their respective owners.
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Interfacing i.MX6x to S29GL-S MirrorBit® Flash
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