Texas Instruments 2.7-V to 5.5-V 10-Bit 3-uS Quadruple Digital-to-Analog Converters w/Power Down (Rev. B) Datasheet

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ

S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

D

Four 10-Bit D/A Converters

D

Programmable Settling Time of 3

µ s or 9

µ s Typ

D

TMS320, (Q)SPI



, and Microwire



Compatible Serial Interface

D

Internal Power-On Reset

D

Low Power Consumption:

5.5 mW, Slow Mode – 5-V Supply

3.3 mW, Slow Mode – 3-V Supply

D

Reference Input Buffers

D

Voltage Output Range . . . 2

×

the Reference

Input Voltage

D

Monotonic Over Temperature

D

Dual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies)

description

D

Hardware Power Down (10 nA)

D

Software Power Down (10 nA)

D

Simultaneous Update

applications

D

Battery Powered Test Instruments

D

Digital Offset and Gain Adjustment

D

Industrial Process Controls

D

Machine and Motion Control Devices

D

Communications

D

Arbitrary Waveform Generation

D OR PW PACKAGE

(TOP VIEW)

The TLV5604 is a quadruple 10-bit voltage output digital-to-analog converter (DAC) with a flexible

4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5604 is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and a 10-bit DAC value.

DV

DD

PD

LDAC

DIN

SCLK

CS

FS

DGND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AV

DD

REFINAB

OUTA

OUTB

OUTC

OUTD

REFINCD

AGND

The device has provision for two supplies: one digital supply for the serial interface (via pins DV

DD

and DGND), and one for the DACs, reference buffers and output buffers (via pins AV

DD

and AGND). Each supply is independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins

DV

DD

and DGND), with the DACs operating on a 5-V supply. Of course, the digital and analog supplies can be tied together.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow

DACs A and B to have a different reference voltage then DACs C and D.

The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The

TLV5604C is characterized for operation from 0

°

C to 70

°

C. The TLV5604I is characterized for operation from

– 40

°

C to 85

°

C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

Copyright



2002, Texas Instruments Incorporated

1

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN


TA

0

°

C to 70

°

C

– 40

°

C to 85

°

C

AVAILABLE OPTIONS

PACKAGE

SOIC

(D)

TLV5604CD

TLV5604ID

TSSOP

(PW)

TLV5604CPW

TLV5604IPW

functional block diagram

REFINAB

15

AVDD

16

DVDD

1

DAC A

+

_

Power-On

Reset x2

10 10

10-Bit

DAC

Latch

DIN

4

Serial

Input

Register

2

14

FS

SCLK

CS

7

5

6

DAC

Select/

Control

Logic

14-Bit

Data and

Control

Register

2 2-Bit

Control

Data

Latch

2

Power Down/

Speed Control

DAC B

14

OUTA

13

OUTB

REFINCD

DAC C

12

OUTC

11

OUTD

9

AGND

8

DGND

3

DAC D

LDAC

2

PD

2


•

DALLAS, TEXAS 75265

CS

TERMINAL

NAME NO.

AGND

AVDD

DGND

DIN

9

16

6

8

4

DVDD

FS

1

7

PD

LDAC

REFINAB

REFINCD

SCLK

OUTA

OUTB

OUTC

OUTD

2

3

14

13

12

15

10

5

11

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN


Terminal Functions

I

I

I

I

Analog ground

Analog supply

Chip select. This terminal is active low.

Digital ground

Serial data input

Digital supply

Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to the TLV5604.

Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.

This terminal is active low.

I

I

I

I

Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into the serial interface. The DAC outputs are only updated when LDAC is low.

Voltage reference input for DACs A and B.

Voltage reference input for DACs C and D.

Serial Clock input

O DAC A output

O DAC B output

O DAC C output

O DAC D output

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, (DV

DD

, AV

DD

to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Supply voltage difference, (AV

DD

to DV

DD

)

Digital input voltage range

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–2.8 V to 2.8 V

–0.3 V to DV

DD

+ 0.3 V

Reference input voltage range

Storage temperature range, T stg

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

TLV5604I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

–0.3 V to AV

–40

DD

°

°

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V

C to 70

C to 85

°

°

C

C

– 65

°

C to 150

°

C

260

°

C

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.


•

DALLAS, TEXAS 75265

3

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN


recommended operating conditions

5-V supply

3-V supply

DVDD = 2.7 V

DVDD = 5.5 V

DVDD = 2.7 V

DVDD = 5.5 V

5-V supply (see Note 1)

3-V supply (see Note 1)

Load resistance, RL

Load capacitance, CL

Serial clock rate, SCLK

TLV5604C

TLV5604I

NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.

0

0

2

MIN

4.5

2.7

2

2.4

0

–40

NOM

5

3

MAX

5.5

3.3

0.6

1

2.048

AVDD–1.5

1.024

AVDD–1.5

10

100

20

70

85

UNIT k

Ω pF

MHz

°

C

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted)

static DAC specifications

EZS

EG

Resolution

PARAMETER

Integral nonlinearity (INL), end point adjusted

Differential nonlinearity (DNL)

Zero scale error (offset error at zero scale)

Zero scale error temperature coefficient

Gain error

Gain error temperature coefficient

TEST CONDITIONS

See Note 2

See Note 3

See Note 4

See Note 5

See Note 6

See Note 7

MIN TYP MAX UNIT

10 bits

±

0.1

±

1

±

1

±

12

LSB

LSB

10

10

±

0.6

mV ppm/

°

C

%of FS voltage ppm/

°

C

– 80 Zero scale gain

Gain – 80

NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal

1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).

6. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 k Ω

excluding the effects of the zero-error.

7. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).

8. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5

±

0.5 V and 3

±

0.3 V dc, and measuring the proportion of this signal imposed on the zero-code output voltage.

9. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5

±

0.5 V and 3

±

0.3 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change.

4


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



(unless otherwise noted) (continued)

individual DAC output specifications

VO

PARAMETER

Voltage output RL = 10 k Ω

TEST CONDITIONS

Output load regulation accuracy RL = 2 k

Ω

vs 10 k

Ω

MIN

0

TYP

0.1

MAX UNIT

AVDD–0.4

V

0.25

% of FS voltage reference input (REFINAB, REFINCD)

VI

RI

CI

PARAMETER

Input voltage range

Input resistance

Input capacitance

See Note 10

TEST CONDITIONS MIN

0

TYP

10

5

MAX UNIT

AVDD–1.5

V

M

Ω pF

Reference feed through

REFIN = 1 Vpp at 1 kHz + 1.024 V dc

(see Note 11)

–75 dB

Slow 0.5

REFIN = 0 2 V + 1 024 V dc

Fast 1

NOTES: 10. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.

11. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD) input = 1.024 Vdc + 1 Vpp at 1 kHz.

digital inputs (D0–D11, CS, WEB, LDAC, PD)

PARAMETER

IIH

IIL

CI

High-level digital input current

Low-level digital input current

Input capacitance

TEST CONDITIONS

VI = DVDD

VI = 0 V


±

1

±

1

µ

µ

A

A

3 pF power supply

PARAMETER TEST CONDITIONS

Slow

Fast

Slow

Fast


1.4

2.2

3.5

5.5

1

3

1.5

4.5

Power down supply current,

See Figure 12

10 nA


•

DALLAS, TEXAS 75265

5

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



(unless otherwise noted) (continued)

analog output dynamic performance t ts

PARAMETER TEST CONDITIONS

CL = 100 pF, RL = 10 k

Ω

,

Vref = 2.048 V, 1024 V

To

±

L

,

RL = 10 k Ω

, See Notes 12 and 14

To

±

L

RL = 10 k Ω

, See Note 13

,

Code transition from 7FF to 800

Fast

Slow

Fast

Slow

Fast

Slow


5 V/

µ s

1 V/

µ s

2.5

8.5

1

2

10

4

18

µ

µ s s nV-sec Glitch energy

SNR

S/(N+D)

THD

SFDR

Signal-to-noise ratio

Signal to noise + distortion

Total harmonic Distortion

Spurious free dynamic range

Sinewave generated by DAC, l 1 024 3 V d 2 048 5 V fs = 400 KSPS, fOUT = 1.1 kHz sinewave,

CL = 100 pF RL = 10 k Ω

,

BW = 20 kHz

68

65

–68

70

NOTES: 12. Settling time is the time for the output signal to remain within

±

0.5LSB of the final measured value for a digital input code change of 020 hex to 3FF hex or 3FF hex to 020 hex.

13. Settling time is the time for the output signal to remain within

±

0.5LSB of the final measured value for a digital input code change of one count, 1FF hex to 200 hex.

14. Limits are ensured by design and characterization, but are not production tested.

6


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



(unless otherwise noted) (continued) digital input timing requirements

tsu(CS–FS) Setup time, CS low before FS

↓ tsu(FS–CK) Setup time, FS low before first negative SCLK edge tsu(C16–FS)

Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before rising edge of FS tsu(C16–CS) twH twL tsu(D) th(D) twH(FS)

Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS is used instead of the SCLK positive edge to update the DAC, then the setup time is between the FS rising edge and CS rising edge.

Pulse duration, SCLK high

Pulse duration, SCLK low

Setup time, data ready before SCLK falling edge

Hold time, data held valid after SCLK falling edge

Pulse duration, FS high

MIN NOM MAX UNIT

10 ns

8 ns

10 ns

10

25

25

8

5

20 ns ns ns ns ns ns

PARAMETER MEASUREMENT INFORMATION

twH twL

ÎÎÎÎ

SCLK

1

ÎÎÎÎ

ÎÎÎÎ tsu(D)

DIN

ÎÎÎÎ

D15

2 th(D)

CS

ÎÎÎÎ tsu(FS-CK) tsu(CS-FS) twH(FS)

D14

3

D13

4

D12

5 15

D1

16

D0 tsu(C16-CS) tsu(C16-FS)

ÎÎ

ÎÎ

ÎÎ

ÎÎÎ

ÎÎÎ

FS

Figure 1. Timing Diagram


•

DALLAS, TEXAS 75265

7

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN


TYPICAL CHARACTERISTICS

LOAD REGULATION

0.35

0.30

VDD = 5 V,

VREF = 2 V,

VO = Full Scale

0.25

5 V Slow Mode, Sink

0.20

5 V Fast Mode, Sink

0.15

0.10

0.05

0

0 0.02 0.04

0.1

0.2

0.4

0.8

Load Current – mA

Figure 2

1 2 4

LOAD REGULATION

4.002

4.00

3.998

3.996

3.994

3.992

3.99

5 V Slow Mode, Source

5 V Fast Mode, Source

3.988

3.986

VDD = 5 V,

VREF = 2 V,

VO = Full Scale

3.984

0 0.02 0.04

0.1

0.2

0.4

0.8


1 2

Figure 4

4

LOAD REGULATION

0.20

0.18

0.16

0.14

0.12

VDD = 3 V,

VREF = 1 V,

VO = Full Scale

3 V Slow Mode, Sink

0.10

0.08

0.06

3 V Fast Mode, Sink

0.04

0.02

0

0 0.01 0.02 0.05 0.1

0.2

0.5


Figure 3

0.8

1 2

LOAD REGULATION

2.003

2.0025

2.002

2.0015

2.001

2.0005

3 V Fast Mode, Source

3 V Slow Mode, Source

2

1.9995

VDD = 3 V,

VREF = 1 V,

VO = Full Scale

1.999

0 0.01 0.02 0.05 0.1

0.2

0.5


0.8

1

Figure 5

2

8


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



SUPPLY CURRENT vs

TEMPERATURE

4

3.5

VDD = 3 V,

VREF = 1.024 V,

VO = Full Scale

Fast Mode

3

2.5

2


TEMPERATURE

4

3.5

Fast Mode

3

2.5

I DD

2

Slow Mode

1.5

1

VDD = 5 V,

VREF = 1.024 V,

VO = Full Scale

0.5

–40 –20 0 20 40

T – Temperature –

°

C

60

Figure 7

80 100

I DD

1.5

1

Slow Mode

0.5

–40 –20 0 20 40

T – Temperature –

°

C

60

Figure 6

80 100

–50

–60

–70

–80

0

–20

–30

––40

TOTAL HARMONIC DISTORTION vs

FREQUENCY

0

–10

Vref = 1 V dc + 1 V p/p Sinewave,

Output Full Scale

5

Fast Mode

50 10 20 30 f – Frequency – kHz

Figure 8

100

–50

–60

–70

–80

0

TOTAL HARMONIC DISTORTION vs

FREQUENCY

0

–10



–20

–30

––40

5

Slow Mode

50 10 20 30 f – Frequency – kHz

Figure 9

100


•

DALLAS, TEXAS 75265

9

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



–20

–30

––40

0

TOTAL HARMONIC DISTORTION AND NOISE vs

FREQUENCY

–10



–50

–60

–70

–80

0 5

0

TOTAL HARMONIC DISTORTION AND NOISE vs

FREQUENCY

–10



–20

–30

––40

–50

Fast Mode Slow Mode

–60

–70

10 20 30 f – Frequency – kHz

Figure 10

50 100

–80

0 5

4000


TIME

(WHEN ENTERING POWER-DOWN MODE)

10 20 30 f – Frequency – kHz

Figure 11

3500

50 100

3000

2500

2000

1500

I DD 1000

500

0

0 200 800 1000 400 600 t – Time – ns

Figure 12

10


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



0.2

INTEGRAL NONLINEARITY

VDD = 5 V, Vref = 2 V,

CLK = 1 MHz

0

–0.2

–0.4

–0.6

0 64 128 192 256 320 384 448 512 576

Digital Code

640 704 768 832 896 960 1024

Figure 13

DIFFERENTIAL NONLINEARITY

0.15

0.1

VDD = 5 V, Vref = 2 V,

CLK = 1 MHz

0.05

0

–0.05

–0.1

0 64 128 192 256 320 384 448 512 576 640

Digital Code

704 768 832 896 960 1024

Figure 14


•

DALLAS, TEXAS 75265

11

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN


APPLICATION INFORMATION general function

The TLV5604 is a 10-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer.

The output voltage (full scale determined by external reference) is given by:

2 REF

CODE

2n

[V]

Where REF is the reference voltage and CODE is the digital input value within the range of 0

10

to 2 n

–1, where n=10 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data

format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).

serial interface

Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK.

After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new level.

The serial interface of the TLV5604 can be used in two basic modes:

D

Four wire (with chip select)

D

Three wire (without chip select)

Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows an example with two TLV5604s connected directly to a TMS320 DSP.

TLV5604

CS FS DIN SCLK

TLV5604

CS FS DIN SCLK

TMS320

DSP

XF0

XF1

FSX

DX

CLKX

Figure 15. TMS320 Interface

12


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN


APPLICATION INFORMATION serial interface (continued)

If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5604 to a TMS320, SPI, or Microwire port using only three pins.

TMS320

DSP

FSX

DX

CLKX

TLV5604

FS

DIN

SCLK

CS

SPI

SS

MOSI

SCLK

TLV5604

FS

DIN

SCLK

CS

Microwire

I/O

SO

SK

TLV5604

FS

DIN

SCLK

CS

Figure 16. Three-Wire Interface

Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5604. After the write operation(s), the DAC output is updated automatically on the next positive clock edge following the sixteenth falling clock edge.

serial clock frequency and update rate

The maximum serial clock frequency is given by: f

SCLKmax

+ t wH(min)

1

) t wL(min)

+

20 MHz

The maximum update rate is: f

UPDATEmax

+

16 ǒ t

wH(min)

1

) t

wL(min)

Ǔ + 1.25 MHz

Note that the maximum update rate is a theoretical value for the serial interface since the settling time of the

TLV5604 has to be considered also.

data format

The 16-bit data word for the TLV5604 consists of two parts:

D

Control bits

D

New DAC value

(D15 . . . D12)

(D11 . . . D0)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6

A1 A0 PWR SPD New DAC value (10 bits)

X: don’t care

SPD: Speed control bit.

1

→

fast mode 0

→

slow mode

PWR: Power control bit.

1

→

power down 0

→

normal operation

D5 D4 D3 D2 D1

X

D0

X


•

DALLAS, TEXAS 75265

13

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN


APPLICATION INFORMATION

In power down mode, all amplifiers within the TLV5604 are disabled. A particular DAC (A, B, C, D) of the

TLV5604 is selected by A1 and A0 within the input word.

A1

0

0

1

1

A0

0

1

0

1

DAC

A

B

C

D

TLV5604 interfaced to TMS320C203 DSP

Hardware interfacing

Figure 17 shows an example of how to connect the TLV5604 to a TMS320C203 DSP. The serial port is configured in burst mode, with FSX generated by the TMS320C203 to provide the Frame Sync (FS) input to the TLV5604. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose input/output port bits IO0 and IO1 are used to generate the Chip Select ( CS) and DAC Latch

Update ( LDAC ) inputs to the TLV5604. The active low Power Down ( PD ) is pulled high all the time to ensure the DACs are enabled.

TMS320C203 TLV5604

DX

CLKX

FSX

I/O 0

I/O 1

SDIN

SCLK

FS

CS

LDAC

VDD

PD

REF

REFINAB

REFINCD

VOUTA

VOUTB

VOUTC

VOUTD

VSS

Figure 17. TLV5604 Interfaced with TMS320C203

Software

The application example generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and it is quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.

The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses

LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The samples are stored in a look-up table, which describes two full periods of a sine wave.

The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the tsu(C16-FS) timing requirement will occur. To avoid this, the program waits until the transmission of the previous word has been completed.

14


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ;

; Processor: TMS320C203 runnning at 40 MHz;

; Description:

;

; This program generates a differential in-phase (sine) on (OUTA–OUTB) and it’s

; quadrature (cosine) as a differential signal on (OUTC–OUTD).

;

; The DAC codes for the signal samples are stored as a table of 64 12–bit values,

; describing 2 periods of a sine function. A rolling pointer is used to address the

; table location in the first period of this waveform, from which the DAC A samples are

; read. The samples for the other 3 DACs are read at an offset to this rolling pointer:

; DAC Function Offset from rolling pointer;

; A

; B

; C sine inverse sine cosine

0

16

8

; D

; inverse cosine 24

; The on-chip timer is used to generate interrupts at a fixed rate. The interrupt

; service routine first pulses LDAC low to update all DACs simultaneously with the

; values which were written to them in the previous interrupt. Then all 4 DAC values are

; fetched and written out through the synchronous serial interface. Finally, the

; rolling pointer is incremented to address the next sample, ready for the next

; interrupt.

;

;




; ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ;

; ––––––––––I/O and memory mapped regs –––––––––––– –––––––––––––––––––––––––––––––

.include ”regs.asm”

; ––––––––––––––jump vectors––––––––––––––––––––––––––––––––––––––––––––––––––––––

.ps

0h b b b b start int1 int23 timer_isr

;–––––––––––––––––––––– variables ––––––––––––––––––––––––––––– ––––––––––––––––––– temp .equ

0060h r_ptr iosr_stat

DACa_ptr

.equ

.equ

.equ

0061

0062h

0063h

DACb_ptr

DACc_ptr

DACd_ptr

.equ

.equ

.equ

0064h

0065h

0066h

;––––––––– constants ––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––––

; DAC control bits to be OR’ed onto data

; all fast mode

DACa_control

DACb_control

.equ

.equ

DACc_control

DACd_control

.equ

.equ

09000h

0d000h

;––––––––––– tables –––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––

02000h

01000h

05000h

.ds

sinevals

.word

.word

.word

.word

.word

.word

00800h

0097Ch

00AE9h

00C3Ah

00D61h

00E53h

.word

.word

.word

.word

.word

.word

.word

.word

00F07h

00F76h

00F9Ch

00F76h

00F07h

00E53h

00D61h

00C3Ah


•

DALLAS, TEXAS 75265

15

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

00AE9h

0097Ch

00800h

00684h

00517h

003C6h

0029Fh

001ADh

000F9h

0008Ah

00064h

0008Ah

000F9h

001ADh

0029Fh

003C6h

00517h

00684h

00800h

0097Ch

00AE9h

00C3Ah

00D61h

00E53h

00F07h

00F76h

00F9Ch

00F76h

00F07h

00E53h

00D61h

00C3Ah

00AE9h

0097Ch

00800h

00684h

00517h

003C6h

0029Fh

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

.word

001ADh

000F9h

0008Ah

00064h

0008Ah

000F9h

001ADh

0029Fh

003C6h

00517h

00684h

;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; Main Program

;–––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––––––––––

.ps

1000h

.entry

start

;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; disable interrupts

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– setc INTM ; disable maskable interrupts splk #0ffffh, IFR ; clear all interrupts splk #0004h, IMR ; timer interrupts unmasked

16


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; set up the timer

; timer period set by values in PRD and TDDR

; period = (CLKOUT1 period)

×

(1+PRD)

×

(1+TDDR)

; examples for TMS320C203 with 40 MHz main clock

; Timer rate TDDR PRD

; 80 kHz

; 50 kHz

9

9

24 (18h)

39 (27h)

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– prd_val.equ

tcr_val.equ

0029h

0018h splk #0000h, temp out temp, TIM

; clear timer splk #prd_val, temp ; set PRD out temp, PRD splk #tcr_val, temp ; set TDDR, and TRB=1 for auto-reload out temp, TCR

;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; Configure IO0/1 as outputs to be :

; IO0 CS – and set high

; IO1 LDAC – and set high

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– in temp, ASPCR ; configure as output lacl temp or #0003h sacl temp out temp, ASPCR in temp, IOSR lacl temp or #0003h sacl temp out temp, IOSR

; set them high

;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; set up serial port for

; SSPCR.TXM=1

; SSPCR.MCM=1

; SSPCR.FSM=1

Transmit mode – generate FSX

Clock mode – internal clock source

Burst mode

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– splk #0000Eh, temp out temp, SSPCR splk #0002Eh, temp

; reset transmitter out temp, SSPCR

;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; reset the rolling pointer

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– lacl #000h sacl r_ptr

;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; enable interrupts

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– clrc INTM

; enable maskable interrupts

;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; loop forever!

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– next idle b next

;wait for interrupt

;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; all else fails stop here

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– done b done ;hang there


•

DALLAS, TEXAS 75265

17

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; Interrupt Service Routines

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– int1 ret ; do nothing and return int23 timer_isr: ret ; do nothing and return in iosr_stat, IOSR ; store IOSR value into variable space lacl iosr_stat ; load acc with iosr status

; reset IO1 – LDAC low and sacl out

#0FFFDh temp ; temp, IOSR ; or and out add

#0002h sacl temp out temp, IOSR

#0FFFEh sacl temp temp, IOSR lacl r_ptr

#sinevals sacl DACa_ptr add #08h sacl DACc_ptr add #08h sacl DACb_ptr add sacl mar

#08h

DACd_ptr

*,ar0

; set IO1 – LDAC high

;

;

; reset IO0 – CS low

;

;

; load rolling pointer to accumulator

; add pointer to table start

; to get a pointer for next DAC a sample

; add 8 to get to DAC C pointer

; add 8 to get to DAC B pointer

; add 8 to get to DAC D pointer

; set ar0 as current AR

; DAC A lar lacl or sacl out ar0, DACa_ptr ; ar0 points to DAC a sample

* ; get DAC a sample into accumulator

#DACa_control ; OR in DAC A control bits temp ; temp, SDTR ; send data

;––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––––––––––––––––––––––––––––––––––

; We must wait for transmission to complete before writing next word to the SDTR.

; TLV5604 interface does not allow the use of burst mode with the full packet rate, as

; we need a CLKX –ve edge to clock in last bit before FS goes high again, to allow SPI

; compatibility.

;––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––– rpt nop

#016h ; wait long enough for this configuration

; of MCLK/CLKOUT1 rate

; DAC B lar lacl or sacl out rpt nop ar0, DACb_ptr ; ar0 points to DAC a sample


#DACb_control ; OR in DAC B control bits temp temp, SDTR

#016h

;

; send data

; wait long enough for this configuration


18


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



; DAC C lar lacl or sacl out rpt nop ar0, DACc_ptr ; ar0 points to DAC a sample


#DACc_control ; OR in DAC C control bits temp temp, SDTR

#016h

;

; send data



; DAC D lar lacl or sacl out lacl add and sacl rpt or sacl out clrc ret

.end

ar0, DACd_ptr ; ar0 points to DAC a sample


#DACd_control ; OR in DAC D control bits temp ; temp, SDTR r_ptr

#1h

#001Fh r_ptr

#016h nop

; now take CS high again lacl iosr_stat

#0001h temp temp, IOSR intm

; send data

; load rolling pointer to accumulator

; increment rolling pointer

; count 0–31 then wrap back round

; store rolling pointer



; load acc with iosr status

; set IO0 – CS high

;

;

; re-enable interrupts

; return from interrupt


•

DALLAS, TEXAS 75265

19

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



TLV5604 interfaced to MCS



51 microcontroller

hardware interfacing

Figure 18 shows an example of how to connect the TLV5604 to an MCS



51 Microcontroller. The serial DAC input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the

DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5604. The active low power down pin (PD) of the TLV5604 is pulled high to ensure that the DACs are enabled.

MCS

®

51 TLV5604

RxD

TxD

P3.3

P3.4

P3.4

REF

SDIN

SCLK

LDAC

CS

FS

REFINAB

REFINCD

VDD

PD

VOUTA

VOUTB

VOUTC

VOUTD

VSS

Figure 18. TLV5604 Interfaced with MCS



51 software

The example is the same as for the TMS320C203 in this datasheet, but adapted for a MCS



51 controller. It generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and it’s quadrature

(cosine) signal as the differential signal between VOUTC and VOUTD.

The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses

LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The samples are stored as a look-up table, which describes one full period of a sine wave.

The serial port of the controller is used in Mode 0, which transmits 8 bits of data on RxD, accompanied by a synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the

TLV5604. The CS and FS signals are provided in the required fashion through control of IO port 3, which has bit addressable outputs.

MCS is a registered trademark of Intel Corporation.

20


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

; Processor: 80C51

;

; Description:

;

; This program generates a differential in–phase (sine) on (OUTA–OUTB) and it’s

; quadrature (cosine) as a differential signal on (OUTC–OUTD).

;




;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––

NAME GENIQ

MAIN

ISR

SEGMENT CODE

SEGMENT CODE

SINTBL

VAR1

STACK

SEGMENT CODE

SEGMENT DATA

SEGMENT IDATA

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

; Code start at address 0, jump to start

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

CSEG AT 0

LJMP start ; Execution starts at address 0 on power–up.

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

; Code in the timer0 interrupt vector

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

CSEG AT 0BH

LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

; Global variables need space allocated

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

Temp_ptr:

RSEG VAR1

DS 1 rolling_ptr: DS 1

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

; Interrupt service routine for timer 0 interrupts

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

RSEG ISR timer0isr:

PUSH PSW

PUSH ACC

CLR

SETB

INT1

INT1

; pulse LDAC low

; to latch all 4 previous values at the same time

; 1st thing done in timer isr => fixed period

CLR T0 ; set CS low

; The signal to be output on each DAC is a sine function.

; One cycle of a sine wave is held in a table @ sinevals as 32 samples of msb,

; lsb pairs (64 bytes). We have one pointer which rolls round this table,

; rolling_ptr, incrementing by 2 bytes (1 sample) on each interrupt (at the end of

; this routine).

; The DAC samples are read at an offset to this rolling pointer:

; DAC Function Offset from rolling_ptr

; A sine

; B inverse sine

0

32

; C cosine

; D inverse cosine

MOV

MOV

DPTR,#sinevals

R7,rolling_ptr

16

48

; set DPTR to the start of the table of sine signal values

; R7 holds the pointer into the sine table

MOV A,R7

MOVC A,@A+DPTR

CLR

MOV

INC

T1

SBUF,A

R7

MOV A,R7

MOVC A,@A+DPTR

; get DAC A msb

; msb of DAC A is in the ACC

; transmit it – set FS low

; send it out the serial port

; increment the pointer in R7

; to get the next byte from the table

; which is the lsb of this sample, now in ACC


•

DALLAS, TEXAS 75265

21

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



A_MSB_TX:

JNB

CLR

MOV

TI,A_MSB_TX ; wait for transmit to complete

TI

SBUF,A

; clear for new transmit

; and send out the lsb of DAC A

; DAC C next

; DAC C codes should be taken from 16 bytes (8 samples) further on in the sine table

; – this gives a cosine function

MOV

ADD

ANL

MOV

A,R7

A,#0FH

A,#03FH

R7,A

; pointer in R7

; add 15 – already done one INC

; wrap back round to 0 if > 64

; pointer back in R7

MOVC A,@A+DPTR

ORL A,#01H

; get DAC C msb from the table

; set control bits to DAC C address

A_LSB_TX:

JNB TI,A_LSB_TX ; wait for DAC A lsb transmit to complete

SETB T1 ; toggle FS

CLR

CLR

MOV

T1

TI

SBUF,A


; and send out the msb of DAC C

INC

MOV

R7

A,R7

MOVC A,@A+DPTR




C_MSB_TX:

JNB

CLR

MOV

TI,C_MSB_TX ; wait for transmit to complete

TI ; clear for new transmit

SBUF,A ; and send out the lsb of DAC C

; DAC B next

; DAC B codes should be taken from 16 bytes (8 samples) further on

; in the sine table – this gives an inverted sine function

MOV A,R7 ; pointer in R7

ADD

ANL

MOV

A,#0FH

A,#03FH

R7,A




MOVC A,@A+DPTR

ORL A,#02H

C_LSB_TX:

JNB TI,C_LSB_TX

SETB T1

CLR T1

CLR TI

MOV SBUF,A

INC

MOV

R7

A,R7

MOVC A,@A+DPTR

; get DAC B msb from the table

; set control bits to DAC B address

; wait for DAC C lsb transmit to complete

; toggle FS


; and send out the msb of DAC B

; get DAC B LSB




B_MSB_TX:

JNB

CLR

MOV

TI,B_MSB_TX

TI

SBUF,A

; wait for transmit to complete


; and send out the lsb of DAC B

22


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



; DAC D next

; DAC D codes should be taken from 16 bytes (8 samples) further on in the sine table

; – this gives an inverted cosine function

MOV A,R7 ; pointer in R7

ADD

ANL

MOV

A,#0FH

A,#03FH

R7,A




MOVC A,@A+DPTR

ORL A,#03H

B_LSB_TX:

JNB TI,B_LSB_TX

SETB T1

CLR T1

CLR

MOV

TI

SBUF,A

INC R7

MOV A,R7

MOVC A,@A+DPTR

; get DAC D msb from the table

; set control bits to DAC D address

; wait for DAC B lsb transmit to complete

; toggle FS


; and send out the msb of DAC D




D_MSB_TX:

JNB

CLR

MOV

TI,D_MSB_TX

TI

SBUF,A

; wait for transmit to complete


; and send out the lsb of DAC D

; increment the rolling pointer to point to the next sample

; ready for the next interrupt

MOV

ADD

ANL

MOV

A,rolling_ptr

A,#02H

A,#03FH rolling_ptr,A

; add 2 to the rolling pointer


; store in memory again

D_LSB_TX:

JNB TI,D_LSB_TX

CLR TI

SETB T1

SETB T0

POP

POP

ACC

PSW

; wait for DAC D lsb transmit to complete

; clear for next transmit

; FS high

; CS high

RETI

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

; Stack needs definition

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

RSEG STACK

DS 10h ; 16 Byte Stack!


•

DALLAS, TEXAS 75265

23

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN



;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

; Main program code

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

RSEG MAIN start:

MOV SP,#STACK–1 ; first set Stack Pointer

CLR

MOV

MOV

MOV

A

SCON,A

TMOD,#02H

TH0,#038H

SETB INT1

SETB T1

SETB T0

SETB ET0

SETB EA

MOV rolling_ptr,A

SETB TR0

; set serial port 0 to mode 0

; set timer 0 to mode 2 – auto-reload

; set TH0 for 5 kHs interrupts

; set LDAC = 1

; set FS = 1

; set CS = 1

; enable timer 0 interrupts

; enable all interrupts

; set rolling pointer to 0

; start timer 0 always:

JMP always ; while(1) !

RET

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

; Table of 32 sine wave samples used as DAC data

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ––––––

RSEG SINTBL sinevals:

DW

DW

DW

DW

DW

DW

01000H

0903EH

05097H

0305CH

0B086H

070CAH

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

0F0E0H

0F06EH

0F039H

0F06EH

0F0E0H

070CAH

0B086H

0305CH

05097H

0903EH

01000H

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

06021H

0A0E8H

0C063H

040F9H

080B5H

0009FH

00051H

00026H

00051H

0009FH

080B5H

040F9H

0C063H

0A0E8H

06021H

END

24


•

DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN


MECHANICAL DATA

D (R-PDSO-G**)

14 PIN SHOWN

PLASTIC SMALL-OUTLINE PACKAGE

14

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

8

0.010 (0,25) M

0.008 (0,20) NOM

0.157 (4,00)

0.150 (3,81)

0.244 (6,20)

0.228 (5,80)

Gage Plane

1

A

7

0

°

– 8

°

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

Seating Plane

0.004 (0,10)

DIM

PINS **

A MAX

A MIN

8 14 16

0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.394

(10,00)

0.386

(9,80)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

4040047 / D 10/96


•

DALLAS, TEXAS 75265

25

TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µ


WITH POWER DOWN


MECHANICAL DATA

PW (R-PDSO-G**)

14 PIN SHOWN

PLASTIC SMALL-OUTLINE PACKAGE

0,65

0,30

0,19

0,10 M

14 8

1

A

7

4,50

4,30

6,60

6,20

0,15 NOM

Gage Plane

0

°

– 8

°

0,25

0,75

0,50

1,20 MAX

0,15

0,05

PINS **

DIM

A MAX

A MIN

8

3,10

2,90

14

5,10

4,90

Seating Plane

0,10

16

5,10

4,90

20

6,60

6,40

24

7,90

7,70

28

9,80

9,60

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

4040064 / E 08/96

26


•

DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

27-Aug-2009 www.ti.com

PACKAGING INFORMATION

Orderable Device

TLV5604CD

TLV5604CDG4

TLV5604CDR

TLV5604CDRG4

TLV5604CPW

TLV5604CPWG4

TLV5604CPWR

TLV5604CPWRG4

TLV5604ID

TLV5604IDG4

TLV5604IPW

TLV5604IPWG4

TLV5604IPWR

TLV5604IPWRG4

Status

(1)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

Package

Type

SOIC

SOIC

SOIC

SOIC

TSSOP

TSSOP

TSSOP

TSSOP

SOIC

SOIC

TSSOP

TSSOP

TSSOP

TSSOP

Package

Drawing

D

D

D

D

PW

PW

PW

PW

D

D

PW

PW

PW

PW

Eco Plan

(2)

Pins Package

Qty

16 40 Green (RoHS & no Sb/Br)

Lead/Ball Finish MSL Peak Temp

(3)

CU NIPDAU Level-1-260C-UNLIM

16 CU NIPDAU Level-1-260C-UNLIM

16

40 Green (RoHS & no Sb/Br)



16 CU NIPDAU Level-1-260C-UNLIM

16

16

16

16

16

16








CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

16

16

16

16






CU NIPDAU

CU NIPDAU

CU NIPDAU

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Aug-2009 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

25-Sep-2009

*All dimensions are nominal

Device

TLV5604CDR

TLV5604CPWR

TLV5604IPWR

Package

Type

Package

Drawing

SOIC

TSSOP

TSSOP

D

PW

PW

Pins

16

16

16

SPQ

2500

2000

2000

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

16.4

330.0

330.0

12.4

12.4

A0

(mm)

6.5

6.9

6.9

B0

(mm)

10.3

5.6

5.6

K0

(mm)

P1

(mm)

2.1

1.6

1.6

8.0

W

(mm)

Pin1

Quadrant

16.0

8.0

12.0

8.0

12.0

Q1

Q1

Q1

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

25-Sep-2009

*All dimensions are nominal

Device

TLV5604CDR

TLV5604CPWR

TLV5604IPWR

Package Type Package Drawing Pins

SOIC

TSSOP

TSSOP

D

PW

PW

16

16

16

SPQ

2500

2000

2000

Length (mm) Width (mm) Height (mm)

346.0

346.0

346.0

346.0

346.0

346.0

33.0

29.0

29.0

Pack Materials-Page 2

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

Logic

Power Mgmt

Microcontrollers

RFID amplifier.ti.com

dataconverter.ti.com

www.dlp.com

dsp.ti.com

www.ti.com/clocks interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

RF/IF and ZigBee® Solutions www.ti.com/lprf

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

Telephony

Video & Imaging

Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2009, Texas Instruments Incorporated

Texas Instruments 2.7-V to 5.5-V 10-Bit 3-uS Quadruple Digital-to-Analog Converters w/Power Down (Rev. B) Datasheet

description

applications

functional block diagram

Terminal Functions

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

recommended operating conditions

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted)

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted) (continued)

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted) (continued)

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted) (continued) digital input timing requirements

PARAMETER MEASUREMENT INFORMATION

TYPICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS

APPLICATION INFORMATION general function

serial interface

APPLICATION INFORMATION serial interface (continued)

serial clock frequency and update rate

wH(min)

wL(min)

data format

APPLICATION INFORMATION

TLV5604 interfaced to TMS320C203 DSP

APPLICATION INFORMATION

APPLICATION INFORMATION

APPLICATION INFORMATION

APPLICATION INFORMATION

APPLICATION INFORMATION

APPLICATION INFORMATION

TLV5604 interfaced to MCS

51 microcontroller

APPLICATION INFORMATION

APPLICATION INFORMATION

APPLICATION INFORMATION

APPLICATION INFORMATION

MECHANICAL DATA

MECHANICAL DATA

PACKAGE OPTION ADDENDUM

PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

PACKAGE MATERIALS INFORMATION

Related manuals

Texas Instruments

2.7-V To 5.5-V Low-Power Dual 8-Bit Digital-to-Analog Converter With Power Down (Rev. D)

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