Infineon SAF-XE161HL-20F80V AA Microcontroller Data Sheet

16-Bit

Architecture

XE161FL, XE161HL

16-Bit Single-Chip

Real Time Signal Controller

XE166 Family / Econo Line

Data Sheet

V1.2 2012-07

M i c r o c o n t r o l l e r s

Edition 2012-07

Published by

Infineon Technologies AG

81726 Munich, Germany

©

2012 Infineon Technologies AG

All Rights Reserved.

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Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (

www.infineon.com

).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

16-Bit

Architecture

XE161FL, XE161HL

16-Bit Single-Chip

Real Time Signal Controller

XE166 Family / Econo Line

Data Sheet

V1.2 2012-07

M i c r o c o n t r o l l e r s

XE161FL, XE161HL

XE166 Family / Econo Line

XE161xL Data Sheet

Revision History: V1.2 2012-07

Previous Versions: V1.0 2010-12, V1.1 2011-09

Page Subjects (major changes since last revision)

52

,

53

74

The value of absolute sum of overload currents parameter in absolute maximum rating parameter and operating conditions tables are switched.

Table description on coding of bit field LEVxV is updated.

Trademarks

C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.

We Listen to Your Comments

Is there any information in this document that you feel is wrong, unclear or missing?

Your feedback will help us to continuously improve the quality of this document.

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[email protected]

Data Sheet V1.2, 2012-07



Table of Contents


4

4.1

4.1.1

4.2

4.2.1

4.3

4.3.1

4.3.2

4.3.3

4.4

4.5

4.6

4.7

3.8

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.16

3.17

3.18

3.19

1

1.1

1.2

2

2.1

2.2

Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Memory Checker Module (MCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Capture/Compare Unit (CC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . . 42

MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Window Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Voltage Range definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

DC Parameters for Upper Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 58

DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 60

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Data Sheet 1 V1.2, 2012-07

4.7.1

4.7.2

4.7.2.1

4.7.2.2

4.7.2.3

4.7.3

4.7.4

4.7.5

4.7.6

5

5.1

5.2

5.3




Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Wakeup Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Selecting and Changing the Operating Frequency . . . . . . . . . . . . . . 82

External Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Pad Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Synchronous Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Data Sheet 2 V1.2, 2012-07



Summary of Features

16-Bit Single-Chip

Real Time Signal Controller

XE161xL (XE166 Family)

1 Summary of Features

For a quick overview and easy reference, the features of the XE161xL are summarized here.

• High-performance CPU with five-stage pipeline and MPU

– 12.5 ns instruction cycle @ 80 MHz CPU clock (single-cycle execution)

– One-cycle 32-bit addition and subtraction with 40-bit result

– One-cycle multiplication (16

× 16 bit)

– Background division (32 / 16 bit) in 21 cycles

– One-cycle multiply-and-accumulate (MAC) instructions

– Enhanced Boolean bit manipulation facilities

– Zero-cycle jump execution

– Additional instructions to support HLL and operating systems

– Register-based design with multiple variable register banks

– Fast context switching support with two additional local register banks

– 16 Mbytes total linear address space for code and data

– 1,024 Bytes on-chip special function register area (C166 Family compatible)

– Integrated Memory Protection Unit (MPU)

• Interrupt system with 16 priority levels providing 64 interrupt nodes

– Selectable external inputs for interrupt generation and wake-up

– Fastest sample-rate 12.5 ns

• Eight-channel interrupt-driven single-cycle data transfer with

Peripheral Event Controller (PEC), 24-bit pointers cover total address space

• Clock generation from internal or external clock sources, using on-chip PLL or prescaler

• Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip

Memory Areas

• On-chip memory modules

– 2 Kbytes on-chip dual-port RAM (DPRAM)

– 6 Kbytes on-chip data SRAM (DSRAM)

– 4 Kbytes on-chip program/data SRAM (PSRAM)

– Up to 160 Kbytes on-chip program memory (Flash memory)

– Memory content protection through Error Correction Code (ECC) for Flash memory and through parity for RAMs

Data Sheet 3 V1.2, 2012-07




• On-Chip Peripheral Modules

– Synchronizable 12-bit A/D Converter with up to 10 channels, conversion time below 1

μs, optional data preprocessing (data reduction, range check), broken wire detection

– 16-channel general purpose capture/compare unit (CC2)

– Two capture/compare units for flexible PWM signal generation (CCU6x)

– Multi-functional general purpose timer unit with 5 timers

– Up to 4 serial interface channels to be used as UART, LIN, high-speed synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s),

IIS interface

– On-chip MultiCAN interface (Rev. 2.0B active) with up to 32 message objects

(Full CAN/Basic CAN) on 2 CAN nodes and gateway functionality

– On-chip system timer and on-chip real time clock

• Single power supply from 3.0 V to 5.5 V

• Power reduction and wake-up modes with flexible power management

• Programmable window watchdog timer and oscillator watchdog

• Up to 33 general purpose I/O lines

• On-chip bootstrap loaders

• Supported by a full range of development tools including C compilers, macroassembler packages, emulators, evaluation boards, HLL debuggers, simulators, logic analyzer disassemblers, programming boards

• On-chip debug support via Device Access Port (DAP), Single-Pin DAP (SPD) or

JTAG interface

• 48-pin Green VQFN package, 0.5 mm (10.7 mil) pitch

Ordering Information

The ordering code for an Infineon microcontroller provides an exact reference to a specific product. This ordering code identifies:

• the function set of the corresponding product type

• the temperature range

1)

:

– SAF-…: -40°C to 85°C

– SAK-…: -40°C to 125°C

• the package and the type of delivery.

For ordering codes for the XE161xL please contact your sales representative or local distributor.

1) Not all derivatives are offered in all temperature ranges.

Data Sheet 4 V1.2, 2012-07




1.1

Device Types

The following XE161xL device types are available and can be ordered through Infineon’s direct and/or distribution channels.

Table 1

Derivative

1)

Synopsis of XE161xL Device Types

Flash

Memory

2)

PSRAM

DSRAM

3)

Capt./Comp.

Modules

ADC

4)

Chan.

Interfaces

4)

10 XE161FL-12FxV 96 Kbytes 4 Kbytes

6 Kbytes

XE161HL-12FxV 96 Kbytes 4 Kbytes

6 Kbytes

CC2

CCU60/3

CC2

CCU60/3

10

2 CAN Nodes,

4 Serial Chan.

4 Serial Chan.

XE161FL-20FxV 160 Kbytes 4 Kbytes

6 Kbytes

XE161HL-20FxV 160 Kbytes 4 Kbytes

6 Kbytes

CC2

CCU60/3

CC2

CCU60/3

1) x is a placeholder for available speed grade in MHz. Can be 66 or 80.

2) Specific information about the on-chip Flash memory in

Table 3

.

3) All derivatives additionally provide 2 Kbytes DPRAM.

4) Specific information about the available channels in

Table 5

.

10

10

2 CAN Nodes,

4 Serial Chan.

4 Serial Chan.

Data Sheet 5 V1.2, 2012-07




1.2

Definition of Feature Variants

The XE161xL types are offered with several Flash memory sizes.

Table 3

and

Table 4

describe the location of the available Flash memory.

Table 3 Continuous Flash Memory Ranges

Total Flash Size

160 Kbytes

96 Kbytes

1st Range

1)

C0’0000

H

…

C0’EFFF

H

C0’0000

H

…

C0’EFFF

H

2nd Range

C1’0000

H

…

C2’0FFF

H

C1’0000

H

…

C1’0FFF

H

3rd Range

C4’0000

H

…

C4’7FFF

H

C4’0000

H

…

C4’7FFF

H

1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000

H

to C0’FFFF

H

).

Table 4 Flash Memory Module Allocation (in Kbytes)

Total Flash Size Flash 0

1)

Flash 1

160 128 32

96 64 32


H

to C0’FFFF

H

).

The XE161xL types are offered with different interface options.

Table 5

lists the available channels for each option.

Table 5

Total Number

10 ADC0 channels

2 CAN nodes

Interface Channel Association

4 serial channels

Available Channels / Message Objects

CH0, CH2, CH3, CH4, CH8, CH9, CH16, CH17, CH19,

CH20

CAN0, CAN1

32 message objects

U0C0, U0C1, U1C0, U1C1

Data Sheet 6 V1.2, 2012-07



General Device Information

2 General Device Information

The XE161xL series (16-Bit Single-Chip

Real Time Signal Controller) is a part of the Infineon XE166 Family of full-feature singlechip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 80 million instructions per second) with extended peripheral functionality and enhanced IO capabilities. Optimized peripherals can be adapted flexibly to meet the application requirements. These derivatives utilize clock generation via PLL and internal or external clock sources. On-chip memory modules include program Flash, program RAM, and data RAM.

V

AREF

V

AGND

(1) (1)

V

DDIM

V

DDPB

(2) (3)

V

SS

(3)

XTAL1

XTAL2

Port 10

12 bit

Port 5

6 bit

Port 2

12 bit

Port 6

3 bit

PORST TRST

TESTM

SPD/DAP/

JTAG

1 / 2 / 4 bit

Debug

2 bit via Port Pins

MC_XY _LOGSYMB 48

Figure 1

Data Sheet

XE161xL Logic Symbol

7 V1.2, 2012-07




2.1

Pin Configuration and Definition

The pins of the XE161xL are described in detail in

Table 6

, which includes all alternate

functions. For further explanations please refer to the footnotes at the end of the table.

The following figure summarizes all pins, showing their locations on the four sides of the package.

TESTM

TRST

P6.3

P6.1

P6.0

V

SS

V

DDPB

V

AREF

V

AGND

P5.0

P5.2

P5.3

3

4

5

6

1

2

7

8

9

10

11

12

VQFN48

32

31

30

29

28

27

36

35

34

33

26

25

P10.5

P10.4

P10.3

P10.2

P10.1

P10.0

P2.13

P2.10

P2.9

P2.8

P2.7

P2.6

MC_XY_PIN48

Figure 2 XE161xL Pin Configuration (top view)

Data Sheet 8 V1.2, 2012-07




Key to Pin Definitions

• Ctrl.: The output signal for a port pin is selected by bit field PC in the associated register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to

1x00

B

, output O1 is selected by 1x01

B

, etc.

Output signal OH is controlled by hardware.

• Type: Indicates the pad type and its power supply domain (B, M).

– St: Standard pad

– Sp: Special pad e.g. XTALx

– DA: Digital IO and analog input

– In: Input only pad

– PS: Power supply pad

Table 6 Pin Definitions and Functions

Pin Symbol

1 TESTM

2

3

TRST I

I

Ctrl.

Type Function

In/B

Testmode Enable

Enables factory test modes, must be held HIGH for normal operation (connect to

V

DDPB

).

An internal pullup device will hold this pin high when nothing is driving it.

In/B

Test-System Reset Input

For normal system operation, pin TRST should be held low. A high level at this pin at the rising edge of PORST activates the XE161xL’s debug system.

In this case, pin TRST must be driven low once to reset the debug system.

An internal pulldown device will hold this pin low when nothing is driving it.

P6.3

CCU63_COU

T62

T3OUT

U1C1_SELO

0

U1C1_DX2D I

ADC0_REQT

RyF

I

O0 / I St/B

Bit 3 of Port 6, General Purpose Input/Output

O1 St/B

CCU63 Channel 2 Output

O2

O3

St/B

St/B

St/B

St/B

GPT12E Timer T3 Toggle Latch Output

USIC1 Channel 1 Select/Control 0 Output

USIC1 Channel 1 Shift Control Input

External Request Trigger Input for ADC0/1

Data Sheet 9 V1.2, 2012-07




Table 6

Pin Symbol

4 P6.1

Pin Definitions and Functions (cont’d)

ADC0_CH17 I

Ctrl.

Type Function

O0 / I DA/B Bit 1 of Port 6, General Purpose Input/Output

DA/B Analog Input Channel 17 for ADC0

EMUX1

T3OUT

O1

O2

U1C1_DOUT O3

ADC0_REQT

RyE

I

DA/B External Analog MUX Control Output 1 (ADC0)

DA/B GPT12E Timer T3 Toggle Latch Output

DA/B USIC1 Channel 1 Shift Data Output

DA/B External Request Trigger Input for ADC0

5

CCU63_CTR

APB

U1C1_DX0A I

I

ESR1_6

P6.0

DA/B CCU63 Emergency Trap Input

I

DA/B USIC1 Channel 1 Shift Data Input

DA/B ESR1 Trigger Input 6


ADC0_CH16 I

EMUX0 O1

O2 CCU63_COU

T61

BRKOUT O3


DA/B External Analog MUX Control Output 0 (ADC0)

DA/B CCU63 Channel 1 Output

DA/B OCDS Break Signal Output

DA/B External Request Gate Input for ADC0 ADC0_REQG

TyG

U1C1_DX0E I

I

10 P5.0

ADC0_CH0 I

I

11 P5.2

ADC0_CH2 I

I

DA/B USIC1 Channel 1 Shift Data Input

In/B

In/B

Bit 0 of Port 5, General Purpose Input

Analog Input Channel 0 for ADC0

In/B


In/B


TDI_A

12 P5.3

ADC0_CH3 I

T3INA I

I

I In/B

JTAG Test Data Input

In/B


In/B


In/B

GPT12E Timer T3 Count/Gate Input

Data Sheet 10 V1.2, 2012-07




Table 6

Pin Symbol


Ctrl.

Type Function

13 P5.4

ADC0_CH4 I

I

I CCU63_T12

HRB

T3EUDA I

In/B

In/B

In/B



External Run Control Input for T12 of CCU63

14

TMS_A

P5.8

ADC0_CH8 I

CCU6x_T12H

RC

CCU6x_T13H

RC

I

15 P5.9

ADC0_CH9 I

CC2_T7IN I

I

I

I

I

In/B

GPT12E Timer T3 External Up/Down Control

Input

In/B

JTAG Test Mode Selection Input

In/B


In/B


In/B

External Run Control Input for T12 of CCU60/3

In/B

In/B

External Run Control Input for T13 of CCU60/3


In/B


In/B

CAPCOM2 Timer T7 Count Input

16 P2.0

CCU63_CC6

0

RxDC0C

CCU63_CC6

0INB

ADC0_CH19 I

T5INB I

I

I


O2 DA/B CCU63 Channel 0 Output

DA/B CAN Node 0 Receive Data Input

DA/B CCU63 Channel 0 Input


DA/B GPT12E Timer T5 Count/Gate Input

Data Sheet 11 V1.2, 2012-07




Table 6

Pin Symbol


Ctrl.

Type Function

17 P2.1

TxDC0


O1

O2

DA/B CAN Node 0 Transmit Data Output

DA/B CCU63 Channel 1 Output CCU63_CC6

1

CCU63_CC6

1INB

I DA/B CCU63 Channel 1 Input

ADC0_CH20

T5EUDB

ESR1_5

ERU_0A0

I

I

I

I


DA/B GPT12E Timer T5 External Up/Down Control

Input

DA/B ESR1 Trigger Input 5

DA/B External Request Unit Channel 0 Input A0

21 P2.2

TxDC1

CCU63_CC6

2

CCU63_CC6

2INB

ESR2_5

ERU_1A0

I

I

I

O0 / I St/B

O1

O2

St/B

St/B

St/B


CAN Node 1 Transmit Data Output


CCU63 Channel 2 Input

St/B

ESR2 Trigger Input 5

St/B

External Request Unit Channel 1 Input A0

22 P2.3

O0 / I St/B


U0C0_DOUT O1 St/B

USIC0 Channel 0 Shift Data Output

CCU63_COU

T63

O2 St/B


CC2_CC16 O3 / I St/B

CAPCOM2 CC16IO Capture Inp./ Compare Out.

ESR2_0

U0C0_DX0E I

I

U0C1_DX0D I

RxDC0A I

St/B


St/B

USIC0 Channel 0 Shift Data Input

St/B


St/B

CAN Node 0 Receive Data Input

Data Sheet 12 V1.2, 2012-07




Table 6

Pin Symbol


Ctrl.

Type Function

23 P2.4

O0 / I St/B


U0C1_DOUT O1 St/B


TxDC0 O2 St/B




ESR1_0

U0C0_DX0F I

I

RxDC1A

24 P2.5

St/B

St/B



I St/B


O0 / I St/B


U0C0_SCLK

OUT

TxDC0

O1

O2

St/B

USIC0 Channel 0 Shift Clock Output

St/B




U0C0_DX1D I

ESR1_10

25 P2.6

St/B

USIC0 Channel 0 Shift Clock Input

I St/B


O0 / I St/B


U0C0_SELO

0

U0C1_SELO

1

O1

O2

St/B

St/B





CLKIN1 I St/B

Clock Signal Input 1

U0C0_DX2D I

RxDC0D I

ESR2_6 I

St/B

St/B

St/B




Data Sheet 13 V1.2, 2012-07




Table 6

Pin Symbol

26 P2.7

U0C1_SELO

0


Ctrl.

Type Function

O0 / I St/B

O1 St/B



U0C0_SELO

1

O2 St/B




U0C1_DX2C I

ESR2_7 I

RxDC1C

U1C0_DX0A I

I

St/B

St/B

St/B

St/B





27 P2.8

U0C1_SCLK

OUT

O0 / I St/B


O1 St/B


EXTCLK O2 St/B

Programmable Clock Signal Output



U0C1_DX1D I

28 P2.9

St/B


O0 / I St/B


U0C1_DOUT O1

TxDC1 O2

St/B

St/B





C1 I St/B

Configuration Pin 1

TCK_A

29 P2.10

I St/B

DAP0/JTAG Clock Input

O0 / I St/B


U0C1_DOUT O1

U0C0_SELO

3

O2

St/B

St/B





U0C1_DX0E I St/B


CAPINA I St/B

GPT12E Register CAPREL Capture Input

Data Sheet 14 V1.2, 2012-07




Table 6

Pin Symbol


Ctrl.

Type Function

30, P2.13

O0 / I St/B


U1C1_DOUT O1 St/B


CCU63_COU

T60

U1C1_DX0B I

O2 St/B


St/B


U1C0_DX0B I

31 P10.0

St/B


O0 / I St/B


St/B


St/B


U0C1_DOUT O1

CCU60_CC6

0

O2

CCU60_CC6

0INA

ESR1_2

U0C0_DX0A I

I

I St/B

St/B

St/B




U0C1_DX0A I St/B


U1C1_DX0C I

32 P10.1

St/B


O0 / I St/B


U0C0_DOUT O1

CCU60_CC6

1

O2

St/B

St/B



CCU60_CC6

1INA

U0C0_DX0B I

I St/B


U0C0_DX1A I

33 P10.2

St/B


St/B


O0 / I St/B


O1 St/B


U0C0_SCLK

OUT

CCU60_CC6

2

O2 St/B


CCU60_CC6

2INA

U0C0_DX1B I

I St/B


St/B


Data Sheet 15 V1.2, 2012-07




Table 6

Pin Symbol

34 P10.3

CCU60_COU

T60


Ctrl.

Type Function

O0 / I St/B

O2 St/B



U0C0_DX2A I

U0C1_DX2A I

St/B


St/B


RxDC1D

35 P10.4

U0C0_SELO

3

CCU60_COU

T61

U0C0_DX2B I

U0C1_DX2B I

I St/B


O0 / I St/B


O1 St/B


O2 St/B

St/B

St/B




ESR1_9

36 P10.5

U0C1_SCLK

OUT

CCU60_COU

T62

I

O1

O2

St/B

O0 / I St/B

St/B

St/B





U0C1_DX1B I

37 P10.6

St/B


O0 / I St/B


U0C0_DOUT

U1C0_DOUT

U1C0_DX2D I

CCU6x_CTR

APA

I

U1C0_DX0F I

O1

O2

U1C0_SELO

0

U0C0_DX0C I

O3

St/B


St/B


St/B


St/B

St/B

St/B

St/B



CCU60/CCU63 Emergency Trap Input


Data Sheet 16 V1.2, 2012-07




Table 6

Pin Symbol


Ctrl.

Type Function

38 P10.7

O0 / I St/B


U0C1_DOUT O1 St/B


O2 St/B


CCU60_COU

T63

CCU63_COU

T61

O3 St/B


U0C1_DX0B I

CCU60_CCP

OS0A

I

T4INB

39 P10.8

St/B

St/B


CCU60 Position Input 0

I St/B


O0 / I St/B


O1 St/B

USIC0 Channel 0 Master Clock Output

U0C0_MCLK

OUT

U0C1_SELO

0

U1C0_SCLK

OUT

CCU60_CCP

OS1A

I

O2

O3

St/B

St/B

St/B




U0C0_DX1C I

BRKIN_B I

T3EUDB I

U1C0_DX1A

ESR2_11

I

I

St/B


St/B

OCDS Break Signal Input

St/B

GPT12E Timer T3 External Up/Down Control

Input

St/B


St/B


Data Sheet 17 V1.2, 2012-07




Table 6

Pin Symbol

40 P10.9

U0C0_SELO

4


Ctrl.

Type Function

O0 / I St/B

O1 St/B



O2 St/B

USIC0 Channel 1 Master Clock Output

U0C1_MCLK

OUT

TxDC1

CCU60_CCP

OS2A

TCK_B

I

O3 St/B

St/B



44

T3INB

P10.10

I

I St/B

DAP0/JTAG Clock Input

St/B


O0 / I St/B


O1 St/B


U0C0_SELO

0

CCU60_COU

T63

O2 St/B


U1C0_DOUT O3

U0C0_DX2C I

TDI_B

U0C1_DX1A I

I

St/B


St/B


St/B

JTAG Test Data Input

St/B


45 P10.12

O0 / I St/B


U1C0_DOUT O1 St/B


U0C0_DOUT O2

CCU63_COU

T62

O3

TDO_A

SPD_0

OH

I/OH

St/B

St/B

St/B

St/B



DAP1/JTAG Test Data Output

SPD Input/Output

C0

U0C0_DX0D I

I St/B

Configuration Pin 0

St/B


U1C0_DX0C I

U1C0_DX1E I

46 XTAL2 O

St/B


St/B


Sp/M Crystal Oscillator Amplifier Output

Data Sheet 18 V1.2, 2012-07




7,

20,

41

6,

19,

42

Table 6

Pin Symbol

47 XTAL1


I

Ctrl.

Type Function

ESR2_9

48 PORST I

I

Sp/M Crystal Oscillator Amplifier Input

To clock the device from an external source, drive

XTAL1, while leaving XTAL2 unconnected.

Voltages on XTAL1 must comply to the core supply voltage

V

DDIM

.

St/B


In/B

Power On Reset Input

A low level at this pin resets the XE161xL completely. A spike filter suppresses input pulses

<10 ns. Input pulses >100 ns safely pass the filter.

The minimum duration for a safe recognition should be 120 ns.

An internal pullup device will hold this pin high when nothing is driving it.

8

9

18,

43

V

AREF

V

AGND

V

DDIM

-

-

PS/B Reference Voltage for A/D Converters ADC0

V

V

DDPB

SS

-

-

PS/B Reference Ground for A/D Converters ADC0

PS/M Digital Core Supply Voltage for Domain M

Decouple with a ceramic capacitor, see Data

Sheet for details.

All

V

DDIM

pins must be connected to each other.

PS/B Digital Pad Supply Voltage for Domain B

Connect decoupling capacitors to adjacent

V

DDP

/

V

SS

pin pairs as close as possible to the pins.

PS/-- Digital Ground

All

V

SS

pins must be connected to the ground-line or ground-plane.

Data Sheet 19 V1.2, 2012-07




2.2

Identification Registers

The identification registers describe the current version of the XE161xL and of its modules.

Table 7

Short Name

XE161xL Identification Registers

Value Address

SCU_IDMANUF

SCU_IDCHIP

SCU_IDMEM

SCU_IDPROG

JTAG_ID

1820

H

2801

H

3028

H

1313

H

001D’6083

H

00’F07E

H

00’F07C

H

00’F07A

H

00’F078

H

---

Notes

Data Sheet 20 V1.2, 2012-07



Functional Description

3 Functional Description

The architecture of the XE161xL combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a well-balanced design. On-chip memory blocks allow the design of compact systems-on-silicon with maximum performance suited for computing, control, and communication.

The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data

SRAM) and the generic peripherals are connected to the CPU by separate high-speed buses. Another bus, the LXBus, connects additional on-chip resources and external

resources (see

Figure 3

). This bus structure enhances overall system performance by

enabling the concurrent operation of several subsystems of the XE161xL.

The block diagram gives an overview of the on-chip components and the advanced internal bus structure of the XE161xL.

PSRAM

Flash Memory

System Functions

Clock, Reset, Power

Control

DPRAM

CPU

MAC Unit

DSRAM

MPU Interrupt & PEC

Interrupt Bus

OCDS

Debug Support

LXBUS

Controller

MCHK

WWD

RTC

ADC0

Module

GPT

CC2

Module

CCU6 x

Modules

USICx

Modules

Multi

CAN

8-/10- /

12 -Bit

5

Timers

16

Chan.

3+1

Chan.

each

2

Chan.

each

Analog and Digital General Purpose IO (GPIO) Ports

MC_L- SERIES_BLOCKDIAGRAM

Figure 3

Data Sheet

Block Diagram

21 V1.2, 2012-07




3.1

Memory Subsystem and Organization

The memory space of the XE161xL is configured in the von Neumann architecture. In this architecture all internal and external resources, including code memory, data memory, registers and I/O ports, are organized in the same linear address space.

Table 8

Address Area

XE161xL Memory Map

1)

Start Loc. End Loc.

Area Size

2)

IMB register space

Reserved

FF’FF00

H

F0’0000

H

FF’FFFF

H

FF’FEFF

H

256 bytes

< 1 Mbyte

Notes

Minus IMB registers.

508 Kbytes Mirrors EPSRAM up to 4 Kbytes With Flash timing.

Reserved for EPSRAM E8’1000

H

Emulated PSRAM E8’0000

H

Reserved for PSRAM

PSRAM

E0’1000

H

E0’0000

H

Reserved for Flash

Flash 1

Reserved for Flash

Flash 0

C4’8000

H

C4’0000

H

C2’1000

H

C0’0000

H

External memory area

External IO area

4)

40’0000

H

21’0000

H

Reserved 20’B800

H

USIC0-1 alternate regs.

20’B000

H

MultiCAN alternate regs. 20’8000

H

EF’FFFF

H

E8’0FFF

H

E7’FFFF

H

E0’0FFF

H

DF’FFFF

H

C4’7FFF

H

C3’FFFF

H

C2’0FFF

H

BF’FFFF

H

3F’FFFF

H

20’FFFF

H

20’B7FF

H

20’AFFF

H

508 Kbytes up to 4 Kbytes Program SRAM.

1760 Kbytes

32 Kbytes

124 Kbytes

132 Kbytes

8 Mbytes

1984 Kbytes

18 Kbytes

2 Kbytes

12 Kbytes

3)

Mirrors PSRAM

Accessed via

LXBus Controller

Accessed via

LXBus Controller

Reserved

USIC0-1 registers

20’5000

H

20’4000

H

20’7FFF

H

20’4FFF

H

12 Kbytes

4 Kbytes

MultiCAN registers 20’0000

H

20’3FFF

H

16 Kbytes

Accessed via

LXBus Controller

Accessed via

LXBus Controller

External memory area

SFR area

Dual-port RAM

(DPRAM)

Reserved for DPRAM

01’0000

H

00’FE00

H

00’F600

H

00’F200

H

1F’FFFF

H

00’FFFF

H

00’FDFF

H

00’F5FF

H

1984 Kbytes

0.5 Kbytes

2 Kbytes

1 Kbytes

Data Sheet 22 V1.2, 2012-07




Table 8

Address Area

XE161xL Memory Map (cont’d)

1)

(cont’d)

Start Loc. End Loc.

Area Size

2)

Notes

ESFR area

XSFR area

00’F000

H

00’E000

H

00’F1FF

H

00’EFFF

H

0.5 Kbytes

4 Kbytes

Data SRAM (DSRAM) 00’C800

H

Reserved for DSRAM 00’8000

H

00’DFFF

H

00’C7FF

H

6 Kbytes

18 Kbytes

External memory area 00’0000

H

00’7FFF

H

32 Kbytes

1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate external bus accesses.

2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.


H

to C0’FFFF

H

).

4) Several pipeline optimizations are not active within the external IO area.

This common memory space consists of 16 Mbytes organized as 256 segments of

64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the register spaces (ESFR/SFR) additionally are directly bit addressable.

The internal data memory areas and the Special Function Register areas (SFR and

ESFR) are mapped into segment 0, the system segment.

The Program Management Unit (PMU) handles all code fetches and, therefore, controls access to the program memories such as Flash memory and PSRAM.

The Data Management Unit (DMU) handles all data transfers and, therefore, controls access to the DSRAM and the on-chip peripherals.

Both units (PMU and DMU) are connected to the high-speed system bus so that they can exchange data. This is required if operands are read from program memory, code or data is written to the PSRAM, code is fetched from external memory, or data is read from or written to external resources. These include peripherals on the LXBus such as USIC or MultiCAN. The system bus allows concurrent two-way communication for maximum transfer performance.

4 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.

The PSRAM is accessed via the PMU and is optimized for code fetches. A section of the

PSRAM with programmable size can be write-protected.

Data Sheet 23 V1.2, 2012-07




6 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data.

The DSRAM is accessed via a separate interface and is optimized for data access.

2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined variables, for the system stack, and for general purpose register banks. A register bank can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,

RH7) General Purpose Registers (GPRs).

The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR, any location in the DPRAM is bit addressable.

1024 bytes (2

× 512 bytes) of the address space are reserved for the Special Function

Register areas (SFR space and ESFR space). SFRs are word-wide registers which are used to control and monitor functions of the different on-chip units. Unused SFR addresses are reserved for future members of the XE166 Family. In order to ensure upward compatibility they should either not be accessed or written with zeros.

The on-chip Flash memory stores code, constant data, and control data. The

160 Kbytes of on-chip Flash memory consist of 1 module of 32 Kbytes (preferably for data storage) and 1 module of 128 Kbytes. Each module is organized in 4-Kbyte sectors.

The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used internally to store operation control parameters and protection information.

Each sector can be separately write protected

1)

, erased and programmed (in blocks of

128 Bytes). The complete Flash area can be read-protected. A user-defined password sequence temporarily unlocks protected areas. The Flash modules combine 128-bit read access with protected and efficient writing algorithms for programming and erasing.

Dynamic error correction provides extremely high read data security for all read access operations. Access to different Flash modules can be executed in parallel.

For Flash parameters, please see

Section 4.6

.

Memory Content Protection

The contents of on-chip memories can be protected against soft errors (induced e.g. by radiation) by activating the parity mechanism or the Error Correction Code (ECC).

The parity mechanism can detect a single-bit error and prevent the software from using incorrect data or executing incorrect instructions.

The ECC mechanism can detect and automatically correct single-bit errors. This supports the stable operation of the system.

It is strongly recommended to activate the ECC mechanism wherever possible because this dramatically increases the robustness of an application against such soft errors.

1) To save control bits, sectors are clustered for protection purposes, they remain separate for programming/erasing.

Data Sheet 24 V1.2, 2012-07




3.2

Central Processing Unit (CPU)

The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instructionfetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three register banks, and dedicated

SFRs. The ALU features a multiply-and-divide unit, a bit-mask generator, and a barrel shifter.

PMU

CPU

Prefetch

Unit

Branch

Unit

FIFO

IDX0

IDX1

QX0

QX1

+/-

Multiply

Unit

MAH

MAC

+/-

CSP

CPUCON1

CPUCON2

IP

Return

Stack

QR0

QR1

VECSEG

TFR

IFU

DPP0

DPP1

DPP2

DPP3

Injection/

Exception

Handler

SPSEG

SP

STKOV

STKUN

+/-

MRW

MCW

MSW

MAL

2-Stage

Prefetch

Pipeline

5-Stage

Pipeline

CP

IPIP

R15

R14

R14

Division Unit

Multiply Unit

MDC

PSW

MDH

ZEROS

Bit-Mask-Gen.

Barrel-Shifter

+/-

MDL

ONES

ALU

ADU

GPRs

RF

R1

R0

R1

R0

Buffer

WB

DMU

PSRAM

Flash/ROM

DPRAM

R15

R14

GPRs

R1

R0

DSRAM

EBC

Peripherals

mca04917_x.vsd

Figure 4 CPU Block Diagram

Data Sheet 25 V1.2, 2012-07




With this hardware most XE161xL instructions are executed in a single machine cycle of

12.5 ns @ 80-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle, no matter how many bits are shifted. Also, multiplication and most MAC instructions execute in one cycle. All multiple-cycle instructions have been optimized so that they can be executed very fast; for example, a

32-/16-bit division is started within 4 cycles while the remaining cycles are executed in the background. Another pipeline optimization, the branch target prediction, eliminates the execution time of branch instructions if the prediction was correct.

The CPU has a register context consisting of up to three register banks with 16 wordwide GPRs each at its disposal. One of these register banks is physically allocated within the on-chip DPRAM area. A Context Pointer (CP) register determines the base address of the active register bank accessed by the CPU at any time. The number of these register bank copies is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 32 Kwords is provided for storage of temporary data. The system stack can be allocated to any location within the address space (preferably in the on-chip

RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate

SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during each stack access to detect stack overflow or underflow.

The high performance of the CPU hardware implementation can be best utilized by the programmer with the highly efficient XE161xL instruction set. This includes the following instruction classes:

• Standard Arithmetic Instructions

• DSP-Oriented Arithmetic Instructions

• Logical Instructions

• Boolean Bit Manipulation Instructions

• Compare and Loop Control Instructions

• Shift and Rotate Instructions

• Prioritize Instruction

• Data Movement Instructions

• System Stack Instructions

• Jump and Call Instructions

• Return Instructions

• System Control Instructions

• Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

Data Sheet 26 V1.2, 2012-07




3.3

Memory Protection Unit (MPU)

The XE161xL’s Memory Protection Unit (MPU) protects user-specified memory areas from unauthorized read, write, or instruction fetch accesses. The MPU can protect the whole address space including the peripheral area. This completes established mechanisms such as the register security mechanism or stack overrun/underrun detection.

Four Protection Levels support flexible system programming where operating system, low level drivers, and applications run on separate levels. Each protection level permits different access restrictions for instructions and/or data.

Every access is checked (if the MPU is enabled) and an access violating the permission rules will be marked as invalid and leads to a protection trap.

A set of protection registers for each protection level specifies the address ranges and the access permissions. Applications requiring more than 4 protection levels can dynamically re-program the protection registers.

3.4

Memory Checker Module (MCHK)

The XE161xL’s Memory Checker Module calculates a checksum (fractional polynomial division) on a block of data, often called Cyclic Redundancy Code (CRC). It is based on a 32-bit linear feedback shift register and may, therefore, also be used to generate pseudo-random numbers.

The Memory Checker Module is a 16-bit parallel input signature compression circuitry which enables error detection within a block of data stored in memory, registers, or communicated e.g. via serial communication lines. It reduces the probability of error masking due to repeated error patterns by calculating the signature of blocks of data.

The polynomial used for operation is configurable, so most of the commonly used polynomials may be used. Also, the block size for generating a CRC result is configurable via a local counter. An interrupt may be generated if testing the current data block reveals an error.

An autonomous CRC compare circuitry is included to enable redundant error detection, e.g. to enable higher safety integrity levels.

The Memory Checker Module provides enhanced fault detection (beyond parity or ECC) for data and instructions in volatile and non volatile memories. This is especially important for the safety and reliability of embedded systems.

Data Sheet 27 V1.2, 2012-07




3.5

Interrupt System

The architecture of the XE161xL supports several mechanisms for fast and flexible response to service requests; these can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

Using a standard interrupt service the current program execution is suspended and a branch to the interrupt vector table is performed. With the PEC just one cycle is ‘stolen’ from the current CPU activity to perform the PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source pointer, the destination pointer, or both. An individual

PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. PEC services are particularly well suited to supporting the transmission or reception of blocks of data.

The XE161xL has eight PEC channels, each with fast interrupt-driven data transfer capabilities.

With a minimum interrupt response time of 7/11

1)

CPU clocks, the XE161xL can react quickly to the occurrence of non-deterministic events.

Interrupt Nodes and Source Selection

The interrupt system provides 64 physical nodes with separate control register containing an interrupt request flag, an interrupt enable flag and an interrupt priority bit field. Most interrupt sources are assigned to a dedicated node. A particular subset of interrupt sources shares a set of nodes. The source selection can be programmed using the interrupt source selection (ISSR) registers.

External Request Unit (ERU)

A dedicated External Request Unit (ERU) is provided to route and preprocess selected on-chip peripheral and external interrupt requests. The ERU features 4 programmable input channels with event trigger logic (ETL) a routing matrix and 4 output gating units

(OGU). The ETL features rising edge, falling edge, or both edges event detection. The

OGU combines the detected interrupt events and provides filtering capabilities depending on a programmable pattern match or miss.

Trap Processing

The XE161xL provides efficient mechanisms to identify and process exceptions or error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap causes an immediate system reaction similar to a standard interrupt service (branching

1) Depending if the jump cache is used or not.

Data Sheet 28 V1.2, 2012-07




to a dedicated vector table location). The occurrence of a hardware trap is also indicated by a single bit in the trap flag register (TFR). Unless another higher-priority trap service is in progress, a hardware trap will interrupt any ongoing program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.

Depending on the package option up to 3 External Service Request (ESR) pins are provided. The ESR unit processes their input values and allows to implement user controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup and power control can be efficiently realized.

Software interrupts are supported by the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. Alternatively to emulate an interrupt by software a program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an interrupt control register.

3.6

On-Chip Debug Support (OCDS)

The On-Chip Debug Support system built into the XE161xL provides a broad range of debug and emulation features. User software running on the XE161xL can be debugged within the target system environment.

The OCDS is controlled by an external debugging device via the debug interface. This consists of the 2-pin Device Access Port (DAP) or of the 1-pin Single Pin DAP (SPD) or of the JTAG port conforming to IEEE-1149. The debug interface can be completed with an optional break interface.

The debugger controls the OCDS with a set of dedicated registers accessible via the debug interface (SPD, DAP or JTAG). In addition the OCDS system can be controlled by the CPU, e.g. by a monitor program. An injection interface allows the execution of

OCDS-generated instructions by the CPU.

Multiple breakpoints can be triggered by on-chip hardware, by software, or by an external trigger input. Single stepping is supported, as is the injection of arbitrary instructions and read/write access to the complete internal address space. A breakpoint trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the activation of an external signal.

Tracing of data can be obtained via the debug interface, or via the external bus interface for increased performance.

Tracing of program execution is supported by the XE166 Family emulation device.

The SPD interface uses one interface signal, DAP interface uses two interface signals, the JTAG interface uses four interface signals, to communicate with external circuitry.

The debug interface can be amended with two optional break lines.

Data Sheet 29 V1.2, 2012-07




3.7

Capture/Compare Unit (CC2)

The CAPCOM unit supports generation and control of timing sequences on up to

16 channels with a maximum resolution of one system clock cycle (eight cycles in staggered mode). The CAPCOM unit is typically used to handle high-speed I/O tasks such as pulse and waveform generation, pulse width modulation (PWM), digital to analog (D/A) conversion, software timing, or time recording with respect to external events.

Two 16-bit timers with reload registers provide two independent time bases for the capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.

This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs allow event scheduling for the capture/compare registers relative to external events.

The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer and programmed for capture or compare function.

All registers have each one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event.

The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers.

When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.

Table 9 Compare Modes

Compare Modes Function

Mode 0

Mode 1

Interrupt-only compare mode;

Several compare interrupts per timer period are possible

Pin toggles on each compare match;

Several compare events per timer period are possible

Data Sheet 30 V1.2, 2012-07




Table 9

Compare Modes (cont’d)

Compare Modes

Mode 2

Function

Mode 3

Interrupt-only compare mode;

Only one compare interrupt per timer period is generated

Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;

Only one compare event per timer period is generated

Double Register

Mode

Single Event Mode

Two registers operate on one pin;

Pin toggles on each compare match;

Several compare events per timer period are possible

Generates single edges or pulses;

Can be used with any compare mode

When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin associated with this register. In addition, a specific interrupt request for this capture/compare register is generated.

Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event.

The contents of all registers selected for one of the five compare modes are continuously compared with the contents of the allocated timers.

When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the compare mode selected.

Data Sheet 31 V1.2, 2012-07




Reload Reg.

T7REL

f

CC

T7IN

T6OUF

CC16IO

CC17IO

CC31IO

f

CC

T6OUF

T7

Input

Control

Mode

Control

(Capture or

Compare)

T8

Input

Control

Timer T7 T7IRQ

CC16IRQ

CC17IRQ

Sixteen

16-bit

Capture/

Compare

Registers

Timer T8

CC31IRQ

T8IRQ

Figure 5 CAPCOM Unit Block Diagram

Reload Reg.

T8REL

MC_CAPCOM2_BLOCKDIAG

Data Sheet 32 V1.2, 2012-07




3.8

Capture/Compare Units CCU6x

The XE161xL types feature the CCU60 and CCU63 units.

CCU6 is a high-resolution capture and compare unit with application-specific modes. It provides inputs to start the timers synchronously, an important feature in devices with several CCU6 modules.

The module provides two independent timers (T12, T13), that can be used for PWM generation, especially for AC motor control. Additionally, special control modes for block commutation and multi-phase machines are supported.

Timer 12 Features

• Three capture/compare channels, where each channel can be used either as a capture or as a compare channel.

• Supports generation of a three-phase PWM (six outputs, individual signals for highside and low-side switches)

• 16-bit resolution, maximum count frequency = peripheral clock

• Dead-time control for each channel to avoid short circuits in the power stage

• Concurrent update of the required T12/13 registers

• Center-aligned and edge-aligned PWM can be generated

• Single-shot mode supported

• Many interrupt request sources

• Hysteresis-like control mode

• Automatic start on a HW event (T12HR, for synchronization purposes)

Timer 13 Features

• One independent compare channel with one output

• 16-bit resolution, maximum count frequency = peripheral clock

• Can be synchronized to T12

• Interrupt generation at period match and compare match

• Single-shot mode supported

• Automatic start on a HW event (T13HR, for synchronization purposes)

Additional Features

• Block commutation for brushless DC drives implemented

• Position detection via Hall sensor pattern

• Automatic rotational speed measurement for block commutation

• Integrated error handling

• Fast emergency stop without CPU load via external signal (CTRAP)

• Control modes for multi-channel AC drives

• Output levels can be selected and adapted to the power stage

Data Sheet 33 V1.2, 2012-07




f

SYS

TxHR

Interrupts

T12

Channel 0

Channel 1

Channel 2

CCU6 Module Kernel com pare

1

1

Deadtime

Control

Multichannel

Control

1

T13 st art

Channel 3

1 com pare

3 2 2 2

Input / Output Control

3

Trap

Control

1 m c_ccu6_blockdiagram . vsd

Figure 6 CCU6 Block Diagram

Timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. Timer T13 can work in compare mode only. The multi-channel control unit generates output patterns that can be modulated by timer T12 and/or timer

T13. The modulation sources can be selected and combined for signal modulation.

Data Sheet 34 V1.2, 2012-07




3.9

General Purpose Timer (GPT12E) Unit

The GPT12E unit is a very flexible multifunctional timer/counter structure which can be used for many different timing tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT12E unit incorporates five 16-bit timers organized in two separate modules,

GPT1 and GPT2. Each timer in each module may either operate independently in a number of different modes or be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation: Timer, Gated Timer, Counter, and Incremental

Interface Mode. In Timer Mode, the input clock for a timer is derived from the system clock and divided by a programmable prescaler. Counter Mode allows timer clocking in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes each timer has one associated port pin (TxIN) which serves as a gate or clock input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.

The counting direction (up/down) for each timer can be programmed by software or altered dynamically by an external signal on a port pin (TxEUD), e.g. to facilitate position tracking.

In Incremental Interface Mode the GPT1 timers can be directly connected to the incremental position sensor signals A and B through their respective inputs TxIN and

TxEUD. Direction and counting signals are internally derived from these two input signals, so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components. It may also be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.

In addition to the basic operating modes, T2 and T4 may be configured as reload or capture register for timer T3. A timer used as capture or reload register is stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at the associated input pin (TxIN). Timer T3 is reloaded with the contents of T2 or T4, triggered either by an external signal or a selectable state transition of its toggle latch T3OTL. When both

T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be continuously generated without software intervention.

Note: Signals T2IN, T2EUD, T4EUD, T6OUT, T6IN and T6EUD are not connected to pins.

Data Sheet 35 V1.2, 2012-07




T3CON.BPS1

f

GPT

T2IN

T2EUD

2 n

:1 Basic Clock

U/D

T2

Mode

Control

Reload

Capture

Aux. Timer T2

T3IN

T3EUD

Interrupt

Request

(T2IRQ)

T3

Mode

Control

U/D

Core Timer T3 T3OTL

Toggle

Latch

Interrupt

Request

(T3IRQ)

T3OUT

T4IN

T4EUD

Capture

T4

Mode

Control

Reload

Aux. Timer T4

U/D

Interrupt

Request

(T4IRQ)

MC_GPT_BLOCK1

Figure 7 Block Diagram of GPT1

Data Sheet 36 V1.2, 2012-07




With its maximum resolution of 2 system clock cycles, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The counting direction (up/down) for each timer can be programmed by software or altered dynamically with an external signal on a port pin (TxEUD). Concatenation of the timers is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, and/or it may be output on pin

T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2 timers and to initiate a reload from the CAPREL register.

The CAPREL register can capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared after the capture procedure. This allows the XE161xL to measure absolute time differences or to perform pulse multiplication without software overhead.

The capture trigger (timer T5 to CAPREL) can also be generated upon transitions of

GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.

Data Sheet 37 V1.2, 2012-07




T6CON.BPS2

f

GPT

T5IN

T5EUD

2 n

:1

T5

Mode

Control

Basic Clock

GPT2 Timer T5

U/D

Clear

Interrupt

Request

(T5IRQ)

CAPIN

T3IN/

T3EUD

T6IN

T6EUD

Capture

CAPREL

Mode

Control

GPT2 CAPREL

Reload

Clear

T6

Mode

Control

U/D

GPT2 Timer T6

Interrupt

Request

(CRIRQ)

Interrupt

Request

(T6IRQ)

Toggle

FF

T6OTL

T6OUT

T6OUF

MC_GPT_BLOCK2

Figure 8 Block Diagram of GPT2

Data Sheet 38 V1.2, 2012-07




3.10

Real Time Clock

The Real Time Clock (RTC) module of the XE161xL can be clocked with a clock signal selected from internal sources or external sources (pins).

The RTC basically consists of a chain of divider blocks:

• Selectable 32:1 and 8:1 dividers (on - off)

• The reloadable 16-bit timer T14

• The 32-bit RTC timer block (accessible via registers RTCH and RTCL) consisting of:

– a reloadable 10-bit timer




All timers count up. Each timer can generate an interrupt request. All requests are combined to a common node request.

f

RTC

RUN

M UX

: 8

M UX

PRE REFCLK

T14REL 10 Bits

CNT

INT0

Interrupt Sub Node

CNT

INT1

CNT

INT2

REL-Register

6 Bits 6 Bits

RTCINT

CNT

INT3

10 Bits

f

CNT

T14

T14-Register

10 Bits 6 Bits 6 Bits

CNT-Register

10 Bits

M CB05568B

Figure 9 RTC Block Diagram

Note: The registers associated with the RTC are only affected by a power reset.

Data Sheet 39 V1.2, 2012-07




The RTC module can be used for different purposes:

• System clock to determine the current time and date

• Cyclic time-based interrupt, to provide a system time tick independent of CPU frequency and other resources

• 48-bit timer for long-term measurements

• Alarm interrupt at a defined time

Data Sheet 40 V1.2, 2012-07




3.11

A/D Converters

For analog signal measurement, a 12-bit A/D converters (ADC0) with 10 multiplexed input channels and a sample and hold circuit have been integrated on-chip. Conversions use the successive approximation method. The sample time (to charge the capacitors) and the conversion time are programmable so that they can be adjusted to the external circuit. The A/D converters can also operate in 8-bit and 10-bit conversion mode, further reducing the conversion time.

Several independent conversion result registers, selectable interrupt requests, and highly flexible conversion sequences provide a high degree of programmability to meet the application requirements.

For applications that require more analog input channels, external analog multiplexers can be controlled automatically. For applications that require fewer analog input channels, the remaining channel inputs can be used as digital input port pins.

The A/D converters of the XE161xL support two types of request sources which can be triggered by several internal and external events.

• Parallel requests are activated at the same time and then executed in a predefined sequence.

• Queued requests are executed in a user-defined sequence.

In addition, the conversion of a specific channel can be inserted into a running sequence without disturbing that sequence. All requests are arbitrated according to the priority level assigned to them.

Data reduction features reduce the number of required CPU access operations allowing the precise evaluation of analog inputs (high conversion rate) even at a low CPU speed.

Result data can be reduced by limit checking or accumulation of results. Two cascadable filters build the hardware to generate a configurable moving average.

The Peripheral Event Controller (PEC) can be used to control the A/D converters or to automatically store conversion results to a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer.

Each A/D converter contains eight result registers which can be concatenated to build a result FIFO. Wait-for-read mode can be enabled for each result register to prevent the loss of conversion data.

In order to decouple analog inputs from digital noise and to avoid input trigger noise, those pins used for analog input can be disconnected from the digital input stages. This can be selected for each pin separately with the Port x Digital Input Disable registers.

The Auto-Power-Down feature of the A/D converters minimizes the power consumption when no conversion is in progress.

Broken wire detection for each channel and a multiplexer test mode provide information to verify the proper operation of the analog signal sources (e.g. a sensor system).

Data Sheet 41 V1.2, 2012-07




3.12

Universal Serial Interface Channel Modules (USIC)

The XE161xL features the USIC modules USIC0 and USIC1. Each module provides two serial communication channels.

The Universal Serial Interface Channel (USIC) module is based on a generic data shift and data storage structure which is identical for all supported serial communication protocols. Each channel supports complete full-duplex operation with a basic data buffer structure (one transmit buffer and two receive buffer stages). In addition, the data handling software can use FIFOs.

The protocol part (generation of shift clock/data/control signals) is independent of the general part and is handled by protocol-specific preprocessors (PPPs).

The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and outputs of each USIC channel can be assigned to different interface pins, providing great flexibility to the application software. All assignments can be made during runtime.

Bus Buffer & Shift Structure Protocol Preprocessors

Control 0

DBU

0

DSU

0

PPP_A

PPP_B

PPP_C

PPP_D

Pins

Control 1

DBU

1

DSU

1

PPP_A

PPP_B

PPP_C

PPP_D f sys

Fractional

Dividers

Baud rate

Generators

USIC_basic.vsd

Figure 10 General Structure of a USIC Module

The regular structure of the USIC module brings the following advantages:

• Higher flexibility through configuration with same look-and-feel for data management

• Reduced complexity for low-level drivers serving different protocols

• Wide range of protocols with improved performances (baud rate, buffer handling)

Data Sheet 42 V1.2, 2012-07




Target Protocols

Each USIC channel can receive and transmit data frames with a selectable data word width from 1 to 16 bits in each of the following protocols:

• UART (asynchronous serial channel)

– module capability: maximum baud rate =

f

SYS

/ 4

– data frame length programmable from 1 to 63 bits

– MSB or LSB first

• LIN Support (Local Interconnect Network)


f

SYS

/ 16

– checksum generation under software control

– baud rate detection possible by built-in capture event of baud rate generator

• SSC/SPI (synchronous serial channel with or without data buffer)


f

SYS

/ 2, limited by loop delay

– number of data bits programmable from 1 to 63, more with explicit stop condition

– MSB or LSB first

– optional control of slave select signals

• IIC (Inter-IC Bus)

– supports baud rates of 100 kbit/s and 400 kbit/s

• IIS (Inter-IC Sound Bus)


f

SYS

/ 2

Note: Depending on the selected functions (such as digital filters, input synchronization stages, sample point adjustment, etc.), the maximum achievable baud rate can be limited. Please note that there may be additional delays, such as internal or external propagation delays and driver delays (e.g. for collision detection in UART mode, for IIC, etc.).

Data Sheet 43 V1.2, 2012-07




3.13

MultiCAN Module

The MultiCAN module contains two independently operating CAN nodes with Full-CAN functionality which are able to exchange Data and Remote Frames using a gateway function. Transmission and reception of CAN frames is handled in accordance with CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.

The two CAN nodes share a common set of message objects. Each message object can be individually allocated to either of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to set up a FIFO buffer.

The message objects are organized in double-chained linked lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to its own message object list and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations.

Clock

Control

f

CAN

Address

Decoder

Interrupt

Control

MultiCAN Module Kernel

CAN

Node n

TXDCn

RXDCn

Message

Object

Buffer

Linked

List

Control

Port

Control

CAN

Node 0

TXDC0

RXDC0

CAN Control mc_multican_block.vsd

Figure 11 Block Diagram of MultiCAN Module

Data Sheet 44 V1.2, 2012-07




MultiCAN Features

• CAN functionality conforming to CAN specification V2.0 B active for each CAN node

(compliant to ISO 11898)

• Independent CAN nodes

• Set of independent message objects (shared by the CAN nodes)

• Dedicated control registers for each CAN node

• Data transfer rate up to 1 Mbit/s, individually programmable for each node

• Flexible and powerful message transfer control and error handling capabilities

• Full-CAN functionality for message objects:

– Can be assigned to one of the CAN nodes

– Configurable as transmit or receive objects, or as message buffer FIFO

– Handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering

– Remote Monitoring Mode, and frame counter for monitoring

• Automatic Gateway Mode support

• 16 individually programmable interrupt nodes

• Analyzer mode for CAN bus monitoring

3.14

System Timer

The System Timer consists of a programmable prescaler and two concatenated timers

(10 bits and 6 bits). Both timers can generate interrupt requests. The clock source can be selected and the timers can also run during power reduction modes.

Therefore, the System Timer enables the software to maintain the current time for scheduling functions or for the implementation of a clock.

3.15

Window Watchdog Timer

The Window Watchdog Timer is one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time.

The Window Watchdog Timer is always enabled after an application reset of the chip. It can be disabled and enabled at any time by executing the instructions DISWDT and

ENWDT respectively. The software has to service the Window Watchdog Timer before it overflows. If this is not the case because of a hardware or software failure, the Window

Watchdog Timer overflows, generating a reset request.

The Window Watchdog Timer has a ‘programmable window boundary’, it disallows refresh during the Window Watchdog Timer’s count-up. A refresh during this windowboundary will cause the Window Watchdog Timer to also generate a reset request.

The Window Watchdog Timer is a 16-bit timer clocked with either the system clock or the independent wake-up oscillator clock, divided by 16,384 or 256. The Window Watchdog

Timer register is set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the Window Watchdog Timer is reloaded.

Data Sheet 45 V1.2, 2012-07




When clocked by

f

SYS

= 80 MHz, time intervals between 12.5 ns and 13.4 s can be monitored.

When clocked by

f

WU

= 500 kHz, time intervals between 2.0 µs and 2147.5 s can be monitored.

The default Watchdog Timer interval after power-up is 0.13 s (@

f

WU

= 500 kHz).

3.16

Clock Generation

The Clock Generation Unit can generate the system clock signal

f

SYS

for the XE161xL from a number of external or internal clock sources:

• External clock signals with pad voltage or core voltage levels

• External crystal or resonator using the on-chip oscillator

• On-chip clock source for operation without crystal/resonator

• Wake-up clock (ultra-low-power) to further reduce power consumption

The programmable on-chip PLL with multiple prescalers generates a clock signal for maximum system performance from standard crystals, a clock input signal, or from the on-chip clock source. See also

Section 4.7.2

.

The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency falls below a certain limit or stops completely. In this case, the system can be supplied with an emergency clock to enable operation even after an external clock failure.

All available clock signals can be output on the EXTCLK pin.

Data Sheet 46 V1.2, 2012-07




3.17

Parallel Ports

The XE161xL provides up to 33 I/O lines which are organized into 3 input/output ports and 1 input port. All port lines are bit-addressable, and all input/output lines can be individually (bit-wise) configured via port control registers. This configuration selects the direction (input/output), push/pull or open-drain operation, activation of pull devices, and edge characteristics (shape) and driver characteristics (output current) of the port drivers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs without pull devices active.

All port lines have alternate input or output functions associated with them. These alternate functions can be programmed to be assigned to various port pins to support the best utilization for a given application. For this reason, certain functions appear several

times in

Table 10

.

All port lines that are not used for alternate functions may be used as general purpose

I/O lines.

Table 10

Group

P2

P5

P6

P10

Summary of the XE161xL’s Ports

Width I/O Connected Modules

12

6 I

I/O Analog inputs, ADC, CAN, CC2, CCU6, DAP/JTAG,

GPT12E, SCU, USIC

Analog inputs, CCU6, JTAG, GPT12E, CC2

3

12

I/O

I/O

Analog inputs, ADC, CCU6, JTAG, GPT12E, USIC

CAN, CCU6, GPT12E, DAP/JTAG, SPD, USIC

Data Sheet 47 V1.2, 2012-07




3.18

Power Management

The XE161xL provides the means to control the power it consumes either at a given time or averaged over a certain duration.

Two mechanisms can be used (and partly in parallel):

• Clock Generation Management controls the frequency of internal and external clock signals. Clock signals for currently inactive parts of logic are disabled automatically. The user can drastically reduce the consumed power by reducing the

XE161xL system clock frequency.

External circuits can be controlled using the programmable frequency output

EXTCLK.

• Peripheral Management permits temporary disabling of peripheral modules. Each peripheral can be disabled and enabled separately. The CPU can be switched off while the peripherals can continue to operate.

Wake-up from power reduction modes can be triggered either externally with signals generated by the external system, or internally by the on-chip wake-up timer. This supports intermittent operation of the XE161xL by generating cyclic wake-up signals.

Full performance is available to quickly react to action requests while the intermittent sleep phases greatly reduce the average system power consumption.

Note: When selecting the supply voltage and the clock source and generation method, the required parameters must be carefully written to the respective bit fields, to avoid unintended intermediate states. Recommended sequences are provided which ensure the intended operation of power supply system and clock system.

Please refer to the Programmer’s Guide.

Data Sheet 48 V1.2, 2012-07




3.19

Instruction Set Summary

Table 11

lists the instructions of the XE161xL.

The addressing modes that can be used with a specific instruction, the function of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “Instruction Set Manual”.

This document also provides a detailed description of each instruction.

Table 11

Mnemonic

ADD(B)

ADDC(B)

SUB(B)

SUBC(B)

MUL(U)

Instruction Set Summary

Description

Add word (byte) operands

Add word (byte) operands with Carry

Bytes

2 / 4

2 / 4

Subtract word (byte) operands

Subtract word (byte) operands with Carry

(Un)Signed multiply direct GPR by direct GPR

(16-

× 16-bit)

2

(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

2 / 4

2 / 4

DIV(U)

DIVL(U)

CPL(B)

NEG(B)

AND(B)

OR(B)

XOR(B)

BCLR/BSET

BMOV(N)

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

Complement direct word (byte) GPR 2

Negate direct word (byte) GPR

Bitwise AND, (word/byte operands)

2

2 / 4

Bitwise OR, (word/byte operands)

Bitwise exclusive OR, (word/byte operands)

Clear/Set direct bit

Move (negated) direct bit to direct bit

2 / 4

2 / 4

2

4

BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit

BCMP Compare direct bit to direct bit

BFLDH/BFLDL

CMP(B)

CMPD1/2

CMPI1/2

PRIOR

SHL/SHR

4

4

Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data

Compare word (byte) operands

Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR

Shift left/right direct word GPR

4

2 / 4

Compare word data to GPR and decrement GPR by 1/2 2 / 4

Compare word data to GPR and increment GPR by 1/2 2 / 4

2

2

Data Sheet 49 V1.2, 2012-07




Table 11

Mnemonic

ROL/ROR

ASHR

MOV(B)

MOVBS/Z

Instruction Set Summary (cont’d)

Description Bytes

Rotate left/right direct word GPR

Arithmetic (sign bit) shift right direct word GPR

2

2

Move word (byte) data 2 / 4

Move byte operand to word op. with sign/zero extension 2 / 4

JMPA/I/R

JMPS

JB(C)

JNB(S)

CALLA/I/R

CALLS

PCALL

TRAP

PUSH/POP

SCXT

Jump absolute/indirect/relative if condition is met

Jump absolute to a code segment

Jump relative if direct bit is set (and clear bit)

Jump relative if direct bit is not set (and set bit)

Call absolute/indirect/relative subroutine if condition is met 4

Call absolute subroutine in any code segment 4

Push direct word register onto system stack and call absolute subroutine

4

Call interrupt service routine via immediate trap number 2

Push/pop direct word register onto/from system stack

Push direct word register onto system stack and update register with word operand

2

4

4

4

4

4

2 RET(P) Return from intra-segment subroutine

(and pop direct word register from system stack)

Return from inter-segment subroutine RETS

RETI

SBRK

Return from interrupt service subroutine

Software Break

Software Reset SRST

IDLE

PWRDN

SRVWDT

Enter Idle Mode

Unused instruction

1)

Service Watchdog Timer

DISWDT/ENWDT Disable/Enable Watchdog Timer

EINIT End-of-Initialization Register Lock

ATOMIC

EXTR

Begin ATOMIC sequence

Begin EXTended Register sequence

EXTP(R)

EXTS(R)

Begin EXTended Page (and Register) sequence

Begin EXTended Segment (and Register) sequence

4

4

4

4

2

2

2

4

4

2

2

2 / 4

2 / 4

Data Sheet 50 V1.2, 2012-07




Table 11

Mnemonic

Instruction Set Summary (cont’d)

NOP

CoMUL/CoMAC

CoADD/CoSUB

Co(A)SHR

Description

Null operation

Multiply (and accumulate)

Add/Subtract

(Arithmetic) Shift right

CoSHL Shift left

CoLOAD/STORE Load accumulator/Store MAC register

CoCMP

CoMAX/MIN

Compare

Maximum/Minimum

CoABS/CoRND

CoMOV

Absolute value/Round accumulator

Data move

4

4

CoNEG/NOP Negate accumulator/Null operation 4

1) The Enter Power Down Mode instruction is not used in the XE161xL, due to the enhanced power control scheme. PWRDN will be correctly decoded, but will trigger no action.

4

4

4

4

Bytes

2

4

4

4

Data Sheet 51 V1.2, 2012-07



Electrical Parameters

4 Electrical Parameters

The operating range for the XE161xL is defined by its electrical parameters. For proper operation the specified limits must be respected when integrating the device in its target environment.

4.1

General Parameters

These parameters are valid for all subsequent descriptions, unless otherwise noted.

Table 12 Absolute Maximum Rating Parameters

Parameter Symbol Values Unit Note /

Test Condition

Output current on a pin when high value is driven

I

Min.

Typ.

Max.

OH

SR -15

− − mA

Output current on a pin when low value is driven

I

OL

SR

− −

15 mA

Overload current

Absolute sum of overload currents

I

OV

SR -5

Σ|

I

SR

OV

|

−

−

−

5

50 mA

1) mA

1)

Junction Temperature

Storage Temperature

T

J

SR -40

T

ST

SR -65

V

DDP

SR -0.5

−

−

−

150

150

°C

°C

Digital supply voltage for

IO pads and voltage regulators

6.0

V

Voltage on any pin with respect to ground (Vss)

V

IN

SR -0.5

−

V

DDP

+

0.5

V

V

IN

≤

V

DDP(max)

1) Overload condition occurs if the input voltage

V

IN

is out of the absolute maximum rating range. In this case the current must be limited to the listed values by design measures.

Note: Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for an extended time may affect device reliability.

During absolute maximum rating overload conditions (

V

IN

>

V

DDP

or

V

IN

<

V

SS

) the voltage on V

DDP

pins with respect to ground ( V

SS

) must not exceed the values defined by the absolute maximum ratings.

Data Sheet 52 V1.2, 2012-07




4.1.1

Operating Conditions

The following operating conditions must not be exceeded to ensure correct operation of the XE161xL. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed.

Note: Typical parameter values refer to room temperature and nominal supply voltage, minimum/maximum parameter values also include conditions of minimum/maximum temperature and minimum/maximum supply voltage.

Additional details are described where applicable.

Table 13

Parameter

Operating Conditions

Voltage Regulator Buffer

Capacitance for DMP_M

External Load

Capacitance

Symbol Values

C

EVRM

SR

C

L

SR

−

Min.

Typ.

Max.

1.0

−

4.7

20

3)

−

Unit Note /

Test Condition

μF

1)2)

System frequency

Overload current for analog inputs

6)

f

SYS

I

OVA

SR

−

SR -2

−

−

80

5 pF pin out driver= default

4)

MHz

5) mA not subject to production test

Overload current for digital

inputs

6)

I

OVD

SR -5

−

5 mA not subject to production test

Overload current coupling factor for analog inputs

7)

K

OVA

CC

−

2.5 x

10

-4

1.5 x

10

-3

-

I

OV

< 0 mA; not subject to production test

−

1.0 x

10

-6

1.0 x

10

-4

-

I

OV

> 0 mA; not subject to production test

Data Sheet 53 V1.2, 2012-07




Table 13

Parameter

Operating Conditions (cont’d)

Symbol Values

Overload current coupling factor for digital I/O pins

K

OVD

CC

Min.

Typ.

Max.

−

1.0 x

10

-2

3.0 x

10

-2

Unit Note /

Test Condition

I

OV

< 0 mA; not subject to production test

−

1.0 x

10

-4

5.0 x

10

-3

I

OV

> 0 mA; not subject to production test

Absolute sum of overload currents

Σ|

I

OV

|

SR

− −

30 mA not subject to production test

Digital core supply voltage for domain M

8)

V

DDIM

CC

−

1.5

−

V



V

DDP

SR 3.0

−

5.5

V

Digital ground voltage

V

SS

SR

−

0

−

V

1) To ensure the stability of the voltage regulators the EVRs must be buffered with ceramic capacitors. Separate buffer capacitors with the recomended values shall be connected as close as possible to each

V

DDIM

pin to keep the resistance of the board tracks below 2 Ohm. Connect all

V

DDIM

pins together. The minimum capacitance value is required for proper operation under all conditions (e.g. temperature). Higher values slightly increase the startup time.

2) Use one Capacitor for each pin.

3) This is the reference load. For bigger capacitive loads, use the derating factors listed in the PAD properties section.

4) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output current may lead to increased delays or reduced driving capability (

C

L

).

5) The operating frequency range may be reduced for specific device types. This is indicated in the device designation (...FxxL). 66 MHz devices are marked ...F66L.

6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range:

V

OV

>

V

IHmax

(

I

OV

> 0) or

V

OV

<

V

ILmin

((

I

OV

< 0). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified limits. Proper operation under overload conditions depends on the application. Overload conditions must not occur on pin XTAL1.

7) An overload current (

I

OV

) through a pin injects a certain error current ( current adds to the respective pins leakage current (

I

I

INJ

) into the adjacent pins. This error

OZ

). The amount of error current depends on the overload current and is defined by the overload coupling factor

K

OV

. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it.The total current through a pin is |

I

TOT

| = |

I

OZ

|

+ (|

I

OV

|

K

OV

). The additional error current may distort the input voltage on analog inputs.

Data Sheet 54 V1.2, 2012-07




8) Value is controlled by on-chip regulator.

4.2

Voltage Range definitions

The XE161xL timing depends on the supply voltage. If such a dependency exists the timing values are given for 2 voltage areas commonly used. The voltage areas are defined in the following tables.

Table 14

Parameter

Upper Voltage Range Definition



Symbol Values

V

DDP

Min.

Typ.

Max.

SR 4.5

5.0

5.5

Unit Note /

Test Condition

V

Table 15

Parameter

Lower Voltage Range Definition

Symbol Values



Min.

Typ.

Max.

V

DDP

SR 3.0

3.3

4.5

Unit Note /

Test Condition

V

4.2.1

Parameter Interpretation

The parameters listed in the following include both the characteristics of the XE161xL and its demands on the system. To aid in correctly interpreting the parameters when evaluating them for a design, they are marked accordingly in the column “Symbol”:

CC (Controller Characteristics):

The logic of the XE161xL provides signals with the specified characteristics.

SR (System Requirement):

The external system must provide signals with the specified characteristics to the

XE161xL.

Data Sheet 55 V1.2, 2012-07




4.3

DC Parameters

These parameters are static or average values that may be exceeded during switching transitions (e.g. output current).

The XE161xL can operate within a wide supply voltage range from 3.0 V to 5.5 V.

However, during operation this supply voltage must remain within 10 percent of the selected nominal supply voltage. It cannot vary across the full operating voltage range.

Because of the supply voltage restriction and because electrical behavior depends on the supply voltage, the parameters are specified separately for the upper and the lower voltage range.

During operation, the supply voltages may only change with a maximum speed of dV/dt < 1 V/ms.

Leakage current is strongly dependent on the operating temperature and the voltage level at the respective pin. The maximum values in the following tables apply under worst case conditions, i.e. maximum temperature and an input level equal to the supply voltage.

The value for the leakage current in an application can be determined by using the respective leakage derating formula (see tables) with values from that application.

The pads of the XE161xL are designed to operate in various driver modes. The DC parameter specifications refer to the pad current limits specified in

Section 4.7.4

.

Data Sheet 56 V1.2, 2012-07




Pullup/Pulldown Device Behavior

Most pins of the XE161xL feature pullup or pulldown devices. For some special pins these are fixed; for the port pins they can be selected by the application.

The specified current values indicate how to load the respective pin depending on the intended signal level.

Figure 12

shows the current paths.

The shaded resistors shown in the figure may be required to compensate system pull currents that do not match the given limit values.

V

DDP

Pullup

Pulldown

V

SS

Figure 12 Pullup/Pulldown Current Definition

MC_XC2X_PULL

Data Sheet 57 V1.2, 2012-07




4.3.1

DC Parameters for Upper Voltage Area

Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current

I

OV

.

Note: Operating Conditions apply.

Table 16

is valid under the following conditions:

V

DDP

≤ 5.5 V;

V

DDP typ. 5 V;

V

DDP

≥ 4.5 V

Table 16

Parameter

DC Characteristics for Upper Voltage Range

Pin capacitance (digital inputs/outputs).

Symbol Values

C

Min.

Typ.

Max.

IO

CC

− −

10

Unit Note /

Test Condition

pF not subject to production test

Input Hysteresis

1)

Absolute input leakage current on pins of analog ports

2)

Absolute input leakage current for all other pins.

2)3)

|

HYS CC 0.11 x

I

OZ1

|

CC

|

I

OZ2

|

CC

V

DDP

−

−

−

10

0.2

−

0.2

−

200

5

10

V nA

μA

μA

R

S

= 0 Ohm

Pull Level Force Current

4)

Pull Level Keep Current

5)

|

I

PLF

| SR 220

|

I

PLK

|

SR

−

−

−

−

30

μA

μA

V

IN

>

V

IN

<

V

SS

V

DDP

;

T

J

≤ 110 °C;

V

IN

>

V

SS

;

V

IN

<

V

DDP

T

J

≤ 150 °C;

V

V

IN

>

IN

<

V

SS

V

DDP

;

V

IN

≥

V

IHmin

(pulldown_ena bled)

;

V

IN

≤

V

ILmax

(pullup_enable d)

V

IN

≥

V

IHmin

(pullup_enable d);

V

IN

≤

V

ILmax


Input high voltage (all except XTAL1)

V

IH

SR 0.7 x

V

DDP

−

V

DDP

+

0.3

V

Data Sheet 58 V1.2, 2012-07




Table 16

DC Characteristics for Upper Voltage Range (cont’d)


Test Condition

Input low voltage

(all except XTAL1)

Output High voltage

6)

V

V

IL

SR -0.3

OH

CC

Min.

Typ.

Max.

V

DDP

-

1.0

−

−

0.3 x

V

DDP

−

V

DDP

-

0.4

− −

V

V

V

I

I

OH

≥

OH

≥

I

OHmax

I

OHnom

7)

Output Low Voltage

6)

V

OL

CC

−

−

−

−

0.4

1.0

V

V

I

OL

≤

I

OL

≤

I

OLnom

I

OLmax

8)

1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions.

2) If the input voltage exceeds the respective supply voltage due to ground bouncing (

V

IN

<

V

SS

) or supply ripple

(

V

IN

>

V

DDP

), a certain amount of current may flow through the protection diodes. This current adds to the leakage current. An additional error current (

I

INJ

) will flow if an overload current flows through an adjacent pin.

Please refer to the definition of the overload coupling factor

K

OV

.

3) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (

T

J

= junction temperature [°C]):

I

OZ

= 0.05 x e

(1.5 + 0.028 x TJ>)

[

μA]. For example, at a temperature of 95 °C the resulting leakage current is 3.2

μA. Leakage derating depending on voltage level

(DV =

V

DDP

-

V

PIN

[V]):

I

OZ

=

I

OZtempmax

- (1.6 x DV) (

μA]. This voltage derating formula is an approximation which applies for maximum temperature.

4) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device.

5) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level.

6) The maximum deliverable output current of a port driver depends on the selected output driver mode. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is determined by the external circuit.

7) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,

VOH->VDDP). However, only the levels for nominal output currents are verified.

8) As a rule, with decreasing output current the output levels approach the respective supply level (

V

OL

->

V

SS

,

V

OH

->

V

DDP

). However, only the levels for nominal output currents are verified.

Data Sheet 59 V1.2, 2012-07




4.3.2

DC Parameters for Lower Voltage Area

Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current

I

OV

.


Table 17


V

DDP

V

DDP

≤ 4.5 V

≥ 3.0 V;

V

DDP typ. 3.3 V;

Table 17

Parameter

DC Characteristics for Lower Voltage Range

Symbol Values

Pin capacitance (digital inputs/outputs).

C

Min.

Typ.

Max.

IO

CC

− −

10

Unit Note /

Test Condition


Input Hysteresis

1)

Absolute input leakage current on pins of analog ports

2)

Absolute input leakage current for all other pins.

2)3)

|

HYS CC 0.07 x

I

OZ1

|

CC

|

I

OZ2

|

CC

V

DDP

−

−

−

10

0.2

−

0.2

Pull Level Force Current

4)

Pull Level Keep Current

5)

|

I

PLF

| SR 150

|

I

PLK

|

SR

−

−

−

−

200

2

6

−

10

V nA

μA

μA

μA

μA

R

S

= 0 Ohm

V

IN

>

V

IN

<

V

SS

V

DDP

;

T

J

≤ 110 °C;

V

V

IN

>

IN

<

V

SS

V

DDP

;

T

J

≤ 150 °C;

V

IN

>

V

SS

;

V

IN

<

V

DDP

V

IN

≥

V

IHmin


;

V

IN

≤

V

ILmax

(pullup_enable d)

;

V

IN

≥

V

IHmin

(pullup_enable d);

V

IN

≤

V

ILmax


Data Sheet 60 V1.2, 2012-07




Table 17

DC Characteristics for Lower Voltage Range (cont’d)

Parameter

Input low voltage

(all except XTAL1)

Output High voltage

6)

Symbol Values Unit Note /

Test Condition

Input high voltage (all except XTAL1)

V

IH

Min.

Typ.

Max.

SR 0.7 x

V

DDP

−

V

DDP

0.3

+

V

IL

SR -0.3

−

V

OH

CC

V

DDP

-

1.0

−

0.3 x

V

DDP

−

− −

V

OL

CC

−

−

V

DDP

-

0.4

−

−

0.4

1.0

V

V

V

V

I

I

OH

≥

OH

≥

I

OHmax

I

OHnom

7)

Output Low Voltage

6)

V

V

I

OL

≤

I

OL

≤

I

OLnom

I

OLmax

8)

1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot suppress switching due to external system noise under all conditions.

2) If the input voltage exceeds the respective supply voltage due to ground bouncing (

V

IN

<

V

SS

) or supply ripple

(

V

IN

>

V

DDP

), a certain amount of current may flow through the protection diodes. This current adds to the leakage current. An additional error current (

I

INJ

) will flow if an overload current flows through an adjacent pin.

Please refer to the definition of the overload coupling factor

K

OV

.

3) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (

V V I

T

J

I

= junction temperature [°C]):

I

OZ

= 0.05 x e

(1.5 + 0.028 x TJ>)

[

μA]. For example, at a temperature of 95 °C the resulting leakage current is 3.2

μA. Leakage derating depending on voltage level

(DV =

DDP

-

PIN

[V]):

OZ

=

OZtempmax

- (1.6 x DV) (

μA]. This voltage derating formula is an approximation which applies for maximum temperature.

4) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device.

5) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level.

6) The maximum deliverable output current of a port driver depends on the selected output driver mode. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is determined by the external circuit.

7) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,

VOH->VDDP). However, only the levels for nominal output currents are verified.

8) As a rule, with decreasing output current the output levels approach the respective supply level (

V

OL

->

V

SS

,

V

OH

->

V

DDP

). However, only the levels for nominal output currents are verified.

Data Sheet 61 V1.2, 2012-07




4.3.3

Power Consumption

The power consumed by the XE161xL depends on several factors such as supply voltage, operating frequency, active circuits, and operating temperature. The power consumption specified here consists of two components:

• The switching current

I

S

depends on the device activity

• The leakage current

I

LK

depends on the device temperature

To determine the actual power consumption, always both components, switching current

I

S

and leakage current

I

LK

must be added:

I

DDP

=

I

S

+

I

LK

.

Note: The power consumption values are not subject to production test. They are verified by design/characterization.

To determine the total power consumption for dimensioning the external power supply, also the pad driver currents must be considered.

The given power consumption parameters and their values refer to specific operating conditions:

• Active mode:

Regular operation, i.e. peripherals are active, code execution out of Flash.

• Stopover mode:

Crystal oscillator and PLL stopped, Flash switched off, clock in most parts of domain

DMP_M stopped.

Note: The maximum values cover the complete specified operating range of all manufactured devices.

The typical values refer to average devices under typical conditions, such as nominal supply voltage, room temperature, application-oriented activity.

After a power reset, the decoupling capacitors for

V

DDIM

are charged with the maximum possible current.

For additional information, please refer to

Section 5.2

,

Thermal Considerations

.


Data Sheet 62 V1.2, 2012-07




Table 18 Switching Power Consumption


Test Condition

Power supply current

(active) with all peripherals active and EVVRs on

I

SACT

CC

Min.

Typ.

Max.

−

6 + 0.5 x

f

SYS

1)

8 +

0.75 x

f

SYS

1)

mA power_mode= active ; voltage_range= both

2)3)4)

Power supply current in stopover mode, EVVRs on

I

SSO

CC

−

0.7

2.0

mA power_mode= stopover ; voltage_range= both

1)

f

SYS

in MHz

2) The pad supply voltage pins (

V

DDPB

) provide the input current for the on-chip EVVRs and the current consumed by the pin output drivers. A small current is consumed because the drivers input stages are switched.

3) Please consider the additional conditions described in section "Active Mode Power Supply Current".

4) The pad supply voltage only has a minor influence on this parameter.

Active Mode Power Supply Current

The actual power supply current in active mode not only depends on the system frequency but also on the configuration of the XE161xL’s subsystem.

Besides the power consumed by the device logic the power supply pins also provide the current that flows through the pin output drivers.

A small current is consumed because the drivers’ input stages are switched.

Data Sheet 63 V1.2, 2012-07




30

20

10

80

70

60

50

40

I

S

[mA]

I

I

SACTmax

SACTtyp

20 40 60 80

f

SYS

[MHz]

MC_XC2XL_IS

Figure 13 Supply Current in Active Mode as a Function of Frequency


Table 19 Leakage Power Consumption


Test Condition

Leakage supply current

1)2)

Min.

Typ.

Max.

I

LK1

CC

−

−

−

−

0.03

0.4

1.7

3.5

0.04

1.1

4.9

10.7

mA mA mA mA

T

J

= 25 °C

T

J

= 85 °C

T

J

= 125 °C

T

J

= 150 °C

1) The supply current caused by leakage depends mainly on the junction temperature and the supply voltage.

The temperature difference between the junction temperature

T

J

and the ambient temperature

T

A

must be taken into account. As this fraction of the supply current does not depend on device activity, it must be added to other power consumption values.

2) All inputs (including pins configured as inputs) are set at 0 V to 0.1 V or at

V

DDP

- 0.1 V to

(including pins configured as outputs) are disconnected.

V

DDP

and all outputs

Data Sheet 64 V1.2, 2012-07

12

10

8

6

4

2




Leakage Power Consumption Calculation

The leakage power consumption can be calculated according to the following formulas:

I

LK1

= 470,000 + e

-

α

with

α = 5000 / (273 + B×

T

J

)

Parameter B must be replaced by

• 1.0 for typical values

• 1.3 for maximum values

I

LK

[mA]

I

LK1max

I

LK1typ

-50 0 50 100 125 150

T

J

[°C]

MC_XC2XL_ILKN

Figure 14 Leakage Supply Current as a Function of Temperature

Data Sheet 65 V1.2, 2012-07




4.4

Analog/Digital Converter Parameters

These parameters describe the conditions for optimum ADC performance.


Table 20

Parameter

ADC Parameters for All Voltage Ranges

Symbol Values

Switched capacitance at an analog input

C

AINSW

CC

Min.

Typ.

Max.

−

9 20

Unit Note /

Test Condition


1)

Total capacitance at an analog input

C

AINT

CC

−

20 30 pF not subject to production test

1)

Switched capacitance at the reference input

C

AREFSW

CC

−


1)

Total capacitance at the reference input

C

AREFT

CC

−


1)

Broken wire detection delay against VAGND

2)

t

BWG

CC

− −

50

3)

Broken wire detection

delay against VAREF

2)

Conversion time for 8-bit

result

2)


result

2)


result

2)

Analog reference ground

t

BWR

CC

− −

50

4)

t

c8

CC (10 + STC x

t

ADCI

+ 2 x

t

SYS

t

c10

CC (12 + STC x

t

ADCI

+ 2 x

t

SYS

t

c12

CC (16 + STC x

t

ADCI

+ 2 x

t

SYS

V

AGND

SR

V

SS

-

0.05

−

1.5

V

AIN

SR

V

AGND

−

V

AREF

V

Analog input voltage range

V

5)

Analog reference voltage

V

AREF

SR

V

AGND

+ 1.0

−

V

DDPB

+ 0.05

V

1) These parameter values cover the complete operating range. Under relaxed operating conditions

(temperature, supply voltage) typical values can be used for calculation.

Data Sheet 66 V1.2, 2012-07




2) This parameter includes the sample time (also the additional sample time specified by STC), the time to determine the digital result and the time to load the result register with the conversion result. Values for the basic clock

t

ADCI

depend on programming.

3) The broken wire detection delay against

V

AGND

is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 500 µs. Result below 10% (66

H

)

4) The broken wire detection delay against

V

AREF

is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10 µs. This function is influenced by leakage current, in particular at high temperature. Result above 80% (332

H

)

5)

V

AIN

may exceed

V

AGND

or

V

AREF

up to the absolute maximum ratings. However, the conversion result in these cases will be X000

H

or X3FF

H

, respectively.

Table 21

Parameter

ADC Parameters for Upper Voltage Range

Symbol Values

Input resistance of the selected analog channel

Min.

Typ.

Max.

R

AIN

CC

−

0.9

1.5

Input resistance of the reference input

R

AREF

CC

−

0.5

2.5

1

5.0

Unit Note /

Test Condition

kOh m not subject to production test

1) kOh m not subject to production test

1)

LSB Differential Non-Linearity

Error

2)3)4)5)

Gain Error

2)3)4)5)

Integral Non-

Linearity

2)3)4)5)

Offset Error

2)3)4)5)

Analog clock frequency

|

|

|

EA

DNL

|

CC

|

EA

GAIN

|

CC

−

−

EA

CC

INL

|

−

EA

CC

OFF

|

−

f

ADCI

SR 2

2

2.5

2.0

2.0

−

−

2.5

6.0

4.0

4.0

20

17.5

5.5

LSB

LSB

LSB

MHz Std. reference input (

V

AREF

)

MHz Alt. reference input (CH0)

LSB

6)7)

Total Unadjusted Error

3)4)

Wakeup time from analog powerdown, fast mode

Wakeup time from analog powerdown, slow mode

|TUE|

CC

−

t

WAF

CC

−

t

WAS

CC

−

−

−

7.0

11.5

μs

μs

Data Sheet 67 V1.2, 2012-07






2) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.

3) If a reduced analog reference voltage between 1V and

V

DDPB

/ 2 is used, then there are additional decrease in the ADC speed and accuracy.

4) If the analog reference voltage range is below

V

DDPB

but still in the defined range of

V

DDPB

/ 2 and

V

DDPB

is used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE,

DNL, INL, Gain and Offset errors increase also by the factor 1/k.

5) If the analog reference voltage is >

V

DDPB

, then the ADC converter errors increase.

6) TUE is based on 12-bit conversion.

7) TUE is tested at

V

AREF

=

V

DDPB

= 5.0 V,

V

AGND

= 0 V. It is verified by design for all other voltages within the defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog port pins (see

I

OV

specification) does not exceed 10 mA, and if

V

AREF

and

V

AGND

remain stable during the measurement time.

Table 22

Parameter

ADC Parameters for Lower Voltage Range

Symbol Values

Input resistance of the selected analog channel

Min.

Typ.

Max.

R

AIN

CC

−

1.4

2.5

Input resistance of the reference input

R

AREF

CC

−

1.0

2.5

2.0

5.5

Unit Note /

Test Condition

kOh m not subject to production test

1) kOh m not subject to production test

1)

LSB Differential Non-Linearity

Error

2)3)4)5)

Gain Error

2)3)4)5)

Integral Non-

Linearity

2)3)4)5)

Offset Error

2)3)4)5)

Analog clock frequency

|

|

|

EA

DNL

|

CC

|

EA

GAIN

|

CC

−

−

EA

CC

INL

|

−

EA

CC

OFF

|

−

f

ADCI

SR 2

3.0

2.5

2.0

−

8.0

7.5

5.5

16.7

LSB

LSB

LSB

Total Unadjusted Error

3)4)

|TUE|

CC

2

−

−

2.5

12.1

7.5

MHz Std. reference input (

V

AREF

)

MHz Alt. reference input (CH0)

LSB

6)7)

Data Sheet 68 V1.2, 2012-07




Table 22

ADC Parameters for Lower Voltage Range (cont’d)


Test Condition

Wakeup time from analog powerdown, fast mode

t

WAF

Min.

Typ.

Max.

CC

− −

8.5

μs

Wakeup time from analog powerdown, slow mode

t

WAS

CC

− −

15.0

μs



2) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.

3) If a reduced analog reference voltage between 1V and

V

DDPB

/ 2 is used, then there are additional decrease in the ADC speed and accuracy.

4) If the analog reference voltage range is below

V

DDPB

but still in the defined range of

V

DDPB

/ 2 and

V

DDPB

is used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE,

DNL, INL, Gain and Offset errors increase also by the factor 1/k.

5) If the analog reference voltage is >

V

DDPB

, then the ADC converter errors increase.

6) TUE is based on 12-bit conversion.

7) TUE is tested at

V

AREF

=

V

DDPB

= 3.3 V,

V

AGND

= 0 V. It is verified by design for all other voltages within the defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog port pins (see

I

OV

specification) does not exceed 10 mA, and if measurement time.

V

AREF

and

V

AGND

remain stable during the

V

AIN

R

Source

C

Ext

R

AIN, On

C

AINT

-

C

AINS

A/D Converter

C

AINS

MCS05570

Figure 15 Equivalent Circuitry for Analog Inputs

Sample time and conversion time of the XE161xL’s A/D converters are programmable.

The timing above can be calculated using

Table 23

.

The limit values for

f

ADCI

must not be exceeded when selecting the prescaler value.

Data Sheet 69 V1.2, 2012-07




Table 23 A/D Converter Computation Table

:

GLOBCTR.5-0

(DIVA)

000000

B

000001

B

000010

B

111110

B

111111

B

f f f f f f

A/D Converter

Analog Clock

f

ADCI

SYS

SYS

/ 2

SYS

/ 3

SYS

/ (DIVA+1)

SYS

/ 63

SYS

/ 64

:

INPCRx.7-0

(STC)

00

H

01

H

02

H

FE

H

FF

H

t

Sample Time

1)

t

S

t

ADCI

× 2

t

ADCI

× 3

t

ADCI

× 4

t

ADCI

× (STC+2)

t

ADCI

× 256

ADCI

× 257

1) The selected sample time is doubled if broken wire detection is active (due to the presampling phase).

Converter Timing Example A:

Assumptions:

Analog clock

Sample time

t

S

Conversion 12-bit:

f

SYS

f

ADCI

t

C12



t

C10

t

C8

= 80 MHz (i.e.

t

SYS

= 12.5 ns), DIVA = 03

H

, STC = 00

H

=

f

SYS

/ 4 = 20 MHz, i.e.

t

ADCI

= 50 ns

=

t

ADCI

× 2 = 100 ns

= 16

×

t

ADCI

+ 2

×

t

SYS

= 16

× 50 ns + 2 × 12.5 ns = 0.825 μs

= 12

×

t

ADCI

+ 2

×

t

SYS

= 12

× 50 ns + 2 × 12.5 ns = 0.625 μs

= 10

×

t

ADCI

+ 2

×

t

SYS

= 10

× 50 ns + 2 × 12.5 ns = 0.525 μs

Converter Timing Example B:

Assumptions:

Analog clock

Sample time

f

SYS

f

ADCI

t

S


t

C12


t

C10

= 66 MHz (i.e.

t

SYS

= 15.2 ns), DIVA = 03

H

, STC = 00

H

=

f

SYS

/ 4 = 16.5 MHz, i.e.

t

ADCI

= 60.6 ns

=

t

ADCI

× 2 = 121.2 ns

= 16

×

t

ADCI

+ 2

×

t

SYS

= 16

× 60.6 ns + 2 × 15.2 ns = 1.0 μs

= 12

×

t

ADCI

+ 2

×

t

SYS

= 12

× 60.6 ns + 2 × 15.2 ns = 0.758 μs

Data Sheet 70 V1.2, 2012-07





t

C8

= 10

×

t

ADCI

+ 2

×

t

SYS

= 10

× 60.6 ns + 2 × 15.2 ns = 0.636 μs

Data Sheet 71 V1.2, 2012-07




4.5

System Parameters

The following parameters specify several aspects which are important when integrating the XE161xL into an application system.

Note: These parameters are not subject to production test but verified by design and/or characterization.


Table 24 Various System Parameters


Test Condition

Short-term deviation of internal clock source frequency

1)

Δ

f

INT

Min.

Typ.

Max.

CC -1

−

1 %

Δ

T

J

=

≤ 10°C

Internal clock source frequency

f

INT

CC 4.8

5.0

5.2

MHz

Wakeup clock source frequency

2)

Startup time from poweron with code execution from Flash

f

WU

CC 400

210

140

110

t

SPO

CC 1.4

−

−

−

−

1.9

700

390

260

200

2.4

kHz FREQSEL= 00 kHz FREQSEL= 01 kHz FREQSEL= 10 kHz FREQSEL= 11 ms

f

WU

= 500 kHz

Startup time from stopover mode with code execution from PSRAM

Core voltage (PVC) supervision level

Supply watchdog (SWD) supervision level

t

SSO

CC 11 /

f

WU

3)

V

V

PVC

CC

SWD

CC

V

LV

-

0.03

V

LV

-

0.10

6)

−

V

V

LV

LV

12 /

f

WU

3)

V

LV

+

0.07

4)

V

LV

+

0.15

μs

V

V

5) voltage_range= lower

5)

V

LV

-

0.15

V

LV

V

LV

+

0.15

V voltage_range= upper

5)

1) The short-term frequency deviation refers to a timeframe of a few hours and is measured relative to the current frequency at the beginning of the respective timeframe. This parameter is useful to determine a time span for re-triggering a LIN synchronization.

2) This parameter is tested for the fastest and the slowest selection. The medium selections are not subject to production test - verified by design/characterization.

3)

f

WU

in MHz.

Data Sheet 72 V1.2, 2012-07




4) This value includes a hysteresis of approximately 50 mV for rising voltage.

5)

V

LV

= selected SWD voltage level

6) The limit

V

LV

- 0.10 V is valid for the OK1 level. The limit for the OK2 level is

V

LV

- 0.15 V.

Conditions for

t

SPO

Timing Measurement

The time required for the transition from Power-On to Base mode is called

t

SPO

. It is measured under the following conditions:

Precondition: The pad supply is valid, i.e.

V

DDPB

is above 3.0 V and remains above 3.0 V even though the XE161xL is starting up. No debugger is attached.

Start condition: Power on reset is removed (PORST = 1).

End condition: External pin toggle caused by first user instruction executed from Flash after startup.

Conditions for

t

SSO

Timing Measurement

The time required for the transition from Stopover to Stopover Waked-Up mode is called

t

SSO

. It is measured under the following conditions:

Precondition: The Stopover mode has been entered using the procedure defined in the

Programmer’s Guide.

Start condition: Pin toggle on ESR pin triggering the startup sequence.

End condition: External pin toggle caused by first user instruction executed from PSRAM after startup.

Data Sheet 73 V1.2, 2012-07




Coding of bit fields LEVxV in SWD Configuration Registers

After power-on the supply watch dog is preconfigured to operate in the lower voltage range.

Table 25

Code

Coding of bit fields LEVxV in Register SWDCON0

Default Voltage Level Notes

1)

0000

B

0001

B

0010

B

- 0101

B

0110

B

0111

B

1000

B

1001

B

1010

B

- 1110

B

-

3.0 V

3.1 V - 3.4 V

3.6 V

4.0 V

4.2 V

4.5 V

4.6 V - 5.0 V out of valid operation range

LEV1V: reset request step width is 0.1 V

LEV2V: no request step width is 0.1 V

1111

B

5.5 V

1) The indicated default levels are selected automatically after a power reset.

Coding of bit fields LEVxV in PVC Configuration Registers

The core voltages are controlled internally to the nominal value of 1.5 V; a variation of

±10 % is allowed. These operation conditions limit the possible PVC monitoring values to the predefined reset values shown in

Table 26

.

Table 26

Code

Coding of bit fields LEVxV in Registers PVCyCONz

Default Voltage Level Notes

1)

000

B

- 011

B

100

B

101

B

-

1.35 V

1.45 V out of valid operation range

LEV1V: reset request

LEV2V: interrupt request

2)

110

B

- 111

B

out of valid operation range

1) The indicated default levels are selected automatically after a power reset.

2) Due to variations of the tolerance of both the Embedded Voltage Regulators (EVR) and PVC levels, this interrupt can be triggered inadvertently, even though the core voltage is within the normal range. It is, therefore, recommended not to use this warning level.

Data Sheet 74 V1.2, 2012-07




4.6

Flash Memory Parameters

The XE161xL is delivered with all Flash sectors erased and with no protection installed.

The data retention time of the XE161xL’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed.



Table 27 Flash Parameters

Parameter

Parallel Flash module program/erase limit depending on Flash read activity

Flash erase endurance for security pages

Flash wait states

3)

Symbol

N

PP

Min.

Typ.

Max.

SR

−

−

N

SEC

SR 10

Values

−

−

−

2

1

−

1)

2)

t

N

WSFLASH

SR

1

2

3

ER

CC

4

−

−

−

−

−

7

4)

−

−

−

−

8.0

Erase time per sector/page

Programming time per page

Data retention time

t t

PR

CC

−

RET

CC 20

3

4)

−

3.5

−

Drain disturb limit

N

DD

SR 32

− −

Unit Note /

Test Condition

N

FL_RD

≤ 1

N

FL_RD

> 1 cycle s

t

RET

≥ 20 years

f

SYS

≤ 8 MHz

f

SYS

≤ 13 MHz

f

SYS

≤ 17 MHz

f

SYS

> 17 MHz ms ms year s cycle s

N

ER

≤ 1,000 cycl es

Data Sheet 75 V1.2, 2012-07




Table 27

Flash Parameters (cont’d)

Parameter

Number of erase cycles

Symbol

N

Min.

Typ.

Max.

ER

SR

−

Values

−

15000

Unit Note /

Test Condition

cycle s

t

RET

≥ 5 years;

Valid for up to

64 user selected sectors (data storage)

− −

1000 cycle s

t

RET

≥ 20 years

1) All Flash module(s) can be erased/programmed while code is executed and/or data is read from only one Flash module or from PSRAM. The Flash module that delivers code/data can, of course, not be erased/programmed.

2) Flash module 1 can be erased/programmed while code is executed and/or data is read from Flash module 0.

3) Value of IMB_IMBCTRL.WSFLASH.

4) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few system clock cycles. This increases the stated durations noticably only at extremely low system clock frequencies.

Access to the XE161xL Flash modules is controlled by the IMB. Built-in prefetch mechanisms optimize the performance for sequential access.

Flash access waitstates only affect non-sequential access. Due to prefetch mechanisms, the performance for sequential access (depending on the software structure) is only partially influenced by waitstates.

Data Sheet 76 V1.2, 2012-07




4.7

AC Parameters

These parameters describe the dynamic behavior of the XE161xL.

4.7.1

Testing Waveforms

These values are used for characterization and production testing (except pin XTAL1).

O utput delay

H old tim e

O utput delay

H old tim e

0.8 V

D D P

0.7 V

D D P

Input S ignal

(driven by tester)

0.3 V

D D P

0.2 V

D D P

O utput S ignal

(m easured)

O utput tim ings refer to the rising edge of C LKO U T.

Input tim ings are calculated from the tim e, w hen the input signal reaches

V

IH

or V

IL

, respectively.

M C D 05556C

Figure 16 Input Output Waveforms

V

Load

+ 0.1 V

V

OH

- 0.1 V

Timing

Reference

Points

V

Load

- 0.1 V

V

OL

+ 0.1 V

Figure 17

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded

V

OH

/

V

OL

level occurs (

I

OH

/

I

OL

= 20 mA).

MCA05565

Floating Waveforms

Data Sheet 77 V1.2, 2012-07




4.7.2

Definition of Internal Timing

The internal operation of the XE161xL is controlled by the internal system clock

f

SYS

.

Because the system clock signal

f

SYS

can be generated from a number of internal and external sources using different mechanisms, the duration of the system clock periods

(TCSs) and their variation (as well as the derived external timing) depend on the mechanism used to generate

f

SYS

. This must be considered when calculating the timing for the XE161xL.

Phase Locked Loop Operation (1:N)

f

I N

f

SYS

TCS

Direct Clock Drive (1:1)

f

I N

f

SYS

TCS

Prescaler Operation (N:1)

f

I N

f

SYS

TCS

M C_XC2X_CLOCKGEN

Figure 18 Generation Mechanisms for the System Clock

Note: The example of PLL operation shown in

Figure 18

uses a PLL factor of 1:4; the

example of prescaler operation uses a divider factor of 2:1.

The specification of the external timing (AC Characteristics) depends on the period of the system clock (TCS).

Data Sheet 78 V1.2, 2012-07




Direct Drive

When direct drive operation is selected (SYSCON0.CLKSEL = 11

B

), the system clock is derived directly from the input clock signal CLKIN1:

f

SYS

=

f

IN

.

The frequency of

f

SYS

is the same as the frequency of

f

IN

. In this case the high and low times of

f

SYS

are determined by the duty cycle of the input clock

f

IN

.

Selecting Bypass Operation from the XTAL1

1)

input and using a divider factor of 1 results in a similar configuration.

Prescaler Operation

When prescaler operation is selected (SYSCON0.CLKSEL = 10

B

, PLLCON0.VCOBY =

1

B

), the system clock is derived either from the crystal oscillator (input clock signal

XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):

f

SYS

=

f

OSC

/ K1.

If a divider factor of 1 is selected, the frequency of

f

this case the high and low times of clock

f

OSC

(external or internal).

f

SYS

SYS

equals the frequency of

f

OSC

. In

are determined by the duty cycle of the input

The lowest system clock frequency results from selecting the maximum value for the divider factor K1:

f

SYS

=

f

OSC

/ 1024.

4.7.2.1

Phase Locked Loop (PLL)

When PLL operation is selected (SYSCON0.CLKSEL = 10

B

, PLLCON0.VCOBY = 0

B

), the on-chip phase locked loop is enabled and provides the system clock. The PLL multiplies the input frequency by the factor F (

f

SYS

=

f

IN

× F).

F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=

NDIV+1), and the output divider K2 (= K2DIV+1):

(F = N / (P

× K2)).

The input clock can be derived either from an external source at XTAL1 or from the onchip clock source.

The PLL circuit synchronizes the system clock to the input clock. This synchronization is performed smoothly so that the system clock frequency does not change abruptly.

Adjustment to the input clock continuously changes the frequency of

f

SYS locked to

f

IN

. The slight variation causes a jitter of

f

SYS

so that it is

which in turn affects the duration of individual TCSs.

1) Voltages on XTAL1 must comply to the core supply voltage

V

DDIM

.

Data Sheet 79 V1.2, 2012-07




The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the minimum TCS possible under the given circumstances.

The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or oscillator), the accumulated jitter is limited. This means that the relative deviation for periods of more than one TCS is lower than for a single TCS (see formulas

and

Figure 19

).

This is especially important for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible.

The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO output clock is divided by the output prescaler K2 to generate the system clock signal

f

SYS

. The number of VCO cycles is K2

× T, where T is the number of consecutive

f

SYS

cycles (TCS).

The maximum accumulated jitter (long-term jitter) D

Tmax

is defined by:

D

Tmax

[ns] =

±(220 / (K2 ×

f

SYS

) + 4.3)

This maximum value is applicable, if either the number of clock cycles T > (

f

SYS

/ 1.2) or the prescaler value K2 > 17.

In all other cases for a timeframe of T

× TCS the accumulated jitter D

T

is determined by:

D

T

[ns] = D

Tmax

× [(1 - 0.058 × K2) × (T - 1) / (0.83 ×

f

SYS

- 1) + 0.058

× K2]

f

SYS

in [MHz] in all formulas.

Example, for a period of 3 TCSs @ 33 MHz and K2 = 4:

D max

=

±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!)

D

3

= 5.97

× [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4]

= 5.97

× [0.768 × 2 / 26.39 + 0.232]

= 1.7 ns

Example, for a period of 3 TCSs @ 33 MHz and K2 = 2:

D max

=

±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!)

D

3

= 7.63

× [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2]

= 7.63

× [0.884 × 2 / 26.39 + 0.116]

= 1.4 ns

Data Sheet 80 V1.2, 2012-07




Acc. jitter

D

T ns

±9

±5

±4

±3

±8

±7

±6

±2

±1

0

1 20

f

SYS

= 33 MHz

f

SYS

= 66 MHz

40 60 80

f

VCO

= 66 MHz

f

VCO

= 132 MHz

Cycles

100

T

MC_XC2X_JITTER

Figure 19 Approximated Accumulated PLL Jitter

Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed

C

L

= 20 pF.

The maximum peak-to-peak noise on the pad supply voltage (measured between

V

DDPB

pin and

V

SS

pin) is limited to a peak-to-peak voltage of

V

PP

= 50 mV. This can be achieved by appropriate blocking of the supply voltage as close as possible to the supply pins and using PCB supply and ground planes.

PLL frequency band selection

Different frequency bands can be selected for the VCO so that the operation of the PLL can be adjusted to a wide range of input and output frequencies:

Data Sheet 81 V1.2, 2012-07




Table 28

Parameter

System PLL Parameters

Symbol

VCO output frequency

Values

f

Min.

Typ.

Max.

VCO

CC 50

−

110

10

100

20

−

−

−

40

160

80

Unit Note /

Test Condition

MHz

MHz

MHz

MHz

VCOSEL

= 00

B

;

VCOmode

= controlled

VCOSEL

= 00

B

;

VCOmode

= free running

VCOSEL

= 01

B

;

VCOmode

= controlled

VCOSEL

= 01

B

;

VCOmode

= free running

4.7.2.2

Wakeup Clock

When wakeup operation is selected (SYSCON0.CLKSEL = 00

B

), the system clock is derived from the low-frequency wakeup clock source:

f

SYS

=

f

WU

.

In this mode, a basic functionality can be maintained without requiring an external clock source and while minimizing the power consumption.

4.7.2.3

Selecting and Changing the Operating Frequency

When selecting a clock source and the clock generation method, the required parameters must be carefully written to the respective bit fields, to avoid unintended intermediate states.

Many applications change the frequency of the system clock (

f

SYS

) during operation in order to optimize system performance and power consumption. Changing the operating frequency also changes the switching currents, which influences the power supply.

To ensure proper operation of the on-chip EVRs while they generate the core voltage, the operating frequency shall only be changed in certain steps. This prevents overshoots and undershoots of the supply voltage.

To avoid the indicated problems, recommended sequences are provided which ensure the intended operation of the clock system interacting with the power system.

Please refer to the Programmer’s Guide.

Data Sheet 82 V1.2, 2012-07




4.7.3

External Clock Input Parameters

These parameters specify the external clock generation for the XE161xL. The clock can be generated in two ways:

• By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2.

• By supplying an external clock signal. This clock signal can be supplied either to pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain).

If connected to CLKIN1, the input signal must reach the defined input levels

If connected to XTAL1, a minimum amplitude

V

IL

and

V

IH

.

V

AX1

(peak-to-peak voltage) is sufficient for the operation of the on-chip oscillator.

Note: The given clock timing parameters ( t

1

…

t

4

) are only valid for an external clock input signal.


Table 29 External Clock Input Characteristics


Test Condition

Oscillator frequency

f

Min.

Typ.

Max.

OSC

SR 4

−

40 MHz Input= Clock

Signal

XTAL1 input current absolute value

|

I

4

IL

| CC

−

−

−

16

20

MHz Input= Crystal or Resonator

μA

Input clock high time

Input clock low time

Input clock rise time

Input clock fall time

Input voltage amplitude on

XTAL1

1)

Input voltage range limits for signal on XTAL1

t t

1

t

2

SR

SR

t

3

SR

4

V

SR

AX1

6

6

−

−

SR 0.3 x

V

DDIM

0.4 x

V

DDIM

0.5 x

V

DDIM

−

−

8

8

−

−

−

−

−

8

8

−

−

− ns ns ns ns

V

V

V

f f

OSC

≥ 4 MHz;

OSC

≤ 16 MHz

f f

OSC

≥ 16 MHz;

OSC

≤ 25 MHz

f f

OSC

≥ 25 MHz;

OSC

≤ 40 MHz

2)

V

IX1

SR -1.7 +

V

DDIM

−

1.7

V

1) The amplitude voltage

V

AX1

refers to the offset voltage

V

OFF

. This offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by

V

IX1

.

Data Sheet 83 V1.2, 2012-07




2) Overload conditions must not occur on pin XTAL1.

Note: For crystal/resonator operation, it is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for oscillator operation.

The manufacturers of crystals and ceramic resonators offer an oscillator evaluation service. This evaluation checks the crystal/resonator specification limits to ensure a reliable oscillatior operation.

t

1

t

3

V

OFF

V

AX1

0.9 V

AX1

0.1 V

AX1

t

2

t

4

t

OSC

= 1/f

OSC

MC_ EXTCLOCK

Figure 20 External Clock Drive XTAL1

Data Sheet 84 V1.2, 2012-07




4.7.4

Pad Properties

The output pad drivers of the XE161xL can operate in several user-selectable modes.

Strong driver mode allows controlling external components requiring higher currents such as power bridges or LEDs. Reducing the driving power of an output pad reduces electromagnetic emissions (EME). In strong driver mode, selecting a slower edge reduces EME.

The dynamic behavior, i.e. the rise time and fall time, depends on the applied external capacitance that must be charged and discharged. Timing values are given for a capacitance of 20 pF, unless otherwise noted.

In general, the performance of a pad driver depends on the available supply voltage

V

DDP

. Therefore the following tables list the pad parameters for the upper voltage range and the lower voltage range, respectively.



Table 30


V

DDP

≤ 5.5 V;

V

DDP typ. 5 V;

V

DDP

≥ 4.5 V

Table 30

Parameter

Standard Pad Parameters for Upper Voltage Range


Test Condition

Maximum output driver current (absolute value)

1)

I

Omax

CC

Min.

Typ.

Max.

− −

3.0

mA Driver_Strength

= Medium

− −

5.0

− −

0.5

mA Driver_Strength

= Strong mA Driver_Strength

= Weak

Nominal output driver current (absolute value)

I

Onom

CC

− −

1.0

mA Driver_Strength

= Medium

− −

1.6

mA Driver_Strength

= Strong

− −

0.25

mA Driver_Strength

= Weak

Data Sheet 85 V1.2, 2012-07




Table 30

Standard Pad Parameters for Upper Voltage Range (cont’d)


Test Condition

Rise and Fall times (10% -

90%)

t

RF

Min.

Typ.

Max.

CC

− −

38 +

0.6 x

C

L

−

−

−

−

−

−

1 +

0.45 x

C

L

16 +

0.45 x

C

L

200 +

2.5 x

C

L ns ns ns ns

C

C

L

≥ 20 pF;

L

≤ 100 pF;

Driver_Strength

= Medium

C

C

L

≥ 20 pF;

L

≤ 100 pF;

Driver_Strength

= Strong ;

Driver_Edge=

Soft

C

C

L

≥ 20 pF;

L

≤ 100 pF;

Driver_Strength

= Strong ;

Driver_Edge=

Slow

C

C

L

≥ 20 pF;

L

≤ 100 pF;

Driver_Strength

= Weak

1) The total output current that may be drawn at a given time must be limited to protect the supply rails from damage. For any group of 16 neighboring output pins, the total output current in each direction (

Σ

I

OL

and

Σ

-

I

OH

) must remain below 25 mA.

Table 31

Parameter

Standard Pad Parameters for Lower Voltage Range

Maximum output driver current (absolute value)

1)

Symbol

I

Omax

CC

Values

Min.

Typ.

Max.

− −

1.8

−

−

−

−

3.0

0.3

Unit

mA

Note /

Test Condition

Driver_Strength

= Medium mA Driver_Strength


= Weak

Data Sheet 86 V1.2, 2012-07




Table 31

Standard Pad Parameters for Lower Voltage Range (cont’d)


Test Condition

Nominal output driver current (absolute value)

I

Onom

CC

Min.

Typ.

Max.

− −

0.8

mA Driver_Strength

= Medium

Rise and Fall times (10% -

90%)

−

−

t

RF

CC

−

−

−

−

−

−

−

−

−

−

1.0

0.15

73 +

0.85 x

C

L

6 + 0.6 x

C

L

33 +

0.6 x

C

L

385 +

3.25 x

C

L mA Driver_Strength


= Weak ns

C

C

L

≥ 20 pF;

L

≤ 100 pF;

Driver_Strength

= Medium ns ns ns

C

C

L

≥ 20 pF;

L

≤ 100 pF;

Driver_Strength

= Strong ;

Driver_Edge=

Soft

C

C

L

≥ 20 pF;

L

≤ 100 pF;

Driver_Strength

= Strong ;

Driver_Edge=

Slow

C

C

L

≥ 20 pF;

L

≤ 100 pF;

Driver_Strength

= Weak

1) The total output current that may be drawn at a given time must be limited to protect the supply rails from damage. For any group of 16 neighboring output pins, the total output current in each direction (

Σ

I

OL

and

Σ

-

I

OH

) must remain below 25 mA.

Data Sheet 87 V1.2, 2012-07




4.7.5

Synchronous Serial Interface Timing

The following parameters are applicable for a USIC channel operated in SSC mode.



Table 32


C

L

= 20 pF; voltage_range= upper

SSC

= master ;

Table 32

Parameter

USIC SSC Master Mode Timing for Upper Voltage Range

Slave select output SELO active to first SCLKOUT transmit edge

Symbol

t

1

CC

Slave select output SELO inactive after last

SCLKOUT receive edge

t

2

CC

Data output DOUT valid time

t

3

CC

Receive data input setup time to SCLKOUT receive edge

t

4

SR

t

5

SR Data input DX0 hold time from SCLKOUT receive edge

1)

t

SYS

= 1 /

f

SYS

t

6

SYS

1)

-

-6

31

-4

Values

t

Min.

Typ.

Max.

8

SYS

1)

-

− −

−

−

−

−

−

9

−

−

Unit

ns ns ns ns ns

Note /

Test Condition

Data Sheet 88 V1.2, 2012-07




Table 33


C

L

= 20 pF; voltage_range= lower

SSC

= master ;

Table 33

Parameter

USIC SSC Master Mode Timing for Lower Voltage Range


Test Condition

t

Min.

Typ.

Max.

SYS

10

1)

-

− − ns Slave select output SELO active to first SCLKOUT transmit edge

t

1

CC

Slave select output SELO inactive after last

SCLKOUT receive edge


t

2

CC

t

3

CC

Receive data input setup time to SCLKOUT receive edge

Data input DX0 hold time from SCLKOUT receive edge

1)

t

SYS

= 1 /

f

SYS

t

4

SR

t

5

SR

t

9

SYS

1)

-

-7

40

-5

−

−

−

−

−

11

−

− ns ns ns ns

Table 34


C

L


SSC

= slave ;

Table 34

Parameter

USIC SSC Slave Mode Timing for Upper Voltage Range

Select input DX2 setup to first clock input DX1 transmit edge

1)

Receive data input setup time to shift clock receive

edge

1)

t

Symbol

10

Values

Min.

Typ.

Max.

SR 10

Select input DX2 hold after last clock input DX1

receive edge

1)

t

11

SR 7

t

12

SR 7

−

−

−

−

−

−

Unit Note /

Test Condition

ns ns ns

Data Sheet 89 V1.2, 2012-07




Table 34

USIC SSC Slave Mode Timing for Upper Voltage Range (cont’d)


Test Condition

Data input DX0 hold time from clock input DX1

receive edge

1)

t

13

Min.

Typ.

Max.

SR 5

− − ns


t

14

CC 7

−

33 ns

1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0).

Table 35


C

L


SSC

= slave ;

Table 35 USIC SSC Slave Mode Timing for Lower Voltage Range


Test Condition

Select input DX2 setup to first clock input DX1 transmit edge

1)

t

10

Min.

Typ.

Max.

SR 10

− − ns

Select input DX2 hold after last clock input DX1

receive edge

1)

t

11

SR 7

− − ns

Receive data input setup time to shift clock receive

edge

1)

t

12

SR 7

− − ns

Data input DX0 hold time from clock input DX1

receive edge

1)

t

13

SR 5

− − ns


t

14

CC 8

−

41 ns

1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0).

Data Sheet 90 V1.2, 2012-07




Master Mode Timing

Select Output

SELOx

Inactive

t

1

Clock Output

SCLKOUT

Data Output

DOUT

Active

First Transmit

Edge

t

3

Receive

Edge

Data Input

DX0

t

4

Data valid

t

5

Transmit

Edge

t

3

t

2

Inactive

Last Receive

Edge

t

4

Data valid

t

5

Slave Mode Timing

Select Input

DX2

Inactive

t

10

Clock Input

DX1

Data Input

DX0

Active

First Transmit

Edge

Receive

Edge

t

12

t

13

Data valid

t

14

Data Output

DOUT

t

11

Inactive

Transmit

Edge

Last Receive

Edge

t

12

t

13

Data valid

t

14

Drawn for BRGH .SCLKCFG = 00

B

. Also valid for for SCLKCFG = 01

B

with inverted SCLKOUT signal.

USIC_SSC_TMGX.VSD

Figure 21 USIC - SSC Master/Slave Mode Timing

Note: This timing diagram shows a standard configuration where the slave select signal is low-active and the serial clock signal is not shifted and not inverted.

Data Sheet 91 V1.2, 2012-07




4.7.6

Debug Interface Timing

The debugger can communicate with the XE161xL via 1-pin SPD interface, via the 2-pin

DAP interface or via the standard JTAG interface.

Debug via DAP

The following parameters are applicable for communication through the DAP debug interface.



Table 36


C

L


Table 36 DAP Interface Timing for Upper Voltage Range


Test Condition

DAP0 clock period

DAP0 high time

DAP0 low time

DAP0 clock rise time

DAP0 clock fall time

t t t t

11

12

t

13

t

14

15

16

Min.

Typ.

Max.

SR 100

1)

SR 8

SR 8

SR

−

SR

−

SR 6

−

−

−

−

−

−

−

−

−

4

4

− ns ns ns ns ns

DAP1 setup to DAP0 rising edge ns pad_type= stan dard

DAP1 hold after DAP0 rising edge

t

17

SR 6

− − ns pad_type= stan dard

DAP1 valid per DAP0 clock period

2)

t

19

CC 92 95

− ns

1) The debug interface cannot operate faster than the overall system, therefore

t

11

≥

t

SYS

.

2) The Host has to find a suitable sampling point by analyzing the sync telegram response.

pad_type= stan dard

Data Sheet 92 V1.2, 2012-07




Table 37


C

L


Table 37 DAP Interface Timing for Lower Voltage Range


Test Condition

DAP0 clock period

DAP0 high time

DAP0 low time

DAP0 clock rise time

DAP0 clock fall time

t t t t

11

12

t

13

t

14

15

16

Min.

Typ.

Max.

SR 100

1)

SR 8

SR 8

SR

−

SR

−

SR 6

−

−

−

−

−

−

−

−

−

4

4

− ns ns ns ns ns

DAP1 setup to DAP0 rising edge ns pad_type= stan dard

DAP1 hold after DAP0 rising edge

t

17

SR 6

− − ns pad_type= stan dard

DAP1 valid per DAP0 clock period

2)

t

19

CC 87 92

− ns


t

11

≥

t

SYS

.

2) The Host has to find a suitable sampling point by analyzing the sync telegram response.

pad_type= stan dard

t

11

0.5

V

DDP

t

15

t

14

0.9

V

DDP

0.1

V

DDP

t

12

t

13

MC_DAP0

Figure 22 Test Clock Timing (DAP0)

Data Sheet 93 V1.2, 2012-07




DAP0

t

1 6

t

1 7

DAP1

MC_ DAP1_RX

Figure 23 DAP Timing Host to Device

t

1 1

DAP1

t

1 9

MC_ DAP1_TX

Figure 24 DAP Timing Device to Host

Note: The transmission timing is determined by the receiving debugger by evaluating the sync-request synchronization pattern telegram.

Data Sheet 94 V1.2, 2012-07




Debug via JTAG

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000.



Table 38


C

L


Table 38 JTAG Interface Timing for Upper Voltage Range


Test Condition

TCK clock period

TCK high time

TCK low time

TCK clock rise time

TCK clock fall time

t

1

SR

t

2

SR

t

3

SR

t

4

SR

t

5

SR

t

6

SR

16

−

−

Min.

Typ.

Max.

100

16

6

1)

−

−

−

−

−

−

−

−

−

8

8

− ns ns ns ns ns

TDI/TMS setup to TCK rising edge ns

TDI/TMS hold after TCK rising edge

t

7

SR 6

− − ns

TDO valid from TCK falling edge (propagation delay)

3)

t

8

CC

−

29 32 ns

TDO high impedance to valid output from TCK falling edge

4)3)

t

9

CC

−

29 32 ns

TDO valid output to high impedance from TCK

falling edge

3)

t

10

CC

−

29 32 ns

TDO hold after TCK falling

edge

3)

t

18

CC 5

− − ns


t

1

≥

t

SYS

.

2) Under typical conditions, the JTAG interface can operate at transfer rates up to 10 MHz.

3) The falling edge on TCK is used to generate the TDO timing.

2)

4) The setup time for TDO is given implicitly by the TCK cycle time.

Data Sheet 95 V1.2, 2012-07




Table 39


C

L


Table 39 JTAG Interface Timing for Lower Voltage Range


Test Condition

TCK clock period

TCK high time

TCK low time

TCK clock rise time

TCK clock fall time

t

1

SR

t

2

SR

t

3

SR

t

4

SR

t

5

SR

t

6

SR

16

−

−

Min.

Typ.

Max.

100

16

6

1)

−

−

−

−

−

−

−

−

−

8

8

− ns ns ns ns ns

TDI/TMS setup to TCK rising edge ns

TDI/TMS hold after TCK rising edge

t

7

SR 6

− − ns

TDO valid from TCK falling edge (propagation delay)

2)

t

8

CC

−

39 43 ns

TDO high impedance to valid output from TCK falling edge

3)2)

t

9

CC

−

39 43 ns

TDO valid output to high impedance from TCK

falling edge

2)

t

10

CC

−

39 43 ns

TDO hold after TCK falling

edge

2)

t

18

CC 5

− − ns


t

1

≥

t

SYS

.

2) The falling edge on TCK is used to generate the TDO timing.

3) The setup time for TDO is given implicitly by the TCK cycle time.

Data Sheet 96 V1.2, 2012-07

t

1

0.5

V

D D P

t

2

t

3

Figure 25 Test Clock Timing (TCK)

TCK

t

5




t

4

0.9

V

D D P

0.1

V

D D P

MC_ JTAG_ TCK

t

6

t

7

TMS

t

6

t

7

TDI

t

9

t

8

t

1 0

TDO

t

1 8

MC_JTAG

Figure 26 JTAG Timing

Data Sheet 97 V1.2, 2012-07




Debug via SPD

The SPD interface will work with standard SPD tools having a sample/output clock frequency deviation of +/- 5% or less.

Note: For further details please refer to application note AP24004 in section SPD Timing

Requirements.


Data Sheet 98 V1.2, 2012-07



Package and Reliability

5 Package and Reliability

The XE166 Family devices use the package type:

• PG-VQFN (Plastic Green - Very Thin Profile Quad Flat Non-Leaded Package)

The following specifications must be regarded to ensure proper integration of the

XE161xL in its target environment.

5.1

Packaging

These parameters specify the packaging rather than the silicon.

Table 40 Package Parameters (PG-VQFN-48-54)

Parameter Symbol

Min.

Exposed Pad Dimension Ex

× Ey –

Power Dissipation

Thermal resistance

Junction-Ambient

P

DISS

R

ΘJA

–

–

Limit Values

Max.

5.2 x 5.2

0.7

73

Unit Notes

mm –

W –

K/W No thermal via,

2-layer

1)

49

43

K/W No thermal via,

4-layer

2)

K/W 4-layer, no pad

3)

K/W 4-layer, pad

4)

34

1) Device mounted on a 2-layer JEDEC board (according to JESD 51-3) without thermal vias; exposed pad not soldered.

2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) without thermal vias; exposed pad not soldered.

3) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not soldered.

4) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered to the board.

Note: To improve the EMC behavior, it is recommended to connect the exposed pad to the board ground, independent of the thermal requirements.

Board layout examples are given in an application note.

Package Compatibility Considerations

The XE161xL is a member of the XE166 Family of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies.

Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pin-count but for different device types. In

Data Sheet 99 V1.2, 2012-07




particular, the size of the Exposed Pad (if present) may vary.

If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration.

Package Outlines

7

±0.1

6.8

Index Marking

A

B

+0.03

48x

0.08

0.4 x 45˚

0.9 MAX.

(0.65)

24

25

11 x 0.5 = 5.5

0.5

36

37

C

(0.2)

0.05 MAX.

0.26

13

12

0.15

±0.03

48

0.23

±0.05

(5.2)

1

Index Marking

48x

0.1

M

A B C

(6.2)

PG-VQFN-48-15, -19, -20, -22, -24, -48, -51, -52, -53, -55, -56-PO V12

Figure 27

PG-VQFN-48-54 (Plastic Green Thin Quad Flat Package)

All dimensions in mm.

You can find complete information about Infineon packages, packing and marking in our

Infineon Internet Page “Packages”:

http://www.infineon.com/packages

Data Sheet 100 V1.2, 2012-07




5.2

Thermal Considerations

When operating the XE161xL in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage.

The maximum heat that can be dissipated depends on the package and its integration into the target board. The “Thermal resistance

R

ΘJA

” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 150 °C.

The difference between junction temperature and ambient temperature is determined by

ΔT = (

P

INT

+

P

IOSTAT

+

P

IODYN

)

×

R

ΘJA

The internal power consumption is defined as

P

INT

=

V

DDP

×

I

DDP

(switching current and leakage current).

The static external power consumption caused by the output drivers is defined as

P

IOSTAT

=

Σ((

V

DDP

-

V

OH

)

×

I

OH

) +

Σ(

V

OL

×

I

OL

)

The dynamic external power consumption caused by the output drivers (

P

IODYN

) depends on the capacitive load connected to the respective pins and their switching frequencies.

If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation:

• Reduce

V

DDP

, if possible in the system

• Reduce the system frequency

• Reduce the number of output pins

• Reduce the load on active output drivers

Data Sheet 101 V1.2, 2012-07




5.3

Quality Declarations

The operation lifetime of the XE161xL depends on the operating temperature. The lifetime decreases with increasing temperature as shown in

Table 42

.

Table 41 Quality Parameters

Parameter

Operation lifetime

ESD susceptibility according to Human Body

Model (HBM)

Symbol

t

OP

V

HBM

SR

Values

Min.

Typ.

Max.

CC

−

−

Moisture sensitivity level MSL CC

−

−

−

−

20

2000

3

Unit Note /

Test Condition

a

V

−

See

Table 42

EIA/JESD22-

A114-B

JEDEC

J-STD-020C

Table 42 Lifetime Dependency on Temperature

Operating Time

20 a

95 500 h

68 500 h

49 500 h

26 400 h

14 500 h

Operating Temperature

T

J

≤ 110°C

T

J

= 120°C

T

J

= 125°C

T

J

= 130°C

T

J

= 140°C

T

J

= 150°C

Data Sheet 102 V1.2, 2012-07

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

Infineon SAF-XE161HL-20F80V AA Microcontroller Data Sheet

Architecture

16-Bit Single-Chip

Real Time Signal Controller

XE166 Family / Econo Line

Data Sheet

V1.2 2012-07

Architecture

16-Bit Single-Chip

Real Time Signal Controller

XE166 Family / Econo Line

Data Sheet

V1.2 2012-07

Table of Contents

1 Summary of Features

2 General Device Information

3 Functional Description

4 Electrical Parameters

5 Package and Reliability

Related manuals

Table of contents

Infineon SAF-XE161HL-20F80V AA Microcontroller Data Sheet

Architecture

16-Bit Single-Chip

Real Time Signal Controller

XE166 Family / Econo Line

Data Sheet

V1.2 2012-07

Architecture

16-Bit Single-Chip

Real Time Signal Controller

XE166 Family / Econo Line

Data Sheet

V1.2 2012-07

Table of Contents

1 Summary of Features

2 General Device Information

3 Functional Description

4 Electrical Parameters

5 Package and Reliability

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