si5321 (614296 байта)

si5321 (614296 байта)
Si5321
SONET/SDH P R E C I S I O N C L O C K M U L T I P L I E R I C
Features
„
Ultra-low jitter clock output with jitter
generation as low as 0.3 psRMS
„
„
No external components (other than a
resistor and bypassing)
„ Input clock ranges at 19, 39, 78, 155, „
„
311, or 622 MHz
„ Output clock ranges at 19, 39, 78, 155, „
311, 622, 1244, or 2488 MHz
„
„ Maximum range includes 693 MHz for „
10 GbE FEC support
„
Digital hold for loss-of-input clock
Support for 255/238 (15/14),
255/237 (85/79), and 66/64 FEC scaling
(ITU-T G.709 and IEEE 802.3ae)
Selectable loop bandwidth
Loss-of-signal alarm output
Low power
Small size (9x9 mm)
Backwards compatible with Si5320
Si5321
Si5321
Ordering Information:
Applications
See page 30.
SONET/SDH line/port cards
„ Terabit routers
Core switches
„ Digital cross connects
„
„
Description
The Si5321 is a precision clock multiplier that exceeds the requirements of high-speed
communication systems, including OC-192/OC-48 and 10 Gigabit Ethernet. This device
phase locks to an input clock in the 19, 39, 78, 155, 311 or 622 MHz frequency range
and generates a frequency-multiplied clock output that can be configured for operation
in the 19, 39, 78, 155, 622, 1244, or 2488 MHz frequency range. Silicon Laboratories
DSPLL™ technology provides PLL functionality with unparalleled performance. It
eliminates external loop filter components, provides programmable loop parameters,
and simplifies design. FEC rates are supported by selectable forward and reverse 255/
238 (15/14), 255/237 (85/79), and 66/64 (33/32) conversion factors. The ITU-T G.709
255/237 rate and the IEEE 802.3ae 66/64 rate are supported when using a 155 MHz or
higher rate input clock. The performance and integration of Silicon Laboratories’ Si5321
clock IC provides high-level support of the latest specifications and systems. It operates
from a single 3.3 V supply.
Functional Block Diagram
REXT
VSEL33
V DD
GND
Biasing & Supply Regulation
FXDDELAY
CLKIN+
CLKIN–
VALTIME
LOS
CAL_ACTV
÷
2
DH_ACTV
DSPLL™
÷
CLKOUT+
CLKOUT–
2
Signal
Detect
3
2
2
Calibration
FRQSEL[2:0]
RSTN/CAL
BWBOOST
BWSEL[1:0]
INFRQSEL[2:0] FEC[2:0]
Rev. 2.2 7/04
Copyright © 2004 by Silicon Laboratories
Si5321
Si5321
2
Rev. 2.2
Si5321
TA B L E O F C O N T E N TS
SECTION
PAGE
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1. DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.5. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3. Pin Descriptions: Si5321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 2.2
3
Si5321
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5321 Supply Voltage3, 3.3 V Supply
Symbol
Test Condition
Min1
Typ
Max1
Unit
TA
–202
25
85
°C
VDD33
3.135
3.3
3.465
V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. The Si5321 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient
temperature of –20 to 85° C.
3. The Si5321 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of Figure 5 on page 16.
4
Rev. 2.2
Si5321
C LKIN +
C LKIN –
V IS
A. O peration with Single-Ended C lock Input*
N ote: W hen using single-ended clock sources, the unused clock
input on the Si5321 m ust be ac-coupled to ground.
C LKIN +
0.5 V ID
C LKIN –
(C LKIN+) – (C LKIN –)
V ID
B. O peration with D ifferential C lock Input
N ote: Transm ission line term ination, when required, m ust be provided
externally.
Figure 1. CLKIN Voltage Characteristics
80%
20%
tF
tR
Figure 2. Rise/Fall Time Measurement
(C L K IN + ) - (C L K IN - )
0 V
tL O S
Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition
Rev. 2.2
5
Si5321
Table 2. DC Characteristics, VDD = 3.3 V
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current 1
IDD
622.08 MHz In,
19.44 MHz Out
—
141
155
mA
Supply Current 2
IDD
19.44 MHz In,
622.08 MHz Out
—
135
145
mA
Power Dissipation Using 3.3 V Supply
Clock Output
PD
19.44 MHz In,
622.08 MHz Out
—
445
479
mW
1.0
1.5
2.0
V
Common Mode Input
(CLKIN)
Voltage1,2,3
VICM
Single-Ended Input Voltage2,3,4
(CLKIN)
VIS
See Figure 1A
200
—
5004
mVPP
Differential Input Voltage Swing2,3,4
(CLKIN)
VID
See Figure 1B
200
—
5004
mVPP
Input Impedance
(CLKIN+, CLKIN–)
RIN
—
80
—
kΩ
Differential Output Voltage Swing
(CLKOUT)
VOD
100 Ω Load
Line-to-Line
750
825
1100
mVPP
Output Common Mode Voltage
(CLKOUT)
VOCM
100 Ω Load
Line-to-Line
1.4
1.8
2.2
V
Output Short to GND (CLKOUT)
ISC(–)
–60
—
—
mA
Output Short to VDD25 (CLKOUT)
ISC(+)
—
15
—
mA
Input Voltage Low (LVTTL Inputs)
VIL
—
—
0.8
V
Input Voltage High (LVTTL Inputs)
VIH
2.0
—
—
V
Input Low Current (LVTTL Inputs)
IIL
—
—
50
µA
Input High Current (LVTTL Inputs)
IIH
—
—
50
µA
Internal Pulldowns (LVTTL Inputs)
Ipd
—
—
50
µA
Input Impedance (LVTTL Inputs)
RIN
50
—
—
kΩ
Output Voltage Low (LVTTL Outputs)
VOL
IO = 0.5 mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs)
VOH
IO = 0.5 mA
2.0
—
—
V
Notes:
1. The Si5321 device provides weak 1.5 V internal biasing that enables ac-coupled operation.
2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be accoupled to ground.
3. Transmission line termination, when required, must be provided externally.
4. Although the Si5321 device can operate with input clock swings as high as 1500 mVPP, Silicon Laboratories recommends
maintaining the input clock amplitude below 500 mVPP for optimal performance.
6
Rev. 2.2
Si5321
Table 3. AC Characteristics
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Input Clock Frequency (CLKIN)
FEC[2:0] = 000 (non FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
fCLKIN
No FEC Scaling
Input Clock Frequency (CLKIN)
FEC[2:0] = 001 (forward FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
fCLKIN
Input Clock Frequency (CLKIN)
FEC[2:0] = 010 (reverse FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
fCLKIN
Input Clock Frequency (CLKIN)
FEC[2:0] = 100 (forward FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
fCLKIN
Input Clock Frequency (CLKIN)
FEC[2:0] = 101 (reverse FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
fCLKIN
Min
Typ
Max
19.436
38.872
77.744
155.48
310.97
621.95
—
—
—
—
—
—
21.685
43.369
86.738
173.48
346.95
693.90
18.142
36.284
72.568
145.13
290.27
580.54
—
—
—
—
—
—
20.239
40.478
80.955
161.91
323.82
647.64
20.826
41.652
83.305
166.61
333.22
666.44
—
—
—
—
—
—
23.234
46.465
92.934
185.87
371.74
743.47
N/A
N/A
N/A
144.52
289.05
578.11
N/A
N/A
N/A
—
—
—
N/A
N/A
N/A
161.23
322.46
644.92
N/A
N/A
N/A
167.31
334.62
669.25
N/A
N/A
N/A
—
—
—
N/A
N/A
N/A
186.66
373.31
746.61
Unit
MHz
255/238 FEC Scaling
MHz
238/255 FEC Scaling
255/237 FEC Scaling
Minimum input frequency
is in the 155 MHz range
237/255 FEC Scaling
Minimum input frequency
is in the 155 MHz range
MHz
MHz
MHz
Note: The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function
with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 for
FEC rate conversion.
Rev. 2.2
7
Si5321
Table 3. AC Characteristics (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Input Clock Frequency (CLKIN)
FEC[2:0] = 110 (forward FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
fCLKIN
66/64 FEC Scaling
Minimum input frequency
is in the 155 MHz range
Input Clock Frequency (CLKIN)
FEC[2:0] = 111 (reverse FEC)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
fCLKIN
Input Clock Rise Time (CLKIN)
tR
Input Clock Fall Time (CLKIN)
tF
Input Clock Duty Cycle
CLKOUT Frequency Range
FRQSEL[2:0] = 001
FRQSEL[2:0] = 000
FRQSEL[2:0] = 100
FRQSEL[2:0] = 010
FRQSEL[2:0] = 101
FRQSEL[2:0] = 011
FRQSEL[2:0] = 110
FRQSEL[2:0] = 111
Min
Typ
Max
N/A
N/A
N/A
150.79
301.58
603.16
N/A
N/A
N/A
—
—
—
N/A
N/A
N/A
168.22
336.44
672.88
N/A
N/A
N/A
160.36
320.72
641.46
N/A
N/A
N/A
—
—
—
N/A
N/A
N/A
178.90
357.80
715.59
Figure 2
—
—
11
ns
Figure 2
—
—
11
ns
CDUTY_IN
40
50
60
%
fO_19
fO_39
fO_78
fO_155
fO_311
fO_622
fO_1250
fO_2500
19.436
38.872
77.744
155.48
310.97
621.95
1243.9
2487.8
—
—
—
—
—
—
—
—
21.685
43.369
86.738
173.48
346.95
693.90
1387.8
2775.6
64/66 FEC Scaling
Minimum input frequency
is in the 155 MHz range
Unit
MHz
MHz
MHz
CLKOUT Rise Time
tR
Figure 2; single-ended;
after 3 cm of 50 Ω FR4
stripline
—
190
220
ps
CLKOUT Fall Time
tF
Figure 2; single-ended;
after 3 cm of 50 Ω FR4
stripline
—
185
205
ps
Output Clock Duty Cycle
CDUTY_OUT
Differential:
(CLKOUT+) – (CLKOUT–)
48
—
52
%
RSTN/CAL Pulse Width
tRSTN
20
—
—
ns
Note: The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function
with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 for
FEC rate conversion.
8
Rev. 2.2
Si5321
Table 3. AC Characteristics (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Transitionless Period Required
on CLKIN for Detecting a LOS
Condition.
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
tLOS
Figure 3
Recovery Time for Clearing an
LOS Condition
VALTIME = 0
VALTIME = 1
tVAL
Min
Typ
/fo_622
/fo_622
12/
fo_622
10
/fo_622
9
/fo_622
8/
fo_622
—
—
—
—
—
—
1.6
90
—
—
24
16
Measured from when a
valid reference clock is
applied until the LOS flag
clears
Max
Unit
32
/fo_622
/fo_622
32/
fo_622
32
/fo_622
32
/fo_622
32/
fo_622
32
3.2
220
s
ms
Note: The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function
with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 for
FEC rate conversion.
Rev. 2.2
9
Si5321
Table 4. AC Characteristics (PLL Performance Characteristics)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
f = 8 Hz
1000
—
—
ns
f = 80 Hz
100
—
—
ns
f = 800 Hz
10
—
—
ns
12 kHz to 20 MHz
—
0.9
1.2
ps
50 kHz to 80 MHz
—
0.27
0.35
ps
12 kHz to 20 MHz
—
0.9
1.2
ps
50 kHz to 80 MHz
—
0.27
0.35
ps
12 kHz to 20 MHz
—
7.6
11
ps
50 kHz to 80 MHz
—
3.6
10.0
ps
12 kHz to 20 MHz
—
6.7
9.2
ps
50 kHz to 80 MHz
—
3.0
10.0
ps
Wander/Jitter at 800 Hz Bandwidth
(BWSEL[1:0] = 10 and BWBOOST = 0)
Jitter Tolerance (see Figure 7)
JTOL(PP)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
JGEN(RMS)
CLKOUT RMS Jitter Generation
FEC[2:0] = 001, 010, 100, 101, 110, 111
JGEN(RMS)
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
JGEN(PP)
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 001, 010, 100, 101, 110, 111
JGEN(PP)
Jitter Transfer Bandwidth (see Figure 6)
FBW
BW = 800 Hz
—
800
—
Hz
JP
< 800 Hz
—
0.0
0.05
dB
f = 16 Hz
500
—
—
ns
f = 160 Hz
50
—
—
ns
f = 1600 Hz
5
—
—
ns
12 kHz to 20 MHz
—
.80
1.0
ps
50 kHz to 80 MHz
—
.25
.30
ps
12 kHz to 20 MHz
—
6.4
10.0
ps
50 kHz to 80 MHz
—
3.0
5.0
ps
FBW
BW = 1600 Hz
—
1600
—
Hz
JP
< 1600 Hz
—
0.0
0.05
dB
Wander/Jitter Transfer Peaking
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 10 and BWBOOST = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
JGEN(RMS)
JGEN(PP)
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5321 (tPT_MTIE) never reaches one nanosecond.
10
Rev. 2.2
Si5321
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
JTOL(PP)
f = 16 Hz
1000
—
—
ns
f = 160 Hz
100
—
—
ns
f = 1600 Hz
10
—
—
ns
12 kHz to 20 MHz
—
0.8
1.2
ps
50 kHz to 80 MHz
—
0.27
0.35
ps
12 kHz to 20 MHz,
—
0.9
1.2
ps
50 kHz to 80 MHz,
—
0.27
0.35
ps
12 kHz to 20 MHz,
—
6.7
10.0
ps
50 kHz to 80 MHz,
—
3.0
5.0
ps
12 kHz to 20 MHz,
—
6.5
10.0
ps
50 kHz to 80 MHz,
—
3.0
5.0
ps
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 01 and BWBOOST = 0)
Jitter Tolerance (see Figure 9)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
JGEN(RMS)
CLKOUT RMS Jitter Generation
FEC[2:0] = 001, 010, 100, 101, 110, 111
JGEN(RMS)
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
JGEN(PP)
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 001, 010, 100, 101, 110, 111
JGEN(PP)
Jitter Transfer Bandwidth (see Figure 6)
FBW
BW = 1600 Hz
—
1600
—
Hz
JP
< 1600 Hz
—
0.0
0.1
dB
f = 32 Hz
500
—
—
ns
f = 320 Hz
50
—
—
ns
f = 3200 Hz
5
—
—
ns
12 kHz to 20 MHz,
—
0.8
1.0
ps
50 kHz to 80 MHz,
—
0.25
0.3
ps
12 kHz to 20 MHz,
—
6.1
10.0
ps
50 kHz to 80 MHz,
—
3.0
5.0
ps
BW = 3200 Hz
—
3200
—
Hz
Wander/Jitter Transfer Peaking
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 01 and BWBOOST = 1)
Jitter Tolerance (see figure 7)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
Jitter Transfer Bandwidth (see Figure 6)
JGEN(RMS)
JGEN(PP)
FBW
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5321 (tPT_MTIE) never reaches one nanosecond.
Rev. 2.2
11
Si5321
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Wander/Jitter Transfer Peaking
Symbol
Test Condition
Min
Typ
Max Unit
JP
< 3200 Hz
—
0.05
0.1
dB
JTOL(PP)
f = 32 Hz
1000
—
—
ns
f = 320 Hz
100
—
—
ns
f = 3200 Hz
10
—
—
ns
12 kHz to 20 MHz
—
0.9
1.1
ps
50 kHz to 80 MHz
—
0.3
0.4
ps
12 kHz to 20 MHz
—
0.85
1.1
ps
50 kHz to 80 MHz
—
0.3
0.45
ps
12 kHz to 20 MHz
—
7.1
10.0
ps
50 kHz to 80 MHz
—
3.2
5.0
ps
12 kHz to 20 MHz
—
6.6
11.0
ps
50 kHz to 80 MHz
—
3.2
5.5
ps
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 00 and BWBOOST= 0)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
JGEN(RMS)
CLKOUT RMS Jitter Generation
FEC[2:0] = 001, 010, 100,101, 110, 111
JGEN(RMS)
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
JGEN(PP)
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 001, 010, 100,101, 110, 111
JGEN(PP)
Jitter Transfer Bandwidth (see Figure 6)
FBW
BW = 3200 Hz
—
3200
—
Hz
JP
< 3200 Hz
—
0.05
0.1
dB
f = 64 Hz
500
—
—
ns
f = 640 Hz
50
—
—
ns
f = 6400 Hz
5
—
—
ns
12 kHz to 20 MHz
—
0.75
0.95
ps
50 kHz to 80 MHz
—
0.27
0.35
ps
12 kHz to 20 MHz
—
6.1
10.0
ps
50 kHz to 80 MHz
—
3.1
5.0
ps
FBW
BW = 6400 Hz
—
6400
—
Hz
JP
< 6400 Hz
—
0.05
0.1
dB
Wander/Jitter Transfer Peaking
Wander/Jitter at 6400 Hz Bandwidth
(BWSEL[1:0] = 00 and BWBOOST = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
JGEN(RMS)
JGEN(PP)
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5321 (tPT_MTIE) never reaches one nanosecond.
12
Rev. 2.2
Si5321
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
JTOL(PP)
f = 64 Hz
1000
—
—
ns
f = 640 Hz
100
—
—
ns
f = 6400 Hz
10
—
—
ns
12 kHz to 20 MHz
—
1.0
1.3
ps
50 kHz to 80 MHz
—
0.4
.55
ps
12 kHz to 20 MHz
—
1.0
1.5
ps
50 kHz to 80 MHz
—
.45
0.7
ps
12 kHz to 20 MHz
—
9.3
13.0
ps
50 kHz to 80 MHz
—
4.1
6.0
ps
12 kHz to 20 MHz
—
8.0
20.0
ps
50 kHz to 80 MHz
—
4.0
7.5
ps
Wander/Jitter at 6400 Hz Bandwidth
(BWSEL[1:0] = 11 and BWBOOST = 0)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
JGEN(RMS)
CLKOUT RMS Jitter Generation
FEC[2:0] = 001, 010, 100,101, 110, 111
JGEN(RMS)
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
JGEN(PP)
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 001, 010, 100,101, 110, 111
JGEN(PP)
Jitter Transfer Bandwidth (see Figure 6)
FBW
BW = 6400 Hz
—
6400
—
Hz
JP
< 6400 Hz
—
0.05
0.1
dB
f = 128 Hz
500
—
—
ns
f = 1280 Hz
50
—
—
ns
f = 12800 Hz
5
—
—
ns
12 kHz to 20 MHz
—
.85
1.2
ps
50 kHz to 80 MHz
—
.35
.55
ps
12 kHz to 20 MHz
—
6.8
11.0
ps
50 kHz to 80 MHz
—
3.4
5.5
ps
FBW
BW = 12,800 Hz
—
12800
—
Hz
JP
< 12,800 Hz
—
0.05
.1
dB
TAQ
RSTN/CAL high to
CAL_ACTV low, with valid
clock input and VALTIME = 0
—
300
350
ms
Wander/Jitter Transfer Peaking
Wander/Jitter at 12800 Hz Bandwidth
(BWSEL[1:0] = 11 and BWBOOST = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
FEC[2:0] = 000
CLKOUT Peak-Peak Jitter Generation
FEC[2:0] = 000
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Acquisition Time
JGEN(RMS)
JGEN(PP)
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5321 (tPT_MTIE) never reaches one nanosecond.
Rev. 2.2
13
Si5321
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Clock Output Wander with
Temperature Gradient 1,2
CCO_TG
Stable Input Clock;
Temperature
Gradient <10 °C/min;
800 Hz Loop BW
—
—
45
ps/
°C/
min
Initial Frequency Accuracy in Digital Hold
Mode (first 100 ms with voltage and
temperature held constant)
CDH_FA
Stable Input Clock
Selected until entering
Digital Hold
—
—
5.5
ppm
Clock Output Frequency Accuracy Over
Temperature in Digital Hold Mode
CDH_T
Constant Supply Voltage
—
17.2
30
ppm
/°C
Clock Output Frequency Accuracy Over
Supply Voltage in Digital Hold Mode
CDH_V33
Constant Temperature
—
—
600
ppm
/V
Clock Output Phase Step3(See Figure 8)
tPT_MTIE
When hitlessly recovering
from Digital Hold mode
–200
0
200
ps
mPT
When hitlessly recovering
from Digital Hold mode
—
—
—
—
—
—
—
—
10
5
2.5
1.25
ps/
µs
Clock Output Phase Step Slope3
(See Figure 8)
BWSEL[1:0] = 11, BWBOOST = 0
BWSEL[1:0] = 00, BWBOOST = 0
BWSEL[1:0] = 01, BWBOOST = 0
BWSEL[1:0] = 10, BWBOOST = 0
6400 Hz, No Scaling
3200 Hz, No Scaling
1600 Hz, No Scaling
800 Hz, No Scaling
Max Unit
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5321 (tPT_MTIE) never reaches one nanosecond.
14
Rev. 2.2
Si5321
Table 5. Absolute Maximum Ratings
Parameter
3.3 V DC Supply Voltage
LVTTL Input Voltage
Symbol
Value
Unit
VDD33
–0.5 to 3.6
V
VDIG
–0.3 to (VDD33 + 0.3)
V
±50
mA
Maximum Current any output PIN
Operating Junction Temperature
TJCT
–55 to 150
°C
Storage Temperature Range
TSTG
–55 to 150
°C
1.0
kV
ESD HBM Tolerance (100 pf, 1.5 kΩ)
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
Test Condition
Value
Unit
ϕJA
Still Air
20
°C/W
0
Phase Noise (dBc/Hz)
-20
-40
-60
-80
-100
-120
-140
-160
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
Offset Frequency
Figure 4. Typical Si5321 Phase Noise (CLKIN = 155.52 MHz, CLKOUT = 622.08 MHz, and
Loop BW = 800 Hz)
Rev. 2.2
15
Si5321
3.3 V Supply
Ferrite Bead
0.1 µF
2200 pF
22 pF
10 kΩ1%
Input Clock Source
FEC Scaling Select
PLL Bandwidth Select
PLL Bandwidth Multiplier
LOS Validation Time
Powerdown Control
Fixed Delay Mode Control
GND
Calibration Active
Status Output
CAL_ACTV
100 Ω
0.1 µF
CLKOUT+
CLKIN–
0.1 µF
Input Clock Frequency Select
VDD25
VDD33
CLKIN+
REXT
0.1 µF
VSEL33
33 µF
CLKOUT–
INFRQSEL[2:0]
FEC[2:0]
Si5321
Clock Output
0.1 µF
FRQSEL[2:0]
BWSEL[1:0]
BWBOOST
VALTIME
LOS
PWRDN/CAL
DH_ACTV
FXDDELAY
Figure 5. Si5321 Typical Application Circuit (3.3 V Supply)
16
Clock Output
Frequency Select
Rev. 2.2
Loss of Signal (LOS)
Digital Hold Active
Si5321
2. Functional Description
The Si5321 is a high-performance precision clock
multiplication and clock generation device. This device
accepts a clock input in the 19, 39, 78, 155, 311, or
622 MHz range, attenuates significant amounts of jitter,
and multiplies the input clock frequency to generate a
clock output in the 19, 39, 78, 155, 311, 622, 1250, or
2500 MHz range. Additional forward or reverse clock
rate scaling by a factor of 255/238, 255/237, or 66/64 is
provided. This allows systems to easily provide clocks
that are scaled for forward error correction (FEC) rates.
The 255/238 and 255/237 factors support the ITU-T
G.709 requirements for optical transport unit (OTU) OC48 and OC-192 rates. The 66/64 factor allows
conversion between XSBI and 10 GbE Base R rates.
Typical applications for the Si5321 in SONET/SDH
systems are generation and/or cleaning of 19.44, 38.88,
77.76, 155.52, 311.04, 622.08, 1244.16, or
2488.32 MHz clocks from 19.44, 38.88, 77.76, 155.52,
311.04, or 622.08 MHz clock sources.
The Si5321 employs Silicon Laboratories DSPLL™
technology to provide excellent jitter performance while
minimizing the external component count and
maximizing flexibility and ease of use. The Si5321
DSPLL phase locks to the input clock signal, attenuates
jitter, and multiplies the clock frequency to generate the
device’s SONET/SDH-compliant clock output. The
DSPLL loop bandwidth is user selectable, allowing
Si5321 jitter performance optimization for different
applications. The Si5321 can produce a clock output
with jitter generation as low as 0.3 psRMS (see Table 4
on page 10), making the device an ideal solution for
clock multiplication in SONET/SDH (including OC-48,
OC-192, and OC768), Gigabit Ethernet, and 10 GbE
systems.
The Si5321 monitors the clock input signal for loss-ofsignal and provides a loss-of-signal (LOS) alarm when it
detects missing pulses. The Si5321 provides a digital
hold capability that allows the device to continue
generation of a stable output clock when the input
reference is lost.
2.1. DSPLL™
The Si5321’s phase-locked loop (PLL) uses Silicon
Laboratories' DSPLL technology to eliminate jitter,
noise, and the need for external loop filter components
found in traditional PLL implementations. This is
achieved by using a digital signal processing (DSP)
algorithm to replace the loop filter commonly found in
analog PLL designs. This algorithm processes the
phase detector error term and generates a digital
control value to adjust the frequency of the voltage-
controlled oscillator (VCO). The technology produces
low phase noise clocks with less jitter than is generated
using traditional methods. See Figure 4 for an example
phase noise plot. In addition, because external loop
filter components are not required, sensitive noise entry
points are eliminated thus making the DSPLL less
susceptible to board-level noise sources. This digital
technology also provides highly-stable and consistent
operation over all process, temperature, and voltage
variations. The benefits are smaller, lower power,
cleaner, reliable, and easy-to-use clock circuits.
2.1.1. Selectable Loop Filter Bandwidth
The digital characteristics of the DSPLL loop filter allow
control of the loop filter parameters without the need to
change external components. The Si5321 provides the
user with up to eight user-selectable loop bandwidth
settings for different system requirements. The base
loop bandwidth is selected using the BWSEL[1:0] pins
along with BWBOOST = 0 pins. When the BWBOOST
is driven high, the bandwidth selected on the
BWSEL[1:0] pins is doubled. (See Table 7.)
When the BWBOOST pin is asserted, the Si5321 shows
improved jitter generation performance. The BWBOOST
function is defined only when hitless recovery and FEC
scaling are disabled. Therefore, when BWBOOST is
high, the user must also drive FXDDELAY high and
FEC[1:0] to 000 for proper operation.
2.2. Clock Input and Output Rate Selection
The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x,
1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock frequency
multiplication function with an option for additional
frequency scaling by a factor of 255/238, 238/255, 255/
237, 237/255, 66/64, or 64/66 for FEC rate compatibility.
Output rates vary in accordance with the input clock
rate. The multiplication factor is configured by selecting
the input and output clock frequency ranges for the
device.
The Si5321 accepts an input clock in the 19, 38, 77,
155, 311, or 622 MHz frequency range. The input
frequency range is selected using the INFRQSEL[2:0]
pins. The INFRQSEL[2:0] settings and associated
output clock rates are listed in Table 8.
The Si5321’s DSPLL phase locks to the clock input
signal to generate an internal VCO frequency that is a
multiple of the input clock frequency. The internal VCO
frequency is divided down to produce a clock output in
the 19, 39, 78, 155, 311, 622, 1250, or 2500 MHz
frequency range. The clock output range is selected
using the frequency select (FRQSEL[2:0]) pins. The
FRQSEL[2:0] settings and associated output clock rates
are given in Table 9.
Rev. 2.2
17
Si5321
The Si5321 clock input frequencies are variable within
the range specified in Table 3 on page 7. The output
rates are scaled accordingly. If a 19.44 MHz input clock
is used, the clock output frequency is 19.44, 38.88,
77.76, 155.52 MHz, etc.
Table 7. Loop Bandwidth and FEC Settings
External Inputs
BWSEL
FEC
BWBOOST [1:0]
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
18
00
00
00
00
00
00
00
00
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
00
10
11
01
01
01
01
01
01
01
01
01
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0xx
0xx
0xx
0xx
000
001
010
011
100
101
110
111
Effective
FEC
Conversion
Rate
Effective
PLL
Bandwidth
(Hz)
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
1/1
1/1
1/1
1/1
1/1
255/238
238/255
Reserved
255/237
237/255
66/64
64/66
3200
3200
3200
—
3200
3200
3200
3200
800
800
800
—
800
800
800
800
6400
6400
6400
—
6400
6400
6400
6400
6400
1600
12800
3200
1600
1600
1600
—
1600
1600
1600
1600
Table 8. Nominal Clock Input Frequencies
Input Clock
Frequency
Range
Reserved
622 MHz
311 MHz
155 MHz
77 MHz
38 MHz
19 MHz
Reserved
INFRQSEL2 INFRQSEL1 INFRQSEL0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Table 9. Nominal Clock Output Frequencies
Output Clock
Frequency
Range
2,488.32 MHz
1244.16 MHz
622.08 MHz
311.04 MHz
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
FRQSEL2
FRQSEL1
FRQSEL0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
2.2.1. FEC Rate Conversion
The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x,
1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock frequency
multiplication function with an option for additional
forward or reverse frequency scaling by a factor of 255/
238 (15/14), 255/237 (85/79), or 66/64 (33/32) for FEC
rate conversion applications. The 255/237 and the 66/
64 rate conversions requires the input clock rate to be in
the 155 MHz or higher ranges. The multiplication factor
is configured by selecting the input and output clock
frequency ranges for the device. The additional
frequency scaling for FEC rate conversion is selected
using the FEC[2:0] control inputs.
For example, a 622.08 MHz output clock (a non-FEC
rate) can be generated from a 19.44 MHz input clock (a
non-FEC rate) by setting INFRQSEL[2:0] = 001
(19.44 MHz range), setting FRQSEL[2:0] = 011 (32x
multiplication) and setting FEC[2:0] = 000 (no FEC
scaling). A 666.51 MHz output clock (an FEC rate) can
be generated from a 19.44 MHz input clock (a non-FEC
rate) by setting INFRQSEL[2:0] = 001 (19.44 MHz
range), setting FRQSEL[2:0] = 011 (32x multiplication)
Rev. 2.2
Si5321
and setting FEC[2:0] = 001 (255/238 FEC scaling).
.
Finally, a 622.08 MHz output clock (a non-FEC rate) can
be generated from a 20.83 MHz input clock (an FEC
rate) by setting INFRQSEL[2:0] = 001 (19.44 MHz
range), setting FRQSEL[2:0] = 011 (32x multiplication)
and setting FEC[2:0] = 010 (238/255 FEC scaling).
Jitter
Transfer
Jitter Out
(s)
Jitter In
0 dB
Jp
Peaking
–20 dB/dec.
2.3. PLL Performance
The Si5321 PLL provides extremely low jitter
generation, high jitter tolerance, and a well-controlled
jitter transfer function with low peaking and a high
degree of jitter attenuation.
FBW
fJitter
Figure 6. PLL Jitter Transfer Mask/Template
2.3.1. Jitter Generation
2.3.3. Jitter Tolerance
Jitter generation is defined as the amount of jitter
produced at the output of the device with a jitter free
input clock. Generated jitter arises from sources within
the VCO and other PLL components. Jitter generation is
a function of the PLL bandwidth setting. Higher loop
bandwidth settings may result in lower jitter generation
but may also result in less attenuation of jitter than
might be present on the input clock signal.
Jitter tolerance for the Si5321 is defined as the
maximum peak-to-peak sinusoidal jitter that can be
present on the incoming clock. The tolerance is a
function of the jitter frequency because tolerance
improves for lower input jitter frequency.
2.3.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of
input clock jitter that passes to the outputs. The DSPLL
technology used in the Si5321 provides tightlycontrolled jitter transfer curves because the PLL gain
parameters are determined by digital circuits that do not
vary over supply voltage, process, and temperature. In
a system application, a well-controlled transfer curve
minimizes the output clock jitter variation from board to
board and provides more consistent system level jitter
performance.
The jitter transfer characteristic is a function of the
BWSEL[1:0] setting. Lower bandwidth settings result in
more jitter attenuation of the incoming clock but may
result in higher jitter generation. Table 4 on page 10
gives the 3 dB bandwidth and peaking values for
specified BWSEL settings. Figure 6 shows the jitter
transfer curve mask.
Input
Jitter
Am plitude
–20 dB/dec.
Excessive Input Jitter Range
10 ns
F BW
f Jitter In
Figure 7. Jitter Tolerance Mask/Template
2.4. Loss-of-Signal Alarm
The Si5321 has loss-of-signal (LOS) circuitry that
constantly monitors the CLKIN input clock for missing
pulses. The LOS circuitry sets a LOS output alarm
signal when missing pulses are detected.
The LOS circuitry operates as follows. Regardless of
the selected input clock frequency range, the LOS
circuitry divides down the input clock into the 19 MHz
range. The LOS circuitry then over-samples this divided
down input clock to search for extended periods of time
without input clock transitions. If the LOS circuitry
detects four consecutive samples of the divided down
input clock that are the same state (i.e., 1111 or 0000), a
LOS condition is declared; the Si5321 goes into digital
hold mode, and the LOS output alarm signal is set high.
The LOS sampling circuitry runs at a frequency of fO_78,
where fO_78 is the output clock frequency when the
FRQSEL[2:0] pins are set to 100. Figure 3 on page 5
and Table 3 on page 7 list the minimum and maximum
transitionless time periods required for declaring a LOS
on the input clock (tLOS).
Rev. 2.2
19
Si5321
Once the LOS alarm is asserted, it is held high until the
input clock is validated over a time period designated by
the VALTIME pin. When VALTIME is low, the validation
time period is about 1 ms. When VALTIME is high, the
validation time period is about 100 ms. If another LOS
condition is detected on the input clock during the
validation time (i.e., if another set of 1111 or 0000
samples are detected), the LOS alarm remains asserted
and the validation time starts over. When the LOS alarm
is finally released, the Si5321 exits digital hold mode
and locks to the input clock. The LOS alarm is
automatically set high at power-on and at every low-tohigh transition of the RSTN/CAL pin. In these cases, the
Si5321 undergoes a self-calibration before releasing the
LOS alarm and locking to the input clock.
The Si5321 also provides an output indicating the digital
hold status of the device, DH_ACTV. The Si5321 only
enters the digital hold mode upon the loss of the input
clock. When this occurs, the LOS alarm will also be
active. Therefore, applications that require monitoring of
the status of the Si5321 need only monitor the
CAL_ACTV and either the LOS or DH_ACTV outputs to
know the state of the device.
2.5. Digital Hold of the PLL
When no valid input clock is available, the Si5321
digitally holds the internal oscillator to its last frequency
value. This provides a stable clock to the system until an
input clock is valid again. This clock maintains stable
operation in the presence of constant voltage and
temperature. The frequency accuracy specifications for
digital hold mode are given in Table 4 on page 10.
2.6. Hitless Recovery from Digital Hold
When the Si5321 device is locked to a valid input clock,
a loss of the input clock switches the device to digital
hold mode. When the input clock signal returns, the
device performs a hitless transition from digital hold
mode back to the selected input clock. That is, the
device executes “phase build-out” to absorb the phase
difference between the internal VCO clock operating in
digital hold mode and the new/returned input clock. The
maximum phase step seen at the clock output during
this transition, and the maximum slope of this step, is
specified in Table 4 on page 10.
Asserting the Fixed Delay (FXDDELAY) pin disables
this feature and the output clock phase and frequency
locks with a known phase relationship to the input clock.
Consequently, abrupt phase change on the input clock
propagates through the device and the output slews at
the loop bandwidth until the phase relationship is
restored.
20
mPT
tPT_MTIE
Recovery from digital hold
Figure 8. Recovery from Digital Hold
2.7. Reset
The Si5321 provides a Reset/Calibration pin (RSTN/
CAL) that resets the device and disables all of the
device outputs. When the RSTN/CAL pin is driven low,
the internal circuitry enters reset mode and all LVTTL
outputs are forced into a high-impedance state. Also,
the CLKOUT+ and CLKOUT– pins are connected to
VDD25 through 100 Ω on-chip resistors. This feature is
useful for applications that employ redundant clock
sources and for in-circuit test applications. A low-to-high
transition on RSTN/CAL initializes all digital logic to a
known condition and initiates self-calibration of the
DSPLL. At the completion of self-calibration, the DSPLL
begins to lock to the clock input signal.
2.8. PLL Self-Calibration
The Si5321 achieves optimal jitter performance by
using self-calibration circuitry to set the VCO center
frequency and loop gain parameters within the DSPLL.
Internal circuitry generates self calibration automatically
on powerup or after a loss-of-power condition. Selfcalibration also can be manually initiated by a low-tohigh transition on the RSTN/CAL input.
A self-calibration should be initiated after changing the
state of the FEC[2:0] inputs. Whether manually initiated
or automatically initiated at powerup, the self-calibration
process requires the presence of a valid input clock.
If the self-calibration is initiated without a valid input
clock, the device waits for a valid input clock before
executing the self-calibration. The Si5321 does not
provide an output clock while waiting for a valid input
clock or while executing its self-calibration. When the
input clock is validated, the calibration procedure
executes to completion; the device locks to the input
clock, and the output clock turns on. Subsequent losses
of the input clock do not require self-calibration. If the
input clock is lost following self-calibration, the device
enters digital hold mode with the output clock frequency
held to its last value before the LOS condition was
Rev. 2.2
Si5321
detected. When the input clock returns and is validated,
the device exits digital hold mode by re-locking to the
input clock without executing another self-calibration.
2.9. Bias Generation Circuitry
The Si5321 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents, which significantly
reduces power consumption and variation as compared
with traditional implementations that use an internal
resistor. The bias generation circuitry requires a 10 kΩ
(1%) resistor connected between REXT and GND.
2.10. Differential Input Circuitry
The Si5321 provides a differential input for the clock
input, CLKIN. This input is internally-biased to a voltage
of VICM (see Table 2 on page 6) and may be driven by a
differential or single-ended driver circuit. For
transmission line termination, the termination resistor is
connected externally as shown.
2.11. Differential Output Circuitry
The Si5321 utilizes a current mode logic (CML)
architecture to drive the differential clock output,
CLKOUT.
For single-ended output operation simply connect to
either CLKOUT+ or CLKOUT– and leave the unused
signal unconnected.
2.12. Power Supply Connections
The Si5321 incorporates an on-chip voltage regulator to
power the device from a 3.3 V supply. The voltage
regulator requires an external compensation circuit of
one resistor and one capacitor to ensure stability over
all operating conditions.
Internally, the Si5321 VDD33 pins are connected to the
on-chip voltage regulator input and to the device’s
LVTTL I/O circuitry. The VDD25 pins supply power to the
core DSPLL circuitry, and are also used for connection
of the external compensation circuit.
The regulator’s compensation circuit is a resistor and a
capacitor in series between the VDD25 node and ground.
Typically, the resistor is incorporated into the capacitor’s
equivalent series resistance (ESR). The target RC time
constant for this combination is 15 to 50 µs. The
capacitor used in the Si5321 evaluation board is a 33 µf
tantalum capacitor with an ESR of 0.8 Ω. This gives an
RC time constant of 26.4 µs. The Venkel part number
TA6R3TCR336KBR is an example of a capacitor that
meets these specifications. (See Figure 5.)
To get optimal performance from the Si5321 device, the
power supply noise spectrum must comply with the plot
in Figure 9. This plot shows the power supply noise
tolerance mask for the Si5321. The customer should
provide a 3.3 V supply that does not have noise density
in excess of the amount shown in the diagram.
However, the diagram cannot be used as spur criteria
for a power supply that contains single tone noise.
Vn (µV/√Hz)
2100
42
f
10 kHz
100 Mhz
500 kHz
Figure 9. Power Supply Noise Tolerance Mask
Rev. 2.2
21
Si5321
2.13. Design and Layout Guidelines
Precision clock circuits are susceptible to board noise
and EMI. To take precautions against unacceptable
levels of board noise and EMI affecting performance of
the Si5321, consider the following:
„
„
„
„
„
22
Power the device from 3.3 V since the internal
regulator provides >40 dB of isolation to the VDD25
pins (which power the PLL circuitry).
When powering the device from 3.3 V, use an
isolated, local plane to connect the VDD25 pins.
Avoid running signal traces over or below this plane
without a ground plane in between.
Route all I/O traces between ground planes as much
as possible
Maintain an input clock amplitude in the 200 mVPP to
500 mVPP differential range.
Excessive high-frequency harmonics of the input
clock should be minimized. The use of filters on the
input clock signal can be used to remove highfrequency harmonics.
Rev. 2.2
Si5321
3. Pin Descriptions: Si5321
8
7
6
5
4
3
2
1
Rsvd_NC
Rsvd_NC
Rsvd_NC
Rsvd_NC
Rsvd_NC
FEC[0]
FEC[1]
Rsvd_NC
Rsvd_GND
Rsvd_GND
Rsvd_NC
FXDDELAY
FRQSEL[2]
FEC[2]
BWSEL[0]
B
Rsvd_GND
GND
GND
GND
GND
GND
VSEL33
BWSEL[1]
C
DH_ACTV
VDD25
VDD25
VDD33
VDD33
VDD33
BWBOOST
CLKIN+
D
CAL_ACTV
VDD25
VDD25
VDD33
VDD33
VDD33
GND
LOS
VDD25
VDD25
VDD25
VDD25
VDD25
GND
INFRQSEL[0]
F
GND
GND
GND
GND
GND
GND
GND
INFRQSEL[1]
G
FRQSEL[1]
CLKOUT–
CLKOUT+
FRQSEL[0]
VALTIME
RSTN/CAL
REXT
INFRQSEL[2]
H
A
CLKIN–
E
Bottom View
Figure 10. Si5321 Pin Configuration (Bottom View)
Rev. 2.2
23
Si5321
1
A
2
3
4
5
6
7
8
FEC[1]
FEC[0]
Rsvd_NC
Rsvd_NC
Rsvd_NC
Rsvd_NC
Rsvd_NC
B
BWSEL[0]
FEC[2]
FRQSEL[2]
FXDDELAY
Rsvd_NC
Rsvd_GND
Rsvd_GND
Rsvd_NC
C
BWSEL[1]
VSEL33
GND
GND
GND
GND
GND
Rsvd_GND
D
CLKIN+
BWBOOST
VDD33
VDD33
VDD33
VDD25
VDD25
DH_ACTV
E
CLKIN–
GND
VDD33
VDD33
VDD33
VDD25
VDD25
CAL_ACTV
F
INFRQSEL[0]
GND
VDD25
VDD25
VDD25
VDD25
VDD25
LOS
G
INFRQSEL[1]
GND
GND
GND
GND
GND
GND
GND
H
INFRQSEL[2]
REXT
RSTN/CAL
VALTIME
FRQSEL[0]
CLKOUT+
CLKOUT–
FRQSEL[1]
Top View
Figure 11. Si5321 Pin Configuration (Transparent Top View)
24
Rev. 2.2
Si5321
Table 10. Si5321 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
D1
E1
CLKIN+
CLKIN–
I
F1
G1
H1
INFRQSEL[0]
INFRQSEL[1]
INFRQSEL[2]
I*
LVTTL*
Input Frequency Range Select.
Pins(INFRQSEL[2:0]) select the frequency range for
the input clock, CLKIN. (See Table 3 on page 7.)
000 = Reserved.
001 = 19 MHz range.
010 = 38 MHz range.
011 = 77 MHz range.
100 = 155 MHz range.
101 = 311 MHz range.
110 = 622 MHz range.
111 = Reserved.
H6
H7
CLKOUT+
CLKOUT–
O
CML
Differential Clock Output.
High-frequency clock output. The frequency of the
CLKOUT output is a multiple of the frequency of the
CLKIN input. The input-to-output frequency multiplication factor is set by selecting the clock input range
and the clock output range. The frequency of the
CLKOUT clock output can be in the 19, 38, 77, 155,
311, 622, 1244 or 2488 MHz range as indicated in
Table 3 on page 7. The clock output frequency is
selected using the FRQSEL[2:0] pins. The clock
input frequency is selected using the
INFRQSEL[2:0] pins. An additional scaling factor
may be selected for FEC operation using the
FEC[2:0] control pins.
AC Coupled
System Clock Input.
200–500 mVPPD Clock input to the DSPLL circuitry. The frequency of
(See Table 2) the CLKIN signal is multiplied by the DSPLL to generate the CLKOUT clock output. The input-to-output
frequency multiplication factor is set by selecting the
clock input range and the clock output range. The
frequency of the CLKIN clock input can be in the 19,
38, 77, 155, 311, or 622 MHz range (nominally
19.44, 38.88, 77.76, 155.52, 311.04, or
622.08 MHz) as indicated in Table 3 on page 7. The
clock input frequency is selected using the
INFRQSEL[2:0] pins. The clock output frequency is
selected using the FRQSEL[1:0] pins. An additional
scaling factor may be selected for FEC operation
using the FEC[2:0] control pins.
*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
Rev. 2.2
25
Si5321
Table 10. Si5321 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
H5
H8
B3
FRQSEL[0]
FRQSEL[1]
FRQSEL[2]
I*
LVTTL*
Clock Output Frequency Range Select.
Select the frequency range of the clock output, CLKOUT. (See Table 3 on page 7.)
001 = 19 MHz Frequency Range.
000 = 39 MHz Frequency Range.
100 = 78 MHz Frequency Range.
010 = 155 MHz Frequency Range.
101 = 311 MHz Frequency Range.
011 = 622 MHz Frequency Range.
110 = 1.25 GHz Frequency Range.
111 = 2.5 GHz Frequency Range.
A3
A2
B2
FEC[0]
FEC[1]
FEC[2]
I*
LVTTL*
FEC Selection.
Enables or disables scaling of the input-to-output
frequency multiplication factor for FEC clock rate
compatibility.
The frequency of the CLKOUT output is a multiple of
the frequency of the CLKIN input. Selecting the
clock input range, the clock output range, and the
FEC scaling factor sets the input-to-output frequency multiplication factor. The clock output frequency is selected using the FRQSEL[2:0] pins. The
clock input frequency is selected using the
INFRQSEL[2:0] pins. Scaling factors of 255/238,
238/255, 255/237, 237/255, 66/64, or 64/66 may be
selected for FEC operation using the FEC[2:0] control pins as indicated below. Scaling factors of 255/
237, 237/255, 66/64, or 64/66 require that the input
clock rate be in the 155 MHz or higher range.
000 = No FEC scaling.
001 = 255/238 FEC scaling.
010 = 238/255 FEC scaling.
011 = Reserved.
100 = 255/237 FEC scaling (155 MHz or higher
input clock range required).
101 = 237/255 FEC scaling (155 MHz or higher
input clock range required).
110 = 66/64 FEC scaling (155 MHz or higher input
clock range required).
111 = 64/66 FEC scaling (155 MHz or higher input
clock range required).
*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
26
Rev. 2.2
Si5321
Table 10. Si5321 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
B1
C1
BWSEL[0]
BWSEL[1]
I*
LVTTL*
Bandwidth Select.
BWSEL[1:0] pins set the bandwidth of the loop filter
within the DSPLL to 6400, 3200, 1600, or 800 Hz as
indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
Note: The loop filter bandwidth is twice the value
indicated here when BWBOOST is set high.
D2
BWBOOST
I*
LVTTL*
Bandwidth Boost.
Active high input to boost the selected bandwidth
2x. When this pin is high the loop filter bandwidth
selected on BWSEL[1:0] is doubled. When this pin
is high, FXDDELAY must also be high and FEC[2:0]
must be 000.
B4
FXDDELAY
I*
LVTTL*
Fixed Delay Mode.
Set high to disable hitless recovery from digital hold
mode. This configuration is useful in applications
that require a known or constant input-to-output
phase relationship.
When this pin is high, hitless switching from digital
hold mode back to a valid clock input is disabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY high, the clock output
changes as necessary to re-establish the initial/
default input-to-output phase relationship that is
established after powerup or reset. The rate of
change is determined by the setting of BWSEL[1:0].
When this pin is low, hitless switching from Digital
Hold mode back to a valid clock input is enabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY low, the device enables
“phase build out” to absorb the phase difference
between the clock output and the clock input so that
the phase change at the clock output is minimized.
In this case, the input-to-output phase relationship
following the transition out of digital hold mode is
determined by the phase relationship at the time
that switching occurs.
Note: FXDDELAY should remain at a static high or static
low level during normal operation. Transitions on
this pin are allowed only when the RSTN/CAL pin
is low. FXDDELAY must be set high when
BWBOOST is set high.
*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
Rev. 2.2
27
Si5321
Table 10. Si5321 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
H4
VALTIME
I*
LVTTL*
Clock Validation Time for LOS.
VALTIME sets the clock validation times for recovery
from an LOS alarm condition. When VALTIME is
high, the validation time is approximately 100 ms.
When VALTIME is low, the validation time is approximately 2 ms.
H3
RSTN/CAL
I*
LVTTL*
Reset/Calibrate.
When low, all LVTTL outputs are forced into a high
impedance state, the DSPLL is forced out-of-lock,
and the device control logic is reset.
A low-to-high transition on RSTN/CAL initializes all
digital logic to a known condition and initiates selfcalibration of the DSPLL. At the completion of selfcalibration, the DSPLL begins to lock to the selected
clock input signal and begins to drive out the output
clock signal onto the CLKOUT pins.
F8
LOS
O
LVTTL
Loss-of-Signal (LOS) Alarm for CLKIN.
Active high output indicates that the Si5321 has
detected missing pulses on the input clock signal.
The LOS alarm is cleared after either 100 ms or 13 s
of a valid CLKIN clock input, depending on the setting of the VALTIME input.
D8
DH_ACTV
O
LVTTL
Digital Hold Mode Active.
Active high output indicates that the DSPLL is in
digital hold mode. Digital hold mode locks the
current state of the DSPLL and forces the DSPLL to
continue generation of the output clock with no
additional phase or frequency information from the
input clock.
E8
CAL_ACTV
O
LVTTL
Calibration Mode Active.
This output is driven high during the DSPLL self-calibration and the subsequent initial lock acquisition
period.
C2
VSEL33
I*
LVTTL*
Select 3.3 V VDD Supply.
This is an enable pin for the internal regulator. To
enable the regulator, connect this pin to the VDD33
pins.
D3–D5,
E3–E5
VDD33
VDD
Supply
3.3 V Supply.
3.3 V power is applied to the VDD33 pins. Typical
supply bypassing/decoupling for this configuration is
indicated in the typical application diagram for 3.3 V
supply operation.
*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
28
Rev. 2.2
Si5321
Table 10. Si5321 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
D6, D7, E6,
E7, F3–F7
VDD25
VDD
Supply
2.5 V Supply.
These pins provide a means of connecting the
compensation network for the on-chip regulator.
C3–C7, E2,
F2, G2–G8
GND
GND
Supply
Ground.
Must be connected to system ground. Minimize the
ground path impedance for optimal performance of
the device.
H2
REXT
I
Analog
External Biasing Resistor.
Used by on-chip circuitry to establish bias currents
within the device. This pin must be connected to
GND through a 10 kΩ (1%) resistor.
A4–8, B5, B8
RSVD_NC
LVTTL
Reserved—No Connect.
This pin must be left unconnected for normal
operation.
B6, B7, C8
RSVD_GND
LVTTL
Reserved—GND.
This pin must be tied to GND for normal operation.
*Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
Rev. 2.2
29
Si5321
4. Ordering Guide
30
Part Number
Package
Temperature
Si5321-F-BC
63-Ball CBGA
–20 to 85 °C
Rev. 2.2
Si5321
5. Package Outline
Figure 12 illustrates the package details for the Si5321. Table 11 lists the values for the dimensions shown in the
illustration.
Figure 12. 63-Ball Ceramic Ball Grid Array (CBGA)
Table 11. Package Diagram Dimensions
Dimension
Description
Minimum
Nominal
Maximum
A
Total Package Height
2.36
2.51
2.66
A1
Standoff
0.65
0.70
0.75
A2
Body Thickness
0.93
1.03
1.13
b
Solder Ball Diameter
0.65
0.70
0.75
D
Body Size
9.00 BSC
D1
Total Array Pitch
7.00 REF
e
Solder Ball Pitch
1.00 BSC
S
Pitch Centerline
0.50 REF
X
Die Length
—
5.22
—
Y
Die Width
—
3.36
—
Rev. 2.2
31
Si5321
6. 9x9 mm CBGA Card Layout
Placement Courtyard
Table 12. Recommended Land Pattern Dimensions
Symbol
Parameter
Dimension
Notes
Min
Nom
Max
C
Column Width
—
7.00 REF
—
D
Row Height
—
7.00 REF
—
E
Pad Pitch
—
1.00 BSC
—
F
Placement Courtyard
10.00
—
—
1
X
Pad Diameter
0.64
0.68
0.72
2, 3
Notes:
1. The Placement Courtyard is the minimum keep-out area required to assure assembly clearances.
2. Pad Diameter is Copper Defined (Non-Solder Mask Defined/NSMD).
3. OSP Surface Finish Recommended.
4. Controlling dimension is millimeters.
5. Land Pad Dimensions comply with IPC-SM-782 guidelines.
6. Target solder paste volume per pad is 0.065 mm3 ± 0.010 mm3 (4000 mils3 ± 600 mils3).
Recommended stencil aperture dimensions to achieve target solder paste volume are 0.191 mm
thick x 0.68±0.01 mm diameter, with a 0.025 mm taper.
7. Recommended stencil type is chemically etched stainless steel with circularly tapered apertures.
32
Rev. 2.2
Si5321
DOCUMENT CHANGE LIST
Revision 2.0 to Revision 2.1
„
„
„
„
„
Updated Table 3, “AC Characteristics,” on page 7.
Updated Figure 8, “Recovery from Digital Hold,” on
page 20.
Updated Figure 12, “63-Ball Ceramic Ball Grid Array
(CBGA),” on page 31.
Updated Table 11, “Package Diagram Dimensions,”
on page 31.
Added Figure 4, “Typical Si5321 Phase Noise
(CLKIN = 155.52 MHz, CLKOUT = 622.08 MHz, and
Loop BW = 800 Hz),” on page 15.
Revision 2.1 to Revision 2.2
„
„
Updated Table 3, “AC Characteristics,” on page 7.
Updated Table 11, “Package Diagram Dimensions,”
on page 31.
Rev. 2.2
33
Si5321
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: [email protected]
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
34
Rev. 2.2
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