Intel 82573 E,V,L GbE controllers, 82562 EZ,EX,GZ,GX Platform LAN Connect Design Guide
Below you will find brief information for GbE controllers 82573 E,V,L, Platform LAN Connect 82562 EZ,EX,GZ,GX. The Intel® 82573 family of GbE controllers support Gigabit Ethernet, with additional features available on the Intel® 82573E and Intel® 82573V. The Intel® 82562 family supports 10/100 Mb/s Ethernet with manageability (82562EX/GX) or basic 10/100 Mb/s Ethernet (82562EZ/GZ). Each device supports the same footprint enabling motherboard designs to support multiple LAN components.
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82573/82562 Dual Footprint Design
Guide
October 2009
315518-006
Revision 2.7
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details.
The 82573/82562 Ethernet Controllers may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Hyper-Threading Technology requires a computer system with an Intel products/ht/Hyperthreading_more.htm
for additional information.
®
Pentium
®
4 processor supporting HT Technology and a HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
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Copyright © 2009, Intel Corporation. All Rights Reserved.
2
Design Guide—82573/82562
Contents
LCI Connection to the 82562 Platform LAN Connect Device .......................................9
Clock Request Signal (82573L)................................................................. 10
PCIe* Routing Example ........................................................................... 11
General Design Considerations for Ethernet Controllers .......................................... 13
Integrated Magnetics Module ................................................................... 14
Designing with the 82562 Platform LAN Connect Device ......................................... 14
82562EZ/EX PLC Device LAN Disable Guidelines ......................................... 14
Serial EEPROM for 82562 PLC Implementations .......................................... 15
Magnetics Modules for the 82562 PLC Device ............................................. 16
Power Supplies for 82562 PLC Implementations ......................................... 16
82562 PLC Device Test Capability ............................................................. 16
Integrated Magnetics Module for 1000BASE-T ............................................ 16
NVM Interface for the 82573.................................................................... 17
Power Supplies for the 82573 Device ........................................................ 18
82573 Controller Power Supply Filtering .................................................... 20
82573 Controller Power Management and Wake Up..................................... 20
Active State Power Management Support................................................... 20
82573 Device Test Capability ................................................................... 21
General Layout Considerations for Ethernet Controllers .......................................... 21
Guidelines for Component Placement ........................................................ 21
Board Stack Up Recommendations............................................................ 23
Differential Pair Trace Routing.................................................................. 24
Signal Trace Geometry............................................................................ 25
Trace Length and Symmetry .................................................................... 25
Impedance Discontinuities ....................................................................... 25
Reducing Circuit Inductance..................................................................... 26
4.1.13 Ground Planes Under the Magnetics Module ............................................... 27
Termination Resistors for Designs Based on 82562 PLC Device ..................... 29
Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC Device............ 29
Termination Resistors for 82573-Based Designs ......................................... 29
3
82573/82562—Design Guide
Light Emitting Diodes for 82573-Based Designs ..........................................29
Troubleshooting Common Physical Layout Issues ...................................................30
Routing Summary...................................................................................32
Terminating Unused SPI Signals ...............................................................38
SPI Dual Footprint - SO8 and SO16 Packages .............................................38
82573E/82573V Ball Out .........................................................................40
6.1.1
Vibration Mode .......................................................................................44
Temperature Stability and Environmental Requirements...............................45
Equivalent Series Resistance ....................................................................46
4
Design Guide—82573/82562
Figures
13 SPI Shared Flash Exclusively Used with Intel
82573.................................................... 34
Tables
4 82562 PLC Recommended Integrated Magnetics Modules .............................................. 16
18 SPI Stuffing Option Topology Routing Summary for the 2116 Stackup............................. 38
19 SPI Stuffing Option Topology Routing Summary for the 1080 Stackup............................. 38
20 Crystal Parameters................................................................................................... 44
5
6
82573/82562—Design Guide
Date
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.6
1.5
Revision History
Revision
Oct 2009
Dec 2007
Sept 2007
May 2007
Jan 2007
Oct 2006
June 2006
Sept 2005
July 2005
July 2005
Description
Added crystal manufacturer information.
Updated Analog Front End reference schematic (sheet 6).
Updated section 3.3.2 (item number 3).
Updated Table 21. Under “LED Circuits” in the “Remarks” column, changed anode to cathode and cathode to anode.
Added magnetics model numbers to Tables 4 and 5.
Major edit all sections.
Updated EEPROM/Flash Configuration Size table.
Updated Compatible Flash Parts table.
Updated 82573L ball out definitions.
Updated figure title for Figure 13 (removed “non-shared”.
Removed “or greater” from items 4 and 5 in section 3.3.2
Removed all references to Dev_OFF and replaced with DEVICE_OFF, changed the
Intel logo and used the new template style.
Integrated information for the 82573E into this document, 82573/82562 Dual
Footprint Design Guide.
Updated DEVICE_OFF# (ball L7) to indicate that an internal pull-up resistor does not exist.
Initial release.
Design Guide—82573/82562
1.0
Note:
Note:
Table 1.
Introduction
Product features and specifications are subject to change without notice.
Verify with your local Intel sales office that you have the latest information before finalizing a design.
The Intel
®
945/Intel
®
I/O Control Hub 7 (ICH7) 82801GB platform supports several footprint compatible Ethernet options depending upon the target application. The term
“footprint compatible” means the silicon devices are all manufactured in a 15 mm by 15 mm, 196 Thin and Fine Ball Grid Array (TF-BGA) package, with the same ball pattern.
Many of the critical signal pin locations are identical, allowing designers to create a single LAN on Motherboard (LOM) design that accommodates all devices. This is a flexible, cost-effective, multipurpose design technique that maximizes value while meeting performance requirements.
Since some of the signal pins differ in usage, the term “pin compatible” is not applicable.
Available LAN components with the same footprint include the Intel and 82573L Gigabit Ethernet Controllers and Intel
®
®
82573E, 82573V
82562EZ, 82562EX, 82562GZ and
82562GX Platform LAN Connect (PLC) components. (For purposes of this document, the 82573E, 82573V and the 82573L will be referred to as the 82573; and the
82562EZ, 82562EX, 82562GZ and 82562GX will be referred to as the 82562 unless otherwise noted. Specific device data can be referenced in their respective datasheets for feature differences.) ICHx refers to ICH6 and ICH7 components.
The requirements for connection speed and manageability determine which LAN components should be used on a specific platform. As these requirements change, footprint compatibility make it possible to refocus the platform without the need for a motherboard redesign.
LAN Component Connections/Features
LAN Component Interface
Intel
®
82573E
PCI
Express*
(PCIe*)
Connection
GbE (1000BASE-T) with manageability
Intel
®
82573V
Intel
®
82573L
Intel
®
82562EX/GX (196 BGA)
PCIe*
PCIe*
LCI
GbE (1000BASE-T) with manageability
GbE (1000BASE-T)
10/100 Mb/s Ethernet with manageability
Intel
®
82562EZ/GZ (196 BGA) LCI Basic 10/100 Mb/s Ethernet
Features
GbE, Intel
®
Active
Management Technology
(Intel
® alerting
AMT), ASF 2.0
GbE, ASF 2.0 alerting
GbE, no manageability
Ethernet 10/100 Mb/s connection, ASF 1.0 alerting
Ethernet 10/100 Mb/s connection
7
1.1
1.2
Note:
82573/82562—Design Guide
Scope
This document contains Ethernet design guidelines applicable to LOM designs based on the Intel
®
945/ICH7 82801GB chipset. The document identifies similarities and differences between the 82562 Platform LAN Connect device and the 82573 controller.
•
- describes the port interfaces specific to each device.
•
- explains requirements to connect an Ethernet device.
•
- describes board layout techniques applicable to these devices.
•
- describes the Flash interface applicable to these devices.
•
- describes selection criteria for crystal devices.
This document assumes the reader is acquainted with high-speed design and board layout techniques. Please see the reference document list for additional design information.
Reference Documents
• Intel
®
82573 Family of GbE Controllers Datasheet. Intel Corporation.
• Intel
®
82562GX 10/100 Mb/s Platform LAN Connect (PLC) Networking Silicon
Datasheet. Intel Corporation.
• Intel
®
82562GZ 10/100 Mb/s Platform LAN Connect (PLC) Networking Silicon
Datasheet. Intel Corporation.
• 82573E Intel
®
Corporation.
Active Management Technology (Intel
®
AMT) Design Guide. Intel
• Intel
®
82573 NVM Map and Programming Information Guide. Intel Corporation.
• Intel
®
ICHx Integrated LAN Controller Function Disable and Power Control. Intel
Corporation.
• Intel
®
Ethernet Controllers Timing Device Selection Guide. Intel Corporation.
• PCI Express Specification, Revision 1.0a. PCI Special Interest Group.
• PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special
Interest Group.
• IEEE Standard 802.3, 2000 Edition. Institute of Electrical and Electronics Engineers
(IEEE).
1
Intel documentation is subject to frequent revision. Verify with your local Intel sales office that you have the latest information before finalizing a design.
8
1. This document incorporates various IEEE standards previously published separately.
Design Guide—82573/82562
2.0
Figure 1.
System Data Port Interfaces
The 82562 PLC device and the 82573 controller use different system interfaces, as illustrated below in
.
ICHx Platform LAN Connect Sections
PCIe*
Intel®
82573
Intel
®
ICHx
MDI
Magnetic
Module
RJ-45
Connector
LCI
Intel®
82562
2.1
2.2
Note:
Further details can be found in the reference design schematics (see
).
LCI Connection to the 82562 Platform LAN Connect Device
The 82562 PLC device uses the LAN Connect Interface (LCI) to connect to the ICHx. LCI is a point-to-point interface optimized to support one device.
Line termination mechanisms are not specified for the LAN Connect Interface. Slew rate controlled output buffers achieve acceptable signal integrity by controlling signal reflection, undershoot and ringing.
Further details on connecting the LCI between the 82562 PLC device and ICHx can be obtained in the Intel
®
945/ICH7 82801GB chipset design guide.
PCIe* Port Connection to the 82573 Device
PCIe* is a dual simplex point-to-point serial differential low-voltage interconnect. The signaling bit rate is 2.5 Gb/s per lane per direction. Each port consists of a group of transmitters and receivers located on the same chip. Each lane consists of a transmitter and a receiver pair. A link between the ports of two devices is a collection of lanes. The link between the 82573 and the ICHx device is a single lane.
Each signal is 8b/10b encoded with an embedded clock.
PCIe* topology consists of a transmitter (Tx) located on one device connected through a differential pair connected to the receiver (Rx) on a second device. The 82573 controller can be located on the motherboard or on an add-in card using a connector specified by PCIe*.
9
82573/82562—Design Guide
Note:
2.2.1
2.2.2
The lane is AC coupled between its corresponding transmitter and receiver. The AC coupling capacitor is located on the board close to transmitter side. Its recommended value is 0.1 µF. Each end of the link is terminated on the die into nominal 100 differential DC impedance. Board termination is not required.
For more information on PCIe*, refer to the PCI Express* Base Specification, Revision
1.0a and PCI Express* Card Electromechanical Specification, Revision 1.0a.
In manufacturing, vias are required for testing and troubleshooting purposes. The via size should be a 17-mil (±2 mils for manufacturing variance) Finished Hole Size (FHS).
PCIe* Reference Clock
The 82573 Ethernet controller uses a 100 MHz differential reference clock, denoted
PE_CLKp and PE_CLKn. This signal is typically generated on the system board and routed to the PCIe* port. For add-in cards, the clock is furnished at the PCIe* connector.
The frequency tolerance for the PCIe* reference clock is +/- 300 ppm.
Clock Request Signal (82573L)
The 82573L supports Clock Request. The Clock Request (CLKREQ#) signal is located at ball P9 of the 82573L. When it is sampled high, this open-drain signal alerts the system that the 82573L does not need the PCIe* differential reference clock. During normal operation, the 82573L keeps CLKREQ# asserted (low) and the system supplies this clock to the device on the PE_CLKp and PE_CLKn signals. The 82573L deasserts
CLKREQ# (high) when it is in an electrical idle state (L1 or L2) and the system might choose to continue supplying the reference clock or gate it. The CLKREQ# signal should be connected to the clock driver supplying the 82573L PCIe* clock. If other devices use the same CLKREQ# signal, a pull-up resistor should be used to ensure that no device pulls this signal low when it is powered off (see
).
10
Design Guide—82573/82562
Figure 2.
Clock Request Signal Implementation (82573L)
VCC
2.2.3
2.2.4
CLK1
CLK
CLKREQ#
CLK2
CLK
CLKREQ#
CLK3
CLKREQ#
CLK
CLKREQ#
To enable clock management, bit 2 of word 0Fh must be set to 1b. (The Intel
®
NVM Map and Programming Information Guide provides further details.)
82573
Other PCIe* Signals
The 82573 device also implements other signals required by the PCIe* specification.
The Ethernet controller signals power management events to the system using the
PE_WAKE# signal, which operates very similarly to the familiar PCI PME# signal.
Finally, there is a PE_RST# signal that serves as the familiar reset function for the
82573 controller.
PCIe* Routing Example
This section provides an example for routing PCIe* signals. The diagrams provided are examples only and are not specifically for the 82573.
11
82573/82562—Design Guide
Figure 3.
PCIe* Routing Example
DB
L O M
M M M M M M M
R R
P P
N N
M M
R
P
R
P
R
P
R
P
N
M
N
M M
N N
M
N
M
R
P
R R
P P
N
M
N
M
K K K K K K K K K
H H
G G
H
G
H
G G
H H
G
H
G
H H
G G
E
D
C
E
D
C
B B
A A
B
A
E
D
C
E
D D
E E
D
C C C
E
D
C
E E
D D
C C
B
A
B
A
B
A
B
A
B B
A A
U 1 b c a
1 2
1 2
2 1
2 1
C
C
C
C
2 2
3 0
2 1
3 2 g g g e
1 f
2
1 2
2 1
2 1
C 2
C 2
C 2
C 2
8
7
3
5
3.0
6 2 C
1 3 C
0 2 C
4 2 C
2 1
2 1
1 2
1 2
8 1 C
7 1 C
9 2 C
3 3 C
2 1
2 1
1 2
1 2
C H I P S E T
T
N
M
R
P
R
P
R
P
N
M
N
M
R
P
R
P
N
M
N
M
R R
P P
N N
M M
R
P
R
P
N
M
N
M M M M M M M M
K K K K K K K K K
H
G
H
G
H
G
H
G
H
G
H H
G G
H
G
H
G
E
D
E
D
E
D
C C C
B
A
B B
A A
E
D
E
D
C C
B
A
B
A
E E
D D
C C
B B
A A
E
D
E
D
C C
B
A
B
A
2 U
1 4
Di me n s i o n Mi n Ma x T y pi c a l De s c r i pt i o n
( m i l s ) ( m i l s ) ( m i l s ) a d e f g b c
5
5
5 x
0
0 h
5 0 0
1
2 5
0 0
0
0
5
5
0
0
2
2
1
5
2
7
0
8
0
0
5
0
0
D
T
T r r a a c e c e l
P
P i
P
L e a i i s t i t t a n g r c c
h n h t t c l e h e e n g n f g r t t
(
(
C
C e e n t n t o o f m e o m h h f f r r o m o m e e t d i a l r f r
f
-
B G A b a l l t o c
B G A
B G A b a b a l l l l t t o o c c e n t e n t e e r r o f o f
1 7
1 7 -
t t e d i o r o f e f
C n e e
C e t r n i t e r n t e a l e n t r i
)
) p a a o f i l o r f a p a c i t o r p a d p
1 c
1
7
7
-
o n
1 9
1 v
9 e r m i m i g e l l n c
F H
F H e
S
S f a i r s e p e r a t i v r o n i v i o
1 9
1 9 m i m i l l v v i i a a o n o n
P C
P C I
I -
-
E
E d c l a t a o c k t r t r a c a c e s e s a s w i t a m s o o p t u t i h i s i m u n d m e i a p a i t n t h e r a r d i p a f i f r e r c e o n t i n d u a l c t p o r a i s r e p e r a t i o n
F H S h
=
=
F i h e i n i g s h t h e o d f
H t o l h i e s s i t r z a e c e a b o v e t h e r e f e r e n c e p l a n e , t y p i c a l l y t h e d i a l e c t r i c t h i c k n e s s
L O M b c a
T
1 6 T 1 5 T 1 4 T 1
3
T 1 2
R 1 6 R 1 5 R 1 4 R 1 3 R 1 2
T
1 1 T 1 0
R 1 1 R 1 0
L 1 6 L 1 5 L 1 4 L 1 3 L 1 2 L 1 1 L 1 0 L 9
R 8
T 7 T 6
R 7 R 6
T 5
R 5
T 4
R 4
L 8 L 7 L 6 L 5 L 4 L 3
R 1
P 1 6 P 1 5 P 1 4 P 1 3 P 1 2 P 1 1 P 1 0 P 8 P 7 P 6 P 5
N 8 N 7 N 6 N 5 N 4 N 1 6 N 1 5 N 1 4 N 1 3 N 1 2 N 1 1 N 1 0
M 1 6 M 1 5 M 1 4 M 1 3 2 M 1 M 1 0 M 9 M 8 M 7 M 6 M 5 M 4 M 3 M 2 M 1
P 1
N 1
L 2 L 1
K 1 6 K 1 5 K 1 4 K 1 3 K 1 2
J 1 6 J 1 5 J 1 4 J 1 3 J 1 2
K 1 1 K 1 0
J 1 1 J 1 0 J 9
K 8
J 8
K 7 K 6
J 7 J 6
K 5
J 5
K 4
J 4 J 3 J 2
K 1
J 1
H 1 6 H 1 5 H 1 4 H 1 3 H 1 2 H 1 1 H 1 0
G 1 6 G 1 5 G 1 4 G 1 3 2 G 1 G 0 G 9
H 8
G 8
H 7 H 6 H 5 H 4
G 7 G 6 G 5 G 4
H 1
G 2 G 1
E
F 1 6
1 6
F 1 5
E 1 5
F 1 4
E 1 4
F 1
E 1 3
3 F
E
1
1
2
2
F
E
1
1
1
1
F
E
1
1
0
0
F 8 F 7 F 6 F 5
E 8 E 7 E 6 E 5
D 1 6 D 1 5 D 1 4 D 1 3 D 1 2
C 1 6 C 1 5 C 1 4 C 1 3 C 1 2
D 1 1
C 1 1
D 1 0 D 9
C 1 0 C 9
D 8
C 8
D 7 D 6
C 7 C 6
D 5
C 5
B 1 6 B 1 5 B 1 4 B 1 3 B 1 2 B 1 1 B 1 0
A 1 6 A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0
B 8 B 7 B 6 B 5 B 4
A 8 A 7 A 6 A 5
D 2 D 1
C 2 C 1
F 1
E 1
B 1
A 1
1 2
1 2
2 1
2 1
C 2 2
C 3 0
C 2 1
C 3 2 e
1 f
2
1 2
2
2
1
1
C 2 8
C 2 7
C 2 3
C 2 5 g g g
U 1
Note:
The 82573 is a x1, and the drawing is for a x4 design and is shown only for reference.
Note:
The second drawing is an enlargement of a section of the first drawing.
Ethernet Component Design Guidelines
These sections provide recommendations for selecting components and connecting special pins. The main design elements are the 82562 Platform LAN Connect device or the 82573, an integrated magnetics module with RJ-45 connector, and a clock source.
12
Design Guide—82573/82562
3.1
3.1.1
Note:
General Design Considerations for Ethernet Controllers
These recommendations apply to all designs, Fast Ethernet (10/100 Mb/s) or GbE (10/
100/1000 Mb/s).
Follow good engineering practices with respect to unused inputs by terminating them with pull-up or pull-down resistors, unless the datasheet, design guide or reference schematic indicates otherwise. Pull-up or pull-down resistors must not be attached to any balls identified as reserved. These devices might have special test modes that could be entered unintentionally.
Clock Source
All designs require a 25 MHz clock source. The 82562 PLC device and the 82573 use the 25 MHz source to generate clocks up to 125 MHz for the PHY circuits. For optimum results with lowest cost, connect a 25 MHz parallel resonant crystal and appropriate load capacitors at the XTAL1 and XTAL2 leads. The frequency tolerance of the timing device should be 30 ppm or better. Refer to the Intel
Ethernet Controllers Timing Device
Selection Guide for more information on choosing crystals.
There are three steps to crystal qualification:
1. Verify that the vendor’s published specifications in the component datasheet meet the required conditions for frequency, frequency tolerance, temperature, oscillation mode and load capacitance.
2. Independently measure the component’s electrical parameters in real systems.
Measure frequency at a test output to avoid test probe loading effects at XTAL2.
Check that the measured behavior is consistent from sample to sample and that it meets the published specifications. For crystals, it is also important to examine startup behavior while varying system voltage and temperature.
3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems.
provides guidelines for crystal selection.
13
82573/82562—Design Guide
3.1.2
3.2
3.2.1
Note:
Integrated Magnetics Module
The magnetics module has a critical effect on overall IEEE and emissions conformance.
The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation. Occasionally, components that meet basic specifications can cause the system to fail IEEE testing because of interactions with other components or the printed circuit board itself. Carefully qualifying new magnetics modules can help prevent this type of problem.
The steps involved in magnetics module qualification are similar to those for oscillator qualification:
1. Verify that the vendor’s published specifications in the component datasheet meet the required IEEE specifications.
2. Independently measure the component’s electrical parameters on the test bench, checking samples from multiple lots. Check that the measured behavior is consistent from sample to sample as well as meeting the published specifications.
3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems. Vary temperature and voltage while performing system level tests.
Magnetics modules for 1000BASE-T Ethernet are similar to those designed solely for
10/100 Mb/s, except that there are four differential signal pairs instead of two.
contains parametric guidelines.
Designing with the 82562 Platform LAN Connect Device
This section provides design guidelines specific to the PLC device.
82562EZ/EX PLC Device LAN Disable Guidelines
The ICHx Integrated LAN Controller resides on the ICHx VccSus3_3 and VccSus1_8 power wells. These are typically referred to as auxiliary (aux) or standby supplies at the platform level.
The ICHx Integrated LAN_RST# is the ICHx resume-well input. It can be held low indefinitely to keep the ICHx in a reset state. The LAN reset (LAN_RST#) signal must not be de-asserted sooner than 10 ms after the resume power supply reaches its nominal voltage. This ensures that the ICHx is initialized.
shows a possible solution for ICHx LAN disable.
14
Design Guide—82573/82562
Figure 4.
82562EZ/EX LAN Disable Circuitry
Super IO
GP Port or
ICH GPIO or
Micro
Controller
(mobile)
3.3 Vstb
1K
3.3 Vstb
1K
MMBT3904
470 Ohms 100 Ohms
100 Ohms
100 Ohms
100 Ohms
3.3 Vstb
Sensor/
Supervisor
RST#
LAN_RST#
RSM_RST#
ICH
TESTEN
ISOL_TCK
ISOL_TI
ISOL_EXEC
3.2.2
Table 2.
Table 3.
Notes:
1.
2.
The 100 resistors for the test mode signals are required for the eXclusive OR (XOR) Tree and isolate mode.
The PLC device should be connected to a super I/O pin that retains its value during PCIe* reset and is driven from the resume well and defaults to a value of one on power up.
Serial EEPROM for 82562 PLC Implementations
The serial EEPROM for LAN implementations based on 82562 PLC devices connects to the ICHx. Depending on the size of the EEPROM, the 82562 PLC might or might not
support legacy manageability. Table 2 and Table 3
list the EEPROM map for the PLC device. Details for the EEPROM can be obtained in the I/O Control Hub 4, 5, and 6
EEPROM Map and Programming Information Guide.
82562 PLC Memory Layout (128-byte EEPROM)
00h
3Fh
Hardware/Software
Reserved Area
Note:
No manageability provided.
82562 PLC Memory Layout (512-byte EEPROM)
00h
3Fh
40h
FFh
HW/SW Reserved Area
ASF 1.0
Legacy Manageability
Note:
Legacy manageability only.
15
82573/82562—Design Guide
3.2.3
Note:
Table 4.
3.2.4
3.2.5
3.3
3.3.1
3.3.2
Magnetics Modules for the 82562 PLC Device
Carefully select a 5-core magnetics module for your design. Table 4 lists suggested
integrated magnetics modules for use with the 82562 PLC. These modules also contain integrated USB jacks.
These components are pin-compatible with the magnetics modules shown in
for the 82573.
82562 PLC Integrated Magnetics Modules
1
Pulse
Manufacturer
Stewart Connector
Systems
Foxconn
Discrete Magnetics Module
Part Number
H1138 - MDI only
H1338 - MDI and MDI-X only
Check with manufacturer for availability.
Check with manufacturer for availability.
Integrated Magnetics Module
Part Number
JW0A1P01R-E
JW0A1P01R - Magjack
SI70027
UB11123-J51
1. These modules have been used successfully in past designs, however no particular product is recommended.
Power Supplies for 82562 PLC Implementations
The 82562 PLC uses a single 3.3V power supply. The 3.3V supply must provide approximately 90 mA current for full speed operation. Standby power must be furnished in order to allow wake up from a power down.
82562 PLC Device Test Capability
The device contains an eXclusive OR (XOR) test tree mechanism for simple board tests.
Details of the XOR tree operation are available from your Intel representative.
Designing with the 82573
This section provides design guidelines specific to the 82573.
LAN Disable for 82573
The DEVICE_OFF# signal can be used for disabling the device from system BIOS. The
DEVICE_OFF# input is completely asynchronous. It can be connected to a Super I/O pin that retains its value during the PCIe* reset, is driven from a resume well and defaults to a one on power up. The DEVICE_OFF# pin does not have an internal pull-up resistor, therefore an external pull-up resistor is recommended for normal operation.
Integrated Magnetics Module for 1000BASE-T
Magnetics modules for 1000BASE-T Ethernet are similar to those designed solely for
10/100 Mb/s, except that there are four differential signal pairs instead of two. The following guidelines are listed to help verify specific electrical parameters:
1. Verify that the rated return loss is 18 dB or greater from 2 MHz through 30 MHz for
100BASE-TX.
2. Verify that the rated return loss is 12 dB or greater at 80 MHz for 100BASE-TX.
(The specification requires greater than or equal to 10 dB.)
16
Design Guide—82573/82562
Table 5.
3.3.3
3.3.4
3. Verify that the rated return loss is 10 dB (2 dB margin) at 100 MHz for 1000BASE-
TX on the platform at 100 MHz, measured at the RJ-45 and into 85 , 100 , and
115 references.
4. Verify that the insertion loss is less than 1.0 dB at 100 KHz through 80 MHz for
100BASE-TX.
5. Verify that the insertion loss is less than 1.4 dB at 100 KHz through 100 MHz for
1000 BASE-T.
6. Verify at least 30 dB of crosstalk isolation between adjacent channels (through 150
MHz).
7. Verify high voltage isolation to 1500 Vrms.
8. Transmitter OCL should be greater than or equal to 350 µH with 8 mA DC bias.
Table 5 lists suggested magnetics modules for use with the 82573. These modules also
contain integrated USB jacks. A good quality Gigabit Ethernet magnetics module can also be used with the 82562 Platform LAN Connect device.
82573 Magnetics Modules
1
Manufacturer
Discrete Magnetics
Module Part Number
Integrated Magnetics
Module Part Number
Pulse Engineering
H5019D (low profile)
H5007
JW0A2P019D - Magjack
Bel Fuse S558-5999–P3
Check with manufacturer for availability.
1. These modules have been used successfully in past designs, however no particular product is recommended.
Note:
These components are pin-compatible with the magnetics modules shown in
for the 82562 PLC device.
82573 LEDs
The 82573 controller contains three programmable LED outputs. The LEDs are independently programmable to provide particular speed, link, activity and event status. The behavior of the LEDs is controlled by bits read from the Non-Volatile
Memory (NVM). 82573-based designs need to ensure that the NVM is programmed correctly.
NVM Interface for the 82573
The 82573 provides a single Serial Peripheral Interface (SPI) that only supports SPI
EEPROMs or SPI Flash devices. The 82573 is configured for either an EEPROM or Flash device based on the setting of the NVM_TYPE input pin. If the NVM_TYPE pin is pulled high, an SPI EEPROM is connected. If the NVM_TYPE pin is pulled low, an SPI Flash connection is enabled. In most cases a single physical footprint on the board can accommodate either a SPI Flash or SPI EEPROM device, which can be populated with a
SPI Flash or SPI EEPROM device depending on the desired configuration. Flash is required for Intel
®
AMT support.
The 82573 enables the SPI Flash to be shared for access with the ICH7. In this case, the 82573 SPI Flash can be used as the single consolidated system Flash device. While the ICH7 device owns the Flash, the 82573 can request access to the Flash through the
ICH7 SPI arbitration pin (NVM_REQ signal on the 82573). In this instance, the Flash contains both the firmware code used for network management and the BIOS code
17
82573/82562—Design Guide
used by the platform to power up the system. The NVM_SHARED input pin configures the 82573 for operation in this mode. When the NVM_SHARED input pin is pulled low, the SPI Flash has shared access with the ICH.
The SPI bus is a high speed bus and requires careful design consideration. The routing
recommendations are provided in Section 5.1
. Since this is a high speed bus, the recommendations should be followed if possible. If there are any deviations, it is strongly recommended that they are simulated to ensure design compliance.
Table 6.
Table 7.
Table 8.
Note:
3.3.5
EEPROM/Flash Configuration Size
Configuration Minimum NVM Size
ASF or APT Manageability
No Manageability (Intel
Shared Flash with Intel
®
AMT, ASF or APT)
®
AMT (82573E only)
64 Kb
1 Kb
8 Mb to 16 Mb total
The minimum requirement for
Intel
®
AMT is 4 Mb
Shared Flash without Intel® AMT
8 Mb to 16 Mb total mobile
4 Mb to 16 Mb total for desktop
128 Kb (minimum) is reserved for the LAN image
Dedicated Flash with Intel
®
AMT (82573E only) 4 Mb
Dedicated Flash without Intel
®
AMT 128 Kb
Memory Family
SPI EEPROM
SPI EEPROM
SPI Flash
SPI Flash
SPI Flash
SPI Flash
Compatible EEPROM Parts
Vendor
1
1 Kbit
Atmel*
STM*
Catalyst*
AT25010N-10SI-2.7
95010WMN6
CAT25010S
1. The vendors listed here manufacture EEPROM parts that have been used successfully in previous designs.
Compatible Flash Parts
ST Micro*
Chingis*
SST*
Vendor 4 Mb
25PE40
1
,
M45PE40
2
PM25LV040
25VF040B
25LF040A
8 Mb
25PE80
1
M45PE80
,
2
25VF080B
16 Mb
25VF016B
1. ST Micro* parts can only be used with Intel® non-AMT Systems.
2. These parts have been fully tested but are not pin compatible with the other Flash components listed in this table.
Additional 8 Mb and 16 Mb Flash parts will become available in early 2007 and will be validated for use with the 82573 GbE controller. Consult your local Intel representative for availability information.
Power Supplies for the 82573 Device
The 82573 controller requires three power supplies (3.3V, 2.5V, and 1.2V).
18
Design Guide—82573/82562
Figure 5.
A central power supply can provide all the required voltage sources or the power can be derived and regulated locally by the Ethernet control circuitry. All voltage sources must remain present during power down in order to use the 82573 Ethernet controller's LAN wake up capability.
Instead of using external regulators to supply 2.5V and 1.2V, a designer can use power transistors in conjunction with on-chip regulation circuitry. The 82573 also provides the option to use the on-die voltage regulator to supply 2.5V. This option does not require
the external pass transistor for 2.5V regulation. Circuit details are shown in Figure 5
.
The 82573 controller has a LAN_PWR_GOOD input signal. This signal serves as an indicator that all power rails to the LAN device are stable and as an external reset. In a situation where a central power supply furnishes all the voltage sources,
LAN_PWR_GOOD can possibly be tied to the POWER_GOOD output of the power supply.
Designs that generate some of the voltages locally can connect LAN_PWR_GOOD to a power monitor chip. The system must drive LAN_PWR_GOOD inactive for a minimum of
50 ms, preferably 80 ms, after all three LAN power rails are stable.
82573 2.5V and 1.2V LVR Schematic
Install when using the
Integrated 2.5V Voltage
Regulator with External
Pass Transistor. Do not install if on-die 2.5V
regulator is used.
Q3 Requires Heat-
Sink surface pad of
0.5'' x 0.5'' min.
Place Q3 close to LAN Controller
1 ohm is not needed for R19 for 82573L.
0 ohm may be used instead. 82573L-only designs may connect C23 directly to 2.5V.
Intel recommends using
40uF at the emitter of Q3 on the 3.3V rail for 82573E/V.
Use ceramic capacitors.
Q4 Requires Heat-Sink surface
pad of 0.5'' x 0.5'' min.
Place Q4 close to LAN Controller
1 ohm is not needed for R18 for 82573L.
0 ohm may be used instead. 82573L-only designs may connect C29 directly to 1.2V.
Intel recommends using
40uF at the emitter of Q3 on the 3.3V rail for 82573E/V.
Use ceramic capacitors.
The power sources should ramp up during a brief power-up interval (approximately 20 ms) with LAN_PWR_GOOD de-asserted. The 82573 controller must not be left in a prolonged state where some, but not all, voltages are applied. The 3.3V power source
19
82573/82562—Design Guide
3.3.6
3.3.7
3.3.8
should be powered up prior to the 2.5V or 1.2V sources. The 2.5V and 1.2V supplies can be powered up simultaneously; otherwise, the 2.5V supply needs to power up before the 1.2V supply. At any time during power up, the supply voltages must be:
1.2V < 2.5V < 3.3V. In desktop systems based on ICH, LAN_PWR_GOOD is typically tied to the same signal that drives RSMRST# on the ICH.
82573 Controller Power Supply Filtering
Bypass capacitors, with values between 0.01 µF and 0.1 µF, are needed for each power rail. If possible, the capacitors should be placed close to the device and adjacent to power pads. Decoupling capacitors should connect to the power planes with short, thick traces of 15 mils (0.4 mm) or more and 14-mil (0.35 mm) vias. Bypass capacitance is required at the silicon.
Approximately 20µF of bulk capacitance for each of the main 1.2V and 2.5V levels is recommended. The bulk capacitors should be placed as close as possible to the device power connections.
82573 Controller Power Management and Wake Up
The 82573 supports low power operation as defined in the PCI Bus Power Management
Specification. There are two defined power states, D0 and D3. The D0 state provides full power operation and is divided into two sub-states: D0u (uninitialized) and D0a
(active). The D3 state provides low power operation and is also divided into two substates: D3hot and D3cold.
To enter the low power state, the software device driver must stop data transmission and reception. Either the operating system or the software device driver must program the Power Management Control/Status Register (PMCSR) and the Wakeup Control
Register (WUC). If wake up is desired, the appropriate wake up LAN address filters must also be set. The initial power management settings are specified by NVM bits.
When the 82573 transitions to either of the D3 low power states, the 1.2V, 2.5V, and
3.3V sources must continue to be supplied to the device. Otherwise, it will not be possible to use a wake up mechanism. The AUX_PRESENT signal is a logic input to the
82573 that denotes auxiliary power is available. If AUX_POWER is asserted, the 82573 device advertises that it supports wake up from a D3cold state.
The 82573 device supports both Advanced Power Management (APM) wake up and
Advanced Configuration and Power Interface (ACPI) wake up. Note that APM wake up is also known as Wake on LAN (WoL).
Wake up uses the PE_WAKE# signal to wake the system up. PE_WAKE# is an active low signal typically connected to WAKE# on the ICH that goes active in response to receiving a Magic Packet*, a network wakeup packet, or link status change indication.
PE_WAKE# remains asserted until it is disabled through the Power Management
Control/Status Register.
Active State Power Management Support
The 82573L is capable of supporting Active State Power Management (ASPM) PCIe* power management.
In order to support ASPM, three items are required from the platform:
1. BIOS modifications for ASPM support. The ICH7 BIOS specification can be consulted for details on implementing ASPM specifically for the 82573.
20
Design Guide—82573/82562
3.3.9
4.0
4.1
4.1.1
2. EEPROM/Flash image that supports ASPM. A LAN image advertising ASPM support is required. The 82573 NVM Map and Programming Information Guide can be consulted for details.
3. Updated LAN driver from Intel. ASPM cannot be enabled properly with a default operating system GbE driver.
82573 Device Test Capability
The 82573 contains a test access port conforming to the IEEE 1149.1a-1994 (JTAG)
Boundary Scan specification. To use the test access port, connect these balls to pads accessible by your test equipment.
A Boundary Scan Definition Language (BSDL) file describing the 82573 device is available for use in your test environment. The 82573 also contains an eXclusive-OR
(XOR) test tree mechanism for simple board tests. Details of the XOR tree operation are available from your Intel representative.
Ethernet Component Layout Guidelines
These sections provide recommendations for performing printed circuit board layouts.
Good layout practices are essential to meet IEEE PHY conformance specifications and electromagnetic interference (EMI) regulatory requirements.
General Layout Considerations for Ethernet Controllers
Critical signal traces should be kept as short as possible to decrease the likelihood of being affected by high frequency noise from other signals, including noise carried on power and ground planes. Keeping the traces as short as possible can also reduce capacitive loading.
Since the transmission line medium extends onto the printed circuit board, special attention must be paid to layout and routing of the differential signal pairs.
Designing for GbE operation is very similar to designing for 10 Mb/s and 100 Mb/s. For the 82573, system level tests should be performed at all three speeds.
Guidelines for Component Placement
Component placement can affect signal quality, emissions, and component operating temperature. This section provides guidelines for component placement.
Careful component placement can:
• Decrease potential problems directly related to EMI, which could cause failure to meet applicable government test specifications.
• Simplify the task of routing traces. To some extent, component orientation affects the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.
Minimizing the amount of space needed for the Ethernet LAN interface is important because other interfaces compete for physical space on a motherboard near the connector. The Ethernet LAN circuits need to be as close as possible to the connector.
21
82573/82562—Design Guide
Figure 6.
General Placement Distances
Keep silicon traces at least 1" from edge of
PB (2" is preferred).
Keep LAN silicon 1" - 4" from LAN connector.
Integrated
RJ-45 w/LAN
Magnetics
LAN
Silicon
Keep 50 mil minimum distance betewen TX and
RX traces (100 mils is preferred).
4.1.2
4.1.3
Figure 6 shows some basic placement distance guidelines. It shows two differential
pairs, but it can be generalized for a GbE system with four analog pairs. The ideal placement for the Ethernet silicon would be approximately one inch behind the magnetics module.
While it is generally a good idea to minimize lengths and distances, Figure 6 also shows
the need to keep the LAN silicon away from the board edge and the magnetics module for best EMI performance.
Crystals and Oscillators
Clock sources should not be placed near I/O ports or board edges. Radiation from these devices can be coupled onto the I/O ports or out of the system chassis. Crystals should also be kept away from the Ethernet magnetics module to prevent interference.
Place the crystal and load capacitors on the printed circuit boards as close to the
Ethernet component as possible, within 0.75 inch. If an oscillator is used instead of a crystal, the clock signal should be connected with the shortest, most direct trace possible. Other potentially noisy traces should be kept away from the clock trace.
External Clock Oscillator
If an external oscillator is used to provide a clock to the 82573, the connection shown
in Figure 7 must be used. The XTAL2 output signal of the 82573 must not be
connected. The XTAL1 input signal receives the output of the oscillator directly. AC coupling is not recommended.
22
Design Guide—82573/82562
Figure 7.
External Clock Oscillator Connectivity to the 82573
82573
82563EB/82564EB
XTAL2
XTAL1
3.3 V
Table 9.
4.1.4
Specification for External Clock Oscillator
Parameter Name
Frequency
Swing
Frequency Tolerance
Operating Temperature
Aging
Symbol
f o
V p-p
f/f o
T opr
f/f o
Value
25.0 MHz
3.3 ± 0.3 V
±30 ppm
0 °C to +70 °C
±5 ppm per year
Conditions
at 25 °C
-
0 °C to +70 °C
-
-
Board Stack Up Recommendations
Printed circuit boards for these designs typically have four, six, eight, or more layers.
Here is a description of a typical four-layer board stackup:
• Layer 1 is a signal layer. It can contain the differential analog pairs from the
Ethernet device to the magnetics module.
• Layer 2 is a signal ground layer. Chassis ground can also be fabricated in Layer 2 under the connector side of the magnetics module.
• Layer 3 is used for power planes.
• Layer 4 is a signal layer. For GbE designs, it is common to route two of the differential pairs on this layer.
This board stack up configuration can be adjusted to conform to specific design rules.
23
82573/82562—Design Guide
4.1.5
Figure 8.
Differential Pair Trace Routing
Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes. The following suggestions should be observed to help optimize board performance:
• Maintain constant symmetry and spacing between the traces within a differential pair.
• Keep the signal trace lengths of a differential pair equal to each other.
• Keep the total length of each differential pair under four inches. Designs with differential traces longer than five inches are much more likely to have degraded receive Bit Error Rate (BER) performance, IEEE PHY conformance failures, and excessive EMI radiation.
• Do not route the transmit differential traces closer than 100 mils to the receive differential traces.
• Do not route any other signal traces both parallel to the differential traces and closer than 100 mils to the differential traces (300 mils is recommended).
• Keep maximum separation within differential pairs to 10 mils.
• For high-speed signals, keep the number of corners and vias to a minimum. If a
90° bend is required, it is recommended to use two 45° bends instead. ( Figure 8 )
Trace Routing
45°
45°
• Route traces away from board edges by a distance greater than the trace height above the ground plane. This enables the field around the trace to couple more easily to the ground plane rather than to adjacent wires or boards.
• Do not route traces and vias under crystals or oscillators. This prevents coupling to or from the clock. As a general rule, place traces from clocks and drives at a minimum distance from apertures by a distance that is greater than the largest aperture dimension.
• Ensure that the reference plane for the differential pairs is continuous and has low impedance. It is recommended that the reference plane is either ground or 1.2V
(the voltage used by the PHY). This provides an adequate return path for high frequency noise currents.
• Do not route differential pairs over splits in the associated reference plane.
• Place differential termination components as close as possible to the LAN silicon.
• At most, use two vias per trace.
24
Design Guide—82573/82562
4.1.6
Note:
4.1.7
4.1.8
Signal Trace Geometry
The key factors in controlling trace EMI radiation are the trace length and the ratio of trace width to trace height above the ground plane. To minimize trace inductance, highspeed signals and signal layers that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1. To maintain trace impedance, the width of the trace should be modified when changing from one board layer to another if the two layers are not equidistant from the power or ground plane.
Each pair of signals should have a differential impedance of 100 . ±15%. If a particular tool cannot design differential traces, it is permissible to specify 55 to 65 single-ended traces as long as the spacing between the two traces is minimized. As an example, consider a differential trace pair on Layer 1 that is 8 mils (0.2 mm) wide and
2 mils (0.05 mm) thick, with a spacing of 8 mils (0.2 mm). If the fiberglass layer is 8 mils (0.2 mm) thick with a dielectric constant, E
R
, of 4.7, the calculated single-ended impedance would be approximately 61 and the calculated differential impedance would be approximately 100 .
When performing a board layout, the CAD tool must not automatically route the differential pairs without intervention. In most cases, the differential pairs will have to be routed manually.
Measuring trace impedance for layout designs targeting 100 often results in lower actual impedance. Designers should verify actual trace impedance and adjust the layout accordingly. If the actual impedance is consistently low, a target of 105 to
110 should compensate for second order effects.
It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential impedance by up to 10 , when the traces within a pair are closer than 30 mils (edge-to-edge).
Trace Length and Symmetry
As indicated earlier, the overall length of differential pairs should be less than four inches measured from the Ethernet device to the magnetics.
The differential traces (within each pair) should be equal within 50 mils (1.25 mm) and as symmetrical as possible. Asymmetrical and unequal length traces in the differential pairs contribute to common mode noise. Common mode noise can degrade the receive circuit’s performance and contribute to radiated emissions.
Impedance Discontinuities
Impedance discontinuities cause unwanted signal reflections. Thus, vias (signal through holes) and other transmission line irregularities should be avoided. If vias must be used, a reasonable budget is two per differential trace. Unused pads and stub traces should also be avoided.
25
82573/82562—Design Guide
4.1.9
4.1.10
Note:
4.1.11
Reducing Circuit Inductance
Traces should be routed over a continuous ground plane with no interruptions. If there are vacant areas on a ground or power plane, the signal conductors should not cross the vacant area. This increases inductance and associated radiated noise levels. Noisy logic grounds should be separated from analog signal grounds to reduce coupling.
Noisy logic grounds can also affect sensitive DC subsystems such as analog to digital conversion, operational amplifiers, etc. All ground vias should be connected to every ground plane; and similarly, every power via, to all power planes at equal potential.
This helps reduce circuit inductance. Another recommendation is to physically locate grounds to minimize the loop area between a signal path and its return path. Rise and fall times should be as slow as possible since signals with fast rise and fall times contain many high frequency harmonics, which can radiate significantly. The most sensitive signal returns closest to the chassis ground should be connected together. This results in a smaller loop area and reduce the likelihood of crosstalk. The effect of different configurations on the amount of crosstalk can be studied using electronics modeling software.
Signal Isolation
To maintain best signal integrity, digital signals should be far away from the analog traces. A good rule to follow is no digital signal should be within 30 mils (7.5 mm) of the differential pairs. If digital signals on other board layers cannot be separated by a ground plane, they should be routed at right angles with respect to the differential pairs. If there is another LAN controller on the board, the differential pairs should be kept away from that circuit.
Some rules to follow for signal isolation:
• Separate and group signals by function on separate layers if possible. If possible, maintain a gap of 50 mils between all differential pairs (Ethernet) and other nets, but group associated differential pairs together.
Over the length of the trace run, each differential pair should be at least 0.3 inches away from any parallel signal traces.
• Physically group together all components associated with one clock trace to reduce trace length and radiation.
• Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals.
• Avoid routing high-speed LAN traces near other high-frequency signals associated with a video controller, cache controller, processor, or other similar devices.
Power and Ground Planes
Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return. These practices significantly reduce EMI radiation.
The following guidelines help reduce circuit inductance in both backplanes and motherboards:
• Route traces over a continuous plane with no interruptions. Do not route over a split power or ground plane. If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This increases inductance and EMI radiation levels.
• Separate noisy digital grounds from analog grounds to reduce coupling. Noisy digital grounds can affect sensitive DC subsystems.
26
Design Guide—82573/82562
4.1.12
4.1.13
Figure 9.
• Connect all ground vias to every ground plane and every power via to all power planes at equal potential. This helps reduce circuit inductance.
• Physically locate grounds between a signal path and its return. This minimizes the loop area.
• Avoid fast rise and fall times as much as possible. Signals with fast rise and fall times contain many high frequency harmonics, which can radiate EMI.
• Split ground planes beneath magnetics modules. The RJ-45 connector side of the transformer module should have chassis ground beneath it.
Traces for Decoupling Capacitors
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and thin traces are more inductive and would reduce the intended effect of decoupling capacitors. For similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the decoupling capacitors should be sufficiently large in diameter to decrease series inductance.
Ground Planes Under the Magnetics Module
The magnetics module chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of
100 mils minimum. Splitting the ground planes beneath the transformer minimizes noise coupling between the primary and secondary sides of the transformer and between the adjacent coils in the magnetics. This arrangement also improves the common mode choke functionality of magnetics module.
Ground Plane Separation
0.10 Inches Minimum Spacing
Magnetics Module
Void or Separate Ground Plane
Separate Chassis Ground Plane
Gnd_Plane_Sep
Figure 9 shows the split plane layout for a discrete magnetics module. Capacitors are
used to interconnect chassis ground and signal ground.
27
82573/82562—Design Guide
Figure 10 shows the preferred method for implementing a ground split under an
integrated magnetics module/RJ-45 connector. The capacitor stuffing options (C1 through C6) are used to reduce and filter high frequency emissions. The values of the capacitor stuffing options can be different for each board. Experiments need to be performed to determine which values provide best EMI performance.
Figure 10.
Ideal Ground Split Implementation
Board Edge RJ/Mag.
Chassis
GND
Capacitor
Stuffing
Options
RJ Shield connected to
Chassis
GND
Capacitor
Stuffing
Options
C1
C2
C3
C4
C5
Digital
GND
C6
Resistive
Terminations
28
The following table lists possible starting values for these capacitors.
Capacitors Value
C3, C4
C1, C2, C5, C6
4.7µF or 10 µF
470 pF to 0.1 µF
The placement of C1 through C6 can also be different for each board design (not all of the capacitors might need to be populated). Also, the capacitors might not be needed on both sides of the magnetic module.
Design Guide—82573/82562
4.2
Layout for the 82562 PLC Device
This section provides layout guidelines specific to the 82562 PLC device.
4.2.1
Termination Resistors for Designs Based on 82562 PLC Device
The recommended value to terminate the transmit and receive differential pairs is
110 ±1%. These termination resistors should be placed as close to the Platform LAN connect component as possible. This is due to the fact these resistors are terminating the entire impedance that is seen at the termination source, including the wire impedance reflected through the transformer.
Figure 11.
82562 PLC Device Differential Signal Termination
MDI
MDI
Intel
®
ICH7
Lan Connect
Interface
Intel LAN Device
Magnetics
Module
RJ45
4.2.2
4.3
4.3.1
4.3.2
Place termination resistors as close to the Intel LAN device as possible.
Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC
Device
The 82562 PLC device has three high-current outputs to directly drive LEDs for link, activity and speed indication. Since LEDs are likely to be integral to a magnetics module, the LED traces need to be routed away from potential sources of EMI noise. In some cases, it might be desirable to attach filter capacitors.
Layout for the 82573
Termination Resistors for 82573-Based Designs
The four differential pairs are terminated with 49.9 (1% tolerance) resistors, placed near the 82573. One resistor connects to the positive MDI signal trace and another resistor connects to the negative MDI signal trace. The opposite ends of the resistors connect together and to ground through a single 0.1 µF capacitor. The capacitor should be placed as close as possible to the 49.9 ohm resistors, using a wide trace.
Suggested component values should not be varied. The pads and traces for these components should be arranged with symmetrical pads and traces so that the length and symmetry of the differential pairs are not disturbed.
Light Emitting Diodes for 82573-Based Designs
The 82573 controller provides three programmable high-current outputs to directly drive LEDs for link activity and speed indication. Since the LEDs are likely to be integral to a magnetics module, the LED traces should be routed away from potential sources of
EMI noise. In some cases, it might be desirable to attach filter capacitors.
29
4.4
4.5
82573/82562—Design Guide
Physical Layer Conformance Testing
Physical layer conformance testing (IEEE testing) is a fundamental requirement for all
Ethernet LAN products. PHY testing is the final determination that a layout has been performed successfully. If designers do not have the resources and equipment to perform these tests, consideration should be made to have these tests contracted to an outside facility.
Crucial tests are as follows, listed in order of priority:
1. Bit Error Rate (BER). This is a good indicator of real world network performance.
Perform bit error rate testing with long and short cables and many link partners.
2. Output Amplitude, Rise and Fall Time (10/100 Mb/s), Symmetry and Droop (1000
Mb/s). The appropriate PHY test waveform for the 82573 should be used.
3. Return Loss. This indicates proper impedance matching and is measured through the RJ-45 connector back toward the magnetics module.
4. Jitter Test (10/100 Mb/s) or Unfiltered Jitter Test (1000 Mb/s). This indicates clock recovery ability (master and slave for the GbE controller).
5. Harmonic Content for 10 Mb/s.
6. Duty Cycle Distortion for 100 Mb/s.
Troubleshooting Common Physical Layout Issues
The following is a list of common physical layer design and layout mistakes in LOM
Designs.
1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and will distort the transmit or receive waveforms.
2. Lack of symmetry between the two traces within a differential pair. Asymmetry can create common-mode noise and distort the waveforms. For each component and via that one trace encounters, the other trace should encounter the same component or via at the same distance from the Ethernet silicon.
3. Excessive distance between the Ethernet silicon and the magnetics. Long traces on
FR4 fiberglass epoxy substrate will attenuate the analog signals. In addition, any impedance mismatch in the traces will be aggravated if they are longer than the four-inch rule.
4. Routing any other trace parallel to and close to one of the differential traces.
Crosstalk getting onto the receive channel will cause degraded long cable BER.
Crosstalk getting onto the transmit channel can cause excessive EMI emissions and can cause poor transmit BER on long cables. At a minimum, other signals should be kept 0.3 inches from the differential traces.
5. Routing one pair of differential traces too close to another pair of differential traces.
After exiting the Ethernet silicon, the trace pairs should be kept 0.3 inches or more away from the other trace pairs. The only possible exceptions are in the vicinities where the traces enter or exit the magnetics, the RJ-45 connector, and the
Ethernet silicon.
6. Use of a low quality magnetics module.
7. Re-use of an out-of-date physical layer schematic in an Ethernet silicon design. The terminations and decoupling can be different from one PHY to another.
30
Design Guide—82573/82562
5.0
5.1
Table 10.
5.2
Note:
8. Incorrect differential trace impedances. It is important to have ~100 W impedance between the two traces within a differential pair. This becomes even more important as the differential traces become longer. To calculate differential impedance, many impedance calculators only multiply the single-ended impedance by two. This does not take into account edge-to-edge capacitive coupling between the two traces. When the two traces within a differential pair are kept close to each other, the edge coupling can lower the effective differential impedance by 5 W to
20 W. Short traces have fewer problems if the differential impedance is slightly off target.
9. For the 82562EZ(EX) PLC design, use of a capacitor too large between the transmit traces or too much capacitance on the magnetic module’s transmit center tap to ground. Using capacitors more than a few pico-Farads in either of these locations can slow the 100 Mb/s rise and fall times. This also causes return loss to fail at higher frequencies and degrades the transmit BER performance. If a capacitor is used, it should be less than 22 pF.
Flash Guidelines
General guidelines and design considerations for supporting Flash devices is discussed in this section.
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) is new and is used to support a single SPI compatible Flash device. The SPI device can be used exclusively as the system BIOS device, exclusively for the Intel
®
82573.
82573, or shared between system BIOS and the
SPI Signal Description for the ICH7
ICH7 Signal Name
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_CS#
SPI_ARB
Description
SPI serial output data from the Intel® ICH7 to the SPI Flash device.
SPI serial input data from the SPI Flash device to the Intel® ICH7.
SPI clock output from the Intel® ICH7.
SPI chip select.
SPI arbitration signal. This signal is used to arbitrate the SPI bus with the 82573 when shared Flash is implemented.
Serial Flash Vendors
The following vendors manufacture serial Flash devices that have been used successfully in previous designs. Additional details on the compatibility requirements for SPI devices can be obtained through the ICH7 External Design Specification (EDS).
Information on packaging and density on SPI devices can be obtained directly through the vendor.
SST: http://www.ssti.com/
STM: http://us.st.com/stonline/index.shtml
This is not an extensive list. There might be other vendors. Your local Flash vendor can be contacted to determine if a compatible device is available.
31
82573/82562—Design Guide
5.3
5.3.1
Serial Peripheral Interface General Routing Guidelines
This section contains preliminary information and details for layout and routing guidelines for the ICH7 SPI. Additional serial Flash specific design considerations can be referred to the serial Flash vendor documentation.
The guidelines in this section cover three main topologies:
1. Non-shared Topology: The SPI device is used exclusively as the system BIOS. This document covers the guidelines on the SPI device used exclusively for the 82573.
(
2. Shared Topology: The SPI device is shared between the system BIOS and the
82573.
3. Stuffing Options: This option supports a non-shared configuration for either system
BIOS or for the 82573 through a single serial Flash device or shared topology through a single serial Flash device using stuffing options on the motherboard.
Routing Summary
Figure 12.
SPI as System BIOS Topology (Non-shared Technology)
VccSus3_3
Intel® ICH7
SPI_MOSI
SPI_MISO
SPI_CS#
SPI_CLK
R1
R1
R R
L1
L1
L1
L1
R
R2
Serial Flash
Serial In
Serial Out
Chip Select
Clock
Notes:
1.
2.
3.
R = 8.2 K to 10 K should be placed close to the ICH7 component.
R1 = 47 for desktop systems or 33 for mobile designs. R1 should be placed less than 100 mils from the ICH7 device.
R2 = 47 for desktop systems or 33 for mobile designs. R2 should be placed less than 100 mils from the serial Flash device.
32
Design Guide—82573/82562
Table 11.
SPI Non-shared Routing Summary for the 2116 Stackup
Signal Name Impedance
Width (W) /
Spacing (S)
Layer Length
SPI_MOSI
SPI_MISO#
SPI_CS#
SPI_CLK
60 ± 15%
W = 5 mils
S = 7 mils
Microstrip L1 = 0.5 – 11”
Figure
Note:
1.
“W” represents the width of the signal. “S” represents spacing to any other signal.
1
Notes
Table 12.
SPI Non-shared Routing Summary for the 1080 Stackup
Signal Name Impedance
Width (W) /
Spacing (S)
Layer Length
SPI_MOSI
SPI_MISO#
SPI_CS#
SPI_CLK
50 ± 15%
W = 4 mils
S = 5 mils
Microstrip L1 = 0.5 – 10”
Figure
Note:
1.
“W” represents the width of the signal. “S” represents spacing to any other signal.
1
Notes
Table 13.
SPI Non-shared Routing Summary for the Mobile Stackup
Signal Name Impedance
Width (W) /
Spacing (S)
Layer Length
SPI_MOSI
SPI_MISO#
SPI_CS#
SPI_CLK
55 ± 15%
W = 4 mils
S = 5 mils
Stripline L1 = 0.5 – 10”
Figure
Note:
1.
“W” represents the width of the signal. “S” represents spacing to any other signal.
1
Notes
33
82573/82562—Design Guide
Figure 13.
SPI Shared Flash Exclusively Used with Intel
®
82573
Intel® ICH7
SPI_MOSI
SPI_MISO
SPI_CS#
SPI_CLK
SPI_ARB
L1A
L1A
L1A
L1A
L1B
L1B
R
R
L1B
L1B
R
Serial Flash
Serial Input
Serial Output
Chip Select
Clock
L2
L1C
L1C
L1C
L1C
Intel® 82573
NVM_SI
NVM_SO
NVM_CS#
NVM_CLK
NVM_REQ
Table 14.
Note:
R = 47 and should be placed within 100 mils of the Flash device. (For mobile designs, R should be placed within 500 mils of the Flash device.)
SPI Shared Topology Routing Summary for the 2116 Stackup
Signal Name Impedance
Width (W) /
Spacing (S)
Layer Length Figure
SPI_MOSI
SPI_MISO#
SPI_CS#
SPI_CLK
SPI_ARB
60 ± 15%
W = 5 mils
S = 7 mils
Microstrip
L1
L1
A
B
L1 c
= 0.5 – 8”
= 0.1” target
= 0.1 – 14”
L2 = 1” – 18”
1
Notes
Note:
1.
“W” represents the width of the signal. “S” represents spacing to any other signal.
34
Design Guide—82573/82562
Table 15.
SPI Shared Topology Routing Summary for the 1080 Stackup
Signal Name Impedance
Width (W) /
Spacing (S)
Layer Length
SPI_MOSI
SPI_MISO#
SPI_CS#
SPI_CLK
SPI_ARB
50 ± 15%
W = 4 mils
S = 5 mils
Microstrip
Figure
L1
L1
L1
A
B c
= 0.5 – 8”
= 0.1” target
= 0.5 – 14”
L2 = 1” – 18”
Note:
1.
“W” represents the width of the signal. “S” represents spacing to any other signal.
1
Notes
Table 16.
SPI Shared Topology Routing Summary for the Mobile Stackup
Signal Name Impedance
Width (W) /
Spacing (S)
Layer Length Figure
SPI_MOSI
SPI_MISO#
SPI_CS#
SPI_CLK
SPI_ARB
55 ± 15%
W = 4 mils
S = 7 mils
Stripline
L1
L1
L1
A
B c
= 0.5 – 10”
= 0.1” target
= 0.5 – 6”
L2 = 11”
Note:
1.
“W” represents the width of the signal. “S” represents spacing to any other signal.
Figure 14.
Stuffing Options Supporting Shared Topology (Desktop Only)
VccSus3_3
SPI_MOSI
1
Notes
Intel ®
ICH7
L1
R4
R1
L1
L2
R2
L3 L1
L2
R3
L5
R5
L1
Serial Flash
R7
L1
Intel ®
82573
35
36
82573/82562—Design Guide
VccSus3_3
SPI_MISO
Intel ®
ICH7
L4
R1
L2
L3
R2
L2 L1
L2
R3
R5
L1
Serial Flash
L5
Intel ®
82573
SPI_CS#
VccSus3_3
Intel
®
ICH7
L4
R1
L2
L3
R2
L2
L2
R3
L5
Intel
®
82573
L4
Serial Flash
Design Guide—82573/82562
Intel
®
ICH7
L1
R4
L3
L2
SPI_SCK
R2
L2 L1
L2
R3
R5
L1
Serial Flash
L5
L2
L2
R6
R7
L1
Intel
®
82573
Intel
®
ICH7
SPI_ARB
L6
R9
Intel
®
82573
Table 17.
Configurations and Stuffing Options
Configurations
SPI device as system BIOS only
SPI device used exclusively with the 82573
SPI Device shared between system BIOS and 82573
Stuffing Options
R1 = 8.2 K to 10 K
R2, R5 = 0
R4, R8 = 47
R3, R6, R7, R9 = Empty
R1, R2, R4 = Empty
R3, R5, R9 = 0
R6 = 8.2 K to 10 K
R7, R8 = 47
R1, R6 = Empty
R2, R3, R4, R7, R9 = 0
R5, R8 = 47
37
82573/82562—Design Guide
Table 18.
SPI Stuffing Option Topology Routing Summary for the 2116 Stackup
Signal Name Impedance
Width (W) /
Spacing (S)
Layer Length Figure
SPI_MOSI
SPI_MISO#
SPI_CS#
SPI_CLK
SPI_ARB
60 ± 15%
W = 5 mils
S = 7 mils
Microstrip
L1 = 0.1” target
L2 = 0.1 - 0.25”
L3 = 0.5” - 7.5”
L4 = 0.2”
L5 = 1” - 14”
L6 = 1”–18”
Note:
1.
“W” represents the width of the signal. “S” represents spacing to any other signal.
1
Notes
Table 19.
5.3.2
5.3.3
SPI Stuffing Option Topology Routing Summary for the 1080 Stackup
Signal Name Impedance
Width (W) /
Spacing (S)
Layer Length Figure
SPI_MOSI
SPI_MISO#
SPI_CS#
SPI_CLK
SPI_ARB
50 ± 15%
W = 4 mils
S = 5 mils
Microstrip
L1 = 0.1” target
L2 = 0.1 -
0.25”
L3 = 0.5” - 7.5”
L4 = 0.2”
L5 = 1” - 14”
Note:
1.
“W” represents the width of the signal. “S” represents spacing to any other signal.
Notes
1
Terminating Unused SPI Signals
If the SPI is not implemented on the platform, all SPI signals can be left unconnected.
SPI Dual Footprint - SO8 and SO16 Packages
Although SPI is comprised of a 4-signal bus, SPI devices can be found in both 8-pin and
16-pin Small Outline Integrated Circuit (SOIC) packages. This section contains an example of an SO8 and SO16 dual footprint to accommodate both packages on the board. More details regarding these devices can be found in the vendors’ datasheets.
38
Design Guide—82573/82562
Figure 15.
SPI Dual Footprint for SO8 and SO16 Packages
HOLD#
Vcc
NC
NC
NC
NC
Chip Select
Data Out
Clock
Data In
NC
NC
NC
NC
Vss
Write Protect#
39
82573/82562—Design Guide
5.4
5.4.1
82573/82562 PLC Ball Outs
82573E/82573V Ball Out
1
A
VSS
B C
VCC25_
OUT
PE_T0n
D E
PE_TR0p NC
2
IREG25_IN
VCC25_
OUT
VSS VSS VSS
F G H
PE_R0n PE_CLKp TEST0
J
PE_R0p PE_CLKn TEST1 TEST4 VSS
K
TEST3 TEST6
L
TEST7
M
TEST8
N
VSS
P
TEST11
THERMn FUSEV TEST10 VCC33
3
IREG25_IN
VSS NC
NVM_
SHARED
TEST15 VCC33 VCC25 TEST2 TEST5 VCC12 THERMp TEST9 TEST12
CTRL_12
4 CTRL_25 NVM_REQ
VCC12
VSS
5
NVM_
PROT
EN25REG
VCC12
VSS
6
NVM_
TYPE
VCC25
AUX_
PRESENT
VSS
7
VCC33 NC SDP[3] VSS
8 SDP[0] SDP[1]
SDP[2]
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC25
VCC12
VCC25 VCC33 VCC12 NC
VCC25
JTAG_TMS JTAG_TDI
VCC25
VCC12
VCC25
VCC12
VCC12
VCC12
VCC12
NC
NC
NC
JTAG_
TCK
LAN_PWR_
GOOD
VCC33
JTAG_TDO
VSS VCC12 VCC12 VCC12
DEVICE_
OFF#
NC VCC25 PE_RST#
VSS VSS VSS VCC12 VCC12 VCC12 NC TEST13 VCC33 VSS
9 NVM_SI NVM_SO NVM_SK
VCC33 VSS VSS VSS VSS VCC12 VCC12 VCC12 NC NC TEST14
10 VCC12
NVM_CS#
VSS NC
11 VCC25 LED0# LED1# NC NC
12 LED2#
PHY_
HSDACp
VSS PHY_REF NC
VSS VSS VSS VSS VCC12 VCC12 VCC12 VCC33 ALT_CLK125
PE_WAKE#
VSS
VCC12
VSS
VCC12
VCC12 VCC12
VCC12 VCC25
VCC12
NC
NC
VCC25
SMB_DAT
SMB_ALRT#/
ASF_PWR_
GOOD
SMB_CLK
NC VSS VCC33
13 TEST_EN
PHY_
HSDACn
MDI0p VSS
14 TEST16
PHY_
TSTPT
MDI0n NC
MDI1p MDI2p VCC12 MDI3p NC
MDI1n MDI2n VSS
VCC25 NC NC
MDI3n XTAL2 XTAL1
CLK_VIEW
NC
NC
NC
NC
NC
40
Design Guide—82573/82562
5.4.2
82573L Ball Out
1
A
VSS
B C
VCC25_
OUT
PE_T0n
D E
PE_TR0p NC
2
VCC3.3_
REG25
VCC25_
OUT
VSS
3
VCC3.3_
REG25
VSS NC
VSS VSS
NVM_
SHARED
NC
F G H
PE_R0n PE_CLKp TEST0
J
TEST3 TEST6
PE_R0p PE_CLKn TEST1 TEST4 VSS
VCC33 VCC25 TEST2
K L
TEST7
M
TEST8 VSS
N
TEST5 VCC12 THERMp TEST9 NC
P
NC
THERMn FUSEV TEST10 VCC33
CTRL_12
4 CTRL_25 NVM_REQ
VCC12
VSS
5
NVM_
PROT
EN25REG
VCC12
VSS
6
NVM_
TYPE
VCC25 AUX_PWR VSS
7
VCC33 NC NC VSS
8 NC NC
NC
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC25
VCC12
VCC25 VCC33 VCC12 NC
VCC25
JTAG_TMS JTAG_TDI
VCC25
VCC12
VCC25
VCC12
VCC12
VCC12
VCC12
NC
NC
NC
JTAG_
TCK
LAN_PWR_
GOOD
VCC33
JTAG_TDO
VSS VCC12 VCC12 VCC12
DEVICE_
OFF#
NC VCC25 PE_RST#
VSS VSS VSS VCC12 VCC12 VCC12 NC NC VCC33 VSS
9 NVM_SI NVM_SO NVM_SK
VCC33 VSS VSS
10 VCC12
NVM_CS#
VSS
VSS VSS VCC12 VCC12 VCC12 NC NC CLK_REQ#
NC VSS VSS VSS VSS VCC12 VCC12 VCC12 VCC33 ALT_CLK125
PE_WAKE#
11 VCC25 LED0# LED1# NC NC
12 LED2#
PHY_
HSDACp
VSS PHY_REF NC
VSS VSS VCC12 VCC12 VCC12 NC
VCC12 VCC12 VCC12 VCC25 NC
RSVD
VCC25 NC VSS
RSVD RSVD
VCC33
13 TEST_EN
PHY_
HSDACn
MDI0p VSS
14 NC
PHY_
TSTPT
MDI0n NC
MDI1p MDI2p VCC12 MDI3p NC
MDI1n MDI2n VSS
VCC25 NC NC
MDI3n XTAL2 XTAL1
CLK_VIEW
NC
NC
NC
NC
NC
41
82573/82562—Design Guide
5.4.3
1
A
NC
2
NC
82562EX Ball Out
B
NC
NC
3
VCC
VSS
C
NC
D
NC
E
VCC
F
NC
G
NC
H
NC
J
NC
K
NC
L
NC
M
NC
N
VSS
NC
NC
VSS
NC NC
NC
NC
NC
NC
NC NC
VSS
NC
NC
NC
VCC
NC NC
NC
NC NC
NC
VCC
NC
P
NC
4
NC NC
5
NC
NC
NC
VSS VSS
VSS NC
NC
NC VCC
VCC
NC
NC
NC
VSS VSS
VSS
VCCR
VCCR
VCCR VCC VCC
NC NC
NC
NC
6
NC
7
VCC
VSS
8
NC NC
NC
NC VSS VSS
NC
VSS VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VCC VCC
VCC
ADV10 NC
VCC
NC
NC
NC
NC
VSS VSS
VSS
VSS VCC VCC VCC
NC
NC VCC VSS
9
NC
NC
NC
NC
VSS VSS VSS VSS VCC
VCC
VCC
NC
10
NC
NC VSS
ISOL_EXEC
VSS
VSS
VSS
VSS
11
VCCT
SPDLED# ACTLED#
NC
VCCT VSS
VSS
VCC VCC
VCC
VCC
VCC VCC
VSS
NC
NC
NC
NC
NC
NC
NC
NC
12
LILED# TOUT
VSSA ISOL_TI
VCCT
13
TESTEN
RBIAS100
TDP
VSSA RDP
14
NC RBIAS10 TDN
ISOL_TCK
RDN
NC
NC
NC
NC
NC
NC VSS
NC
NC
VCC
NC
JRXD[2] VSSP
VCC
JTXD[1]
JRSTSYNC
JRXD[1]
JRXD[0]
NC NC
NC
X2 X1
JTXD[2] JTXD[0]
JCLK NC
42
Design Guide—82573/82562
5.4.4
1
A
NC
82562GZ Ball Out
B
NC
C
NC
D
NC
E
VCC
F
NC
2
NC NC NC NC VSS
NC
3
VCC VSS NC NC NC
NC
G
NC
H
NC
J
NC
K
NC
L
NC
M
NC
N
VSS
P
NC
NC NC NC VSS NC NC NC VCC
NC NC NC VCC NC NC NC NC
4
NC NC
5
NC NC
NC VSS VSS VSS NC NC NC VCC 3.3V
NC NC NC
NC
VSS VSS VSS VCCR VCCR VCCR 3.3V
3.3V
NC NC NC
6
NC NC NC VSS VSS VSS 3.3V
3.3V
3.3V
3.3V
VSS VSS VCC NC
7
VCC VSS
8
NC NC
NC
NC
VSS VSS VSS VSS 3.3V
3.3V
3.3V
ADV10/
LAN_
DISABLE#
NC
VSS VSS VSS VSS 3.3V
3.3V
3.3V
NC NC
NC NC
VCC VSS
9
NC NC NC
10
NC
NC
NC
NC
NC VSS VSS VSS VSS 3.3V
3.3V
3.3V
NC
VSS
ISOL_
EXEC
VSS VSS VSS VSS 3.3V
3.3V
3.3V
NC NC NC
11
VCC
SPDLED# ACTLED#
NC VCCT VSS VSS 3.3V
3.3V
3.3V
VSS NC NC NC
12
LILED# TOUT VSS ISOL_TI VCCT NC
13
TESTEN
RBIAS
100
TDP VSS RDP
14
NC
RBIAS
10
TDN
ISOL_
TCK
RDN
NC
NC
NC NC
3.3V
NC
VSS NC
NC VSS NC JRXD[1] VSS VCC
NC VCC JTXD[1]
JRSTSYNC
JRXD[1] JRXD[0]
X2 X1 JTXD[2] JTXD[0] JCLK NC
43
82573/82562—Design Guide
6.0
6.1
Table 20.
6.1.1
6.1.2
Crystal Guidelines
Crystal Selection Parameters
Quartz crystals are generally considered to be the mainstay of frequency control components due to their low cost and implementation simplicity. They are available from numerous vendors in many package types and with various specification options.
All crystals used with Intel
®
Ethernet controllers are described as “AT-cut”, which refers to the angle the unit is sliced with respect to the long axis of the quartz stone.
lists the crystal electrical parameters and provides suggested values for typical designs. The parameters listed are described in the following subsections.
Crystal Parameters
Parameter
Vibration Mode
Nominal Frequency
Frequency Tolerance
Temperature Stability
Calibration Mode
Load Capacitance
Shunt Capacitance
Equivalent Series Resistance
Drive Level
Aging
Recommended crystal manufacturers:
Suggested Value
Fundamental
25.000 MHz at 25
°
C (required)
• ±30 ppm recommended at 25
°
C
• ±30 ppm required for the 82573L only
±30 ppm at 0
°
C to 70
°
C required for the 82573
Parallel
20 pF
6 pF maximum
• For 82573: 40 at 25 MHz
• For 82562: 20 at 25 MHz
0.5 mW
±5 ppm per year maximum
Rami Technology Asia Ltd*
TXC Corporation*
AS-25.000-20-F-SMD-TR-NS5
6C25000355
Vibration Mode
Crystals in the frequency range listed in Table 20
are available in both fundamental and third overtone. Unless there is a special need for third overtone, fundamental mode crystals should be used.
At any given operating frequency, third overtone crystals are thicker and more rugged than fundamental mode crystals. Third overtone crystals are more suitable for use in military or harsh industrial environments. Third overtone crystals require a trap circuit
(extra capacitor and inductor) in the load circuitry to suppress fundamental mode oscillation as the circuit powers up. Selecting values for these components is beyond the scope of this document.
Nominal Frequency
Intel Ethernet controllers use a crystal frequency of 25.000 MHz. The 25 MHz input is used to generate a 125 MHz transmit clock for 100BASE-TX and 1000BASE-TX operation. 10 MHz and 20 MHz transmit clocks are used for 10BASE-T operation.
44
Design Guide—82573/82562
6.1.3
Note:
Frequency Tolerance
The frequency tolerance for an Ethernet physical layer device is dictated by the IEEE
802.3 specification as ±50 parts per million (ppm). This measurement is referenced to a standard temperature of 25° C.
Intel recommends using a crystal device with a ±30 ppm frequency tolerance to ensure that the total crystal circuit tolerance does not exceed ±50 ppm. In addition to the crystal device, factors such as PCB trace capacitance, pad capacitance, and loading capacitors’ tolerance add to the overall frequency variance.
6.1.4
Note:
Temperature Stability and Environmental Requirements
Temperature stability is a standard measure of how the oscillation frequency varies over the full operational temperature range (and beyond). Several optional temperature ranges are currently available, including -40° C to +85° C for industrial environments. Some vendors separate operating temperatures from temperature stability. Manufacturers may also list temperature stability as
50 ppm in their data sheets.
Crystals also carry other specifications for storage temperature, shock resistance, and reflow solder conditions. Crystal vendors should be consulted early in the design cycle to discuss the application and its environmental requirements.
6.1.5
Calibration Mode
The terms “series-resonant” and “parallel-resonant” are often used to describe crystal circuits. Specifying parallel mode is critical to determining how the crystal frequency is calibrated at the factory.
A crystal specified and tested as series-resonant oscillates without problem in a parallel-resonant circuit, but the frequency is higher than nominal by several hundred parts per million. The purpose of adding load capacitors to a crystal circuit is to establish resonance at a frequency higher than the inherent series resonant frequency of the crystal.
Figure 16 illustrates a simplified schematic of the 82562 and the 82573 crystal circuit.
The crystal and the capacitors form a feedback element for the internal inverting amplifier. This combination is called parallel-resonant because it has positive reactance at the selected frequency. In other words, the crystal behaves like an inductor in a parallel LC circuit.
Figure 16.
Crystal Circuit
LAN
Silicon
X1 or Xin
LAN
Silicon
X2 or Xout
C1 C2
45
82573/82562—Design Guide
6.1.6
Note:
6.1.7
6.1.8
Note:
Load Capacitance
The formula for crystal load capacitance is as follows:
C
L
=
stray where C1 = C2 = 22 pF (as suggested in most Intel reference designs) and C stray
= allowance for additional capacitance in pads, traces and the chip carrier within the Ethernet controller package
An allowance of 3 pF to 7 pF accounts for lumped stray capacitance. The calculated load capacitance is 16 pF with an estimated stray capacitance of about 5 pF.
Individual stray capacitance components can be estimated and added. For example, surface mount pads for the load capacitors add approximately 2.5 pF in parallel to each capacitor. This technique is especially useful if Y1, C1 and C2 must be placed farther than approximately one-half (0.5) inch from the controller. It is worth noting that thin circuit boards generally have higher stray capacitance than thick circuit boards.
Standard capacitor loads used by crystal manufacturers include 16 pF, 18 pF and 20 pF.
Any of these values will generally operate with the controller. However, a difference of several pico-Farads between the calibrated load and the actual load will pull the oscillator slightly off frequency.
C1 and C2 may vary by as much as 5% (approximately 1 pF) from their nominal values.
Shunt Capacitance
The shunt capacitance parameter is relatively unimportant compared to load capacitance. Shunt capacitance represents the effect of the crystal’s mechanical holder and contacts. The shunt capacitance should equal a maximum of 6 pF (7 pF is also acceptable).
Equivalent Series Resistance
Equivalent Series Resistance (ESR) is the real component of crystal impedance at the calibration frequency, which the inverting amplifier loop gain must overcome. ESR varies inversely with frequency for a given crystal family. The lower the ESR, the faster the crystal starts up. Crystals with an ESR value of 50 or better should be used.
The specific controller documentation should be verified since some devices may have tighter ESR requirements. For example, Intel recommends that 82573 devices use crystals with an ESR value of 20 or less.
46
Design Guide—82573/82562
6.1.9
6.1.10
6.2
Note:
Drive Level
Drive level refers to power dissipation in use. The allowable drive level for a Surface
Mounted Technology (SMT) crystal is less than its through-hole counterpart since surface mount crystals are typically made from narrow, rectangular AT strips, rather than circular AT quartz blanks.
Some crystal datasheets list crystals with a maximum drive level of 1 mW. However,
Intel Ethernet controllers drive crystals to a level less than the suggested 0.5 mW value. This parameter does not have much value for on-chip oscillator use.
Aging
Aging is a permanent change in frequency (and resistance) occurring over time. This parameter is most important in its first year because new crystals age faster than old crystals. Crystals used should have a maximum of ±5 ppm per year aging.
Reference Crystal
The normal tolerances of the discrete crystal components can contribute to small frequency offsets with respect to the target center frequency. To minimize the risk of tolerance-caused frequency offsets causing a small percentage of production line units to be outside of the acceptable frequency range, it is important to account for those shifts while empirically determining the proper values for the discrete loading capacitors, C1 and C2.
Most crystals will oscillate slightly higher or slightly lower than the exact center of the target frequency even with a perfect support circuit. Therefore, frequency measurements (which determine the correct value for C1 and C2) should be performed with an ideal reference crystal. When the capacitive load is exactly equal to the crystal load rating, an ideal reference crystal will be perfectly centered at the desired target frequency.
There are several methods available for choosing the appropriate reference crystal:
• If a Saunders and Associates (S&A) crystal network analyzer is available, then discrete crystal components can be tested until one is found with zero or nearly zero ppm deviation (with the appropriate capacitive load). A crystal with zero or near zero ppm deviation will be a good reference crystal to use in subsequent frequency tests to determine the best values for C1 and C2.
• If a crystal analyzer is not available, then the selection of a reference crystal can be done by measuring a statistically valid sample population of crystals, which has units from multiple lots and approved vendors. The crystal, which has an oscillation frequency closest to the center of the distribution, should be the reference crystal used during testing to determine the best values for C1 and C2.
• It may also be possible to ask the approved crystal vendors or manufacturers to provide a reference crystal with zero or nearly zero deviation from the specified frequency when it has the specified C-load capacitance.
For the 82562 devices, it is recommended to choose a crystal with an ESR value of
20 For the 82573 devices, it is recommended to choose a crystal with an ESR value of 40 or less (for a maximum of 50 .
When choosing a crystal, IEEE specifications compliance for Fast Ethernet (10/100 Mb/ s) and Gigabit Ethernet (1000 Mb/s) must be considered. To ensure this, the transmitter reference frequency must be precise within 50 ppm. Intel recommends the use of a transmitter reference frequency that is accurate to within 30 ppm to account for variations in crystal accuracy due to crystal manufacturing tolerance.
47
6.3
6.4
82573/82562—Design Guide
Circuit Board
Since the dielectric layers of the circuit board are allowed some reasonable variation in thickness, the stray capacitance from the printed board (to the crystal circuit) will also vary. If the thickness tolerance for the outer layers of dielectric are controlled within
±17% of nominal value, the circuit board should not cause more than ±2 pF variation to the stray capacitance at the crystal. When tuning crystal frequency, it is recommended that at least three circuit boards are tested for frequency. These boards should differ from production lots of bare circuit boards.
Alternatively, a larger sample population of circuit boards can be used. A larger population increases the probability of obtaining the full range of possible variations in dielectric thickness and the full range of variation in stray capacitance.
Next, the exact same crystal and discrete load capacitors (C1 and C2) must be soldered onto each board, and the LAN reference frequency should be measured on each circuit board.
The circuit board, which has a LAN reference frequency closest to the center of the frequency distribution, should be used while performing the frequency measurements to select the appropriate values for C1 and C2.
Temperature Changes
Temperature changes can cause the crystal frequency to shift. Therefore, frequency measurements should be done in the final system chassis across the system rated operating temperature range.
48
Design Guide—82573/82562
7.0
Table 21.
Design and Layout Checklists
82573 Design Checklist
General
82573
Remarks
Obtain the most recent documentation and specification updates.
Documents are subject to frequent change.
Observe instructions for special pins needing pull-up or pull-down resistors.
Do not connect pull-up or pulldown resistors to any pins marked No Connect, Test, or
Reserved.
Connect PCIe* interface pins to corresponding pins on ICH.
Place AC coupling capacitors
(0.1 µF) near the PCIe* transmitter.
Connect balls G2 PE_CLKn and G1 PE_CLKp to 100 MHz
PCIe* system clock.
Connect PE_RST# to PLTRST# on the ICH.
Connect PE_WAKE# to
PE_WAKE# on the ICH.
Connect ball P5
LAN_PWR_GOOD to
RSMRST# on the ICH.
Connect ball L7 DEVICE_OFF# to SUPER_IO_GP_DISABLE#.
Connect to the reset supervisor for the LAN power well.
Connect to a super I/O pin that retains its value during
PCIe* reset, is driven from the resume well, and defaults to one on power-up.
If not connected to Super I/O pin, then DEVICE_OFF# should be connected with an external pull-up resistor.
Pull down ball D12, PHY_REF, with a 4.99 K 1% resistor.
Pull down ball A13, TEST_EN, with a 3.3 K resistor
Leave ball C3, DOCK_IND, unconnected. This feature is not supported in the 82573.
82573L only: Connect ball
P9, CLKREQ#, to the clock driver responsible for generating the PCIe* clock.
82573L only: This signal can be left unconnected if functionality is not desired; however, functionality must also be disabled in the NVM.
Ensure that ball C6,
AUX_PRESENT (AUX_PWR for the 82573L), is pulled-up to
3.3V standby power supply if the LAN controller is powered from standby supplies. This signal should be pulled down if auxiliary power is not used.
Done Comments
49
82573/82562—Design Guide
Table 21.
(Continued) 82573 Design Checklist
Clock Source
EEPROM and
Flash Memory
Use a 25 MHz 30 ppm accuracy at 25° C clock source. Avoid components that introduce jitter.
Connect two 22 pF load capacitors to the crystal.
Remarks
Parallel resonant crystals are preferred. An oscillator can be used if testability rules require turning off the clock. If an oscillator is used, consider a series termination resistor of
22 to 33 . Avoid PLL clock buffers.
Capacitance affects accuracy of the frequency. It must be matched to crystal specifications, including estimated trace capacitance in calculation.
This applies to EEPROM or
Flash devices.
Use 0.1 µF decoupling capacitor.
Connect WP# and HOLD# signals to VCC through a
3.3 K resistor.
For shared Flash configuration, connect ball
D3, NVM_SHARED, to ground through a 3.3 K resistor.
If SPI Flash is used, connect ball A6, NVM_TYPE, to ground through a 3.3 K resistor.
To disable SPI NVM protection, install a jumper to connect ball A5, NVM_PROT, to ground.
Connect ball B4, NVM_REQ, to
SPI_ARB on the ICH device.
This signal should be unconnected for dedicated
LAN Flash configuration.
Check EEPROM connections to
NVM_CS#, NVM_SK, NVM_SI, and NVM_SO.
This applies to EEPROM or
Flash devices.
If both shared and dedicated configuration options are available, a 0 stuffing option for this signal should be used.
Done Comments
50
Design Guide—82573/82562
Table 21.
(Continued) 82573 Design Checklist
EEPROM and
Flash Memory
(continued)
SMBus
Remarks
For dedicated LAN Flash:
• Connect NVM_CS# to
CS# on the Flash device.
• Connect NVM_SK through a 47 resistor to SCK on the Flash device and through 8.2 K to 10 K resistor to ground.
• Connect NVM_SI through a 47 resistor to SI on the Flash device.
• Connect NVM_SO through a 47 resistor to SO on the Flash device.
For shared LAN Flash:
• Connect NVM_CS# to
CS# on the Flash device.
• Connect NVM_SK through a 47 resistor to SCK on the Flash device and through 8.2 K to 10 K resistor to ground.
• Connect NVM_SI to
ICH_SPI_MOSI and through a 47 resistor to
SI on the Flash device.
• Connect NVM_SO
ICH_SPI_MISO through a
47 resistor to SO on the
Flash device.
If both shared and non-shared options are to be made available, use 0 resistors to minimize the stubs seen on the NVM lines.
The 47 resistors should be placed closest to the outputs.
A value other than 47 can be optimal depending on board characteristics. A simulation should be done if a different value is used.
The 47 resistors should be placed closest to the outputs.
A value other than 47 can be optimal depending on board characteristics. A simulation should be done if a different value is used.
The reference schematics and the ICH7 layout guidelines can be consulted for further details.
82573L only: The SMBus interface is not functional for the 82573L. Please leave it unconnected.
82573L only: If these pins are connected to the SMBus, it will not affect normal operation of the SMBus but the 82573L will not be seen on the bus.
82573E/V only: If SMBus is not used, connect pull-up resistors to SMB_CLK,
SMB_DATA and SMB_ALRT#.
82573E/V only: If SMBus is used, use pull-up resistors on
SMB_DATA, SMB_ALRT# and
SMB_CLK somewhere on the board.
82573E/V only: For ASF and
Intel
®
AMT applications with
SMBus, connect ball N11,
SMB_ALRT#/ASF_PWRGOOD, to the system PWR_GOOD signal or to VCC through a 3.3
K pull-up resistor.
82573E/V only: Connect ball N11 SMB_ALRT#/
ASF_PWRGOOD to SMB_INT for certain management modes.
82573E/V only: 3.3 K pullup resistors are reasonable values.
82573E/V only: SMBus signals are open drain.
82573E/V only: The 3.3V rail, not 3.3V AUX should be used. Alternatively, ball N11 can be configured as an
SMB_ALRT# output.
82573E/V only: The design guide provides further details for management modes.
Done Comments
51
82573/82562—Design Guide
Table 21.
(Continued) 82573 Design Checklist
Transmit and
Receive
Differential Pairs
Magnetics
Module (10/
100/1000BASE-
T Applications)
Discrete
Magnetics
Module/RJ-45
Connector
Option (10/100/
1000BASE-T
Applications)
Remarks
For 10/100/1000BASE-T applications using the 82573E controller, use pairs of 49.9 termination resistors with
0.1µF capacitors attached between center nodes and ground.
This applies to all four differential pairs of each port.
If applicable, use integrated magnetics modules/RJ-45 connectors to minimize space requirements.
Multivendor pin compatibility is possible. The design guide provides further details on recommended models and manufacturers.
Qualify magnetics module carefully for Return Loss,
Insertion Loss, Open Circuit
Inductance, Common Mode
Rejection, and Crosstalk
Isolation.
Magnetics module is critical to passing IEEE PHY conformance tests and EMI test.
Supply 2.5V to the transformer center taps and use 0.1µF bypass capacitors.
2.5V biases the controller's output buffers. Magnetics with four center tap pins can have better characteristics than those with 1 to 2 center tap pins. Capacitors with low ESR should be used.
Bob Smith termination: Use
4 x 75 resistors for cableside center taps and unused pins.
Bob Smith termination: Use an EFT capacitor attached to the termination plane.
Suggested values are
1500 pF/2KV or 1000 pF/3KV.
Connect signal pairs correctly to RJ-45 connector.
This method terminates pairto-pair common mode impedance of the CAT5 cable.
A minimum of 50-mil spacing from capacitor to traces and components should be maintained.
Done Comments
52
Design Guide—82573/82562
Table 21.
(Continued) 82573 Design Checklist
Power Supply and Signal
Ground
Connect external PNP transistors to the regulator control CTRL_12 and CTRL_25 outputs to supply 1.2V and
2.5V, respectively. The connections and transistor parameters are critical.
Pull ball B5, EN2.5REG, up to enable the on-die 2.5V regulator or pulled down to disable the on-die regulator.
Place a 1 1%, 0.5 W resistor at the emitter of the PNP transistor for the 1.2V regulator circuit to drop some of the voltage. Two 2.0 1%,
0.25 W resistors or any combination that yields 1.0 ,
0.5 W may also be used.
Remarks
Alternatively, external regulators are needed to generate these voltages. If the internal voltage regulator control circuit is not used, the
CTRL pins may be left unconnected.
Ensure that there is adequate capacitance on the PNPs.
82573E/V only: Place a 1 resistor in series with a 10 µF ceramic capacitor at the collector of each PNP.
Provide a 3.3V supply. Use auxiliary power supplies.
Design with power supplies that start up properly.
The design should be verified with the reference schematic.
82573L only: Intel recommends using a 20 µF capacitance at the emitter of each PNP for the 82573L.
82573E/V only: Intel recommends using 40 µF of capacitance at the emitter of each PNP.
82573E/V only:
Alternatively, a 10 µF tantalum capacitor can be used in place of the RC combination.
Auxiliary power is necessary to support wake up from powerdown states.
A good guideline is that all voltages should ramp to within their control bands in
20 ms or less. It is desirable that voltages ramp in sequence (3.3V ramps first,
2.5V ramps second, 1.2V ramps last) and that the voltage rise be monotonic.
The minimum rise time on the
3.3V power is 100 µs.
Done Comments
53
82573/82562—Design Guide
Table 21.
(Continued) 82573 Design Checklist
Power Supply and Signal
Ground
(continued)
Chassis Ground
(10/100/
1000BASE-T
Applications)
LED Circuits
Use decoupling and bulk capacitors generously.
Remarks
Use approximately 12 bypass capacitors for the Ethernet silicon. Add approximately
20 µF to 30 µF of bulk capacitance per voltage rail, typically using 10 µF capacitors. If power is distributed on traces, bulk capacitors should be used at both ends. If power is distributed on cards, bulk capacitors should be used at the connector.
If the 1.2V and 2.5V rails are externally supplied (the
82573 has no control), ensure the following connections:
• IREG2.5_IN (balls A2 and
A3) should be tied to the
3.3V rail.
• VCC2.5_OUT (balls B1 and B2) should be connected to the 2.5V rail. Alternatively, it could be left floating.
• CTRL_1.2 (ball P3) should be tied to ground through a 3.3 K resistor.
Alternatively, it could be left floating.
• CTRL_2.5 (ball A4) should be tied to ground through a 3.3 K resistor.
Alternatively, it could be left floating.
• EN2.5REG (ball B5) should be pulled down through a 3.3 K resistor
If possible, provide a separate chassis ground to connect the shroud of the RJ-45 connector and to terminate the line side of the magnetics module.
Place pads for approximately
4 to 6 "stitching" capacitors to bridge the gap from chassis ground to signal ground.
Basic recommendation is a single green LED for activity and a dual (bi-color) LED for speed. Many other configurations are possible.
LEDs are configurable through the NVM.
Pull-down resistors do not need to be exactly 3.3 K; however, they must be greater than 1 K.
This design improves EMI behavior.
Typical values range from
0.1 µF to 4.7 µF. The correct value should be determined through experiment.
Two-LED configuration is compatible with integrated magnetics modules. For the
Link/Activity LED, connect the cathode to the LED1# pin and the anode to VCC. For the bicolor speed LED pair, one end is driven by the LED2# signal.
The other end should be connected to LED0#.
Done Comments
54
Design Guide—82573/82562
Table 21.
Table 22.
(Continued) 82573 Design Checklist
LED Circuits
(continued)
Mfg Test
Connect LEDs to 3.3V as indicated in reference schematics.
Add current limiting resistors to LED paths.
The 82573 controller supports a JTAG Test Access Port.
Remarks
The 3.3V AUX should be used for designs supporting wakeup. Consider adding one to two filtering capacitors per
LED for extremely noisy situations. The suggested starting value is 470 pF.
Typical current limiting resistors are 250 to 330 when using a 3.3V supply.
Current limiting resistors are typically included with integrated magnetics modules.
These signals need to be connected to the ICH if using system level JTAG.
Done
82573 Layout Checklist
General
Ethernet Devices
Remarks
Obtain the most recent documentation and specification updates.
Route the transmit and receive differential traces before routing the digital traces.
Documents are subject to frequent change.
Layout of differential traces is critical.
Place the Ethernet silicon at least 1 inch from the edge of the board.
Place the silicon at least 1 inch from the integrated magnetics module but less than 4 inches.
Place the AC coupling capacitors on the PCIe transmit traces as close as possible to the 82573 but not further than 250 mils.
With closer spacing, fields can follow the surface of the magnetics module or wrap past the edge of board. EMI may increase. Optimum location is approximately 1 inch behind the magnetics module.
The trace length must be under 4 inches from the
Ethernet controller through the magnetics to the RJ-45 connector. Signal attenuation will cause problems for traces longer than 4 inches.
However, due to EMI, the silicon should be placed at least 1 inch away from the magnetics module.
Size 0402, X7R is recommended. The AC coupling capacitors should be placed near the transmitter for PCIe*.
Done
Comments
Comments
55
82573/82562—Design Guide
Table 22.
(Continued) 82573 Layout Checklist
Remarks
Ethernet Devices
(continued)
For the 82573 controller, ensure the trace impedance for the PCIe*differential pairs is 100 +/- 20%.
Match trace lengths between
PCIe pairs to within 3 inches.
Match trace lengths within each PCIe* pair on a segment-by-segment basis.
Match trace lengths within a pair to 5 mils.
Place crystal and load capacitors within 0.75 inches of the Ethernet device.
Clock Source
Non-Volatile
Memory
Transmit and
Receive
Differential Pairs
These traces should be routed differentially.
This reduces EMI.
Match the length of the clock lines to within 200 mils.
Design traces for 100 differential impedance
(± 20%).
Avoid highly resistive traces
(for example, 4 mil traces longer than 4 inches).
A large difference in length between the clock lines leads to clock skew.
Keep clock lines away from other digital traces (especially
RESET signals), I/O ports, board edge, transformers and differential pairs.
Ensure that traces meet the specifications of the design guide (placement is not critical). Refer to the design guide for routing specifications for particular stackups.
Place 47 damping resistors on the NVM lines close to the signal driver. 0.1 inch is recommended. Refer to the design guide for all length requirements.
For both shared and dedicated
NVM configuration options, place 0 resistors to minimize the stubs on the
NVM lines for each option.
This reduces EMI.
EEPROM and Flash can be placed a few inches away from the Ethernet controller to provide better spacing of critical components.
This is a primary requirement for 10/100/1000 Mb/s
Ethernet. Paired 50 traces do not make 100 differential. An impedance calculator can be used to verify this.
If trace length is a problem, thicker board dielectrics should be used to allow wider traces. Thicker copper is better than wider traces.
Done Comments
56
Design Guide—82573/82562
Table 22.
(Continued) 82573 Layout Checklist
Transmit and
Receive
Differential Pairs
(continued)
Magnetics
Module (10/
100/1000BASE-
T Applications)
Make traces symmetrical.
Do not make 90° bends.
Avoid through holes (vias).
Keep traces close together inside a differential pair.
Keep trace-to-trace length difference within each pair to less than 50 mils.
Pair-to-pair trace length does not have to be matched as differences are not critical.
Try to keep differential pairs
50 mils or more away from each other and other traces, including NVM traces and parallel digital traces.
Remarks
Pairs should be matched at pads, vias and turns. Rules for the autorouter should be carefully established.
Asymmetry contributes to impedance mismatch. MDI pairs must not use autoroute.
Corners can be beveled with turns based on 45° angles
If vias are used, the budget is two per trace.
Traces should be kept within
10 mils regardless of trace geometry.
This will minimize signal skew and common mode noise.
Improves long cable performance.
The difference between the length of longest pair and the length of the shortest pair should be kept below
2 inches.
This minimizes crosstalk and noise injection. Pairs may be spaced as close as 30 mils as long as crosstalk isolation is
34 dB or more. Tighter spacing is allowed closer to connections.
Done
Keep traces at least
0.1 inch away from the board edge.
Avoid unused pads and stubs along the traces
Route traces on appropriate layers.
Place termination resistors and capacitors close to the
Ethernet device.
This reduces EMI.
Unused pads and stubs cause impedance discontinuities.
Pairs should be run on different layers as needed to improve routing. Digital signals on adjacent layers must cross at 90° angles.
Splits in power and ground planes must not cross.
This prevents reflections.
Symmetrical pads should be used. Termination components should not be connected to differential pairs with stub traces.
Capacitors connected to center taps should be placed very close (less than 0.1 inch recommended) to integrated magnetics module.
This improves Bit Error Rate
(BER).
Comments
57
82573/82562—Design Guide
Table 22.
(Continued) 82573 Layout Checklist
Power Supply and Signal
Ground
Chassis Ground
(10/100/
1000BASE-T
Applications)
LED Circuits
When using the internal regulator control circuits of the 82573 controller with external PNP transistors, keep the distance from the
CTRL_12 and CTRL_25 output balls to the transistors very short (less 0.5 inches) and use 25 mil (minimum) wide traces.
Use planes if possible.
Remarks
A low inductive loop should be kept from the regulator control pin, through the PNP transistor, and back to the chip from the transistor's collector output. The power pins should connect to the collector of the transistor through a power plane to reduce the inductive path.
This reduces oscillation and ripple in the power supply.
Narrow finger-like planes and very wide traces are allowed.
If traces are used, 100 mils is the minimum.
Done
The 1.2V and 2.5V regulating circuits require 0.5 inch x 0.5 inch thermal relief pads for each PNP.
A 1 , 0.5 W resistor should be placed at the emitter of the
PNP for the 1.2V regulating circuit.
Use decoupling and bulk capacitors generously. The
1.2V and 2.5V rails should have 25 µF of capacitance.
Place these to minimize the inductance from each power pin to the nearest decoupling capacitor.
40 µF is recommended at the emitter (on the 3.3V rail) of each PNP used in the voltage regulating circuit.
If decoupling capacitors are used on the LED lines, place them carefully.
If possible, provide a separate chassis ground "island" to ground the shroud of the RJ-
45 connector and to terminate the line side of the magnetics module. This design improves
EMI behavior.
Place 4 to 6 pairs of pads for
"stitching" capacitors to bridge the gap from chassis ground to signal ground.
Keep LED traces away from sources of noise (for example, high speed digital traces running in parallel).
The pads should be placed on the top layer under the PNP.
This resistor is used for heat dissipation.
Decoupling and bulk capacitors should be placed close to Ethernet device, with some along every side, using short, wide traces and large vias. If power is distributed on traces, bulk capacitors should be used at both ends. If power is distributed on cards, bulk capacitors should be used at the connector.
Capacitors on LED lines should be placed near the
LEDs.
The split in ground plane should be at least 50 mils.
The split should run under the center of magnetics module.
Differential pairs never cross the split.
The exact number and values empirically based on EMI performance must be determined.
LED traces can carry noise into integrated magnetics modules, RJ-45 connectors, or out to the edge of the board, increasing EMI.
Comments
58
Design Guide—82573/82562
Table 23.
82562EX/GX/GZ Design Checklist
Section
General
Ethernet Device
Clock Source
Check Items
Have up-to-date product documentation and spec updates.
Remarks
Documents are subject to frequent change
Observe instructions for special pins needing pull-up or pull-down resistors.
Do not connect pull-up or pulldown resistors to any pins marked No Connect, Test, or
Reserved.
Connect LCI signals to corresponding signals on ICHx device.
Verify LAN disable circuit.
Use a 93C46 EEPROM for nonalerting applications or a
93C66 EEPROM for ASF 1.0.
Place the Ethernet silicon at least one inch from the edge of the Printed Circuit Board
(PCB) and at least one inch from any integrated magnetics module. The trace impedance for the LCI port is
60 .
Place the transmit LCI termination carefully.
See the related 82562 datasheet.
EEPROM for 82562V attaches to ICH. Add decoupling capacitor. EEPROMs should be rated for at least 1 MHz.
With closer spacing, fields can follow the surface of the magnetics module or wrap past the edge of the PCB. EMI can increase. Optimum location is approximately one inch behind the magnetics module.
Place the transmit LCI termination close to the ICH.
Place the receive LCI termination close to the silicon.
Connect RBIAS 10 to ground through a 619 1% resistor.
Connect RBIAS 100 to ground through a 649 1% resistor.
Use 25 MHz 30 ppm accuracy
@ 25° C clock source. Avoid components that introduce jitter.
Parallel resonant crystals are preferred.
Connect two 22 pF load caps to crystal.
Capacitance affects accuracy of the frequency. Must be matched to crystal specs, including estimated trace capacitance in calculation.
Place crystal and load capacitors within 0.75 inches from the Ethernet device.
The Ethernet clock plays a key role in EMI.
Done Comments
59
82573/82562—Design Guide
Table 23.
(Continued) 82562EX/GX/GZ Design Checklist
Section
EEPROM and
FLASH Memory
Check Items
Use decoupling capacitor.
EEPROM ORG ties to 3.3 V for x16 access.
Placement is not critical due to slow signal speeds.
Remarks
Applies to EEPROM or FLASH devices.
For Microwire EEPROMs.
Depends on EEPROM used.
Acceptable to place a few inches away from the
Ethernet controller or ICH to provide better spacing of critical components.
82562V LCI devices use a
110 +/- 1% termination resistor across Tx+/-.
82562V LCI devices use a
110 +/- 1% termination resistor across Rx+/-.
Keep traces away from the
PCB edge.
Avoid unused pads and stubs along the traces.
110 improves transmit return loss.
110 improves receives Bit
Error Rate (BER).
Transmit and
Receive
Differential Pairs
Use short traces.
Avoid highly resistive traces.
For example, avoid four mil traces longer than four inches.
Make traces symmetric.
Do not make 90 degree bends.
Avoid through holes (vias).
Keep traces close together within differential pairs.
Keep trace-to-trace length difference within each pair to less than 50 mils.
Keep differential pairs 50 mils or more away from each other and away from parallel digital traces.
Keep trace length under four inches from the Ethernet controller through the magnetics to the RJ-45 controller.
If trace length is a problem, use thicker PCB dielectrics to allow wider traces. Thicker copper is even better than wider traces.
Try to match the pairs at pads, vias, and turns.
Establish rules carefully for the auto-router. Asymmetry contributes to impedance mismatch.
Bevel corners with turns based on 45 degree angles.
If using through holes (vias), the budget is two per trace.
Keep within 30 mils regardless of trace geometry.
Minimizes signal skew and common mode noise, which reduces radiated EMI.
Improves long cable performance. Less than 30 mils is better; and within 10 mils is best.
Minimizes crosstalk and noise injection. 100 mil spacing is better. Guard traces are generally not recommended and would reduce the impedance if done incorrectly.
Controls EMI.
Use 0 resistors sparingly for dual footprint designs.
Done Comments
60
Design Guide—82573/82562
Table 23.
(Continued) 82562EX/GX/GZ Design Checklist
Section
Transmit and
Receive
Differential Pairs
(continued)
Magnetics
Module
Discrete
Magnetics
Module/RJ-45
Connector
Option
Check Items
Route traces on layers on appropriate layers.
For 82562G family LCI devices, use 5-core model.
Remarks
Run pairs on different layers as needed to improve routing.
Use layers adjacent to ground or power layers if possible.
Make sure digital signals on adjacent layers cross at 90 degree angles.
Place termination resistors
(and capacitors if applicable) close to Ethernet device.
Qualify magnetics module carefully for Return Loss,
Insertion Loss, Open Circuit
Inductance, Common Mode
Rejection, and Crosstalk
Isolation.
Prevents reflections. Use symmetrical pads.
Integrated magnetics modules/RJ-45 connectors are available to minimize space requirements.
Modules with pin compatibility from 10/100 to GbE are available, containing internal jumpers for the unused pairs.
Multi-vendor pin compatibility is possible. Contact manufacturers.
Magnetics module is critical to passing IEEE PHY conformance tests and EMI test.
Auto-transformer models provide better cable termination.
For 82562G family LCI devices, use a 0.1 F capacitor on receive center tap.
Capacitors connected to center taps should be placed very close to Ethernet device.
Improves BER. DO NOT use for MDI-X mode.
For 82562V LCI devices, do not use capacitor on transmit center tap.
Bob Smith termination: use 4 x 75 resistors for cable-side center taps and unused pins.
Bob Smith termination: use an EFT capacitor attached to the termination plane.
Suggested values are
1500 pF/2 KV or 1000 pF/3
KV.
Connect signal pairs correctly to RJ-45 connector.
For severe EMI problems, a capacitor up to 22 pF might be used, but is generally not recommended. Larger values will diminish signal strength and fail IEEE PHY conformance.
Terminates pair-to-pair common mode impedance of the CAT5 cable.
For high-voltage isolation, maintain greater than 70 mil spacing from capacitor to traces and components.
Round all acute metal-fill angles to remove corners.
The differential pairs use pins
1-2 (Transmit in 10/100), 3-6
(Receive in 10/100), 4-5 (GbE only), and 7-8 (GbE only).
Take care not to reverse the polarity.
Done Comments
61
82573/82562—Design Guide
Table 23.
(Continued) 82562EX/GX/GZ Design Checklist
Section
Power Supply and Signal
Ground
Chassis Ground
Termination
Plane
Check Items
For 82562G family devices, provide a 3.3 V supply.
Design with power supplies that start up properly.
Use planes if possible.
Use auxiliary power supplies.
If using decoupling capacitors on LED lines, place them carefully.
Use decoupling and bulk capacitors generously.
Place 4-6 pairs of pads for
"stitching" capacitors to bridge the gap from chassis ground to signal ground.
Remarks
82562G family LCI components are singlevoltage devices.
A good guideline is that all voltages should ramp to within their control bands in
20 ms or less. It is desirable that voltages ramp in sequence and that the voltage rise be monotonic.
Narrow finger-like planes and very wide traces are allowed.
Necessary to have the
Ethernet device wake up from power down states.
Capacitors on LED lines should be placed near the
LEDs.
Place decoupling and bulk capacitors close to the
Ethernet device, with some along every side, using short, wide traces and large vias. If power is distributed on traces, bulk capacitors should be used at both ends. If power is distributed on cards, bulk capacitors should be used at the connector.
For discrete magnetics board designs: If possible, provide a separate chassis ground
"island" to ground the shroud of the RJ-45 connector and to terminate the line side of the magnetics module. This design improves EMI behavior.
Split in ground plane should be at least 50 mils wide. Split should run under center of magnetics module.
Differential pairs never cross the split.
Determine the exact number and values empirically based on EMI performance. Expect to populate approximately two capacitor sites.
For designs with nonintegrated magnetics modules, lay out Bob Smith termination plane. The termination plane floats over chassis ground.
Splits in ground plane should be at least 50 mils to prevent arcing during hi-pot tests.
Done Comments
62
Design Guide—82573/82562
Table 23.
(Continued) 82562EX/GX/GZ Design Checklist
Section
LED Circuits
Mfg Test
Check Items
Basic recommendation is a single green LED for Activity and a dual (bi-color) LED for
Speed. Many other configurations are possible.
Connect LEDs to 3.3 V as indicated in reference schematics.
Keep LED traces away from sources of noise, for example, high speed digital traces running in parallel.
Add current limiting resistors to LED paths.
82562V devices use an XOR
Tree Test Access Port.
Remarks
Two LED configurations are compatible with integrated magnetics modules. For the
Link/Activity LED, connect the anode to the ACTLED# pin and the cathode to the
LILED# pin. For the bi-color speed LED pair, have the
SPDLED# signal drive one end. The other end should be connected to 3.3 V.
Use 3.3 V AUX for designs supporting wakeup. Consider adding filtering capacitors for extremely noisy situations.
Suggested starting value 470 pF.
LED traces can carry noise into integrated magnetics modules, RJ-45 connectors, or out to the edge of the PCB, increasing EMI.
Typical current limiting resistors are 250-330 ohms when using a 3.3 V supply.
Current limiting resistors are typically included with integrated magnetics modules.
See the related 82562 datasheet.
Done Comments
Table 24.
82562EX/GX/GZ Layout Checklist
Section
General
Ethernet
Controller
Check Items
Have up-to-date product documentation and spec updates
Route the transmit and receive differential traces before routing the digital traces.
Layout of differential traces is critical.
Remarks
Documents are subject to frequent change
Place the Ethernet controller at least one inch from the edge of the board (two inches is preferred) and at least one inch from any integrated magnetics module.
With closer spacing, fields can follow the surface of the magnetics module or wrap past edge of board. EMI may increase. Optimum location is approximately one inch behind the magnetics module.
For the 82562GZ(GX) PLC device, the trace impedance for the LCI port is 60
.
Done Comments
63
82573/82562—Design Guide
Table 24.
(Continued) 82562EX/GX/GZ Layout Checklist
Section
Ethernet
Controller
(continued)
Check Items
For the 82562GZ(GX) PLC device, place the transmit LCI termination carefully.
Remarks
For the 82562GZ(GX) PLC device, place the transmit LCI termination close to ICH, and place the receive LCI termination close to the
82562GZ(GX) PLC device.
Clock Source
Place crystal and load capacitors within 0.75 inches from Ethernet controller.
The Ethernet clock plays a key role in EMI.
EEPROM and
FLASH Memory
Transmit and
Receive
Differential Pairs
Placement is not critical due to slow signal speeds.
Design traces for 110
differential impedance (±20%) for the
82562GZ(GX).
Use short traces.
Avoid highly resistive traces, for example, four mil traces longer than four inches.
Make traces symmetrical.
Do not make 90 degree bends.
Avoid through holes (vias).
Keep traces close together within differential pairs.
Keep trace-to-trace length difference within each pair to less than 50 mils.
Keep differential pairs 100 mils (50 mils for the
82562GZ(GX) or more away from each other and away from parallel digital traces.
Okay to place a few inches away from Ethernet controller or ICH to provide better spacing of critical components.
Primary requirement for 10/
100 Mb/s Ethernet. Paired
54.9 traces do not make
110 differential. Check impedance calculator.
Keep trace length under four inches from the Ethernet controller through the magnetics to the RJ-45 connector.
If trace length is a problem, use thicker board dielectrics to allow wider traces. Thicker copper is even better than wider traces.
Try to match the pairs at pads, vias and turns. Establish rules carefully for the autorouter. Asymmetry contributes to impedance mismatch.
Bevel corners with turns based on 45 degree angles.
If using through holes (vias), the budget is two per trace.
Keep within 30 mils regardless of trace geometry.
Minimizes signal skew and common mode noise.
Improves long cable performance.
Minimizes crosstalk and noise injection. 300 mil (100 mil for the 82562GZ(GX) spacing is better. Guard traces are generally not recommended and will reduce the impedance if done incorrectly.
Keep traces away from the board edge.
Controls EMI.
Done Comments
64
Design Guide—82573/82562
Table 24.
(Continued) 82562EX/GX/GZ Layout Checklist
Section
Transmit and
Receive
Differential Pairs
(continued)
Magnetics
Module
Power Supply and Signal
Ground
Check Items
Avoid unused pads and stubs along the traces
Route traces on layers on appropriate layers.
Remarks
Use 0 resistors sparingly for dual footprint designs.
Run pairs on different layers as needed to improve routing.
Use layers adjacent to ground or power layers if possible.
Make sure digital signals on adjacent layers cross at 90 degree angles.
Place termination resistors
(and capacitors if applicable) close to Ethernet controller.
Capacitors connected to center taps should be placed very close to magnetics module.
Prevents reflections. Use symmetrical pads.
Use of power planes is essential for optimized performance of the controller
Use decoupling and bulk capacitors generously.
If using decoupling capacitors on LED lines, place them carefully.
Narrow finger-like planes and very wide traces are not recommended and a continuous plane should be used.
Place decoupling and bulk capacitors close to Ethernet controller, with some along every side, using short, wide traces and large vias. If power is distributed on traces, bulk capacitors should be used at both ends. If power is distributed on cards, bulk capacitors should be used at the connector.
Capacitors on LED lines should be placed near the
LEDs.
Done Comments
65
82573/82562—Design Guide
Table 24.
(Continued) 82562EX/GX/GZ Layout Checklist
Section
Power Supply and Signal
Ground
(continued)
Chassis Ground
Termination
Plane
LED Circuits
Check Items
Bypass the emitter and collector of the external PNP transistors as closely as possible to the body of the transistors.
Remarks
The bypass capacitor at the emitter should be at least 4.7
µF (preferably 10 to 20 µF).
The larger capacitors should be concentrated near the transistor.
Ceramic X5R or X7R type capacitors should be placed as closely as possible to the body of the transistors.
Do not disperse the large capacitors in a large area as this can cause instability to the circuit.
The high frequency bypass capacitors (0.1 µF X7R capacitors) for the controller should be placed as closely as possible to the corresponding balls.
Trace lengths should have around eight mils of width.
If possible, provide a separate chassis ground "island" to ground the shroud of the RJ-
45 connector and to terminate the line side of the magnetics module. This design improves
EMI behavior.
Split in ground plane should be at least 50 mils. Split should run under center of magnetics module.
Differential pairs never cross the split.
Place four to six pairs of pads for "stitching" capacitors to bridge the gap from chassis ground to signal ground.
Keep LED traces away from sources of noise, for example, high speed digital traces running in parallel.
Determine exact number and values empirically based on
EMI performance. For
82562GZ(GX) controllers, expect to populate approximately two capacitor sites.
For designs with nonintegrated magnetics modules, lay out Bob Smith termination plane. Term plane floats over chassis ground.
Splits in ground plane should be at least 50 mils.
LED traces can carry noise into integrated magnetics modules, RJ-45 connectors, or out to the edge of the board, increasing EMI.
Done Comments
66
Design Guide—82573/82562
8.0
Note:
Note:
Table 25.
Bill of Materials
Allowing for both dedicated and shared configurations in the layout will add 12 0 resistors to the bill of materials.
Using the internal 2.5V regulator reduces the bill of materials by one BCP69-19 PNP, three 0.1 µF capacitors, two 10 µF capacitors, and one 4.7 µF capacitor.
Dedicated 82573 NVM
Quantity
4
1
3
1
2
1
1
2
2
6
5
2
21
2
1
2
7
Component
0.1 µF X7R 0402 Capacitor
3.3 K Resistor
22 pF Capacitor
25 MHz, 30 ppm Crystal
0 0603 Resistor
0.1 µF Capacitor
4.7 µF Capacitor
10 µF Capacitor
BCP69-16 PNP
2.0 , 1% Resistor
SPI EEPROM/Flash
10 K Resistor
47 Resistor
4.99 K, 1% Resistor
49.9 K, 1% Resistor
Integrated Magnetics Module
470 pF EMC Capacitor
Notes
PCIe* AC coupling
Pull-up and pull-down
Crystal load
Supplies
Decoupling, MDI
Decoupling
Decoupling
LVR
LVR
NVM
NVM
NVM
PHYREF
MDI
LED
67
82573/82562—Design Guide
Table 26.
Shared 82573 NVM
Quantity
2
2
1
20
6
5
4
1
2
2
1
2
2
5
Component
0.1 µF X7R 0402 Capacitor
3.3 K Resistor
22 pF Capacitor
25 MHz, 30 ppm Crystal
0 0603 Resistor
0.1 µF Capacitor
4.7 µF Capacitor
10 µF Capacitor
BCP69-16 PNP
2.0 , 1% Resistor
4.99 K, 1% Resistor
49.9 K, 1% Resistor
Integrated Magnetics Module
470 pF EMC Capacitor
Notes
PCIe* AC coupling
Pull-up and pull-down
Crystal load
Supplies
Decoupling
Decoupling
Decoupling
LVR
LVR
PHYREF
MDI
LED
68
Design Guide—82573/82562
9.0
Reference Schematics
The following pages show a dual footprint design for the 82573E/82573V/82573L GbE
Controller and the 82562 Platform LAN Connect device.
69
70 us SMB
PCI Express* x1
(LCI) nnect rface Inte
LAN Co
82573/82562—Design Guide
Design Guide—82573/82562
* ss pre ort et P rn Ethe
M RO EP /E NVM s LED
573 82 JTAG e rfac nte ct I ne on LAN C
PCI Ex
Contro t Tes us SMB g rin rma
Mon
The
P Pins SD sta Cry
71
82573/82562—Design Guide
72
s Pin VCC
Pins VSS n tio ge
Regula
Volta
Design Guide—82573/82562
73
74
82573/82562—Design Guide

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Key features
- Dual footprint design
- Gigabit Ethernet support
- 10/100 Mb/s Ethernet support
- Manageability support
- PCI Express* interface
- LAN Connect Interface