AOZ8881 Ultra-Low Capacitance TVS Diode Array General Description

AOZ8881 Ultra-Low Capacitance TVS Diode Array  General Description
AOZ8881
Ultra-Low Capacitance TVS Diode Array
General Description
Features
The AOZ8881 is a transient voltage suppressor array
designed to protect high speed data lines such as HDMI,
MDDI, USB, SATA, and Gigabit Ethernet from damaging
ESD events.
 ESD protection for high-speed data lines:
– IEC 61000-4-2, level 4 (ESD) immunity test
– Air discharge: ±15 kV; Contact discharge: ±15 kV
– IEC61000-4-4 (EFT) 40 A (5/50 nS)
– IEC61000-4-5 (Lightning) 2.5 A (8/20 µS)
– Human Body Model (HBM) ±24 kV
 Array of surge rated diodes with internal TVS diode
This device incorporates four surge rated, low
capacitance steering diodes and a TVS in a single
package. During transient conditions, the steering diodes
direct the transient to either the positive side of the power
supply line or to ground.
 Small package saves board space
 Protects two I/O lines
The AOZ8881 provides a typical line to ground
capacitance of 0.3 pF and low insertion loss up to 6 GHz
providing greater signal integrity making it ideally suited
for HDMI 1.3 applications, such as Digital TVs, DVD
players, set-top boxes and USB applications in mobile
computing devices.
 Low clamping voltage
 Low operating voltage: 5.0 V
Applications
 USB, MDDI, SATA ports
 Monitors and flat panel displays
The AOZ8881 comes in a RoHS compliant and Halogen
Free 1.2 mm x 1.1 mm x 0.55 mm DFN-6 package and is
rated -40 °C to +85 °C junction temperature range.
 Set-top box
 Video graphics cards
 Digital Video Interface (DVI)
 Notebook computers
Typical Application
VBUS
+5V
USB 2.0
Controller
D+
D+
D-
DVBUS
AOZ8881
USB 2.0
Port
GND
Figure 1. USB Port
Rev. 1.0 September 2013
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Page 1 of 8
AOZ8881
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ8881DI-05
-40 °C to +85 °C
DFN-6
Green Product
RoHS Compliant
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
VN
1
6
VP
NC
2
5
CH2
NC
3
4
CH1
DFN-6
(Top Thru View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
Storage Temperature (TS)
-65 °C to +150 °C
ESD Rating per IEC61000-4-2, contact
(1)
±15 kV
ESD Rating per IEC61000-4-2, air(1)
ESD Rating per Human Body Model
±15 kV
(2)
±24 kV
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150 pF, RDischarge = 330 Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100 pF, RDischarge = 1.5 kΩ.
Maximum Operating Ratings
Parameter
Rating
Junction Temperature (TJ)
Rev. 1.0 September 2013
-40 °C to +125 °C
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Page 2 of 8
AOZ8881
Electrical Characteristics
TA = 25°C unless otherwise specified.
Symbol
VRWM
VBR
IR
VCL
Cj
Parameter
Reverse Working Voltage
Conditions
Min.
Typ.
Max.
Units
5.0
V
Between I/O and VN(3)
(4)
Reverse Breakdown Voltage
IT = 1 mA, between I/O and VN
Reverse Leakage Current
VRWM = 5 V, between I/O and VN
6.0
V
1
µA
15
-15
V
V
20
-20
V
V
24
-24
V
V
0.45
pF
(5)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 1 A, tp = 100 ns, any I/O pin to Ground
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5 A, tp = 100 ns, any I/O pin to Ground(5)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 12 A, tp = 100 ns, any I/O pin to Ground(5)
Channel Input Capacitance
VR = 0 V, f = 1 MHz, any I/O pin to Ground
0.30
Notes:
3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
4. VBR is measured at the pulse test current IT.
5. Measurements performed using a 100 ns Transmission Line Pulse (TLP) system.
Rev. 1.0 September 2013
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Page 3 of 8
AOZ8881
Typical Performance Characteristics
Clamping Voltage vs. Peak Pulse Current
Forward Voltage vs. Forward Peak Pulse Current
(tperiod = 100ns, tr = 1ns)
20
15
10
5
20
15
10
0
5
0
0
2
4
6
8
10
Forward Current, IPP (A)
Rev. 1.0 September 2013
(tperiod = 100ns, tr = 1ns)
25
Clamping Voltage, VCL (V)
Forward Voltage (V)
25
12
14
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0
2
4
6
8
10
Peak Puse Current, IPP (A)
12
14
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AOZ8881
Protecting USB Ports from ESD
Because electrostatic discharge (ESD) is common in
electronic systems, a device that provides protection
from the undesirable effects of ESD must be included in
the system design. Designing ESD protection structures
is becoming more and more challenging with the system
bus and I/O operating more often at high-speed data
rates. An Integrated Circuit (IC) connected to external
ports can be damaged by ESD from the operating
environment. The result of ever-shrinking IC process
technology is the decrease of ESD robustness because
of the smaller geometry of the silicon die.
Since USB is a hot insertion and removal system, the
USB components are subjected to ESD and cable
discharge event more frequently. Traditional methods of
ESD protection include metal oxide varistors (MOVs),
and regular CMOS or bipolar clamping diodes. At higher
data rates the parasitic characteristics of those devices
can cause distortion, deterioration and data loss of the
signal integrity. AOZ8881 offers ESD protection for
high-speed data rates and for diode array chips for ease
of design.
The very low 0.6 pF (typical) line capacitance of the
AOZ8881 ensures less distortion of the 480 Mbit/s
USB 2.0 signal; the chips also protect against
electrostatic discharge up to the stringent IEC61000-4-2
level 4, 8 kV (Contact Discharge) and 15kV standard
(Air Discharge). They also provide ultra low matching
capacitance to help improve the signal quality of
differential data lines. Monolithic integration provides
high device reliability, and an optimized pin-out allows
EMI-free board layouts. Figure 2 illustrates the flow
through design of the PCB layout with the AOZ8881
package design. The pinout of the AOZ8881 is designed
to simply drop onto the IO lines of a USB 2.0 design
without having to divert the signal lines that may add
more parasitic inductance. Pins 1, 2, 3 and 4 connected
to the internal TVS devices and ground. Pins 5 and 6 are
no connects. The no connects are in place so the
package can be securely soldered onto the PCB surface.
D+
D+
D-
D-
VP
Ground
Figure 2. Flow-through Layout
Rev. 1.0 September 2013
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Page 5 of 8
AOZ8881
USB 2.0 PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8881 devices should be located as close as possible
to the noise source. The placement of the AOZ8881
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines that
enter the PCB through the I/O connector. Placing the
AOZ8881 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8881 device. Long signal traces
will act as antennas to receive energy from fields that are
Rev. 1.0 September 2013
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize
interconnecting line lengths by placing devices with the
most interconnect as close together as possible. The
protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design.
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AOZ8881
Package Dimensions, DFN-6, 1.2 mm x 1.1 mm x 0.55 mm
D
A
E
c
A1
Pin 1 Dot
by Marking
SIDE VIEW
TOP VIEW
b (6x)
e
L (5x)
1
L1
BOTTOM VIEW
RECOMMENDED LAND PATTERN
Dimensions in millimeters
0.20 (6x)
0.45 (6x)
Symbols
A
A1
b
c
D
E
e
L
L1
1.15
0.25
0.70
0.40
Min.
0.50
0.00
0.15
Nom. Max.
0.55
0.60
—
0.05
0.20
0.25
0.152 Ref.
1.15
1.20
1.25
1.05
1.00
1.10
0.40 BSC
0.30
0.40
0.50
0.375 0.475 0.575
Dimensions in inches
Symbols
A
A1
b
c
D
E
e
L
L1
Min.
0.020
0.000
0.006
Nom. Max.
0.022 0.024
—
0.002
0.008 0.010
0.006 Ref.
0.045 0.047 0.049
0.041 0.043 0.045
0.016 BSC
0.012 0.016 0.020
0.015 0.019 0.023
1.00
UNIT: mm
Note:
1. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Rev. 1.0 September 2013
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Page 7 of 8
AOZ8881
Part Marking
AOZ8881DI-05
(1.2 x 1.1 DFN)
BB3
Product Number Code
Assembly Lot Code
Week Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.0 September 2013
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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