29 LV320

29 LV320
MX29LV320D T/B
MX29LV320D T/B
DATASHEET
P/N:PM1281
REV. 1.2, OCT. 02, 2009
1
MX29LV320D T/B
Contents
FEATURES.............................................................................................................................................................. 5
GENERAL DESCRIPTION...................................................................................................................................... 6
PIN CONFIGURATION............................................................................................................................................ 7
PIN DESCRIPTION.................................................................................................................................................. 8
BLOCK DIAGRAM................................................................................................................................................... 9
BLOCK DIAGRAM DESCRIPTION....................................................................................................................... 10
BLOCK STRUCTURE............................................................................................................................................ 11
Table 1.a: MX29LV320DT SECTOR GROUP ARCHITECTURE................................................................. 11
Table 1.b: MX29LV320DB SECTOR GROUP ARCHITECTURE ................................................................ 13
BUS OPERATION.................................................................................................................................................. 15
Table 2-1. BUS OPERATION....................................................................................................................... 15
Table 2-2. BUS OPERATION....................................................................................................................... 16
FUNCTIONAL OPERATION DESCRIPTION........................................................................................................ 17
READ OPERATION..................................................................................................................................... 17
WRITE OPERATION.................................................................................................................................... 17
DEVICE RESET........................................................................................................................................... 17
STANDBY MODE......................................................................................................................................... 17
OUTPUT DISABLE...................................................................................................................................... 17
BYTE/WORD SELECTION.......................................................................................................................... 18
HARDWARE WRITE PROTECT.................................................................................................................. 18
ACCELERATED PROGRAMMING OPERATION ....................................................................................... 18
TEMPORARY SECTOR GROUP UNPROTECT OPERATION .................................................................. 18
SECTOR GROUP PROTECT OPERATION................................................................................................ 18
CHIP UNPROTECT OPERATION................................................................................................................ 19
AUTOMATIC SELECT BUS OPERATIONS................................................................................................. 19
SECTOR LOCK STATUS VERIFICATION................................................................................................... 19
READ SILICON ID MANUFACTURER CODE............................................................................................. 19
READ SILICON ID MX29LV320DT CODE................................................................................................... 19
READ SILICON ID MX29LV320DB CODE.................................................................................................. 19
READ INDICATOR BIT (Q7) FOR SECURITY SECTOR............................................................................ 20
INHERENT DATA PROTECTION................................................................................................................. 20
COMMAND COMPLETION.......................................................................................................................... 20
LOW VCC WRITE INHIBIT.......................................................................................................................... 20
WRITE PULSE "GLITCH" PROTECTION.................................................................................................... 20
LOGICAL INHIBIT........................................................................................................................................ 20
POWER-UP SEQUENCE............................................................................................................................ 20
POWER-UP WRITE INHIBIT....................................................................................................................... 21
POWER SUPPLY DECOUPLING................................................................................................................ 21
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MX29LV320D T/B
COMMAND OPERATIONS.................................................................................................................................... 22
TABLE 3. MX29LV320D T/B COMMAND DEFINITIONS............................................................................. 22
AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY....................................................................... 23
SECTOR ERASE......................................................................................................................................... 24
CHIP ERASE............................................................................................................................................... 25
SECTOR ERASE SUSPEND....................................................................................................................... 25
SECTOR ERASE RESUME......................................................................................................................... 26
AUTOMATIC SELECT OPERATIONS......................................................................................................... 26
AUTOMATIC SELECT COMMAND SEQUENCE........................................................................................ 26
READ MANUFACTURER ID OR DEVICE ID.............................................................................................. 27
SECURITY SECTOR LOCK STATUS.......................................................................................................... 27
VERIFY SECTOR GROUP PROTECTION.................................................................................................. 27
SECURITY SECTOR FLASH MEMORY REGION...................................................................................... 27
FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY ..... 27
FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY ..... 28
CUSTOMER LOCKABLE: SECURITY SECTOR NOT PROGRAMMED OR PROTECTED AT THE
FACTORY.................................................................................................................................................... 28
ENTER AND EXIT SECURITY SECTOR..................................................................................................... 28
RESET OPERATION................................................................................................................................... 29
COMMON FLASH MEMORY INTERFACE (CFI) MODE...................................................................................... 30
QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE................................ 30
Table 4-1. CFI mode: Identification Data Values.......................................................................................... 30
Table 4-2. CFI Mode: System Interface Data Values................................................................................... 30
Table 4-3. CFI Mode: Device Geometry Data Values................................................................................... 31
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values............................................. 32
ELECTRICAL CHARACTERISTICS..................................................................................................................... 33
ABSOLUTE MAXIMUM STRESS RATINGS................................................................................................ 33
OPERATING TEMPERATURE AND VOLTAGE........................................................................................... 33
DC CHARACTERISTICS............................................................................................................................. 34
SWITCHING TEST CIRCUIT....................................................................................................................... 35
SWITCHING TEST WAVEFORM................................................................................................................ 35
AC CHARACTERISTICS............................................................................................................................. 36
WRITE COMMAND OPERATION.......................................................................................................................... 37
Figure 1. COMMAND WRITE OPERATION................................................................................................. 37
READ/RESET OPERATION.................................................................................................................................. 38
Figure 2. READ TIMING WAVEFORM......................................................................................................... 38
Figure 3. RESET# TIMING WAVEFORM.................................................................................................... 39
ERASE/PROGRAM OPERATION......................................................................................................................... 40
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM....................................................................... 40
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART............................................................. 41
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM................................................................. 42
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART..................................................... 43
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MX29LV320D T/B
Figure 8. ERASE SUSPEND/RESUME FLOWCHART............................................................................... 44
Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORM........................................................................... 45
Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM...................................................................... 45
Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM.................................................................... 46
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART..................................................... 47
SECTOR GROUP PROTECT/CHIP UNPROTECT............................................................................................... 48
Figure 13. SECTOR GROUP PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)................ 48
Figure 14. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv............................................... 49
Figure 15. CHIP UNPROTECT ALGORITHM WITH RESET#=Vhv............................................................. 50
Table 5. TEMPORARY SECTOR GROUP UNPROTECT............................................................................ 51
Figure 16. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORM.................................................. 51
Figure 17. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART................................................ 52
Figure 18. SILICON ID READ TIMING WAVEFORM................................................................................... 53
WRITE OPERATION STATUS............................................................................................................................... 54
Figure 19. DATA# POLLING TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)........................ 54
Figure 20. DATA# POLLING ALGORITHM.................................................................................................. 55
Figure 21. TOGGLE BIT TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)............................. 56
Figure 22. TOGGLE BIT ALGORITHM........................................................................................................ 57
Figure 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to
word mode).................................................................................................................................................. 58
RECOMMENDED OPERATING CONDITIONS..................................................................................................... 59
ERASE AND PROGRAMMING PERFORMANCE................................................................................................ 60
DATA RETENTION................................................................................................................................................ 60
LATCH-UP CHARACTERISTICS.......................................................................................................................... 60
TSOP PIN CAPACITANCE.................................................................................................................................... 60
ORDERING INFORMATION.................................................................................................................................. 61
PART NAME DESCRIPTION................................................................................................................................. 62
PACKAGE INFORMATION.................................................................................................................................... 63
REVISION HISTORY ............................................................................................................................................ 67
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MX29LV320D T/B
32M-BIT [4M x 8 / 2M x 16] 3V SUPPLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Byte/Word switchable
- 4,194,304 x 8 / 2,097,152 x 16
• Sector Structure
- 8K-Byte x 8 and 64K-Byte x 63
• Extra 64K-Byte sector for security
- Features factory locked and identifiable, and customer lockable
• Twenty-Four Sector Groups
- Provides sector group protect function to prevent program or erase operation in the protected sector group
- Provides chip unprotect function to allow code changing
- Provides temporary sector group unprotect function for code changing in previously protected sector groups
• Power Supply Operation
- Vcc 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to 1.5 x Vcc
• Low Vcc write inhibit : Vcc ≤ Vlko
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
• Functional compatible with MX29LV320C T/B device
PERFORMANCE
• High Performance
- Fast access time: 70ns
- Fast program time: 11us/word typical utilizing accelerate function
- Fast erase time: 0.7s/sector, 35s/chip (typical)
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 5uA (typical)
• Typical 100,000 erase/program cycle
• 20 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Provides accelerated program capability
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MX29LV320D T/B
PACKAGE
• 44-Pin SOP
• 48-Pin TSOP
• 48-Ball TFBGA (6 x 8mm)
• 48-Ball LFBGA (6 x 8mm)
• All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
MX29LV320DT/B is a 32Mbit flash memory that can be organized as 4Mbytes of 8 bits each or as 2Mbytes of 16
bits each. These devices operate over a voltage range of 2.7V to 3.6V typically using a 3V power supply input.
The memory array is divided into 64 equal 64 Kilo byte blocks. However, depending on the device being used
as a Top-Boot or Bottom-Boot device, the top or the bottom first block is further subdivided into 8 equal 8Kbyte
blocks. The outermost two sectors at the top or at the bottom are respectively the boot blocks for this device.
This flash memory also provides an additional factory lockable or customer lockable 64Kbyte sector to provide
security feature.
The MX29LV320DT/B is offered in a 44-pin SOP, a 48-pin TSOP and a 48-ball CSP(TFBGA) JEDEC standard
package. These packages are offered in leaded, as well as lead-free versions that are compliant to the RoHS
specifications. The software algorithm used for this device also adheres to the JEDEC standard for single power
supply devices. These flash parts can be programmed in system or on commercially available EPROM/Flash
programmers.
Separate OE# and CE# (Output Enable and Chip Enable) signals are provided to simplify system design. When
used with high speed processors, the 70ns read access time of this flash memory permits operation with minimal
time lost due to system timing delays.
The automatic write algorithm provided on Macronix flash memories perform an automatic erase prior to write.
The user only needs to provide a write command to the command register. The on-chip state machine automatically controls the program and erase functions including all necessary internal timings. Since erase and write
operations take much longer time than read operations, erase/write can be interrupted to perform read operations in other sectors of the device. For this, Erase Suspend operation along with Erase Resume operation are
provided. Data# polling or Toggle bits are used to indicate the end of the erase/write operation.
These devices are manufactured at the Macronix fabrication facility using the time tested and proven Macronix's
advanced technology. This proprietary non-epi process provides a very high degree of latch-up protection for
stresses up to 100 milliamperes on address and data pins from -1V to 1.5xVCC.
With low power consumption and enhanced hardware and software features, this flash memory retains data reliably for at least twenty years. Erase and programming functions have been tested to meet a typical specification
of 100,000 cycles of operation.
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MX29LV320D T/B
PIN CONFIGURATION
44 SOP
WE#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
48 TSOP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
48-Ball TFBGA/LFBGA (6mm x 8mm, Top View, Balls Facing Down)
6
A13
A12
A14
A15
A16
BYTE#
Q15/
A-1
GND
5
A9
A8
A10
A11
Q7
Q14
Q13
Q6
4
WE#
RESET#
NC
A19
Q5
Q12
VCC
Q4
RY/BY#
WP#/
ACC
A18
A20
Q2
Q10
Q11
Q3
A7
A17
A6
A5
Q0
Q8
Q9
Q1
A3
A4
A2
A1
A0
CE#
OE#
GND
B
C
D
E
F
G
H
3
2
1
A
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MX29LV320D T/B
PIN DESCRIPTION
SYMBOL
A0~A20
Q0~Q14
Q15/A-1
CE#
WE#
OE#
BYTE#
RESET#
RY/BY#
Vcc
WP#/ACC
GND
NC
LOGIC SYMBOL
VCC
PIN NAME
Address Input
15 Data Inputs/Outputs
Q15(Data Input/Output, word mode);
A-1(LSB Address Input, byte mode)
Chip Enable Input
Write Enable Input
Output Enable Input
Word/Byte Selection Input
Hardware Reset Pin, Active Low
Ready/Busy Output
3.0 volt-only single power supply
Hardware Write Protect/Acceleration
Pin
Device Ground
Pin Not Connected Internally
21
A0-A20
Q0-Q15
(A-1)
16 or 8
CE#
OE#
WE#
RESET#
RY/BY#
WP#/ACC
BYTE#
Note: If customers do not need WP#/ACC feature,
please connect WP#/ACC pin to VCC or let it floating.
The WP#/ACC has an internal pull-up when
unconnected WP#/ACC is at Vih.
GND
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MX29LV320D T/B
BLOCK DIAGRAM
CE#
OE#
WE#
RESET#
BYTE#
WP#/ACC
CONTROL
INPUT
LOGIC
STATE
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
BUFFER
FLASH
REGISTER
ARRAY
ARRAY
Y-DECODER
AND
STATE
X-DECODER
ADDRESS
A0-AM
WRITE
PROGRAM/ERASE
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
AM: MSB address
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MX29LV320D T/B
BLOCK DIAGRAM DESCRIPTION
The block diagram on Page 9 illustrates a simplified architecture of MX29LV320D T/B. Each block in the block
diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the
memory array..
The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, BYTE#, and WP#/ACC.
It creates internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND
BUFFER" to latch the external address pins A0-AM(A20). The internal addresses are output from this block to
the main array and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", and "FLASH ARRAY". The X-DECODER decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines
of the flash array. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively through the y-pass gates. Sense amplifiers are used to read out the contents of the flash memory, while
the "PGM DATA HV" block is used to selectively deliver high power to bit-lines during programming. The "I/O
BUFFER" controls the input and output on the Q0-Q15/A-1 pads. During read operation, the I/O buffer receives
data from sense amplifiers and drives the output pads accordingly. In the last cycle of program command, the I/O
buffer transmits the data on Q0-Q15/A-1 to "PROGRAM DATA LATCH", which controls the high power drivers in
"PGM DATA HV" to selectively program the bits in a word or byte according to the user input pattern.
The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary
high voltage to the X-DECODER, FLASH ARRAY, and "PGM DATA HV" block. The logic control module comprises of the "WRITE STATE MACHINE (WSM)", "STATE REGISTER", "COMMAND DATA DECODER", and
"COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-A15/A-1
is latched in the command data latch and is decoded by the command data decoder. The state register receives
the command and records the current state of the device. The WSM implements the internal algorithms for program or erase according to the current command state by controlling each block in the block diagram.
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MX29LV320D T/B
BLOCK STRUCTURE
The main flash memory array can be organized as 4M Bytes x 8 or as 2M Words x 16. The details of the address ranges and the corresponding sector addresses are shown in Table 1. Table 1.a shows the sector group
architecture for the Top Boot part, whereas Table 1.b shows the sector group architecture for the Bottom Boot
part. The specific security sector addresses are shown at the bottom off each of these tables.
Table 1.a: MX29LV320DT SECTOR GROUP ARCHITECTURE
Sector
Group
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
Sector Size
Byte Mode Word Mode
(Kbytes)
(Kwords)
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
Address Range
Sector
Sector Address
A20-A12
Byte Mode (x8)
Word Mode (x16)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
000000h-07FFFh
008000h-0FFFFh
010000h-17FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
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MX29LV320D T/B
Sector
Group
9
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
17
18
19
20
21
22
23
24
Sector Size
Byte Mode Word Mode
(Kbytes)
(Kwords)
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
8
4
8
4
8
4
8
4
8
4
8
4
8
4
8
4
Address Range
Sector
Sector Address
A20-A12
Byte Mode (x8)
Word Mode (x16)
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3F1FFFh
3F2000h-3F3FFFh
3F4000h-3F5FFFh
3F6000h-3F7FFFh
3F8000h-3F9FFFh
3FA000h-3FBFFFh
3FC000h-3FDFFFh
3FE000h-3FFFFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1F8FFFh
1F9000h-1F9FFFh
1FA000h-1FAFFFh
1FB000h-1FBFFFh
1FC000h-1FCFFFh
1FD000h-1FDFFFh
1FE000h-1FEFFFh
1FF000h-1FFFFFh
Top Boot Security Sector Addresses
Sector Size
Byte Mode
Word Mode
(Kbytes)
(Kwords)
64
32
Address Range
Sector Address
A20~A12
Byte Mode (x8)
Word Mode (x16)
111111xxx
3F0000h-3FFFFFh
1F8000h-1FFFFFh
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12
MX29LV320D T/B
Table 1.b: MX29LV320DB SECTOR GROUP ARCHITECTURE
Sector
Group
1
2
3
4
5
6
7
8
9
9
9
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
17
17
17
Sector Size
Byte Mode Word Mode
(Kbytes)
(Kwords)
8
4
8
4
8
4
8
4
8
4
8
4
8
4
8
4
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
Address Range
Sector
Sector Address
A20-A12
Byte Mode (x8)
Word Mode (x16)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
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13
MX29LV320D T/B
Sector
Group
17
18
18
18
18
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
23
23
23
24
24
24
24
Sector Size
Byte Mode Word Mode
(Kbytes)
(Kwords)
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
Address Range
Sector
Sector Address
A20-A12
Byte Mode (x8)
Word Mode (x16)
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
Bottom Boot Security Sector Addresses
Sector Size
Byte Mode
Word Mode
(Kbytes)
(Kwords)
64
32
Address Range
Sector Address
A20~A12
Byte Mode (x8)
Word Mode (x16)
000000xxx
000000h-00FFFFh
00000h-07FFFh
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14
MX29LV320D T/B
BUS OPERATION
Table 2-1. BUS OPERATION
Mode Select
Device Reset
Standby Mode
Output Disable
Read Mode
Write (Note1)
Accelerate Program
Temporary SectorGroup Unprotect
RECE#
SET#
L
X
Vcc ± Vcc ±
0.3V 0.3V
H
L
H
L
H
L
H
L
WE#
OE#
Address
Data (I/O)
Q0~Q7
X
X
X
HighZ
Byte#
Vil
Vih
Q8~Q15
HighZ
HighZ
X
X
X
HighZ
HighZ
HighZ
H
H
H
L
L
H
L
H
H
X
AIN
AIN
AIN
HighZ
DOUT
DIN
DIN
HighZ
Q8-Q14=
HighZ
Q15=A-1
HighZ
DOUT
DIN
DIN
L/H
L/H
Note3
Vhv
AIN
DIN
HighZ
DIN
Note3
X
X
L/H
X
X
Note3
Vhv
X
X
X
Sector-Group Protect
(Note2)
Vhv
L
L
H
Chip Unprotect
(Note2)
Vhv
L
L
H
Sector Address,
A6=L, A1=H, DIN, DOUT
A0=L
Sector Address,
A6=H, A1=H, DIN, DOUT
A0=L
WP#/
ACC
L/H
Notes:
1. All sectors will be unprotected if WP#/ACC=Vhv.
2. The two outmost boot sectors are protected if WP#/ACC=Vil.
3. When WP#/ACC = Vih, the protection conditions of the two outmost boot sectors depend on previous
protection conditions."Sector/Sector Block Protection and Unprotection" describes the protect and unprotect
method.
4. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector
protection, or data polling algorithm.
5. In Word Mode (Byte#=Vih), the addresses are AM to A0.
In Byte Mode (Byte#=Vil), the addresses are AM to A-1 (Q15).
6. AM: MSB of address.
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MX29LV320D T/B
Table 2-2. BUS OPERATION
Item
Sector Lock Status
Verification
Read Silicon ID
Manufacturer Code
Read Silicon ID
MX29LV320DT
Read Silicon ID
MX29LV320DB
Read Indicator Bit
(Q7) For Security
Sector
Control Input
AM A11
to to A9
CE# WE# OE#
A12 A10
A8
to
A7
A6
A5
to
A2
A1
A0
Q0~Q7
Q8~Q15
L
H
L
SA
x
Vhv
x
L
x
H
L
01h or 00h
(Note 1)
x
L
H
L
x
x
Vhv
x
L
x
L
L
C2h
x
L
H
L
x
x
Vhv
x
L
x
L
H
A7h
L
H
L
x
x
Vhv
x
L
x
L
H
A8h
L
H
L
x
x
Vhv
x
L
x
H
H
99h or 19h
(Note 2)
22h(Word)
x (Byte)
22h(Word)
x (Byte)
x
Notes:
1. Sector unprotected code:00h. Sector protected code:01h.
2. Factory locked code: 99h. Factory unlocked code: 19h.
3. AM: MSB of address.
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MX29LV320D T/B
FUNCTIONAL OPERATION DESCRIPTION
READ OPERATION
To perform a read operation, the system addresses the desired memory array or status register location by providing its address on the address pins and simultaneously enabling the chip by driving CE# & OE# LOW, and
WE# HIGH. After the Tce and Toa timing requirements have been met, the system can read the contents of the
addressed location by reading the Data (I/O) pins. If either the CE# or OE# is held HIGH, the outputs will remain
tri-stated and no data will appear on the output pins.
WRITE OPERATION
To perform a write operation, the system provides the desired address on the address pins, enables the chip by
asserting CE# LOW, and disables the Data (I/O) pins by holding OE# HIGH. The system then places data to be
written on the Data (I/O) pins and pulses WE# LOW. The device captures the address information on the falling
edge of WE# and the data on the rising edge of WE#. To see an example, please refer to the timing diagram
in Figure 1 on Page 32. The system is not allowed to write invalid commands (commands not defined in this
datasheet) to the device. Writing an invalid command may put the device in an undefined state.
DEVICE RESET
Driving the RESET# pin LOW for a period of Trp or more will return the device to Read mode. If the device is in
the middle of a program or erase operation, the reset operation will take at most a period of Tready1 before the
device returns to Read mode. Until the device does returns to Read mode, the RY/BY# pin will remain Low (Busy
Status).
When the RESET# pin is held at GND±0.3V, the device only consumes standby (Isbr) current. However, the device draws larger current if the RESET# pin is held at a voltage greater than GND+0.3V and less than or equal to
Vil.
It is recommended to tie the system reset signal to the RESET# pin of the flash memory. This allows the device
to be reset with the system and puts it in a state where the system can immediately begin reading boot code
from it.
STANDBY MODE
The device enters Standby mode whenever the RESET# and CE# pins are both held High. While in this mode,
WE# and OE# will be ignored, all Data Output pins will be in a high impedance state, and the device will draw
minimal (Isb) current.
OUTPUT DISABLE
While in active mode (RESET# HIGH and CE# LOW), the OE# pin controls the state of the output pins. If OE# is
held HIGH, all Data (I/O) pins will remain tri-stated. If held LOW, the Byte or Word Data (I/O) pins will drive data.
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MX29LV320D T/B
FUNCTIONAL OPERATION DESCRIPTION (cont'd)
BYTE/WORD SELECTION
The BYTE# input pin is used to select the organization of the array data and how the data is input/output on the
Data (I/O) pins. If the BYTE# pin is held HIGH, Word mode will be selected and all 16 data lines (Q0 to Q15) will
be active.
If BYTE# is forced LOW, Byte mode will be active and only data lines Q0 to Q7 will be active. Data lines Q8 to
Q14 will remain in a high impedance state and Q15 becomes the A-1 address input pin.
HARDWARE WRITE PROTECT
By driving the WP#/ACC pin LOW, the outermost two boot sectors are protected from all erase/program operations. If WP#/ACC is held HIGH (Vih to VCC), these two outermost sectors revert to their previously protected/
unprotected status.
ACCELERATED PROGRAMMING OPERATION
By applying high voltage (Vhv) to the WP#/ACC pin, the device will enter the Accelerated Programming mode.
This mode permits the system to skip the normal command unlock sequences and program byte/word locations
directly. Typically, this mode provides a 30% reduction in overall programming times. During accelerated programming, the current drawn from the WP#/ACC pin is no more than Icp1.
TEMPORARY SECTOR GROUP UNPROTECT OPERATION
The system can apply Vhv to the RESET# pin to place the device in Temporary Unprotect mode. In this mode,
previously protected sectors can be programmed/erased just as though they were unprotected. The device returns to normal operation once Vhv is removed from the RESET# pin and previously protected sectors will once
again be protected.
SECTOR GROUP PROTECT OPERATION
The MX29LV320D T/B provides user programmable protection against program/erase operations for selected
sectors. Most sectors cannot protected individually. Instead, they are bound in groups of four or less called Sector-Groups. Protection is available for individual Sector-Groups, which includes all member sectors. Boot sectors are the exception to this rule as they are assigned unique Sector-Group addresses and can be protected
individually without protecting any adjacent sectors or Sector-Groups. The three sectors adjacent to the boot
sectors form a non-standard Sector-Group. Please refer to Table 1a and Table 1b which show all Sector-Group
assignments.
During the protection operation, the sector address of any sector within a Sector-Group may be used to specify
the Sector-Group being protected.
There are two methods available to protect Sector-Groups. The first and preferred method is activated by applying Vhv on the RESET# pin and following the timing in Figure 13 and the algorithm shown in Figure 14. This is
a command operation that can be performed either on an external programmer or in-circuit by the system controller. The second method is strictly a bus operation and is entered by asserting Vhv on A9 and OE# pins, with
A6 and CE# at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge.
Contact Macronix for more details on this method.
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MX29LV320D T/B
FUNCTIONAL OPERATION DESCRIPTION (cont'd)
CHIP UNPROTECT OPERATION
The Chip Unprotect operation unprotects all sectors within the device. It is standard procedure and highly recommended to protect all Sector-Groups prior using the Chip Unprotect operation. This will prevent possible damage
to the Sector-Group protection logic. All Sector Groups are unprotected when shipped from the factory, so this
operation is only necessary if the user has previously protected any Sector-Groups and wishes to unprotect them
now.
MX29LV320D T/B provides two methods for unprotecting the entire chip. The first and preferred method is entered by applying Vhv on RESET# pin and following the timing diagram in Figure 13 and using the algorithm
shown in Figure 15.
The second method is entered by asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for more
details on this method.
AUTOMATIC SELECT BUS OPERATIONS
The following five bus operations require A9 to be raised to Vhv. Please see AUTOMATIC SELECT COMMAND
SEQUENCE in the COMMAND OPERATIONS section for details of equivalent command operations that do not
require the use of Vhv.
SECTOR LOCK STATUS VERIFICATION
To determine the protected state of any sector using bus operations, the system performs a READ OPERATION
with A9 raised to Vhv, the sector address applied to address pins A20 to A12, address pins A6 & A0 held LOW,
and address pin A1 held HIGH. If data bit Q0 is LOW, the sector is not protected, and if Q0 is HIGH, the sector
is protected.
READ SILICON ID MANUFACTURER CODE
To determine the Silicon ID Manufacturer Code, the system performs a READ OPERATION with A9 raised to
Vhv and address pins A6, A1, & A0 held LOW. The Macronix ID code of C2h should be present on data bits Q0
to Q7.
READ SILICON ID MX29LV320DT CODE
To verify the Silicon ID MX29LV320DT Code, the system performs a READ OPERATION with A9 raised to Vhv,
address pins A6 & A1 held LOW, and address pin A0 held HIGH. The MX29LV320DT code of A7h should be
present on data bits Q0 to Q7. Q15 to Q8 will be tri-stated unless Word mode is selected. In this case, Q15 to
Q8 will output the value 22h.
READ SILICON ID MX29LV320DB CODE
To verify the Silicon ID MX29LV320DB Code, the system performs a READ OPERATION with A9 raised to Vhv,
address pins A6 & A1 held LOW, and address pin A0 held HIGH. The MX29LV320DT code of A8h should be
present on data bits Q0 to Q7. Q15 to Q8 will be tri-stated unless Word mode is selected. In this case, Q15 to
Q8 will output the code 22h.
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19
MX29LV320D T/B
FUNCTIONAL OPERATION DESCRIPTION (cont'd)
READ INDICATOR BIT (Q7) FOR SECURITY SECTOR
To determine if the Security Sector has been locked at the factory, the system performs a READ OPERATION
with A9raised to Vhv, address pin A6 held LOW, and address pins A1 & A0 held HIGH. If the Security Sector
has been locked at the factory, the code 99h will be present on data bits Q0 to Q7. Otherwise, the factory
unlocked code of 19h will be present.
INHERENT DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to Read mode during
power up. Additionally, the following design features protect the device from unintended data corruption.
COMMAND COMPLETION
Only after the successful completion of the specified command sets will the device begin its erase or program
operation. If any command sequence is interrupted or given an invalid command, the device immediately returns
to Read mode.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than Vlko. This prevents data from spuriously
being altered during power-up, power-down, or temporary power interruptions. The device automatically resets
itself when Vcc is lower than Vlko and write cycles are ignored until Vcc is greater than Vlko. The system must
provide proper signals on control pins after Vcc rises above Vlko to avoid unintentional program or erase operations.
WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write
cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at
Vih, WE# a Vih, or OE# at Vil.
POWER-UP SEQUENCE
Upon power up, the MX29LV320D T/B is placed in Read mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences.
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MX29LV320D T/B
FUNCTIONAL OPERATION DESCRIPTION (cont'd)
POWER-UP WRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on
the rising edge of WE#.
POWER SUPPLY DECOUPLING
A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
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21
MX29LV320D T/B
COMMAND OPERATIONS
TABLE 3. MX29LV320D T/B COMMAND DEFINITIONS
Command
Addr
Data
XXX
F0
Automatic Select
Manifacture ID
Device ID
Sector Factory
Byte
AAA
AA
555
55
AAA
90
Word
555
AA
2AA
55
555
90
Byte
AAA
AA
555
55
AAA
90
Word
555
AA
2AA
55
555
90
Byte
AAA
AA
555
55
AAA
90
Addr
X00
X00
X01
X02
X03
X06
Data
C2h
C2h
ID
ID
99/19
99/19
Addr
Data
Addr
Data
Addr
Data
4th Bus
Cycle
Sector Protect
Verify
Word
Byte
555
AAA
AA
AA
2AA
555
55
55
555
AAA
90
90
(Sector) (Sector)
X02
X04
00/01
Enter Security
Sector Region
Enable
Word
Byte
555
AAA
AA
AA
2AA
555
55
55
555
AAA
88
88
00/01
Addr
Data
Addr
Data
Exit Security
Sector
Command
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Reset
Mode
Word
555
AA
2AA
55
555
90
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Read
Mode
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Program
Chip Erase
Sector Erase
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555
AA
2AA
55
555
90
XXX
00
AAA
AA
555
55
AAA
90
XXX
00
555
AA
2AA
55
555
A0
Addr
Data
AAA
AA
555
55
AAA
A0
Addr
Data
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
AAA
AA
555
55
AAA
80
AAA
AA
555
55
AAA
10
555
AAA
AA
AA
2AA
555
55
55
555
AAA
80
80
555
AAA
AA
AA
2AA
555
55
55
Sector Sector
30
30
CFI Read
Word
Byte
55
98
AA
98
Erase
Erase
Suspend Resume
Byte/
Byte/
Word
Word
XXX
XXX
B0
30
Notes:
1. ID 22A7h(Top), 22A8h(Bottom).
2. It is not allowed to adopt any other code which is not in the above command definition table.
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MX29LV320D T/B
COMMAND OPERATIONS (cont'd)
AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY
The MX29LV320D T/B provides the user the ability to program the memory array in Byte mode or Word mode. As
long as the users enters the correct cycle defined in the Table 3 (including 2 unlock cycles and the A0H program
command), any byte or word data provided on the data lines by the system will automatically be programmed
into the array at the specified location.
After the program command sequence has been executed, the internal write state machine (WSM) automatically
executes the algorithms and timings necessary for programming and verification, which includes generating suitable program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do
not pass verification or have low margins. The internal controller protects cells that do pass verification and margin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells
continue to be programmed.
With the internal WSM automatically controlling the programming process, the user only needs to enter the program command and data once.
Programming will only change the bit status from "1" to "0". It is not possible to change the bit status from "0" to
"1" by programming. This can only be done by an erase operation. Furthermore, the internal write verification
only checks and detects errors in cases where a "1" is not successfully programmed to "0".
Any commands written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready1. When the embedded program algorithm
is complete or the program operation is terminated by a hardware reset, the device will return to Read mode.
The typical chip program time at room temperature of the MX29LV320D T/B is less than 36 seconds.
After the embedded program operation has begun, the user can check for completion by reading the following
bits in the status register:
Status
In progress
Finished
Exceed time limit
Q7*1
Q7#
Q7
Q7#
Q6*1
Toggling
Stop toggling
Toggling
Q5
0
0
1
RY/BY# *2
0
1
0
*1: When an attempt is made to program a protected sector, the program operation will abort thus preventing any
data changes in the protected sector. Q7 will output complement data and Q6 will toggle briefly (1us or less) before aborting and returning the device to Read mode.
*2: RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
ERASING THE MEMORY ARRAY
There are two types of erase operations performed on the memory array -- Sector Erase and Chip Erase. In the
Sector Erase operation, one or more selected sectors may be erased simultaneously. In the Chip Erase operation, the complete memory array is erased except for any protected sectors.
P/N:PM1281
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23
MX29LV320D T/B
COMMAND OPERATIONS (cont'd)
SECTOR ERASE
The sector erase operation is used to clear data within a sector by returning all of its memory locations to the
"1" state. It requires six command cycles to initiate the erase operation. The first two cycles are "unlock cycles",
the third is a configuration cycle, the fourth and fifth are also "unlock cycles", and the sixth cycle is the Sector
Erase command. After the sector erase command sequence has been issued, an internal 50us time-out counter
is started. Until this counter reaches zero, additional sector addresses and Sector Erase commands may be issued thus allowing multiple sectors to be selected and erased simultaneously. After the 50us time-out counter
has expired, no new commands will be accepted and the embedded sector erase operation will begin. Note that
the 50us timer-out counter is restarted after every erase command sequence. If the user enters any command
other than Sector Erase or Erase Suspend during the time-out period, the erase operation will abort and the device will return to Read mode.
After the embedded sector erase operation begins, all commands except Erase Suspend will be ignored. The
only way to interrupt the operation is with an Erase Suspend command or with a hardware reset. The hardware
reset will completely abort the operation and return the device to Read mode.
The system can determine the status of the embedded sector erase operation by the following methods:
Status
Time-out period
In progress
Finished
Exceeded time limit
Q7
Q6
Q5
Q3 (note 1)
Q2
0
0
1
0
Toggling
Toggling
Stop toggling
Toggling
0
0
0
1
0
1
1
1
Toggling
Toggling
1
Toggling
RY/BY#
(note 2)
0
0
1
0
Note :
1.The Q3 status bit is the time-out indicator. When Q3=0, the time-out counter has not yet reached zero and
a new Sector Erase command may be issued to specify the address of another sector to be erased. When
Q3=1, the time-out counter has expired and the Sector Erase operation has already begun. Erase Suspend
is the only valid command that may be issued once the embedded erase operation is underway.
2. RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
3. When an attempt is made to erase only protected sector(s), the program operation will abort thus preventing
any data changes in the protected sector(s). Q7 will output its complement data and Q6 will toggle briefly (100us
or less) before aborting and returning the device to Read mode. If unprotected sectors are also specified,
however, they will be erased normally and the protected sector(s) will remain unchanged.
4. Q2 is a localized indicator showing a specified sector is undergoing erase operation or not. Q2 toggles when
user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase
suspend mode). When a sector has been completely erased, Q2 stops toggling at the sector even when the
device is still in erase operation for remaining selected sectors. At that circumstance, Q2 will still toggle when
device is read at any other sector that remains to be erased.
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MX29LV320D T/B
COMMAND OPERATIONS (cont'd)
CHIP ERASE
The Chip Erase operation is used erase all the data within the memory array. All memory cells containing a "0"
will be returned to the erased state of "1". This operation requires 6 write cycles to initiate the action. The first
two cycles are "unlock" cycles, the third is a configuration cycle, the fourth and fifth are also "unlock" cycles, and
the sixth cycle initiates the chip erase operation.
During the chip erase operation, no other software commands will be accepted, but if a hardware reset is received or the working voltage is too low, that chip erase will be terminated. After Chip Erase, the chip will automatically return to Read mode.
The system can determine the status of the embedded chip erase operation by the following methods:
Status
In progress
Finished
Exceed time limit
Q7
0
1
0
Q6
Toggling
Stop toggling
Toggling
Q5
0
0
1
Q2
Toggling
1
Toggling
RY/BY#*1
0
1
0
*1: RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
SECTOR ERASE SUSPEND
After beginning a sector erase operation, Erase Suspend is the only valid command that may be issued. If system issues an Erase Suspend command during the 50us time-out period following a Sector Erase command, the
time-out period will terminate immediately and the device will enter Erase-Suspended Read mode. If the system
issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter
Erase-Suspended Read mode until Tready1 time has elapsed. The system can determine if the device has entered the Erase-Suspended Read mode through Q6, Q7, and RY/BY#.
After the device has entered Erase-Suspended Read mode, the system can read or program any sector(s) except those being erased by the suspended erase operation. Reading any sector being erased or programmed
will return the contents of the status register. Whenever a suspend command is issued, user must issue a resume command and check Q6 toggle bit status, before issue another erase command. The system can use the
status register bits shown in the following table to determine the current state of the device:
Status
Q7
Erase suspend read in erase suspended sector
1
Erase suspend read in non-erase suspended sector
Erase suspend program in non-erase suspended sector
Data
Q7#
Q6
No
toggle
Data
Toggle
Q5
Q3
Q2
RY/BY#
0
N/A
Toggle
1
Data
0
Data
N/A
Data
N/A
1
0
When the device has suspended erasing, user can execute the command sets except sector erase and chip
erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume.
P/N:PM1281
REV. 1.2, OCT. 02, 2009
25
MX29LV320D T/B
COMMAND OPERATIONS (cont'd)
SECTOR ERASE RESUME
The sector Erase Resume command is valid only when the device is in Erase-Suspended Read mode. After
erase resumes, the user can issue another Ease Suspend command, but there should be a 4ms interval between Ease Resume and the next Erase Suspend command. If the user enters an infinite suspend-resume loop,
or suspend-resume exceeds 1024 times, erase times will increase dramatically.
AUTOMATIC SELECT OPERATIONS
When the device is in Read mode, Erase-Suspended Read mode, or CFI mode, the user can issue the
Automatic Select command shown in Table 3 (two unlock cycles followed by the Automatic Select command 90h)
to enter Automatic Select mode. After entering Automatic Select mode, the user can query the Manufacturer ID,
Device ID, Security Sector locked status, or Sector-Group protected status multiple times without issuing a new
Automatic Select command.
While In Automatic Select mode, issuing a Reset command (F0h) will return the device to Read mode (or EaseSuspended Read mode if Erase-Suspend was active).
Another way to enter Automatic Select mode is to use one of the bus operations shown in Table 2-2. BUS
OPERATION. After the high voltage (Vhv) is removed from the A9 pin, the device will automatically return to
Read mode or Erase-Suspended Read mode.
AUTOMATIC SELECT COMMAND SEQUENCE
Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured
silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles.
The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle,
and user can read at any address any number of times without entering another command sequence. The Reset
command is necessary to exit the Automatic Select mode and back to read array. The following table shows the
identification code with corresponding address.
Manufacturer ID
Device ID
Secured Silicon
Sector Protect Verify
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Address (Hex)
X00
X00
X01
X02
X03
X06
(Sector address) X 02
(Sector address) X 04
Data (Hex)
C2
C2
22A7/22A8
A7/A8
99/19
99/19
00/01
00/01
Representation
Top/Bottom Boot Sector
Top/Bottom Boot Sector
Factory locked/unlocked
Factory locked/unlocked
Unprotected/protected
Unprotected/protected
After entering automatic select mode, no other commands are allowed except the reset command.
P/N:PM1281
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MX29LV320D T/B
COMMAND OPERATIONS (cont'd)
READ MANUFACTURER ID OR DEVICE ID
The Manufacturer ID (identification) is a unique hexadecimal number assigned to each manufacturer by the JEDEC committee. Each company has its own manufacturer ID, which is different from the ID of all other companies. The number assigned to Macronix is C2h.
The Device ID is a unique hexadecimal number assigned by the manufacturer for each one of the flash devices
made by that manufacturer.
The above two ID types are stored in a 16-bit register on the flash device -- eight bits for each ID. This register is
normally read by the user or by the programming machine to identify the manufacturer and the specific device.
After entering Automatic Select mode, performing a read operation with A1 & A0 held LOW will cause the device
to output the Manufacturer ID on the Data I/O (Q7 to Q0) pins. Performing a read operation with A1 LOW and A0
HIGH will cause the device to output the Device ID.
SECURITY SECTOR LOCK STATUS
After entering Automatic Select mode, the customer can check the lock status of the Security Sector by performing a read operations with A0 and A1 held HIGH. If the code 99h is read from data pins Q7 to Q0, the sector has
been locked at the factory. If the code 19h is read, the sector has not been locked at the factory.
VERIFY SECTOR GROUP PROTECTION
After entering Automatic Select mode, performing a read operation with A1 held HIGH and A0 held LOW and the
address of the sector to be checked applied to A20 to A12, data bit Q0 will indicate the protected status of the
addressed sector. If Q0 is HIGH, the sector is protected. Conversely, if Q0 is LOW, the sector is unprotected.
SECURITY SECTOR FLASH MEMORY REGION
The Security Sector region is an extra memory space of 64KBytes (32KWords) in length. The Security Sector
can be locked by the factory prior to shipping, or it can be locked by the customer later.
FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY
In a factory locked device, the Security Sector is permanently locked before shipping from the factory. The device will have a 16-byte (8-word) ESN in the security region. In bottom boot devices, the ESN occupies addresses 00000h to 0000Fh in byte mode or 00000h to 00007h in word mode. In top boot devices, the EXN occupies
addresses 3F0000h to 3F000Fh in byte mode or 1F800h to 1F8007h in word mode.
P/N:PM1281
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MX29LV320D T/B
COMMAND OPERATIONS (cont'd)
FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY
In a factory locked device, the Security Sector is permanently locked before shipping from the factory. The device will have a 16-byte (8-word) ESN in the security region. In bottom boot devices, the ESN occupies addresses 00000h to 0000Fh in byte mode or 00000h to 00007h in word mode. In top boot devices, the EXN occupies
addresses 3F0000h to 3F000Fh in byte mode or 1F800h to 1F8007h in word mode.
CUSTOMER LOCKABLE: SECURITY SECTOR NOT PROGRAMMED OR PROTECTED AT THE FACTORY
When the security feature is not required, the Security Sector can provide an extra sector of memory, which can
be read, programmed, and erased with the same endurance limitations specified for normal sectors.
Two methods are available for protecting the Security Sector. Note that once the Security Sector is protected,
there is NO way to unprotect it and its contents can no longer be altered.
The first protection method requires writing the three-cycle Enter Security Region command followed by the use
of the Sector-Group protect algorithm as illustrated in Figure 14-1 with the following exception: the RESET#
pin may be at either Vih or Vhv. Unlike normal Sector-Groups, which do require Vhv on the RESET# pin, the
Security Sector may be permanently locked in-circuit without the use of high voltage.
The second protection method also uses the three-cycle Enter Security Region command, but uses bus
operations that applies Vhv to the A9 and OE# pins with A6, CE#, and WE# held LOW and the SA address
applied to A20 to A12. The protection operation begins at the falling edge of WE# and terminates at the rising
edge. Contact Macronix for more details on using this method.
After the Security Sector is locked and verified, the system must write an Exit Security Sector Region command,
go through a power cycle, or issue a hardware reset to return the device to read normal array mode.
ENTER AND EXIT SECURITY SECTOR
The device allows the user to access the extra 64K-Byte sector identified as the Security Sector, which may contain a random, 128-bits electronic serial number (ESN), or it may contain user data.
To access the Security Sector, the user must issue a three-cycle "Enter Security Sector" command sequence. To
exit the Security Sector and return to normal operation, the user issues the four-cycle "Exit Security Sector" command. Before issuing the "Exit Security Sector" command, please ensure the entering of security sector region.
P/N:PM1281
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28
MX29LV320D T/B
COMMAND OPERATIONS (cont'd)
RESET OPERATION
In the following situations, executing reset command will reset device back to Read mode:
•
•
•
•
•
•
•
•
Among erase command sequence (before the full command set is completed)
Sector erase time-out period
Erase fail (while Q5 is high)
Among program command sequence (before the full command set is completed, erase-suspended program
included)
Program fail (while Q5 is high, and erase-suspended program fail is included)
Read silicon ID mode
Sector protect verify
CFI mode
While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset
device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode,
user must issue reset command to reset device back to read array mode.
When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command.
P/N:PM1281
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29
MX29LV320D T/B
COMMON FLASH MEMORY INTERFACE (CFI) MODE
QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE
MX29LV320D T/B features CFI mode. Host system can retrieve the operating characteristics, structure and
vendor-specified information such as identifying information, memory size, byte/word configuration, operating
voltages and timing information of this device by CFI mode. The device enters the CFI Query mode when the
system writes the CFI Query command, 98H, to address 55h/AAh (depending on Word/Byte mode) any time the
device is ready to read array data. The system can read CFI information at the addresses given in Table 4.
Once user enters CFI query mode, user can not issue any other commands except reset command. The reset
command is required to exit CFI mode and go back to the mode before entering CFI. The system can write the
CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select
mode. The CFI unused area is Macronix's reserved.
Table 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code
Address for alternate algorithm extended query table
Address (h) Address (h)
(Word Mode) (Byte Mode)
10
20
11
22
12
24
13
26
14
28
15
2A
16
2C
17
2E
18
30
19
32
1A
34
Data (h)
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Table 4-2. CFI Mode: System Interface Data Values
Description
Vcc supply minimum program/erase voltage
Vcc supply maximum program/erase voltage
VPP supply minimum program/erase voltage
VPP supply maximum program/erase voltage
Typical timeout per single word/byte write, 2n us
Typical timeout for maximum-size buffer write, 2n us
Typical timeout per individual block erase, 2n ms
Typical timeout for full chip erase, 2n ms
Maximum timeout for word/byte write, 2n times typical
Maximum timeout for buffer write, 2n times typical
Maximum timeout per individual block erase, 2n times typical
Maximum timeout for chip erase, 2n times typical
P/N:PM1281
Address (h) Address (h)
(Word Mode) (Byte Mode)
1B
36
1C
38
1D
3A
1E
3C
1F
3E
20
40
21
42
22
44
23
46
24
48
25
4A
26
4C
Data (h)
0027
0036
0000
0000
0004
0000
000A
0000
0005
0000
0004
0000
REV. 1.2, OCT. 02, 2009
30
MX29LV320D T/B
Table 4-3. CFI Mode: Device Geometry Data Values
Description
Device size = 2n in number of bytes
Flash device interface description (02=asynchronous x8/x16)
Maximum number of bytes in buffer write = 2n (not support)
Number of erase regions within device
Index for Erase Bank Area 1
[2E,2D] = # of same-size sectors in region 1-1
[30, 2F] = sector size in multiples of 256-bytes
Index for Erase Bank Area 2
Index for Erase Bank Area 3
Index for Erase Bank Area 4
P/N:PM1281
Address (h) Address (h)
(Word Mode) (Byte Mode)
27
4E
28
50
29
52
2A
54
2B
56
2C
58
2D
5A
2E
5C
2F
5E
30
60
31
62
32
64
33
66
34
68
35
6A
36
6C
37
6E
38
70
39
72
3A
74
3B
76
3C
78
Data (h)
0016
0002
0000
0000
0000
0002
0007
0000
0020
0000
003E
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0000
REV. 1.2, OCT. 02, 2009
31
MX29LV320D T/B
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Query - Primary extended table, unique ASCII string, PRI
Major version number, ASCII
Minor version number, ASCII
Unlock recognizes address (0= recognize, 1= don't recognize)
Erase suspend (2= to both read and program)
Sector protect (N= # of sectors/group)
Temporary sector unprotect (1=supported)
Sector protect/Chip unprotect scheme
Simultaneous R/W operation (0=not supported)
Burst mode (0=not supported)
Page mode (0=not supported)
Minimum ACC (acceleration) supply (0= not supported), [D7:D4] for
volt, [D3:D0] for 100mV
Maximum ACC (acceleration) supply (0= not supported), [D7:D4] for
volt, [D3:D0] for 100mV
Top/Bottom boot block indicator
02h=bottom boot device 03h=top boot device
P/N:PM1281
Address (h) Address (h)
(Word Mode) (Byte Mode)
40
80
41
82
42
84
43
86
44
88
45
8A
46
8C
47
8E
48
90
49
92
4A
94
4B
96
4C
98
Data (h)
0050
0052
0049
0031
0031
0000
0002
0004
0001
0004
0000
0000
0000
4D
9A
00A5
4E
9C
00B5
4F
9E
0002/0003
REV. 1.2, OCT. 02, 2009
32
MX29LV320D T/B
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM STRESS RATINGS
-65oC to +125oC
-65oC to +150oC
-0.5V to +4.0 V
-0.5V to +10.5 V
-0.5V to Vcc +0.5V
Surrounding Temperature with Bias
Storage Temperature
Voltage Range
VCC
RESET#, A9 and OE#
The other pins
Output Short Circuit Current (less than one second)
200 mA
Note:
1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to Vcc+2V during transition and for less than 20ns during transitions.
OPERATING TEMPERATURE AND VOLTAGE
Commercial (C) Grade
Surrounding Temperature (TA )
Industrial (I) Grade
Surrounding Temperature
VCC Supply Voltages
VCC range
(TA )
0°C to +70°C
-40°C to +85°C
+2.7 V to 3.6 V
P/N:PM1281
REV. 1.2, OCT. 02, 2009
33
MX29LV320D T/B
DC CHARACTERISTICS
Symbol Description
Min.
Typ.
Max.
Remark
Iilk
Input Leak
Iilk9
A9 Leak
Iolk
Output Leak
Icr1
Read Current(5MHz)
10mA
16mA
CE#=Vil, OE#=Vih
Icr2
Read Current(1MHz)
2mA
4mA
Icw
Write Current
15mA
30mA
Isb
Standby Current
5uA
15uA
Isbr
Reset Current
5uA
15uA
CE#=Vil, OE#=Vih
CE#=Vil, OE#=Vih,
WE#=Vil
Vcc=Vcc max,
other pin disable
Vcc=Vccmax,
Reset# enable,
other pin disable
Isbs
Sleep Mode Current
Accelerated Pgm Current, WP#/Acc pin
(Word/Byte)
Accelerated Pgm Current, Vcc pin,
(Word/Byte)
Input Low Voltage
5uA
15uA
5mA
10mA
CE#=Vil, OE#=Vih
15mA
30mA
CE#=Vil, OE#=Vih
Icp1
Icp2
Vil
± 1.0uA
35uA(0~70°C)/
A9=10.5V
45uA(-40~85°C)
± 1.0uA
-0.5V
0.8V
Input High Voltage
Very High Voltage for hardware
Protect/Unprotect/Accelerated
Program/Auto Select/Temporary
Unprotect
Output Low Voltage
0.7xVcc
Vcc+0.3V
9.5V
10.5V
Voh1
Ouput High Voltage
0.85xVcc
Ioh1=-2mA
Voh2
Ouput High Voltage
Vcc-0.4V
Ioh2=-100uA
Vlko
Low Vcc Lock-out Voltage
Vih
Vhv
Vol
0.45V
2.3V
P/N:PM1281
Iol=4.0mA
2.5V
REV. 1.2, OCT. 02, 2009
34
MX29LV320D T/B
SWITCHING TEST CIRCUIT
Vcc
0.1uF
R2
TESTED DEVICE
CL
R1
+3.3V
DIODES=IN3064
OR EQUIVALENT
R1=6.2K ohm
R2=1.6K ohm
Test Condition
Output Load : 1 TTL gate
Output Load Capacitance,CL : 30pF
Rise/Fall Times : 5ns
In/Out reference levels :1.5V
SWITCHING TEST WAVEFORM
3.0V
1.5V
1.5V
Test Points
0.0V
INPUT
OUTPUT
P/N:PM1281
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35
MX29LV320D T/B
AC CHARACTERISTICS
Symbol Description
Min.
Typ.
Max.
Unit
Taa
Valid data output after address
70
ns
Tce
Valid data output after CE# low
70
ns
Toe
Valid data output after OE# low
30
ns
Tdf
Data output floating after OE# high
Output hold time from the earliest rising edge of address, CE#,
OE#
Read period time
30
ns
0
ns
70
ns
Tsrw
Latency Between Read and Write Operation (*Note 1)
45
ns
Twc
Write period time
70
ns
Tcwc
Command write period time
70
ns
Tas
Address setup time
0
ns
Tah
Address hold time
45
ns
Tds
Data setup time
45
ns
Tdh
Data hold time
0
ns
Tvcs
Vcc setup time
200
us
Toh
Trc
Tcs
Chip enable Setup time
0
ns
Tch
Chip enable hold time
0
ns
Toes
Output enable setup time
0
ns
Toeh
Output enable hold time
0
ns
Tws
WE# setup time
0
ns
Twh
WE# hold time
0
ns
Tcep
CE# pulse width
45
ns
Tceph
CE# pulse width high
30
ns
Twp
WE# pulse width
35
ns
Twph
WE# pulse width high
30
ns
Read
Toggle & Data#
Polling
Tbusy Program/Erase active time by RY/BY#
90
ns
Tghwl
Read recover time before write
0
ns
Tghel
Read recover time before write
0
ns
Twhwh1 Program operation
Byte
9
300
us
Twhwh1 Program operation
Word
11
360
us
7
210
us
0.7
2
sec
35
50
us
Twhwh1 Acc program operation (Word/Byte)
Twhwh2 Sector erase operation
Tbal
Sector add hold time
* Note 1: Sampled only, not 100% tested.
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36
MX29LV320D T/B
WRITE COMMAND OPERATION
Figure 1. COMMAND WRITE OPERATION
Tcwc
CE#
Vih
Vil
Tch
Tcs
WE#
Vih
Vil
Toes
OE#
Twph
Twp
Vih
Vil
Addresses
Vih
VA
Vil
Tah
Tas
Tdh
Tds
Data
Vih
Vil
DIN
VA: Valid Address
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REV. 1.2, OCT. 02, 2009
37
MX29LV320D T/B
READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORM
CE#
Tce
Vih
Vil
Tsrw
Vih
WE#
OE#
Vil
Toeh
Tdf
Toe
Vih
Vil
Toh
Taa
Trc
Vih
Addresses
Outputs
ADD Valid
Vil
Voh
HIGH Z
DATA Valid
HIGH Z
Vol
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38
MX29LV320D T/B
AC CHARACTERISTICS
Item
Trp1
Trp2
Trh
Trb1
Trb2
Tready1
Description
RESET# Pulse Width (During Automatic Algorithms)
RESET# Pulse Width (NOT During Automatic Algorithms)
RESET# High Time Before Read
RY/BY# Recovery Time (to CE#, OE# go low)
RY/BY# Recovery Time (to WE# go low)
RESET# PIN Low (During Automatic Algorithms) to Read or Write
RESET# PIN Low (NOT During Automatic Algorithms) to Read or
Tready2
Write
Setup
MIN
MIN
MIN
MIN
MIN
MAX
Speed
10
500
70
0
50
20
Unit
us
ns
ns
ns
ns
us
MAX
500
ns
Figure 3. RESET# TIMING WAVEFORM
Trb1
CE#, OE#
Trb2
WE#
Tready1
RY/BY#
RESET#
Trp1
Reset Timing during Automatic Algorithms
CE#, OE#
Trh
RY/BY#
RESET#
Trp2
Tready2
Reset Timing NOT during Automatic Algorithms
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MX29LV320D T/B
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
CE#
Tch
Twp
WE#
Twph
Tcs
Tghwl
OE#
Last 2 Erase Command Cycle
Twc
Address
2AAh
VA
SA
Tds
Data
Read Status
Tah
Tas
Tdh
55h
VA
In
Progress Complete
10h
Tbusy
Trb
RY/BY#
SA: 555h for chip erase
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40
MX29LV320D T/B
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 80h Address 555h
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 10h Address 555h
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Chip Erase Completed
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MX29LV320D T/B
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Read Status
CE#
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Tbal
Last 2 Erase Command Cycle
Twc
Address
Tas
Sector
Address 0
2AAh
Tds
Data
Tdh
55h
Sector
Address 1
Sector
Address n
Tah
VA
VA
In
Progress Complete
30h
30h
Tbusy
30h
Trb
RY/BY#
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42
MX29LV320D T/B
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 80h Address 555h
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 30h Sector Address
Last Sector
to Erase ?
NO
YES
Data# Polling Algorithm or
Toggle Bit Algorithm
Data=FFh ?
NO
YES
Auto Sector Erase Completed
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43
MX29LV320D T/B
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
ERASE SUSPEND
not toggled
YES
Read Array or
Program
Reading or
Programming End
NO
YES
Write Data 30H
ERASE RESUME
Continue Erase
Another
Erase Suspend ?
NO
YES
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44
MX29LV320D T/B
Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORM
CE#
Tch
Twhwh1
Twp
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Program Command Cycle
555h
Address
VA
PA
Tds
VA
Tdh
A0h
Data
Last 2 Read Status Cycle
Tah
Tas
Status
PD
Tbusy
DOUT
Trb
RY/BY#
Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM
Vhv
(9.5V ~ 10.5V)
WP#/ACC
Vil or Vih
Vil or Vih
250ns
250ns
P/N:PM1281
REV. 1.2, OCT. 02, 2009
45
MX29LV320D T/B
Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM
WE#
Twhwh1 or Twhwh2
Tcep
CE#
Tceph
Tghwl
OE#
Tah
Tas
Address
555h
Tds
Data
VA
PA
VA
Tdh
A0h
Status
PD
DOUT
Tbusy
RY/BY#
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46
MX29LV320D T/B
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
Read Again Data:
Program Data?
No
YES
No
Last Word to be
Programed
YES
Auto Program Completed
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47
MX29LV320D T/B
SECTOR GROUP PROTECT/CHIP UNPROTECT
Figure 13. SECTOR GROUP PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)
150us: Sector Protect
15ms: Chip Unprotect
1us
CE#
WE#
OE#
Verification
Data
60h
SA, A6
A1, A0
60h
40h
VA
VA
Status
VA
Vhv
RESET#
Vih
VA: valid address
P/N:PM1281
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MX29LV320D T/B
Figure 14. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect Mode
No
First CMD=60h?
Yes
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Wait 150us
Reset
PLSCNT=1
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Retry Count +1
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
No
Retry Count=25?
No
Data=01h?
Yes
Yes
Device fail
Protect another
Yes
sector?
No
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
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49
MX29LV320D T/B
Figure 15. CHIP UNPROTECT ALGORITHM WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
No
First CMD=60h?
Yes
All sectors
protected?
No
Protect All Sectors
Yes
Write [A6,A1,A0]:[1,1,0]
data: 60h
Wait 15ms
Write [A6,A1,A0]:[1,1,0]
data: 40h
Retry Count +1
Read [A6,A1,A0]:[1,1,0]
No
Retry Count=1000?
Yes
Device fail
No
Data=00h?
Yes
Last sector
verified?
No
Yes
Temporary Unprotect
RESET#=Vih
Write reset CMD
Chip Unprotect Done
P/N:PM1281
REV. 1.2, OCT. 02, 2009
50
MX29LV320D T/B
Table 5. TEMPORARY SECTOR GROUP UNPROTECT
Parameter
Trpvhh
Tvhhwl
Alt Description
Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET#
Trsp RESET# Vhv to WE# Low
Condition Speed
MIN
500
MIN
4
Unit
ns
us
Figure 16. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORM
Program or Erase Command Sequence
CE#
WE#
Tvhhwl
RY/BY#
Vhv
10V
RESET#
0 or Vih
Vil or Vih
Trpvhh
Trpvhh
P/N:PM1281
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51
MX29LV320D T/B
Figure 17. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
Mode Operation Completed
(1) Remove Vhv Volt from Reset#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Notes:
1. Temporary unprotect all protected sectors Vhv=9.5~10.5V.
2. After leaving temporary unprotect mode, the previously protected sectors are again protected.
P/N:PM1281
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52
MX29LV320D T/B
Figure 18. SILICON ID READ TIMING WAVEFORM
CE#
Vih
Vil
Tce
Vih
WE#
Vil
Toe
Vih
OE#
Tdf
Vil
Toh
Toh
Vhv
Vih
A9
A0
Vil
Vih
Vil
Taa
A1, A6
Taa
Vih
Vil
ADD
DATA
Q0-Q7
Vih
Vil
Vih
Vil
DATA OUT
DATA OUT
C2h
A7h (Top boot)
A8h (Bottom boot)
P/N:PM1281
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53
MX29LV320D T/B
WRITE OPERATION STATUS
Figure 19. DATA# POLLING TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
Address
VA
VA
Taa
Toh
Q7
Complement
Complement
True
Valid Data
Q0-Q6
Status Data
Status Data
True
Valid Data
High Z
High Z
Tbusy
RY/BY#
P/N:PM1281
REV. 1.2, OCT. 02, 2009
54
MX29LV320D T/B
Figure 20. DATA# POLLING ALGORITHM
Start
Read Q7~Q0 at valid address
(Note 1)
Q7 = Data# ?
No
Yes
No
Q5 = 1 ?
Yes
Read Q7~Q0 at valid address
Q7 = Data# ?
(Note 2)
No
Yes
FAIL
Pass
Notes:
1. For programming, valid address means program address.
For erasing, valid address means erase sectors address.
2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
P/N:PM1281
REV. 1.2, OCT. 02, 2009
55
MX29LV320D T/B
Figure 21. TOGGLE BIT TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
Address
VA
VA
VA
VA
Taa
Toh
Q6/Q2
Valid Status
(first read)
Valid Status
Valid Data
(second read)
(stops toggling)
Valid Data
Tbusy
RY/BY#
VA : Valid Address
P/N:PM1281
REV. 1.2, OCT. 02, 2009
56
MX29LV320D T/B
Figure 22. TOGGLE BIT ALGORITHM
Start
Read Q7-Q0 Twice
(Note 1)
NO
Q6 Toggle ?
YES
NO
Q5 = 1?
YES
Read Q7~Q0 Twice
NO
Q6 Toggle ?
YES
Program/Erase fail
Write Reset CMD
Program/Erase Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
P/N:PM1281
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57
MX29LV320D T/B
AC CHARACTERISTICS
WORD/BYTE CONFIGURATION (BYTE#)
Parameter
Telfl/Telfh
Tflqz
Tfhqv
Description
CE# to BYTE# from L/H
BYTE# from L to Output Hiz
BYTE# from H to Output Active
MAX
MAX
MIN
Speed Options
70
5
25
70
Unit
ns
ns
ns
Figure 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to
word mode)
CE#
OE#
Telfh
BYTE#
Q0~Q14
DOUT
(Q0-Q7)
Q15/A-1
VA
DOUT
(Q0-Q14)
DOUT
(Q15)
Tfhqv
P/N:PM1281
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MX29LV320D T/B
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device powerup. If the timing in the figure is ignored, the device may not operate correctly.
Vcc
Vcc(min)
GND
Tvr
Tvcs
Tf
CE#
WE#
Tce
Vil
Vih
Vil
Tf
OE#
WP#/ACC
Tr
Vil
Taa
Vih
Tr or Tf
Valid
Address
Vil
Voh
DATA
Toe
Vih
Tr or Tf
ADDRESS
Tr
Vih
High Z
Valid
Ouput
Vol
Vih
Vil
Figure A. AC Timing at Device Power-Up
Symbol
Tvr
Tr
Tf
Tvcs
Parameter
Vcc Rise Time
Input Signal Rise Time
Input Signal Fall Time
Vcc Setup Time
Min.
20
200
P/N:PM1281
Max.
500000
20
20
Unit
us/V
us/V
us/V
us
REV. 1.2, OCT. 02, 2009
59
MX29LV320D T/B
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Chip Erase Time
Sector Erase Time
Erase/Program Cycles
Chip Programming Time
Accelerated Byte/Word Program Time
Word Program Time
Byte Programming Time
MIN.
Byte Mode
Word Mode
LIMITS
TYP.
35
0.7
100,000
36
24
7
11
9
MAX.
50
2
108
72
210
360
300
UNITS
sec
sec
Cycles
sec
sec
us
us
us
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC. Programming specifications assume checkboard data pattern.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and
including 100,000 program/erase cycles.
3. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.
DATA RETENTION
PARAMETER
Condition
Min.
Data retention
55˚C
20
Max.
UNIT
years
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
-1.0V
-100mA
Input voltage difference with GND on all pins except I/O pins
Input voltage difference with GND on all I/O pins
Vcc Current
All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing
MAX.
10.5V
1.5 x Vcc
+100mA
TSOP PIN CAPACITANCE
Parameter Symbol
CIN2
COUT
CIN
Parameter Description
Control Pin Capacitance
Output Capacitance
Input Capacitance
Test Set
VIN=0
VOUT=0
VIN=0
P/N:PM1281
TYP
7.5
8.5
6
MAX
9
12
7.5
UNIT
pF
pF
pF
REV. 1.2, OCT. 02, 2009
60
MX29LV320D T/B
ORDERING INFORMATION
PART NO.
MX29LV320DTMC-70G
MX29LV320DBMC-70G
MX29LV320DTTI-70G
MX29LV320DBTI-70G
MX29LV320DTXBI-70G
MX29LV320DBXBI-70G
MX29LV320DTXEI-70G
MX29LV320DBXEI-70G
ACCESS TIME
(ns)
70
70
70
70
70
70
70
70
Ball Pitch/
Ball Size
0.8mm/0.3mm
0.8mm/0.3mm
0.8mm/0.4mm
0.8mm/0.4mm
PACKAGE
Remark
44 Pin SOP
44 Pin SOP
48 Pin TSOP
48 Pin TSOP
48-Ball TFBGA
48-Ball TFBGA
48-Ball LFBGA
48-Ball LFBGA
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
* 44-pin SOP is only for Pachinko Socket
P/N:PM1281
REV. 1.2, OCT. 02, 2009
61
MX29LV320D T/B
PART NAME DESCRIPTION
MX 29
LV 320 D T T I
70 G
OPTION:
G: Pb-free package
SPEED:
70: 70ns
TEMPERATURE RANGE:
C: Commercial (0°C to 70°C)
I: Industrial (-40°C to 85°C)
PACKAGE:
M: SOP
T: TSOP
XB: TFBGA (0.8mm ball pitch, 0.3mm ball size)
XE: LFBGA (0.8mm ball pitch, 0.4mm ball size)
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
REVISION:
D
DENSITY & MODE:
320: 32Mb, x8/x16 Boot Block
TYPE:
LV: 3V
DEVICE:
29:Flash
P/N:PM1281
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62
MX29LV320D T/B
PACKAGE INFORMATION
P/N:PM1281
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MX29LV320D T/B
P/N:PM1281
REV. 1.2, OCT. 02, 2009
64
MX29LV320D T/B
48-Ball TFBGA (for MX29LV320D TXBI/BXBI)
P/N:PM1281
REV. 1.2, OCT. 02, 2009
65
MX29LV320D T/B
48-Ball LFBGA (for MX29LV320D TXEI/BXEI)
P/N:PM1281
REV. 1.2, OCT. 02, 2009
66
MX29LV320D T/B
REVISION HISTORY
Revision No. Description
1.0
1. Removed "Preliminary"
1.1
1. Added Tsrw (AC/WAVEFORM)
2. Added pin description note for WP#/ACC pin
3. Added 20 years data retention condition
4. Revised Figure 19. data# polling timing waveform
1.2
1. Modified SA44/SA45 address
Page
P5
P36,38
P8
P5-6, 60
P54
P12
Date
AUG/14/2008
MAY/18/2009
OCT/02/2009
P/N:PM1281
REV. 1.2, OCT. 02, 2009
67
MX29LV320D T/B
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substantial
harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or
damages that may be incurred due to use of Macronix's products in the prohibited applications.
Copyright© Macronix International Co., Ltd. 2006~2009. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX
Logo, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands of other
companies are for identification purposes only and may be claimed as the property of the respective companies.
MACRONIX INTERNATIONAL CO., LTD.
Macronix Offices : Japan
Macronix Asia Limited.
Macronix Offices : Taiwan
Headquarters, FAB2
Macronix, International Co., Ltd.
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Taipei Office
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#906, 9F, Kangnam Bldg., 1321-4, Seocho-Dong, Seocho-Ku,
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Tel: +65-6346-5505
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Macronix (Hong Kong) Co., Limited,
SuZhou Office
Macronix Europe N.V.
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Macronix Offices : USA
Macronix (Hong Kong) Co., Limited,
Shenzhen Office
Macronix Asia Limited.
Macronix Offices : Singapore
Macronix Pte. Ltd.
1 Marine Parade Central, #11-03 Parkway Centre,
Macronix (Hong Kong) Co., Limited.
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Kawasaki-ku Kawasaki-shi,
Kanagawa Pref. 210-0005, Japan
Tel: +81-44-246-9100
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Room 1401 & 1404, Block A, TianAN Hi-Tech PLAZA Tower,
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Tel: +1-408-262-8887
Fax: +1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
68
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