datasheet for PUMA68SV16000AB by Apta Group

datasheet for PUMA68SV16000AB by Apta Group
512K x 32 SRAM MEMORY
PUMA 68SV16000B-020/025/35
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Issue 2.0 : May 2001
Description
Features
The PUMA 68SV16000B/AB is a 16Mbit CMOS High
• Very Fast Access Times of 20, 25, 35 ns.
Speed Static RAM organised as 512K x 32 in a
• JEDEC 68 'J' leaded plastic Surface Mount
Substrate.
JEDEC 68 pin surface mount PLCC, available with
access times of 20, 25, and 35ns. The output width
is user configurable as 8 , 16 or 32 bits using four
Chip Selects (CS1~4). The plastic device is
screened to ensure high reliability.
The device features multiple ground pins for maximum noise immunity and TTL compatible inputs
and outputs. The PUMA 68SV16000 offers a dramatic
space saving advantage over four standard 512Kx8
devices.
• Commercial, Industrial, or Military Grade.
• User Configurable as 8 / 16 / 32 bit wide output.
• Operating Power :
• Standby Power : CMOS
2.30 W (max)
144 mW (max)
• TTL Compatible Inputs and Outputs.
• Fully Static operation.
• Multiple ground pins for maximum noise
immunity.
• Single 3.3V±0.3V Power supply.
• Pin compatible with 4M Modules.
Block Diagram (Alternative - Page 7 )
OE
WE
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
512K x 8
SRAM
VCC
A9
A10
A7
1 68 67 66 65 64 63 62 61
A8
2
A6
3
WE
4
CS4
5
CS3
6
GND
A3
7
A4
A2
8
A5
A0
9
A1
A0~A18
NC
Pin Definition (Alternative - Page 7 )
D0
10
60
D16
D1
11
59
D17
D2
12
58
D18
D3
13
57
D19
D4
14
56
D20
D5
15
D21
D6
16
PUMA 68SV16000
55
54
D22
D7
17
D23
GND
VIEW
53
18
52
GND
D8
19
51
D24
D9
20
50
D25
D10
21
D11
FROM
ABOVE
49
D26
22
48
D27
D12
23
47
D28
D13
24
46
D29
D14
25
45
D30
D15
26
44
D31
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+3.3V)
Ground
NC
A18
GND
NC
NC
NC
A17
CS2
OE
CS1
A16
A13
A14
A15
A12
Pin Functions
A11
VCC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A0 - A18
D0 - D31
CS1~4
WE
Package Details
OE
NC
VCC
GND
Plastic 68 J-Leaded JEDEC PLCC
PUMA 68SV16000 - 020/025/35
Issue 2.0 : May 2001
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Parameter
Symbol
(2)
T
Voltage on any pin relative to VSS
Power Dissipation
Storage Temperature
V
PT
TSTG
Min
Typ
Max
Unit
-0.5
-65
-
4.6
1.0
150
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
(Commercial)
(Industrial)
(Military)
Symbol
Min
Typ
Max
VCC
VIH
VIL
TA
TAI
TAM
3.0
2.2
-0.3
0
-40
-55
3.3
-
3.6
VCC+0.3
0.8
70
85
125
Unit
V
V
V
o
C
o
C (Suffix I)
o
C (Suffix M)
DC Electrical Characteristics (VCC=3.3V±10%, TA = -55oC to +125oC)
Parameter
I/P Leakage Current
Symbol Test Condition
max
Unit
ILI
0V < VIN < VCC
-8
-
8
µA
ILO
CS = VIH, VI/O = GND to VCC
-8
-
8
µA
32-bit mode
ICC32
Min. Cycle, CS = VIL, f=fMAX, IOUT = 0mA
-
-
640
mA
16-bit mode
ICC16
As Above.
-
-
420
mA
8-bit mode
ICC8
As Above.
-
-
310
mA
TTL levels
ISB1
CS = VIH, f=fMAX
-
-
200
mA
CMOS levels
ISB2
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V, f=0
-
-
40
mA
VOL
IOL = 8.0mA
-
-
0.4
V
VOH
IOH = -4.0mA
2.4
-
-
V
Address,OE,WE
Output Leakage Current
Operating Supply Current
Min Typ
Standby Supply Current
Output Voltage
Notes :
1/ Typical values are at VCC=3.3V,TA=25oC and specified loading.
2/ CS above refers to CS1~4.
3/ At f=fMAX address and data inputs are cycling at maximum frequency.
2
PUMA 68SV16000 - 020/025/35
Issue 2.0 : May 2001
Capacitance (VCC=3.3V±10%,TA=25oC)
Note: Capacitance calculated, not measured.
Parameter
Symbol Test Condition
Input Capacitance (Address,OE,WE)
I/P Capacitance (other)
I/O Capacitance
CIN1
CIN2
CI/O
VIN = 0V
VIN = 0V
VI/O = 0V
AC Test Conditions
max
Unit
35
10
30
pF
pF
pF
Output Load
I/O Pin
* Input pulse levels: 0V to 3.0V
645Ω
* Input rise and fall times: 3ns
1.76V
* Input and Output timing reference levels: 1.5V
100pF
* Output load: see diagram
* VCC=3.3V±10%
Operation Truth Table
CS
OE
WE
DATA PINS
SUPPLY CURRENT
MODE
H
X
X
High Impedance
ISB1 , ISB2
Standby
L
L
H
Data Out
ICC32 , ICC16 , ICC8
Read
L
H
L
Data In
ICC32 , ICC16 , ICC8
Write
L
L
L
Data In
ICC32 , ICC16 , ICC8
Write
L
H
H
High-Impedance
ISB1 , ISB2
High-Z
CS above refers to CS1~4.
Notes : H = VIH : L =VIL : X = VIH or VIL
3
PUMA 68SV16000 - 020/025/35
Issue 2.0 : May 2001
AC OPERATING CONDITIONS
Read Cycle
-020
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
-025
-35
Symbol
min
max
min
max
min
max
Unit
t RC
tAA
tACS
tOE
t OH
tCLZ
tOLZ
t CHZ
t OHZ
20
3
3
0
0
0
20
20
9
9
9
25
3
3
0
0
0
25
25
11
11
11
35
3
3
0
0
0
35
35
14
14
14
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-020
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
Symbol
t WC
t CW
t AW
tAS
t WP
t WR
t WHZ
t DW
t DH
t OW
-025
-35
min
max
min
max
min
max
Unit
20
14
14
0
14
0
0
10
0
3
9
-
25
16
16
0
16
0
0
12
0
3
11
-
35
25
25
0
25
0
0
12
0
5
12
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
PUMA 68SV16000 - 020/025/35
Issue 2.0 : May 2001
Read Cycle Timing Waveform (1,2)
t RC
Address
t AA
OE
t OE
t OH
t OLZ
CS1~4
t ACS
Don't
care.
t OHZ (3)
t CLZ (4,5)
Dout
Data Valid
t CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
t WR(7)
OE
t AS(6)
t AW
t CW
CS1~4
Don't
Care
WE
t OHZ(3,9)
t OW
t WP(2)
High-Z
Dout
t DW
Din
High-Z
t DH
Data Valid
5
(8)
PUMA 68SV16000 - 020/025/35
Issue 2.0 : May 2001
Write Cycle No.2 Timing Waveform (1,5)
tWC
Address
t AS(6)
t WR(7)
t CW
CS1~4
t AW
t WP(2)
WE
tOH
t WHZ(3,9)
t OW
High-Z
Dout
t DW
Din
(8)
(4)
Don't
Care
t DH
High-Z
Data Valid
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS1~4 and WE low.
(3) If OE, CS1~4, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS1~4 and WE low, too avoid inadvertant writes.
(7) CS1~4 or WE must be high during address transitions.
(8) When CS1~4 are low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
6
PUMA 68SV16000 - 020/025/35
Issue 2.0 : May 2001
Vcc
A10
A8
A9
A7
CS4
WE1
A6
GND
A5
CS3
A4
A3
A2
NC
A0
A1
Version 'A' Pin Definition
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
D0
D1
10
60
D16
11
59
D17
D2
D3
12
13
58
57
D18
D4
D5
14
56
D20
15
55
D21
D6
D7
GND
16
VIEW
54
FROM
53
D22
D23
52
GND
D8
D9
19
51
D24
20
50
D25
D10
D11
21
49
22
48
D26
D27
D12
23
47
D28
D13
D14
24
46
25
45
D29
D30
D15
26
44
D31
17
18
ABOVE
D19
NC
GND
A18
WE3
WE4
A17
WE2
OE
CS2
CS1
A16
A15
A14
A13
A12
Vcc
A11
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Version A Block Diagram
A0~A18
OE
WE4
WE3
WE2
WE1
512K x 8
SRAM
512K x 8
SRAM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
7
512K x 8
512K x 8
SRAM
SRAM
PUMA 68SV16000 - 020/025/35
Package Information
Issue 2.0 : May 2001
Dimensions in mm(inches)
25.27 (0.995)
25.02 (0.985)
Pin 68
Pin 1
XXXXXX-X
5.08
(0.200)
max
0.46
(0.018)
1.27
(0.050)
0.90
(0.035)
typ
23.11 (0.910)
24.13 (0.950)
Ordering Information
Notes:
1. All dimensions in mm (inches).
PUMA68SV16000ABM-025
Access Time
020 = 20ns
025 = 25ns
35
Temperature
= 35ns
Blank = Commercial
I
= Industrial
M
= Military
Construction
B
Pinout
Blank = 1 x /WE
A
Organisation
= CSP Based
= 4 x /WE
16000 = 16MBit, configurable
512Kx32, 1M x 16, 2M x 8
Voltage
SV = 3.3V +/-10%
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for aparticular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director.
8
PUMA 68SV16000 - 020/025/35
Issue 2.0 : May 2001
Customer Guidelines
Visual Inspection Standard
All devices inspected to ANSI 2 standard
Moisture Sensitivity
Devices are moisture sensitive.
Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH).
After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent
processing (peak package body temp 220OC) must be :
A : Mounted within 72 Hours at factory conditions of <30OC/60% RH
OR
B : Stored at <20% RH
If these conditions are not met or indicator card is >20% when read at 23OC +/-5% devices require baking as
specified below.
If baking is required, devices may be baked for :A : 24 hours at 125OC +/-5% for high temperature device containers
OR
B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers.
Packaging Standard
Devices packaged in dry nitrogen, JED-STD-020.
Packaged in trays as standard.
Tape and reel available for shipment quantities exceeding 200pcs upon request.
Soldering Recomendations
IR/Convection -
Ramp Rate
Temp. exceeding 183OC
Peak Temperature
Time within 5OC of peak
Ramp down
6OC/sec max.
150 secs. max.
225OC
20 secs max.
6OC/sec max.
Vapour Phase -
Ramp up rate
Peak Temperature
Time within 5OC of peak
Ramp down
6OC/sec max.
215 - 219OC
60 secs max.
6OC/sec max.
Note : The above recomendations are based on standard industry practice.
Failiure to comply with the above recomendations invalidates product warranty.
9
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