datasheet for VL47B1G63A

datasheet for VL47B1G63A

Product Specifications

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

General Information

8GB 1Gx64 DDR3 SDRAM NON-ECC UNBUFFERED SODIMM 204-PIN

Description

The VL47B1G63A is a 1Gx64 DDR3 SDRAM high density SODIMM. This memory module is dual rank, consists of sixteen CMOS 512Mx8 bits with 8 banks DDR3 Synchronous DRAMs in BGA packages and a 2K EEPROM in an 8pin MLF package. This module is a 204-pin small-outline dual in-line memory module and is intended for mounting into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR3

SDRAM.

Features

 204-pin, small-outline dual in-line memory module (SODIMM)

 Fast data transfer rates: PC3-12800, PC3-10600,

PC3-8500, PC3-6400

 VDD = VDDQ = 1.5V +/-0.075V

 JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 compatible )

 VDDSPD = 3.0V to 3.6V

 Eight internal component banks for concurrent operation

 8-bit pre-fetch architecture

 Bi-directional differential data-strobe

 Nominal and dynamic on-die termination (ODT)

 ZQ calibration support

 Programmable CAS# latency: 11(DDR3-1600), 9 (DDR3-1333),

7 (DDR3-1066), 6 (DDR3-800)

 Programmable burst; length (8)

 Average refresh period 7.8 us

 Asynchronous reset

 Fly-by topology

 On board terminated command, address, and control bus

 Serial presence detect (SPD) with EEPROM

 Gold edge contacts

 Lead-free, RoHS compliant

 PCB: Height 30.00mm (1.181”), double sided components

Order Information:

VL47B1G63A K0 S

X

DRAM DIE (Option)

DRAM MANUFACTURER

S - SAMSUNG

MODULE SPEED

K0: PC3-12800 @ CL11

K9: PC3-10600 @ CL9

F8: PC3-8500 @ CL7

E7: PC3-6400 @ CL6

VL: Lead-free/RoHS

Pin Description

Pin Name

A0~A15

A10/AP

A12/BC#

BA0~BA2

DQ0~DQ63

DQS0~DQS7

DQS0#~DQS7#

DM0~DM7

CK0, CK0#, CK1, CK1#

ODT0, ODT1

CKE0, CKE1

CS0#, CS1#

RAS#

CAS#

WE#

RESET#

VDD

VSS

SA0~SA1

SDA

SCL

VREFCA

VREFDQ

VDDSPD

VTT

NC

Function

Address Inputs

Address Input/ Autoprecharge

Address Input/ Burst Chop

Bank Address Inputs

Data Input/Output

Data Strobes

Data Strobes Complement

Data Masks

Clock Input

On-die Termination Control

Clock Enables

Chip Selects

Row Address Strobes

Column Address Strobes

Write Enable

Register and SDRAM Control

Voltage Supply

Ground

SPD Address

SPD Data Input/Output

SPD Clock Input

Reference Voltage for CA

Reference Voltage for DQ

SPD Voltage Supply

Termination Voltage

No Connect

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Product Specifications

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

Pin Configuration

204-PIN DDR3 SODIMM FRONT 204-PIN DDR3 SODIMM BACK

Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name

1 VREFDQ 53 DQ19 105 VDD 157 DQ42 2 VSS 54 VSS 106 VDD 158 DQ46

9

11

13

15

17

3

5

7

VSS

DQ0

DQ1

VSS

DM0

VSS

DQ2

DQ3

55 VSS 107 A10 159

57 DQ24 109 BA0 161

59 DQ25 111 VDD 163

DQ43

VSS

DQ48

61 VSS 113 WE# 165

63 DM3 115 CAS# 167

DQ49

VSS

65 VSS 117 VDD 169 DQS6#

67 DQ26 119 A13 171 DQS6

69 DQ27 121 CS1# 173 VSS

29

31

33

35

37

19

21

23

25

VSS

DQ8

DQ9

VSS

71

73

75

77

VSS

CKE0 125

VDD

NC

123

127

129

VDD

NC

VSS

DQ32

175

177

179

181

27 DQS1# 79 BA2 131 DQ33 183

DQS1

VSS

DQ10

DQ11

VSS

81

83

85

87

89

VDD

A12

A9

VDD

A8

133

135 DQS4# 187

137

139

141

VSS

DQS4

VSS

DQ34

185

189

191

193

VSS

DM7

VSS

DQ58

DQ59

DQ50

DQ51

VSS

DQ56

DQ57

39

41

DQ16

DQ17

91 A5 143 DQ35 195

93 VDD 145 VSS 197

43 VSS 95

45 DQS2# 97

47 DQS2

A3

A1

147

149

DQ40

DQ41

VSS

SA0

199 VDDSPD

201

99 VDD 151 VSS 203

SA1

VTT

49

51

VSS 101 CK0 153 DM5

DQ18 103 CK0# 155 VSS

*: These pins are not used in this module.

4

6

8

DQ4

DQ5

VSS

56 DQ28 108 BA1 160 DQ47

58 DQ29 110 RAS# 162 VSS

60 VSS 112 VDD 164 DQ52

10 DQS0# 62 DQS3# 114 CS0#

12 DQS0 64 DQS3 116 ODT0

166

168

DQ53

VSS

14

16

18

VSS

DQ6

DQ7

66

68

70

VSS

DQ30

DQ31

118

120

122

VDD

ODT1

NC

170

172

174

DM6

VSS

DQ54

20

22

24

26

28

VSS

DQ12

DQ13

VSS

DM1

30 RESET# 82

32 VSS 84

34

36

38

DQ14

DQ15

VSS

86

88

90

72 VSS 124 VDD 176 DQ55

74 CKE1 126 VREFCA 178 VSS

76

78

80

VDD

A15

A14

128

130

132

VSS

DQ36

DQ37

180

182

184

DQ60

DQ61

VSS

VDD

A11

A7

134

136

138

VSS

DM4

VSS

186 DQS7#

188 DQS7

190 VSS

VDD 140 DQ38 192 DQ62

A6 142 DQ39 194 DQ63

40

42

44

46

48

DQ20

DQ21

VSS

DM2

VSS

92

94

96

98

A4

VDD 146 DQ44 198 EVENT# *

A2

A0

144

148

150

VSS

DQ45

VSS

50 DQ22 102 CK1 154 DQS5

52 DQ23 104 CK1# 156 VSS

196

200

202

100 VDD 152 DQS5# 204

VSS

SDA

SCL

VTT

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PART NO.:

Function Block Diagram

Product Specifications

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

A0-A15

BA0-BA2

RAS#

CAS#

WE#

CKE0

ODT0

CKE1

ODT1

RESET#

CK0

CK0#

CS1#

CS0#

DQS0

DQS0#

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Vss

DQS1

DQS1#

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

Vss

DQS2

DQS2#

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

Vss

DQS3

DQS3#

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

Vss

3.3pF

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D0

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D8

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D1

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D9

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D2

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D10

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D3

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D11

ZQ

Vss

D0-D7

A0-A15: SDRAMs D0-D15

BA0-BA2: SDRAMs D0-D15

RAS#: SDRAMs D0-D15

CAS#: SDRAMs D0-D15

WE#: SDRAMs D0-D15

CKE0: SDRAMs D0-D7

ODT0: SDRAMs D0-D7

CKE1: SDRAMs D8-D15

ODT1: SDRAMs D8-D15

RESET#: SDRAMs D0-D15

CK1

CK1#

3.3pF

D8-D15

DQS4

DQS4#

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

Vss

DQS5

DQS5#

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

Vss

DQS6

DQS6#

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

Vss

DQS7

DQS7#

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS

D4

DQS#

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS

D5

DQS#

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS

D6

DQS#

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D12

ZQ

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D13

ZQ

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D14

ZQ

Vss

Vss

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS

D7

DQS# DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D15

ZQ

Vss

Command, address, control, and clock line terminations

A0-A15, BA0-BA2

RAS#, CAS#, WE#,

CS0#, CKE0, ODT0

CS1#, CKE1, ODT1

CK0, CK1

CK0#, CK1#

DDR3

SDRAM

DDR3

SDRAM

36 ohm +/-5%

VTT

30 ohm +/-5%

0.1uF

VD D

Serial PD

SCL

Vss

WP

A0 A1 A2

SA0 SA1

Vss

SDA

VDDSPD

VDD

VTT

VR EFCA

VREFDQ

VSS

Notes:

1. Unless otherw ise noted, resistor values are 15 ohms +/-5%

2. ZQ resistors are 240 ohms +/-1%

Serial PD

D0-D15

D0-D15

D0-D15

D0-D15

D0-D15

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Product Specifications

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

Symbol

VDD

Absolute Maximum Ratings

Parameter

Voltage on VDD pin relative to VSS

VDDQ Voltage on VDDQ pin relative to VSS

VIN, VOUT Voltage on any pin relative to VSS

TSTG Storage temperature

MIN

-0.4

-0.4

-0.4

-55

MAX

1.975

1.975

1.975

100

Unit

V

V

V

0

C

IL

IOZ

IVREF

Input leakage current; Any input 0V<VIN<VDD;

VREF input 0V<VIN<0.95V;

Other pins not under test = 0V

Address, RAS#,

CAS#, WE#, BA

CS#, CKE, ODT,

CK, CK#

DM

Output leakage current;

0V<VOUT<VDDQ; DQs and ODT are disabled

DQ, DQS, DQS#

VREF supply leakage current; VREF = Valid VREF level

-32

-16

-4

-10

-16

Symbol

VDD

VDDQ

Supply Voltage

I/O Supply Voltage

VREFDQ (DC) I/O reference voltage DQ bus

DC Operating Conditions

Parameter Min

1.425

1.425

0.49 x VDD

Typical

1.5

1.5

0.5 x VDD

Max

1.575

1.575

0.51 x VDD

32

16

4

10

16 uA uA uA uA uA

Unit Notes

V

V

V

1,2

1,2

3,4

VREFCA (DC) Input reference voltage CMD/ADD bus 0.49 x VDD 0.5 x VDD 0.51 x VDD V 3,4

VTT

Symbol

T

OPER

Termination Reference Voltage -0.483 x VDDQ 0.5 x VDDQ +0.517 x VDDQ

Note:

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD

4. For reference: approximate VDD/2 +/-15mV.

5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce timing margins.

Operating Temperature Condition

Parameter

Operating temperature

Rating

0 - 95

V 5

Units Notes

o

C 1,2

Notes:

1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51-2.

2. At 0 – 85

85 o

C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when o

C < TOPER <= 95 o

C.

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Product Specifications

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

Input DC Logic Level

All voltages referenced to VSS

Parameter Symbol

Command and Address

VIHCA(DC)

Input High (Logic 1) Voltage (DDR3-800/1066/1333/1600)

VILCA(DC) Input Low (Logic 0) Voltage

(DDR3-800/1066/1333/1600)

Min

VREF + 0.100

VSS

DQ and DM

VIHDQ(DC) Input High (Logic 1) Voltage

(DDR3-800/1066/1333/1600)

VILDQ(DC) Input Low (Logic 0) Voltage (DDR3-800/1066/1333/1600)

Symbol

Input AC Logic Level

All voltages referenced to VSS

Parameter

VREF + 0.100

VSS

Min

Max

VDD

VREF - 0.100

VDD

VREF - 0.100

Max

Command and Address

VIHCA(AC) Input High (Logic 1) Voltage

(DDR3-800/1066/1333/1600)

VILCA(AC) Input Low (Logic 0) Voltage

(DDR3-800/1066/1333/1600)

VREF + 0.175

-

-

VREF - 0.175

DQ and DM

VIHDQ(AC)

Input High (Logic 1) Voltage

(DDR3-800/1066)

VILDQ(AC)

Input Low (Logic 0) Voltage (DDR3-800/1066)

VIHDQ(AC) Input High (Logic 1) Voltage

(DDR3-1333/1600)

Input Low (Logic 0) Voltage

(DDR3-1333/1600)

VILDQ(AC)

Parameter

VREF + 0.175

-

VREF + 0.150

-

-

VREF - 0.175

-

VREF - 0.150

Input/Output Capacitance

TA=25

0

C, f=100MHz

Symbol

K0

(DDR3-1600)

K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Min Max Min Max Min Max Min Max

Input capacitance

(A0~A15, BA0~BA2, RAS#, CAS#, WE#)

Input capacitance

(CKE0, CKE1), (ODT0, ODT1), (CS0#, CS1#)

Input capacitance (CK0, CK0#), (CK1, CK1#)

CIN1

CIN2

CIN3

16

10

24.8

14.4

16

10

24.8

14.4

16

10

28

16

16

10

28

16

10.4 15.2 10.4 15.2 10.4 16.8 10.4 16.8

Unit

V

V

V

V

V

V

V

V

V

V

Unit

Unit

pF pF pF

Input/Output capacitance (DQ, DQS, DQS#, DM) CIO 7 8.6 7 9 7 9.4 7 10

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5

pF

Product Specifications

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

IDD Specification

Condition Symbol

K0

(DDR3-1600)

K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Operating one bank active-precharge current;

tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD);

CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.

Precharge power-down current;

All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING.

Precharge standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is

HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING.

Precharge quiet standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is

HIGH; Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING.

Active power-down current;

All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING.

Active standby current;

All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING.

Operating burst read current;

All device banks open; Continuous burst reads; IOUT = 0mA;

BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS

MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as IDD4W.

Operating burst write current;

All device banks open; Continuous burst writes; BL = 8; CL =

CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Burst refresh current;

tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Self refresh current;

CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING.

IDD0*

IDD1*

IDD2P-F**

IDD2P-S**

IDD2N**

IDD2Q**

IDD3P**

IDD3N**

IDD4R*

IDD4W*

IDD5**

IDD6**

600

720

320

240

480

480

480

800

1120

1240

2880

240

560

680

320

240

480

400

400

720

1000

1160

2720

240

520

640

320

240

400

400

400

640

880

960

2480

240

Operating bank interleave read current;

All bank interleaving reads; IOUT = 0mA; BL = 8; CL =

CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is

HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R.

IDD7* 1800 1760 1440

Note: IDD specification is based on Samsung A-die components.

*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.

**: Value calculated reflects all module ranks in this operating condition.

520

640

320

240

400

400

400

640

880

960

2480

240

1440

Unit

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6

mA mA mA mA mA mA mA mA mA mA mA mA mA

Product Specifications

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

Parameter

AC TIMING PARAMETERS & SPECIFICATIONS

Symbol

K0

(DDR3-1600)

MIN MAX

K9

(DDR3-1333)

MIN MAX

F8

(DDR3-1066)

MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - 8 -

E7

(DDR3-800)

MIN MAX

8 -

Average Clock Period

Clock Period

Average high pulse width

Average low pulse width

Clock Period Jitter

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

Cumulative error across n = 13, 14 ... 49, 50 cycles

Absolute clock HIGH pulse width

Absolute clock Low pulse width

Data Timing

DQS,DQS# to DQ skew, per group, per access

DQ output hold time from DQS, DQS#

DQ low-impedance time from CK, CK#

DQ high-impedance time from CK, CK#

Data setup time to DQS, DQS# referenced to Vih(ac)Vil(ac) levels

Data hold time to DQS, DQS# referenced to

Vih(ac)Vil(ac) levels

DQ and DM Input pulse width for each input tCK(avg) tCK(abs) tCH(avg) tCL(avg) tJIT(per) tJIT(per, lck) tJIT(cc) tJIT(cc, lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) tERR(nper) tCH(abs) tCL(abs) tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) tDH(base) tDIPW ns

1.25 <1.50 1.5 <1.875 1.875 <2.5 2.5 3.3 tCK(avg)min

+

tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+

tJIT(per)max tCK(avg)min

+

tJIT(per)min tCK(avg)max

+

tJIT(per)max

0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 ns ns tCK(avg)

0.47

-70

-60

-103

-122

-136

-147

-155

-163

-169

-175

-180

-184

-188

0.43

0.43

-

0.38

-450

-

10

45

360

140

120

0.53

70

60

103

122

136

147

155

163

169

175

180

184

188

-

-

100

-

225

225

-

-

-

0.47

-80

-70

-118

-140

-155

-168

-177

-186

-193

-200

-205

-210

-

0.38

-500

-

30

65

400

160

140

0.53

80

70

118

140

155

168

177

186

193

200

205

210

-215 215 -242 242 tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min

tERR(nper)max=(1+ 0.68ln(n))*tJIT(per)max

0.43 - 0.43 -

0.43 - 0.43 -

125

-

250

250

-

-

-

0.47

-90

-80

-132

-157

-175

-188

-200

-209

-217

-224

-231

-237

-

0.38

-600

-

25

100

490

180

160

0.53

90

80

132

157

175

188

200

209

217

224

231

237

150

-

300

300

-

-

-

0.47

-100

-90

-147

-175

-194

-209

-222

-232

-241

-249

-257

-263

-269

0.43

0.43

-

0.38

-800

-

75

150

600

200

180

0.53

100

90

147

175

194

209

222

232

241

249

257

263

269

-

-

200

-

400

400

-

-

-

Unit

tCK(avg) ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK(avg) tCK(avg) ps tCK(avg) ps ps ps ps ps

Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –

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7

Product Specifications

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

Parameter

Data Strobe Timing

DQS, DQS# READ Preamble

DQS, DQS# differential READ Postamble

AC TIMING PARAMETERS & SPECIFICATIONS

Symbol

K0

(DDR3-1600)

MIN MAX

K9

(DDR3-1333)

MIN MAX

F8

(DDR3-1066)

MIN MAX

E7

(DDR3-800)

MIN MAX

tRPRE tRPST

0.9

0.3

-

-

0.9

0.3

-

-

0.9

0.3

-

-

0.9

0.3

-

-

DQS, DQS# output high time

DQS, DQS# output low time

DQS, DQS# WRITE Preamble

DQS, DQS# WRITE Postamble

DQS, DQS# rising edge output access time from rising CK, CK#

DQS, DQS# low-impedance time

(Referenced from

DQS, DQS# high-impedance time

(Referenced from RL+BL/ 2)

DQS, DQS# differential input low pulse width

DQS, DQS# differential input high pulse width

DQS, DQS# rising edge to CK, CK# rising edge

DQS,DQS# failing edge setup time to CK,

CK# rising edge

DQS,DQS# failing edge hold time to CK,

CK# rising edge

Command and Address Timing

DLL locking time

Internal READ Command to PRECHARGE

Command delay

Delay from start of internal write transaction to internal read command

WRITE recovery time

Mode Register Set command cycle time

Mode Register Set command update delay

CAS# to CAS# command delay

Auto precharge write recovery + precharge time

Multi-Purpose Register Recovery Time

ACTIVE to PRECHARGE command period

ACTIVE to ACTIVE command period for

1KB page size

ACTIVE to ACTIVE command period for

2KB page size

Four activate window for 1KB page size

Four activate window for 2KB page size

Command and Address setup time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

Command and Address hold time from CK,

CK# referenced to Vih(ac) / Vil(ac) levels

Control & Address Input pulse width for each input tDLLK tRTP tWTR tWR tMRD tMOD tCCD tDAL(min) tMPRR tRAS tQSH tQSL tWPRE tWPST tDQSCK tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH tRRD tRRD tFAW tFAW tIS(base) tIH(base) tIPW

512 max

(4tCK,7.5ns) max

(4tCK,7.5ns)

15

4 max

(12tCK,15ns)

4

1

35 max

(4tCK,6ns) max

(4tCK,7.5ns)

30

40

45

-450

-

0.45

0.45

-0.27

0.18

0.18

0.4

0.4

0.9

0.3

-225

120

560

-

-

-

-

-

-

-

225

225

0.55

0.55

0.27

-

-

-

-

-

-

225

-

9*tREFI

-

-

-

-

-

-

-

-500

-

0.45

0.45

-0.25

0.2

0.2

0.4

0.4

0.9

0.3

-255

140

620

250

250

0.55

0.55

0.25

-

-

-

-

-

-

255

-

-

-600

-

0.45

0.45

-0.25

0.2

0.2

0.38

0.38

0.9

0.3

-300

512 max

(4tCK,7.5ns) max

(4tCK,7.5ns)

15

-

-

-

-

-

512 max

(4tCK,7.5ns) max

(4tCK,7.5ns)

15

4 max

(12tCK,15ns)

4

-

- 4 max

(12tCK,15ns)

4

WR + roundup (tRP / tCK(AVG))

-

9*tREFI

1

36 max

(4tCK,6ns) max

(4tCK,7.5ns)

30

45

65

-

-

-

-

-

1

37.5 max

(4tCK,7.5ns) max

(4tCK,10ns)

37.5

50

125

-

-

-

-

-

-

-

-

9*tREFI

-

-

-

-

-

200

780

300

300

0.55

0.55

0.25

-

-

-

-

-

-

300

-

-

512 max

(4tCK,7.5ns) max

(4tCK,7.5ns)

15

4 max

(12tCK,15ns)

4

1

37.5 max

(4tCK,10ns) max

(4tCK,10ns)

40

50

200

-800

-

0.45

0.45

-0.25

0.2

0.2

0.38

0.38

0.9

0.3

-400

275

900

-

-

-

-

-

-

-

-

400

400

0.55

0.55

0.25

-

-

-

-

-

-

400

-

-

-

9*tREFI

-

-

-

-

Unit

ns ns ps ns nCK nCK nCK nCK ns ps ps tCK tCK tCK(avg) tCK(avg) tCK tCK ps ps ps tCK tCK tCK(avg) tCK(avg) tCK(avg) nCK

Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –

www.virtium.com

8

Product Specifications

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

Parameter

Refresh Timing

4Gb REFRESH to REFRESH OR

REFRESH to ACTIVE command interval

Average periodic refresh interval

(0°C<= TCASE <= 85 °C)

Average periodic refresh interval

(85°C<= TCASE <= 95 °C)

AC TIMING PARAMETERS & SPECIFICATIONS

Symbol

K0

(DDR3-1600)

MIN MAX

K9

(DDR3-1333)

MIN MAX

F8

(DDR3-1066)

MIN MAX

tRFC tREFI tREFI

300

7.8

3.9

-

-

-

300

7.8

3.9

-

-

-

300

7.8

3.9

-

-

-

E7

(DDR3-800)

MIN MAX

300

7.8

3.9

-

-

-

Calibration Timing

Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - 512 - tZQoper tZQCS

256

64

-

-

256

64

-

-

256

64

-

-

-

-

Normal operation Full calibration time

Normal operation Short calibration time

Reset Timing

Exit Reset from CKE HIGH to a valid command

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

Valid Clock Requirement after Self Refresh

Entry (SRE)

Valid Clock Requirement before Self

Refresh Exit (SRX)

Power Down Timing

Exit Power Down with DLL to any valid command; Exit Precharge Power Down with

DLL frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL

CKE minimum pulse width tXPR tXS tXSDLL tCKESR tCKSRE tCKSRX tXP tXPDLL tCKE tCPDED tPD max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC+10ns) tDLLK(min) tCKE(min) +

1tCK max(5tC,

10ns) max(5tC,

10ns) max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

-

- max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC+10ns) tDLLK(min) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

-

-

9*tREFI max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

-

- max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC +10ns) tDLLK(min) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

-

-

9*tREFI max

(3tCK,7.5ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

-

-

256

64 max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC +10ns) tDLLK(min) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

-

-

-

-

9*tREFI max

(3tCK,7.5ns) max

(10tCK,24ns) max (3tCK,

7.5ns)

1 tCKE(min)

-

-

-

-

-

-

-

-

-

-

9*tREFI

Command pass disable delay

Power Down Entry to Exit Timing

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power

Down entry

Timing of WR command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WRA command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WR command to Power Down entry (BL4MRS)

Timing of WRA command to Power Down entry (BL4MRS)

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry tACTPDEN tPRPDEN

1

1 tRDPDEN tWRPDEN tWRAPDEN tWRPDEN tWRAPDEN tREFPDEN

RL + 4 +1

WL + 4

+(tWR/ tCK)

WL+4+WR+

1

WL + 2

+(tWR/ tCK)

WL+2+WR+

1

1 tMRSPDEN tMOD(min)

-

-

-

-

-

-

-

-

-

1

1

RL + 4 +1

WL + 4

+(tWR/ tCK)

WL+4+WR+1

WL + 2

+(tWR/ tCK)

WL+2+WR+1

1 tMOD(min)

-

-

-

-

-

-

-

-

-

1

1

RL + 4 +1

WL + 4

+(tWR/ tCK)

WL+4+WR+1

WL + 2

+(tWR/ tCK)

WL+2+WR+1

1 tMOD(min)

-

-

-

-

-

-

-

-

-

1

1

RL + 4 +1

WL + 4

+(tWR/ tCK)

WL+4+WR+1

WL + 2

+(tWR/ tCK)

WL+2+WR+1

1 tMOD(min)

-

-

-

-

-

-

-

-

-

Unit

ns us nCK nCK tCK nCK nCK nCK nCK nCK nCK us tCK tCK tCK

Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –

www.virtium.com

9

Product Specifications

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

Parameter

ODT Timing

ODT high time without write command or with write command and BC4

AC TIMING PARAMETERS & SPECIFICATIONS

Symbol

K0

(DDR3-1600)

MIN MAX

K9

(DDR3-1333)

MIN MAX

F8

(DDR3-1066)

MIN MAX

ODTH4 4 - 4 - 4 -

ODTH8 6 - 6 - 6 -

E7

(DDR3-800)

MIN MAX

4

6

-

- ODT high time with Write command and BL8

Asynchronous RTT turn-on delay (Power-

Down with DLL frozen)

Asynchronous RTT turn-off delay (Power-

Down with DLL frozen)

ODT turn-on

RTT_NOM and RTT_WR turn-off time from

ODTL off reference

RTT dynamic change skew tAONPD tAOFPD tAON tAOF tADC

2

2

-225

0.3

0.3

8.5

8.5

225

0.7

0.7

2

2

-250

0.3

0.3

8.5

8.5

250

0.7

0.7

2

2

-300

0.3

0.3

8.5

8.5

300

0.7

0.7

2

2

-400

0.3

0.3

8.5

8.5

400

0.7

0.7

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is programmed

DQS/DQS delay after tDQS margining mode is programmed

Setup time for tDQSS latch tWLMRD tWLDQSEN tWLS

40

25

165

-

-

-

40

25

195

-

-

-

40

25

245

-

-

-

40

25

325

-

-

-

Hold time for tDQSS latch

Write leveling output delay

Write leveling output error tWLH tWLO tWLOE

165

0

0

-

7.5

2

195

0

0

-

9

2

245

0

0

-

9

2

325

0

0

-

9

2

Unit

nCK nCK ns ns ps tCK(avg) tCK(avg) ps ns ns tCK tCK ps

Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –

www.virtium.com

10

Product Specifications

Package Dimensions

PART NO.:

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

FRONT VIEW

67.60

3.40 MAX

4.0 +/- 0.10 (2X)

20.00

30.00

1.80 (2X)

TYP

6.00 TYP

2.15 TYP

PIN 1

1.0 +/- 0.10

TYP

0.5 R

0.60 TYP

63.60 TYP

0.45 TYP

BACK VIEW

PIN 203

1.0 +/- 0.10

2.55 TYP

PIN 204

39.00 TYP

3.00 TYP

21.00 TYP

24.80 TYP

4.00 TYP

PIN 2

Note: 1. All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.

2. The dimensional diagram is for reference only.

Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –

www.virtium.com

11

Product Specifications

PART NO.:

Revision History:

VN-130809

Date Rev. Page Changes

02/28/2011 1.0 All Spec release

VL47B1G63A-K0-K9-F8-E7S

REV: 1.0

Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA –

www.virtium.com

12

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