FlashOverview AN

FlashOverview AN
Flash Memory: An Overview
Application Note
1. Introduction
All computer-based systems contain memory. Memory is where information is stored while waiting to be
operated on by the Central Processing Unit (CPU) of the computer. There are two types of memory: volatile
memory and non-volatile memory. Volatile memory retains its information only while power is applied to the
memory device. The contents of this memory type may be easily and quickly changed. Non-volatile memory
retains its information even when no power is applied to the memory device. Although the information in most
non-volatile memories may be changed, the process involved is much slower than for volatile memory.
2. Volatile Memory
Volatile memory loses its contents when the device loses power. Random Access Memory (RAM) is the
traditional name used for volatile memory. The name refers to the ability to access any location of the
memory quickly with no particular order of accesses needed. Static RAM (SRAM) and Dynamic RAM (DRAM)
are two examples of volatile memories that have this characteristic.
SRAM typically uses six transistors for each memory bit (cell) to retain data as long as power is being
supplied. This makes each memory cell relatively large and limits SRAM to use in lower density memories.
SRAM can provide faster access to data, use less standby power, and tends to be more expensive than
DRAM.
DRAM uses a single transistor and a small capacitor for each bit of memory. Since capacitors do not hold a
charge indefinitely, DRAM cells must be frequently recharged (refreshed) to avoid losing the contents. These
smaller memory cells allow DRAM to be used for high density, low cost memories, but are typically slower
than SRAM.
3. Non-Volatile Memory
Non-volatile memory is memory that retains its contents even if the power is lost. Non-volatile memory was
originally called Read Only Memory (ROM) because its contents were loaded during the manufacturing
process and could be read, but never erased or reprogrammed. Over time, the ability to erase and reprogram
ROM was added in different ways and referred to as Electrically Programmable ROM (EPROM), Electrically
Erasable and Programmable ROM (EEPROM), and flash EEPROM - commonly referred to simply as flash
memory.
ROM memory is programmed by the way it is manufactured and stores permanent code and data that is
generally used to initialize and operate a computer system.
EPROM can be electrically programmed one byte at a time but is not electrically erasable. It has to be
exposed to ultra-violet (UV) light for about twenty minutes in order to erase all bits in the memory array.
EPROM uses a single transistor for each data bit and can be used in relatively high density memories.
EEPROM is electrically erasable and programmable in-system, one byte at a time, but the memory cells use
more transistors and are larger than those in EPROMs, thus EEPROM has higher costs and lower density
(generally less than 1 Mb).
Flash EEPROM memory can be electrically programmed a single byte or word at a time, but a large group of
bytes or words – called a block, sector, or page – are electrically erased at the same time. Due to the erase
operation being much faster than the prior EPROM or EEPROM devices, these devices came to be called
flash erase EEPROM, or simply flash memories. The flash memory cell uses a single transistor to store one
or more bits of information. Flash technology combines the high density of EPROM with the electrical
Publication Number FlashOverview_AN
Revision A1
Issue Date November 15, 2010
A pplication
Note
in-system erase and programmability of EEPROMs. Flash memory has become the dominant type of
non-volatile memory in use.
Table 3.1 compares the fundamental features of flash memory with those of the other memory technologies
discussed earlier. The remainder of the application note will cover only flash memory.
Table 3.1 Compares Flash Memory with Other Memory Technologies
Flash
Memory
Non volatile
High
Density
Low Power
One Transistor
Per Cell
In-System
Rewriteable
x
x
x
x
x
SRAM
DRAM
x
EPROM
x
EEPROM
x
x
x
x
Fully
Bit-Alterable
High-Performance
Read
x
x
x
x
x
x
x
x
x
x
x
x
x
4. Flash Memory Architectures
Two main architectures dominate flash memory: NOR and NAND.
NOR is typically used for code storage and execution. NOR allows quick random access to any location in the
memory array, 100% known good bits for the life of the part, and code execution directly from NOR flash
memory.
NOR is available in both parallel and serial interface configurations. Parallel configurations support either
separate or multiplexed address and data busses. Serial configurations support data transfers of 1, 2, or 4
bits in a host controlled synchronous transfers. This document refers to parallel NOR features and controls.
NAND is used for data storage. NAND flash requires a relatively long initial read access to the memory array,
98% good bits when shipped with additional bit failure over the life of the part (ECC highly recommended),
program/erase times are much faster than NOR and NAND costs less per bit than NOR.
NAND is primarily available in a parallel configuration with mulitplexed address and data busses.
Table 4.1 Difference Between NOR and NAND
Parameter
NOR
NAND
Density
1 Mbit – 2 Gbit
256 Mbit - 64 Gbit
10,000 ns
Read initial access
55 ns
Read sequential access
7 ns
50 ns
Program
0.3 - 1.5 Mbytes / s
2 - 166 Mbytes / s
Erase
0.2 - 0.7 Mbytes / s
10 - 60 Mbytes / s
Access Method
Random
Sequential
5. Spansion® Flash Memory
Spansion is one of the world's leading suppliers of NOR flash memory. Spansion flash memory products
include a broad spectrum of densities and features to support a wide range of customer specific markets such
as hand-held/mobile electronics, computer, set-top boxes, and automotive applications. Spansion primarily
uses two flash memory technologies: Floating Gate and MirrorBit®.
Floating Gate technology was first introduced in the early 1990's. It offered fast access times, and high
program/erase endurance cycles. This technology allowed the storage of only one data bit per cell. However,
with the introduction of MirrorBit technology in 2001, Spansion is able to offer a more cost-effective solution to
customers, while still maintaining fast access times and high endurance cycles. The cost effective solution is
the design of the MirrorBit storage cell, which can store two data bits per cell, instead of just one data bit. This
design enables manufacturing costs to be significantly lower than that of Floating Gate technology. MirrorBit
technology definitely has a clear economical, as well as a technological advantage over Floating Gate
technology.
2
FlashOverview_AN_A1
November 15, 2010
App l ic atio n
5.1
No t e
Distinctive Features
Spansion parallel NOR flash memory offers many distinctive features that help designers build feature-rich,
cost-effective systems. Key distinctive characteristics include:
 Secured Silicon Sector
 ACC
 WP#
 VI/O
 CFI
 Write Buffer
 Advanced Sector Protection
 Page Mode
 Burst Mode
 Simultaneous Read/Write
Secured Silicon Sector feature enables permanent part identification through an Electronic Serial Number
(ESN). The Secure Silicon Sector provides a 128 Bytes to 1 Kbytes area for code or data that can be
permanently protected. Once this sector is protected, no further changes within the sector can occur. The
Secure Silicon Sector Indicator Bit (DQ7) is used to determine whether or not the Secure Silicon Sector is
protected. Spansion offers the device with the Secure Silicon Sector either customer lockable or factory
locked. The customer-lockable version is shipped with the Secure Silicon Sector unprotected and has the
Secure Silicon Sector Indicator Bit permanently set to a 0. The factory-locked version is always protected and
has the Secure Silicon Sector Indicator Bit permanently set to a 1.
ACC (Accelerated Program Operation) is an input pin that allows for faster programming or erases operation
when raised to a specified voltage (12V or 9V).
WP# (Write Protect) is a hardware method for protecting boot sectors using standard control logic signals.
VI/O is a feature that allows the signal interface voltage levels to be determined by the VI/O power supply.
CFI is a feature that provides device-specific information to the system, allowing host software to easily
reconfigure for different flash devices. The device enters the CFI Query mode when the system writes the CFI
Query command, 98h, to address 55h, any time the device is ready to read array data. The system can also
write the CFI Query command when the device is in the Autoselect mode.
Write Buffer allows the system to write up to 32 words in one programming operation. It is implemented to
speed up programming operations. A Write Buffer is a set of registers used to hold several words that are to
be programmed as a group.
Advanced Sector Protection provides command-controlled rather than voltage-controlled protection to any
sector against inadvertent or malicious program or erase operations. Refer to the data sheet for detailed
information.
Page Mode allows high speed random read access to memory addresses near the initial access address.
Use of page mode can increase asynchronous read throughput by up to 300%.
Burst Mode allows high speed sequential reading of the flash without the need to update the address lines.
Synchronous transfers can occur at rates of up to 216 MBytes per second.
Simultaneous Read/Write allows the flash to be read from at the same time a program or erase operation is
being performed. Flash with this feature are subdivided into multiple banks of sector groups. While program
or erasing is occurring in one bank, the system can read from any other bank.
November 15, 2010
FlashOverview_AN_A1
3
A pplication
5.2
Note
Basic Operation
There are three basic operations in a flash memory: read (a byte or a word), program (a byte or a word), and
erase (one or more sectors).
5.2.1
Read
Spansion provides three types of read operations: asynchronous read, asynchronous page read, and
synchronous burst read. Asynchronous read is a read not occurring at predetermined or regular intervals (not
dependent on a clock). Typical read access time is 55 to 120 ns. Figure 5.1 shows the timing diagram.
Figure 5.1 Asynchronous Read Operation Timing
t RC
Addresses Stable
Addresses
t ACC
CE#
t RH
t RH
t DF
t OE
OE#
t OEH
WE#
t CE
t OH
High-Z
High-Z
Outputs
Output Valid
RESET#
RY/BY# 0 V
Asynchronous page read is an asynchronous read operation of several words, in which the first word of the
group takes a longer initial access time, and subsequent words in the group take less “page” access time to
be read. The page size of the page mode devices varies between 8 and 32 bytes, with the page being
selected by the least significant two to four bits of the address bus. Page mode interface provides faster read
access speed for random locations within a page. Initial access time is typically 70 to 120 ns. Access time
within a page is typically 20 to 30 ns. Figure 5.2 shows the page read timing diagram.
Figure 5.2 Page Read Timing
A19-A3
A2-A1
Same Page
Aa
t ACC
Data Bus
Ab
t PACC
Qa
Ac
tPACC
Qb
Ad
t PACC
Qc
Qd
CE#
Synchronous burst read is a read occurring at regular intervals dependent on a clock edge. Burst mode
devices require three extra control pins to perform burst read: Clock, Load Burst Address (LBA#) or Address
Valid (ADV#), and Burst Address Advance (BAA#) or RDY.
4
FlashOverview_AN_A1
November 15, 2010
App l ic atio n
No t e
When the burst device first powers up, it is enabled for asynchronous read operation. To enable synchronous
burst read, the system must issue the burst mode enable command sequence. The initial address of an
access is loaded by the clock edge when LBA# or AVD# is low. The first data word is available after the initial
access time delay. Sequential words are available on each subsequent rising clock edge after an initial burst
access delay of typically 50 to 104 ns. Burst accesses can continue at a clock rate of up to 108 MHz.
Depending on the specific device, Spansion burst mode flash offers a number of read modes to interface with
a wide range of microprocessors. They are linear burst, interleaved burst, and continuous sequential burst. In
the linear and interleaved burst modes, the device delivers a stream of words from a 4, 8, 16, or 32 word
aligned block. (For the S29CD family, the burst is 32-bit double words.) If the initial address is not at the
beginning of the block, the sequence of words following the initial access will wrap from the end to the
beginning of the block. In continuous sequential burst mode the device reads sequentially through the entire
address range. Refer to a specific burst device data sheet for detailed information. Figure 5.3 shows burst
read mode.
Figure 5.3 Burst Read Timing
t CEZ
t CES
CE#
CLK
t LBAS
LBA#
t BAAS
t LBAH
BAA#
A0:A18
t ACS
t BAAH
Aa
t BDH
t ACH
t BACC
DQ0:DQ15
t IACC
Da
Da + 1
t OE
Da + 2
Da + 3
Da
t OEZ
OE#*
IND#
5.2.2
Program
The unprogrammed state of a flash memory cell is a high signal level or logical one. Changing a flash
memory cell (or bit) to a low voltage level or zero is called programming. Programming on Spansion Floating
Gate flash is generally done one byte or word at a time. MirrorBit technology uses a write buffer to program
one byte to as many as 32 bytes.
One key point to note is that programming only changes ones to zeros. Programming is initiated by a series of
write accesses that form a program command. The required sequence of write accesses prevents unintended
changes to stored data.
5.2.3
Erase
Erasure of a flash device is done through multiple write accesses that form an erase command. The erase
completion time is dependent upon the sector size and technology. The erase command sequence initiates
the embedded erase algorithm – an internal algorithm that automatically preprograms the memory array (if it
is not already programmed) before executing the erase operation simultaneously on all bits of the sector.
One key point to note is that chip or sector erasing only changes zeros to ones. During erase, the device
automatically times the erase pulse widths and verifies the proper cell margin.
November 15, 2010
FlashOverview_AN_A1
5
A pplication
5.3
Note
Temperature Ranges
Spansion flash memory devices are available in various temperature ranges, as shown in Table 5.1.
Table 5.1 Various Temperature Options
5.4
Code
Name
Description
C
Commercial
0 to +70°C or + 85°C
W
Wireless
-25 to +85°C
I
Industrial
-40 to +85°C
V
Automotive-In cabin
-40 to +105°C
N
Extended
-40 to +125°C
H
Hot
-40 to +145°C
Spansion Product Families
Table 5.2 Spansion Product Families
Product Family
Architecture
Density
Core Voltage
AL
Floating Gate Technology, Low Voltage, Asynchronous,
Parallel NOR Flash Memory
8 Mb – 16 Mb
3V
AS
Floating Gate Technology, Super Low Voltage,
Asynchronous, Parallel NOR Flash Memory
8 Mb – 16 Mb
1.8V
CD
Floating Gate Technology, Very Low Voltage,
Simultaneous Read/Write, Synchronous, Parallel NOR
Flash Memory
16 Mb – 32 Mb
2.5V
CL
Floating Gate Technology, Low Voltage, Simultaneous
Read/Write, Synchronous, Parallel NOR Flash Memory
16 Mb – 32 Mb
3V
F
Floating Gate Technology, Asynchronous, Parallel NOR
Flash Memory
1 Mb – 8 Mb
5V
FL
Floating Gate or MirrorBit Technology, Low Voltage, High
Performance, Serial NOR Flash Memory
8 Mb – 512 Mb
3V
GL
MirrorBit Technology, Low Voltage, Page Mode,
Asynchronous, Parallel NOR Flash Memory
32 Mb – 2 Gb
3V
JL
Floating Gate Technology, Low Voltage, Simultaneous
Read/Write, Asynchronous, Parallel NOR Flash Memory
32 Mb – 64 Mb
3V
NS
Floating Gate or MirrorBit Technology, Super Low
Voltage, Simultaneous Read/Write, Synchronous,
Multiplexed Parallel NOR Flash Memory
32 Mb – 256 Mb
1.8V
PL
Floating Gate Technology, Low Voltage, Simultaneous
Read/Write, Page Mode, Asynchronous Parallel NOR
Flash Memory
32 Mb – 128 Mb
3V
VS
MirrorBit Technology, Super Low Voltage, Simultaneous
Read/Write, Synchronous, Multiplexed Parallel NOR
Flash Memory
128 Mb – 256 Mb
1.8V
WS
MirrorBit Technology, Super Low Voltage, Simultaneous
Read/Write, Synchronous, Parallel NOR Flash Memory
64 Mb – 512 Mb
1.8V
XS
MirrorBit Technology, Super Low Voltage, Simultaneous
Read/Write, Synchronous, Multiplexed Parallel NOR
Flash Memory
128 Mb – 256 Mb
1.8V
Note:
Devices have prefixes such as AM29, S25, and S29.
6. Conclusion
Spansion flash memory provides a compact, easy to use, non-volatile code and data storage solution for
electronic products. Spansion provides a broad portfolio of flash memories to suit a wide range of
applications. The memory size, voltage, speed, and package, can be selected to suit the application.
6
FlashOverview_AN_A1
November 15, 2010
App l ic atio n
No t e
7. Revision History
Section
Description
Revision A0 (November 10, 2005)
Initial release
Revision A1 (November 15, 2010)
Global
November 15, 2010
Updated to reflect current flash portfolio
FlashOverview_AN_A1
7
A pplication
Note
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2005-2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™
and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
8
FlashOverview_AN_A1
November 15, 2010
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement