RNA52A10MM Datasheet

RNA52A10MM Datasheet

Data Sheet

RNA52A10MM

Dual CMOS system–RESET IC

R03DS0091EJ0600

(Previous code: REJ03D0858-0500)

Rev.6.00

Dec 19, 2014

Description

The RNA52A10MM incorporates two reset circuits, one with and one without a delay function, allowing the generation of separate reset signals for a microprocessor and associated system circuits. The detection voltage of each reset circuit is determined by the value of an external resistor, and the internal reference voltage is 1.0 V. The CMOS process for the RNA52A10MM means that the device draws only 1.1

μA (typ.). The reset cancellation delay time is set with a high degree of accuracy by the values of a capacitor and resistor connected with the CD pin. The MR (manual reset) input pin is provided for the reset circuit with the delay function, and the reset signal is output in response to a high level on the MR input pin. The MR pin is pulled down by a 2-M

Ω internal resistor. Output pins Vo1 and Vo2 are open drain.

Features

• Two CMOS reset circuits, one with and one without the delay function

• Reference voltage: 1.0 V

• Reference voltage accuracy: ± 50 mV

• Reference voltage hysteresis: 6% (typ.)

• Low current consumption: 1.1 μA (typ.)

• Delay time set by an external CR circuit

• Manual reset input

• Open-drain output

• MMPAK-8 (8-pin) package

• Operating temperature range: – 40 to 85°C

• Ordering Information

Part Name Package Type Package Code

Package

Abbreviation

MM RNA52A10MMEL MMPAK-8 pin PLSP0008JC-A

Application

• Power-supply monitoring and resetting for microprocessors

• Power supply sequence control for microprocessors

• Desktop and laptop PCs

• PC peripheral devices such as printers

• Digital still cameras, digital video cameras, and PDAs

• Battery-driven products

• Wireless communications systems

Taping Abbreviation

(Quantity)

EL (3,000 pcs / Reel)

R03DS0091EJ0600 Rev.6.00

Dec 19, 2014

Page 1 of 11

RNA52A10MM

Pin Arrangement

Outline and Article Indication

• RNA52A10MM

MR

Vo1

Vo2

GND

3

4

1

2

Index band

6

5

8

7

VDD

Vi1

Vi2

CD

Marking

R 0 1

Y M W

Y : Year code

(the last digit of year)

M : Month code

W : Week code

MMPAK–8

Lot No.

R03DS0091EJ0600 Rev.6.00

Dec 19, 2014

Page 2 of 11

RNA52A10MM

Functional Block Diagram and Typical application Circuit

V

DD1

R

S1

R

S2

V

DD2

R

S3

7

Vi1

6

Vi2

Reset circuit 1

Reset circuit 2

V

DD3

R

L1

Vo1

2

Vo2

3

R

L2

RESET

Microcomputer

V

DD4

R

S4

V

REF

1.0V

2M

8

VDD

1

MR

5

CD GND

4

C

D

R

D

V

DD0

C

1

Notes: 1. Please refer to the following equations to set up reset-threshold voltages for power supplies V

DD1

and V

DD2

, and to set up external voltage-dividing resistor pairs R

S1

and R

S2

, and R

S3

and R

S4

.

(1) V

DD1

reset-threshold voltage = V

REF

× (R

S1

+R

S2

)/R

S2

(2) V

DD2

reset-threshold voltage = V

REF

×

(R

S3

+R

S4

)/R

S4

Note that values must be set up within the following range: R

S1

, R

S2

, R

S3

, R

S4

≤ 50 kΩ

See the following graph for the relationship between the reference voltage variation and the value selected for

R

S1

, R

S2

, R

S3

and R

S4

.

2. For capacitor C1, select a type which has excellent frequency characteristics. For stable operation, place it between the VDD pin and the GND pin and as close as is possible to the chip.

3. The value of capacitor C

1

must suit the system environment in terms of the quality of the power supply and so forth.

Reference Voltage Variation vs. Parallel Resistance

5

4

3

2

1

0

-1

0.1

1 10 100

Parallel Resistance (RS1//RS2, RS3//RS4) [kΩ]

1000

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Dec 19, 2014

Page 3 of 11

RNA52A10MM

Timing Diagram

1. I/O Table

MR

L

H

Vi1, Vi2

≤ V

REF

≥ (V

REF

+V

HYS

)

≤ V

REF

≥ (V

REF

+V

HYS

)

Vo1

L

H

L

H

Vo2

L

H (after T

DLY0

)

L

2. Timing Chart

(V

REF

+V

HYS

)

Vi1, Vi2

V

REF

(V

REF

+V

HYS

)

V

DD0

MR

V

DD3

Vo1

T

DLY0

Vo2

Absolute Maximum Ratings

T

DLY0

T

DLY0

V

DD4

Supply voltage (VDD)

Continuous power dissipation

(Ta = 25°C, in still air)

V

DD

6.0 V

Input voltage (Vi1, Vi2, MR, CD) V

IN

Output voltage (

Vo1, Vo2) V

OUT

–0.3 to V

DD

–0.3 to 6.0

V

V

Output current (

Vo1, Vo2) I

OUT

30 mA

P

D

145 mW

Operating temperature

Storage temperature

T

OPR

T

STG

–40 to 85

–55 to 125

Note: Refer to the relevant characteristic curve on page 6 for continuous power dissipation.

°C

°C

Recommended Operating Conditions

Supply voltage (VDD) V

DD

1.4 5.5 V

Input voltage (Vi1, Vi2, MR, CD) V

IN

Output voltage (

Vo1, Vo2) V

OUT

0 5.5 V

Output current (

Vo1, Vo2) I

OUT

V

DD

V

Operating temperature T

OPR

–40 85 °C

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Dec 19, 2014

Page 4 of 11

RNA52A10MM

Electrical Characteristics

(Ta = 25°C, unless otherwise noted)

Supply voltage

Current consumption

Test

Conditions

Circuit

V

DD

1.4 — 5.5 V

I

DD

V

DD

= 5.5 V

V i1

= V

i2

= 5.5 V

V

REF

0.95 1.00 1.05 V = 3.3 V

1

2 Reference voltage

Reference voltage temperature coefficient

(Reference value for design)

ΔV

REF

V

REF

⋅ΔT a ppm

— ±100 —

°C

T a

= –40 to 85°C 2

Vi1, Vi2 input hysteresis voltage

V

HYS

28.5

(V

REF

×3%)

60

(V

REF

×6%)

94.5

(V

REF

×9%) mV V

DD

= 3.3 V 2

Vi1, Vi2 input current

CD input threshold voltage

Vo1, Vo2 low-level output voltage

Vo1, Vo2 output leakage current

I

IN

V

DLY

V

OL

I

LK

V

DD

×0.43

V

DD

×0.63

V

DD

×0.83

V

V

DD

= 5.5 V

V i1

= V

i2

= 5.5 V

V

DD

= 3.3 V

V i1

= V

i2

= 1.2 V

V

DD

= 1.4V

V

i2

= 0 V

I

OL

= 0.5 mA

V

DD

= 3.3V

V i1

= V

i2

= 0 V

I

OL

= 5 mA

V

DD

= V nA

O1

= V

O2

= 5.5 V

V i1

= V

i2

= 1.2 V

3

4

5

6

7

Vo2

Delay time

Note1

Incomplete discharge of capacity CD complete discharge of capacity CD

Vo1

Rise response time

T

DLY

1.1 11 ms

T

DLY0

7 ms

V

DD

= 3.3 V

V i2

= 0 V

→1.2 V

C

D

= 0.3

μF, R

D

= 39 k

Ω

8

8

Vo1, Vo2 fall response time

MR low-level input voltage

MR high-level input voltage

MR input pull-down resistance

V

DD

< 4.5V

V

DD

≥ 4.5V

T

T

PLH

PHL

μs

μs

V

IL

— —

DD

V

DD

= 3.3 V

V i1

= V

i2

= 1.2 V

V

DD

= 3.3 V

V

V i1

= V

i2

= 1.2 V

V

IH

V

DD

×0.75

V

DD

V

DD

= 3.3 V

V i1

= 0 V

→1.2 V

V

DD

= 3.3 V

V i1

= V i2

= 1.2 V

→0 V

C

D

= 0.3

μF, R

D

= 39 k

Ω

R

MR

0.5 2 —

Ω

V i1

= V

i2

= 1.2 V

V

DD

= 5.5 V

V

MR

= 5.5 V

9

10

11

11

12

13

Notes: 1. When capacitor C

D

is completely discharged and charging starts in the state that C

D

pin voltage is 0 V, the minimum value of delay time T

DLY0

is 7 ms. However, when the discharging time is short and charging starts in the state that the voltage does not completely fall to 0 V, the minimum value of delay time T

DLY

Then, the minimum value of Low time (reset time) of

Vo2 is 1.1 ms as the delay time T

DLY

is 1.1 ms.

. Refer to

Regulations for state of capacitor C

D

electrical discharge and delay time on page 10 for details.

2. Refer to the characteristic curves on page 6 for temperature dependence of the main characteristics.

3. Refer to pages 8 and 9 for the test circuits.

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Dec 19, 2014

Page 5 of 11

RNA52A10MM

Characteristic curves

Heat decrease curve

200

150

100

50

0

0 25 50 75 100

Ambient Temperature Ta [

°C]

125 150

Reference voltage V

REF

1.04

1.02

V

DD

= 3.3 V

1.00

0.98

0.96

-50 -25 0 25 50

Ambient Temperature Ta [

°C]

75 100

Vo1, Vo2 Low-level output voltage V

OL

0.4

0.3

0.2

V

DD

= 3.3 V, I

OL

= 5 mA

0.1

V

DD

= 1.4 V, I

OL

= 0.5 mA

0

-50 -25 0 25 50

Ambient Temperature Ta [

°C]

75 100

Rise Response Time T

PLH

1000

100

V

DD

= 3.3 V, Vi1 = 0 to 1.2 V

10

1

-50 -25 0 25 50

Ambient Temperature Ta [

°C]

75 100

R03DS0091EJ0600 Rev.6.00

Dec 19, 2014

Current Dissipation I

DD

20

15

10

5

V

DD

= 5.5 V, Vi1 = Vi2 = 5.5 V

0

-50 -25 0 25 50

Ambient Temperature Ta [

°C]

75 100

Vi1, Vi2 Input Current I

IN

2.0

1.5

1.0

0.5

V

DD

= 5.5 V, Vi1 = Vi2 = 5.5 V

0.0

-50 -25 0 25 50

Ambient Temperature Ta [

°C]

75 100

Delay time T

DLY0

20

15

V

DD

= 3.3 V, Vi2 = 0 to 1.2 V

CD = 0.3

μF, RD = 39 kΩ

10

5

0

-50 -25 0 25 50

Ambient Temperature Ta [

°C]

75 100

1000

100

Fall Response Time T

PHL

V

DD

= 3.3 V, Vi1 = Vi2 = 1.2 to 0 V

CD = 0.3

μF, RD = 39 KΩ

Vi2

10

Vi1

1

-50 -25 0 25 50

Ambient Temperature Ta [

°C]

75 100

Page 6 of 11

RNA52A10MM

Pin Descriptions

Pin No. Pin Name Function

Manual reset input pin for reset circuit 2 (the circuit with the delay function).

The MR signal is active high, so applying a high level to MR sets the Vo2 pin to the low level.

1 MR

> V

REF

when the signal on the MR pin is changed back from the high to the low level, the Vo2 pin is returned from the low to the high level after a delay time T

DLY0

. This can be set as required. The MR pin is pulled down to the GND level via an internal 2-M

Ω resistor . However, we recommend connection of the pin to the GND line when it is not in use.

2

3

Vo1

Vo2

Reset signal output pin for reset circuit 1 (the circuit with no delay function). The output is open-drain.

The recommended value of the pull-up resistor (R

L1

) is 3 k to 100 k

Ω. When the voltage input on pin Vi1 falls to or below V

REF

, the signal output from the

Vo1 pin is changed from the high to the low level. Since the characteristic includes hysteresis, the signal output from the

Vo1 pin changes from the low to the high level when the voltage input on pin Vi1 rises to or above V

REF

+V

HYS

. Refer to the timing diagram on page 4 for details.

Reset signal output pin for reset circuit 2 (the circuit with the delay function). The output is open-drain.

The recommended value for the pull-up resistor (R

L2

) is 3 k to 100 k

Ω. When the voltage input on pin Vi2 falls to or below V

REF

, the signal output from the

Vo2 pin is changed from the high to the low level. Since the input characteristic includes hysteresis, the signal output from the

Vo2 pin changes from the low to the high level when the voltage input on pin Vi2 rises to or above V

REF

+V

HYS

and the set delay time T

DLY0

has elapsed. Refer to the timing diagram on page 4 and regulations for state of capacitor C

D

electrical discharge and delay time on page 10 for details.

Pin for connection to the resistor (R

D

) and capacitor (C

D

) for setting of the delay time, T

DLY0

. Refer to the Block

Diagram and Typical Application Circuit on page 2 for an example of the connection. The relation by which the resistance and capacitance set up the delay time can be expressed as T

DLY0

= 0.94

× C

D

× R

D

. Refer to this formula in determining the values of resistance and capacitance. Resistance R

D

must use the one within the range of 1 k to 1 M

Ω. Ensure that capacitor C

D

has a value no greater than 1.3

μF. The dependence of delay time T

DLY0

on the values of external capacitor C

D

and external resistor R

D is illustrated on page 10. To avoid errors due to noise input via the CD pin, this input includes a Schmitt-trigger inverter.

Voltage input pin for reset circuit 2 (the circuit with the delay function). When the input voltage falls to or below

V

REF

, the signal output from the

Vo2 pin is changed to the low level. Since the input characteristic includes hysteresis, the signal output from the

Vo2 pin is changed from the low to the high level after the voltage input on pin Vi2 has risen to or above V

REF

+V

HYS

and delay time T

DLY

has elapsed. The reset-threshold voltage is derived from the power-supply voltage V

6 Vi2

DD2

according to the division ratio set up by resistors R

S3 and R

S4 as described under the block diagram and typical application circuit on page 3. To avoid shifting of the reset detection voltage being shifted by input current via the Vi2 pin, select a value no greater than 25 k

Ω for parallel resistors R

S3 and R

S4

. Refer to the graph on page 3 for details. Besides, to avoid errors due to noise in powersupply voltage V

DD2

, select a capacitor with superior frequency characteristics and connect it between the Vi2 and GND pins.

Voltage input pin for reset circuit 1 (the circuit without the delay function). When the input voltage falls to or below V

REF

, the signal output from the

Vo1 pin is changed to the low level. Since the input characteristic includes hysteresis, the signal output from the

Vo1 pin is changed from the low to the high level after the voltage input on pin Vi1 has risen to or above V

REF

+V

HYS

. The reset-threshold voltage is derived from the

7 Vi1

DD1

according to the division ratio set up by resistors R

S1 and R

S2 as described under the block diagram and typical application circuit on page 3. To avoid shifting of the reset detection voltage being shifted by input current via the Vi1 pin, select a value no greater than 25 k

Ω for parallel resistors R

S1 and R

S2

.

Refer to the graph on page 3 for details. Besides, to avoid errors due to noise in power-supply voltage V

DD1

, select a capacitor with superior frequency characteristics and connect it between the Vi2 and GND pins.

Power-supply pin for the chip. For stable operation, select a capacitor with superior frequency characteristics and connect it between the VDD and GND pins and as close to the chip as possible. When selecting the value

8 VDD of the capacitor, consider aspects of the system environment such as the quality of the power supply. Refer to the block diagram and typical application circuit on page 3 for details.

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Dec 19, 2014

Page 7 of 11

RNA52A10MM

Test Circuits

1

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

A

3

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

A

A

2

4

5 6

V

V

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5 V

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

V

V

V

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

7

A A

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

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Dec 19, 2014

Page 8 of 11

RNA52A10MM

Test Circuits (cont.)

8

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

9

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

10

Vi2

0 V

Vo2

0 V

1.06 V

TDLY0

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

1.65 V

3.3 V

3.3 V

11

Vi1

0 V

Vo1

0 V

1.06 V

TPLH

1.65 V

3.3 V

3.3 V

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

12

Vi1, Vi2

3.3 V

Vo1, Vo2

3.3 V

1.0 V

TPHL

1.65V

0 V

0 V

13

V

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

A

1 MR

2 Vo1

3 Vo2

4 GND

VDD 8

Vi1 7

Vi2 6

CD 5

V

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Dec 19, 2014

Page 9 of 11

RNA52A10MM

Regulations for state of capacitor C

D

electrical discharge and delay time

(1) Operation to MR input signal

MR

CD

Vth+

Vth-

TDLY

Capacitor incomplete electrical discharge

Vth-

Capacitor complete electrical discharge

Vth+

0V

TDLY0

Vo2

(2) Operation to Vi2 input signal

V

REF

+V

HYS

Vi2

V

REF

V

REF

V

REF

+V

HYS

CD

Vth+

Vth-

TDLY

Capacitor incomplete electrical discharge

Vth-

Capacitor complete electrical discharge

Vth+

0V

TDLY0

Vo2

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Dec 19, 2014

Page 10 of 11

RNA52A10MM

Relation between Delay Time T

DLY

and External Component Values C

D,

R

D

1000

100

10

C D

= 1.0

μF

μF

C

D

= 0.33

C D

= 0.1

μF

μF

C

D

= 0.033

C

D

= 0.01

μF

1

1 10

Resistance R

D

[kΩ]

100

Package Dimensions

Package Name

MMPAK-8

JEITA Package Code

P-LSOP8-2.8 x 2.95 - 0.65

RENESAS Code

PLSP0008JC-A

2.95

± 0.2

Previous Code

MASS[Typ.]

0.02 g

0.13

+0.12

-0.03

1000

Unit: mm

0 to 0.1

R03DS0091EJ0600 Rev.6.00

Dec 19, 2014

0.1

0.65

1.95

0.1

M

0.2

+0.1

-0.05

Page 11 of 11

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

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Renesas Electronics Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K

Tel: +44-1628-585-100, Fax: +44-1628-585-900

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, Germany

Tel: +49-211-6503-0, Fax: +49-211-6503-1327

Renesas Electronics (China) Co., Ltd.

Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China

Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

Renesas Electronics (Shanghai) Co., Ltd.

Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333

Tel: +86-21-2226-0888, Fax: +86-21-2226-0999

Renesas Electronics Hong Kong Limited

Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2265-6688, Fax: +852 2886-9022/9044

Renesas Electronics Taiwan Co., Ltd.

13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan

Tel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.

80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949

Tel: +65-6213-0200, Fax: +65-6213-0300

Renesas Electronics Malaysia Sdn.Bhd.

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas Electronics Korea Co., Ltd.

12F., 234 Teheran-ro, Gangnam-Ku, Seoul, 135-920, Korea

Tel: +82-2-558-3737, Fax: +82-2-558-5141 http://www.renesas.com

© 2014 Renesas Electronics Corporation. All rights reserved.

Colophon 4.0

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