I/O Features in Stratix IV Devices

I/O Features in Stratix IV Devices
6. I/O Features in Stratix IV Devices
September 2012
SIV51006-3.4
SIV51006-3.4
This chapter describes how Stratix IV devices provide I/O capabilities that allow
you to work in compliance with current and emerging I/O standards and
requirements. With these device features, you can reduce board design interface costs
and increase development flexibility.
Altera Stratix IV FPGAs deliver a breakthrough level of system bandwidth and
power efficiency for high-end applications, allowing you to innovate without
compromise. Stratix IV I/Os are specifically designed for ease-of-use and rapid
system integration while simultaneously providing the high bandwidth required to
maximize internal logic capabilities and produce system-level performance.
Stratix IV device I/O capability far exceeds the I/O bandwidth available from
previous generation FPGAs. Independent modular I/O banks with a common bank
structure for vertical migration lend efficiency and flexibility to the high-speed I/O.
Package and die enhancements with dynamic termination and output control provide
best-in-class signal integrity. Numerous I/O features assist high-speed data transfer
into and out of the device, including:
■
Up to 32 full-duplex clock data recovery (CDR)-based transceivers supporting
data rates between 600 Mbps and 8.5 Gbps
■
Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express® (PIPE) (PCIe) Gen1 and Gen2, Gigabit Ethernet
(GbE), Serial RapidIO®, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G,
SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken
■
Complete PCIe protocol solution with embedded PCIe hard IP blocks that
implement PHY-MAC layer, data link layer, and transaction layer functionality
■
Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
■
Low-voltage differential signaling (LVDS), reduced swing differential signaling
(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTL
■
Single data rate (SDR) and half data rate (HDR—half frequency and twice data
width of SDR) input and output options
■
Up to 132 full duplex 1.6 Gbps true LVDS channels (132 Tx + 132 Rx) on the row
I/O banks
■
Hard dynamic phase alignment (DPA) block with serializer/deserializer
(SERDES)
■
Deskew, read and write leveling, and clock-domain crossing functionality
■
Programmable output current strength
■
Programmable slew rate
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described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
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ISO
9001:2008
Registered
Stratix IV Device Handbook
Volume 1
September 2012
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6–2
Chapter 6: I/O Features in Stratix IV Devices
I/O Standards Support
■
Programmable delay
■
Programmable bus-hold circuit
■
Programmable pull-up resistor
■
Open-drain output
■
Serial, parallel, and dynamic on-chip termination (OCT)
■
Differential OCT
■
Programmable pre-emphasis
■
Programmable equalization
■
Programmable differential output voltage (VOD)
This chapter contains the following sections:
■
“I/O Standards Support”
■
“I/O Banks” on page 6–5
■
“I/O Structure” on page 6–17
■
“On-Chip Termination Support and I/O Termination Schemes” on page 6–24
■
“OCT Calibration” on page 6–32
■
“Termination Schemes for I/O Standards” on page 6–38
■
“Design Considerations” on page 6–46
I/O Standards Support
Stratix IV devices support a wide range of industry I/O standards. Table 6–1 lists the
I/O standards Stratix IV devices support, as well as the typical applications. These
devices support VCCIO voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 V.
Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 1 of 2)
I/O Standard
3.3-V LVTTL/LVCMOS
Stratix IV Device Handbook
Volume 1
(1), (2)
Application
General purpose
2.5-V LVCMOS
General purpose
1.8-V LVCMOS
General purpose
1.5-V LVCMOS
General purpose
1.2-V LVCMOS
General purpose
3.0-V PCI/PCI-X
PC and embedded system
SSTL-2 Class I and II
DDR SDRAM
SSTL-18 Class I and II
DDR2 SDRAM
SSTL-15 Class I and II
DDR3 SDRAM
HSTL-18 Class I and II
QDRII/RLDRAM II
HSTL-15 Class I and II
QDRII/QDRII+/RLDRAM II
HSTL-12 Class I and II
General purpose
Differential SSTL-2 Class I and II
DDR SDRAM
Differential SSTL-18 Class I and II
DDR2 SDRAM
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Standards Support
6–3
Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 2 of 2)
I/O Standard
Application
Differential SSTL-15 Class I and II
DDR3 SDRAM
Differential HSTL-18 Class I and II
Clock interfaces
Differential HSTL-15 Class I and II
Clock interfaces
Differential HSTL-12 Class I and II
Clock interfaces
LVDS
High-speed communications
RSDS
Flat panel display
mini-LVDS
Flat panel display
LVPECL
Video graphics and clock distribution
Notes to Table 6–1:
(1) The 3.3-V LVTTL/LVCMOS standard is supported using VCCIO at 3.0 V.
(2) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to “3.3-V I/O
Interface” on page 6–19.
f For more information about transceiver supported I/O standards, refer to the
Transceiver Architecture in Stratix IV Devices chapter.
I/O Standards and Voltage Levels
Stratix IV devices support a wide range of industry I/O standards, including
single-ended, voltage-referenced single-ended, and differential I/O standards.
Table 6–2 lists the supported I/O standards and typical values for input and output
VCCIO, VCCPD, VREF, and board VTT.
Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices (1) (Part 1 of 3)
VCCIO (V)
I/O Standard
Standard
Support
Input Operation
Column
Row
I/O Banks I/O Banks
3.3-V LVTTL
(3)
3.3-V LVCMOS
2.5-V LVCMOS
Output Operation
Column
I/O Banks
Row
I/O Banks
VTT (V)
VCCPD (V)
VREF (V)
(Board
(Pre-Driver (Input Ref
Termination
Voltage)
Voltage)
Voltage)
JESD8-B
3.0/2.5
3.0/2.5
3.0
3.0
3.0
—
—
JESD8-B
3.0/2.5
3.0/2.5
3.0
3.0
3.0
—
—
JESD8-5
3.0/2.5
3.0/2.5
2.5
2.5
2.5
—
—
1.8-V LVCMOS
JESD8-7
1.8/1.5
1.8/1.5
1.8
1.8
2.5
—
—
1.5-V LVCMOS
JESD8-11
1.8/1.5
1.8/1.5
1.5
1.5
2.5
—
—
1.2-V LVCMOS
JESD8-12
1.2
1.2
1.2
1.2
2.5
—
—
3.0-V PCI
PCI
Rev 2.1
3.0
3.0
3.0
3.0
3.0
—
—
3.0-V PCI-X
PCI-X
Rev 1.0
3.0
3.0
3.0
3.0
3.0
—
—
JESD8-9B
(2)
(2)
2.5
2.5
2.5
1.25
1.25
SSTL-2 Class II
JESD8-9B
(2)
(2)
2.5
2.5
2.5
1.25
1.25
SSTL-18 Class I
JESD8-15
(2)
(2)
1.8
1.8
2.5
0.90
0.90
SSTL-18 Class II
JESD8-15
(2)
(2)
1.8
1.8
2.5
0.90
0.90
SSTL-2 Class I
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–4
Chapter 6: I/O Features in Stratix IV Devices
I/O Standards Support
Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices (1) (Part 2 of 3)
VCCIO (V)
I/O Standard
Standard
Support
Input Operation
Column
Row
I/O Banks I/O Banks
Output Operation
Column
I/O Banks
Row
I/O Banks
VTT (V)
VCCPD (V)
VREF (V)
(Board
(Pre-Driver (Input Ref
Termination
Voltage)
Voltage)
Voltage)
—
(2)
(2)
1.5
1.5
2.5
0.75
0.75
—
(2)
(2)
1.5
—
2.5
0.75
0.75
JESD8-6
(2)
(2)
1.8
1.8
2.5
0.90
0.90
JESD8-6
(2)
(2)
1.8
1.8
2.5
0.90
0.90
JESD8-6
(2)
(2)
1.5
1.5
2.5
0.75
0.75
HSTL-15 Class II
JESD8-6
(2)
(2)
1.5
—
2.5
0.75
0.75
HSTL-12 Class I
JESD8-16A
(2)
(2)
1.2
1.2
2.5
0.6
0.6
HSTL-12 Class II
JESD8-16A
(2)
(2)
1.2
—
2.5
0.6
0.6
Differential SSTL-2
Class I
JESD8-9B
(2)
(2)
2.5
2.5
2.5
—
1.25
Differential SSTL-2
Class II
JESD8-9B
(2)
(2)
2.5
2.5
2.5
—
1.25
Differential
SSTL-18 Class I
JESD8-15
(2)
(2)
1.8
1.8
2.5
—
0.90
Differential
SSTL-18 Class II
JESD8-15
(2)
(2)
1.8
1.8
2.5
—
0.90
Differential
SSTL-15 Class I
—
(2)
(2)
1.5
1.5
2.5
—
0.75
Differential
SSTL-15 Class II
—
(2)
(2)
1.5
—
2.5
—
0.75
Differential
HSTL-18 Class I
JESD8-6
(2)
(2)
1.8
1.8
2.5
—
0.90
Differential
HSTL-18 Class II
JESD8-6
(2)
(2)
1.8
1.8
2.5
—
0.90
Differential
HSTL-15 Class I
JESD8-6
(2)
(2)
1.5
1.5
2.5
—
0.75
Differential
HSTL-15 Class II
JESD8-6
(2)
(2)
1.5
—
2.5
—
0.75
Differential
HSTL-12 Class I
JESD8-16A
(2)
(2)
1.2
1.2
2.5
—
0.60
Differential
HSTL-12 Class II
JESD8-16A
(2)
(2)
1.2
—
2.5
—
0.60
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
LVDS
(4), (5), (8)
ANSI/TIA/
EIA-644
(2)
(2)
2.5
2.5
2.5
—
—
RSDS
(6), (7), (8)
—
(2)
(2)
2.5
2.5
2.5
—
—
—
(2)
(2)
2.5
2.5
2.5
—
—
mini-LVDS
(6), (7),
(8)
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–5
Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices (1) (Part 3 of 3)
VCCIO (V)
I/O Standard
Standard
Support
Input Operation
Column
Row
I/O Banks I/O Banks
LVPECL
—
(4)
2.5
Output Operation
Column
I/O Banks
Row
I/O Banks
—
—
VTT (V)
VCCPD (V)
VREF (V)
(Board
(Pre-Driver (Input Ref
Termination
Voltage)
Voltage)
Voltage)
2.5
—
—
Notes to Table 6–2:
(1) VCCPD is either 2.5 or 3.0 V. For VCCIO = 3.0 V, VCCPD = 3.0 V. For VCCIO = 2.5 V or less, VCCPD = 2.5 V.
(2) Single-ended HSTL/SSTL, differential SSTL/HSTL, and LVDS input buffers are powered by VCCPD. Row I/O banks support both true differential
input buffers and true differential output buffers. Column I/O banks support true differential input buffers, but not true differential output buffers.
I/O pins are organized in pairs to support differential standards. Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers
without on-chip RD support.
(3) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to “3.3-V I/O Interface” on page 6–19.
(4) Column I/O banks support LVPECL I/O standards for input clock operation. Clock inputs on column I/Os are powered by VCCCLKIN when configured
as differential clock inputs. They are powered by VCCIO when configured as single-ended clock inputs. Differential clock inputs in row I/Os are
powered by VCCPD.
(5) Column and row I/O banks support LVDS outputs using two single-ended output buffers, an external one-resistor (LVDS_E_1R), and a
three-resistor (LVDS_E_3R) network.
(6) Row I/O banks support RSDS and mini-LVDS I/O standards using a true LVDS output buffer without a resistor network.
(7) Column and row I/O banks support RSDS and mini-LVDS I/O standards using two single-ended output buffers with one-resistor (RSDS_E_1R
and mini-LVDS_E_1R) and three-resistor (RSDS_E_3R and mini-LVDS_E_3R) networks.
(8) The emulated differential output standard that supports the tri-state feature includes: LVDS_E_1R, LVDS_E_3R, RSDS_E_1R, RSDS_E_3R,
Mini_LVDS_E_1R, and Mini_LVDS_E_3R. For more information, refer to the I/O Buffer (ALTIOBUF) Megafunction User Guide.
f For more information about the electrical characteristics of each I/O standard, refer to
the DC and Switching Characteristics for Stratix IV Devices chapter.
I/O Banks
Stratix IV devices contain up to 24 I/O banks, as shown in Figure 6–1 and Figure 6–2.
The row I/O banks contain true differential input and output buffers and dedicated
circuitry to support differential standards at speeds up to 1.6 Gbps.
Each I/O bank in Stratix IV devices can support high-performance external memory
interfaces with dedicated circuitry. The I/O pins are organized in pairs to support
differential standards. Each I/O pin pair can support both differential input and
output buffers. The only exceptions are the clk[1,3,8,10], PLL_L[1,4]_clk, and
PLL_R[1,4]_clk pins, which support differential input operations only.
f For information about the number of channels available for the LVDS I/O standard,
refer to the High-Speed Differential I/O Interface and DPA in Stratix IV Devices chapter.
For more information about transceiver-bank-related features, refer to the Transceiver
Architecture in Stratix IV Devices chapter.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–6
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
Bank 1A
Bank 8A
Bank 8B
(1), (2), (3), (4), (5), (6), (7), (8)
Bank 8C
Bank 7B
Bank 7C
I/O banks 8A, 8B, and 8C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 7A
Bank 6C
Bank 5C
Bank 2C
LVPECL I/O standard for input operation on dedicated
clock input pins.
Bank 2B
SSTL-15 Class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15
Class II, differential HSTL-12 Class II standards are
only supported for input operations.
I/O banks 4A, 4B, and 4C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 2A
I/O banks 3A, 3B, and 3C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 3A
Bank 3B
Bank 3C
Bank 4C
Bank 4B
Bank 5B
Bank 1C
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I, and differential HSTL-12
Class I standards for input and output operations.
Bank 5A
Bank 1B
Bank 6B
I/O banks 7A, 7B, and 7C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 6A
Figure 6–1. Stratix IV E Devices I/0 Banks
Bank 4A
Notes to Figure 6–1:
(1) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
inverted.
(2) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support.
(3) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(4) Column I/O supports PCI/PCI-X with on-chip clamp diode. Row I/O supports PCI/PCI-X with external clamp diode.
(5) Clock inputs on column I/Os are powered by VCCCLKIN when configured as differential clock inputs. They are powered by VCCIO when configured as
single-ended clock inputs. All outputs use the corresponding bank VCCIO.
(6) Row I/O supports the true LVDS output buffer.
(7) Column and row I/O banks support LVPECL standards for input clock operation.
(8) Figure 6–1 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–7
Bank 3A
Bank 3B
Bank 3C
Bank 4C
Bank 4B
Transceiver Bank
GXBR2
Bank 6C
Bank5C
I/O banks 4A, 4B & 4C support all
single-ended and differential input
and output operation.
I/O banks 3A, 3B & 3C support all
single-ended and differential input
and output operation.
Bank 5A
Bank 2B
Bank 5B
Bank 2C
Bank 1C
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8V, 1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I
& II, SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15
Class I, HSTL-12 Class I, LVDS, RSDS, mini-LVDS,
differential SSTL-2 Class I & II, differential SSTL-18
Class I & II, differential SSTL-15 Class I, differential
HSTL-18 Class I & II, differential HSTL-15 Class I and
differential HSTL-12 Class I standards for input and
output operation.
SSTL-15 class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15
Class II, differential HSTL-12 Class II standards are
only supported for input operations
Transceiver Bank
GXBR1
Bank 6B
Bank 1B
I/O banks 7A, 7B & 7C support all
single-ended and differential input
and output operation.
Transceiver Bank
GXBR3
Bank 7A
Transceiver Bank
GXBR0
Bank 1A
Bank 7B
Bank 7C
I/O banks 8A, 8B & 8C support all
single-ended and differential input
and output operation.
Bank 2A
Transceiver Bank
GXBL3
Transceiver Bank
GXBL2
Transceiver Bank
GXBL1
Transceiver Bank
GXBL0
Bank 8C
Bank 8B
Bank 8A
(1), (2), (3), (4), (5), (6), (7), (8), (9)
Bank 6A
Figure 6–2. Stratix IV GX Devices I/O Banks
Bank 4A
Notes to Figure 6–2:
(1) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
inverted.
(2) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support.
(3) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(4) Column I/O supports PCI/PCI-X with an on-chip clamp diode. Row I/O supports PCI/PCI-X with an external clamp diode.
(5) Clock inputs on column I/Os are powered by VCCCLKIN when configured as differential clock inputs. They are powered by VCCIO when configured as
single-ended clock inputs. All outputs use the corresponding bank VCCIO.
(6) Row I/O supports the true LVDS output buffer.
(7) Column and row I/O banks support LVPECL standards for input clock operation.
(8) Figure 6–2 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
(9) Stratix IV devices do not support the PCI clamp diode when VCCIO is 1.2 V, 1.5 V, or 1.8 V.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–8
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
Modular I/O Banks
The I/O pins in Stratix IV devices are arranged in groups called modular I/O banks.
Depending on device densities, the number of Stratix IV device I/O banks range from
16 to 24. The number of I/O pins on each bank is 24, 32, 36, 40, or 48. Figure 6–4
through Figure 6–16 show the number of I/O pins available in each I/O bank.
In Stratix IV devices, the maximum number of I/O banks per side is either four or six,
depending on the device density. When migrating between devices with a different
number of I/O banks per side, it is the middle or “B” bank that is removed or
inserted. For example, when moving from a 24-bank device to a 16-bank device, the
banks that are dropped are “B” banks, namely: 1B, 2B, 3B, 4B, 5B, 6B, 7B, and 8B.
Similarly, when moving from a 16-bank device to a 24-bank device, the banks that are
added are the same “B” banks.
After migration from a smaller device to a larger device, the bank size increases or
remains the same, but never decreases. For example, the number of I/O pins to a bank
may increase from 24 to 26, 32, 36, 40, 42, or 48, but will never decrease. This is shown
in Figure 6–3.
Figure 6–3. Bank Migration Path with Increasing Device Size
24
Stratix IV Device Handbook
Volume 1
26
32
36
40
42
48
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–9
Figure 6–4 through Figure 6–16 show the number of I/O pins and packaging
information for different sets of available devices. They show the top view of the
silicon die that corresponds to a reverse view for flip chip packages. They are
graphical representations only.
1
For Figure 6–4 through Figure 6–16, the pin count includes all general purpose I/Os,
dedicated clock pins, and dual purpose configuration pins. Transceiver pins and
dedicated configuration pins are not included in the pin count.
40
Bank 2C
Bank 5C
26
Bank 2A
Bank 5A
32
40
Bank 4A
Bank
Name
Number
of I/Os
40
32
Bank 7A
26
Bank 4C
26
24
Bank 6C
EP4SE230
EP4SE360
24
Bank 1C
Bank 7C
32
Bank 3C
26
24
Bank 6A
24
Bank 1A
Bank 3A
32
Bank 8C
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–4. Number of I/Os in Each Bank in EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package
24
32
32
24
40
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Altera Corporation
Bank 7A
Bank 4A
40
40
September 2012
Bank 4B
Bank 2A
24
48
Bank 4C
Bank 2C
32
42
EP4SE360
EP4SE530
EP4SE820
Bank 3C
Bank 1C
32
42
Bank 3B
Bank 1A
Bank 3A
48
24
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–5. Number of I/Os in Each Bank in EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin FineLine BGA
Package
Bank 6A
48
Bank 6C
42
Bank 5C
42
Bank 5A
48
Bank
Name
Number
of I/Os
Stratix IV Device Handbook
Volume 1
6–10
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
48
32
32
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–6. Number of I/Os in Each Bank in EP4SE530 and EP4SE820 Devices in the 1517-Pin FineLine BGA Package
50
Bank 1A
Bank 6A
50
24
Bank 1B
Bank 6B
24
42
Bank 1C
Bank 6C
42
42
Bank 2C
Bank 5C
42
24
Bank 2B
Bank 5B
24
50
Bank 2A
Bank 5A
50
48 Bank 4A
48 Bank 4B
32 Bank 4C
32 Bank 3C
48 Bank 3B
48 Bank 3A
EP4SE530
EP4SE820
Bank
Name
Number
of I/Os
48
48
48
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–7. Number of I/Os in Each Bank in EP4SE530 and EP4SE820 Devices in the 1760-Pin Fineline BGA Package
50
Bank 1A
Bank 6A
50
36
Bank 1B
Bank 6B
36
50
Bank 1C
Bank 6C
50
50
Bank 2C
Bank 5C
50
36
Bank 2B
Bank 5B
36
50
Bank 2A
Bank 5A
50
Stratix IV Device Handbook
Volume 1
48 Bank 4A
48 Bank 4B
48 Bank 4C
48 Bank 3C
48 Bank 3B
48 Bank 3A
EP4SE530
EP4SE820
Bank
Name
Number
of I/Os
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–11
40
Bank
GXBR1
Bank 2A
24
24
40
Bank 7C
Bank 7A
Number of
Transceiver
Channels
4
Bank
GXBR0
32
Bank 4A
Bank 2C
40
26
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
Bank 4C
Bank 1C
24
26
Bank 3C
Bank 1A
Bank 3A
32
24
Bank
Name
Bank 8A
40
Number
of I/Os
Bank 8C
Figure 6–8. Number of I/Os in Each Bank in EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin
FineLine BGA Package
4
Bank
Name
Number
of I/Os
Altera Corporation
32
40
Bank 7C
Bank 7A
Bank 4C
Bank 4A
32
40
Bank
GXBL0
Bank 3C
4
Number of
Transceiver
Channels
Bank
GXBR1
4
Bank
GXBR0
4
EP4SGX290
EP4SGX360
32
Bank
GXBL1
Bank 3A
4
Number of
Transceiver
Channels
September 2012
32
Bank
1C
40
1
Bank 8C
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–9. Number of I/Os in Each Bank in EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA Package
Bank
Name
Number
of I/Os
Stratix IV Device Handbook
Volume 1
6–12
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
Bank
GXBL0
24
24
40
Bank 7C
Bank 7A
40
*Number of
Transceiver
Channels
Bank 4A
4*
Bank 6A
32
Bank 6C
26
Bank
GXBR1
4*
Bank
GXBR0
4*
Bank
Name
Number
of I/Os
40
Bank
GXBL1
Bank 4C
4*
EP4SGX70
EP4SGX110
24
Bank 1C
Bank 3C
26
24
Bank 1A
Bank 3A
32
Bank 8C
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–10. Number of I/Os in Each Bank in EP4SGX70 and EP4SGX110 Devices in the 1152-Pin FineLine BGA Package
32
32
24
40
Bank 8C
Bank 7C
Bank 7B
Bank 7A
24
Bank 8B
Bank 4B
Bank 4A
40
40
24
Bank
GXBL0
Bank 4C
4 (2)
32
4 (2)
Bank
GXBL1
Bank 3C
Bank 1C
32
42
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
Bank 3B
Bank 1A
Bank 3A
48
24
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–11. Number of I/Os in Each Bank in EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1152-Pin FineLine BGA Package (1), (2)
Bank 6A
48
Bank 6C
42
Bank
GXBR1
4 (2)
Bank
GXBR0
4 (2)
Bank
Name
Number
of I/Os
Notes to Figure 6–11:
(1) Except for the EP4SGX530 device, all listed devices have two variants in the F1152 package option—one with no PMA-only transceiver channels
and the other with two PMA-only transceiver channels for each transceiver bank. The EP4SGX530 device is only offered with two PMA-only
transceiver channels for each transceiver bank in the F1152 package option.
(2) There are two additional PMA-only transceiver channels in each transceiver bank for devices with the PMA-only transceiver package option.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–13
24
32
32
24
40
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–12. Number of I/Os in Each Bank in EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1517-Pin FineLine BGA Package (1)
48
Bank 1A
Bank 6A
48
42
Bank 1C
Bank 6C
42
42
Bank 2C
Bank 5C
42
48
Bank 2A
Bank 5A
48
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
Bank
GXBR1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR0
4 (1)
40
24
32
32
24
40
Bank 4A
Bank
GXBL1
Bank 4B
4 (1)
Bank 4C
4 (1)
Bank 3C
Bank
GXBR2
Bank 3B
Bank
GXBL2
Bank 3A
4 (1)
Bank
Name
Number
of I/Os
Note to Figure 6–12:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–14
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
48
32
32
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–13. Number of I/Os in Each Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine
BGA Package (1)
50
Bank 1A
Bank 6A
50
42
Bank 1C
Bank 6C
42
42
Bank 2C
Bank 5C
42
20
Bank 2B
Bank 5B
20
50
Bank 2A
Bank 5A
50
4 (1)
Bank
GXBL3
Bank
GXBR3
4 (1)
4 (1)
Bank
GXBL2
Bank
GXBR2
4 (1)
4 (1)
Bank
GXBL1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR1
Bank
GXBR0
48 Bank 4A
48 Bank 4B
32 Bank 4C
32 Bank 3C
48 Bank 3B
48 Bank 3A
EP4SGX530
EP4SGX290
EP4SGX360
4 (1)
Bank
Name
Number
of I/Os
Note to Figure 6–13:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–15
48
32
32
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–14. Number of I/Os in Each Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin FineLine
BGA Package (1)
50
Bank 1A
Bank 6A
50
42
Bank 1C
Bank 6C
42
42
Bank 2C
Bank 5C
42
Bank 5A
50
50
EP4SGX290
EP4SGX360
EP4SGX530
Bank 2A
Bank
GXBR1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR0
4 (1)
48
48
32
32
48
48
Bank 4A
Bank
GXBL1
Bank 4B
4 (1)
Bank 4C
4 (1)
Bank 3C
Bank
GXBR2
Bank 3B
Bank
GXBL2
Bank 3A
4 (1)
Bank
Name
Number
of I/Os
Note to Figure 6–14:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–16
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
1
The information in Figure 6–15 and Figure 6–16 applies to Stratix IV GX and GT
devices.
48
32
32
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–15. Number of I/Os in Each Bank in EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin FineLine
BGA Package (1)
40
Bank 1A
Bank 6A
38
21
Bank 1C
Bank 6C
22
21
Bank 2C
Bank 5C
19
13
Bank 2B
Bank 5B
12
41
Bank 2A
Bank 5A
42
4 (1)
Bank
GXBL2
Bank
GXBR2
4 (1)
4 (1)
Bank
GXBL1
Bank
GXBR1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR0
4 (1)
Bank 4A
48
Bank 4B
48
Bank 4C
32
Bank 3C
32
Bank 3B
48
48
Bank 3A
EP4S100G3
EP4S100G4
EP4S100G5
Bank
Name
Number
of I/Os
Note to Figure 6–15:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–17
24
32
32
24
40
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–16. Number of I/Os in Each Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin
FineLine BGA Package (1)
43
Bank 1A
Bank 6A
44
22
Bank 1C
Bank 6C
23
23
Bank 2C
Bank 5C
23
46
Bank 2A
Bank 5A
46
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G5
Bank
GXBR1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR0
4 (1)
40
24
32
32
24
40
Bank 4A
Bank
GXBL1
Bank 4B
4 (1)
Bank 4C
4 (1)
Bank 3C
Bank
GXBR2
Bank 3B
Bank
GXBL2
Bank 3A
4 (1)
Bank
Name
Number
of I/Os
Note to Figure 6–16:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
I/O Structure
The I/O element (IOE) in Stratix IV devices contain a bidirectional I/O buffer and I/O
registers to support a complete embedded bidirectional single data rate or DDR
transfer. The IOEs are located in I/O blocks around the periphery of the Stratix IV
device. There are up to four IOEs per row I/O block and four IOEs per column I/O
block. The row IOEs drive row, column, or direct link interconnects. The column IOEs
drive column interconnects.
The Stratix IV bidirectional IOE also supports the following features:
September 2012
■
Programmable input delay
■
Programmable output-current strength
■
Programmable slew rate
■
Programmable output delay
■
Programmable bus-hold
■
Programmable pull-up resistor
■
Open-drain output
■
On-chip series termination with calibration
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–18
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
■
On-chip series termination without calibration
■
On-chip parallel termination with calibration
■
On-chip differential termination
■
PCI clamping diode
I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output-enable
(OE) path for handling the OE signal to the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. The input
path consists of the DDR input registers, alignment and synchronization registers,
and HDR. You can bypass each block of the input path.
The output and OE paths are divided into output or OE registers, alignment registers,
and HDR blocks. You can bypass each block of the output and OE paths.
Figure 6–17 shows the Stratix IV IOE structure.
Figure 6–17. IOE Structure in Stratix IV Devices (1),
(2), (3), (4)
Firm Core
DQS Logic Block
OE Register
D
OE
from
Core
2
Half Data
Rate Block
D6_OCT
D5_OCT
PRN
Q
Dynamic OCT Control (2)
Alignment
Registers
OE Register
D
VCCIO
D5, D6
Delay
PRN
Q
VCCIO
PCI Clamp
Programmable
Pull-Up Resistor
Programmable
Current
Strength and
Slew Rate
Control
Output Register
Write
Data
from
Core
Half Data
Rate Block
4
Alignment
Registers
PRN
D
Q
From OCT
Calibration
Block
Output Buffer
D5, D6
Delay
Output Register
D
Open Drain
PRN
Q
D2 Delay
Input Buffer
D3_0
Delay
clkout
To
Core
D3_1
Delay
To
Core
Read
Data
to
Core
4
Half Data
Rate Block
Alignment and
Synchronization
Registers
D1
Delay
Bus-Hold
Circuit
Input Register
PRN
D
Q
Input Register
Input Register
PRN
D
DQS
CQn
On-Chip
Termination
PRN
Q
D
Q
D4 Delay
clkin
Notes to Figure 6–17:
(1) The following features are not supported by true differential standards: open drain or tri-state output,; programmable current strength and slew
rate control; PCI Clamp; programmable pull-up resistor; bus-hold circuit.
(2) The D3_0 and D3_1 delays have the same available settings in the Quartus® II software
(3) One dynamic OCT control is available per DQ/DQS group.
(4) Column I/O supports PCI/PCI-X with an on-chip clamp diode. Row I/O supports PCI/PCI-X with an external clamp diode.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–19
f For more information about I/O registers and how they are used for memory
applications, refer to the External Memory Interfaces in Stratix IV Devices chapter.
3.3-V I/O Interface
Stratix IV I/O buffers support 3.3-V I/O standards. You can use them as transmitters
or receivers in your system. The output high voltage (VOH), output low voltage (VOL),
input high voltage (VIH), and input low voltage (VIL) levels meet the 3.3-V I/O
standards specifications defined by EIA/JEDEC Standard JESD8-B with margin when
the Stratix IV VCCIO voltage is powered by 3.0 V.
To ensure device reliability and proper operation, when interfacing with a 3.3-V I/O
system using Stratix IV devices, ensure that you do not violate the absolute maximum
ratings of the devices. Altera recommends performing IBIS simulation to determine
that the overshoot and undershoot voltages are within the guidelines.
When using the Stratix IV device as a transmitter, you can use slow slew rate and
series termination to limit overshoot and undershoot at the I/O pins, but they are not
required. Transmission line effects that cause large voltage deviations at the receiver
are associated with an impedance mismatch between the driver and the transmission
lines. By matching the impedance of the driver to the characteristic impedance of the
transmission line, you can significantly reduce overshoot voltage. You can use a series
termination resistor placed physically close to the driver to match the total driver
impedance to the transmission line impedance. Stratix IV devices support series OCT
for all LVTTL and LVCMOS I/O standards in all I/O banks.
When using the Stratix IV device as a receiver, you can use a clamping diode (on-chip
or off-chip) to limit overshoot, though this is not required. Stratix IV devices provide
an optional on-chip PCI-clamping diode for column I/O pins. You can use this diode
to protect the I/O pins against overshoot voltage.
The 3.3-V I/O standard is supported using bank supply voltage (VCCIO) at 3.0 V. In
this method, the clamping diode (on-chip or off-chip), when enabled, can sufficiently
clamp overshoot voltage to within the DC and AC input voltage specifications. The
clamped voltage can be expressed as the sum of the supply voltage (VCCIO) and the
diode forward voltage.
f For more information about the absolute maximum rating and maximum allowed
overshoot during transitions, refer to the DC and Switching Characteristics for Stratix IV
Devices chapter.
External Memory Interfaces
In addition to the I/O registers in each IOE, Stratix IV devices also have dedicated
registers and phase-shift circuitry on all I/O banks for interfacing with external
memory interfaces.
f For more information about external memory interfaces, refer to the External Memory
Interfaces in Stratix IV Devices chapter.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–20
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
High-Speed Differential I/O with DPA Support
Stratix IV devices have the following dedicated circuitry for high-speed differential
I/O support:
■
Differential I/O buffer
■
Transmitter serializer
■
Receiver deserializer
■
Data realignment
■
Dynamic phase aligner (DPA)
■
Synchronizer (FIFO buffer)
■
Phase-locked loops (PLLs)
f For more information about DPA support, refer to the High-Speed Differential I/O
Interfaces and DPA in Stratix IV Devices chapter.
Programmable Current Strength
The output buffer for each Stratix IV device I/O pin has a programmable current
strength control for certain I/O standards. Use programmable current strength to
mitigate the effects of high signal attenuation due to a long transmission line or a
legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL standards have several
levels of current strength that you can control. Table 6–3 lists the programmable
current strength for Stratix IV devices.
Table 6–3. Programmable Current Strength (Part 1 of 2) (1),
I/O Standard
3.3-V LVTTL
Stratix IV Device Handbook
Volume 1
(2)
IOH / IOL Current Strength
Setting (mA) for
Column I/O Pins
IOH / IOL Current Strength
Setting (mA) for
Row I/O Pins
16, 12, 8, 4
12, 8, 4
3.3-V LVCMOS
16, 12, 8, 4
8, 4
2.5-V LVCMOS
16, 12, 8, 4
12, 8, 4
1.8-V LVCMOS
12, 10, 8, 6, 4, 2
8, 6, 4, 2
1.5-V LVCMOS
12, 10, 8, 6, 4, 2
8, 6, 4, 2
1.2-V LVCMOS
8, 6, 4, 2
4, 2
SSTL-2 Class I
12, 10, 8
12, 8
SSTL-2 Class II
16
16
SSTL-18 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
SSTL-18 Class II
16, 8
16, 8
SSTL-15 Class I
12, 10, 8, 6, 4
8, 6, 4
SSTL-15 Class II
16, 8
—
HSTL-18 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
HSTL-18 Class II
16
16
HSTL-15 Class I
12, 10, 8, 6, 4
8, 6, 4
HSTL-15 Class II
16
—
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–21
Table 6–3. Programmable Current Strength (Part 2 of 2) (1),
(2)
IOH / IOL Current Strength
Setting (mA) for
Column I/O Pins
IOH / IOL Current Strength
Setting (mA) for
Row I/O Pins
HSTL-12 Class I
12, 10, 8, 6, 4
8, 6, 4
HSTL-12 Class II
16
—
I/O Standard
Notes to Table 6–3:
(1) The default setting in the Quartus II software is 50-OCT RS without calibration for all non-voltage reference and
HSTL and SSTL Class I I/O standards. The default setting is 25-OCT RS without calibration for HSTL and SSTL
Class II I/O standards.
(2) The 3.3-V LVTTL and 3.3-V LVCMOS are supported using VCCIO and VCCPD at 3.0 V.
1
Altera recommends performing IBIS or SPICE simulations to determine the best
current strength setting for your specific application.
Programmable Slew Rate Control
The output buffer for each Stratix IV device regular- and dual-function I/O pin has a
programmable output slew-rate control that you can configure for low-noise or
high-speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. A slower slew rate can help reduce system noise, but adds
a nominal delay to the rising and falling edges. Each I/O pin has an individual
slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis.
1
You cannot use the programmable slew rate feature when using OCT.
The Quartus II software allows four settings for programmable slew rate control—0,
1, 2, and 3—where 0 is slow slew rate and 3 is fast slew rate. Figure 6–4 lists the
default slew rate settings from the Quartus II software.
Table 6–4. Default Slew Rate Settings
I/O Standard
Slew Rate Option
Default Slew Rate
1.2-V, 1.5-V, 1.8-V, 2.5-V LVCMOS, and 3.3-V LVTTL/LVCMOS
0, 1, 2, 3
3
SSTL-2, SSTL-18, SSTL-15, HSTL-18, HSTL-15, and HSTL-12
0, 1, 2, 3
3
3.0-V PCI/PCI-X
0, 1, 2, 3
3
LVDS_E_1R, mini-LVDS_E_1R, and RSDS_E_1R
0, 1, 2, 3
3
LVDS_E_3R, mini-LVDS_E_3R, and RSDS_E_3R
0, 1, 2, 3
3
You can use faster slew rates to improve the available timing margin in
memory-interface applications or when the output pin has high-capacitive loading.
1
September 2012
Altera recommends performing IBIS or SPICE simulations to determine the best slew
rate setting for your specific application.
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–22
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
Programmable I/O Delay
The following sections describe programmable IOE delay and programmable output
buffer delay.
Programmable IOE Delay
The Stratix IV device IOE includes programmable delays, shown in Figure 6–17 on
page 6–18, that you can activate to ensure zero hold times, minimize setup times, or
increase clock-to-output times. Each pin can have a different input delay from
pin-to-input register or a delay from output register-to-output pin values to ensure
that the bus has the same delay going into or out of the device. This feature helps read
and time margins because it minimizes the uncertainties between signals in the bus.
f For more information about programmable IOE delay specifications, refer to the
High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices chapter.
Programmable Output Buffer Delay
Stratix IV devices support delay chains built inside the single-ended output buffer, as
shown in Figure 6–17 on page 6–18. The delay chains can independently control the
rising and falling edge delays of the output buffer, providing the ability to adjust the
output-buffer duty cycle, compensate channel-to-channel skew, reduce simultaneous
switching output (SSO) noise by deliberately introducing channel-to-channel skew,
and improve high-speed memory-interface timing margins. Stratix IV devices
support four levels of output buffer delay settings. The default setting is No Delay.
f For more information about programmable output buffer delay specifications, refer to
the High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices chapter.
Open-Drain Output
Stratix IV devices provide an optional open-drain output (equivalent to an open
collector output) for each I/O pin. When configured as open drain, the logic value of
the output is either high-Z or 0. Typically, an external pull-up resistor is required to
provide logic high.
Bus Hold
Each Stratix IV device I/O pin provides an optional bus-hold feature. Bus-hold
circuitry can weakly hold the signal on an I/O pin at its last-driven state. Because the
bus-hold feature holds the last-driven state of the pin until the next input signal is
present, you do not need an external pull-up or pull-down resistor to hold a signal
level when the bus is tri-stated.
Bus-hold circuitry also pulls non-driven pins away from the input threshold voltage
where noise can cause unintended high-frequency switching. You can select this
feature individually for each I/O pin. The bus-hold output drives no higher than
VCCIO to prevent over-driving signals. If you enable the bus-hold feature, you cannot
use the programmable pull-up option. Disable the bus-hold feature if the I/O pin is
configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately
7 k to weakly pull the signal level to the last-driven state.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–23
f For more information about the specific sustaining current driven through this
resistor and the overdrive current used to identify the next-driven input level, refer to
the High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices chapter.
Bus-hold circuitry is active only after configuration. When going into user mode, the
bus-hold circuit captures the value on the pin present at the end of configuration.
Programmable Pull-Up Resistor
Each Stratix IV device I/O pin provides an optional programmable pull-up resistor
during user mode. If you enable this feature for an I/O pin, the pull-up resistor
(typically 25 K ) weakly holds the I/O to the VCCIO level.
Programmable pull-up resistors are only supported on user I/O pins and are not
supported on dedicated configuration pins, JTAG pins, or dedicated clock pins. If you
enable the programmable pull-up option, you cannot use the bus-hold feature.
1
When the optional DEV_OE signal drives low, all the I/O pins remain tri-stated even
with the programmable pull-up option enabled.
Programmable Pre-Emphasis
Stratix IV LVDS transmitters support programmable pre-emphasis to compensate for
the frequency dependent attenuation of the transmission line. The Quartus II software
allows four settings for programmable pre-emphasis.
f For more information about programmable pre-emphasis, refer to the High-Speed
Differential I/O Interfaces and DPA in Stratix IV Devices chapter.
Programmable Differential Output Voltage
Stratix IV LVDS transmitters support programmable VOD. The programmable VOD
settings allow you to adjust output eye height to optimize trace length and power
consumption. A higher VOD swing improves voltage margins at the receiver end; a
smaller VOD swing reduces power consumption. The Quartus II software allows four
settings for programmable VOD.
f For more information about programmable VOD, refer to the High-Speed Differential I/O
Interfaces and DPA in Stratix IV Devices chapter.
MultiVolt I/O Interface
The Stratix IV architecture supports the MultiVolt I/O interface feature that allows the
Stratix IV devices in all packages to interface with systems of different supply
voltages.
You can connect the VCCIO pins to a 1.2-, 1.5-, 1.8-, 2.5-, or 3.0-V power supply,
depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply. (For example, when VCCIO pins are
connected to a 1.5-V power supply, the output levels are compatible with 1.5-V
systems.)
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–24
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
f For more information about pin connection guidelines, refer to the Stratix IV GX and
Stratix IV E Device Family Pin Connection Guidelines.
The Stratix IV VCCPD power pins must be connected to a 2.5- or 3.0-V power supply.
Using these power pins to supply the pre-driver power to the output buffers increases
the performance of the output pins. Table 6–5 lists Stratix IV MultiVolt I/O support.
Table 6–5. Stratix IV MultiVolt I/O Support
(1)
Input Signal (V)
VCCIO (V)
Output Signal (V)
(3)
1.2
1.5
1.8
2.5
3.0
3.3
1.2
1.5
1.8
2.5
3.0
3.3
1.2
Y
—
—
—
—
1.5
—
Y
Y
—
—
—
Y
—
—
—
—
—
—
—
Y
—
—
—
—
1.8
—
Y
Y
—
—
—
—
—
Y
—
—
—
2.5
—
—
—
Y
Y (2)
Y (2)
—
—
—
Y
—
—
3.0
—
—
—
Y
Y
Y
—
—
—
—
Y
—
Notes to Table 6–5:
(1) The pin current may be slightly higher than the default value. You must verify that the driving device’s VOL maximum and VOH minimum voltages
do not violate the applicable Stratix IV VIL maximum and VIH minimum voltage specifications.
(2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3.0 V or 3.3 V. You have the option to use
an internal clamping diode for column I/O pins.
(3) Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one VCCIO, either 1.2, 1.5, 1.8, or 3.0 V. The LVDS I/O standard
is not supported when VCCIO is 3.0 V. The LVDS input operations are supported when VCCIO is 1.2 V, 1.5 V, 1.8 V, or 2.5 V. The LVDS output
operations are only supported when VCCIO is 2.5 V.
On-Chip Termination Support and I/O Termination Schemes
Stratix IV devices feature dynamic series and parallel OCT to provide I/O impedance
matching and termination capabilities. OCT maintains signal quality, saves board
space, and reduces external component costs.
Stratix IV devices support:
■
On-chip series termination (RS) with calibration
■
On-chip series termination (RS) without calibration
■
On-chip Parallel termination (RT) with calibration
■
Dynamic series termination for single-ended I/O standards
■
Dynamic Parallel termination for single-ended I/O standards
■
On-chip differential termination (RD) for differential LVDS I/O standards
Stratix IV devices support OCT in all I/O banks by selecting one of the OCT I/O
standards.
These devices also support OCT RS and RT in the same I/O bank for different I/O
standards if they use the same VCCIO supply voltage. You can independently configure
each I/O in an I/O bank to support OCT RS, programmable current strength, or OCT
RT.
1
Stratix IV Device Handbook
Volume 1
You cannot configure both OCT RS and programmable current strength for the same
I/O buffer.
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–25
A pair of RUP and RDN pins are available in a given I/O bank and are shared for
series- and parallel-calibrated termination. The RUP and RDN pins share the same VCCIO
and GND, respectively, with the I/O bank where they are located. The RUP and RDN
pins are dual-purpose I/Os and function as regular I/Os if you do not use the
calibration circuit.
For calibration, the connections are as follows:
■
The RUP pin is connected to VCCIO through an external 25- ±1% or 50- ±1%
resistor for an on-chip series termination value of 25-or 50-, respectively.
■
The RDN pin is connected to GND through an external 25- ±1% or 50- ±1%
resistor for an on-chip series termination value of 25-or 50-, respectively.
For on-chip parallel termination, the connections are as follows:
■
The RUP pin is connected to VCCIO through an external 50- ±1% resistor.
■
The RDN pin is connected to GND through an external 50- ±1% resistor.
On-Chip Series (RS) Termination Without Calibration
Stratix IV devices support driver-impedance matching to provide the I/O driver with
controlled output impedance that closely matches the impedance of the transmission
line. As a result, you can significantly reduce reflections. Stratix IV devices support
on-chip series termination for single-ended I/O standards (Figure 6–18).
The RS shown in Figure 6–18 is the intrinsic impedance of the output transistors.
Typical RS values are 25  and 50 . When you select matching impedance, current
strength is no longer selectable.
Figure 6–18. On-Chip Series Termination Without Calibration
Stratix IV Driver
Series Termination
Receiving
Device
VCCIO
RS
ZO = 50 Ω
RS
GND
To use on-chip termination for the SSTL Class I standard, you must select the 50-
on-chip series termination setting, thus eliminating the external 25- RS (to match
the 50- transmission line). For the SSTL Class II standard, you must select the 25-
on-chip series termination setting (to match the 50- transmission line and the
near-end external 50- pull-up to VTT).
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–26
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
On-Chip Series Termination with Calibration
Stratix IV devices support on-chip series termination with calibration in all banks. The
on-chip series termination calibration circuit compares the total impedance of the I/O
buffer to the external 25- ±1% or 50- ±1% resistors connected to the RUP and RDN
pins and dynamically enables or disables the transistors until they match.
The RS shown in Figure 6–19 is the intrinsic impedance of the transistors. Calibration
occurs at the end of device configuration. When the calibration circuit finds the
correct impedance, it powers down and stops changing the characteristics of the
drivers.
Figure 6–19. On-Chip Series Termination with Calibration
Stratix IV Driver
Series Termination
Receiving
Device
VCCIO
RS
ZO = 50 Ω
RS
GND
Table 6–6 lists the I/O standards that support on-chip series termination with and
without calibration.
Table 6–6. Selectable I/O Standards for On-Chip Series Termination with and Without Calibration
(Part 1 of 2)
On-Chip Series Termination Setting
I/O Standard
3.3-V LVTTL/LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
Stratix IV Device Handbook
Volume 1
Row I/O ()
Column I/O ()
50
50
25
25
50
50
25
25
50
50
25
25
50
1.5-V LVCMOS
50
1.2-V LVCMOS
50
SSTL-2 Class I
50
50
SSTL-2 Class II
25
25
SSTL-18 Class I
50
50
SSTL-18 Class II
25
25
25
50
25
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–27
Table 6–6. Selectable I/O Standards for On-Chip Series Termination with and Without Calibration
(Part 2 of 2)
On-Chip Series Termination Setting
I/O Standard
Row I/O ()
Column I/O ()
SSTL-15 Class I
50
50
SSTL-15 Class II
—
25
HSTL-18 Class I
50
50
HSTL-18 Class II
25
25
HSTL-15 Class I
50
50
HSTL-15 Class II
—
25
HSTL-12 Class I
50
50
HSTL-12 Class II
—
25
Left-Shift Series Termination Control
Stratix IV devices support left-shift series termination control. You can use left-shift
series termination control to get the calibrated OCT RS with half of the impedance
value of the external reference resistors connected to the RUP and RDN pins. This feature
is useful in applications that require both 25- and 50- calibrated OCT RS at the
same VCCIO. For example, if your application requires 25- and 50- calibrated OCT
RS for SSTL-2 Class I and Class II I/O standards, you only need one OCT calibration
block with 50- external reference resistors.
You can enable the left-shift series termination control feature in the ALTIOBUF
megafunction in the Quartus II software. The Quartus II software only allows
left-shift series termination control for 25- calibrated OCT RS with 50- external
reference resistors connected to the RUP and RDN pins. You can only use left-shift series
termination control for the I/O standards that support 25- calibrated OCT RS .
1
This feature is automatically enabled if you are using a bidirectional I/O with 25-
calibrated OCT RS and 50- parallel OCT.
f For more information about how to enable the left-shift series termination feature in
the ALTIOBUF megafunction, refer to the I/O Buffer (ALTIOBUF) Megafunction User
Guide.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–28
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
On-Chip Parallel Termination with Calibration
Stratix IV devices support on-chip parallel termination with calibration in all banks.
On-chip parallel termination with calibration is only supported for input
configuration of input and bidirectional pins. Output pin configurations do not
support on-chip parallel termination with calibration. Figure 6–20 shows on-chip
parallel termination with calibration. When you use parallel OCT, the VCCIO of the
bank must match the I/O standard of the pin where the parallel OCT is enabled.
Figure 6–20. On-Chip Parallel Termination with Calibration
Stratix IV OCT
VCCIO
100 Ω
ZO = 50 Ω
V
REF
100 Ω
GND
Transmitter
Receiver
The on-chip parallel termination calibration circuit compares the total impedance of
the I/O buffer to the external 50- ±1% resistors connected to the RUP and RDN pins
and dynamically enables or disables the transistors until they match. Calibration
occurs at the end of device configuration. When the calibration circuit finds the
correct impedance, it powers down and stops changing the characteristics of the
drivers. Table 6–7 lists the I/O standards that support on-chip parallel termination
with calibration.
Table 6–7. Selectable I/O Standards with On-Chip Parallel Termination with Calibration
I/O Standard
Stratix IV Device Handbook
Volume 1
On-Chip Parallel
Termination Setting
(Column I/O) ()
On-Chip Parallel
Termination Setting
(Row I/O) ()
SSTL-2 Class I, II
50
50
SSTL-18 Class I, II
50
50
SSTL-15 Class I, II
50
50
HSTL-18 Class I, II
50
50
HSTL-15 Class I, II
50
50
HSTL-12 Class I, II
50
50
Differential SSTL-2 Class I, II
50
50
Differential SSTL-18 Class I, II
50
50
Differential SSTL-15 Class I, II
50
50
Differential HSTL-18 Class I, II
50
50
Differential HSTL-15 Class I, II
50
50
Differential HSTL-12 Class I, II
50
50
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–29
Expanded On-Chip Series Termination with Calibration
OCT calibration circuits always adjust OCT RS to match the external resistors
connected to the RUP and RDN pin; however, it is possible to achieve OCT RS values
other than the 25- and 50- resistors. Theoretically, if you need a different OCT RS
value, you can change the resistance connected to the RUP and RDN pins accordingly.
Practically, the OCT RS range that Stratix IV devices support is limited because of
output buffer size and granularity limitations.
The Quartus II software only allows discrete OCT RS calibration settings of 25, 40, 50,
and 60  . You can select the closest discrete value of OCT RS with calibration settings
in the Quartus II software to your system to achieve the closest timing. For example, if
you are using 20- OCT RS with calibration in your system, you can select the 25-
OCT RS with calibration setting in the Quartus II software to achieve the closest
timing.
Table 6–8 lists expanded OCT RS with calibration supported in Stratix IV devices. Use
expanded on-chip series termination with calibration of SSTL and HSTL for
impedance matching to improve signal integrity but do not use it to meet the JEDEC
standard.
Table 6–8. Selectable I/O Standards with Expanded On-Chip Series Termination with Calibration
Range
Expanded OCT RS Range
I/O Standard
Row I/O ()
Column I/O ()
3.3-V LVTTL/LVCMOS
20–60
20–60
2.5-V LVTTL/LVCMOS
20–60
20–60
1.8-V LVTTL/LVCMOS
20–60
20–60
1.5-V LVTTL/LVCMOS
40–60
20–60
1.2-V LVTTL/LVCMOS
40–60
20–60
SSTL-2
20–60
20–60
SSTL-18
20–60
20–60
SSTL-15
40–60
20–60
HSTL-18
20–60
20–60
HSTL-15
40–60
20–60
HSTL-12
40–60
20–60
Dynamic On-Chip Termination
Stratix IV devices support on and off dynamic termination, both series and parallel,
for a bidirectional I/O in all I/O banks. Figure 6–21 shows the termination schemes
supported in Stratix IV devices. Dynamic parallel termination is enabled only when
the bidirectional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bidirectional I/O acts
as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bidirectional path because signal integrity is
optimized depending on the direction of the data.
Using dynamic OCT helps save power because device termination is internal instead
of external. Termination only switches on during input operation, thus drawing less
static power.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–30
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
1
When using calibrated input parallel and calibrated output series termination on
bidirectional pins, they must use the same termination value because each I/O pin
can only reference one OCT calibration block. The only exception is when using 50 
parallel OCT and 25  series OCT using the left shift series termination control. For
example, you cannot use calibrated 50  parallel OCT on the input buffer of a
bidirectional pin and calibrated 40  series OCT on the output buffer because these
would require two separate calibration blocks with different RUP and RDN resistor
values.
Figure 6–21. Dynamic Parallel OCT in Stratix IV Devices
VCCIO
VCCIO
Transmitter
Receiver
100 Ω
100 Ω
50 Ω
ZO = 50 Ω
100 Ω
100 Ω
50 Ω
GND
GND
Stratix IV OCT
Stratix IV OCT
VCCIO
VCCIO
100 Ω
100 Ω
50 Ω
ZO = 50 Ω
100 Ω
100 Ω
50 Ω
GND
GND
Transmitter
Receiver
Stratix IV OCT
Stratix IV OCT
f For more information about tolerance specifications for OCT with calibration, refer to
the DC and Switching Characteristics for Stratix IV Devices chapter.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–31
LVDS Input OCT (RD)
Stratix IV devices support OCT for differential LVDS input buffers with a nominal
resistance value of 100 , as shown in Figure 6–22. Differential OCT RD can be
enabled in row I/O banks when both the VCCIO and VCCPD is set to 2.5 V. Column I/O
banks do not support OCT RD. Dedicated clock input pairs CLK[1,3,8,10][p,n],
PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of Stratix IV
devices do not support RD termination.
Figure 6–22. Differential Input OCT
Transmitter
Receiver
ZO = 50 Ω
100 Ω
ZO = 50 Ω
f For more information about differential on-chip termination, refer to the High-Speed
Differential I/O Interfaces and DPA in Stratix IV Devices chapter.
Summary of OCT Assignments
Table 6–9 lists the OCT assignments for the Quartus II software version 9.1 and later.
Table 6–9. Summary of OCT Assignments in the Quartus II Software
Assignment Name
Value
Applies To
Parallel 50  with calibration
Input buffers for single-ended and
differential HSTL/SSTL standards
Differential
Input buffers for LVDS receivers on
row I/O banks (1)
Input Termination
Series 25  without
calibration
Series 50  without
calibration
Output Termination
Series 25  with calibration
Series 40  with calibration
Output buffers for single-ended
LVTTL/LVCMOS and HSTL/SSTL
standards as well as differential
HSTL/SSTL standards
Series 50  with calibration
Series 60  with calibration
Note to Table 6–9:
(1) You can enable differential OCT RD in row I/O banks when both VCCIO and VCCPD are set to 2.5 V.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–32
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
OCT Calibration
Stratix IV devices support calibrated on-chip series termination (RS) and calibrated
on-chip parallel termination (RT) on all I/O pins. You can calibrate the device’s I/O
bank with any of the OCT calibration blocks available in the device provided the
VCCIO of the I/O bank with the pins using calibrated OCT matches the VCCIO of the
I/O bank with the calibration block and its associated RUP and RDN pins.
OCT Calibration Block Location
Table 6–10 and Table 6–11 list the location of OCT calibration blocks in Stratix IV
devices. For both tables, the following legend applies:
1
■
“Y” indicates I/O banks with OCT calibration block
■
”N” indicates I/O banks without OCT calibration block
■
“—” indicates I/O banks that are not available in the device
Table 6–10 and Table 6–11 do not show transceiver banks and transceiver calibration
blocks.
Table 6–10 lists the OCT calibration blocks in Banks 1A through 4C.
Table 6–10. OCT Calibration Block Counts and Placement in Stratix IV Devices (1A through 4C) (Part 1 of 2)
Device
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
Stratix IV Device Handbook
Volume 1
Bank
Number of
OCT Blocks
1A
1B
1C
2A
2B
2C
3A
3B
3C
4A
4B
4C
780
8
Y
—
N
Y
—
N
Y
—
N
Y
—
N
780
8
Y
—
N
Y
—
N
Y
—
N
Y
—
N
1152
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1152
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1517
10
Y
N
N
Y
N
N
Y
N
Y
Y
N
N
1760
10
Y
N
N
Y
N
N
Y
N
Y
Y
N
N
1152
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1517
10
Y
N
N
Y
N
N
Y
N
Y
Y
N
N
1760
10
Y
N
N
Y
N
N
Y
N
Y
Y
N
N
780
8
Y
—
N
Y
—
N
Y
—
N
Y
—
N
780
8
Y
—
N
Y
—
N
Y
—
N
Y
—
N
1152
8
Y
—
N
—
—
—
Y
—
N
Y
—
N
780
8
Y
—
N
Y
—
N
Y
—
N
Y
—
N
1152
8
Y
—
N
—
—
—
Y
N
N
Y
N
N
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
780
8
Y
—
N
Y
—
N
Y
—
N
Y
—
N
1152
8
Y
—
N
—
—
—
Y
N
N
Y
N
N
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
Pin
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
6–33
Table 6–10. OCT Calibration Block Counts and Placement in Stratix IV Devices (1A through 4C) (Part 2 of 2)
Bank
Number of
OCT Blocks
1A
1B
1C
2A
2B
2C
3A
3B
3C
4A
4B
4C
780
8
—
—
—
—
—
—
Y
—
N
Y
—
N
1152
8
Y
—
N
—
—
—
Y
N
N
Y
N
N
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1760
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1932
10
Y
N
N
Y
—
N
Y
N
Y
Y
N
N
780
8
—
—
—
—
—
—
Y
—
N
Y
—
N
1152
8
Y
—
N
—
—
—
Y
N
N
Y
N
N
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1760
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1932
10
Y
N
N
Y
—
N
Y
N
Y
Y
N
N
1152
8
Y
—
N
—
—
—
Y
N
Y
Y
N
N
1517
10
Y
—
N
Y
—
N
Y
N
Y
Y
N
N
1760
10
Y
—
N
Y
—
N
Y
N
Y
Y
N
N
1932
10
Y
—
N
Y
N
N
Y
N
Y
Y
N
N
EP4S40G2
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
EP4S40G5
1517
10
Y
—
N
Y
—
N
Y
N
Y
Y
N
N
EP4S100G2
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
EP4S100G3
1932
10
Y
—
N
Y
N
N
Y
N
Y
Y
N
N
EP4S100G4
1932
10
Y
—
N
Y
N
N
Y
N
Y
Y
N
N
1517
10
Y
—
N
Y
—
N
Y
N
Y
Y
N
N
1932
10
Y
—
N
Y
N
N
Y
N
Y
Y
N
N
Device
EP4SGX290
EP4SGX360
EP4SGX530
EP4S100G5
Pin
Table 6–11 lists the OCT calibration blocks in Banks 5A through 8C.
Table 6–11. OCT Calibration Block Counts and Placement in Stratix IV Devices (5A through 8C) (Part 1 of 2)
Device
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4SGX70
September 2012
Bank
Number of
OCT Blocks
5A
5B
5C
6A
6B
6C
7A
7B
7C
8A
8B
8C
780
8
Y
—
N
Y
—
N
Y
—
N
Y
—
N
780
8
Y
—
N
Y
—
N
Y
—
N
Y
—
N
1152
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1152
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1517
10
Y
N
N
Y
N
N
Y
N
N
Y
N
Y
1760
10
Y
N
N
Y
N
N
Y
N
N
Y
N
Y
1152
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1517
10
Y
N
N
Y
N
N
Y
N
N
Y
N
Y
1760
10
Y
N
N
Y
N
N
Y
N
N
Y
N
Y
780
8
—
—
—
—
—
—
Y
—
N
Y
—
N
Pin
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–34
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
Table 6–11. OCT Calibration Block Counts and Placement in Stratix IV Devices (5A through 8C) (Part 2 of 2)
Device
EP4SGX110
Pin
780
Bank
Number of
OCT Blocks
5A
5B
5C
6A
6B
6C
7A
7B
7C
8A
8B
8C
8
—
—
—
—
—
—
Y
—
N
Y
—
N
1152
8
—
—
—
Y
—
N
Y
—
N
Y
—
N
780
8
—
—
—
—
—
—
Y
—
N
Y
—
N
1152
8
—
—
—
Y
—
N
Y
N
N
Y
Y
N
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
780
8
—
—
—
—
—
—
Y
—
N
Y
—
N
1152
8
—
—
—
Y
—
N
Y
N
N
Y
Y
N
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
780
8
—
—
—
—
—
—
Y
—
N
Y
—
N
1152
8
—
—
—
Y
—
N
Y
N
N
Y
N
N
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1760
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1932
10
Y
—
N
Y
N
N
Y
N
N
Y
N
Y
780
8
—
—
—
—
—
—
Y
—
N
Y
—
N
1152
8
—
—
—
Y
—
N
Y
N
N
Y
N
N
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1760
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
1932
10
Y
—
N
Y
N
N
Y
N
N
Y
N
Y
1152
8
—
—
—
Y
—
N
Y
N
N
Y
N
Y
1517
10
Y
—
N
Y
—
N
Y
N
N
Y
N
Y
1760
10
Y
—
N
Y
—
N
Y
N
N
Y
N
Y
1932
10
Y
N
N
Y
—
N
Y
N
N
Y
N
Y
EP4S40G2
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
EP4S40G5
1517
10
Y
—
N
Y
—
N
Y
N
N
Y
N
Y
EP4S100G2
1517
8
Y
—
N
Y
—
N
Y
N
N
Y
N
N
EP4S100G3
1932
10
Y
N
N
Y
—
N
Y
N
N
Y
N
Y
EP4S100G4
1932
10
Y
N
N
Y
—
N
Y
N
N
Y
N
Y
1517
10
Y
—
N
Y
—
N
Y
N
N
Y
N
Y
1932
10
Y
N
N
Y
—
N
Y
N
N
Y
N
Y
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
EP4S100G5
Sharing an OCT Calibration Block on Multiple I/O Banks
An OCT calibration block has the same VCCIO as the I/O bank that contains the block.
OCT RS calibration is supported on all I/O banks with different VCCIO voltage
standards, up to the number of available OCT calibration blocks. You can configure
the I/O banks to receive calibration codes from any OCT calibration block with the
same VCCIO. All I/O banks with the same VCCIO can share one OCT calibration block,
even if that particular I/O bank has an OCT calibration block.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
6–35
For example, Figure 6–23 shows a group of I/O banks that has the same VCCIO
voltage. If a group of I/O banks has the same VCCIO voltage, you can use one OCT
calibration block to calibrate the group of I/O banks placed around the periphery.
Because 3B, 4C, 6C, and 7B have the same VCCIO as bank 7A, you can calibrate all four
I/O banks (3B, 4C, 6C, and 7B) with the OCT calibration block (CB7) located in bank
7A. You can enable this by serially shifting out OCT RS calibration codes from the
OCT calibration block located in bank 7A to the I/O banks located around the
periphery.
1
I/O banks that do not contain calibration blocks share calibration blocks with I/O
banks that do contain calibration blocks.
Figure 6–23 is a top view of the silicon die that corresponds to a reverse view for flip
chip packages. It is a graphical representation only. This figure does not show
transceiver banks and transceiver calibration blocks.
Bank 7A
Bank 7B
Bank 7C
Bank 8C
Bank 8B
Bank 8A
CB 7
Figure 6–23. Example of Calibrating Multiple I/O Banks with One Shared OCT Calibration Block
Bank 1A
Bank 6A
Bank 1B
Bank 6B
Bank 1C
Bank 6C
I/O bank with the same VCCIO
Bank 2C
Bank 5C
I/O bank with different VCCIO
Bank 2B
Bank 5B
Bank 2A
Bank 5A
Bank 4A
Bank 4B
Bank 4C
Bank 3C
Bank 3B
Bank 3A
Stratix IV
OCT Calibration Block Modes of Operation
Stratix IV devices support OCT RS and OCT RT on all I/O banks. The calibration can
occur in either power-up or user mode.
Power-Up Mode
In power-up mode, OCT calibration is automatically performed at power up.
Calibration codes are shifted to selected I/O buffers before transitioning to user
mode.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–36
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
User Mode
In user mode, the OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER[9..0] signals are used to
calibrate and serially transfer calibration codes from each OCT calibration block to
any I/O. Table 6–12 lists the user-controlled calibration block signal names and their
descriptions.
Table 6–12. OCT Calibration Block Ports for User Control
Signal Name
Description
OCTUSRCLK
Clock for OCT block.
ENAOCT
Enable OCT Termination (Generated by user IP).
When ENOCT = 0, each signal enables the OCT serializer for the
corresponding OCT calibration block.
ENASER[9..0]
When ENAOCT = 1, each signal enables OCT calibration for the
corresponding OCT calibration block.
S2PENA_<bank#>
Serial-to-parallel load enable per I/O bank.
nCLRUSR
Clear user.
Figure 6–24 shows the flow of the user signal. When ENAOCT is 1, all OCT calibration
blocks are in calibration mode; when ENAOCT is 0, all OCT calibration blocks are in
serial data transfer mode. The OCTUSRCLK clock frequency must be 20 MHz or less.
1
You must generate all user signals on the rising edge of OCTUSRCLK.
Figure 6–24 does not show transceiver banks and transceiver calibration blocks.
CB9
Bank 1A
CB7
CB8
CB0
CB6
ENAOCT, nCLRUSR,
Bank 1B
Bank 1C
S2PENA_1C
Stratix IV
Core
Bank 2C
Bank 6C
S2PENA_6C
Bank 5C
OCTUSRCLK,
ENASER[N]
Bank 5B
CB1
CB5
CB3
Bank 4A
Bank 4B
Bank 4C
Bank 3C
Bank 3B
Bank 3A
Bank 5A
CB4
CB2
Stratix IV Device Handbook
Volume 1
Bank 6A
Bank 6B
S2PENA_4C
Bank 2B
Bank 2A
Bank 7A
Bank 7B
Bank 7C
Bank 8C
Bank 8B
Bank 8A
Figure 6–24. Signals Used for User Mode Calibration
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
6–37
OCT Calibration
Figure 6–25 shows user mode signal-timing waveforms. To calibrate OCT block[N]
(where N is a calibration block number), you must assert ENAOCT one cycle before
asserting ENASER[N]. Also, nCLRUSR must be set to low for one OCTUSRCLK cycle before
the ENASER[N] signal is asserted. Assert the ENASER[N] signals for 1000 OCTUSRCLK
cycles to perform OCTRS and OCTRT calibration. You can de-assert ENAOCT one clock
cycle after the last ENASER is de-asserted.
Serial Data Transfer
After you complete calibration, you must serially shift out the 28-bit OCT calibration
codes (14-bit OCT RS and 14-bit OCT RT) from each OCT calibration block to the
corresponding I/O buffers. Only one OCT calibration block can send out the codes at
any time by asserting only one ENASER[N] signal at a time. After you de-assert ENAOCT,
wait at least one OCTUSRCLK cycle to enable any ENASER[N] signal to begin serial
transfer. To shift the 28-bit code from the OCT calibration block[N], you must assert
ENASER[N] for exactly 28 OCTUSRCLK cycles. Between two consecutive asserted ENASER
signals, there must be at least one OCTUSRCLK cycle gap. (Figure 6–25).
Figure 6–25. OCT User Mode Signal—Timing Waveform for One OCT Block
OCTUSRCLK
ENAOCT
Calibration Phase
nCLRUSR
ENASER0
1000 OCTUSRCLK Cycles
28
OCTUSRCLK
Cycles
ts2p (1)
S2PENA_1A
Note to Figure 6–25:
(1) ts2p  25 ns.
After calibrated codes are shifted in serially to each I/O bank, the calibrated codes
must be converted from serial to parallel format before being used in the I/O buffers.
Figure 6–25 shows the S2PENA signals that can be asserted at any time to update the
calibration codes in each I/O bank. All I/O banks that received the codes from the
same OCT calibration block can have S2PENA asserted at the same time, or at a
different time, even while another OCT calibration block is calibrating and serially
shifting codes. The S2PENA signal is asserted one OCTUSRCLK cycle after ENASER is
de-asserted for at least 25 ns. You cannot use I/Os for transmitting or receiving data
when their S2PENA is asserted for parallel codes transfer.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–38
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Example of Using Multiple OCT Calibration Blocks
Figure 6–26 shows a signal timing waveform for two OCT calibration blocks doing RS
and RT calibration. Calibration blocks can start calibrating at different times by
asserting the ENASER signals at different times. ENAOCT must remain asserted while any
calibration is ongoing. You must set nCLRUSR low for one OCTUSRCLK cycle before each
ENASER[N] signal is asserted. In Figure 6–26, when you set nCLRUSR to 0 for the second
time to initialize OCT calibration block 0, this does not affect OCT calibration block 1,
whose calibration is already in progress.
Figure 6–26. OCT User-Mode Signal Timing Waveform for Two OCT Blocks
OCTUSRCLK
Calibration Phase
ENAOCT
nCLRUSR
1000 OCTUSRCLK
28 OCTUSRCLK
CY CLE S
CY CLE S
ENASER0
ENASER1
1000 OCTUSRCLK
28 OCTUSRCLK
CY CLE S
CY CLE S
ts2p (1)
S2PENA_1A (2)
ts2p (1)
S2PENA_2A (3)
Notes to Figure 6–26:
(1) ts2p  25 ns.
(2) S2PENA_1A is asserted in Bank 1A for calibration block 0.
(3) S2PENA_2A is asserted in Bank 2A for calibration block 1.
RS Calibration
If only RS calibration is used for an OCT calibration block, its corresponding ENASER
signal only requires to be asserted for 240 OCTUSRCLK cycles.
1
You must assert the ENASER signal for 28 OCTUSRCLK cycles for serial transfer.
Termination Schemes for I/O Standards
The following sections describe the different termination schemes for the I/O
standards used in Stratix IV devices.
Single-Ended I/O Standards Termination
Voltage-referenced I/O standards require both an input reference voltage, VREF, and a
termination voltage, VTT. The reference voltage of the receiving device tracks the
termination voltage of the transmitting device.
Figure 6–27 and Figure 6–28 show the details of SSTL and HSTL I/O termination on
Stratix IV devices.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
1
6–39
In Stratix IV devices, you cannot use series and parallel OCT simultaneously. For
more information, refer to “Dynamic On-Chip Termination” on page 6–29.
Figure 6–27. SSTL I/O Standard Termination
Termination
SSTL Class I
SSTL Class II
External
On-Board
Termination
25 Ω
50 Ω
25 Ω
50 Ω
50 Ω
50 Ω
VREF
Receiver
Transmitter
OCT
Transmit
VTT
50 Ω
Receiver
Transmitter
Stratix IV
Series OCT 25 Ω
VTT
VTT
50 Ω 50 Ω
50 Ω
50 Ω
8
VREF
VREF
Transmitter
Receiver
VCCIO
25 Ω
OCT
Receive
Receiver
Transmitter
Stratix IV
Parallel OCT
VTT
100 Ω
25 Ω
50 Ω
VREF
Transmitter
Receiver
VCCIO
Series OCT
50 Ω
100 Ω
Series OCT
25 Ω
100 Ω
100 Ω
Receiver
VCCIO
100 Ω
50 Ω
100 Ω
100 Ω
50 8
Transmitter
VCCIO
VCCIO
Stratix IV
Parallel OCT
VCCIO
50 Ω
VREF
100 Ω
OCT
in BiDirectional
Pins
50 Ω
VREF
Stratix IV
Series OCT 50 Ω
VTT
VTT
VTT
100 Ω
50 Ω
100 Ω
100 Ω
100 Ω
Series
OCT 50 Ω
Stratix IV
September 2012
Altera Corporation
Stratix IV
Series
OCT 25 Ω
Stratix IV
Stratix IV
Stratix IV Device Handbook
Volume 1
6–40
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Figure 6–28. HSTL I/O Standard Termination
Termination
HSTL Class II
HSTL Class I
VTT
VTT
VTT
50 Ω 50 Ω
50 Ω
External
On-Board
Termination
50 Ω
50 Ω
VREF
VREF
Transmitter
Receiver
VTT
Stratix IV
Series OCT 50 Ω
Receiver
VTT
Stratix IV
Series OCT 25 Ω
50 Ω
50 Ω
VREF
Receiver
Transmitter
VCCIO
100 Ω
50 Ω
VREF
OCT
Receive
VTT
100 Ω
Stratix IV
Stratix IV Device Handbook
Volume 1
100 Ω
Series OCT
25 Ω
Stratix IV
Parallel OCT
100 Ω
Transmitter
Receiver
VCCIO
VCCIO
100 Ω
50 Ω
100 Ω
VCCIO
50 Ω
100 Ω
VCCIO
100 Ω
Receiver
Stratix IV
Parallel OCT
Receiver
VCCIO
Transmitter
50 Ω
VREF
Transmitter
Series OCT
50 Ω
VTT
50 Ω 50 Ω
50 Ω
VREF
OCT
Transmit
OCT
in BiDirectional
Pins
Transmitter
100 Ω
50 8
100 Ω
Series
OCT 50 Ω
Stratix IV
100 Ω
Stratix IV
100 Ω
Series
OCT 25 Ω
Stratix IV
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
6–41
Differential I/O Standards Termination
Stratix IV devices support differential SSTL-18 and SSTL-2, differential HSTL-18,
HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS. Figure 6–29 through
Figure 6–35 show the details of various differential I/O terminations on these devices.
1
Differential HSTL and SSTL outputs are not true differential outputs. They use two
single-ended outputs with the second output programmed as inverted.
Figure 6–29. Differential SSTL I/O Standard Termination
Termination
Differential SSTL Class II
Differential SSTL Class I
VTT VTT
50 Ω
External
On-Board
Termination
25 Ω
25 Ω
VTT VTT
25 Ω
50 Ω
Receiver
Differential SSTL Class I
Z0= 50 Ω
VTT
VCCIO
50 Ω
100 Ω
Z0= 50 Ω
100 Ω
VTT
VCCIO
GND
100 Ω
50 Ω
Z0= 50 Ω
100 Ω
GND
Altera Corporation
Receiver
Transmitter
Series OCT 25 Ω
VCCIO
Z0= 50 Ω
September 2012
50 Ω
Differential SSTL Class II
Series OCT 50 Ω
Transmitter
50 Ω
50 Ω
50 Ω
25 Ω
50 Ω
Transmitter
OCT
50 Ω
50 Ω
50 Ω
VTT VTT
Receiver
100 Ω
100 Ω
VCCIO
GND
100 Ω
100 Ω
GND
Transmitter
Receiver
Stratix IV Device Handbook
Volume 1
6–42
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Figure 6–30. Differential HSTL I/O Standard Termination
Termination
Differential HSTL Class II
Differential HSTL Class I
VTT VTT
50 Ω
External
On-Board
Termination
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
Receiver
50 Ω
Receiver
Transmitter
Differential HSTL Class II
Differential HSTL Class I
Series OCT 50 Ω
Series OCT 25 Ω
VCCIO
Z0= 50 Ω
OCT
Z0= 50 Ω
VTT
VCCIO
50 Ω
100 Ω
Z0= 50 Ω
100 Ω
VCCIO
GND
100 Ω
VTT
50 Ω
Z0= 50 Ω
100 Ω
Receiver
100 Ω
100 Ω
VCCIO
GND
100 Ω
100 Ω
GND
GND
Stratix IV Device Handbook
Volume 1
50 Ω 50 Ω
50 Ω
Transmitter
Transmitter
VTT VTT
VTT VTT
Transmitter
Receiver
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
6–43
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power,
general-purpose I/O interface standard. In Stratix IV devices, the LVDS I/O standard
requires a 2.5-V VCCIO level. The LVDS input buffer requires 2.5-V VCCPD. Use this
standard in applications requiring high-bandwidth data transfer, such as backplane
drivers and clock distribution. LVDS requires a 100- termination resistor between
the two signals at the input buffer. Stratix IV devices provide an optional 100-
differential termination resistor in the device using on-chip differential termination.
Figure 6–31 shows LVDS termination. The on-chip differential resistor is only
available in the row I/O banks.
Figure 6–31. LVDS I/O Standard Termination
(1)
Termination
LVDS
Differential Outputs
Differential Inputs
External On-Board
Termination
50 Ω
100 Ω
50 Ω
Differential Inputs
Differential Outputs
50 Ω
OCT Receive
(True LVDS
Output)
(2)
100 Ω
50 Ω
Stratix IV OCT
OCT Receive
(Single-Ended
LVDS Output
with One-Resistor
Network,
LVDS_E_1R)
(3)
Differential Inputs
Single-Ended Outputs
≤ 1 inch
50 Ω
100 Ω
Rp
50 Ω
External Resistor
Stratix IV OCT
Single-Ended Outputs
OCT Receive
(Single-Ended
LVDS Output
with Three-Resistor
Network,
LVDS_E_3R)
(3)
Differential Inputs
≤ 1 inch
50 Ω
Rs
100 Ω
Rp
Rs
50 Ω
External Resistor
Stratix IV OCT
Notes to Figure 6–31:
(1) For LVDS output with a three-resistor network, the RS and RP values are 120 and 170 , respectively. For LVDS output with a one-resistor network, the
RP value is 120 .
(2) Side I/O banks support true LVDS output buffers.
(3) Column and side I/O banks support LVDS_E_1R and LVDS_E_3R I/O standards using two single-ended output buffers.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–44
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Differential LVPECL
In Stratix IV devices, the LVPECL I/O standard is supported on input clock pins on
column and row I/O banks. LVPECL output operation is not supported in Stratix IV
devices. LVDS input buffers are used to support LVPECL input operation. AC
coupling is required when the LVPECL common-mode voltage of the output buffer is
higher than the LVPECL input common-mode voltage. Figure 6–32 shows the
AC-coupled termination scheme. The 50- resistors used at the receiver end are
external to the device.
Figure 6–32. LVPECL AC-Coupled Termination
(1)
Altera FPGA
LVPECL Output Buffer
0.1 μF
0.1 μF
Stratix IV LVPECL
Input Buffer
ZO = 50 Ω
50 Ω
VICM
50 Ω
ZO = 50 Ω
Note to Figure 6–32:
(1) The LVPECL AC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
DC-coupled LVPECL is supported if the LVPECL output common mode voltage is
within the Stratix IV LVPECL input buffer specification (Figure 6–33).
Figure 6–33. LVPECL DC-Coupled Termination
(1)
Altera FPGA
LVPECL Output Buffer
Stratix IV LVPECL
Input Buffer
ZO = 50 Ω
ZO = 50 Ω
100 Ω
Note to Figure 6–33:
(1) The LVPECL DC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
6–45
RSDS
Stratix IV devices support the RSDS output standard with data rates up to 230 Mbps
using LVDS output buffer types. For transmitters, use two single-ended output
buffers with the external one- or three-resistor networks in the column I/O bank, as
shown in Figure 6–34. The one-resistor topology is for data rates up to 200 Mbps. The
three-resistor topology is for data rates above 200 Mbps. The row I/O banks support
RSDS output using true LVDS output buffers without an external resistor network.
Figure 6–34. RSDS I/O Standard Termination
(1)
One-Resistor Network (RSDS_E_1R)
Termination
Three-Resistor Network (RSDS_E_3R)
≤1 inch
External
On-Board
Termination
RP
≤1 inch
50 Ω
50 Ω
RS
100 Ω
RP
50 Ω
50 Ω
100 Ω
RS
Receiver
Transmitter
Stratix IV OCT
≤1 inch
RP
OCT
Transmitter
50 Ω
50 Ω
Transmitter
Receiver
≤ 1 inch
RS
RP
100 Ω
RS
Receiver
Transmitter
Stratix IV OCT
50 Ω
50 Ω
100 Ω
Receiver
Note to Figure 6–34:
(1) The RS and RP values are pending characterization.
A resistor network is required to attenuate the LVDS output-voltage swing to meet
RSDS specifications. You can modify the three-resistor network values to reduce
power or improve noise margin. The resistor values chosen must satisfy Equation 6–1.
Equation 6–1.
R
R s  ------p2
-------------------- = 50
R
R s + ------p2
1
Altera recommends performing additional simulations using IBIS models to validate
that custom resistor values meet the RSDS requirements.
f For more information about the RSDS I/O standard, refer to the RSDS Specification
from the National Semiconductor website at www.national.com.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–46
Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
Mini-LVDS
Stratix IV devices support the mini-LVDS output standard with data rates up to
340 Mbps using LVDS output buffer types. For transmitters, use two single-ended
output buffers with external one- or three-resistor networks, as shown in Figure 6–35.
The one-resistor topology is for data rates up to 200 Mbps. The three-resistor topology
is for data rates above 200 Mbps. The row I/O banks support mini-LVDS output using
true LVDS output buffers without an external resistor network.
Figure 6–35. Mini-LVDS I/O Standard Termination
(1)
One-Resistor Network (mini-LVDS_E_1R)
Termination
Three-Resistor Network (mini-LVDS_E_3R)
≤1 inch
External
On-Board
Termination
R
P
50 Ω
50 Ω
≤1 inch
RS
100 Ω
Receiver
R
Receiver
Stratix IV OCT
≤ 1 inch
RS
50 Ω
R
P
100 Ω
RS
OCT
Transmitter
Receiver
100 Ω
Transmitter
Stratix IV OCT
50 Ω
P
50 Ω
RS
Transmitter
≤1 inch
50 Ω
R
P
Transmitter
50 Ω
50 Ω
100 Ω
Receiver
Note to Figure 6–35:
(1) The RS and RP values are pending characterization.
A resistor network is required to attenuate the LVDS output voltage swing to meet the
mini-LVDS specifications. You can modify the three-resistor network values to reduce
power or improve noise margin. The resistor values chosen must satisfy Equation 6–1
on page 6–45.
1
Altera recommends that you perform additional simulations using IBIS models to
validate that custom resistor values meet the RSDS requirements.
f For more information about the mini-LVDS I/O standard, see the mini-LVDS
Specification from the Texas Instruments website at www.ti.com.
Design Considerations
Although Stratix IV devices feature various I/O capabilities for high-performance
and high-speed system designs, there are several other design considerations that
require your attention to ensure the success of your designs.
I/O Bank Restrictions
Each I/O bank can simultaneously support multiple I/O standards. The following
sections provide guidelines for mixing non-voltage-referenced and voltage-referenced
I/O standards in Stratix IV devices.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
6–47
Non-Voltage-Referenced Standards
Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one
VCCIO, either 1.2, 1.5, 1.8, 2.5, or 3.0 V. An I/O bank can simultaneously support any
number of input signals with different I/O standard assignments if it meets the VCCIO
and VCCPD requirement, as shown in Table 6–2 on page 6–3.
For output signals, a single I/O bank supports non-voltage-referenced output signals
that are driving at the same voltage as VCCIO. Because an I/O bank can only have one
VCCIO value, it can only drive out that one value for non-voltage-referenced signals.
For example, an I/O bank with a 2.5-V VCCIO setting can support 2.5-V standard
inputs and outputs as well as 3.0-V LVCMOS inputs (but not output or bidirectional
pins).
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix IV device’s I/O bank
supports multiple VREF pins feeding a common VREF bus. The number of available
VREF pins increases as device density increases. If these pins are not used as VREF pins,
they cannot be used as generic I/O pins and must be tied to VCCIO or GND. Each bank
can only have a single VCCIO voltage level and a single VREF voltage level at a given
time.
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards if all voltage-referenced standards use the same VREF
setting.
For performance reasons, voltage-referenced input standards use their own VCCPD
level as the power source. This feature allows you to place voltage-referenced input
signals in an I/O bank with a VCCIO of 2.5 V or below. For example, you can place
HSTL-15 input pins in an I/O bank with 2.5-V VCCIO. However, the voltage-referenced
input with parallel OCT enabled requires the VCCIO of the I/O bank to match the
voltage of the input standard.
Voltage-referenced bidirectional and output signals must be the same as the I/O
bank’s VCCIO voltage. For example, you can only place SSTL-2 output pins in an I/O
bank with a 2.5-V VCCIO.
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both voltage-referenced and non-voltage-referenced pins by
applying each of the rule sets individually. For example, an I/O bank can support
SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V VCCIO and a 0.9-V VREF.
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs),
and HSTL and HSTL-15 I/O standards with a 1.5-V VCCIO and 0.75-V VREF.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–48
Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
Document Revision History
Table 6–13 lists the revision history for this chapter.
Table 6–13. Document Revision History (Part 1 of 2)
Date
Version
September 2012
3.4
December 2011
3.3
February 2011
March 2010
November 2009
June 2009
April 2009
March 2009
Stratix IV Device Handbook
Volume 1
3.2
3.1
3.0
2.3
2.2
Changes
■
Updated the “Programmable Slew Rate Control” section to close FB #68385.
■
Updated Figure 6–17 to close FB #57979.
Updated Figure 6–2 and Figure 6–17.
■
Updated the “Modular I/O Banks”, “On-Chip Termination Support and I/O Termination
Schemes”, “Dynamic On-Chip Termination”, and “Programmable Pull-Up Resistor”
sections.
■
Updated Figure 6–17, Figure 6–32, and Figure 6–33.
■
Applied new template.
■
Minor text edits.
■
Updated Table 6–2 and Table 6–5.
■
Updated Figure 6–18, Figure 6–19, Figure 6–27, Figure 6–28, and Figure 6–31.
■
Added the “Summary of OCT Assignments” section.
■
Added a note to the “Sharing an OCT Calibration Block on Multiple I/O Banks” section.
■
Updated the “OCT Calibration” section.
■
Minor text edits.
■
Updated Table 6–2, Table 6–4, Table 6–6, Table 6–9, and Table 6–10.
■
Updated Figure 6–1, Figure 6–2, Figure 6–4, Figure 6–5, Figure 6–6, Figure 6–8,
Figure 6–9, Figure 6–10, Figure 6–11, Figure 6–12, Figure 6–13, and Figure 6–31.
■
Added Table 6–8.
■
Added Figure 6–7, Figure 6–14, Figure 6–15, and Figure 6–16.
■
Added “Left-Shift Series Termination Control” and “Expanded On-Chip Series Termination
with Calibration” sections.
■
Updated “MultiVolt I/O Interface”, “RSDS”, “Mini-LVDS”, and “Non-Voltage-Referenced
Standards” sections.
■
Deleted Figure 6-5: Number of I/Os in Each Bank in EP4SE290 and EP4SE360 in the
1517-Pin FineLine BGA Package.
■
Minor text edits.
■
Added introductory sentences to improve search ability.
■
Removed the Conclusion section.
■
Updated Figure 6–2.
■
Updated Table 6–8 and Table 6–9.
■
Deleted Figure 6-14.
■
Updated Table 6–1, Table 6–2,Table 6–3, Table 6–4, Table 6–6, Table 6–8, and Table 6–9.
■
Updated Figure 6–2, Figure 6–7, Figure 6–8, Figure 6–9, Figure 6–10, Figure 6–11, and
Figure 6–12.
■
Added Figure 6–14.
■
Removed Equation 6–2 and “Referenced Documents” section.
2.1
September 2012 Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
6–49
Table 6–13. Document Revision History (Part 2 of 2)
Date
Version
Changes
■
Updated “Modular I/O Banks” on page 6–7.
November 2008
2.0
■
Updated Figure 6–3 and Figure 6–21.
■
Made minor editorial changes.
May 2008
1.0
Initial release.
September 2012
Altera Corporation
Stratix IV Device Handbook
Volume 1
6–50
Stratix IV Device Handbook
Volume 1
Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
September 2012 Altera Corporation
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