datasheet for VL393T2950E

datasheet for VL393T2950E
Product Specifications
PART NO:
REV: 1.5
VL393T2950E-E6/D5/CC
General Information
1GB 128Mx72 DDR2 SDRAM REGISTERED 240 PIN ECC DIMM
Description:
The VL393T2950E is a 128M X 72 DDR2 SDRAM high density DIMM. This memory module consists of
eighteen CMOS 128MX4 bit with 4 banks DDR2 Synchronous DRAMs in BGA packages, two 25-bit Registered
buffers in BGA package, a zero delay PLL clock in BGA package, and a 2K EEPROM in 8-pin TSSOP
package. This module is a 240-pin Dual-In line-Memory Module and is intended for mounting into a connector
socket. Decoupling capacitors are mounted on the printed circuit board for each DDR2 SDRAM.
Features:
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240 -pin, dual-in line memory module (DIMM)
Fast data transfer rate: PC2-5300, PC2-4200, and PC2-3200
Supports ECC error detection and correction
VDD = VDDQ = 1.8V
VDDSPD = 1.7V to 3.6V
JEDEC satandard 1.8V I/O (SSTL_18 compatible)
Differential data strobe (DQS, DQS# ) option
Four-bit prefetch architechture
DLL aligns DQ and DQS transition with CK
Support duplicate output strobe (RDQS/RDQS#)
Programmable CAS# Latency (CL): 3, 4, and 5
Write latency = Read latency - 1 tCK
Programmable Burst ; length (4, 8)
Adjustable data-output drive strength
On-die termination (ODT)
Serial presence detect with EEPROMxc
Gold egde contacts
Lead-free RoHS
PCB: Height 18.29mm (0.720”), double sided component
Average refresh period 7.8us at lower TCASE = 850C,
39us at 850C < TCASE <= 950C
Order Information:
VL393T2950E-E6 S
DRAM MANUFACTURER
S - SAMSUNG
M - MICRON
MODULE SPEED
E6: PC5300 @ CL5
D5: PC4200 @ CL4
CC: PC3200 @ CL3
Pin Name
Function
A0~A13
Address Inputs
BA0 ~ BA1
Bank Address Inputs
DQ0 ~ DQ63
Data Input/Output
C B0 ~ C B7
Check Bits
D QS0 ~ D QS17
Data Strobes
D QS0# ~ D QS17#
D ata Strobes C omplement
OD T0
On-die Termination C ontrol
C K0,C K0#
D ifferenti al Clock Input
C KE0
Clock Enables
C S 0#
C hip Selects
RAS#
Row Address Strobes
C AS#
Column Address Strobes
WE#
Write Enable
RESET#
Regi ster Reset Input
VD D
Voltage Supply 1.8V +/- 0.1V
VD D Q
I/O Power 1.8V +/- 0.1V
VSS
Ground
SA0~SA2
SPD Address
SD A
SPD Data Input/Output
SC L
SPD Clock Input
A10/AP
Address i nput/Autoprecharge
VREF
SSTL_18 Refrence Voltage
VD D SPD
SPD Voltage supply 1.7V to
3.6V
NC
No C onnect
VL : Lead-free/RoHS
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 1 OF 10
Product Specifications
PART NO:
REV: 1.5
VL393T2950E-E6/D5/CC
Pin Configuration
240-PIN DDR2 SODIMM FRONT
240-PIN DDR2 SODIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
31
DQ19
61
A4
91
VSS
121
VSS
1 51
VSS
181
VD D Q
211
DQS14
2
VSS
32
VSS
62
VD D Q
92
DQS5#
122
DQ4
152
DQ28
182
A3
212
DQS14#
3
DQ0
33
DQ24
63
A2
93
DQS5
123
DQ5
153
DQ29
183
A1
213
VSS
4
DQ1
34
DQ25
64
VDD
94
VSS
124
VSS
154
VSS
184
VDD
214
DQ46
5
VSS
35
VSSD
65
VSS
95
DQ42
125
DQS9
155
DQS12
185
C K0
215
DQ47
6
DQS0#
36
DQS3#
66
VSS
96
DQ43
126
DQS9#
156
DQS12#
186
C K 0#
216
VSS
7
DQS0
37
DQS3
67
VD D
97
VSS
127
VSS
157
VSS
187
VD D
217
DQ52
8
VSS
38
VSS
68
NC
98
DQ48
128
DQ6
158
DQ30
188
A0
218
DQ53
9
DQ2
39
DQ26
69
VD D
99
DQ49
129
DQ7
159
DQ31
189
VD D
219
VSS
10
DQ3
40
DQ27
70
A10/AP
100
VSS
130
VSS
160
VSS
190
BA1
22 0
NC
11
VSS
41
VSS
71
BA0
101
SA2
131
DQ12
161
C B4
191
VD D Q
221
NC
12
DQ8
42
C B0
72
VD D Q
102
NC
132
DQ13
162
C B5
192
RAS#
222
VSS
13
DQ9
43
C B1
73
WE#
103
VSS
133
VSS
163
VSS
193
C S 0#
223
DQS15
14
VS S
44
VSS
74
C AS#
104
DQS6#
134
DQS10
164
DQS17
194
VD D Q
224
DQS15#
15
DQS1#
45
DQS8#
75
VD D Q
105
DQS6
135
DQS10#
165
DQS17#
195
ODT0
225
VSS
16
DQS1
46
DQS8
76
C S 1#*
106
VSS
136
VSS
166
VSS
196
A 13
226
DQ54
17
VSS
47
VSS
77
ODT1*
107
DQ50
137
NC
167
C B6
197
VDD
227
DQ55
18
RESET#
48
C B2
78
VD D Q
108
DQ51
138
NC
168
C B7
198
VSS
228
VSS
19
NC
49
CB3
79
VSS
109
VSS
139
VSS
169
V SS
199
DQ36
229
DQ60
20
VSS
50
VSS
80
DQ32
110
DQ56
140
DQ14
170
VD D Q
200
DQ37
230
DQ61
21
DQ10
51
VD DQ
81
DQ33
111
DQ57
141
DQ15
171
C K E 1*
201
VSS
231
VSS
22
DQ11
52
C KE0
82
VSS
112
VSS
1 42
VSS
172
VDD
202
DQS13
232
DQS16
23
VSS
53
VD D
83
DSQ4#
113
DQS7#
143
DQ20
173
NC
203
DQS13#
233
DQS16#
24
DQ16
54
B A 2*
84
DSQ4
114
DQS7
144
DQ21
174
NC
204
VSS
234
VSS
25
DQ17
55
NC
85
VSS
115
VSS
145
VSS
175
VD D Q
205
DQ38
235
DQ62
26
VSS
56
VD D Q
86
DQ34
116
DQ58
146
DQS11
176
A 12
206
DQ39
236
DQ63
27
DQS2#
57
A11
87
DQ35
117
DQ59
147
DQS11#
177
A9
207
VSS
237
VSS
28
DQS2
58
A7
88
VSS
118
VSS
148
VSS
178
VD D
208
DQ44
238
VD D SPD
29
VSS
59
VDD
89
DQ40
119
SDA
149
DQ22
179
A8
209
DQ45
239
SA0
30
DQ18
60
A5
90
DQ41
120
SC L
150
DQ23
180
A6
210
VSS
240
SA1
* These pins are not used in this module.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 2 OF 10
Product Specifications
PART NO:
VL393T2950E-E6/D5/CC
REV: 1.5
Functional Block Diagram
VSS
RCS0#
DM0/DQS9
NC/DQS9#
DQS0
DQS0#
DM
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
DQ4
DQ5
DQ6
DQ7
DM1/DQS10
NC/DQS10#
D0
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DQS2#
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
D9
CS# DQS DQS#
D10
DM2/DQS11
NC/DQS11#
DM
DQ16
DQ17
DQ18
DQ19
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
DQ20
DQ21
DQ22
DQ23
D2
DQS3
DQS3#
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
D11
DM3/DQS12
NC/DQS12#
DM
DQ24
DQ25
DQ26
DQ27
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DQS4#
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
D12
DM4/DQS13
NC/DQS13#
DM
DQ32
DQ33
DQ34
DQ35
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DQS5#
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
D13
DM5/DQS14
NC/DQS14#
DM
DQ40
DQ41
DQ42
DQ43
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
DQ44
DQ45
DQ46
DQ47
D5
DQS6
DQS6#
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
D14
DM6/DQS15
NC/DQS15#
DM
DQ48
DQ49
DQ50
DQ51
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DQS7#
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
D15
DM7DQS16
NC/DQS16#
DM
DQ56
DQ57
DQ58
DQ59
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS D QS#
DM
DQ60
DQ61
DQ62
DQ63
D7
DQS8
DQS8#
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
D16
DM8/DQS17
NC/DQS17#
DM
CB0
CB1
CB2
CB3
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
CB4
CB5
CB6
CB7
D8
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
D17
Serial PD
CS0#
1:2
BA0-BA1
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
R
E
G
I
S
T
E
R
RESET#
RST#
PCK7
RCS0# -> CS#: DDR2 SDRAMs D0-D17
SCL
SDA
VDDSPD
Serial PD
VDD/VDDQ
D0 - D17
WP A0 A1 A2
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
VREF
D0 - D17
SA0 SA1 SA2
RRAS# -> RAS#: DDR2 SDRAMs D0-D17
VSS
D0 - D17
RCAS# -> CAS#: DDR2 SDRAMs D0-D17
RWE# -> WE#: DDR2 SDRAMs D0-D17
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
P
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
L
PCK0#-PCK6#, PCK8#, PCK9# -> CK# : DDR2 SDRAMs D0-D17
CK0#
L
PCK7 -> CK : Register
OE
RESET#
PCK7# -> CK# : Register
Note: Unless otherwies noted, resister values are 22 Ohms
PCK7#**
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 3 OF 10
Product Specifications
PART NO:
REV: 1.5
VL393T2950E-E6/D5/CC
Absolute Maximum Ratings
Symbol
Parameter
MIN
MAX
Unit
VDD
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
V
Storage temperature
-55
100
0
C
0
95(1)
0
C
Command/Address,
RAS#, CAS#, WE#
C S #, C K E
-5
5
uA
C K, C K#
-10
10
uA
DM
-5
5
uA
DQ, DQS, DQS#
-5
5
uA
-36
36
uA
VIN, VOUT
TSTG
TCASE
Device operating Temperatue temperature
Input leakage current; Any input
0V<VIN<VDD; VREF input
0V<VIN<0.95V; Other pins not under
test = 0V
IL
Ouput leakage current;
0V<VOUT<VDDQ; DQs and ODT
are disable
IOZ
IVREF
VREF leakage current; VREF = Valid VREF level
Note:
1. TCASE = 850C - 950C: Average refresh period = 39us
DC Operating Conditions
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
VDD
1.7
1.8
1.9
V
1
I/O Supply voltage
VD D Q
1.7
1.8
1.9
V
4
VDDL Supply voltage
VD DL
1.7
1.8
1.9
V
4
I/O Reference voltage
VREF
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
Supply voltage
Notes: 1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise on VREF may not excedd +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2
percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF and must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VD DL track with VDD.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 4 OF 10
Product Specifications
PART NO:
REV: 1.5
VL393T2950E-E6/D5/CC
Operating Temperature Condition
Parameter
Operating temperature
Symbol
Rating
TOPER
0 to 95
Units
0
C
Notes
1,2,3
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JEDEC JESD51.2
2. At 0 - 950C, operation temperature range, all DRAM specification will be supported.
3. TCASE = 850C - 950C: Average refresh period = 39us
Input DC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.300
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.300
VREF - 0.125
V
Input AC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage
VIH(AC)
VREF + 0.250
-
V
AC Input Low (Logic 0) Voltage
VIL(AC)
-
VREF - 0.250
V
Input/Output Capacitance
TA=250C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA1,RAS#,CAS#,WE#)
CIN1
11
12
pF
Input capacitance (CKE0), (ODT0)
CIN2
11
12
pF
Input capacitance (CS0#)
CIN3
11
12
pF
Input capacitance (CK0, CK0#)
CIN4
10
11
pF
CIN5 (E6)
6.5
7.5
pF
CIN5 (D5,CC)
6.5
8
COUT1 (E6)
6.5
7.5
COUT1 (D5,CC)
6.5
8
Input capacitance (DM0 ~ DM8)
Input capacitance (DQ0 ~ DQ63), (DQS0 ~ DQS17)
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 5 OF 10
pF
Product Specifications
PART NO:
REV: 1.5
VL393T2950E-E6/D5/CC
IDD Specification
Condition
Symbol
-E6
-D5
-CC
Unit
Operating one bank active-precharge;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0
1750
175 0
1660
mA
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4; CL = CL(IDD);tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING; D ata pattern is sames as IDD4W.
IDD1
1930
1930
1930
mA
Precharge pow er-dow n current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
IDD2P
544
544
544
mA
Precharge quite standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
IDD2Q
1030
940
940
mA
Precharge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are SWITCHING.
IDD2N
1120
1030
1 030
mA
Active pow er-dow n current;
All banks open; tCK= tCK(IDD); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs
are FLOATING.
940
940
940
mA
IDD3P
616
616
616
mA
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
Active standby current;
All banks open;tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD));CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
IDD3N
1390
1300
1300
mA
Operating burst w rite current;
All banks open; Continuous burst writes; BL = 4; CL = CL(IDD); AL = 0; tCK= tCK(IDD);
tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4W
229 0
2020
1840
mA
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
IDD4R
24 70
2200
2020
mA
Burst auto refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.
IDD5
2380
2290
2290
mA
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and
address bus inputs are FLOATING; D ata bus inputs are
FLOATING.
IDD6
144
144
144
mA
IDD7
3640
3640
3640
mA
Normal
Operating bank interleave read curent;
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD);
tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
Note:
IDDs were calculated using Samsung components. Other manufacturers' DRAMs may have different values.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 6 OF 10
Product Specifications
PART NO:
REV: 1.5
VL393T2950E-E6/D5/CC
AC Timming Parameters & Specifications
-E6
Parameter
Clock
Data
-CC
Min
Max
Min
Max
Min
Max
Unit
CL=5
tCK (5)
3000
8000
-
-
-
-
ps
CL=4
tCK (4)
3750
8000
3,750
8,000
5,000
8,000
ps
CL=3
tCK (3)
5000
8000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
MIN
(tCH,tCL)
Clock jitter
tJIT
-125
125
-125
125
-125
125
ps
DQ output access time from CK/CK#
tAC
-450
+450
-500
+500
-600
+600
ps
Data-out high impedance window from CK/CK#
tHZ
tAC (MAX)
ps
Data-out low-impedance window from CK/CK#
tLZ
tAC (MIN)
tAC (MAX)
ps
DQ and DM input setup time relative to DQS
tDS
100
100
150
DQ and DM input hold time relative to DQS
tDH
175
225
275
DQ and DM input pulse width (for each input)
tDIPW
0.35
0.35
0.35
Data hold skew factor
tQHS
DQ–DQS hold, DQS to first DQ to go nonvalid,
p e r a cce ss
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
DQS input high pulse width
tDQSH
0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
0.35
tCK
DQS output access time fromCK/CK#
tDQSCK
-400
DQS falling edge to CK rising – setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
0.2
0.2
tCK
DQS–DQ skew, DQS to last DQ valid, per group,
p e r a cce ss
tDQSQ
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
DQS write preamble setup time
tWPRES
0
0
0
ps
DQS write preamble
tWPRE
0.35
0.35
0.35
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Clock cycle time
Data Strobe
-D5
Symbol
MIN
(tCH,tCL)
tAC (MAX)
tAC (MAX)
tAC (MAX)
tAC (MIN)
340
+400
MIN
(tCH,tCL)
tAC (MAX)
tAC (MIN)
400
-450
240
+450
tCK
450
-500
300
+500
ps
ps
350
ps
0.9
1.1
tCK
0.4
0.6
tCK
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 7 OF 10
ps
Product Specifications
PART NO:
REV: 1.5
VL393T2950E-E6/D5/CC
AC Timming Parameters & Specifications ( cont')
-E6
Parameter
Min
Command and Address
Self Refresh
Max
Min
-CC
Max
Min
Max
Unit
Address and control input pulse width for each
input
tIPW
0.6
0.6
0.6
tCK
Address and control input setup time
tIS
200
250
350
ps
tIH
275
375
475
ps
CAS# to CAS# command delay
tCCD
2
2
2
ps
ACTIVE to ACTIVE (same bank) command
tRC
55
55
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
7.5
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
15
15
15
ns
Four Bank Activate period
tFAW
37.5
37.5
37.5
37.5
37.5
37.5
ns
ACTIVE to PRECHARGE command
tRAS
40
70,000
40
70,000
40
70,000
ns
Internal READ to precharge command delay
tRTP
7.5
7.5
7.5
ns
Write recovery time
tWR
15
15
15
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
ns
Internal WRITE to READcommand delay
tWTR
7.5
7.5
10
ns
PRECHARGE command period
tRP
15
15
15
ns
PRECHARGE ALL command period
tRPA
tRP+tCK
tRP+tCK
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
2
2
2
tCK
CKE low to CK,CK# uncertainty
tDELAY
tIS+tCK+tIH
tIS+tCK+tIH
tIS+tCK+tIH
ns
tRFC
105
Address and control input hold time
REFRESH to Active or Refresh to Refresh
command interval
70,000
105
7.8
70,000
105
7.8
70,000
ns
7.8
us
Average periodic refresh interval
tREFI
Exit self refresh to non-READ command
tXSNR
tRFC(MIN)+10
tRFC(MIN)+10
tRFC(MIN)+10
ns
Exit self refresh to READ
tXSRD
200
200
200
tCK
Exit self refresh timing reference
tISXR
tIS
tIS
tIS
ps
ODT turn-on delay
tAOND
2
2
2
2
2
2
tCK
tAC(MAX)+
700
tAC(MIN)
tAC(MAX)+
1000
tAC(MIN)
tAC(MAX)+
1000
ps
ODT turn-on
tAON
tAC(MIN)
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
tAOF
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
ps
tAONPD
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
ps
ODT turn-off (power-down mode)
tAOFPD
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
ps
ODT to power-down entry latency
tANPD
3
3
3
tCK
ODT power-down exit latency
tAXPD
8
8
8
tCK
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
tCK
Exit precharge power-down to any non-READ
command.
tXP
2
2
2
tCK
CKE minimum high/low time
tCKE
3
3
3
tCK
ODT
ODT turn-off
ODT turn-on (power-down mode)
Power-Down
-D5
Symbol
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 8 OF 10
Product Specifications
PART NO:
REV: 1.5
VL393T2950E-E6/D5/CC
Package Dimensions
FRONT VIEW
133.35
3.00 (4X)
TYP.
3.95
MAX
2.00 (4X)
TYP
18.29
PIN 1
5.175 (2X)
1.27+/- 0.10
1.00 TYP.
TYP.
0.80 TYP.
10.00 TYP.
1.50 TYP.
PIN 120
123.00
TYP.
BACK VIEW
PIN 240
PIN 121
5.00 TYP.
55.00
TYP.
63.00
TYP.
NOTE:
All dimensions are in millimeters with tolerance +/- 0.13mm unless otherwise specified.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 9 OF 10
Product Specifications
PART NO:
VL393T2950E-E6/D5/CC
Revision History:
Date
Rev.
P ag e
C h an g es
12/06/06
1.0
All
Released spec
03/05/08
1.4
All
Added speed DDR2-667 (E6), and updated Package Dimension (page 9)
05/12/08
1.5
9
Updated Dimension Package
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 10 OF 10
REV: 1.5
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