Datasheet m464s1724ct1

Datasheet m464s1724ct1
M464S1724CT1
PC100 SODIMM
M464S1724CT1 SDRAM SODIMM
16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
FEATURE
The Samsung M464S1724CT1 is a 16M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M464S1724CT1 consists of eight CMOS 8M x 16 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy
substrate. Three 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each SDRAM. The
M464S1724CT1 is a Small Outline Dual In-line Memory Module
and is intended for mounting into 144-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
• Performance range
Part No.
M464S1724CT1-L1H/C1H
M464S1724CT1-L1L/C1L
•
•
•
•
•
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V ± 0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,250mil) , double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VDD
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VDD
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
DQ45
Pin Front
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
DQ14
DQ15
VSS
NC
NC
Pin
52
54
56
58
60
Back
Pin
DQ46 95
DQ47 97
VSS
99
NC
101
NC
103
105
107
Voltage Key
109
CLK0 62 CKE0 111
VDD
64
VDD 113
RAS 66 CAS 115
WE
68 CKE1 117
CS0
70 *A12 119
CS1
72 *A13 121
DU
74 CLK1 123
VSS
76
VSS 125
NC
78
NC
127
NC
80
NC
129
VDD
82
VDD 131
DQ16 84 DQ48 133
DQ17 86 DQ49 135
DQ18 88 DQ50 137
DQ19 90 DQ51 139
VSS
92
VSS 141
DQ20 94 DQ52 143
Front
DQ21
DQ22
DQ23
VDD
A6
A8
VSS
A9
A10/AP
VDD
DQM2
DQM3
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
**SDA
VDD
Max Freq. (Speed)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
PIN NAMES
Pin
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Back
DQ53
DQ54
DQ55
VDD
A7
BA0
VSS
BA1
A11
VDD
DQM6
DQM7
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
**SCL
VDD
Pin Name
Function
A0 ~ A11
Address input (Multiplexed)
BA0 ~ BA1
Select bank
DQ0 ~ DQ63
Data input/output
CLK0 ~ CLK1
Clock input
CKE0 ~ CKE1 Clock enable input
CS0 ~ CS1
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 7
DQM
VDD
Power supply (3.3V)
VSS
Ground
SDA
Serial data I/O
SCL
Serial clock
DU
Don′t use
NC
No connection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 April. 2000
M464S1724CT1
PC100 SODIMM
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ 0 ~
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power supply/ground
Power and ground for the input buffers and the core logic.
63
VDD/VSS
Rev. 0.0 April. 2000
M464S1724CT1
PC100 SODIMM
FUNCTIONAL BLOCK DIAGRAM
CS1
CS0
DQM0
DQM4
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U0
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
U4
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
CS
U6
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM6
DQM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
U1
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SDRAM U0 ~ U7
RAS
SDRAM U0 ~ U7
CAS
SDRAM U0 ~ U7
WE
SDRAM U0 ~ U7
CKE0
SDRAM U0 ~ U3
CKE1
U5
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A0 ~ A11, BA0 & 1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
CS
U7
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Serial PD
SCL
SA0
SA1 SA2
SDA
WP
SDRAM U4 ~ U7
10Ω
DQn
Every DQ pin of SDRAM
U0/U4
VDD
Three 0.1 uF X7R 0603 Capacitors
per each SDRAM
CLK0/1
To all SDRAMs
Vss
U1/U5
U2/U6
U3/U7
Note : Use a zero ohm jumper to isolate A12 from the SDRAM pins in non-256Mbit designs.
Rev. 0.0 April. 2000
M464S1724CT1
PC100 SODIMM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Storage temperature
Power dissipation
PD
8
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDDQ+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output low voltage
VOL
-
-
0.4
V
IOL = 2mA
ILI
-10
-
10
uA
3
Input leakage current
Note
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A11, BA0 ~ BA1)
CIN1
25
45
pF
Input capacitance (RAS, CAS, WE)
CIN2
25
45
pF
Input capacitance (CKE0 ~ CKE1)
CIN3
15
25
pF
Input capacitance (CLK0 ~ CLK1)
CIN4
15
21
pF
Input capacitance (CS0 ~ CS1)
CIN5
15
25
pF
Input capacitance (DQM0 ~ DQM7)
CIN6
10
12
pF
Data input/output capacitance (DQ0 ~ DQ63)
COUT
10
12
pF
Rev. 0.0 April. 2000
M464S1724CT1
PC100 SODIMM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Version
Test Condition
-1H
Operating current
(One bank active)
Precharge standby current in
power-down mode
ICC1
ICC2P
ICC2PS
ICC2N
Precharge standby current in
non power-down mode
ICC2NS
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC3P
ICC3PS
ICC3N
ICC3NS
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
680
CKE ≤ VIL(max), tCC = 10ns
8
CKE & CLK ≤ VIL(max), tCC =∞
8
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
Unit
Note
mA
1
-1L
mA
160
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
56
CKE ≤ VIL(max), tCC = 10ns
40
CKE & CLK ≤ VIL(max), tCC =∞
40
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
240
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
160
mA
700
mA
1
960
mA
2
C
12
mA
L
6.4
mA
Operating current
(Burst mode)
ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
Refresh current
ICC5
tRC ≥ tRC(min)
Self refresh current
ICC6
CKE ≤ 0.2V
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 0.0 April. 2000
M464S1724CT1
PC100 SODIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
50pF
870Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-1H
-1L
Unit
Note
Row active to row active delay
tRRD(min)
20
20
ns
1
RAS to CAS delay
tRCD(min)
20
20
ns
1
tRP(min)
20
20
ns
1
tRAS(min)
50
50
ns
1
Row precharge time
Row active time
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
100
ns
1
2
CLK
2,5
tDAL(min)
2 CLK + 20 ns
-
5
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
Number of valid output data
70
us
70
CAS latency=3
2
CAS latency=2
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
Rev. 0.0 April. 2000
M464S1724CT1
PC100 SODIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENT, NOT THE WHOLE MODULE.
Parameter
-1H
Symbol
Min
CLK cycle time
CAS latency=3
tCC
CAS latency=2
CLK to valid output delay
CAS latency=3
10
CAS latency=3
Max
1000
10
tSAC
CAS latency=2
Output data hold time
-1L
tOH
CAS latency=2
Min
10
Unit
Note
ns
1
ns
1,2
ns
2
Max
1000
12
6
6
6
7
3
3
3
3
CLK high pulse width
tCH
3
3
ns
3
CLK low pulse width
tCL
3
3
ns
3
Input setup time
tSS
2
2
ns
3
Input hold time
tSH
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
ns
2
CLK to output in Hi-Z
CAS latency=3
CAS latency=2
tSHZ
6
6
6
7
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.0 April. 2000
M464S1724CT1
PC100 SODIMM
SIMPLIFIED TRUTH TABLE
Command
Register
Mode register set
Auto refresh
Refresh
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
H
Entry
Self
refresh
Exit
H
H
Bank active & row addr.
H
X
Read &
column address
Auto precharge disable
H
X
Write &
column address
Auto precharge disable
L
H
H
H
H
X
X
X
L
L
H
H
X
V
L
H
L
H
X
V
X
X
L
H
L
L
H
X
X
L
L
H
H
L
H
L
L
X
H
L
Exit
L
H
Entry
H
L
Precharge power down mode
Exit
L
V
Column
address
(A0 ~ A8 )
L
X
X
All banks
Entry
L
DQM
H
No operation command
H
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
H
X
X
X
L
H
H
H
3
3
Column
address
(A0 ~ A8 )
H
H
Clock suspend or
active power down
3
Row address
H
H
Note
1,2
X
Auto precharge enable
Bank selection
A11,
A9 ~ A0
3
Auto precharge enable
Burst stop
A10/AP
L
L
Precharge
BA0,1
X
V
L
X
H
4
4,5
4
4,5
6
X
X
X
X
X
X
X
V
X
X
X
7
Notes : 1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA 1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.0 April. 2000
M464S1724CT1
PC100 SODIMM
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
2.66
(67.56)
2.50
(63.60)
1
59
61
0.91
(23.20)
0.13
(3.30)
143
2-φ 0.07
(1.80)
1.29
(32.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
0.79
(20.00)
0.24
(6.0)
0.16 ± 0.039
(4.00 ± 0.10)
1.25
(31.75)
2-R 0.078 Min
(2.00 Min)
Z
Y
0.15
(3.70)
62
144
0.157 Min
(4.00 Min)
0.125 Min
(3.20 Min)
0.150 Max
(3.80 Max)
0.04 ± 0.0039
(1.00 ± 0.10)
0.16 ± 0.0039
(4.00 ± 0.10)
0.06 ± 0.0039
(1.50 ± 0.1)
Detail Z
0.100 Min
60
(2.540 Min)
2
0.024 ± 0.001
(0.600 ± 0.050)
0.008 ±0.006
(0.200 ±0.150)
0.03 TYP
(0.80 TYP)
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 8Mx16 SDRAM, TSOP
SDRAM Part No. : K4S281632C
Rev. 0.0 April. 2000
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