null  null
phyCARD-S
Hardware Manual
Document No.:
L-731e_1
SBC Prod. No.:
PCA-A-S1-xxx
CB Prod. No.:
PBA-A-01
Edition:
April 2010
A product of a PHYTEC Technology Holding company
phyCARD-S [PCA-A-S1-xxx]
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark (™) and copyright (©) symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives
any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC
Messtechnik GmbH reserves the right to alter the information contained herein
without prior notification and accepts no responsibility for any damages which
might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Messtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
© Copyright 2010 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or
in part - are reserved. No reproduction may occur without the express written
consent from PHYTEC Messtechnik GmbH.
Address:
EUROPE
NORTH AMERICA
PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
+49 (800) 0749832
Information: [email protected]
1 (800) 278-9913
[email protected]
Technical
Support:
+49 (6131) 9221-31
[email protected]
1 (800) 278-9913
[email protected]
Fax:
+49 (6131) 9221-33
1 (206) 780-9135
Web Site:
http://www.phytec.de
http://www.phytec.com
1st Edition April 2010
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Contents
Index of Figures ........................................................................................... 3
Index of Tables ............................................................................................. 5
Conventions, Abbreviations and Acronyms .............................................. 1
Preface........................................................................................................... 3
1
Introduction......................................................................................... 7
1.1 Block Diagram ........................................................................... 10
1.2 View of the phyCARD-S ........................................................... 11
1.3 Minimum Requirements to Operate the phyCARD-S ............... 13
2
Pin Description .................................................................................. 14
3
Jumpers.............................................................................................. 22
4
Power.................................................................................................. 27
4.1 Primary System Power (VCC_3V3) .......................................... 27
4.2 Standby Voltage (VBAT)........................................................... 28
4.3 On-board Voltage Regulator (U33)............................................ 28
4.4 Supply Voltage for external Logic ............................................. 30
5
Power Management .......................................................................... 31
6
System Configuration and Booting ................................................. 33
7
System Memory................................................................................. 36
7.1 LP-DDR-SDRAM (U24, U25) .................................................. 36
7.2 NAND Flash Memory (U16) ..................................................... 37
7.3 I²C EEPROM (U28)................................................................... 37
7.3.1 Setting the EEPROM Lower Address Bits (J3, J4, J5).38
7.3.2 EEPROM Write Protection Control (J2) ......................39
7.4 Memory Model........................................................................... 39
8
SD / MMC Card Interfaces .............................................................. 40
9
Serial Interfaces................................................................................. 42
9.1 Universal Asynchronous Interface ............................................. 43
9.2 USB-OTG Transceiver (U34) .................................................... 43
9.3 USB-Host Transceiver (U35)..................................................... 44
9.4 Ethernet Interface ....................................................................... 45
9.4.1 PHY Physical Layer Transceiver (U38) .......................46
9.4.2 Software Reset of the Ethernet PHY (J1) .....................48
9.4.3 MAC Address................................................................48
9.5 I2C Interface ............................................................................... 49
9.6 SPI Interface ............................................................................... 50
9.7 Synchronous Serial Interface (SSI) ............................................ 50
10 General Purpose I/Os........................................................................ 52
11 Debug Interface (X1) ........................................................................ 53
12 LVDS Display Interface.................................................................... 56
12.1 Signal configuration (J9, J11) .................................................... 57
12.2 LVDS Display Interface pixel mapping..................................... 58
© PHYTEC Messtechnik GmbH 2010
L-731e_1
phyCARD-S [PCA-A-S1-xxx]
13
LVDS Camera Interface .................................................................. 59
13.1 Signal configuration (J10).......................................................... 59
14 Technical Specifications ................................................................... 60
15 Component Placement Diagram ..................................................... 63
16 Hints for Handling the phyCARD-S ............................................... 65
17 The phyCARD-S on the phyBase .................................................... 66
17.1 Concept of the phyBASE Board ................................................ 67
17.2 Overview of the phyBASE Peripherals ..................................... 69
17.2.1 Connectors and Pin Header........................................... 70
17.2.2 Switches ........................................................................ 71
17.2.3 LEDs ............................................................................. 75
17.2.4 Jumpers ......................................................................... 77
17.3 Functional Components on the phyBASE Board ...................... 81
17.3.1 phyCARD-S SBC Connectivity (X27) ......................... 81
17.3.2 Power Supply (X28) ..................................................... 82
17.3.3 RS-232 Connectivity (P1)............................................. 85
17.3.4 Ethernet Connectivity (X10)......................................... 87
17.3.5 USB Host Connectivity (X7, X8, X9, X30, X33) ........ 88
17.3.6 USB OTG Connectivity (X29) ..................................... 90
17.3.7 Display / Touch Connectivity (X6, X32)...................... 91
17.3.7.1 Display Data Connector (X6) ........................ 92
17.3.7.2 Display Power Connector (X32) ................... 94
17.3.7.3 Touch Screen Connectivity ........................... 95
17.3.8 Camera Interface (X5) .................................................. 97
17.3.9 Audio Interface (X1,X2,X3) ......................................... 99
17.3.10 I2C Connectivity.......................................................... 100
17.3.11 SPI Connectivity ......................................................... 101
17.3.12 User programmable GPIOs......................................... 102
17.3.13 Expansion connectors (X8A, X9A) ............................ 102
17.3.14 Security Digital Card/ MultiMedia Card (X26).......... 105
17.3.15 Boot Mode Selection (JP1) ......................................... 106
17.3.16 System Reset Button (S1) ........................................... 108
17.3.17 RTC at U3 ................................................................... 109
17.3.18 PLD at U25 ................................................................. 110
17.3.19 Carrier Board Physical Dimensions............................ 111
18 Revision History.............................................................................. 112
Index ......................................................................................................... 113
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Contents
Index of Figures
Figure 1:
Block Diagram of the phyCARD-S ......................................... 10
Figure 2:
Top view of the phyCARD-S (controller side)........................ 11
Figure 3:
Bottom view of the phyCARD-S (connector side) .................. 12
Figure 4:
Pin-out of the phyCARD-Connector (top view, with cross
section insert) ........................................................................... 16
Figure 5:
Typical jumper pad numbering scheme ................................... 22
Figure 6:
Jumper locations (top view)..................................................... 23
Figure 7:
Jumper locations (bottom view)............................................... 24
Figure 8:
Power Supply Diagram ............................................................ 29
Figure 9:
JTAG interface at X1 (top view) .............................................. 53
Figure 10: JTAG interface at X1 (bottom view) ........................................ 54
Figure 11: Physical dimensions ................................................................. 60
Figure 12: phyCARD-S component placement (top view) ....................... 63
Figure 13: phyCARD-S component placement (bottom view) ................. 64
Figure 14: phyBASE (phyCARD-S Carrier Board) .................................. 68
Figure 15: phyBASE Overview of Connectors, LEDs and Buttons........... 69
Figure 16: Typical jumper numbering scheme.......................................... 77
Figure 17: phyBASE jumper locations...................................................... 78
Figure 18: phyCARD-S SBC Connectivity to the Carrier Board.............. 81
Figure 19: Power adapter........................................................................... 82
Figure 20: Connecting the Supply Voltage at X28.................................... 83
Figure 21: UART1 connection interface at connector P1 ......................... 85
Figure 22: UART1 connector P1 signal description ................................. 86
Figure 23: Ethernet interface at connector X10 ........................................ 87
Figure 24: USB host interface at connector X7, X30, X33....................... 88
Figure 25: USB OTG interface at connector X29 ..................................... 90
Figure 26: Universal LVDS interface at connector X6.............................. 91
© PHYTEC Messtechnik GmbH 2010
L-731e_1
phyCARD-S [PCA-A-S1-xxx]
Figure 27: Camera interface at connectors X5 ......................................... 97
Figure 28: Audio interface at connectors X1,X2,X3.................................. 99
Figure 29: Expansion connector X8A, X9A............................................. 102
Figure 30: SD Card interface at connector X26 ..................................... 105
Figure 31: Boot Mode Selcetion Jumper JP1.......................................... 106
Figure 32: System Reset Button S1 .......................................................... 108
Figure 33: Carrier Board Physical Dimensions....................................... 111
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Contents
Index of Tables
Table 1:
Abbreviations and Acronyms used in this Manual .................... 2
Table 2:
X-Arc Bus Pin-out.................................................................... 17
Table 3:
Pin-out of the phyCARD-Connector X2.................................. 21
Table 4:
Jumper settings......................................................................... 26
Table 5:
Power Management Pins.......................................................... 31
Table 6:
Power States ............................................................................. 32
Table 7:
Boot Modes of i.MX27 module ............................................... 34
Table 8:
Compatible NAND Flash devices............................................ 37
Table 9:
U28 EEPROM I²C address via J3, J4, and J5 .......................... 38
Table 10:
EEPROM write protection states via J2................................... 39
Table 11:
Location of SD/ MMC Card interface signals ......................... 40
Table 12:
Location of the UART signals ................................................. 43
Table 13:
Location of the USB-OTG signals........................................... 44
Table 14:
Location of the USB-Host signals ........................................... 45
Table 15:
Location of the Ethernet signals............................................... 46
Table 16:
Fast Ethernet controller memory map...................................... 47
Table 17:
Software Reset of the Ethernet PHY ....................................... 48
Table 18:
I2C Interface Signal Location................................................... 49
Table 19:
SPI Interface Signal Location .................................................. 50
Table 20:
SSI Interface Signal Location .................................................. 51
Table 21:
Location of GPIO and IRQ pins .............................................. 52
Table 22:
JTAG connector X1 signal assignment.................................... 55
Table 23:
Display Interface Signal Location............................................ 56
Table 24:
Pixel mapping of 18-bit LVDS display interface ................... 58
Table 25:
Pixel mapping of 24-bit LVDS display interface ................... 58
Table 26:
Camera Interface Signal Location............................................ 59
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
Table 27:
phyBASE Connectors and Pin Headers................................... 70
Table 28:
phyBASE push buttons descriptions ....................................... 71
Table 29:
phyBASE DIP-Switch S3 descriptions.................................... 74
Table 30:
phyBASE LEDs descriptions................................................... 75
Table 31:
phyBASE jumper descriptions................................................. 80
Table 32:
LEDs assembled on the Carrier Board .................................... 83
Table 33:
Distribution of the USB hub's (U4) ports ................................ 89
Table 34:
Universal USB pin header X33 signal description .................. 89
Table 35:
Display data connector signal description ............................... 93
Table 36:
SPI and GPIO connector selection........................................... 94
Table 37:
LVDS power connector X32 signal description...................... 94
Table 38:
Selection of the touch screen controller................................... 96
Table 39:
PHYTEC camera connector X5............................................... 98
Table 40:
Selection of the audio codec .................................................... 99
Table 41:
I2C connectivity ..................................................................... 100
Table 42:
I2C addresses in use ............................................................... 101
Table 43:
SPI connector selection.......................................................... 101
Table 44:
SPI and GPIO connector selection......................................... 103
Table 45:
PHYTEC expansion connector X8A, X9A ........................... 104
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Conventions, Abbreviations and Acronyms
Conventions, Abbreviations and Acronyms
This hardware manual describes the PCA-A-S1 Single Board
Computer in the following referred to as phyCARD-S. The manual
specifies the phyCARD-S's design and function. Precise specifications
for the Freescale i.MX27 microcontrollers can be found in the
enclosed microcontroller Data Sheet/User's Manual.
Conventions
The conventions used in this manual are as follows:
ƒ Signals that are preceded by a "n", "/", or “#”character (e.g.: nRD,
/RD, or #RD), or that have a dash on top of the signal name (e.g.:
RD) are designated as active low signals. That is, their active state
is when they are driven low, or are driving low.
ƒ A "0" indicates a logic zero or low-level signal, while a "1"
represents a logic one or high-level signal.
ƒ Tables which describe jumper settings show the default position in
bold, blue text.
ƒ Text in blue italic indicates a hyperlink within, or external to the
document. Click these links to quickly jump to the applicable
URL, part, chapter, table, or figure.
ƒ References made to the phyCARD-Connector always refer to the
high density molex connector on the undersides of the phyCARDS Single Board Computer.
Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual.
Use the table below to navigate unfamiliar terms used in this
document.
Abbreviation Definition
BSP
Board Support Package (Software delivered with the
Development Kit including an operating system
(Windows, or Linux) preinstalled on the module and
Development Tools).
GPIO
General purpose input and output.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
GPI
GPO
Sx
Sx_y
CB
DFF
EMB
EMI
IRAM
J
JP
PCB
RTC
SMT
SBC
VBAT
Table 1:
General purpose input.
General purpose output.
User button Sx (e.g. S1, S2, etc.) used in reference to
the available user buttons, or DIP-Switches on the
Carrier Board.
Switch y of DIP-Switch Sx; used in reference to the
DIP-Switch on the Carrier Board.
Carrier Board; used in reference to the phyBASE
Development Kit Carrier Board.
D flip-flop.
External memory bus.
Electromagnetic Interference.
Internal RAM; the internal static RAM on the
Freescale i.MX27 microcontroller.
Solder jumper; these types of jumpers require solder
equipment to remove and place.
Solderless jumper; these types of jumpers can be
removed and placed by hand with no special tools.
Printed circuit board.
Real-time clock.
Surface mount technology.
Single Board Computer; used in reference to the
PCA-A-S1 /phyCARD-A-S1 Single Board Computer
SBC standby voltage input
Abbreviations and Acronyms used in this Manual
Note: The BSP delivered with the phyCARD-S usually includes
drivers and/or software for controlling all components such as
interfaces, memory, etc.. Therefore programming close to hardware at
register level is not necessary in most cases. For this reason, this
manual contains no detailed description of the controller's registers, or
information relevant for software development. Please refer to the
i.MX27 Reference Manual, if such information is needed to connect
customer
designed
applications.
2
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Preface
Preface
As a member of PHYTEC's new phyCARD product family the
phyCARD-S is one of a series of PHYTEC Single Board Computers
(SBCs) that can be populated with different controllers and, hence,
offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
(1)
as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2)
as insert-ready, fully functional phyCARD OEM modules,
which can be embedded directly into the user’s peripheral
hardware design.
Implementation of an OEM-able SBC subassembly as the "core" of
your embedded design allows you to focus on hardware peripherals
and firmware without expending resources to "re-invent"
microcontroller circuitry. Furthermore, much of the value of the
phyCARD module lies in its layout and test.
PHYTEC's new phyCARD product family consists of a series of
extremely compact embedded control engines featuring various
processing performance classes while using the newly developed XArc embedded bus standard. The standardized connector footprint and
pin assignment of the X-Arc bus makes this new SBC generation
extremely scalable and flexible. This also allows to use the same
carrier board to create different applications depending on the required
processing power. With this new SBC concept it is possible to design
entire embedded product families around vastly different processor
performances while optimizing overall system cost. In addition, future
advances in processor technology are already considered with this new
embedded bus standard making product upgrades very easy. Another
major advantage is the forgone risk of potential system hardware
redesign steps caused by processor or other critical component
discontinuation. Just use one of PHYTEC's other phyCARD SBCs
© PHYTEC Messtechnik GmbH 2010
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3
phyCARD-S [PCA-A-S1-xxx]
thereby ensuring an extended product life cycle of your embedded
application.
Production-ready Board Support Packages (BSPs) and Design
Services for our hardware will further reduce your development time
and risk and allow you to focus on your product expertise. Take
advantage of PHYTEC products to shorten time-to-market, reduce
development costs, and avoid substantial design issues and risks. With
this new innovative full system solution you will be able to bring your
new ideas to market in the most timely and cost-efficient manner.
For more information go to:
http://www.phytec.com/services/
Ordering Information
The part numbering of the phyCARD has the following structure:
PCA-A-S1-xxxxxx
Generation
A
=
First generation
Performance class
S
M
L
XL
=
=
=
=
small
middle
large
largest
Controller Number of specified performance class
Assembly options (depending on model)
In order to receive product specific information on changes and
updates in the best way also in the future, we recommend to register at
http://www.phytec.de/de/support/registrierung.html
You can also get technical support and additional information
concerning your product.
4
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Preface
The support section of our web site provides product specific
information, such as errata sheets, application notes, FAQs, etc.
http://www.phytec.de/de/support/faq/faq-phycard-s.html
Declaration of Electro Magnetic Conformity of the
PHYTEC phyCARD-S
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD-dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product's pin header rows are longer than 3 m.
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnetic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
© PHYTEC Messtechnik GmbH 2010
L-731e_1
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phyCARD-S [PCA-A-S1-xxx]
6
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Introduction
1 Introduction
The phyCARD-S belongs to PHYTEC’s phyCARD Single Board
Computer module family. The phyCARD SBCs represent the
continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the
phyCARD boards integrate all core elements of a microcontroller
system on a subminiature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware
developments.
PHYTEC's phyCARD family introduces the newly developed X-Arc
embedded bus standard. Apart from processor performance, a large
number of embedded solutions require a corresponding number of
standard interfaces. Among these process interfaces are for example
Ethernet, USB, UART, SPI, I2C, audio, display and camera
connectivity. The X-Arc bus exactly meets this requirement. As well
the location of the commonly used interfaces as the mechanical
specifications are clearly defined. All interface signals of PHYTEC's
new X-Arc bus are available on a single, 100-pin , high-density pitch
(0.635 mm) connector, allowing the phyCARDs to be plugged like a
"big chip" into a target application. The reduced complexity of the
phyCARD SBC as well as the smaller number of interface signals
greatly simplifies the SBC carrier board design helping you to reduce
your time-to-market.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments approximately 20 % of all pin header connectors on the
X-Arc bus are dedicated to Ground. This improves EMI and EMC
characteristics and makes it easier to design complex applications
meeting EMI and EMC guidelines using phyCARD boards even in
high noise environments.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
phyCARD boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD components and laser-drilled
microvias are used on the boards, providing phyCARD users with
access to this cutting edge miniaturization technology for integration
into their own design.
The phyCARD-S is a subminiature (60 x 60 mm) insert-ready Single
Board Computer populated with the Freescale i.MX27
microcontroller. Its universal design enables its insertion in a wide
range of embedded applications.
Precise specifications for the controller populating the board can be
found in the applicable controller Reference Manual or datasheet. The
descriptions in this manual are based on the Freescale i.MX27. No
description of compatible microcontroller derivative functions is
included, as such functions are not relevant for the basic functioning
of the phyCARD-S.
The phyCARD-S offers the following features:
• Subminiature Single Board Computer (´60 x 60 mm) achieved
through modern SMD technology
• Populated with the Freescale i.MX27 microcontroller (BGA404
packaging)
• Improved interference safety achieved through multi-layer PCB
technology and dedicated ground pins
• X-Arc bus including commonly used interfaces such as Ethernet,
USB, UART, SPI, I2C, audio, display and camera connectivity
(both LVDS) available at one 100-pin high-density (0.635 mm)
Molex connector, enabling the phyCARD-S to be plugged like a
"big chip" into target application
• Max. 400 MHz core clock frequency
• Boot from NAND Flash
• 128 MByte (up to 1 GByte) on-board NAND Flash 1
• 32 MByte (up to 512 MByte) Mobile DDR SDRAM on-board
• 4KB (up to 32kB) I2C EEPROM
1 Please contact PHYTEC for more information about additional module configurations.
8
© PHYTEC Messtechnik GmbH 2010
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Introduction
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Serial interface with 4 lines (TTL) allowing simple hardware
handshake
High-Speed USB OTG transceiver
High-Speed USB HOST transceiver
Auto HDX/FDX 10/100MBit Ethernet interface, with HP Auto
MDI/MDI-X support
All controller required supplies generated on board
4 Channel LVDS (18Bit) LCD-Interface
Support of standard 20 pin debug interface through JTAG
connector
One I2C interfaces
One SPI interfaces
SD/MMC card interface with DMA
SSI Interface (AC97)
Optional LVDS Camera Interface1
3 GPIO/IRQ ports
2 Power State outputs to support applications requiring a power
management
1 Wake Up input
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
1.1 Block Diagram
i.MX27
ARM926EJ-S
core
400 MHz Clock
external 26MHz Quartz
DDR2 SDRAM Bus
32 to 256MB
LP-DDR
133MHz
SDRAM
32 bit
64MB to 1GB
NAND Flash
8 bit
EM
I
16k L1 D-cache
Boot 0 / 1 / 2
16k L1 I-cache
USB2-Host
USB-OTG
USB-OTG
+1V2 / 1V45
+1V
+1V
3
+1V
5
+2V775
8
2
Powe
r
Supply
6
I2CMemory
EEPRO
4M
to 32KByte
2
Ethernet PHY
6
6
6
CSPI
1
4
UART
1
7
SDHC
2
3
GPIO (PC25 / 31, PE5)
IP
U
1
2
SSI1 / AC97
LCD
C
18-BitLVDS-Transmitter
CS
I
10-Bit LVDS-Deserializer
JTAG
10
USB
OTG
1
I2C1
Figure 1:
6
2
I2C2
FEC FastEthernet
High-Speed
USB Host
Transceiver
(PC16,
/RESET_IN
/RESET_OUT
4
Transceiver
GPIO
Memory Management
Unit
Boot Configuration
Input
phyCARD-Connector
GPIO
MMU
USB-Host
1
10
4
Card-Edge Connector
Power State Output
Wake Up Input
VLogic Output +2V775
VBat
+3V3
Power
+3V3 Input /
Reset
Reset Output
I2C Master Interface
10/100 Mbit Ethernet
AC97 /
Synchronous serial Interface
SPI Interface
UART TTL
SD / MMC-Card Interface
3 * GPIO / IRQ
LVDS-Display Interface
LVDS-Camera Interface
JTAG Debug-/Test Port
Block Diagram of the phyCARD-S
© PHYTEC Messtechnik GmbH 2010
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Introduction
1.2 View of the phyCARD-S
J4
J3
J5
U35
U28
J2
TP3
TP2
TP1
U24
U26
J6
U34
U25
X1
J7
J8
U33
Figure 2:
U16
Top view of the phyCARD-S (controller side)
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
J10
U29
U32
U30
TP4
J9
X2
U38
U31
J1
U23
Figure 3:
12
U36 U37
Bottom view of the phyCARD-S (connector side)
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Introduction
1.3 Minimum Requirements to Operate the phyCARD-S
Basic operation of the phyCARD-S only requires supply of a +3V3
input voltage with 1.0 A load and the corresponding GND connection.
These supply pins are located at the phyCARD-Connector X2:
VCC_3V3:
X2
1A, 2A, 3A, 1B, 2B, 3B
Connect all +3.3V VCC input pins to your power supply and at least
the matching number of GND pins.
Corresponding GND:
X2 4A, 8A, 13A, 4B, 8B, 13B
Please refer to section 2 for information on additional GND Pins
located at the phyCARD-Connector X2
Caution:
We recommend connecting all available +3V3 input pins to
the power supply system on a custom carrier board
housing the phyCARD-S and at least the matching number
of GND pins neighboring the +3V3 pins.
In addition, proper implementation of the phyCARD-S
module into a target application also requires connecting
all GND pins neighboring signals that are being used in the
application circuitry.
Please refer to section 4 for more information.
© PHYTEC Messtechnik GmbH 2010
L-731e_1
13
phyCARD-S [PCA-A-S1-xxx]
2 Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and
application, it is the user's responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
As Figure 4 indicates, all X-Arc bus signals extend to one surface
mount technology (SMT) connector (0.635 mm) lining on side of the
module (referred to as phyCARD-Connector). This allows the
phyCARD-S to be plugged into any target application like a "big
chip".
The numbering scheme for the phyCARD-Connector is based on a
two dimensional matrix in which column positions are identified by a
letter and row position by a number. Pin 1A, for example, is always
located in the upper left hand corner of the matrix. The pin numbering
values increase moving down on the board. Lettering of the pin
connector rows progresses alphabetically from left to right (refer to
Figure 4).
The numbered matrix can be aligned with the phyCARD-S (viewed
from above; phyCARD-Connector pointing down) or with the socket
of the corresponding phyCARD Carrier Board/user target circuitry.
The upper left-hand corner of the numbered matrix (pin 1A) is thus
covered with the corner of the phyCARD-S marked with a triangle.
The numbering scheme is always in relation to the PCB as viewed
from above, even if all connector contacts extend to the bottom of the
module.
14
© PHYTEC Messtechnik GmbH 2010
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Pin Description
The numbering scheme is thus consistent for both the module’s
phyCARD-Connector as well as the mating connector on the
phyBASE Carrier Board or target hardware, thereby considerably
reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix
previously described, the phyCARD-Connector is usually assigned a
single designator for its position (X1 for example). In this manner the
phyCARD-Connector comprises a single, logical unit regardless of the
fact that it could consist of more than one physical socketed
connector.
The following figure illustrates the numbered matrix system. It shows
a phyCARD-S with SMT phyCARD-Connectors on its underside
(defined as dotted lines) mounted on a Carrier Board. In order to
facilitate understanding of the pin assignment scheme, the diagram
presents a cross-view of the phyCARD-module showing these
phyCARD-Connectors mounted on the underside of the module’s
PCB.
© PHYTEC Messtechnik GmbH 2010
L-731e_1
15
phyCARD-S [PCA-A-S1-xxx]
Figure 4:
Pin-out of the phyCARD-Connector (top view, with cross section
insert)
Table 2 shows the Pin-out of the X-Arc bus with the functional
grouping of the signals, while Table 3 provides an overview of the
Pin-out of the phyCARD-Connector with signal names and
descriptions specific to the phyCARD-S. It also provides the
appropriate signal level interface voltages listed in the SL (Signal
Level) column and the signal direction.
The Freescale i.MX27 is a multi-voltage operated microcontroller and
as such special attention should be paid to the interface voltage levels
to avoid unintentional damage to the microcontroller and other onboard components. Please refer to the Freescale i.MX27 Reference
Manual for details on the functions and features of controller signals
and port pins.
16
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Display
Ethernet
USB OTG
SD/MMC
SPI
AC97/HDA
I/O
In
In
In
In
Out
In
Out
Out
Out
Out
Out
In
In
Out
I2 C
Out
In
In
Out
In
Out
Bi
Bi
Out
Bi
Bi
Bi
Out
Out
In
In
Out
Bi
Out
Out
In
Bi
Bi
In
X-Arc Bus Pin-out
© PHYTEC Messtechnik GmbH 2010
L-731e_1
17
USB Host
USB Host
UART
AC97/HDA
Signal
VCC
VCC
VCC
GND
VCC_LOGIC
VSTBY
nRESET_OUT
GND
LVDS_TX1+
LVDS_TX1LVDS_TX3+
LVDS_TX3GND
LVDS_CAM_RX+
LVDS_CAM_RXLVDS_CAM_nLOCK
I2C_DATA
GND
ETH_LINK
ETH_RX+
ETH_RXGND
USB_PWR2
USB_OC2
GND
nSuspend_to_RAM
USB_D2USB_D2+
nPower_Off
GND
SDIO_D1
SDIO_D3
SDIO_CMD
GND
SPI_CS1
SPI_MOSI
SPI_MISO
GND
UART_RXD
UART_CTS
GND
AC97/HDA_BIT_CLK
AC97/HDA_SYNC
AC97/HDA_nRESET
GND
SDIO_CD
GPIO1/IRQ
for internal use only
GND
CONFIG1
SPI
Table 2:
Pin
1B
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
13B
14B
15B
16B
17B
18B
19B
20B
21B
22B
23B
24B
25B
26B
27B
28B
29B
30B
31B
32B
33B
34B
35B
36B
37B
38B
39B
40B
41B
42B
43B
44B
45B
46B
47B
48B
49B
50B
SD/MMC
Boot Opt.
Pin
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
13A
14A
15A
16A
17A
18A
19A
20A
21A
22A
23A
24A
25A
26A
27A
28A
29A
30A
31A
32A
33A
34A
35A
36A
37A
38A
39A
40A
41A
42A
43A
44A
45A
46A
47A
48A
49A
50A
Ethernet
GPIO
VCC
VCC
VCC
GND
VCC_LOGIC
FEEDBACK
nRESET_IN
GND
LVDS_TX0+
LVDS_TX0LVDS_TX2+
LVDS_TX2GND
LVDS_TXCLK+
LVDS_TXCLKLVDS_CAM_MCLK
I2C_CLK
GND
ETH_SPEED
ETH_TX+
ETH_TXGND
USB_OTG_PWR1
USB_OTG_OC1
GND
USB_OTG_VBUS1
USB_OTG_D1USB_OTG_D1+
USB_OTG_UID1
GND
SDIO_D0
SDIO_D2
SDIO_CLK
GND
SPI_CS0
SPI_RDY
SPI_CLK
GND
UART_TXD
UART_RTS
GND
HDA_SEL/AC97_INT
AC97/HDA_SDATA_OUT
AC97/HDA_SDATA_IN
GND
GPIO0/IRQ/PWM
GPIO2/IRQ
nWKUP
GND
CONFIG0
Camera
UART
Out
Out
Out
Out
In
Bi
Bi
Bi
In
Bi
Bi
Out
Out
In
Out
Out
In
Bi
Out
In
Bi
Bi
In
In
Signal
Display
Camera
I2 C
I/O
In
In
In
In
Out
In
Out
Out
Out
Out
Out
Out
Out
Supply
Supply
Pin Description
SD/MMC
GPIO
Boot Opt.
phyCARD-S [PCA-A-S1-xxx]
Note:
SL is short for Signal Level (V) and is the applicable logic level to
interface a given pin.
Those pins marked as “N/A” have a range of applicable values that
constitute proper operation.
Please refer to the phyCARD Design-In Guide (LAN-051) for
layout recommendations and example circuitry.
Pin # Signal
I/O
Pin Row X2A
SL
Description
1A
VCC_3V3
I
Power
3.3V Primary Voltage Supply Input
2A
VCC_3V3
I
Power
3.3V Primary Voltage Supply Input
3A
VCC_3V3
GND
I
Power
3.3V Primary Voltage Supply Input
4A
-
-
Ground 0V
5A
NVDD7_12_14
O
VCC_LOGIC VCC Logic Output
6A
VCC_FEEDBACK
O
Power
Feedback Output to indicate the supply
voltage required (3V3 or 5V)
7A
X_#RESET
I
VCC3V3
Active low Reset In
8A
GND
-
-
Ground 0V
9A
TXOUT0+
O
LVDS
LVDS Chanel 0 positive Output
10A
TXOUT0-
O
LVDS
LVDS Chanel 0 negative Output
11A
TXOUT2+
O
LVDS
LVDS Chanel 2 positive Output
12A
TXOUT2-
O
LVDS
LVDS Chanel 2 negative Output
13A
GND
-
-
Ground 0V
14A
TXCLKOUT+
O
LVDS
LVDS Clock positive Output
15A
TXCLKOUT-
O
LVDS
LVDS Clock negative output
16A
X_CSI_MCLK
O
VCC_LOGIC Clock Output for Camera Interface
17A
X_I2C_CLK
O
VCC_LOGIC I2C Clock Output
18A
GND
-
-
Ground 0V
19A
X_ETH_SPEED
O
VCC3V3
Ethernet Speed Indicator (Open Drain)
20A
X_ETH_TX+
O (I) VCC3V3
Transmit positive output (normal)
Receive positive input (reversed)
21A
X_ETH_TX-
O (I) VCC3V3
Transmit negative output (normal)
Receive negative input (reversed)
22A
GND
-
-
Ground 0V
23A
X_USB_HS_/PSW
O
VCC3V3
USB-OTG Power switch output open
drain
24A
X_USB_HS_FAULT
I
VCC3V3
USB-OTG over current input signal
25A
GND
-
0
Ground 0V
18
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Pin Description
26A
X_VBUS
I
27A
X_UDM
I/O
28A
X_UDP
I/O
29A
X_UID
I
30A
GND
-
31A
X_SD2_D0
I/O
VCC_LOGIC SD/MMC Data line both in 1-bit and 4-bit
mode
32A
X_SD2_D2
I/O
VCC_LOGIC SD/MMC Data line both in 1-bit and 4-bit
mode
33A
X_SD2_CLK
O
VCC_LOGIC SD/MMC Clock for MMC/SD/SDIO
34A
GND
-
-
35A
X_CSPI1_SS0
O
VCC_LOGIC SPI 1 Chip select 0
36A
X_#CSPI1_RDY
O
37A
X_CSPI1_SCLK
O
VCC_LOGIC SPI 1 SPI data ready in Master mode
VCC_LOGIC SPI 1 clock
38A
GND
-
-
39A
UART1_TXD
O
VCC_LOGIC Serial transmit signal UART 1
40A
UART1_RTS
O
VCC_LOGIC Request to send UART 1
41A
GND
-
-
42A
HAD_SEL/AC_INT
43A
SSI1_TXDAT
5V
USB VBUS Voltage
USB transceiver cable interface, DUSB transceiver cable interface, D+
USB on the go transceiver cable ID
resistor connection
0
Ground 0V
Ground 0V
Ground 0V
Ground 0V
I/O- VCC_LOGIC AC97 Interrupt Input
O VCC_LOGIC AC97 Transmit Output
I
VCC_LOGIC AC97 Receive Input
44A
SSI1_RXDAT
45A
GND
46A
GPIO0_IRQ
I/O
VCC_LOGIC GPIO0 (µC port PC31)
47A
GPIO2_IRQ
I/O
VCC_LOGIC GPIO2 (µC port PE5)
48A
X_WAKEUP
I
VCC3V3
Wakeup Interrupt Input (µC port PC15)
49A
GND
-
-
Ground 0V
50A
X_BOOT1
I
-
Boot-Mode Input
-
© PHYTEC Messtechnik GmbH 2010
-
Ground 0V
L-731e_1
19
phyCARD-S [PCA-A-S1-xxx]
PIN ROW X2B
PIN #
SIGNAL
I/O
SL
DESCRIPTION
1B
VCC_3V3
-
Power
3.3V Primary Voltage Supply Input
2B
VCC_3V3
-
Power
3.3V Primary Voltage Supply Input
3B
-
Power
3.3V Primary Voltage Supply Input
4B
VCC_3V3
GND
-
-
Ground 0V
5B
NVDD7_12_14
O
VCC_LOGIC
Display vertical synchronization pulse
6B
VBAT
-
Power
Standby Voltage Input
7B
X_#RESET_OUT
-
VCC_LOGIC
Active low Reset output
8B
GND
-
-
Ground 0V
9B
TXOUT1+
O
LVDS
LVDS Chanel 0 positive Output
10B
TXOUT1-
O
LVDS
LVDS Chanel 0 negative Output
11B
TXOUT3+
O
LVDS
LVDS Chanel 3 positive Output
12B
TXOUT3-
O
LVDS
LVDS Chanel 3 negative Output
13B
GND
-
-
Ground 0V
14B
RXIN+
O
LVDS
LVDS Receive positive Input for
Camera
15B
RXIN-
O
LVDS
LVDS Receive negative Input for
Camera
16B
LOCK
O
VCC_LOGIC
Lock Output for Camera Interface
17B
X_I2C_DATA
I/O
VCC_LOGIC
I2C Data
18B
GND
-
Ground 0V
-
19B
X_ETH_LINK
X_ETH_RX+
O VCC3V3
I (O) VCC3V3
Ethernet Speed Indicator (Open Drain)
20B
21B
X_ETH_RX-
I (O) VCC3V3
Receive negative input (normal)
Transmit negative output (reversed)
22B
GND
-
-
Ground 0V
23B
X_USB_HS_/PSW2
O
VCC_LOGIC
USB-HOST Power switch output open
drain
24B
X_USB_HS_FAULT2
I
VCC_LOGIC
USB-HOST over current input signal
25B
GND
-
-
Ground 0V
26B
X_#SUSP_RAM
OC
VCC_LOGIC
Suspend to RAM Open Collector
Output (µC port PC16)
27B
X_UDM2
I/O
28B
X_UDP2
I/O
29B
X_#PWR_OFF
OC
30B
GND
20
-
VCC_LOGIC
-
Receive positive input (normal)
Transmit positive output (reversed)
USB
HOST
transceiver
cable
interface, DUSB
HOST
transceiver
cable
interface, D+
Power Off Open Collector Output
(µC port PC17)
Ground 0V
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Pin Description
31B
X_SD2_D1
I/O
VCC_LOGIC
SD/MMC Data line both in 1-bit and
4-bit mode
32B
X_SD2_D3
I/O
VCC_LOGIC
SD/MMC Data line both in 1-bit and
4-bit mode
33B
X_SD2_CMD
O
VCC_LOGIC
SD/MMC
Command
MMC/SD/SDIO
34B
GND
-
-
Ground 0V
35B
X_CSPI1_SS1
O
VCC_LOGIC
SPI 1 Chip select 1
36B
X_CSPI1_MOSI
I/O
VCC_LOGIC
37B
X_CSPI1_MISO
I/O
VCC_LOGIC
SPI 1 Master data out; slave data in
SPI 1 Master data in; slave data out
38B
GND
-
-
Ground 0V
39B
UART1_RXD
I
VCC_LOGIC
Serial data receive signal UART 1
40B
UART1_CTS
I
VCC_LOGIC
Clear to send UART 1
41B
GND
-
-
Ground 0V
42B
SSI1_CLK
I
VCC_LOGIC
AC97 Clock
43B
SSI1_FS
O
VCC_LOGIC
AC97 SYNC
44B
SSI1_RES
O
VCC_LOGIC
AC97 Reset
45B
GND
-
-
Ground 0V
46B
X_SD2_CD
I
VCC_LOGIC
SD/MMC
Card
MMC/SD/SDIO
47B
GPIO1_IRQ
I/O
VCC_LOGIC
GPIO1 (µC port PC25)
48B
X_ONEWIRE
-
VCC_LOGIC
Hardware Introspection Interface
for internal use only
49B
GND
-
-
Ground 0V
50B
Not connected
-
-
Pin left unconnected
Table 3:
Detect
for
for
Pin-out of the phyCARD-Connector X2
© PHYTEC Messtechnik GmbH 2010
L-731e_1
21
phyCARD-S [PCA-A-S1-xxx]
3 Jumpers
For configuration purposes, the phyCARD-S has 11 solder jumpers,
some of which have been installed prior to delivery. Figure 5
illustrates the numbering of the solder jumper pads, while Figure 6
and Figure 7 indicate the location of the solder jumpers on the board.
7 solder jumpers are located on the top side of the module (opposite
side of connectors) and 3 solder jumpers are located on the bottom
side of the module (connector side). Table 4 below provides a
functional summary of the solder jumpers which can be changed to
adapt the phyCARD-S to your needs. It shows their default positions,
and possible alternative positions and functions. A detailed description
of each solder jumper can be found in the applicable chapter listed in
the table.
Note:
Jumpers not listed should not be changed as they are installed with
regard to the configuration of the phyCARD-S.
Figure 5:
Typical jumper pad numbering scheme
e.g.:
e.g.:
If manual jumper modification is required please ensure that the board
as well as surrounding components and sockets remain undamaged
while de-soldering. Overheating the board can cause the solder pads to
loosen, rendering the module inoperable. Carefully heat neighboring
connections in pairs. After a few alternations, components can be
removed with the solder-iron tip. Alternatively, a hot air gun can be
used to heat and loosen the bonds.
22
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Jumpers
Please pay special attention to the "TYPE" column to ensure you are
using the correct type of jumper (0 Ohms, 10k Ohms, etc…). The
jumpers are either 0805 package or 0402 package with a 1/8W or
better power rating.
J4
J3
J5
U35
U28
J2
TP3
TP2
TP1
U26
U24
J6
U34
U25
1
1
J
X1
J7
J8
U33
Figure 6:
U16
Jumper locations (top view)
© PHYTEC Messtechnik GmbH 2010
L-731e_1
23
phyCARD-S [PCA-A-S1-xxx]
J10
U29
U32
U30
TP4
J9
X2
U38
U31
J1
U23
Figure 7:
24
U36 U37
Jumper locations (bottom view)
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Jumpers
The jumpers (J = solder jumper) have the following functions:
Jumper
J1
open
closed
Description
J1 connects the reset input of the Ethernet PHY (U38)
with GPIO PC30. Thereby it is possible to perform a
reset of the Ehernet PHY, not only by hardware, but
also by software.
open
closed
9.4.2
0R
(0402
)
7.3.2
EEPROM U28 is write protected
EEPROM U28 is not write protected
J3, J4, J3 and J5 define the slave addresses (A0 toA2) of
the serial memory U28 on the I2C2 bus. In the highnibble of the address, I2C memory devices have the
slave ID 0xA. The low-nibble is build from A2, A1, A0,
and the R/W bit. .
all 2+3 A0 = 0, A1 = 1, A2= 0, => 0x2 is selected
J4,
J5
other
settings
Chapter
0R
(0402
)
Software reset of the Ethernet PHY
disabled
Software reset of the Ethernet PHY
possible via GPIO PC30
J2 connects pin 7 of the serial memory at U28 to GND.
On many memory devices pin 7 enables/disables the
activation of a write protect function.
It is not guaranteed that the standard serial memory
populating the phyCARD-S will have this write
protection function.
Please refer to the corresponding memory data sheet
for more detailed information.
J2
Type
0R
(0402
)
as the low-nibble of the EEPROM's
address
please refer to Table 9 to find alternative
addresses resulting from other combinations
of jumpers J3, J4, and J5
7.3.1
J6 allows to attach a programming voltage to the IC
Identification Module (IIM) for programming
J6
open
closed
0R
(0805
and/or overriding identification and control
)
information stored in on-chip fuse elements.
VDD_FUSE not connected
Only close Jumper when burning of fuses
is required
© PHYTEC Messtechnik GmbH 2010
L-731e_1
25
phyCARD-S [PCA-A-S1-xxx]
Jumper
J9
1+2
2+3
1+2
2+3
1+2
2+3
Table 4:
Chapter
10k
(0805
)
12.1
10k
(0805
)
rising edge strobe used for the LVDS
camera signals
falling edge strobe used for the LVDS
camera signals
J11 selects either signal OE_ACD, or PS as data enable
of the display interface
J11
Type
rising edge strobe used for the LVDS
display signals
falling edge strobe used for the LVDS
display signals
J10 selects rising, or falling edge strobe for the LVDS
Deserializer at U29 used for the display connectivity of
the phyCARD-S
J10
26
Description
J9 selects rising, or falling edge strobe for the LVDS
Transmitter at U32 used for the display connectivity of
the phyCARD-S.
13.1
0R
(0805
)
12.1
OE_ACD used as data enable
PS used as data enable
Jumper settings
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Power
4 Power
The phyCARD-S operates off of a single power supply voltage.
The following sections of this chapter discuss the primary power pins
on the phyCARD-Connector X2 in detail.
4.1 Primary System Power (VCC_3V3)
The phyCARD-S operates off of a primary voltage supply with a
nominal value of +3.3V. On-board switching regulators generate the
1.3V, 1.45V, 1,5V, 1.8V, and 2.775V voltage supplies required by the
i.MX27 MCU and on-board components from the primary 3.3V
supplied to the SBC.
For proper operation the phyCARD-S must be supplied with a voltage
source of 3.3V ±5 % with 1.0 A load at the VCC pins on the
phyCARD-Connector X2.
VCC_3V3:
X2
1A, 2A, 3A, 1B, 2B, 3B
Connect all +3.3V VCC input pins to your power supply and at least
the matching number of GND pins.
Corresponding GND:
X2 4A, 8A, 13A, 4B, 8B, 13B
Please refer to section 1 for information on additional GND Pins
located at the phyCARD-Connector X2.
Caution:
As a general design rule we recommend connecting all GND pins
neighboring signals which are being used in the application circuitry.
For maximum EMI performance all GND pins should be connected to
a solid ground plane.
© PHYTEC Messtechnik GmbH 2010
L-731e_1
27
phyCARD-S [PCA-A-S1-xxx]
4.2 Standby Voltage (VBAT)
For applications requiring a standby mode a secondary voltage source
of 3.3V can be attached to the phyCARD-S at pin X2B6. This voltage
source is supplying the core and on-chip peripherals of the i.MX27
(e.g. RTC, PLL, etc.), as well as the SDRAM and NAND Flash
memory while the primary system power (VCC_3V3) is removed.
Applications not requiring a standby mode can connect the VBAT pin
to the primary system power supply (VCC = 3.3V), or can leave it
open.
4.3 On-board Voltage Regulator (U33)
The phyCARD-S provides an on-board switching regulator (U33) to
source the five different voltages (1.3V, 1.45V, 1.5V, 1.8V, and
2.775V) required by the processor and on-board components.
Figure 8 presents a graphical depiction of the powering scheme.
The switching regulator has two input voltage rails as can be seen in
Figure 8. 3V3 and 3V3 Backup. 3V3 is supplied from the primary
voltage input pins VCC_3V3 of the phyCARD-S, whereas 3V3
Backup is supplied from the primary voltage input pins (VCC_3V3)
and the secondary voltage input pin VBAT. Not all devices on the
phyCARD-S are supplied from the switching regulator. Some, such as
the Ethernet PHY, the LVDS Transmitter, etc. are directly connected
to the primary voltage input pins VCC_3V3. The following list
summarizes the relation between the different voltage rails and the
devices on the phyCRAD-S:
External voltages: VCC_3V3 and VBAT (optional)
• VCC_3V3: 3V3
Voltage Regulator, Ethernet PHY, LVDS
Transmitter , LVDS Deserializer
• VBAT: 3V3 BACKUP Voltage Regulator
28
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Power
Internally generated voltages: 1V3, 1V45, 1V5, 1V8 and 2V775
•
1V3 on-chip RTC of the i.MX27 (RTCVDD) and 32kHz
oscillator ( OSC32VDD)
•
1V45 i.MX27 core (QVDD)
•
1V5 on-chip PLLs
•
1V8 AVDD, NVDD1_2_3_4_5 and NVDD13 of the i.MX27,
DDR SDRAM, NAND Flash
•
2V775 NVDD6_8_9_10, NVDD7_12_14, NVDD15 and 26MHz
oscillator of the i.MX27, USB-Transceiver, I2C EEPROM
1,45V
3V3 Backup *
i.MX27 Core
DC/DC
Converter
1,8V
AVDD; NVDD1_2_3_4_5; NVDD13;
DDR SDRAM; NAND Flash
DC/DC
Converter
2,775V
3V3 **
NVDD6_8_9_10; NVDD7_12_14; NVDD15;
26MHz Oscillator; USB-Transceiver; I2C EEPROM
DC/DC
Converter
1,5V
on-chip PLLs
DC/DC
Converter
1,3V
RTC; 32kHz Oscillator
DC/DC
Converter
POE Reset
RESET
Supervisor
RESET
*: supplied from VCC_3V3 and VBAT
**: supplied from VCC_3V3
TPS65053
Figure 8:
Power Supply Diagram
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phyCARD-S [PCA-A-S1-xxx]
4.4 Supply Voltage for external Logic
The voltage level of the phyCARDs logic circuitry is VCC_LOGIC
(2.775V) which is generated on-board. In order to allow connecting
external devices to the phyCARD-S without the need of another
voltage source in addition to the primary supply this voltage is brought
out at pins X2A5 and X2B5 of the phyCARD-Connector.
Use of level shifters supplied with VCC_LOGIC allows converting
the signals according to the needs on the custom target hardware.
Alternatively signals can be connected to an open drain circuitry with
a
pull-up
resistor
attached
to
VCC_LOGIC.
30
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Power Management
5 Power Management
The phyCARD-S was designed to support applications requiring a
power management. Three pins of the X-Arc bus are designated for
this purpose. X_#PWR_OFF and X_#SUSP_RAM are output pins
which can be used to indicate the power status of the phyCARD-S,
whereas X_WAKEUP is an input pin to apply a wake up signal to the
phyCARD-S.
All three pins lead to GPIOs of the i.MX. Thus their functionality can
be programmed to your needs.
The following table shows the location of the power management pins
on the phyCARD-Connector and the corresponding GPIOs of the
i.MX27.
Pin Signal
#
48A X_WAKEUP
26B
29B
I/O SL
Description
Wakeup
Interrupt
Input
(µC port PC15)
X_#SUSP_RA OC VCC_LOGIC Suspend to RAM Open
Collector
Output
M
(µC port PC16)
X_#PWR_OF OC VCC_LOGIC Power Off Open Collector
I
VCC3V3
F
Table 5:
Output (µC port PC17)
Power Management Pins
With the two output signals nPower_Off (pin X_#PWR_OFF) and
nSuspend_to_RAM (pin X_#SUSP_RAM) three different power
states can be defined.
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phyCARD-S [PCA-A-S1-xxx]
Power State
Power On
Standby
Off
Signal
nSuspend_to_RAM
nPower_Off
VCC_3V3
VBAT
High
High
On
X
Low
High
Off
On
X
Low
Off
Off
X=don’t care
Table 6:
Power States
Please refer to the chapter "Power Management" in the phyCARD
Design-In Guide for more information about the implementation of
the power management into your design.
Caution:
According to the specification for the phyCARD family writing
custom software to utilize pins X_#SUSP_RAM and X_#PWR_OFF
requires them to be configured as Open Collector Output.
32
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Start-Up System Configuration
6 System Configuration and Booting
Although most features of the i.MX27 microcontroller are configured
and/or programmed during the initialization routine, other features,
which impact program execution, must be configured prior to
initialization via pin termination.
The system start-up configuration includes:
• Clock/PLL configuration
• Boot device select configuration
• NAND Flash configuration
During the reset cycle the operational system boot mode of the
i.MX27 processor is determined by the configuration of the four
external input pins, BOOT[3:0]. The settings of these pins control
where the system is boot from and the memory port size.
The following table shows the different boot modes, which can be
selected by configuring the four external input pins, BOOT[3:0] of the
i.MX27. Please note that only the ones in bold letters are applicable
for the phyCARD-S.
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phyCARD-S [PCA-A-S1-xxx]
Boot Mode Selection
BOOT[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
Table 7:
34
Boot Mode/Device
Bootstrap from UART/USB
Reserved
8-bit NAND Flash (2 Kbyte
page)
16-bit NAND Flash (2 Kbyte
page)
16-bit NAND Flash (512 bytes
page)
16-bit CS0 (NOR-Flash)
32-bit CS0
8 bit NAND Flash (512 bytes
page)
Reserved
per
per
per
per
Boot Modes of i.MX27 module
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Start-Up System Configuration
The i.MX27 processor always begins fetching instruction from the
address 0x00000000 after reset. The BOOT[3:0] pins control the
memory region that is mapped to the address 0x0 as shown in Table 7.
These boot modes information are registered during the system reset.
When an external chip select is enabled by the BOOT[3:0] pins, the
reset vector 0x0 will jump to the corresponding boot address space.
The standard phyCARD-S module with 64MB NAND Flash comes
with a boot configuration of ‘0111’, so the system will boot from the
8-bit NAND Flash at CS0, the phyCARD-S module with more than
128MB NAND flash comes with a boot configuration of ‘0010’.
The configuration circuitry (pull-up or pull-down resistors) are located
on the phyCARD module. They are already set for booting from the
NAND Flash, so no further settings are necessary.
The boot mode input (X2A50: X_BOOT1) allows for starting the
bootstrap program residing in the internal ROM of the i.MX27 rather
than booting from NAND Flash without modifying the circuitries on
the phyCARD-S. In order to start the bootstrap program a low level
must be applied to the boot mode input.
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phyCARD-S [PCA-A-S1-xxx]
7 System Memory
The phyCARD-S provides three types of on-board memory:
• LP-DDR-SDRAM:
• NAND Flash:
• I²C-EEPROM:
32MByte
(up to 256MByte)
128MByte
(up to 1GByte)
4KB
(up to 32KByte)
The following sections of this chapter detail each memory type used
on the phyCARD-S.
7.1 LP-DDR-SDRAM (U24, U25)
The RAM memory of the phyCARD-S in comprised of two 16-bit
wide LP-DDR-SDRAM chips at U24 and U25. They are connected to
the special SDRAM interface of the i.MX27 processor, configured for
32-bit access, and operating at the maximum frequency of 133MHz.
The SDRAM memory is accessed via the second AHB port using chip
select signal /CSD0 (/CS2) starting at 0xA000 0000.
Typically the LP-DDR-SDRAM initialization is performed by a boot
loader or operating system following a power-on reset and must not be
changed at a later point by any application code. When writing custom
code independent of an operating system or boot loader, SDRAM
must be initialized by accessing the appropriate SDRAM
configuration registers on the i.MX27 controller. Refer to the i.MX27
Reference Manual for accessing and configuring these registers.
36
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System Memory
7.2 NAND Flash Memory (U16)
Use of Flash as non-volatile memory on the phyCARD-S provides an
easily reprogrammable means of code storage. The following Flash
devices can be used on the phyCARD-S:
Manufacturer
NAND Flash P/N
ST
Microelectronics
NAND01GR3B2CZA6
E
Table 8:
Density
(MByte)
128
Compatible NAND Flash devices
Additionally, any parts that are footprint (VFBGA) and functionally
compatible with the NAND Flash devices listed above may also be
used with the phyCARD-S.
These Flash devices are programmable with 1.8 V. No dedicated
programming voltage is required.
As of the printing of this manual these NAND Flash devices generally
have a life expectancy of at least 100,000 erase/program cycles and a
data retention rate of 10 years.
The NAND Flash memory is connected to the NF bus. This chip select
signal is used for boot operation.
7.3 I²C EEPROM (U28)
The phyCARD-S is populated with a ST 24W32C 1 non-volatile
4KByte EEPROM with an I²C interface at U28. This memory can be
used to store configuration data or other general purpose data. This
device is accessed through I²C port 2 on the i.MX27. The control
registers for I²C port 2 are mapped between addresses 0x1001 D000
1:
See the manufacturer’s data sheet for interfacing and operation.
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37
phyCARD-S [PCA-A-S1-xxx]
and 0x1001 DFFF. Please see the i.MX27 Reference Manual for
detailed information on the registers.
Three solder jumpers are provided to set the lower address bits: J3, J4
and J5. Refer to section 7.3.1 for details on setting these jumpers.
Write protection to the device is accomplished via jumper J2. Refer to
section 7.3.2 for further details on setting this jumper.
7.3.1 Setting the EEPROM Lower Address Bits (J3, J4,
J5)
The 32KB I²C EEPROM populating U28 on the phyCARD-S module
has the capability of configuring the lower address bits A0, A1, and
A2. The four upper address bits of the device are fixed at ‘1010’ (see
ST 24W32C data sheet). The remaining three lower address bits of the
seven bit I²C device address are configurable using jumpers J3, J4 and
J5. J4 sets address bit A0, J3 address bit A1, and J5 address bit A2.
Table 9 below shows the resulting seven bit I²C device address for the
eight possible jumper configurations.
U28 I²C Device Address
1010 010
1010 011
1010 000
1010 001
1010 110
1010 111
1010 100
1010 101
Table 9:
1:
38
J5
2+3
2+3
2+3
2+3
1+2
1+2
1+2
1+2
J3
2+3
2+3
1+2
1+2
2+3
2+3
1+2
1+2
J4
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
U28 EEPROM I²C address via J3, J4, and J5 1
Defaults are in bold blue text
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System Memory
7.3.2 EEPROM Write Protection Control (J2)
Jumper J2 controls write access to the EEPROM (U28) device.
Closing this jumper allows write access to the device, while removing
this jumper will cause the EEPROM to enter write protect mode,
thereby disabling write access to the device.
The following configurations are possible:
EEPROM Write Protection State
Write access allowed
Write protected
Table 10:
J2
closed
open
EEPROM write protection states via J2 1
7.4 Memory Model
There is no special address decoding device on the phyCARD-S,
which means that the memory model is given according to the
memory mapping of the i.MX27. Please refer to the i.MX27 Reference
Manual for more information on the memory mapping.
1:
Defaults are in bold blue text
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39
phyCARD-S [PCA-A-S1-xxx]
8 SD / MMC Card Interfaces
The X-Arc bus features an SD / MMC Card interface. On the
phyCARD-S the interface signals extend from the controllers second
Secure Digital Host Controller (SD2) to the phyCARD-Connector.
Table 11 shows the location of the different interface signals on the
phyCARD-Connector. The Secure Digital Host Controller is fully
compatible with the SD Memory Card Specification 1.0 and SD I/O
Specification 1.0 with 1 and 4 channel(s) and supports data rates from
25 Mbps to 100 Mbps (refer to the i.MX27 Reference Manual for more
information).
Due to compatibility reasons a card detect signal (X_SD2_CD) is
added to the SD / MMC Card Interface. This signal connects to port
PC29 of the i.MX27.
Pin #
X2A3
1
X2A3
2
X2A3
3
X2B3
1
X2B3
2
X2B3
3
X2B4
6
Signal
I/O SL
Description
X_SD2_D0 I/O VCC_LOGIC SD/MMC Data line both in 1-bit
and 4-bit mode
X_SD2_D2 I/O VCC_LOGIC SD/MMC Data line both in 1-bit
and 4-bit mode
Clock
for
X_SD2_CL O VCC_LOGIC SD/MMC
MMC/SD/SDIO
K
X_SD2_D1 I/O VCC_LOGIC SD/MMC Data line both in 1-bit
and 4-bit mode
X_SD2_D3 I/O VCC_LOGIC SD/MMC Data line both in 1-bit
and 4-bit mode
Command
X_SD2_CM O VCC_LOGIC SD/MMC
MMC/SD/SDIO
D
X_SD2_CD I VCC_LOGIC SD/MMC Card Detect
Table 11:
40
for
for
MMC/SD/SDIO
Location of SD/ MMC Card interface signals
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SD / MMC Card Interfaces
Note:
The signal level of the SD / MMC card interface is 2.775V. Thus
integration of an SD / MMC card slot on custom target hardware
requires level shifters supplied with VCC_LOGIC (X2A5 and X2B5)
at one of the supply rails.
Please refer to the chapter "SD / MMC" in the phyCARD Design-In
Guide for more information about connecting an SD / MMC Card slot
to the phyCARD-S.
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phyCARD-S [PCA-A-S1-xxx]
9 Serial Interfaces
The phyCARD-S provides seven serial interfaces some of which are
equipped with a transceiver to allow direct connection to external
devices:
1.
2.
3.
4.
5.
6.
7.
High speed UART (TTL, derived from UART1 of the i.MX27)
with up to 4.125Mbit/s and hardware flow control (RTS and CTS
signals)
High speed USB OTG transceiver supporting the i.MX27 USB
OTG interface
High speed USB HOST transceiver supporting the i.MX27 USB
Host interface
Auto-MDIX enabled 10/100 Ethernet PHY supporting the
i.MX27 Ethernet MAC
I2C interface (derived from first I2C port of the i.MX27)
Serial Peripheral Interface (SPI) interface (extended from the first
SPI modul of the i.MX27)
Synchronous Serial Interface (SSI) with AC97 support
(originating from the synchronous serial interface of the i.MX27)
The following sections of this chapter detail each of these serial
interfaces and any applicable configuration jumpers.
Caution:
Please pay special attention to the Signal Level (SL) column in the
following tables. Some of the serial interfaces signal level is
VCC_LOGIC, which is 2.775V and which is not identical with the
voltage level of the primary supply voltage of the phyCARD-S. When
connecting these interfaces to external devices level shifters supplied
with VCC_LOGIC (X2A5 and X2B5) at one of the supply rails should
be used.
Please refer to the phyCARD Design-In Guide for more information
about using the serial interfaces of the phyCARD-S in customer
applications.
42
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Serial Interfaces
9.1 Universal Asynchronous Interface
The phyCARD-S provides a high speed universal asynchronous
interface with up to 4.125Mbit/s and hardware flow control (RTS and
CTS signals). The following table shows the location of the signals on
the phyCARD- Connector.
PIN #
SIGNAL
I/O
SL
DESCRIPTION
X2A39 UART1_TXD O VCC_LOGIC Serial transmit signal UART 1
X2A40 UART1_RTS O VCC_LOGIC Request to send UART 1
X2B39 UART1_RXD I VCC_LOGIC Serial data receive signal
X2B40 UART1_CTS
Table 12:
I
UART 1
VCC_LOGIC Clear to send UART 1
Location of the UART signals
The signals extend from UART1 of the i.MX27 directly to the
phyCARD-Connector without conversion to RS-232 level. External
RS-232 transceivers must be attached by the user if RS-232 levels are
required.
9.2 USB-OTG Transceiver (U34)
The phyCARD-S is populated with an NXP ISP1504 USB On-The-Go
High-Speed transceiver at U34 which is capable of high speed, full
speed, and low speed data transmission. The ISP1504 functions as the
transceiver for the i.MX27 USB-OTG Controller. An external USB
Standard-A (for USB host), USB Standard-B (for USB device), or
USB mini-AB (for USB OTG) connector is all that is needed to
interface the phyCARD-S USB OTG functionality. The applicable
interface signals can be found on the phyCARD-Connector as shown
in Table 13.
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phyCARD-S [PCA-A-S1-xxx]
PIN #
SIGNAL
I/O
SL
DESCRIPTION
X2A23 X_USB_HS_/PS
O VCC3V3 USB-OTG Power switch
output open drain
W
X2A24 X_USB_HS_FAU I VCC3V3 USB-OTG over current input
signal
LT
USB VBUS Voltage
X2A26 X_VBUS
I 5V
USB
transceiver
cable
X2A27 X_UDM
I/O
interface, D-
X2A28 X_UDP
I/O
X2A29 X_UID
I
Table 13:
USB transceiver cable
interface, D+
USB on the go transceiver
cable
ID
resistor
connection
Location of the USB-OTG signals
9.3 USB-Host Transceiver (U35)
The phyCARD-S is populated with a second NXP ISP1504 USB Host
High-Speed transceiver (U35) supporting high speed, full speed, and
low speed data rates. The ISP1504 functions as the transceiver for the
second Host Controller (HOST2) of the i.MX27. An external USB
Standard-A (for USB host connector is all that is needed to interface
the phyCARD-S USB Host functionality. The applicable interface
signals (D+/D-/ /PSW/FAULT) can be found on the phyCARDConnector..
44
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Serial Interfaces
PIN #
X2B2
3
X2B2
4
X2B2
7
X2B2
8
SIGNAL
I/O
SL
DESCRIPTION
X_USB_HS_/PSW O VCC_LOGIC USB-HOST Power switch
output open drain
2
X_USB_HS_FAUL I VCC_LOGIC USB-HOST over current
input signal
T2
USB HOST transceiver
X_UDM2
I/O
cable interface, D-
X_UDP2
Table 14:
I/O
USB
transceiver
interface, D+
HOST
cable
Location of the USB-Host signals
9.4 Ethernet Interface
Connection of the phyCARD-S to the world wide web or a local area
network (LAN) is possible using the integrated FEC (Fast Ethernet
Controller) of the i.MX27. The FEC operates with a data transmission
speed of 10 or 100 Mbit/s.
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phyCARD-S [PCA-A-S1-xxx]
9.4.1 PHY Physical Layer Transceiver (U38)
With a physical layer transceiver mounted at U38 the phyCARD-S has
been designed for use in 10Base-T and 100Base-T networks. The
10/100Base-T interface with its LED signals extends to phyCARDConnector X2.
PIN #
X2A1
9
X2A2
0
X2A2
1
X2B1
9
X2B2
0
X2B2
1
SIGNAL
I/O
SL
DESCRIPTION
X_ETH_SPEE O VCC3V3 Ethernet Speed Indicator (Open
Drain)
D
X_ETH_TX+ O (I) VCC3V3 Transmit positive output (normal)
Receive positive input (reversed)
X_ETH_TXX_ETH_LINK
O (I) VCC3V3 Transmit negative output (normal)
Receive negative input (reversed)
O
VCC3V3 Ethernet Speed Indicator (Open
Drain)
X_ETH_RX+ I (O) VCC3V3 Receive positive input (normal)
Transmit positive output (reversed)
X_ETH_RX-
Table 15:
I (O) VCC3V3 Receive negative input (normal)
Transmit
(reversed)
negative
output
Location of the Ethernet signals
The Ethernet PHY provides MII/RMII/SMII interfaces to transmit and
receive data. In addition the PHY also supports HP Auto-MDIX
technology, eliminating the need for the consideration of a direct
connect LAN cable, or a cross-over patch cable. It detects the TX and
RX pins of the connected device and automatically configures the
PHY TX and RX pins accordingly. The Ethernet PHY also features
LinkMD cable diagnostics, which allows detection of common cabling
plant problems such as open and short circuits.
The physical memory area for the Fast Ethernet controller is defined
in Table 16.
46
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Serial Interfaces
Address
0x1002_B + 0x0001FF
0x1002_B + 0x2003FF
Table 16:
Function
Control/Status Registers
MIB Block Counters
Fast Ethernet controller memory map
In order to connect the module to an existing 10/100Base-T network
some external circuitry is required. The required 49,9 Ohm +/-1%
termination resistors on the analog signals (ETH_RX±, ETH_TX±)
are already populated on the module. Connection to an external
Ethernet magnetics should be done using very short signal traces. The
TPI+/TPI- and TPO+/TPO- signals should be routed as 100 Ohm
differential pairs. The same applies for the signal lines after the
transformer circuit. The carrier board layout should avoid any other
signal lines crossing the Ethernet signals.
An example for the external circuitry is shown in the phyCARD's
Design Guide.
If you are using the applicable Carrier Board for the phyCARD-S (part
number PBA-A-01), the external circuitry mentioned above is already
integrated on the board (refer to section 17.3.4).
Caution!
Please see the datasheet of the Ethernet PHY as well as the
phyCARD's Design Guide when designing the Ethernet transformer
circuitry.
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phyCARD-S [PCA-A-S1-xxx]
9.4.2 Software Reset of the Ethernet PHY (J1)
J1 connects the reset input of the Ethernet PHY (U38) with GPIO
PC30. Thereby it is possible to perform a reset of the Ethernet PHY,
not only by hardware, but also by software.
The following configurations are possible:
Software reset of the Ethernet PHY
Software reset disabled
Software reset possible via GPIO PC30
Table 17:
J1
open
closed
Software Reset of the Ethernet PHY 1
9.4.3 MAC Address
In a computer network such as a local area network (LAN), the MAC
(Media Access Control) address is a unique computer hardware
number. For a connection to the Internet, a table is used to convert the
assigned IP number to the hardware's MAC address.
In order to guarantee that the MAC address is unique, all addresses are
managed in a central location. PHYTEC has acquired a pool of MAC
addresses. The MAC address of the phyCARD-S is located on the bar
code sticker attached to the module. This number is a 12-digit HEX
value.
1
Defaults are in bold blue text
48
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Serial Interfaces
9.5 I2C Interface
The Inter-Integrated Circuit (I2C) interface is a two-wire, bidirectional
serial bus that provides a simple and efficient method for data
exchange among devices. The i.MX27 contains two identical and
independent I2C modules. The interface of the first module is available
on the phyCARD-Connector., whereas the second module connects to
the on-board EEPROM (refer to section 7.3). The following table lists
the I2C port on the phyCARD-Connector:
PIN #
SIGNAL
X2A17 X_I2C_CLK
X2B17 X_I2C_DATA
Table 18:
I/O
SL
DESCRIPTION
O VCC_LOGIC I2C Clock Output
I/O VCC_LOGIC I2C Data
I2C Interface Signal Location
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phyCARD-S [PCA-A-S1-xxx]
9.6 SPI Interface
The Serial Peripheral Interface (SPI) interface is a six-wire,
bidirectional serial bus that provides a simple and efficient method for
data exchange among devices. The i.MX27 contains three SPI
modules. The interface signals of the first module (CSPI1) are made
available on the phyCARD-Connector. This module is Master/Slave
configurable. Due to the specification of the X-Arc bus, only two of
the three chips-selects are available on the phyCARD-Connector. The
following table lists the SPI signals on the phyCARD-Connector:
PIN #
X2A3
5
X2B3
5
X2A3
6
X2A3
7
X2B3
6
X2B3
7
SIGNAL
I/O
SL
DESCRIPTION
X_CSPI1_SS0 O VCC_LOGIC SPI 1 Chip select 0
X_CSPI1_SS1
O VCC_LOGIC SPI 1 Chip select 1
X_#CSPI1_R O VCC_LOGIC SPI 1 SPI data ready in Master
mode
DY
X_CSPI1_SC O VCC_LOGIC SPI 1 clock
LK
X_CSPI1_MO I/O VCC_LOGIC SPI 1 Master data out; slave
data in
SI
X_CSPI1_MI I/O VCC_LOGIC SPI 1 Master data in; slave
SO
data out
Table 19:
SPI Interface Signal Location
9.7 Synchronous Serial Interface (SSI)
The Synchronous Serial Interface (SSI) interface of the phyCARD-S
is a full-duplex, serial port that allows to communicate with a variety
of serial devices, such as standard codecs, digital signal processors
(DSPs), microprocessors, peripherals, and popular industry audio
codecs that implement the inter-IC sound bus standard (I2S) and Intel
AC97 standard.
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Serial Interfaces
With reference to the X-Arc bus specification, the main purpose of
this interface is to connect to an external codec, such as AC97. In
AC97 mode the clock and the frame sync signal are synchronous for
the receive and transmit sections of the i.MX27 SSI module. Thus
only four signals extend from the i.MX27 Digital Audio MUX
(AUDMUX)
to
the
phyCARD-Connector
(SSI1_TXDAT,
SSI1_RXDAT, SSI1_CLK, SSI1_FSTXDAT). AC_INT and
SSI1_RES are two additional pins assisting the functionality of this
interface. AC_INT is used as input and output. As output it signals
which codec is supported by the phyCARD. Use of this pin as an input
enables to attach an external interrupt to port PC24. SSI1_RES is
connected to port PC28 of the i.MX27allowing to perform a software
reset for the device attached to the interface. Please also read the
phyCARD Design-In Guide for more information about how to use
the AC97 interface.
Pin #
X2A4
2
X2A4
3
X2A4
4
X2B4
2
X2B4
3
X2B4
4
Signal
AC_INT
I/O SL
Description
I/O VCC_LOGIC AC97 Interrupt Input
SSI1_TXD
AT
SSI1_RXD
AT
SSI1_CLK
O VCC_LOGIC AC97 Transmit Output
SSI1_FS
O VCC_LOGIC AC97 SYNC
SSI1_RES
O VCC_LOGIC AC97 Reset
Table 20:
I
VCC_LOGIC AC97 Receive Input
I
VCC_LOGIC AC97 Clock
SSI Interface Signal Location
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phyCARD-S [PCA-A-S1-xxx]
10 General Purpose I/Os
The X-Arc bus provides 3 GPIO / IRQ signals. Table 21 shows the
location of the GPIO / IRQ pins on the phyCARD-Connector, as well
as the corresponding ports of the i.MX27.
Pin #
X2A4
6
X2A4
7
X2B4
7
Signal
GPIO0_IR
Q
GPIO2_IR
Q
GPIO1_IR
Q
Table 21:
I/O SL
Description
I/O VCC_LOGIC GPIO0 connected to µC port PC31
I/O VCC_LOGIC GPIO2 connected to µC port PE5
I/O VCC_LOGIC GPIO1 connected to µC port PC25
Location of GPIO and IRQ pins
As can be seen in the table above the voltage level is VCC_LOGIC,
which is 2.775V. In other words VCC_LOGIC is not identical with
the supply voltage of the phyCARD-S. To avoid mismatch of the
different voltage levels external devices connected to these pins
should be supplied by VCC_LOGIC available at X2A5 and X2B5
(refer to section 4.4). Alternatively an open drain circuit with a pull-up
resistor attached to VCC_LOGIC can be connected to the GPIOs of
the phyCARD_S.
Please refer to the chapter "GPIOs" in the phyCARD Design-In Guide
for more information about how to integrate the GPIO pins in your
design.
52
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Debug Interface
11 Debug Interface (X1)
The phyCARD-S is equipped with a JTAG interface for downloading
program code into the external flash, internal controller RAM or for
debugging programs currently executing. The JTAG interface extends
to a 2.0 mm pitch pin header at X1 on the edge of the module PCB.
Figure 9 and Figure 10 show the position of the debug interface
(JTAG connector X1) on the phyCARD-S module.
J4
J3
J5
U35
U28
J2
TP3
TP2
TP1
U26
U24
J6
U34
U25
X1
J7
J8
U33
Figure 9:
U16
JTAG interface at X1 (top view)
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53
phyCARD-S [PCA-A-S1-xxx]
J10
U29
TP4
1
U32
U30
J9
X2
U38
U31
J1
U23
Figure 10:
U36 U37
JTAG interface at X1 (bottom view)
Pin 1 of the JTAG connector X1 is on the connector side of the
module. Pin 2 of the JTAG connector is on the controller side of the
module.
Note:
The JTAG connector X1 only populates phyCARD-S modules with
order code PCA-A-S1-D. JTAG connector X1 is not populated on
phyCARD modules with order code PCA-A-S1. We recommend
integration of a standard (2 mm pitch) pin header connector in the user
target circuitry to allow easy program updates via the JTAG interface.
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Debug Interface
See Table 22 for details on the JTAG signal pin assignment.
VCCLOGIC
Pin Row*
A
B
2
1
GND
GND
GND
GND
GND
GND
GND
GND
GND
4
6
8
10
12
14
16
18
20
Signal
Table 22:
3
5
7
9
11
13
15
17
19
Signal
TREF (VCCLOGIC via 100
Ohm)
x_#TRST
x_TDI
x_TMS
x_TCK
x_RTCK
x_TDO
x_#RESET
n.c.
J_DBGACK
(10k
Ohm
pulldown)
JTAG connector X1 signal assignment
*Note: Row A is on the controller side of the module and row B is on
the connector side of the module
PHYTEC offers a JTAG-Emulator adapter (order code JA-002) for
connecting the phyCARD-S to a standard emulator. The JTAGEmulator adapter extends the signals of the module's JTAG connector
to a standard ARM connector with 2 mm pin pitch. The JA-002
therefore functions as an adapter for connecting the module's nonARM-compatible JTAG connector X1 to standard Emulator
connectors.
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55
phyCARD-S [PCA-A-S1-xxx]
12 LVDS Display Interface
The phyCARD-S uses a DS90C383 4-Channel 24-Bit LVDS
Transmitter (U32) to generate LVDS-Signals from the parallel TTL
Display Interface. Thus you can connect a LVDS-Display to the
phyCARD-S. The location of the applicable interface signals
(TXOUT1-3+/TXOUT1-3-/TXCLK+/TXCLK-) can be found in the
table below.
Pin #
X2A9
X2A10
X2A11
X2A12
X2A14
X2A15
X2B9
X2B10
X2B11
X2B12
Table 23:
56
Signal
TXOUT0+
TXOUT0TXOUT2+
TXOUT2TXCLKOU
T+
TXCLKOU
TTXOUT1+
TXOUT1TXOUT3+
TXOUT3-
I/O
O
O
O
O
O
SL
Description
LVDS
LVDS Chanel 0 positive Output
LVDS
LVDS Chanel 0 negative Output
LVDS
LVDS Chanel 2 positive Output
LVDS
LVDS Chanel 2 negative Output
LVDS
LVDS Clock positive Output
O
LVDS
LVDS Clock negative output
O
O
O
O
LVDS
LVDS Chanel 0 positive Output
LVDS
LVDS Chanel 0 negative Output
LVDS
LVDS Chanel 3 positive Output
LVDS
LVDS Chanel 3 negative Output
Display Interface Signal Location
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LVDS Display Interface
12.1 Signal configuration (J9, J11)
J9 selects rising, or falling edge strobe for the LVDS Transmitter at
U32 used for the display connectivity of the phyCARD-S.
Positio Description
Type
n
1+2 rising edge strobe used for the LVDS display 10k (0805)
signals
2+3 falling edge strobe used for the LVDS display
signals
J11 selects either signal OE_ACD, or PS as data enable of the display
interface
Positio Description
n
1+2 OE_ACD used as data enable
2+3
Type
0R
(0805)
PS used as data enable
Most of the displays work with the default configuration of these
jumpers and changing them is usually not necessary.
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phyCARD-S [PCA-A-S1-xxx]
12.2 LVDS Display Interface pixel mapping
The phyCARD specification defines the pixel mapping of the LVDS
display interface. The pixel mapping equates to the OpenLDI
respectively Intel 24.0 standard. Thus you can connect 18-bit as well
as 24-bit LVDS displays to the phyCARD. Table 24 and Table 25
show the recommended pixel mapping of the LVDS display. For
further information please see the phyCARD Design Guide.
Note:
Make sure that the LVDS display you want to use provides the same
pin mapping as the phyCARD. Normally this is only important for 24bit LVDS displays because due to the organization of the LVDS pixel
mapping all common 18-bit LVDS displays should work.
18-bit LVDS Display
1
2
CLK 1
1
A0
G0
R5
A1
B1
B0
A2
DE
VSYNC
A3
0
0
Table 24:
58
4
0
R3
G4
B5
0
5
0
R2
G3
B4
0
6
1
R1
G2
B3
0
7
1
R0
G1
B2
0
6
1
R3
G4
B5
R1
7
1
R2
G3
B4
R0
Pixel mapping of 18-bit LVDS display interface
24-bit LVDS Display
1
2
CLK 1
1
A0
G2
R7
A1
B3
B2
A2
DE
VSYNC
A3
0
B1
Table 25:
3
0
R4
G5
HSYNC
0
3
0
R6
G7
HSYNC
B0
4
0
R5
G6
B7
G1
5
0
R4
G5
B6
G0
Pixel mapping of 24-bit LVDS display interface
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LVDS Camera Interface
13 LVDS Camera Interface
The phyCARD-S uses a DS92LV1212A 1-channel 10-Bit LVDS
Random Lock Deserializer (U29) to receive LVDS-Signals from a
LVDS Camera Interface. The LVDS Deserializer converts the LVDS
signal to a 10-bit wide parallel data bus and separate clock which can
be used as inputs for the i.MX27 Camera Sensor Interface. The 10-bit
wide databus consist of 8 color information bits and 2 sync bits
(HSYNC/VSYNC).
The following table shows the location of the applicable
interface signals (LVDS_CAM_MCLK, LVDS_CAM_nLOCK,
LVDS_CAM_RX+, LVDS_CAM_RX-) on the phyCARD-Connector.
Pin # Signal
I/O SL
Description
X2A16 X_CSI_MCL O VCC_LOGIC Clock Output for Camera
Interface
K
LVDS Receive positive Input
X2B14 RXIN+
O LVDS
X2B15 RXIN-
O
X2B16 LOCK
O
Table 26:
for Camera
LVDS
LVDS Receive negative Input
for Camera
VCC_LOGIC Lock Output for Camera
Interface
Camera Interface Signal Location
13.1 Signal configuration (J10)
J10 selects rising, or falling edge strobe for the LVDS Deserializer at
U29 used for the display connectivity of the phyCARD-S
Position Description
Type
1+2
rising edge strobe used for the LVDS camera 10k
(0805)
signals
2+3
falling edge strobe used for the LVDS camera
signals
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59
phyCARD-S [PCA-A-S1-xxx]
14 Technical Specifications
The physical dimensions of the phyCARD-S are represented in Figure
11. The module's profile is approximately 8.5 mm thick, with a
maximum component height of 4.0 mm on the bottom (connector)
side of the PCB and approximately 3.1 mm on the top
(microcontroller) side. The board itself is approximately 1.4 mm thick.
60mm
56mm
8mm
9.17mm
10.44mm
4mm
4mm
7.17mm
4mm
6mm
9.2mm
10.45mm
7.24mm
4mm
0.635mm
31.11mm
Ref Des
PhyCard S
Ref Des
HOLE D2.7mm
PAD D5.0mm
Figure 11:
Physical dimensions
Note:
To facilitate the integration of the phyCRAD-S into your design, the
footprint of the phyCARD-S is available upon request.
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Technical Specifications
Additional specifications:
Dimensions:
Weight:
Storage temperature:
Operating temperature:
Humidity:
Operating voltage:
Power consumption:
VCC 3.3 V/200mA typical
60 mm x 60 mm
approximately 16 g with all
optional components mounted on
the circuit board
-40°C to +125°C
0°C to +70°C (commercial)
-20°C to +85°C (industrial)
95 % r.F. not condensed
VCC 3.3V
Max. 1.0 watts
Conditions:
VCC = 3.3 V, VBAT = 0 V,
32MB LP-DDR-RAM,
64MB
NAND Flash, Ethernet, 400 MHz
CPU frequency at 20°C
These specifications describe the standard configuration of the
phyCARD-S as of the printing of this manual.
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phyCARD-S [PCA-A-S1-xxx]
Connectors on the phyCARD:
Manufacturer
Number of pins per contact rows
Molex part number (lead free)
Molex
100 (2 rows of 50 pins each)
52885-1074 (receptacle)
Two different heights are offered for the receptacle sockets that
correspond to the connectors populating the underside of the
phyCARD—i.MX27. The given connector height indicates the
distance between the two connected PCBs when the module is
mounted on the corresponding carrier board. In order to get the exact
spacing, the maximum component height (2,5 mm) on the bottom side
of the phyCORE must be subtracted.
Component height 6 mm
Manufacturer
Number of pins per contact row
Molex part number (lead free)
Molex
100 (2 rows of 50 pins each)
55091-1075/1074 (header)
Component height 10 mm
Manufacturer
Number of pins per contact row
Molex part number (lead free)
Molex
100 (2 rows of 50 pins each)
53553-1079 (header)
Please refer to the corresponding data sheets and mechanical
specifications provided by Molex (www.molex.com).
62
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Component Placement Diagram
15 Component Placement Diagram
C15
C149
C110
R37
L12
R69
C23
R68
C13
C150
J4
J3
J5
C138
U28
C148
L11
C106
U35
X5
C14
R38
C109
R14
R15
C146
C145
R24
R25 R26
C147
R31
TP3
TP2
XT1
C135
C11
C142
R75
C144
XT2
R32 R20
TP1
C93
RN12
R5
C92
RN2
R12
R39
R2
R3
RN9
R73
U26
RN3
C107
R82
C143
R1
J6
RN8
U24
C113
C91
R70
RN17 RN13
RN14 RN11
R83
RN10 RN6
R4
R27
R29
U34
X6
R19
R7
D8
C112
J2
C12
X1
U16
C87
C3
C42
C119
C118
R58
L7
C43
C45
RN4
C84
C132
R49
R63
RN16
C44
R56
C141
D5
L9
C123
R21
R41
Figure 12:
C122
R62
R60
X3
R61
C134
C99
R65
R35 R34
C111
C139
C124
L8
U33
R64
L10
C125
R33
R36
C102
C10
L4
L2
R57
R46
L1
R59
D10
C131
R55
C117
D9
J7
J8
RN1
R66
C140
C133
J11
U25
C103
C100
RN18 RN7
RN15 RN5
C108
C137
R67 C22
R6
R74
R40
C136
R81
X4
phyCARD-S component placement (top view)
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© PHYTEC Messtechnik GmbH 2010
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phyCARD-S component placement (bottom view)
C86
U37
U36
R47
C89
U23
XT3
C90
C66
R48
R50
R51
R16
R18
C153
C88
C115
J1
U31
64
Figure 13:
U38
C152
R44
C39
C38
C37
R30
R17
C34
C114
C6
R79
R11 C116
R78
C151
RN19
C33
C32
C56
C61
C2
C54
C60
C69
R13
R23
R22
C47
R77
C35
C46 C16
R10
C41
D6
R71
R80
L3
RN20
C30
C28
C29
C26
J9
C8
C50
C58
C49
X2
C21
C20
C65
C63
R76
C59
C17
R28 C5
C36
D7
C72
R8
C31
C25
C104
C24
C27
C105
C94
C67
C68
C62
C64
C57
C71
C19
C7
C48
C51
R9
C95
R45
TP4
U30
U32
C9
C18
R42
L5
C120
C127
C126
L6
C130
U29
C98
C121
C128
C129
C97
R52
C70
C101
R54
R53
J10
C96
phyCARD-S [PCA-A-S1-xxx]
Hints for Handling
16 Hints for Handling the phyCARD-S
• Modifications on the phyCARD Module
Removal of various components, such as the microcontroller and the
standard quartz, is not advisable given the compact nature of the
module. Should this nonetheless be necessary, please ensure that the
board as well as surrounding components and sockets remain
undamaged while de-soldering. Overheating the board can cause the
solder pads to loosen, rendering the module inoperable. Carefully heat
neighboring connections in pairs. After a few alternations,
components can be removed with the solder-iron tip. Alternatively, a
hot air gun can be used to heat and loosen the bonds.
Caution!
If any modifications to the module are performed, regardless of their
nature, the manufacturer guarantee is voided.
• Integrating the phyCARD into a Target Application
Successful integration in user target circuitry greatly depends on the
adherence to the layout design rules for the GND connections of the
phyCARD module. For best results we recommend using a carrier
board design with a full GND layer. It is important to make sure that
the GND pins that have neighboring signals which are used in the
application circuitry are connected. Just for the power supply of the
module at least 8 GND pins that are located right next to the VCC pins
must be connected
Note!
Please refer to the phyCARD Design-In Guide (LAN-051) for
additional information, layout recommendations and example
circuitry.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
17 The phyCARD-S on the phyBase
PHYTEC phyBASE Boards are fully equipped with all mechanical
and electrical components necessary for the speedy and secure start-up
and subsequent communication to and programming of applicable
PHYTEC Single Board Computer (SBC) modules. phyBASE Boards
are designed for evaluation, testing and prototyping of PHYTEC
Single Board Computers in laboratory environments prior to their use
in customer designed applications.
The phyBASE supports the following features for the phyCARD-S
modules:
• Power supply circuits to supply the modules and the peripheral
devices
• Support of different power modes of appropriate phyCARDs
• Full featured 4 line RS-232 transceiver supporting data rates of up
to 120kbps, hardware handshake and RS-232 connector
• Six USB-Host interfaces
• USB-OTG interface
• 10/100 Mbps Ethernet interface
• Complete Audio and Touchscreen interface
• LVDS display interface with separate connectors for data lines and
display / backlight supply voltage
• Circuitry to allow dimming of a backlight
• LVDS camera interface with I2C for camera control
• Security Digital Card / Multi Media Card Interface
• Two expansion connectors for customer prototyping purposes
featuring one USB, one I2C and on SPI interface, as well as on
GPIO/IRQ at either connector
• DIP-Switch to configure various interface options
• Jumper to configure the boot options for the phyCARD-S module
mounted
• RTC with battery supply/backup
66
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The phyCARD-S on the phyBASE
17.1 Concept of the phyBASE Board
The phyBASE Carrier Board provides a flexible development
platform enabling quick and easy start-up and subsequent
programming of the phyCARD Single Board Computer module. The
Carrier Board design allows easy connection of additional expansion
boards featuring various functions that support fast and convenient
prototyping and software evaluation. The Carrier Board is compatible
with all phyCARDs.
This modular development platform concept is depicted in Figure 14
below and includes the following components:
•
the phyCARD-S Module populated with the i.MX27 processor
and all applicable SBC circuitry such as DDR SDRAM, Flash,
PHYs, and transceivers to name a few.
•
the phyBASE which offers all essential components and
connectors for start-up including: a power socket enabling
connection to an external power adapter, interface connectors
such as DB-9, USB and Ethernet allowing for use of the SBC's
interfaces with standard cable.
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phyCARD-S [PCA-A-S1-xxx]
Figure 14:
phyBASE (phyCARD-S Carrier Board)
The following sections contain specific information relevant to the
operation of the phyCARD-S mounted on the phyBASE Carrier
Board.
Note:
Only features of the phyBASE which are supported by the
phyCARD-S are described. Jumper settings and configurations which
are not suitable for the phyCARD-S are not described in the following
chapters.
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The phyCARD-S on the phyBASE
17.2 Overview of the phyBASE Peripherals
LVDS
X32
U24
X27
U26
Ethernet
X10
D37
D40
X28
JP2 JP1
X6
U23
PWR
U9
U8
D38
D39
The phyBASE is depicted in Figure 15 and includes the following
components and peripherals listed in Table 27, Table 28, Table 29 and
Table 30. For a more detailed description of each peripheral refer to
the appropriate chapter listed in the applicable table. Figure 15
highlights the location of each peripheral for easy identification.
D41
U21
U12
J2
U25
XT1
U4
X34
RS232
P1
U13
X33
U27
U19
U3
Expansion 1
X7
U14
USB Host
9.4mm
U18
U29
X8
X30
X29
USB OTG
phyCARD Connector
U15
D30
U10
U6
U11
Figure 15:
BAT1
S3
U7
MMC / SD card
X26
U5
S1
Reset
S2
U28
ON / OFF
U16
J3
Expansion 2
U20
J1
MIC
OUT
IN
U17
X9
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U22
X4
U1
X3 X2 X1
AUDIO
X5
CAM
U2
phyBASE Overview of Connectors, LEDs and Buttons
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phyCARD-S [PCA-A-S1-xxx]
17.2.1 Connectors and Pin Header
Table 27 lists all available connectors on the phyBASE. Figure 15
highlights the location of each connector for easy identification.
Reference
Designator
X1
X2
X3
X5
X6
X7
X8A
X9A
X10
X26
X27
X28
X29
X30
X32
X33
Stereo Microphone input connector
Stereo Line Out connector
Stereo Line In connector
Camera Interface, RJ45
Display data connector
Dual USB Host connector
Expansion connector 0
Expansion connector 1
Ethernet connector, RJ45 with speed and
link led
Security Digital/MultiMedia Card slot
phyCARD-Connector for mounting the
phyCARD-S
Wall adapter input power jack to supply
main board power (+9 - +36 V)
USB On-The-Go connector
USB Host connector
Display / Backlight supply voltage
connector
USB Host connector
17.3.9
17.3.9
17.3.9
17.3.8
17.3.7.1
17.3.5
17.3.13
17.3.13
17.3.4
17.3.14
17.3.1
17.3.2
17.3.6
17.3.5
17.3.7.2
17.3.5
X34
CPLD JTAG connector
for
internal
use only
P1
Serial Interface, DB-9F
17.3.3
Table 27:
70
See
Section
Description
phyBASE Connectors and Pin Headers
© PHYTEC Messtechnik GmbH 2010
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The phyCARD-S on the phyBASE
Note:
The signal levels of the I2C and SPI interface are shifted from
VCC_LOGIC (2.75V) at the phyCARD Connector to VCC3V3
(3.3 V) by level shifters on the phyCARD Carrier Board.
Ensure that all module connections are not to exceed their expressed
maximum voltage or current. Maximum signal input values are
indicated in the corresponding controller User's Manual/Data Sheets.
As damage from improper connections varies according to use and
application, it is the user‘s responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
17.2.2 Switches
The phyBASE is populated with some switches which are essential for
the operation of the phyCARD-S module on the Carrier Board. Figure
15 shows the location of the switches and push buttons.
Button
S1
S2
Table 28:
See
Section
Description
System Reset Button – system reset signal
17.3.16
generation
Power Button – powering on and off main
17.3.2
supply voltages of the Carrier Board
phyBASE push buttons descriptions
S1 Issues a system reset signal. Pressing this button will toggle the
nRESET_IN pin of the phyCARD microcontroller LOW, causing
the controller to reset.
S2 Issues a power on/off event. Pressing this button less than 2
seconds will toggle the nPWR_KEY pin of the phyBASE CPLD
LOW, causing the CPLD to turn on the supply voltages, pressing
this button for more than 2 seconds causing the CPLD to turn off
the supply voltages.
© PHYTEC Messtechnik GmbH 2010
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71
phyCARD-S [PCA-A-S1-xxx]
Additionally a DIP-Switch is available at S3. The following table
gives an overview of the functions of the DIP-switch.
Note:
The following table describes only settings suitable for the phyCARDS. Other settings must not be used with the phyCARD-S.
72
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The phyCARD-S on the phyBASE
Button Setting
S3_1/
S3_2
0/0
0/1
1/0
S3_3/
S3_4
See
Section
Description
Switches 1 and 2 of DIP-Switch S3 select
which device process the audio and touch
panel signals.
Wolfson audio/touch contrl. (U1)
selected for touch and audio
Wolfson audio/touch contrl. (U1) selected 17.3.9
for audio, dedicated touch contrl. (U28)
for touch
Analog Devices audio contrl. (U17)
selected for audio, dedicated touch contrl.
(U28) for touch
Switches 3 and 4 of DIP-Switch S3
configure the I2C address for the
communication between CPLD and
phyCARD.
0/0
CPLD Address 0x80
Switch 5 of DIP-Switch S3 selects the
interface used for the communication
between CPLD and phyCARD.
S3_5
01
I2C communication selected
Switch 6 of DIP-Switch S3 turns the SPI
Multiplexer on, or off
0
SPI multiplexer off
S3_6
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73
phyCARD-S [PCA-A-S1-xxx]
Switches 7 and 8 of DIP-Switch S3 map
the two slave select signals of the SPI
interface and the two GPIO_IRQ signals
(GIO0_IRQ, GPIO1_IRQ) to two of the
three available connectors.
17.3.7.1
S3_7/
S3_8
0/0
0/1
1/x
Table 29:
1
17.3.11
17.3.12
SS0/GPIO0 -> expansion 0 (X8A),
17.3.13
SS1/GPIO1 -> expansion 1 (X9A)
SS0/GPIO0 -> expansion 0 (X8A),
SS1/GPIO1 -> display data connector (X6)
SS0/GPIO0 -> expansion 1 (X9A),
SS1/GPIO1 -> display data connector (X6)
phyBASE DIP-Switch S3 descriptions 1
Default settings are in bold blue text
74
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The phyCARD-S on the phyBASE
17.2.3 LEDs
The phyBASE is populated with numerous LEDs to indicate the status
of the various USB-Host interfaces, as well as the different supply
voltages. Figure 15 shows the location of the LEDs.
LED
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D37
Color
yellow
yellow
yellow
yellow
yellow
yellow
yellow
green
green
green
green
green
green
green
red
green
D38
D39
green
green
D40
D41
green
green
Table 30:
Description
USB1 amber led
USB2 amber led
USB3 amber led
USB4 amber led
USB5 amber led
USB6 amber led
USB7 amber led
USB1 green led
USB2 green led
USB3 green led
USB4 green led
USB5 green led
USB6 green led
USB7 green led
USB HUB global led
5V supply voltage for peripherals on the
phyBASE
supply voltage of the phyCARD
3V3 supply voltage for peripherals on the
phyBASE
3V3 standby voltage of the phyBASE
standby voltage of the phyCARD
See
Section
17.3.5
17.3.2
phyBASE LEDs descriptions
© PHYTEC Messtechnik GmbH 2010
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75
phyCARD-S [PCA-A-S1-xxx]
Note:
Detailed descriptions of the assembled connectors, jumpers and
switches can be found in the following chapters.
76
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The phyCARD-S on the phyBASE
17.2.4 Jumpers
The phyCARD Carrier Board comes pre-configured with 2 removable
jumpers (JP) and 3 solder jumpers (J). The jumpers allow the user
flexibility of configuring a limited number of features for development
constraint purposes. Table 31 below lists the 5 jumpers, their default
positions, and their functions in each position. Figure 16 depicts the
jumper pad numbering scheme for reference when altering jumper
settings on the development board. Note that pin 1 is always marked
by a square footprint in the jumper location diagrams that follow.
Figure 17 provides a detailed view of the phyBase jumpers and their
default settings.
Before making connections to peripheral connectors it is advisable to
consult the applicable section in this manual for setting the associated
jumpers.
e.g.: JP1
Figure 16:
e.g.: J1
e.g.:
Typical jumper numbering scheme
Table 31 provides a comprehensive list of all Carrier Board jumpers.
The table only provides a concise summary of jumper descriptions.
For a detailed description of each jumper see the applicable chapter
listing in the right hand column of the table.
© PHYTEC Messtechnik GmbH 2010
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77
Figure 17:
78
X26
U16
BAT1
U17
X9
X4
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U22
CAM
D30
U10
U6
U4
U13
X33
U14
U25
U3
Expansion 1
U27
USB Host
U29
J2
X8
U21
U12
X30
U18
X34
XT1
RS232
X7
U15
S3
MMC / SD card
U5
Reset
S1
ON / OFF
J3
Expansion 2
J1
U1
AUDIO
X5
P1
9.4mm
S2
U28
U20
MIC
OUT
IN
D41
USB OTG
X29
D40
D37
X32
X27
U26
Ethernet
X10
JP2 JP1
X28
PWR
X6
LVDS
X3 X2 X1
U23
U9
U8
D38
D39
phyCARD-S [PCA-A-S1-xxx]
U24
U19
U11
U2
U7
phyBASE jumper locations
The following conventions were used in the Jumper column of the
jumper table (Table 31)
• J = solder jumper
• JP = removable jumper
© PHYTEC Messtechnik GmbH 2010
L-731e_1
phyCARD Connector
The phyCARD-S on the phyBASE
Jumper Setting
JP1
Description
Jumper JP1 selects the boot device of
the phyCARD-S
See
Section
open
1+2
FLASH enabled as Boot device
internal ROM of the i.MX27 enabled as 17.3.3
Boot device and thus starting the
bootstrap program
other settings must not be used with
the phyCARD-S
Jumper JP2 connects the input voltage
to connector X32 as supply voltage for
a backlight.
open
closed
VCC12V Backlight disabled
VCC12V Backlight connected to
power supply only 12V DC power
supplies allowed
Jumper J1 selects the function of the
AC97 interrupt
1+2
Pendown signal of the Audio/Touch
controller at U1 is connected to AC97 17.3.7.3
interrupt
GPIO2_IRQ output of the Audio/Touch
controller at U1 connected to AC97
interrupt
Jumper J2 configures the I2C address of
the LED dimmer at U21
JP2
J1
2+3
J2
closed
open
I2C device address of LED dimmer
set to 0xC0
I2C device address of LED dimmer set
to 0xC2
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17.3.7.2
17.3.7.2
17.3.10
79
phyCARD-S [PCA-A-S1-xxx]
Jumper J3 configures the I2C address of
the touch screen controller at U28
J3
1+2
2+3
Table 31:
1
I2C device address set to 0x88
I2C device address set to 0x82
phyBASE jumper descriptions 1
Default settings are in bold
80
17.3.7.3
17.3.10
blue text
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L-731e_1
The phyCARD-S on the phyBASE
17.3 Functional Components on the phyBASE Board
This section describes the functional components of the phyBASE
Carrier Board supporting the phyCARD-S. Each subsection details a
particular connector/interface and associated jumpers for configuring
that interface.
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.1 phyCARD-S SBC Connectivity (X27)
X7
X5
AUDIO
X29
X30
USB OTG
X28
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
X27
U17
J3
D30
1
ON / OFF
S1
U4
U3
BAT1
U5
U29
U19
XT1
B
D39
D37
U23
D40
X34
U24
50
U25
U21
J2
U7
X32
MMC / SD card
Figure 18:
U18
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
Reset
A
phyCARD Connector
S2
LVDS
U28
X6
JP2 JP1
phyCARD-S SBC Connectivity to the Carrier Board
Connector X27 on the Carrier Board provides the phyCARD System on Module
connectivity. The connector is keyed for proper insertion of the SBC.
Figure 18 above shows the location of connector X27, along with
the pin numbering scheme as described in section 1.
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phyCARD-S [PCA-A-S1-xxx]
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.2 Power Supply (X28)
X7
X5
AUDIO
X29
X30
USB OTG
X28
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
J1
U11
U10
X9
U20
U8
U12
U14
X33
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
U28
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
X34
U25
U23
D40
U24
Figure 19:
U29
XT1
U19
U7
MMC / SD card
D37
U18
U21
LVDS
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
BAT1
U5
phyCARD Connector
S1
Reset
J2
X32
X6
JP2 JP1
Power adapter
Caution:
Do not use a laboratory adapter to supply power to the Carrier Board!
Power spikes during power-on could destroy the phyCARD-module
mounted on the Carrier Board! Do not change modules or jumper
settings while the Carrier Board is supplied with power!
Permissible input voltage at X28: +9 - +36 V DC unregulated.
The required current load capacity of the power supply depends on the
specific configuration of the phyCARD mounted on the Carrier Board
as well as whether an optional expansion board is connected to the
Carrier Board. An adapter with a minimum supply of 2.0 A is
recommended.
82
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The phyCARD-S on the phyBASE
Polarity:
+9 - 36 VDC
≥ 2000 mA
-- +
Center Hole
2.5 mm
5.0 mm
GND
Figure 20:
Connecting the Supply Voltage at X28
No jumper configuration is required in order to supply power to the
phyCARD module!
The phyBASE is assembled with a few power LEDs whose functions
are described in the following table:
LEDs
D37
D38
D39
D40
D41
Table 32:
Color
green
green
green
green
green
Description
VCC5V led
VCC_PHYCARD led
VCC3V3 led
VCC3V3STBY led
VSTBY led
LEDs assembled on the Carrier Board
Note:
For powering up the phyCARD the following actions have to be done:
1. Plug in the power supply connector
» All power LEDs should light up and the phyCARD puts
serial output to serial line 0 at P1.
2.
For powering down the phyCARD-S button S2 should be
pressed for a minimum time of 2000ms.
3.
Press button S2 for a maximum time of 1000ms seconds.
» All power LEDs should light up and the phyCARD puts
serial output to serial line 0 at P1.
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83
phyCARD-S [PCA-A-S1-xxx]
Three different power states are possible RUN, OFF and SUSPEND.
•
•
•
During RUN all supply voltages except VSTBY are on. This
means that the phyCARD-S is supplied by VCC_PHYCARD.
In OFF state all supply voltages are turned off. Only the standby
voltage (VCC3V3STBY) of the phyBASE itself is still available
to supply the PLD, the RTC and to provide a high-level voltage
for the Reset and Power switch.
In SUSPEND mode only the standby voltage VSTBY for the
phyCARD-S and the standby voltage (VCC3V3STBY) of the
phyBASE itself are generated. This means the phyCARD-S is
supplied only by VSTBY.
The RUN and OFF state can be entered using the power button S2 as
described in the gray box above. It is also possible to enter OFF state
with the help of the phyCARD's X_#PWR_OFF signal (PC17 of the
i.MX27). To enter OFF state signal X_#PWR_OFF must be active
(low).
SUSPEND state can be entered using signal X_#SUSP_RAM at pin
X2A26B of the phyCARD Connector (PC16 of the i.MX27).
X_#SUSP_RAM must be active (low) for at least 500ms.
84
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The phyCARD-S on the phyBASE
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.3 RS-232 Connectivity (P1)
X7
X5
AUDIO
X28
X29
X30
USB OTG
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
J1
U11
U10
X9
U20
U8
U12
U14
X33
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
U28
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
D37
U18
U29
XT1
U19
X34
U25
U21
J2
U7
X32
MMC / SD card
Figure 21:
U23
D40
U24
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
X6
JP2 JP1
UART1 connection interface at connector P1
Connector P1 is a DB9 sub-connector and provides a connection
interface to UART1 of the i.MX27. The TTL level signals from the
phyCARD-S are converted to RS-232 level signals. UART1 provides
only two handshake signals: RTS and CTS. Figure 22 below shows
the signal mapping of the RS-232 level signals to connector P1.
© PHYTEC Messtechnik GmbH 2010
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85
phyCARD-S [PCA-A-S1-xxx]
1
6
2
7
3
8
4
9
5
Figure 22:
Pin 2:
Pin 7:
Pin 3:
Pin 8:
TxD-RS232
RTS-RS232
RxD-RS232
CTS-RS232
Pin 5:
GND
UART1 connector P1 signal description
The RS-232 interface is hard-wired and no jumpers must be
configured for proper operation.
86
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The phyCARD-S on the phyBASE
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.4 Ethernet Connectivity (X10)
X7
X5
AUDIO
X28
X29
X30
USB OTG
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
U28
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
U29
U19
XT1
X34
U23
D40
U24
U25
U21
J2
U7
X32
MMC / SD card
Figure 23:
D37
U18
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
X6
JP2 JP1
Ethernet interface at connector X10
The Ethernet interface of the phyCARD is accessible at an RJ45
connector (X10) on the Carrier Board. Due to its characteristics this
interface is hard-wired and can not be configured via jumpers. The
LEDs for LINK and SPEED indication are integrated in the connector.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.5 USB Host Connectivity (X7, X8, X9, X30, X33)
X7
X5
AUDIO
X28
X29
X30
USB OTG
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
U28
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
D37
U18
U29
XT1
U19
X34
U25
LVDS
U21
J2
U7
X32
MMC / SD card
Figure 24:
U23
D40
U24
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
BAT1
U5
phyCARD Connector
S1
Reset
X6
JP2 JP1
USB host interface at connector X7, X30, X33
The USB host interface of the phyCARD is accessible via the USB
hub controller U4 on the Carrier Board. The controller supports
control of input USB devices such keyboard, mouse or USB key. The
USB hub has 7 downstream facing ports. Three ports extend to
standard USB connectors at X7 (dual USB A) and X30 (USB A). A
fourth port connects to 9 pin header row X33. These interfaces are
compliant with USB revision 2.0. The remaining ports are accessible
at the display data connector X6 and the expansion connectors X8A
and X9A. These three interfaces provide only the data lines D+ and D. They do not feature a supply line Vbus.
88
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L-731e_1
The phyCARD-S on the phyBASE
LEDs D16 to D30 signal use of the USB host interfaces. Table 30
shows the assignment of the LEDs to the different USB ports.
Table 33 shows the distribution of the seven downstream facing ports
to the different connectors, whereas Table 34 shows the Pin-out of
USB host connector X33.
USB hub port Connector
#
USB1
X30
USB2
X6
X8
USB3
X9
USB4
X33
USB5
USB6
USB7
Table 33:
X7A (bottom)
X7B (top)
3
5
7
2,4,6,8,10
Table 34:
USB A
40 pin FCC (pins 16 and 17)
20 pin header row (pins 19 and
20)
20 pin header row (pins 19 and
20)
9 pin header row (see table
below)
USB A
USB A
Distribution of the USB hub's (U4) ports
Pin number
1
Connector Type
Signal name
USB5_VBUS
USB5_DUSB5_D+
GND
NC
Description
USB5
Power
Supply
USB5 Data USB5 Data +
Ground
Not connected
Universal USB pin header X33 signal description
© PHYTEC Messtechnik GmbH 2010
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89
phyCARD-S [PCA-A-S1-xxx]
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.6 USB OTG Connectivity (X29)
X7
X5
AUDIO
X28
X29
X30
USB OTG
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
U28
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
D37
U29
U19
XT1
X34
U23
D40
U24
U25
LVDS
U21
J2
U7
X32
MMC / SD card
Figure 25:
U18
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
BAT1
U5
phyCARD Connector
S1
Reset
X6
JP2 JP1
USB OTG interface at connector X29
The USB OTG interface of the phyCARD is accessible at connector
X29 (USB Mini AB) on the Carrier Board. This interface is compliant
with USB revision 2.0.
No jumper settings are necessary for using the USB OTG port.
The phyCARD supports the On-The-Go feature. The Universal Serial
Bus On-The-Go is a device capable to initiate the session, control the
connection and exchange Host/Peripheral roles between each other.
90
© PHYTEC Messtechnik GmbH 2010
L-731e_1
The phyCARD-S on the phyBASE
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.7 Display / Touch Connectivity (X6, X32)
X7
X5
AUDIO
X28
X29
X30
USB OTG
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
U28
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
D37
U18
U29
XT1
U19
X34
U25
U21
J2
U7
X32
MMC / SD card
Figure 26:
U23
D40
U24
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
X6
JP2 JP1
Universal LVDS interface at connector X6
The various performance classes of the phyCARD family allow to
attach a large number of different displays varying in resolution,
signal level, type of the backlight, Pin-out, etc. In order not to limit the
range of displays connectable to the phyCARD, the phyBASE has no
special display connector suitable only for a small number of displays.
The new concept intends the use of an adapter board (e.g. phyBASE
LCD interface LCD-014) to attach a special display, or display family
to the phyCARD. Two universal connectors provide the connectivity
for the display adapter. They allow easy adaption also to any customer
display. The display data connector at X6 combines various interface
signals like LVDS, USB, I2C, etc. required to hook up a display. The
display power connector at X32 provides all supply voltages needed to
supply the display and a backlight.
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phyCARD-S [PCA-A-S1-xxx]
17.3.7.1 Display Data Connector (X6)
The display data connector at X6 (40 pin FCC connector 0,5mm pitch)
combines various interface signals.
Pin
number
1
2
3
4
5
6
7
8
9
10
11
12
13
Signal name
Description
SPI 1 clock
14
SPI1_SCLK
SPI_MISO
SPI1_MOSI
SP1I_SS_DISP
DISP_IRQ
VCC3V3
I2C_SCL
I2C_SDA
GND
LS_BRIGHT
VCC3V3
/PWR_KEY
/DISP_ENA
PHYWIRE
15
16
17
18
19
20
21
22
23
GND
USB2_D+
USB2_DGND
TXOUT0TXOUT0+
GND
TXOUT1TXOUT1+
8:
92
SPI 1 Master data in; slave data out
SPI 1 Master data out; slave data in
SPI 1 Chip select display
Display interrupt input
Power supply display
I2C Clock Signal
I2C Data Signal
Ground
PWM brightness Output
Power Supply Display
Power on/off Button
Display enable signal
Hardware Introspection Interface
for internal use only
Ground
USB2 data + 8
USB2 data -1
Ground
LVDS data channel 0 negative output
LVDS data channel 0 positive output
Ground
LVDS data channel 1 negative output
LVDS data channel 1 positive output
LEDs D17 and D24 signal use of the USB interface
© PHYTEC Messtechnik GmbH 2010
L-731e_1
The phyCARD-S on the phyBASE
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
TXOUT2TXOUT2+
GND
TXOUT3TXOUT3+
GND
TXCLKOUTTXCLKOUT+
GND
TP_X+
TP_XTP_Y+
TP_YTP_WP
GND
LS_ANA
Table 35:
Ground
LVDS data channel 2 negative output
LVDS data channel 2 positive output
Ground
LVDS data channel 3 negative output
LVDS data channel 3 positive output
Ground
LVDS clock channel negativ output
LVDS clock channel positive output
Ground
Touch
Touch
Touch
Touch
Touch
Ground
Light sensor Analog Input
Display data connector signal description
The X-Arc bus signals for the SPI interface and the display interrupt
input are shared with the corresponding signals on the expansion
connectors X8A and X9A. Because of that they have to be mapped to
the display data connector by configuring switches 7 and 8 of DIPSwitch S3. The table below shows the required settings.
Button Setting Description
SS0/GPIO0 9 -> expansion 0 (X8A),
S3_7/ 0/0
SS1/GPIO11 -> expansion 1 (X9A)
S3_8
0/1
SS0/GPIO01 -> expansion 0 (X8A),
SS1/GPIO11 -> display data connector (X6)
SS0/GPIO01 -> expansion 1 (X9A),
1/x
SS1/GPIO11 -> display data connector (X6)
9
:
GPIO0 ≙ PC31 and GPIO1 ≙ PC25 of the i.MX27
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phyCARD-S [PCA-A-S1-xxx]
Table 36:
SPI and GPIO connector selection
The default setting does not connect the SPI interface and the GPIO of the X-Arc
bus to the display data connector.
The Light sensor Analog Input at pin 40 extends to an A/D converter
which is connected to the I2C bus at address 0xC8 (write) and 0XC9
(read).
17.3.7.2 Display Power Connector (X32)
The display power connector X32 (AMP microMatch 8-188275-2)
provides all supply voltages needed to supply the display and a
backlight.
Pin number
1
2
3
4
5
6
7
8
9
10
11
12
Table 37:
94
Signal name
GND
VCC3V3
GND
VCC5V
GND
VCC5V
GND
VCC5V
GND
LS_BRIGHT
VCC12V_BL
VCC12V_BL
Description
Ground
3,3V power supply display
Ground
5V power supply display
Ground
5V power supply display
Ground
5V power supply display
Ground
PWM brightness output
12V Backlight power supply
12V Backlight power supply
LVDS power connector X32 signal description
© PHYTEC Messtechnik GmbH 2010
L-731e_1
The phyCARD-S on the phyBASE
The PWM signal at pin 10 can be used to control the brightness of a
display's backlight. It is generated by an LED dimmer. The LED
dimmer is connected to the I2C bus at address 10 0xC0 (write) and
0xC1 (read).
To make VCC12V_BL available at X32 jumper JP2 must be closed.
Caution:
There is no protective circuitry for the backlight. Close jumper JP2
only if a 12 V power supply is connected to X28 as primary supply for
the phyBASE.
17.3.7.3 Touch Screen Connectivity
As many smaller applications need a touch screen as user interface,
provisions are made to connect 4- or 5- wire resistive touch screens to
the display data connector X6 (pins 34 - 38, refer to Table 35). Two
touch screen controllers are available on the phyCARD Carrier Board.
The Wolfson WM9712L audio/touch codec at U1 allows connecting
4- and 5-wire touch panels, whereas the STMPE811 touch panel
controller at U28 is suitable for 4-wire touch panels only. Switches 1
and 2 of DIP-Switch S3 select which controller is used to process the
touch panel signals. The different configurations are shown in Table
38.
10:
Default address. Jumper J2 allows to select a 0xC2 (write) and 0xC3 (read) alternatively
(refer to Table 31).
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phyCARD-S [PCA-A-S1-xxx]
Button Setting
S3_1/
S3_2
Description
Switches 1 and 2 of DIP-Switch S3 select which
device process the audio and touch panel
signals.
0/0
0/1
1/0
Table 38:
Wolfson audio/touch contrl. (U1) selected for
touch and audio
Wolfson audio/touch contrl. (U1) selected for
audio, dedicated touch contrl. (U28) for touch
Analog Devices audio contrl. (U17) selected for
audio, dedicated touch contrl. (U28) for touch
Selection of the touch screen controller
If the Wolfson WM9712L audio/touch codec is chosen, the touch
screen data is available at the AC97 interface. An interrupt or the
pendown signal of the WM9712L , selected by jumper J1 (refer to
section 17.2.4), is connected to the AC97 interrupt pin
(HAD_SEL/AC_INT, pin X2A42). The default configuration selects
the pendown signal to be attached to pin X2A42 of the phyCARD
Connector.
If the dedicated touch screen controller at U28 is chosen, the touch
screen data is available at the I2C interface of the X-Arc bus. The
controller's slave address can be selected with jumper J3 (refer to
section 17.2.4). The default address of the controller is 0x88 (write)
and 0x89 (read). The interrupt output of the touch screen controller is
connected to GPIO2 (GPIO2_IRQ, pin X2A47) which extends to port
PE5 of the i.MX27 on the phyCARD-S.
96
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The phyCARD-S on the phyBASE
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.8 Camera Interface (X5)
X7
X5
AUDIO
X29
X30
USB OTG
X28
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
U28
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
D37
U29
U19
XT1
X34
U23
D40
U24
U25
U21
J2
U7
X32
MMC / SD card
Figure 27:
U18
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
X6
JP2 JP1
Camera interface at connectors X5
The phyCARD-S has an optional camera interface. This interface
extends from the phyCARD-Connector to the RJ45 socket (X5) on the
Carrier Board. The table below shows the Pin-out of connector X5:
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phyCARD-S [PCA-A-S1-xxx]
Pin #
1
2
3
4
5
6
7
8
Table 39:
98
Signal Name
RXIN+
RXINRX_CLKI2C_SDA
I2C_SCL
RXCLK+
VCC_CAM
GND
Description
LVDS Input+
LVDS InputLVDS ClockI2C Data
I2C Clock
LVDS Clock+
Power supply camera (3.3V)
Ground
PHYTEC camera connector X5
© PHYTEC Messtechnik GmbH 2010
L-731e_1
The phyCARD-S on the phyBASE
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.9 Audio Interface (X1,X2,X3)
X7
X5
AUDIO
X29
X30
USB OTG
X28
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U16
U28
U9
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
D37
U18
U29
XT1
U19
X34
U25
LVDS
U21
J2
U7
X32
MMC / SD card
Figure 28:
U23
D40
U24
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U15
BAT1
U5
phyCARD Connector
S1
Reset
X6
JP2 JP1
Audio interface at connectors X1,X2,X3
The AC97/HDA interface on the phyCARD connects to a Wolfson
WM9712L (U1) or AD1986A (U17) audio codec controller on the
Carrier Board. Switches 1 and 2 of DIP-Switch S3 select which codec
is used to process the audio signals. Table 40 shows the different
options.
Button Setting
S3_1/ 0/0
S3_2
0/1
1/0
Table 40:
Description
Wolfson audio/touch contrl. (U1) selected for
touch and audio
Wolfson audio/touch contrl. (U1) selected for
audio, dedicated touch contrl. (U28) for touch
Analog Devices audio contrl. (U17) selected for
audio, dedicated touch contrl. (U28) for touch
Selection of the audio codec
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phyCARD-S [PCA-A-S1-xxx]
Audio devices can be connected to 3,5mm audio jacks at X1, X2, and
X3.
Audio Outputs:
X2 – Line Output - Line_OUTL/Line_OUTR
Audio Inputs:
X1- Microphone Inputs - MIC1/MIC2
X3 - Line Input - Line_INL/Line_INR
Please refer to the audio codec’s reference manual for additional
information regarding the special interface specification.
17.3.10
I2C Connectivity
The I2C interface of the X-Arc bus is available at different connectors
on the phyBASE. The following table provides a list of the connectors
and pins with I2C connectivity.
Connector
Camera interface X5
Display data connector X6
Expansion connector 1
X8A
Expansion connector 2
X9A
Table 41:
Location
pin 4 (I2C_SDA); pin 5 (I2C_SCL)
pin 8 (I2C_SDA); pin 7 (I2C_SCL)
pin 7 (I2C_SDA); pin 8 (I2C_SCL)
pin 7 (I2C_SDA); pin 8 (I2C_SCL)
I2C connectivity
To avoid any conflicts when connecting external I2C devices to the
phyBASE the addresses of the on-board I2C devices must be
considered. Some of the addresses can be configured by jumper. Table
42 lists the addresses already in use. The table shows only the default
address. Please refer to section 17.2.4 for alternative address settings.
100
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The phyCARD-S on the phyBASE
Device
Address used (write / Jumper
read)
LED dimmer (U21)
0xC0 / 0xC1
J2
RTC (U3)
0xA2 / 0xA3
A/D converter (U22)
0xC8 / 0xC9
Touch screen controller 0x88 / 0x89
J3
(U28)
CPLD (U25)
0x80 / 0x81
S3_3,
S3_4
Table 42:
I2C addresses in use
17.3.11
SPI Connectivity
The SPI interface of the X-Arc bus is available at the expansion
connectors X8A and X9A as well as at the display data connector X6
(refer to sections 17.3.7.1 and 17.3.13 to see the Pin-out). Due to the
X-Arc bus specification only two slave select signals are available.
Because of that the CPLD maps the SPI interface to two of the
connectors depending on the configuration of switches 7 and 8 of DIPSwitch S3. The table below shows the possible configurations.
Button Setting Description
SS0/GPIO0 11 -> expansion 0 (X8A),
S3_7/ 0/0
SS1/GPIO11 -> expansion 1 (X9A)
S3_8
0/1
SS0/GPIO01 -> expansion 0 (X8A),
SS1/GPIO11 -> display data connector (X6)
SS0/GPIO01 -> expansion 1 (X9A),
1/x
SS1/GPIO11 -> display data connector (X6)
Table 43:
11
SPI connector selection
: GPIO0 ≙ PC31 and GPIO1 ≙ PC25 of the i.MX27
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phyCARD-S [PCA-A-S1-xxx]
17.3.12
User programmable GPIOs
Two (GPIO0_IRQ and GPIO1_IRQ) of the three GPIO / Interrupt
signals available at the X-Arc bus are freely available. They are
mapped to the expansion connectors X8A and X9A (pin 16), or to the
display data connector X6 (pin 5) depending in the configuration at
DIP-Switch S3 (see Table 43). The third GPIO I Interrupt signal
(GPIO2_IRQ) is used to connect the interrupt output of the touch
screen controller at U28 to the phyCARD-S.
Expansion connectors (X8A, X9A)
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.13
X7
X5
AUDIO
X29
X30
USB OTG
X28
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
J1
U11
U10
X9
U20
U8
U12
U14
X33
X8
Expansion 2
U26
Expansion 1
D41
U16
U28
U9
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
U29
U19
XT1
X34
U21
J2
X32
U7
102
U23
D40
U24
U25
MMC / SD card
Figure 29:
D37
U18
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
X6
JP2 JP1
Expansion connector X8A, X9A
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L-731e_1
The phyCARD-S on the phyBASE
The expansion connectors X8A and X9A provide an easy way to add
other functions and features to the phyBASE. Standard interfaces such
as USB, SPI and I2C as well as different supply voltages and one
GPIO are available at the pin header rows.
As can be seen in Figure 29 the location of the connectors allows to
expand the functionality without expanding the physical dimensions.
Mounting wholes can be used to screw the additional PCBs to the
phyBASE.
The expansion connectors share the SPI interface and the GPIOs of
the X-Arc bus with the display data connector X6. Therefore switches
7 and 8 of DIP-Switch S3 must be configured to map the signals to the
desired connector.
Button Setting Description
SS0/GPIO0 12 -> expansion 0 (X8A),
S3_7/ 0/0
SS1/GPIO11 -> expansion 1 (X9A)
S3_8
0/1
SS0/GPIO01 -> expansion 0 (X8A),
SS1/GPIO11 -> display data connector (X6)
SS0/GPIO01 -> expansion 1 (X9A),
1/x
SS1/GPIO11 -> display data connector (X6)
Table 44:
Pin #
1
2
3
4
5
6
7
8
12
SPI and GPIO connector selection
Signal Name
VCC5V
VCC5V
VCC3V3
VCC3V3
GND
GND
I2C_SDA
I2C_SCL
Description
5V power supply
5V power supply
3,3V power supply
3,3V power supply
Ground
Ground
I2C Data
I2C Clock
: GPIO0 ≙ PC31 and GPIO1 ≙ PC25 of the i.MX27
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phyCARD-S [PCA-A-S1-xxx]
9
10
11
12
13
14
15
16
17
18
19
20
Table 45:
104
GND
GND
SPI_SS_SLOT0
SPI_SS_SLOT1
SPI1_MOSI
SPI1_SCLK
SPI1_MISO
/SPI1_RDY
SLOT0_IRQ
SLOT1_IRQ
GND
GND
USB3_DUSB4_DUSB3_D+
USB4_D+
Ground
Ground
X8A SPI chip select expansion port 0
X9A SPI chip select expansion port 1
SPI master output/slave input
SPI clock output
SPI master input/slave output
SPI data ready input master mode only
X8A Interrupt input expansion port 0
X9A Interrupt input expansion port 1
Ground
Ground
X8A USB3 Data DX9A USB4 Data DX8A USB3 Data D+
X9A USB4 Data D+
PHYTEC expansion connector X8A, X9A
© PHYTEC Messtechnik GmbH 2010
L-731e_1
The phyCARD-S on the phyBASE
Security Digital Card/ MultiMedia Card (X26)
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.14
X7
X5
AUDIO
X28
X29
X30
USB OTG
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U9
U16
U28
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
D37
U29
U19
XT1
X34
U23
D40
U24
U25
U21
J2
U7
X32
MMC / SD card
Figure 30:
U18
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
X6
JP2 JP1
SD Card interface at connector X26
The phyCARD Carrier Board provides a standard SDHC card slot at
X26 for connection to SD/MMC interface cards. It allows easy and
convenient connection to peripheral devices like SD- and MMC cards.
Power to the SD interface is supplied by sticking the appropriate card
into the SD/MMC slot. The card slot X26 connects to the phyCARD-S
via a level shifter to ensure the correct voltage for the SD/MMC cards.
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phyCARD-S [PCA-A-S1-xxx]
Boot Mode Selection (JP1)
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.15
X7
X5
AUDIO
X29
X30
USB OTG
X28
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U16
U28
U9
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
U29
U19
XT1
X34
U23
D40
U24
U25
U21
J2
U7
X32
MMC / SD card
Figure 31:
D37
U18
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
X6
JP2 JP1
Boot Mode Selcetion Jumper JP1
The boot mode jumper JP1 is provided to configure the boot mode of
the phyCARD-S after a reset.
By default the boot mode jumper is open, configuring the
phyCARD-S for booting from the Flash device. Closing jumper JP1
results in start of the on-chip boot strap software of the i.MX27.
Please refer to the phyCARD-S Quick Start Manual as well as the
i.MX27 Reference Manual for Information on how to use the boot
strap mode.
106
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The phyCARD-S on the phyBASE
Jumper Setting
JP1
Description
Jumper JP1 selects the boot device of the
phyCARD-S
open
1+2
FLASH enabled as Boot device
internal ROM of the i.MX27 enabled as Boot
device and thus starting the bootstrap program
other settings must not be used with the
phyCARD-S
© PHYTEC Messtechnik GmbH 2010
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107
phyCARD-S [PCA-A-S1-xxx]
System Reset Button (S1)
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.16
X7
X5
AUDIO
X29
X30
USB OTG
X28
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
J1
U11
U10
X9
U20
U8
U12
U14
X33
X8
Expansion 2
U26
Expansion 1
D41
U16
U28
U9
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
U29
U19
XT1
X34
U25
U23
D40
U24
U7
MMC / SD card
Figure 32:
D37
U18
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U21
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
J2
X32
X6
JP2 JP1
System Reset Button S1
The phyCARD Carrier Board is equipped with a system reset button at
S1. Pressing the button will not only reset the phyCARD mounted on
the phyBASE, but also the peripheral devices, such as the USB Hub,
etc.
108
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L-731e_1
The phyCARD-S on the phyBASE
RTC at U3
9.4mm
P1
X3 X2 X1
MIC
OUT
IN
USB Host
17.3.17
X7
X5
AUDIO
X29
X30
USB OTG
X28
X10
RS232
PWR
Ethernet
U2
CAM
D38
U6
U1
U27
U22
U13
X4
U11
U10
X9
U20
U8
U12
U14
X33
J1
X8
Expansion 2
U26
Expansion 1
D41
U16
U28
U9
X27
U17
J3
D39
D30
S2
ON / OFF
U4
U3
D37
U18
U29
XT1
U19
X34
U25
U23
D40
U24
S3
X26
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U21
LVDS
U5
U15
BAT1
phyCARD Connector
S1
Reset
J2
U7
X32
MMC / SD card
X6
JP2 JP1
For real-time or time-driven applications, the phyBASE is equipped
with an RTC-8564 Real-Time Clock at U3. This RTC device provides
the following features:
• Serial input/output bus (I2C), address 0xA2(write)/0xA3(read)
• Power consumption
Bus active (400 kHz): < 1 mA
Bus inactive, CLKOUT inactive:
= 275 nA
• Clock function with four year calendar
• Century bit for year 2000-compliance
• Universal timer with alarm and overflow indication
• 24-hour format
• Automatic word address incrementing
• Programmable alarm, timer and interrupt functions
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
The Real-Time Clock is programmed via the I2C bus
(address 0xA2 / 0xA3). Since the phyCORE-S is equipped with an
internal I2C controller, the I2C protocol is processed very effectively
without extensive processor action (refer also to section 9.5)
The Real-Time Clock also provides an interrupt output that extends to
the Wakeup signal at X27A48. An interrupt occurs in the event of a
clock alarm, timer alarm, timer overflow and event counter alarm. It
has to be cleared by software. With the interrupt function, the
Real-Time Clock can be utilized in various applications.
If the RTC interrupt is to be used as a software interrupt via a
corresponding interrupt input of the processor.
Note:
After connection of the supply voltage the Real-Time Clock
generates no interrupt. The RTC must be first initialized
(see RTC Data Sheet for more information).
Use of a coin cell at BAT1 allows to buffer the RTC.
17.3.18
PLD at U25
The phyBASE is equipped with a Lattice LC4256V PLD at U25. This
PLD device provides the following features:
• Power management function (section 17.3.2)
• Signal mapping for sound devices WM9712L and AD1986A
(section 17.3.9)
• Configuration the sound device AD1986A for HDA or AC97
• Signal mapping SPI chipselect and interrupt to the expansion or
display connectors (sections 17.3.11 and 17.3.12)
• Touch Signal mapping to WM9712L or STMP811 (section
17.3.7.3)
110
© PHYTEC Messtechnik GmbH 2010
L-731e_1
The phyCARD-S on the phyBASE
Carrier Board Physical Dimensions
D3.2mm
17.3.19
LVDS
X32
X27
U26
Ethernet
X10
D37
D40
X28
JP2 JP1
X6
U23
PWR
U9
U8
D38
D39
124mm
130mm
U24
D41
U21
U12
J2
172mm
185mm
U25
X34
U4
XT1
RS232
P1
U13
X33
U27
U19
U3
Expansion 1
X7
U14
USB Host
9.4mm
U18
U29
X8
X30
X29
USB OTG
phyCARD Connector
U15
D30
U10
U6
U11
BAT1
S3
U7
3mm
3mm
Figure 33:
6.5mm
MMC / SD card
X26
U5
S1
Reset
S2
ON / OFF
U16
U28
U20
J3
Expansion 2
U17
X9
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
U22
J1
MIC
OUT
IN
6.5mm
X4
U1
X3 X2 X1
AUDIO
X5
CAM
U2
Carrier Board Physical Dimensions
Please contact us if a more detailed dimensioned drawing is needed to
integrate the phyBASE into a customer application.
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
18 Revision History
Date
Version
numbers
01-07-2009 Manual
L-731e_0
Changes in this manual
First draft, Preliminary documentation.
Describes the phyCARD-S with
phyBASE- Baseboard.
05-05-2010 Manual
L-731e_1
112
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Index
Index
Emulator.................................... 55
1
100Base-T................................. 46
10Base-T................................... 46
1V3............................................ 29
1V45.......................................... 29
1V5............................................ 29
1V8............................................ 29
Fast Ethernet Controller............ 45
Features ................................. 8, 66
FEC ........................................... 45
G
General Purpose I/Os ................ 52
GND Connection ...................... 65
2
2V775........................................ 29
3
H
Humidity ................................... 61
3V3............................................ 28
A
Audio Codec ............................. 99
B
Block Diagram.......................... 10
Boot Configuration ................... 35
Booting...................................... 33
Booting from NAND Flash ...... 35
Bootstrap................................... 35
C
Camera Interface....................... 59
D
DDR SDRAM........................... 36
Debug Interface......................... 53
Dimensions ............................... 61
Display Interface....................... 56
E
EEPROM ............................ 36, 37
EEPROM Write Protection....... 39
EMC ........................................... 5
© PHYTEC Messtechnik GmbH 2010
F
L-731e_1
I
I²C EEPROM ............................ 37
I2C Interface .............................. 49
I2C Memory............................... 25
I2C2 Bus .................................... 25
IC Identification Module........... 25
ISP1504..................................... 43
J
J1 .........................................25, 48
J10 .......................................26, 59
J11 .......................................26, 57
J2 .........................................25, 39
J3 .........................................25, 38
J4 .........................................25, 38
J5 .........................................25, 38
J6 ............................................... 25
J9 .........................................26, 57
JA-002....................................... 55
JTAG Interface.......................... 53
JTAG-Emulator Adapter........... 55
L
LAN .......................................... 48
113
phyCARD-S [PCA-A-S1-xxx]
LINK LED................................ 87
LVDS
Camera Signals................ 26, 59
Display Signals................ 26, 57
M
MAC ......................................... 48
MAC Address ........................... 48
N
NAND Flash ....................... 36, 37
O
SDRAM .................................... 36
Serial Interfaces ........................ 42
SMT Connector ........................ 14
SPEED LED ............................. 87
SPI Interface ............................. 50
SSI Interface ............................. 50
Standby Voltage........................ 28
Storage Temperature................. 61
Supply Voltage ......................... 27
System Configuration ............... 33
System Memory........................ 36
System Power ........................... 27
Operating Temperature............. 61
Operating Voltage..................... 61
T
P
U
PHY .......................................... 46
phyBASE
Connectors............................. 70
LEDs...................................... 75
Peripherals ............................. 69
Pin Header ............................. 70
Switches................................. 71
phyCARD-Connector ......... 14, 16
Physical Dimensions ................ 60
Physical Layer Transceiver ...... 46
Pin Description ......................... 14
Pin-out ...................................... 21
PLD......................................... 110
Power Consumption ................. 61
Power Management .................. 31
Power Supply............................ 13
Programming Voltage .............. 25
U16 ........................................... 37
U24 ........................................... 36
U25 ........................................... 36
U28 ..................................... 25, 37
U29 ..................................... 26, 59
U32 ..................................... 26, 57
U34 ........................................... 43
U35 ........................................... 44
UART ....................................... 43
USB
Host Transceiver.................... 44
OTG Transceiver ................... 43
USB 2.0............................... 88, 90
USB Device .............................. 43
USB Host .................................. 43
USB OTG ................................. 43
R
Technical Specifications........... 60
V
RS-232 Level............................ 43
RTC ........................................ 109
RTC Interrupt ......................... 110
VBAT ....................................... 28
VCC_3V3 ................................. 27
Voltage Output.......................... 30
Voltage Regulator..................... 28
S
W
SD / MMC Card Interfaces....... 40
Weight....................................... 61
114
© PHYTEC Messtechnik GmbH 2010
L-731e_1
Index
WM9712L..................... 95, 96, 99
X29............................................ 90
X
X1.............................................. 53
© PHYTEC Messtechnik GmbH 2010
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phyCARD-S [PCA-A-S1-xxx]
Document:
phyCARD-S
Document number: L-731e_1, April 2010
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116
© PHYTEC Messtechnik GmbH 2010
L-731e_1
© PHYTEC MesstechnikGmbH 2010
L-731e_1
Published by
© PHYTEC Messtechnik GmbH 2010
Ordering No. L-731e_1
Printed in Germany
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