MAX691A, MAX693A, MAX800, MAX800L, MAX800M

MAX691A, MAX693A, MAX800, MAX800L, MAX800M

19-0094; Rev 11; 8/08

Microprocessor Supervisory Circuits

+8V

5V

REGULATOR

General Description

The MAX691A/MAX693A/MAX800L/MAX800M microprocessor (µP) supervisory circuits are pin-compatible upgrades to the MAX691, MAX693, and MAX695. They improve performance with 30µA supply current, 200ms typ reset active delay on power-up, and 6ns chipenable propagation delay. Features include write protection of CMOS RAM or EEPROM, separate watchdog outputs, backup-battery switchover, and a RESET output that is valid with V

CC down to 1V. The MAX691A/

MAX800L have a 4.65V typical reset-threshold voltage, and the MAX693A/MAX800Ms’ reset threshold is 4.4V

typical. The MAX800L/MAX800M guarantee power-fail accuracies to ±2%.

________________________Applications

Computers

Controllers

Intelligent Instruments

Automotive Systems

Critical µP Power Monitoring

Typical Operating Circuit

0.1

μF

____________________________Features

o 200ms Power-OK/Reset Timeout Period o 1µA Standby Current, 30µA Operating Current o On-Board Gating of Chip-Enable Signals,

10ns max Delay

o MaxCap

® or SuperCap Compatible

o Guaranteed R

ES T Assertion to V

CC

= +1V

o Voltage Monitor for Power-Fail or Low-Battery

Warning

o Power-Fail Accuracy Guaranteed to ±2%

(MAX800L/M)

o Available in 16-Pin Narrow SO, Plastic

DIP, and TSSOP Packages

Ordering Information

PART TEMP RANGE

PIN -

PA C K A G E

MAX691ACUE

MAX691ACSE

MAX691ACWE

MAX691ACPE

MAX691AC/D

MAX691AEUE

MAX691AESE

MAX691AEWE

MAX691AEPE

-0°C to +70°C

-0°C to +70°C

-0°C to +70°C

-0°C to +70°C

-0°C to +70°C

-0°C to +70°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

16 TSSOP

16 Narrow SO

16 Wide SO

16 Plastic DIP

Dice*

16 TSSOP

16 Narrow SO

16 Wide SO

16 Plastic DIP

Ordering Information continued on last page.

* Dice are specified at T

A

= +25°C, DC parameters only.

Devices in PDIP, SO, and TSSOP packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering.

Lead free not available for CERDIP package.

Pin Configuration

*MaxCap

1N4148

0.47F*

NO

CONNECTION

3

V

CC

1

VBATT

5

BATT ON

V

OUT

2

CE OUT

12

9

PFI

4

GND

MAX691A

MAX693A

MAX800L

MAX800M

CE IN

13

WDI

11

7

OSC IN

PFO

10

8

OSC SEL

RESET

15

LOW LINE WDO

6 14

ADDRESS

DECODE

AUDIBLE

ALARM

CMOS RAM

A0-A15

I/O

μP

NMI

RESET

SYSTEM STATUS INDICATORS

MaxCap is a registered trademark of Kanthal Globar, Inc.

TOP VIEW

VBATT

1

V

OUT

2

V

CC

GND

3

4

BATT ON

5

LOW LINE

6

OSC IN

7

OSC SEL

8

MAX691A

MAX693A

MAX800L

MAX800M

DIP/SO/TSSOP

16

RESET

15

RESET

14

WDO

13

CE IN

12

CE OUT

11 WDI

10

PFO

9 PFI

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Microprocessor Supervisory Circuits

ABSOLUTE MAXIMUM RATINGS

Terminal Voltage (with respect to GND)

V

CC

.......................................................................-0.3V to +6V

VBATT...................................................................-0.3V to +6V

All Other Inputs .....................................-0.3V to (V

OUT

Input Current

+ 0.3V)

V

CC

V

CC

Peak...........................................................................1.0A

Continuous.............................................................250mA

VBATT Peak ..................................................................250mA

VBATT Continuous ..........................................................25mA

GND, BATT ON .............................................................100mA

All Other Outputs ............................................................25mA

Continuous Power Dissipation (T

A

= +70°C)

TSSOP (derate 6.70mW/°C above +70°C) ..................533mW

Narrow SO (derate 8.70mW/°C above +70°C) ...........696mW

Wide SO (derate 9.52mW/°C above +70°C)...............762mW

Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW

CERDIP (derate 10.00mW/°C above +70°C) ..............800mW

Operating Temperature Ranges

MAX69_AC_ _/MAX800_C_ _ .............................0°C to +70°C

MAX69_AE_ _/MAX800_E_ _ ...........................-40°C to +85°C

MAX69_AMJE ................................................-55°C to +125°C

Storage Temperature Range .............................-65°C to +160°C

Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(MAX691A, MAX800L: V

CC unless otherwise noted.)

= +4.75V to +5.5V; MAX693A, MAX800M: V

CC

= +4.5V to +5.5V; VBATT = 2.8V, T

A

= T

MIN to T

MAX

,

PARAMETER CONDITIONS MIN TYP MAX UNITS

Operating Voltage Range,

V

CC

, VBATT (Note 1)

0 5.5

V

I

OUT

= 25mA V

CC

- 0.02

V

CC

- 0.05

V

CC

- 0.2

V

CC

- 0.3

V

OUT

Output V

CC

= 4.5V

I

OUT

= 250mA

I

OUT

= 210mA

MAX69_AC

MAX69_AE,

MAX800_C/E

MAX69_A/M

MAX69_AC/AE,

MAX800_C/E

V

CC

- 0.2

V

CC

- 0.35

V

CC

- 0.40

V

CC

- 0.17

V

CC

- 0.3V

V

0.8

1.2

MAX69_AC, MAX800_C

V

CC

-to-V

OUT

On-Resistance V

CC

= 4.5V

V

OUT

Mode in Battery-Backup

VBATT-to-V

OUT

On-Resistance

MAX69_AE, MAX800_E

MAX69_A/M

VBATT = 4.5V, I

OUT

= 20mA

VBATT = 2.8V, I

OUT

= 10mA

VBATT = 2.0V, I

OUT

= 5mA

VBATT = 4.5V

VBATT = 2.8V

VBATT = 2.0V

Supply Current in

Normal Operating Mode

(excludes I

OUT

)

Supply Current in

Battery-Backup Mode

(excludes I

OUT

) (Note 2)

VBATT Standby Current

(Note 3)

Battery Switchover

Threshold

V

CC

> VBATT - 1V

V

CC

< VBATT - 1.2V,

VBATT = 2.8V

VBATT + 0.2V

Power-up

Power-down

≤ V

CC

T

A

= +25°C

T

A

= T

MIN

+ T

MIN

T

A

= +25°C

T

A

= T

MIN

+ T

MIN

VBATT - 0.3

VBATT - 0.25

VBATT - 0.15

-0.1

-1.0

0.8

0.8

30

0.04

VBATT + 0.3

VBATT - 0.3

1.4

1.6

15

25

30

100

1

5

0.02

0.02

Ω

V

Ω

µA

µA

µA

V

2 _______________________________________________________________________________________

Microprocessor Supervisory Circuits

ELECTRICAL CHARACTERISTICS (continued)

(MAX691A, MAX800L: V

CC unless otherwise noted.)

= +4.75V to +5.5V; MAX693A, MAX800M: V

CC

= +4.5V to +5.5V; VBATT = 2.8V, T

A

= T

MIN to T

MAX

,

MIN TYP MAX UNITS PARAMETER CONDITIONS

Battery Switchover

Hysteresis

BATT ON Output

Low Voltage

BATT ON Output

Short-Circuit Current

I

SINK

= 3.2mA

I

SINK

= 25mA

Sink current

Source current

RESET AND WATCHDOG TIMER

MAX691A, MAX800L

MAX693A, MAX800M

Reset Threshold Voltage

MAX800L, T

A

= +25°C, V

CC falling

MAX800M, T

A

= +25°C, V

CC falling

Reset Threshold Hysteresis

V

CC to RESET Delay

LOW LINE-to-RESET Delay

Power-down

1

4.50

4.25

4.55

4.30

60

0.1

0.7

60

15

4.65

4.40

15

80

800

0.4

1.5

100

4.75

4.50

4.70

4.45

mV

V mA

µA

V mV

µs ns

Reset Active Timeout Period,

Internal Oscillator

Power-up

Reset Active Timeout Period,

External Clock (Note 4)

Power-up

Watchdog Timeout Period,

Internal Oscillator

Watchdog Timeout Period,

External Clock (Note 4)

Long period

Short period

Long period

Short period

Minimum Watchdog Input

Pulse Width

V

IL

= 0.8V, V

IH

= 0.75 x V

CC

RESET Output Voltage

I

SINK

= 50µA, V

CC

= 1V, VBATT = 0V, V

CC falling

I

SINK

= 3.2mA, V

CC

= 4.25V

I

SOURCE

= 1.6mA, V

CC

= 5V

140

1.0

70

100

3.5

200

2048

1.6

100

4096

1024

0.004

0.1

280

2.25

140

0.3

0.4

ms

Clock

Cycles sec ms

Clock

Cycles ns

V

7 20 mA

Current

RESET Output Voltage Low

(Note 5)

Output source current

I

SINK

= 3.2mA

LOW LINE Output Voltage

I

SINK

= 3.2mA, V

CC

= 4.25V

I

SOURCE

= 1µA, V

CC

= 5V

LOW LINE Output

Short-Circuit Current

Output source current

WDO Output Voltage

I

SINK

= 3.2mA

I

SOURCE

= 500µA, V

CC

= 5V

WDO Output

Short-Circuit Current

WDI Threshold Voltage

(Note 6)

WDI Input Current

Output source current

V

IH

V

IL

WDI = 0V

WDI = V

OUT

0.1

3.5

1

3.5

0.75 x V

CC

-50

0.4

15

3

-10

20

0.4

100

0.4

10

0.8

50

V

V

µA

V mA

V

µA

_______________________________________________________________________________________ 3

Microprocessor Supervisory Circuits

ELECTRICAL CHARACTERISTICS (continued)

(MAX691A, MAX800L: V

CC unless otherwise noted.)

= +4.75V to +5.5V; MAX693A, MAX800M: V

CC

= +4.5V to +5.5V; VBATT = 2.8V, T

A

= T

MIN to T

MAX

,

PARAMETER

POWER-FAIL COMPARATOR

CONDITIONS MIN TYP MAX UNITS

PFI Input Threshold

PFI Leakage Current

PFO Output Voltage

MAX69_AC/AE/AM, V

CC

= 5V

MAX800_C/E, V

CC

= 5V

I

SINK

= 3.2mA

I

SOURCE

= 1µA, V

CC

= 5V

1.2

1.225

3.5

1.25

1.25

±0.01

1.3

1.275

±25

0.4

V nA

V

PFO Output Short-Circuit

Current

Output source current 1 15 100 µA

PFI-to-PFO Delay

V

IN

= -20mV, V

OD

= 15mV

V

IN

= 20mV, V

OD

= 15mV

25

60

µs

CHIP-ENABLE GATING

CE IN Leakage Current

CE IN-to-CE OUT Resistance

(Note 7)

CE OUT Short-Circuit Current

(Reset Active)

CE IN-to-CE OUT Propagation

Delay (Note 8)

CE OUT Output-Voltage High

(Reset Active)

RESET-to-CE OUT Delay

INTERNAL OSCILLATOR

OSC IN Leakage Current

OSC IN Input Pullup Current

OSC SEL Input Pullup Current

OSC IN Frequency Range

OSC IN External Oscillator

Threshold Voltage

Disable mode

Enable mode

Disable mode,

50

Ω source impedance driver, C

LOAD

= 50pF

V

CC

= 5V, I

OUT

= -100µA

V

CC

= 0V, VBATT = 2.8V, I

OUT

= 1µA

Power-down

OSC SEL = 0V

OSC SEL = V

OUT or floating, OSC IN = 0V

OSC SEL = 0V

OSC SEL = 0V

V

IH

V

IL

0.1

3.5

2.7

±0.005

75

0.75

6

12

0.10

10

10

50

V

OUT

- 0.3

V

OUT

- 0.6

3.65

±1

150

2.0

10

±5

100

100

2.00

µA

Ω mA ns

V

µs

µA

µA

µA kHz

V

OSC IN Frequency with

External Capacitor

OSC SEL = 0V, COSC = 47pF 100 kHz

Note 1: Either V

CC or VBATT can go to 0V, if the other is greater than 2.0V.

Note 2: The supply current drawn by the MAX691A/MAX800L/MAX800M from the battery excluding I

OUT typically goes to 10µA when (VBATT - 1V) < V

CC

< VBATT. In most applications, this is a brief period as V

CC falls through this region.

Note 3: “+” = battery-discharging current, “--” = battery-charging current.

Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature.

Note 5: RESET is an open-drain output and sinks current only.

Note 6: WDI is internally connected to a voltage divider between V

OUT and GND. If unconnected, WDI is driven to 1.6V (typ), disabling the watchdog function.

Note 7: The chip-enable resistance is tested with V

CC

= +4.75V for the MAX691A/MAX800L and V

CC

= +4.5V for the

MAX693A/MAX800M. CE IN = CE OUT = V

CC

/2.

Note 8: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.

4 _______________________________________________________________________________________

Microprocessor Supervisory Circuits

__________________________________________Typical Operating Characteristics

(T

A

= +25°C, unless otherwise noted.)

V

CC

SUPPLY CURRENT vs. TEMPERATURE

(NORMAL OPERATING MODE)

36

34

V

CC

= 5V

VBATT = 2.8V

PFI, CE IN = 0V

BATTERY SUPPLY CURRENT vs. TEMPERATURE

(BATTERY-BACKUP MODE)

2

1.5

V

CC

= 5V

VBATT = 2.8V

NO LOAD

CHIP-ENABLE ON-RESISTANCE vs. TEMPERATURE

120

V

CC

= 4.75V

VBATT = 2.8V

V

CE IN

= V

CC

/2

100

32

1

80

30

60

28

0.5

26

-60 -30 0 30 60

TEMPERATURE (

°C)

90 120 150

VBATT to V

OUT

ON-RESISTANCE vs. TEMPERATURE

20

VBATT = 2.0V

15

VBATT = 2.8V

10

5

-60

VBATT = 4.5V

-30 0 30 60

TEMPERATURE (

°C)

90

V

CC

= 0V

120 150

4.75

VBATT = 2.8V

4.70

RESET THRESHOLD vs. TEMPERATURE

4.65

4.60

MAX691A

MAX800L

4.55

4.50

4.45

4.40

4.35

4.30

-60

MAX693A

MAX800M

-30 0 30 60

TEMPERATURE (

°C)

90 120 150

0.8

0.7

1.0

0.9

0

-60 -30 0 30 60

TEMPERATURE (

°C)

90 120 150

V

CC to V

OUT

ON-RESISTANCE vs. TEMPERATURE

1.2

V

CC

= 5V,

VBATT = 0V

1.1

0.6

-60 -30 0 30 60

TEMPERATURE (

°C)

90 120 150

RESET OUTPUT RESISTANCE vs. TEMPERATURE

600

500

V

CC

= 5V, VBATT = 2.8V

SOURCING CURRENT

400

300

200

100

0

-60 -30

V

CC

= 0V, VBATT = 2.8V

SINKING CURRENT

0 30 60

TEMPERATURE (

°C)

90 120 150

210

200

190

180

1.25

1.00

0.75

40

-60 -30 0 30 60 90

TEMPERATURE (

°C)

120 150 180

PFI THRESHOLD vs. TEMPERATURE

1.50

0.50

0.25

0

-60 -30 0 30 60

V

CC

= +5V,

VBATT = 0V

NO LOAD ON PFO

120 150

TEMPERATURE (

°C)

90

230

220

RESET DELAY vs. TEMPERATURE

V

CC

= 0V TO 5V STEP

VBATT = 2.8V

170

-60 -30 0 30 60

TEMPERATURE (

°C)

90 120 150

_______________________________________________________________________________________ 5

Microprocessor Supervisory Circuits

____________________________Typical Operating Characteristics (continued)

(T

A

= +25°C, unless otherwise noted.)

8

4

BATTERY CURRENT vs. INPUT SUPPLY VOLTAGE

20

VBATT = 2.8V

I

OUT

= 0A

16

12

0

0 1 2

V

CC

(V)

3 4 5

V

CC to V

OUT

vs. OUTPUT CURRENT

(NORMAL OPERATING MODE)

1000

V

CC

= 4.5V

VBATT = 0V

100

10

SLOPE = 0.8

Ω

1

1 10

I

OUT

(mA)

100 1000

100

WATCHDOG AND RESET TIMEOUT PERIOD vs. OSC IN TIMING CAPACITOR (COSC)

1

0.1

10

V

CC

= 5V

VBATT = 2.8V

10

RESET ACTIVE

TIMEOUT PERIOD

LONG WATCHDOG

TIMEOUT PERIOD

SHORT WATCHDOG

TIMEOUT PERIOD

100

COSC (pF)

1000

CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE

20

16

V

CC

= 5V

CE IN = 0V

TO 5V

DRIVER SOURCE

12

8

4

0

0 50 100 150

C

LOAD

(pF)

200 250 300

VBATT to V

OUT

vs. OUTPUT CURRENT

(BATTERY-BACKUP MODE)

1000

V

CC

= 0V

VBATT = 4.5V

100

10

1

1

SLOPE = 8

Ω

10

I

OUT

(mA)

5V

V

CC

RESET

THRESHOLD

100

HI

LOW LINE

LO

HI

RESET

LO

HI

CE OUT

LO

80

μs

800ns

V

CC

to LOW LINE

AND CE OUT DELAY

12

μs

6 _______________________________________________________________________________________

Microprocessor Supervisory Circuits

______________________________________________________________Pin Description

PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

NAME FUNCTION

VBATT

V

OUT

Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not used, connect to GND.

Output Supply Voltage. When V

CC is greater than VBATT and above the reset threshold, V

OUT connects to

V

CC

. When V

CC falls below VBATT and is below the reset threshold, V

OUT connects to VBATT. Connect a 0.1µF capacitor from V

OUT to GND. Connect V

OUT to V

CC if no backup battery is used.

Input Supply Voltage, 5V Input.

V

CC

GND

Ground. 0V reference for all signals.

BATT ON

Battery-On Output. When V

OUT switches to VBATT, BATT ON goes high. When V

OUT switches to V

CC,

BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for V

OUT current requirements greater than 250mA.

LOW LINE LOW LINE output goes low when V

CC the reset threshold.

falls below the reset threshold. It returns high as soon as V

CC rises above

OSC IN

External Oscillator Input. When OSC SEL is unconnected or driven high, a 10µA pull-up connects from V

OUT to

OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3).

OSC SEL

PFI

PFO

WDI

CE OUT

CE IN

WDO

RESET

RESET

Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1).

OSC SEL has a 10µA internal pull-up.

Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO goes low. When PFI is not used, connect PFI to GND or V

OUT

.

Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V.

This is an uncommitted comparator, and has no effect on any other internal circuitry.

Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog timeout period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next transition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between V

OUT and GND, which sets it to mid-supply when left unconnected.

Chip-Enable Output. CE OUT goes low only when CE IN is low and V

CC is above the reset threshold. If CE IN is low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever occurs first.

Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or V

OUT.

Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if

WDI is unconnected.

RESET Output goes low whenever V

CC falls below the reset threshold. RESET will remain low typically for

200ms after V

CC crosses the reset threshold on power-up.

RESET is an active-high output. It is open drain, and the inverse of RESET.

_______________Detailed Description

– —

R

E

S

E

T and RESET Outputs

The MAX691A/MAX693A/MAX800L/MAX800M’s RESET and RESET outputs ensure that the µP (with reset inputs asserted either high or low) powers up in a known state, and prevents code-execution errors during power-down or brownout conditions.

The RESET output is active low, and typically sinks

When deasserted,

V

OUT

- 0.5V. RESET output is open drain, active high, and typically sinks 3.2mA with a saturation voltage of

0.1V. When no backup battery is used, RESET output is guaranteed to be valid down to V

CC

= 1V, and an external 10k

Ω pulldown resistor on RESET insures that it will be valid with V

CC

V

CC down to GND (Figure 1). As goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the R

DS(ON) and the saturation voltage. The 10k

Ω pulldown resistor insures the parallel combination of switch plus resistor is around 10k

Ω and the output saturation voltage is below 0.4V while sinking 40µA. When using a 10k

Ω external pulldown resistor, the high state for

RESET output with V

CC

= 4.75V will be 4.5V typical.

For battery voltages

≥ 2V connected to VBATT, RESET and RESET remain valid for V

CC from 0V to 5.5V.

_______________________________________________________________________________________ 7

Microprocessor Supervisory Circuits

WDI

RESET

15

MAX691A

MAX693A

1k

Ω

TO

μP RESET

WDO

RESET t

1 t

2 t

1 t

3 t

1

= RESET TIMEOUT PERIOD t

2

= NORMAL WATCHDOG TIMEOUT PERIOD t

3

= WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET

Figure 2. Watchdog Timeout Period and Reset Active Time

R E S

— is valid with V

CC down to GND.

RESET and RESET are asserted when V

CC falls below the reset threshold (4.65V for the MAX691A/MAX800L,

4.4V for the MAX693A/MAX800M) and remain asserted for 200ms typ after V

CC rises above the reset threshold on power-up (Figure 5). The devices’ batteryswitchover comparator does not affect reset assertion.

However, both reset outputs are asserted in batterybackup mode since V

CC threshold to enter this mode.

must be below the reset

Watchdog Function

The watchdog monitors µP activity via the Watchdog

Input (WDI). If the µP becomes inactive, RESET and

RESET are asserted. To use the watchdog function, connect WDI to a bus line or µP I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6s nominal), WDO, RESET, and RESET are asserted (see RESET and RESET Outputs section, and the Watchdog Output discussion on this page).

Watchdog Input

A change of state (high to low, low to high, or a minimum 100ns pulse) at the WDI during the watchdog period resets the watchdog timer. The watchdog default timeout is 1.6s.

To disable the watchdog function, leave WDI floating.

An internal resistor network (100k

Ω equivalent impedance at WDI) biases WDI to approximately 1.6V.

Internal comparators detect this level and disable the watchdog timer. When V

CC is below the reset threshold, the watchdog function is disabled and WDI is disconnected from its internal resistor network, thus becoming high impedance.

Watchdog Output

The Watchdog Output (WDO) remains high if there is a transition or pulse at WDI during the watchdog timeout period. The watchdog function is disabled and

– a logic high when V

CC is below the reset threshold, battery-backup mode is enabled, or WDI is an open circuit.

In watchdog mode, if no transition occurs at WDI during the watchdog timeout period, RESET and RESET are asserted for the reset timeout period (200ms typical).

WDO goes low and remains low until the next transition at WDI (Figure 2). If WDI is held high or low indefinitely,

RESET and RESET will generate 200ms pulses every

1.6s. WDO has a 2 x TTL output characteristic.

Selecting an Alternative

Watchdog and Reset Timeout Period

The OSC SEL and OSC IN inputs control the watchdog and reset timeout periods. Floating OSC SEL and OSC

IN or tying them both to V

OUT selects the nominal 1.6s

watchdog timeout period and 200ms reset timeout period. Connecting OSC IN to GND and floating or connecting OSC SEL to V

OUT selects the 100ms normal watchdog timeout delay and 1.6s delay immediately after reset. The reset timeout delay remains 200ms

(Figure 2). Select alternative timeout periods by connecting OSC SEL to GND and connecting a capacitor between OSC IN and GND, or by externally driving OSC

IN (Table 1 and Figure 3). OSC IN is internally connected to a ±100nA (typ) current source that charges and discharges the timing capacitor to create the oscillator frequency, which sets the reset and watchdog timeout periods (see Connecting a Timing Capacitor at OSC IN in the Applications Information section).

8 _______________________________________________________________________________________

Microprocessor Supervisory Circuits

Table 1. Reset Pulse Width and Watchdog Timeout Selections

OSC SEL

Low

Low

Floating

Floating

OSC IN

External Clock Input

External Capacitor

Low

Floating

Watchdog Timeout Period

Normal Immediately After Reset

1024 clks

(600/47pF x C)ms

100ms

1.6s

4096 clks

(2.4/47pF x C)sec

1.6s

1.6s

Reset Timeout Period

2048 clks

(1200/47pF x C)ms

200ms

200ms

MAX691A

MAX693A

MAX800L

MAX800M

50kHz

EXTERNAL

CLOCK

8

OSC SEL

7

OSC IN

EXTERNAL

OSCILLATOR

8

OSC SEL

7

OSC IN

N.C.

INTERNAL OSCILLATOR

1.6s WATCHDOG

8

OSC SEL

N.C.

INTERNAL OSCILLATOR

100ms WATCHDOG

8

OSC SEL

N.C.

7

OSC IN

7

OSC IN

Figure 3. Oscillator Circuits

Chip-Enable Signal Gating

The MAX691A/MAX693A/MAX800L/MAX800M provide internal gating of chip-enable (CE) signals to prevent erroneous data from being written to CMOS RAM in the event of a power failure. During normal operation, the

CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. All these parts use a series transmission gate from

CE OUT (Figure 4).

The 10ns max CE propagation delay from CE IN to CE

OUT enables the parts to be used with most µPs.

Chip-Enable Input

The Chip-Enable Input (CE IN) is high impedance (disabled mode) while RESET and RESET are asserted.

During a power-down sequence where V

CC falls below the reset threshold or a watchdog fault,

CE IN assumes a high-impedance state when the voltage at CE IN goes high or 15µs after reset is asserted, whichever occurs first (Figure 5).

During a power-up sequence, CE IN remains high impedance, regardless of CE IN activity, until reset is deasserted following the reset timeout period.

In the high-impedance mode, the leakage currents into this terminal are ±1µA max over temperature. In the low-impedance mode, the impedance of

– as a 75

Ω resistor in series with the load at CE OUT.

The propagation delay through the CE transmission gate depends on both the source impedance of the drive to

Enable Output (

CE OUT) (see Chip-Enable Propagation

Delay vs. CE OUT Load Capacitance in the Typical

Operating Characteristics). The CE propagation delay is production tested from the 50% point of

50% point of

Ω driver and 50pF of load capacitance (Figure 6). For minimum propagation delay, minimize the capacitive load at CE OUT, and use a low output-impedance driver.

Chip-Enable Output

In the enabled mode, the impedance of CE OUT is equivalent to 75

Ω in series with the source driving CE

IN. In the disabled mode, the 75

Ω transmission gate is off and CE OUT is actively pulled to V

OUT

. This source turns off when the transmission gate is enabled.

L

O W

— —

L I

N

E Output

LOW LINE is the buffered output of the reset threshold comparator. LOW LINE typically sinks 3.2mA at 0.1V.

For normal operation (V

CC above the LOW LINE threshold), LOW LINE is pulled to V

OUT

.

Power-Fail Comparator

The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the IC.

Common uses include low-battery indication (Figure 7), and early power-fail warning (see Typical Operating

Circuit).

Power-Fail Input

Power-Fail Input (PFI) is the input to the power-fail comparator. It has a guaranteed input leakage of ±25nA max over temperature. The typical comparator delay is

25µs from V

IL to V

OL to V

OH nect it to ground.

(power failing), and 60µs from V

IH

(power being restored). If PFI is not used, con-

_______________________________________________________________________________________ 9

Microprocessor Supervisory Circuits

5 BATT ON

4.65V*

V

CC

3

VBATT

1

13

CE IN

CHIP-ENABLE

OUTPUT

CONTROL

OSC IN

OSC SEL

7

8

WDI

PFI

11

9

MAX691A

MAX693A

MAX800L

MAX800M

RESET

GENERATOR

TIMEBASE FOR

RESET AND

WATCHDOG

WATCHDOG

TRANSITION

DETECTOR

WATCHDOG

TIMER

1.25V

4

GND

* 4.4V FOR THE MAX693A/MAX800M

Figure 4. MAX691A/MAX693A/MAX800L/MAX800M Block Diagram

5.0V

4.0V

5.0V

V

CC

RESET

THRESHOLD

CE IN

0V

5V

0V

CE OUT

5V

0V

5V

0V

RESET

RESET

LOGIC LEVELS SHOWN ARE FROM 0V TO 5V.

15

μs

100

μs

100

μs

Figure 5. Reset and Chip-Enable Timing

10 ______________________________________________________________________________________

6

LOW LINE

2

V

OUT

12

16

CE OUT

RESET

15

RESET

14

WDO

10

PFO

Microprocessor Supervisory Circuits

2.8V

+5V

VBATT

V

CC

CE IN

MAX691A

MAX693A

MAX800L

MAX800M

CE OUT

GND

2.0V to 5.5V

+5V

VBATT

V

CC

PFI

MAX691A

MAX693A

MAX800L

MAX800M

PFO

GND

LOW BATT

50

Ω

OUTPUT

IMPEDANCE

C

LOAD

Figure 6. CE Propagation Delay Test Circuit Figure 7. Low-Battery Indicator

Table 2. Input and Output Status in Battery-Backup

Mode

PIN

1

2

NAME

VBATT

V

OUT

STATUS

Supply current is 1µA max.

V

OUT is connected to VBATT through an internal PMOS switch.

3

4

5

6

7

8

9

V

CC

GND

Battery switchover comparator monitors

V

CC for active switchover.

GND 0V, 0V reference for all signals.

BATT ON

Logic high. The open-circuit output is equal to V

OUT

.

LOWLINE

Logic low*

OSC IN OSC IN is ignored.

OSC SEL OSC SEL is ignored.

PFI

The power-fail comparator remains active in the battery-backup mode for

V

CC

≥ VBATT - 1.2V typ.

10

PFO

The power-fail comparator remains active in the battery-backup mode for

V

CC

≥ VBATT - 1.2V typ. Below this voltage, PFO is forced low.

11

12

WDI

CE OUT

Watchdog is ignored.

Logic high. The open-circuit voltage is equal to V

OUT

.

High impedance 13

CE IN

14

WDO

Logic high. The open-circuit voltage is equal to V

OUT

.

15

16

RESET

RESET

Logic low*

High impedance*

* V

CC must be below the reset threshold to enter battery-backup mode.

Power-Fail Output

The Power-Fail Output (PFO) goes low when PFI goes below 1.25V. It typically sinks 3.2mA with a saturation voltage of 0.1V. With PFI above 1.25V, PFO is actively pulled to V

OUT

.

Battery-Backup Mode

Two conditions are required to switch to battery-backup mode: 1) V

CC and 2) V

CC must be below the reset threshold, must be below VBATT. Table 2 lists the status of the inputs and outputs in battery-backup mode.

Battery-On Output

The Battery-On (BATT ON) output indicates the status of the internal V

CC

/battery-switchover comparator, which controls the internal V

For V

CC

CC and VBATT switches.

greater than VBATT (ignoring the small hysteresis effect), BATT ON typically sinks 3.2mA at 0.1V

saturation voltage. In battery-backup mode, this terminal sources approximately 10µA from V

OUT

. Use BATT

ON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-current applications (see

Typical Operating Circuit).

Input Supply Voltage

The Input Supply Voltage (V

CC

5V. V

CC connects to V

OUT

) should be a regulated via a parallel diode and a large PMOS switch. The switch carries the entire current load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. Both the switch and the diode have impedances less than 1

Ω each. The maximum continuous current is 250mA, but power-on transients may reach a maximum of 1A.

______________________________________________________________________________________ 11

Microprocessor Supervisory Circuits

Battery-Backup Input

The Battery-Backup Input (VBATT) is similar to the V

CC input except the PMOS switch and parallel diode are much smaller. Accordingly, the on-resistances of the diode and the switch are each approximately 10

Ω.

Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA.

The reverse leakage of this input is less than 1µA over temperature and supply voltage (Figure 8).

Output Supply Voltage

The Output Supply Voltage (V

OUT

) pin is internally connected to the substrate of the IC and supplies current to the external system and internal circuitry. All opencircuit outputs will, for example, assume the V

OUT age in their high states rather than the V

CC voltvoltage. At the maximum source current of 250mA, V

OUT cally be 200mV below V a 0.1µF capacitor.

CC will typi-

. Decouple this terminal with

__________Applications Information

The MAX691A/MAX693A/MAX800L/MAX800M are not short-circuit protected. Shorting V

OUT to ground, other than power-up transients such as charging a decoupling capacitor, destroys the device.

All open-circuit outputs swing between V

OUT rather than V

CC and GND.

and GND

If long leads connect to the chip inputs, insure that these leads are free from ringing and other conditions that would forward bias the chip’s protection diodes.

There are three distinct modes of operation:

1) Normal operating mode with all circuitry powered up. Typical supply current from V

CC is 35µA while only leakage currents flow from the battery.

2) Battery-backup mode where V

CC is typically within

0.7V below VBATT. All circuitry is powered up and the supply current from the battery is typically less than 60µA.

3) Battery-backup mode where V

CC is less than

VBATT by at least 0.7V. VBATT supply current is

1µA max.

Using SuperCap or MaxCap with the

MAX691A/MAX693A/MAX800L/MAX800M

VBATT has the same operating voltage range as V

CC and the battery switchover threshold voltages are typi-

, cally ±30mV centered at VBATT, allowing use of a

SuperCap and a simple charging circuit as a backup source (Figure 9).

If V

CC is above the reset threshold and VBATT is 0.5V

above V

CC

, current flows to V

OUT and V

CC from VBATT until the voltage at VBATT is less than 0.5V above V

CC

For example, with a SuperCap connected to VBATT and

.

through a diode to V

CC

, if V

CC quickly changes from 5.4V

to 4.9V, the capacitor discharges through V

OUT and V

CC until VBATT reaches 5.1V typ. Leakage current through the SuperCap charging diode and the internal power diode eventually discharges the SuperCap to V

CC

V

CC

. Also, if and VBATT start from 0.1V above the reset threshold and power is lost at V

CC charges through V

CC

, the SuperCap on VBATT disuntil VBATT reaches the reset threshold; then the battery-backup mode is initiated and the current through V

CC goes to zero.

VBATT

V

CC

MAX691A

MAX693A

MAX800L

MAX800M

0.1

μF

V

OUT

+5V

3

V

CC

1N4148

0.47F*

* MaxCap

1

VBATT

MAX691A

MAX693A

MAX800L

MAX800M

GND

4

V

OUT

2

Figure 9. SuperCap or MaxCap on VBATT Figure 8. V

CC and VBATT to V

OUT

Switch

12 ______________________________________________________________________________________

Microprocessor Supervisory Circuits

MAX691A

MAX693A

MAX800L

MAX800M

GND

Rp*

CE IN

V

OUT

CE OUT

*MAXIMUM Rp VALUE DEPENDS ON

THE NUMBER OF RAMS.

MINIMUM Rp VALUE IS 1k

Ω.

Figure 10. Alternate CE Gating

ACTIVE-HIGH

CE LINES

FROM LOGIC

CE

CE

RAM 1

CE

CE

RAM 2

CE

CE

RAM 3

CE

CE

RAM 4

Using Separate Power Supplies for VBATT and V

If using separate power supplies for V

CC

VBATT must be less than 0.3V above V

CC when V

CC

CC

and VBATT, is above the reset threshold. As described in the previous section, if VBATT exceeds this limit and power is lost at V

CC

, current flows continuously from VBATT to

V

CC via the VBATT-to-V

OUT diode and the V

OUT

-to-V

CC switch until the circuit is broken (Figure 8).

Alternate Chip-Enable Gating

Using memory devices with both CE and CE inputs allows the CE loop to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to V

OUT connect device (Figure 10). The CE input of each part then connects directly to the chip-select logic, which does not have to be gated.

Adding Hysteresis to the

Power-Fail Comparator

Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of PFO when

V

IN is near the power-fail comparator trip point. Figure

11 shows how to add hysteresis to the power-fail com-

V

IN

+5V

R1

C1*

V

CC

PFI

R2

R3

MAX691A

MAX693A

MAX800L

MAX800M

PFO

GND

TO

μP

*OPTIONAL

5V

PFO

0V

0V V

L

V

TRIP

V

IN

V

H

V

TRIP

= 1.25

R1 + R2

R2

V

H

= 1.25/

R2 I I R3 V

L

- 1.25

+

5 - 1.25

=

1.25

R1 + R2 I I R3 R1 R3 R2

Figure 11. Adding Hysteresis to the Power-Fail Comparator

+5V

R1

R2

V-

5V

PFO

0V

5 - 1.25

=

1.25 - V

R1 R2

TRIP

NOTE: V

TRIP

IS NEGATIVE.

PFI

V

TRIP

V-

V

CC

MAX691A

MAX693A

MAX800L

MAX800M

GND

Figure 12. Monitoring a Negative Voltage

PFO

0V

______________________________________________________________________________________ 13

Microprocessor Supervisory Circuits

100

80

60

40

V

T

CC

A

= 5V

= +25

°C

0.1

μF CAPACITOR

FROM V

OUT

TO GND

20

0

10 100 1000

RESET COMPARATOR OVERDRIVE,

(Reset Threshold Voltage - V

CC

) (mV)

10000

Figure 13. Maximum Transient Duration without Causing a

Reset Pulse vs. Reset Comparator Overdrive parator. Select the ratio of R1 and R2 such that PFI sees

1.25V when V

IN falls to the desired trip point (V

TRIP

).

Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1µA to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10k

Ω to prevent it from loading down the PFO pin. Capacitor C1 adds noise rejection.

Monitoring a Negative Voltage

The power-fail comparator can be used to monitor a negative supply voltage using Figure 12’s circuit. When the negative supply is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit’s accuracy is affected by the PFI threshold tolerance, the V

CC voltage, and resistors R1 and R2.

Backup-Battery Replacement

The backup battery may be disconnected while V

CC is above the reset threshold. No precautions are necessary to avoid spurious reset pulses.

Negative-Going V

CC

Transients

While issuing resets to the µP during power-up, powerdown, and brownout conditions, these supervisors are relatively immune to short-duration, negative-going V

CC transients (glitches). It is usually undesirable to reset the µP when V

CC experiences only small glitches.

Figure 13 shows maximum transient duration vs. resetcomparator overdrive, for which reset pulses are not generated. The graph was produced using negativegoing V

CC pulses, starting at 5V and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the maximum pulse width a negative-going V

CC transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a V

CC transient that goes 100mV below the reset threshold and lasts for

40µs or less will not cause a reset pulse to be issued.

A 100nF bypass capacitor mounted close to the V

CC pin provides additional transient immunity.

Connecting a Timing Capacitor at OSC IN

When OSC SEL is connected to ground, OSC IN disconnects from its internal 10µA (typ) pullup and is internally connected to a ±100nA current source. When a capacitor is connected from OSC IN to ground (to select alternative reset and watchdog timeout periods), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and watchdog timeout period. To prevent timing errors or oscillator startup problems, minimize external current leakage sources at this pin, and locate the capacitor as close to OSC IN as possible. The sum of PC-board leakage plus OSC capacitor leakage must be small compared to ±100nA.

14 ______________________________________________________________________________________

Microprocessor Supervisory Circuits

Maximum V

CC

Fall Time

The V

CC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/µs. A standard rule of thumb for filter capacitance on most regulators is on the order of 100µF per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial

V

CC fall rate is just the inverse or 1A/100µF = 0.01V/µs.

The V

CC fall rate decreases with time as V

CC falls exponentially, which more than satisfies the maximum fall-time requirement.

Watchdog Software Considerations

A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than “pulsing” the watchdog input high-low-high or low-high-low. This technique avoids a “stuck” loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure

14 shows an example flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should “hang” in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued.

START

SET

WDI

LOW

SUBROUTINE

OR PROGRAM LOOP

SET WDI

HIGH

RETURN

END

Figure 14. Watchdog Flow Diagram

______________________________________________________________________________________ 15

Microprocessor Supervisory Circuits

Ordering Information (continued)

PART TEMP RANGE

PIN -

PA C K A G E

MAX691AEJE -40°C to +85°C

MAX691AMJE

MAX691AMSE/PR

-55°C to +125°C

-55°C to +125°C

MAX691AMSE/PR-T -55°C to +125°C

MAX693ACUE -0°C to +70°C

MAX693ACSE

MAX693ACWE

MAX693ACPE

MAX693AC/D

-0°C to +70°C

-0°C to +70°C

-0°C to +70°C

-0°C to +70°C

MAX693AEUE

MAX693AESE

MAX693AEWE

MAX693AEPE

MAX693AEJE

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

MAX693AMJE

MAX800LCUE

-55°C to +125°C

-0°C to +70°C

MAX800LCSE

MAX800LCPE

MAX800LEUE

MAX800LESE

MAX800LEPE

MAX800MCUE

MAX800MCSE

MAX800MCPE

MAX800MEUE

MAX800MESE

MAX800MEPE

-0°C to +70°C

-0°C to +70°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

-0°C to +70°C

-0°C to +70°C

-0°C to +70°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

* Dice are specified at T

A

= +25°C, DC parameters only.

** Contact factory for availability and processing to MIL-STD-883B.

Devices in PDIP, SO and TSSOP packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering.

Lead free not available for CERDIP package.

16 CERDIP

16 CERDIP**

16 Wide SO**

16 Wide SO**

16 TSSOP

16 Narrow SO

16 Wide SO

16 Plastic DIP

Dice*

16 TSSOP

16 Narrow SO

16 Wide SO

16 Plastic DIP

16 CERDIP

16 CERDIP

16 TSSOP

16 Narrow SO

16 Plastic DIP

16 TSSOP

16 Narrow SO

16 Plastic DIP

16 TSSOP

16 Narrow SO

16 Plastic DIP

16 TSSOP

16 Narrow SO

16 Plastic DIP

___________________Chip Topography

V

CC

GND

V

OUT

VBATT RESET RESET

BATT ON

LOW LINE

OSC IN

PFI PFO

OSC SEL

0.07"

(1.778mm)

SUBSTRATE CONNECTED TO V

OUT

WDI

WDO

CE IN

CE OUT

0.11"

(2.794mm)

Package Information

For the latest package outline information and land patterns, go to

www.maxim-ic.com/packages

.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

16 TSSOP U16-1

21-0066

16 CERDIP

16 Narrow SO

J16-3

S16-3

21-0045

21-0041

16 Plastic DIP

16 Wide SO

P16-1

W16-1

21-0043

21-0042

16 ______________________________________________________________________________________

Microprocessor Supervisory Circuits

REVISION

NUMBER

6

7

4

5

2

3

0

1

8

9

10

11

REVISION

DATE

09/92

12/92

5/93

12/93

3/94

8/94

1/95

12/96

12/99

4/02

11/05

8/08

DESCRIPTION

Initial release

Update Electrical Characteristics table.

Update Electrical Characteristics table, Tables 1 and 2.

Update Electrical Characteristics table.

Update Electrical Characteristics table.

Correction to Figure 4.

Update to new revision and correct errors.

Update Electrical Characteristics table.

Updated Ordering Information, Pin Configuration, Absolute Maximum

Ratings, and Package Information.

Corrected Ordering Information.

Added lead-free information.

Updated Ordering Information.

Revision History

PAGES

CHANGED

2, 3, 4

2, 3, 4, 9, 11

2, 3, 4

2, 3, 4

10

2, 3, 4

1, 2, 16

1

1, 16

1, 16

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17

© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement

Table of contents