HY62UF16806B-LL

HY62UF16806B-LL
HY62UF16806B Series
512Kx16bit full CMOS SRAM
Document Title
512K x16 bit 3.0V Super Low Power Full CMOS slow SRAM
Revision History
Revision No
History
00
Initial Release
01
DC Para Change
Icc
4mA à
Icc1(Min) 40mA à
Icc1(1us)
8mA à
Isb
0.1mA à
Isb1
25uA à
Iccdr
12uA à
Draft Date
Remark
May.29.2001
Preliminary
Mar.20.2002
3mA
20mA
2mA
0.3mA
15uA
6uA
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.01 / Mar. 2002
Hynix Semiconductor
HY62UF16806B
Preliminary
DESCRIPTION
FEATURES
The HY62UF16806B is a high speed, super low
power and 8Mbit full CMOS SRAM organized as
524,288 words by 16bits. The HY62UF16806B
uses high performance full CMOS process
technology and is designed for high speed and
low power circuit technology. It is particularly wellsuited for the high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 1.2V.
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(LL/SL-part)
- 1.2V(min) data retention
• Standard pin configuration
- 48-FBGA
Product
Voltage
Speed
No.
(V)
(ns)
HY62UF16806B-C
2.7~3.3 55/70/85
HY62UF16806B-I
2.7~3.3 55/70/85
Note 1. C : Commercial, I : Industrial
2. Current value is max.
Operation
Current/Icc(mA)
3
3
PIN CONNECTION ( Top View )
H
/OE
A0
A1
A2
CS2
IO9
/UB
A3
A4
/CS1
IO1
IO10 IO11 A5
A6
IO2
IO3
Vss
IO12 A17
A7
IO4
Vcc
Vcc
IO13 Vss
A16
IO5
Vss
IO15 IO14 A14
A15
IO6
IO7
A18
IO16 NC
A12
A13
/WE IO8
A18
A9
A10
A11
A8
NC
MEMORY ARRAY
512K x 16
I/O1
I/O8
DATA I/O
BUFFER
G
/LB
ROW
DECODER
WRITE DRIVER
F
6
BLOCK
DECODER
E
5
COLUMN
DECODER
D
4
PRE DECODER
C
3
BLOCK DIAGRAM
ADD INPUT
BUFFER
B
2
Temperature
(°C)
0~70
-40~85
SENSE AMP
A
1
Standby Current(uA)
LL
15
15
I/O9
I/O16
/CS1
CS2
/OE
/LB
/UB
/WE
PIN DESCRIPTION
Pin Name
/CS1, CS2
/WE
/OE
/LB
/UB
Pin Function
Chip Select
Write Enable
Output Enable
Lower Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
Rev.01/Mar. 2002
Pin Name
I/O1~I/O16
A0~A18
Vcc
Vss
NC
Pin Function
Data Inputs / Outputs
Address Inputs
Power(2.7V~3.3V)
Ground
No Connection
2
HY62UF16806B
ORDERING INFORMATION
Part No.
Speed
HY62UF16806B-DFC
55/70/85
HY62UF16806B-DFI
55/70/85
Note 1. C : Commercial, I : Industrial
Power
LL-part
LL-part
Package
FBGA
FBGA
Temp.
C
I
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
Parameter
Input/Output Voltage
Power Supply
TA
Operating Temperature
TSTG
PD
TSOLDER
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
Rating
-0.3 to Vcc+0.3
-0.3 to 4.6
0 to 70
-40 to 85
-55 to 150
1.0
260 • 10
Unit
V
V
°C
°C
°C
W
°C • sec
Remark
HY62UF16806B-C
HY62UF16806B-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
CS2
/WE
/OE
/LB
/UB
H
X
X
L
L
L
X
L
X
H
H
H
X
X
X
H
H
H
X
X
X
H
H
L
X
X
H
L
X
L
H
L
L
H
L
X
X
H
X
L
H
L
L
H
L
L
L
H
L
X
Mode
Deselected
Output Disabled
Read
Write
I/O Pin
I/O1~I/O8
I/O9~I/O16
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DOUT
Hi-Z
Hi-Z
DOUT
DOUT
DOUT
DIN
Hi-Z
Hi-Z
DIN
DIN
DIN
Power
Standby
Active
Active
Active
Note:
1. H=VIH, L=VIL, X=don't care(VIH or VIL)
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When /UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.01/Mar. 2002
2
HY62UF16806B
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
0
2.2
-0.3(1)
Typ.
3.0
0
-
Max.
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note : 1. VIL = -1.5V for pulse width less than 30ns
DC ELECTRICAL CHARACTERISTICS
Vcc = 2.7V~3.3V, TA = 0°C to 70°C/ -40°C to 85°C
Sym
Parameter
Test Condition
ILI
Input Leakage Current
Vss < VIN < Vcc
Vss < VOUT < Vcc,
/CS1 = VIH or CS2=VIL or
ILO
Output Leakage Current
/OE = VIH or /WE = VIL or
/UB = VIH , /LB = VIH
/CS1 = VIL, CS2=VIH,
Icc
Operating Power Supply Current
VIN = VIH or VIL, II/O = 0mA
/CS1 = VIL, CS2 = VIH,
VIN = VIH or VIL, Cycle Time = Min,
100% Duty, II/O = 0mA
ICC1 Average Operating Current
/CS1 < 0.2V, CS2 > Vcc-0.2V,
VIN < 0.2V or VIN > Vcc-0.2V,
Cycle Time = 1us,
100% Duty, II/O = 0mA
/CS1 = VIH or CS2 = VIL or
ISB
Standby Current (TTL Input)
/UB, /LB = VIH
VIN = VIH or VIL
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
ISB1
Standby Current (CMOS Input)
/UB, /LB > Vcc - 0.2V
LL
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
VOL
Output Low
IOL = 2.1mA
VOH Output High
IOH = -1.0mA
Min
-1
-1
2.4
Typ1.
-
Max
1
1
Unit
uA
uA
3
mA
20
mA
2
mA
0.3
mA
1
15
uA
-
0.4
-
V
V
Note :
1.Typical values are at Vcc = 3.0V, TA = 25°C
2. Typical values are not 100% Tested
CAPACITANCE
(Temp = 25°C, f = 1.0MHz)
Symbol
Parameter
CIN
Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE)
COUT
Output Capacitance (I/O)
Condition
VIN = 0V
VI/O = 0V
Max.
8
10
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
Rev.01/Mar. 2002
3
HY62UF16806B
AC CHARACTERISTICS
Vcc = 2.7V~3.3V, TA = 0°C to 70°C/ -40°C to 85°C unless otherwise specified
-55
-70
#
Symbol
Parameter
Max.
Min.
Max. Min.
READ CYCLE
1
tRC
Read Cycle Time
55
70
2
tAA
Address Access Time
55
70
3
tACS
Chip Select Access Time
55
70
4
tOE
Output Enable to Output Valid
30
35
5
tBA
/LB, /UB Access Time
55
70
6
tCLZ
Chip Select to Output in Low Z
10
10
7
tOLZ
Output Enable to Output in Low Z
5
5
8
tBLZ
/LB, /UB Enable to Output in Low Z
10
10
9
tCHZ
Chip Deselection to Output in High Z
0
30
0
30
10 tOHZ
Out Disable to Output in High Z
0
30
0
30
11 tBHZ
/LB, /UB Disable to Output in High Z
0
30
0
30
12 tOH
Output Hold from Address Change
10
10
WRITE CYCLE
13 tWC
Write Cycle Time
55
70
14 tCW
Chip Selection to End of Write
50
60
15 tAW
Address Valid to End of Write
50
60
16 tBW
/LB, /UB Valid to End of Write
50
60
17 tAS
Address Set-up Time
0
0
18 tWP
Write Pulse Width
45
50
19 tWR
Write Recovery Time
0
0
20 tWHZ
Write to Output in High Z
0
20
0
20
21 tDW
Data to Write Time Overlap
25
30
22 tDH
Data Hold from Write Time
0
0
23 tOW
Output Active from End of Write
5
5
-
-85
Min
Max.
Unit
85
10
5
10
0
0
0
10
85
85
40
85
30
30
30
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
70
70
70
0
60
0
0
35
0
5
25
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
TA = 0°C to 70°C / -40°C to 85°C, unless otherwise specified
PARAMETER
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Level
tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
Output Load
Other
Value
0.4V to 2.2V
5ns
1.5V
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
VTM
= 2.8V
1029 Ohm
DOUT
CL(1)
1728 Ohm
Note
1. Including jig and scope capacitance
Rev.01/Mar. 2002
4
HY62UF16806B
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
tAA
tOH
tACS
/CS1
CS2
tCHZ(3)
tBA
/UB ,/ LB
tBHZ(3)
tOE
/OE
Data
Out
High-Z
tCLZ(3)
tOLZ(3)
tBLZ(3)
tOHZ(3)
Data Valid
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS1
/UB, /LB
CS2
tACS
tCLZ(3)
Data
Out
tCHZ(3)
Data Valid
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and
CS2 are in active status.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active
Rev.01/Mar. 2002
5
HY62UF16806B
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC
ADDR
tWR(2)
tCW
/CS1
CS2
tAW
tBW
/UB,/LB
tWP
/WE
tAS
Data In
tDW
High-Z
tDH
Data Valid
tWHZ(3,7)
tOW
(5)
(6)
Data
Out
WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled)
tWC
ADDR
tAS
tCW
tWR(2)
/CS1
tAW
CS2
tBW
/UB,/LB
tWP
/WE
tDW
Data In
Data
Out
Rev.01/Mar. 2002
High-Z
tDH
Data Valid
High-Z
6
HY62UF16806B
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and a Low /UB and/or /LB.
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the
end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low
transition or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0°C to 70°C / -40°C to 85°C
Symbol
Parameter
VDR
Vcc for Data Retention
Iccdr
Data Retention Current
tCDR
tR
Chip Deselect to Data
Retention Time
Operating Recovery Time
Test Condition
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V,
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
Vcc=1.5V,
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
LL
Min
1.2
Typ1.
-
Max
3.3
Unit
V
-
1.0
6
uA
0
-
-
ns
tRC
-
-
ns
See Data Retention Timing Diagram
Notes:
1. Typical values are under the condition of TA = 25°C .
2. tRC is read cycle time.
Rev.01/Mar. 2002
7
HY62UF16806B
DATA RETENTION TIMING DIAGRAM 1
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
VIH
VDR
CS1>VCC-0.2V
/CS1
VSS
DATA RETENTION TIMING DIAGRAM 2
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
CS2
VDR
0.4V
VSS
Rev.01/Mar. 2002
CS2<0.2V
8
HY62UF16806B
PACKAGE INFORMATION
48ball Fine Pitch Ball Grid Array Package (F)
BOTTOM VIEW
TOP VIEW
B
A
A1 CORNER
INDEX AREA
6
5
4
3
2
1
A
A
B
C
D
C
C1
E
F
G
C1/2
H
B1/2
B1
SIDE VIEW
5
E1
E2
C
E
SEATING PLANE
A
4
r
3 D(DIAMETER)
Note
Symbol
A
B
B1
C
C1
D
E
E1
E2
r
Rev.01/Mar. 2002
Min.
5.9
8.4
0.3
0.9
0.20
-
Typ.
0.75
3.75
6.0
5.25
8.5
0.35
1.0
0.76
0.25
-
Max.
6.1
8.6
0.4
1.10
0.30
0.08
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
5. THIS IS A CONTROLLING DIMENSION.
9
HY62UF16806B
MARKING INSTRUCTION
Package
fBGA
Marking Example
H
Y
U
F
c
s
s
t
x
x
x
x
6
8
0
6
B
y
w
w
p
K
O
R
x
Index
• HYUF6806B
: Part Name
• c
: Power Consumption
-D
• ss
: Low Low Power
: Speed
- 55
- 70
- 85
: 55ns
: 70ns
: 85ns
• t
: Temperature
-C
-I
• y
: Year (ex : 0 = year 2000, 1= year2001)
• ww
: Work Week ( ex : 12 = work week 12)
• p
: Process Code
• xxxxx
: Lot No.
• KOR
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Rev.01/Mar. 2002
: Commercial ( 0 ~ 70 °C)
: Industrial ( -40 ~ 85 °C )
10
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