doc0498_Atmel_AT89_Memory_org

doc0498_Atmel_AT89_Memory_org

The information presented in this chapter is collected from the Microcontroller Architectural Overview, AT89C51, AT89LV51, AT89C52, AT89LV52, AT89C2051, and

AT89C1051 data sheets of this book. The material has been selected and rearranged to form a quick and convenient reference for the programmers of Atmel’s microcontroller family of devices. This guide pertains specifically to the AT89C51, AT89LV51,

AT89C52, and AT89LV52.

Memory Organization

Program Memory

The AT89C Microcontroller has separate address spaces for program memory and data memory. The program memory can be up to 64K bytes long. The lower addresses may reside on-chip.

Figure 1 shows a map of the AT89C51 program memory, and Figure 2 shows a map of the AT89C52 program memory. The AT89C1051/2051 do not have off-board memory expansion.

Figure 1. AT89C51 Program Memory

Flash

Microcontroller

Memory

Organization

Figure 2. AT89C52 Program Memory

0498B-B–12/97

2-21

Data Memory

The AT89C can directly address up to 64K bytes of data memory external to the chip. The MOVX instruction accesses the external data memory. (Refer to the Instruction Set section in this chapter for a detailed description of instructions).

Figure 3. A: The AT89C51 Data Memory

The AT89C51 has 128 bytes of on-chip RAM (256 bytes in the AT89C52) plus a number of Special Function Registers

(SFRs). The lower 128 bytes of RAM can be accessed either by direct addressing (MOV data addr) or by indirect addressing (MOV @Ri). Figure 3 shows the AT89C51 and the AT89C52 data memory organization.

Figure 3. B: The AT89C52 Data Memory

2-22

Memory Organization

Memory Organization

Indirect Address Area

In Figure 3b, the SFRs and the indirect address RAM have the same addresses (80H through 0FFH). Nevertheless, they are two separate areas and are accessed in two different ways.

For example, the following instruction writes 0AAH to Port

0, which is one of the SFRs.

MOV 80H, # 0AAH

The following instruction writes 0BBH in location 80H of the data RAM.

MOVR0, # 80H

[email protected] R0, # 0BBH

Thus, after executing both of these instructions, Port 0 contains 0AAH, and location 80H of the RAM contains 0BBH.

The stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space in devices that implement 256 bytes of internal RAM.

Direct and Indirect Address Area

The 128 bytes of RAM that can be accessed by both direct and indirect addressing can be divided into 3 segments as described in this section and as shown in Figure 4.

1. Register Banks 0-3: Locations 0 through 1FH (32

bytes). Reset default is to register bank 0. To use the other

Figure 4. 128 Bytes of Directly and Indirectly Addressable RAM

register banks, the user must select them in the software.

Each register bank contains eight 1-byte registers, 0 through 7.

Reset initializes the Stack Pointer to location 07H. The

Stack Pointer is then incremented once to start from location 08H, which is the first register (R0) of the second register bank. Thus, in order to use more than one register bank, the SP should be initialized to a different location of the

RAM that is not used for data storage (that is, a higher part of the RAM).

2. Bit Addressable Area: 16 bytes have been assigned for

this segment, 20H through 2FH. Each of the 128 bits of this segment can be directly addressed (0 through 7FH).

These bits can be referred to in two ways. One way is to refer to their addresses, that is, 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0 through 7 can also be referred to as bits 20.0 through 20.7, and bits 8 through FH are the same as 21.0 through 21.7, and so on.

E a c h o f t h e 1 6 b y t e s i n t h i s s e g m e n t c a n a l s o b e addressed as a byte.

3. Scratch Pad Area: Bytes 30H through 7FH are available

to the user as data RAM. However, if the stack pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction.

8 Bytes

58

50

48

40

38

30

28

20

18

10

08

00

78

70

68

60

0 . . .

1

0

3

2

. . . 7F

5F

57

4F

47

3F

7F

77

6F

67

SCRATCH

PAD

AREA

17

0F

07

37

2F

27

BIT

ADDRESSABLE

SEGMENT

1F

REGISTER

BANKS

2-23

Special Function Registers

Table 1 contains a list of all the SFRs and their addresses.

All of the SFRs that are byte- and bit-addressable are located on the first column of the diagram in Figure 5.

Table 1. Special Function Registers

Name Symbol

ACC

(1)

B

(1)

Accumulator

B Register

PSW

(1)

Program Status Word

SP Stack Pointer

DPTR

DPL

P0

(1)

DPH

P1

(1)

P2

(1)

P3

(1)

IP

(1)

IE

(1)

TMOD

TCON

(1)

T2CON

(1)(2)

T2MOD

(2)

TH0

TL0

TH1

TL1

TH2

(2)

TL2

(2)

RCAP2H

(2)

RCAP2L

(2)

SCON

(1)

SBUF

PCON

Notes: 1. Bit addressable

2. AT89C52 only

Data Pointer 2 Bytes

Low Byte

High Byte

Port 0

Port 1

Port 2

Port 3

Interrupt Priority Control

Interrupt Enable Control

Timer/Counter Mode Control

Timer/Counter Control

Timer/Counter 2 Control

Timer/Counter 2 Mode Control

Timer/Counter 0 High Byte

Timer/Counter 0 Low Byte

Timer/Counter 1 High Byte

Timer/Counter 1 Low Byte

Timer/Counter 2 High Byte

Timer/Counter 2 Low Byte

T/C 2 Capture Reg. High Byte

T/C 2 Capture Reg. Low Byte

Serial Control

Serial Data Buffer

Power Control

Address

0E0H

0F0H

0D0H

81H

0A8H

89H

88H

0C8H

0C9H

8CH

8AH

8DH

82H

83H

80H

90H

0A0H

0B0H

0B8H

8BH

0CDH

0CCH

0CBH

0CAH

98H

99H

87H

2-24

Memory Organization

Memory Organization

Contents of the SFRs Just After Power-On or a Reset

Table 2. Contents of the SFRs after power-on or a hardware reset

Register Value in Binary

ACC

(2)

00000000

B

(2)

PSW

(2)

00000000

00000000

00000111 SP

DPTR

DPH

PO

(2)

P1

(2)

P2

(2)

P3

(2)

IP

(2)

DPL

IE

(2)

TMOD

T2MOD

(3)

TCON

(2)

T2CON

(2)(3)

TH0

TL0

TH1

TL1

TH2

(3)

TL2

(3)

RCAP2H

(3)

RRAP2L

(3)

SCON

(2)

SBUF

PCON

Notes: 1. X = Undefined

2. Bit Addressable

3. AT89C52 only

00000000

00000000

11111111

11111111

11111111

11111111

80C51 XXX00000,

80C52 XX000000

80C51 0XX00000,

80C52 0X000000

00000000

XXXXXX00

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

Indeterminate

CMOS 0XXX0000

2-25

Special Function Register Map

Figure 5. SFR Memory Map

8 Bytes

A0

98

90

88

80

C0

B8

B0

A8

E0

D8

D0

C8

F8

F0

E8

B

ACC

PSW

T2CON

(1)

(1)(2)

T2MOD

(2)

RCAP2L

IP

(1)

P3

IE

(1)

P2

SCON

(1)

SBUF

P1

TCON

(1)

TMOD

(1)

P0 SP

Bit Addressable

TL0

DPL

Notes: 1. SFRs converting mode or control bits

2. AT89C52 only

(2)

RCAP2H

(2)

TL1

DPH

TL2

(2)

TH0

TH2

(2)

TH1

PCON

(1)

A7

9F

97

8F

87

C7

BF

B7

AF

E7

DF

D7

CF

FF

F7

EF

2-26

Memory Organization

Memory Organization

SFRs whose bits are assigned for various functions are listed in this section. For more detailed information, refer to the Microcontroller Architectural Overview chapter of this book.

PSW: Program Status Word (Bit Addressable)

CY AC F0 RS1 RS0 OV — P

CY

AC

F0

RS1

RS0

OV

PSW.7

PSW.6

PSW.5

PSW.4

PSW.3

PSW.2

Carry flag.

Auxiliary carry flag.

Flag 0 available to the user for general purpose.

Register Bank selector bit 1.

(1)

Register Bank selector bit 0.

(1)

Overflow flag.

— PSW.1

User definable flag.

P PSW.0

Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of 1 bits in the accumulator.

Note: 1. The values of RS0 and RS1 select the corresponding register bank.

RS1

0

0

1

1

RS0

0

1

0

1

Register Bank

0

1

2

3

Address

00H-07H

08H-0FH

10H-17H

18H-1FH

PCON: Power Control Register (Not Bit Addressable)

SMOD — — — GF1

SMOD

GF1

GF0 PD IDL

Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD = 1, the baud rate is doubled when the

Serial Port is used in modes 1, 2, or 3.

Not implemented, reserved for future use.

(1)

Not implemented, reserved for future use.

(1)

Not implemented, reserved for future use.

(1)

General purpose flag bit.

GF0

PD

IDL

General purpose flag bit.

Power Down bit. Setting this bit activates Power Down operation in the AT89C51.

Idle Mode bit. Setting this bit activates Idle Mode operation in the AT89C51.

If 1s are written to PD and IDL at the same time, PD takes precedence.

Note: 1. User software should not write 1s to reserved bits. These bits may be used in future microcontrollers to invoke new features.

In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.

2-27

Interrupts

In order to use any of the interrupts in the Flash microcontroller, take the following three steps.

1.

Set the EA (enable all) bit in the IE register to 1.

2.

Set the corresponding individual interrupt enable bit in the IE register to 1.

3.

Begin the interrupt service routine at the corresponding

Vector Address of that interrupt. See the following table.

Interrupt Source

IE0

TF0

IE1

Vector Address

0003H

000BH

0013H

TF1 001BH

R1 & T1 0023H

TF2 & EXF2

(1)

002BH

Note: 1. AT89C52 only.

In addition, for external interrupts, pins INT0 and INT1

(P3.2 and P3.3) must be set to 1, and depending on whether the interrupt is to be level or transition activated, bits IT0 or IT1 in the TCON register may need to be set to

1.

ITx = 0 level activated

ITx = 1 transition activated

IE: Interrupt Enable Register (Bit Addressable)

If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled.

EA

EA IE.7

IE.6

IE.5

IE.4

— ET2 ES ET1 EX1 ET0 EX0

Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.

Not implemented, reserved for future use.

(1)

ET2

ES

ET1

EX1

IE.3

IE.2

Enables or disables the Timer 2 overflow or capture interrupt (AT89C52 only).

Enables or disables the serial port interrupt.

Enables or disables the Timer 1 overflow interrupt.

Enables or disables External Interrupt 1.

ET0 IE. 1 Enables or disables the Timer 0 overflow interrupt.

EX0 IE.0

Enables or disables External Interrupt 0.

Note: 1. User software should not write 1s to reserved bits. These bits may be used in future Flash microcontrollers to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.

2-28

Memory Organization

Memory Organization

Assigning Higher Priority to

One or More Interrupts

In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1.

While an interrupt service is in progress, it cannot be interrupted by an interrupt of the same or lower priority.

Priority Within Level

The only purpose of priority within a level is to resolve simultaneous requests of the same priority level.

From high to low, interrupt sources are listed below.

IE0

TF0

IE1

TF1

RI or TI

TF2 or EXF2

IP: Interrupt Priority Register

(Bit Addressable)

If the bit is 0, the corresponding interrupt has a lower priority. If the bit is 1, the corresponding interrupt has a higher priority

PT2

PS

PT1

PX1

IP. 7

IP. 6

IP. 5

IP. 4

IP. 3

IP. 2

— PT2 PS PT1

Not implemented, reserved for future use.

(1)

Not implemented, reserved for future use.

(1)

PX1

Defines the Timer 2 interrupt priority level (AT89C52 only).

Defines the Serial Port interrupt priority level.

Defines the Timer 1 interrupt priority level.

Defines External Interrupt 1 priority level.

PT0 PX0

PT0 IP. 1 Defines the Timer 0 interrupt priority level.

PX0 IP. 0 Defines the External Interrupt 0 priority level.

Note: 1. User software should not write 1s to reserved bits. These bits may be used in future Flash microcontrollers to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.

2-29

TCON: Timer/Counter Control Register (Bit Addressable)

TF1

TF1

TR1

TR1

TCON. 7

TCON. 6

TF0 TR0 IE1 IT1 IE0 IT0

Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows. Cleared by hardware as the processor vectors to the interrupt service routine.

Timer 1 run control bit. Set/cleared by software to turn Timer/Counter 1 ON/OFF.

TF0 TCON. 5

TR0

IE1

IT1

IE0

IT0

TCON. 4

TCON. 3

TCON. 2

TCON. 1

TCON. 0

Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as the processor vectors to the service routine.

Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF.

External Interrupt 1 edge flag. Set by hardware when the External Interrupt edge is detected.

Cleared by hardware when the interrupt is processed.

Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered

External Interrupt.

External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared by hardware when interrupt is processed.

Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered

External Interrupt.

TMOD: Timer/Counter Mode Control Register (Not Bit Addressable)

Timer 1 Timer 0

GATE

GATE

C/T

M1

M0

Note: 1.

C/T M1 M0 GATE C/T M1 M0

When TRx (in TCON) is set and GATE = 1, TIMER/COUNTERx runs only while the INTx pin is high (hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = 1 (software control).

Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation

(input from Tx input pin).

Mode selector bit.

(1)

Mode selector bit.

(1)

M1

0

0

1

1

1

M0

0

1

0

1

1

Operating Mode

0

1

2

3

3

13-bit Timer

16-bit Timer/Counter

8-bit Auto-Reload Timer/Counter

Split Timer Mode: (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits, TH0 is an 8-bit Timer and is controlled by Timer 1 control bits.

(Timer 1) Timer/Counter 1 stopped.

2-30

Memory Organization

Memory Organization

Timer Set-Up

Tables 3 through 6 give TMOD values that can be used to set up Timer 0 in different modes.

It is assumed that only one timer is used at a time. If Timers

0 and 1 must run simultaneously in any mode, the value in

TMOD for Timer 0 must be ORed with the value shown for

Timer 1 (Tables 5 and 6).

For example, if Timer 0 must run in mode 1 GATE (external control), and Timer 1 must run in mode 2 COUNTER, then the value that must be loaded into TMOD is 69H (09H from

Table 3 ORed with 60H from Table 6).

Moreover, it is assumed that the user is not ready at this point to turn the timers on and will do so at another point in the program by setting bit TRx (in TCON) to 1.

Timer/Counter 0

Table 3. Timer/Counter 0 Used as a Timer

MODE TIMER 0

FUNCTION

TMOD

INTERNAL

CONTROL

(1)

EXTERNAL

CONTROL

(2)

2

3

0

1

13-bit Timer

16-bit Timer

8-bit Auto-Reload two 8-bit Timers

00H

01H

02H

03H

08H

09H

0AH

0BH

Timer/Counter 1

Table 5. Timer/Counter 1 Used as a Timer

MODE TIMER 1

FUNCTION

TMOD

INTERNAL

CONTROL

(1)

EXTERNAL

CONTROL

(2)

0

1

2

3

13-bit Timer

16-bit Timer

8-bit Auto-Reload does not run

00H

10H

20H

30H

80H

90H

A0H

B0H

Table 6. Timer/Counter 1 Used as a Counter

MODE COUNTER 1

FUNCTION

TMOD

INTERNAL

CONTROL

(1)

EXTERNAL

CONTROL

(2)

0

1

13-bit Timer

16-bit Timer

40H

50H

C0H

D0H

2 8-bit Auto-Reload 60H E0H

3 not available — —

Notes: 1. The Timer is turned ON/OFF by setting/clearing bit

TR1 in the software.

2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1 (P3.3) wen TR1 = 1 (hardware control).

Table 4. Timer/Counter 0 Used as a Counter

MODE TIMER 0

FUNCTION

TMOD

INTERNAL

CONTROL

(1)

EXTERNAL

CONTROL

(2)

0

1

13-bit Timer

16-bit Timer

04H

05H

0CH

0DH

2 8-bit Auto-Reload 06H 0EH

3 one 8-bit Counter 07H 0FH

Notes: 1. The Timer is turned ON/OFF by setting/clearing bit

TR0 in the software.

2. The Timer is turned ON/OFF by the 1 to 0 transition on INT0 (P3.2) when TR0 = 1 (hardware control).

2-31

T2CON: Timer/Counter 2 Control Register (Bit Addressable)

AT89C52 Only

TF2

TF2

EXF2

RCLK

TLCK

EXEN2

TR2

C/T2

CP/RL2

EXF2

T2CON. 7

T2CON. 6

T2CON. 5

T2CON. 4

T2CON. 3

T2CON. 2

T2CON. 1

T2CON. 0

RCLK TCLK EXEN2 TR2 C/T2 CP/RL2

Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when either

RCLK = 1 or CLK = 1

Timer 2 external flag set when either a capture or reload is caused by a negative transition on

T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 causes the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.

Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of negative transition on T2EX if Timer 2 is not being used to clock the Serial Port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

Software START/STOP control for Timer 2. A logic 1 starts the Timer.

Timer or Counter select. 0 = Internal Timer. 1 = External Event Counter (triggered by falling edge).

Capture/Reload flag. When set, captures occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads occur either with Timer 2 overflows or negative transitions at T2EX when

EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the Timer is forced to autoreload on Timer 2 overflow.

T2MOD: Timer 2 Mode Control Register

T2MOD Address = 0C9H

Not Bit Addressable

-

Bit 7

-

6

-

5

-

4

Reset Value = XXXX XX00B

-

3

-

2

T2OE

1

DCEN

0

Symbol

-

T2OE

DCEN

Function

Not implemented, reserved for future use

Timer 2 Output Enable bit

When set, this bit allows Timer 2 to be configured as an up/down counter.

2-32

Memory Organization

Timer/Counter 2 Set-Up

Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set separately to turn the Timer on.

Table 7. Timer/Counter 2 Used as a Timer

MODE T2CON

16-bit Auto-Reload

16-bit Capture

Baud rate generator receive and transmit same baud rate receive only transmit only

INTERNAL

CONTROL

(1)

00H

01H

34H

24H

14H

EXTERNAL

CONTROL

(2)

08H

09H

36H

26H

16H

Table 8. Timer/Counter 2 Used as a Counter

MODE TMOD

INTERNAL

CONTROL

(1)

EXTERNAL

CONTROL

(2)

16-bit Auto Reload 02H 0AH

16-bit Capture 03H 0BH

Notes: 1. Capture/Reload occurs only on Timer/Counter overflow.

2. Capture/Reload occurs on Timer/Counter overflow and a 1 to 0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generating mode.

Memory Organization

2-33

SCON: Serial Port Control Register (Bit Addressable)

SM0

SM0

SM1

SM2

SM1

SCON. 7

SCON. 6

SCON. 5

SM2 REN

Serial Port mode specifier.

(1)

Serial Port mode specifier.

(1)

TB8 RB8 TI RI

Enables the multiprocessor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI is not activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI is not activated if a valid stop bit was not received. In mode 0, SM2 should be 0. (See Table 9).

REN

TB8

RB8

TI

RI

SCON. 4

SCON. 3

SCON. 2

SCON. 1

SCON. 0

Set/Cleared by software to Enable/Disable reception.

The 9th bit that is transmitted in modes 2 and 3. Set/Cleared by software.

In modes 2 and 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used.

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Must be cleared by software.

Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0 or halfway through the stop bit time in the other modes (except see SM2). Must be cleared by software.

Note: 1.

SM0

0

0

1

1

SM1

0

1

0

1

Mode

0

1

2

3

Description

SHIFT REGISTER

8-Bit UART

9-Bit UART

9-Bit UART

Baud Rate

Fosc./12

Variable

Fosc./64 OR Fosc./32

Variable

Table 9. Serial Port Set-Up

MODE SCON

2

3

0

1

2

3

0

1

10H

50H

90H

D0H

NA

70H

B0H

F0H

SM2 VARIATION

Single Processor

Environment

(SM2 = 0)

Multiprocessor

Environment

(SM2 = 1)

2-34

Memory Organization

Memory Organization

Generating Baud Rates

Serial Port in Mode 0

Mode 0 has a fixed baud rate, which is 1/12 of the oscillator frequency. To run the serial port in this mode, none of the

Timer/Counters need to be set up. Only the SCON register needs to be defined.

Baud Rate =

12

Serial Port in Mode 1

Mode 1 has a variable baud rate. The baud rate can be generated by either Timer 1 or Timer 2 (AT89C52 only).

Using Timer/Counter 1 to

Generate Baud Rates

For this purpose, Timer l is used in mode 2 (Auto-Reload).

Refer to the Timer Setup section of this chapter.

Baud Rate

=

K

×

Oscillator Frequency

32

×

12

× [

256

(

TH1

]

If SMOD = 0, then K = 1.

If SMOD = 1, then K = 2. (SMOD is the PCON register).

The user usually knows the baud rate but needs to know the reload value for TH1. Therefore, the equation to calculate TH1 can be written as follows.

TH1

=

256

– -----------------------------------------------------------------

384

×

Baud Rate

TH1 must be an integer value. Rounding off TH1 to the nearest integer may not produce the desired baud rate. In this case, the user may have to choose another crystal frequency. See Baud Rate table.

Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register (that is, ORL

PCON, # 80H). The address of PCON is 87H.

Using Timer/Counter 2 to Generate Baud

Rates

For this purpose, Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this chapter. If Timer 2 is clocked through pin T2 (P1.0) the baud rate given by the following equation.

Baud Rate =

16

If it is being clocked internally the baud rate is given by the following equation.

Baud Rate =

32

× [

Oscillator Frequency

65536

(

RCAP2H,RCAP2L

]

To obtain the reload value for RCAP2H and RCAP2L the previous equation can be rewritten as follows.

RCAP2H,RCAP2L

=

65536

– -------------------------------------------------------

32

×

Baud Rate

Serial Port in Mode 2

The baud rate is fixed in this mode and is 1/32 or 1/64 of the oscillator frequency, depending on the value of the

SMOD bit in the PCON register.

In this mode, none of the Timers is used, and the clock comes from the internal phase 2 clock.

SMOD = 1, Baud Rate = 1/32 Osc Freq.

SMOD = O, Baud Rate = 1/64 Osc Freq.

To set the SMOD bit, use ORL PCON, # 80H. The address of PCON is 87H.

Serial Port in Mode 3

The baud rate in mode 3 is variable and sets up exactly the same as in mode 1.

2-35

Baud Rate Table

Crystal Frequency

TH1

E0

F0

F8

F9

FA

FF

7.3728 MHz

600

1,200

2,400

2,743

3,200

19,200

8.00 MHz

651

1,302

2,604

2,976

3,472

20,833

11.0592 MHz 12.00 MHz

900

1,800

3,600

8,299

9,600

57,600

976

1,953

3,906

4,464

5,208

62,500

14.75156 MHz 16.00 MHz

1,200

2,400

4,800

5,486

6,400

1,302

2,604

5,208

5,952

6,944

41,666

Table 10. Baud Rate Summary

Baud Rate

9600

2400

1200

9200

9600

2400

1200

Crystal Frequency

12.000 MHz

12.000 MHz

12.000 MHz

11.059 MHz

11.059 MHz

11.059 MHz

11.059 MHz

0

0

1

0

SMOD

1

0

0

TH1 Reload Value

-7 (F9H)

-13 (F3H)

-26 (E6H)

-3 (FDH)

-3 (FDH)

-12 (F4H)

-24 (E8H)

Actual Baud Rate

8923

2404

1202

19200

9600

2400

1200

Error

7%

0.16%

0.16%

0

0

0

0

Note: Due to rounding, there is a slight error in the resulting baud rate. Generally, a 5% error is tolerable using asynchronous

(start/stop) communications. Exact baud rates are possible using an 11.059 MHz crystal. The table above summarizes the TH1 reload values for the most common baud rates, using a 12.000 MHz or 11.059 MHz crystal.

2-36

Memory Organization

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