datasheet for ADSP-21160N by Analog Devices Inc.

datasheet for ADSP-21160N by Analog Devices Inc.

SUMMARY

High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and communication

Super Harvard architecture—4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O

Backward compatible—assembly source level compatible with code for ADSP-2106x DSPs

Single-instruction, multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file

Integrated peripherals—integrated I/O processor, 4M bits on-chip dual-ported SRAM, glueless multiprocessing features, and ports (serial, link, external bus, and JTAG)

SHARC

Digital Signal Processor

ADSP-21160M/ADSP-21160N

FEATURES

100 MHz (10 ns) core instruction rate (ADSP-21160N)

Single-cycle instruction execution, including SIMD operations in both computational units

Dual data address generators (DAGs) with modulo and bitreverse addressing

Zero-overhead looping and single-cycle loop setup, providing efficient program sequencing

IEEE 1149.1 JTAG standard Test Access Port and on-chip emulation

400-ball 27 mm

× 27 mm PBGA package

Available in lead-free (RoHS compliant) package

200 million fixed-point MACs sustained performance

(ADSP-21160N)

CORE PROCESSOR

TIMER

INSTRUCTION

CACHE

32 x 48-BIT

DUAL-PORTED SRAM

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT

ADDR DATA

ADDR DATA

DATA

I/O PORT

DATA

ADDR

ADDR

JTAG

TEST AND

EMULATION

6

DAG1

8 x 4 x 32

DAG2

8 x 4 x 32

PROGRAM

SEQUENCER

PM ADDRESS BUS

32

DM ADDRESS BUS

32

BUS

CONNECT

(PX)

PM DATA BUS

DM DATA BUS

16/32/40/48/64

32/40/64

IOD

64

IOA

18

EXTERNAL

PORT

ADDR BUS

MUX

MULTIPROCESSOR

INTERFACE

32

64

DATA BUS

MUX

HOST PORT

MULT

DATA

REGISTER

FILE

(PEX)

16 x 40-BIT

BARREL

SHIFTER

ALU

BARREL

SHIFTER

DATA

REGISTER

FILE

(PEY)

16 x 40-BIT

MULT

ALU

IOP

REGISTERS

(MEMORY

MAPPED)

DMA

CONTROLLER

SERIAL PORTS

(2)

CONTROL,

STATUS AND

DATA BUFFERS

LINK PORTS

(6)

I/O PROCESSOR

4

6

6

60

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

©2010 Analog Devices, Inc. All rights reserved.

ADSP-21160M/ADSP-21160N

Single-instruction, multiple-data (SIMD) architecture provides

Two computational processing elements

Concurrent execution—each processing element executes the same instruction, but operates on different data

Code compatibility—at assembly level, uses the same instruction set as the ADSP-2106x SHARC DSPs

Parallelism in buses and computational units allows

Single-cycle execution (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch

Transfers between memory and core at up to four

32-bit floating- or fixed-point words per cycle

Accelerated FFT butterfly computation through a multiply with add and subtract

Memory attributes

4M bits on-chip dual-ported SRAM for independent access by core processor, host, and DMA

4G word address range for off-chip memory

Memory interface supports programmable wait state generation and page-mode for off-chip memory

DMA controller supports

14 zero-overhead DMA channels for transfers between

ADSP-21160x internal memory and external memory, external peripherals, host processor, serial ports, or link ports

64-bit background DMA transfers at core clock speed, in parallel with full-speed processor execution

Host processor interface to 16- and 32-bit microprocessors

Multiprocessing support provides

Glueless connection for scalable DSP multiprocessing architecture

Distributed on-chip bus arbitration for parallel bus connect of up to 6 ADSP-21160x processors plus host

6 link ports for point-to-point connectivity and array multiprocessing

Serial ports provide

Two synchronous serial ports with companding hardware

Independent transmit and receive functions

TDM support for T1 and E1 interfaces

64-bit-wide synchronous external port provides

Glueless connection to asynchronous and SBSRAM external memories

Rev. B | Page 2 of 60 | February 2010

ADSP-21160M/ADSP-21160N

TABLE OF CONTENTS

Summary ............................................................... 1

Features ................................................................. 1

Table of Contents .................................................... 3

Revision History ...................................................... 3

General Description ................................................. 4

ADSP-21160x Family Core Architecture .................... 4

Memory and I/O Interface Features ........................... 5

Development Tools ............................................... 8

Designing an Emulator-Compatible DSP Board (Target) 10

Additional Information ......................................... 10

Pin Function Descriptions ........................................ 11

Specifications ......................................................... 15

Operating Conditions—ADSP-21160M .................... 15

Electrical Characteristics—ADSP-21160M ................. 16

Operating Conditions—ADSP-21160N ..................... 17

REVISION HISTORY

2/10—Rev. A to Rev. B

Corrected pin assignments in last 15 rows of

Table 40

(

400-Ball PBGA Pin Assignments ) ...............................

52

Electrical Characteristics—ADSP-21160N ................. 18

Absolute Maximum Ratings ................................... 19

ESD Sensitivity ................................................... 19

Package Information ............................................ 19

Timing Specifications ........................................... 20

Output Drive Currents—ADSP-21160M ................... 47

Output Drive Currents—ADSP-21160N ................... 47

Power Dissipation ............................................... 47

Test Conditions .................................................. 48

Environmental Conditions .................................... 51

400-Ball PBGA Pin Configurations ............................. 52

Outline Dimensions ................................................ 57

Surface-Mount Design ............................................. 57

Ordering Guide ..................................................... 58

Rev. B | Page 3 of 60 | February 2010

ADSP-21160M/ADSP-21160N

GENERAL DESCRIPTION

The ADSP-21160x SHARC

®

DSP family has two members:

ADSP-21160M and ADSP-21160N. The ADSP-21160M is fabricated in a 0.25 micron CMOS process. The ADSP-21160N is fabricated in a 0.18 micron CMOS process. The ADSP-21160N offers higher performance and lower power consumption than the ADSP-21160M. Easing portability, the ADSP-21160x is application source code compatible with first generation

ADSP-2106x SHARC DSPs in SISD (single instruction, single data) mode. To take advantage of the processor’s SIMD (singleinstruction, multiple-data) capability, some code changes are needed. Like other SHARC DSPs, the ADSP-21160x is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160x includes a core running up to

100 MHz, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.

Table 1 shows major differences between the ADSP-21160M

and ADSP-21160N processors.

Table 1. ADSP-21160x SHARC Processor Family Features

Feature

SRAM

Operating Voltage

ADSP-21160M ADSP-21160N

4 Mbits 4 Mbits

3.3 V I/O

2.5 V Core

3.3 V I/O

1.9 V Core

Instruction Rate 80 MHz

Link Port Transfer Rate (6) 80 MBytes/s

Serial Port Transfer Rate (2) 40 Mbits/s

100 MHz

100 MBytes/s

50 Mbits/s

The ADSP-21160x introduces single-instruction, multiple-data

(SIMD) processing. Using two computational units

(ADSP-2106x SHARC DSPs have one), the ADSP-21160x can double performance versus the ADSP-2106x on a range of DSP algorithms.

Fabricated in a state-of-the-art, high speed, low power CMOS process, the ADSP-21160N has a 10 ns instruction cycle time.

With its SIMD computational hardware running at 100 MHz, the ADSP-21160N can perform 600 million math operations per second (480 million operations for ADSP-21160M at a

12.5 ns instruction cycle time).

Table 2 shows performance benchmarks for the ADSP-21160x.

These benchmarks provide single-channel extrapolations of measured dual-channel (SIMD) processing performance. For more information on benchmarking and optimizing DSP code for single- and dual-channel processing, see the Analog Devices website (www.analog.com).

The ADSP-21160x continues the SHARC family’s industryleading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include a 4M-bit dual-ported SRAM memory, host processor interface, I/O processor that supports

14 DMA channels, two serial ports, six link ports, external parallel bus, and glueless multiprocessing.

Table 2. ADSP-21160x Benchmarks

Benchmark Algorithm

1024 Point Complex FFT

(Radix 4, with reversal)

FIR Filter (per tap)

IIR Filter (per biquad)

Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1]

Divide (y/x)

Inverse Square Root

DMA Transfer Rate

ADSP-21160M

80 MHz

115 µs

ADSP-21160N

100 MHz

92 µs

6.25 ns

25 ns

56.25 ns

100 ns

37.5 ns

56.25 ns

560M bytes/s

5 ns

20 ns

45 ns

80 ns

30 ns

45 ns

800M bytes/s

The functional block diagram ( Figure 1 on Page 1 ) of the

ADSP-21160x illustrates the following architectural features:

• Two processing elements, each made up of an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core every core processor cycle

• Interval timer

• On-chip SRAM (4M bits)

• External port that supports:

• Interfacing to off-chip memory peripherals

• Glueless multiprocessing support for six

ADSP-21160x SHARC DSPs

• Host port

• DMA controller

• Serial ports and link ports

• JTAG test access port

Figure 2

shows a typical single-processor system. A multiprocessing system appears in

Figure 5 on Page 9

.

ADSP-21160X FAMILY CORE ARCHITECTURE

The ADSP-21160x processor includes the following architectural features of the ADSP-2116x family core. The

ADSP-21160x is code compatible at the assembly level with the

ADSP-2106x and ADSP-21161.

SIMD Computational Engine

The ADSP-21160x contains two computational processing elements that operate as a single-instruction multiple-data (SIMD) engine. The processing elements are referred to as PEX and

PEY, and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

Rev. B | Page 4 of 60 | February 2010

CLOCK

4

LINK

DEVICES

(6 MAX)

(OPTIONAL)

SERIAL

DEVICE

(OPTIONAL)

SERIAL

DEVICE

(OPTIONAL)

3

4

ADSP-21160X

CLKIN

BMS

CLK_CFG3–0

EBOOT

LBOOT

IRQ2–0

CIF

BRST

ADDR31–0

FLAG3–0

TIMEXP

DATA63–0

RDx

LXCLK

LXACK

LXDAT7–0

WRx

ACK

MS3–0

TCLK0

RCLK0

TFS0

RSF0

DT0

DR0

TCLK1

RCLK1

TFS1

RSF1

DT1

DR1

PAGE

SBTS

CLKOUT

DMAR1–2

DMAG1–2

CS

HBR

HBG

REDY

RPBA

ID2–0

BR1–6

RESET

JTAG

PA

6

CS

ADDR

BOOT

EPROM

(OPTIONAL)

DATA

ADDR

DATA

OE

WE

MEMORY/

MAPPED

DEVICES

(OPTIONAL)

ACK

CS

DMA DEVICE

DATA

(OPTIONAL)

ADDR

DATA

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

Figure 2. Single-Processor System enabled, the same instruction is executed in both processing elements, but each processing element operates on different data.

This architecture is efficient at executing math-intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. In SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the

DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform single-cycle instructions. The three units within each processing element are arranged in parallel, maximizing computational throughput.

Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats.

Rev. B | Page 5 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Data Register File

A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2116x enhanced

Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The processor features an enhanced Harvard architecture in which the data memory (DM) bus transfers data, and the program memory (PM) bus transfers both instructions and data

(see the functional block diagram 1

). With the ADSP-21160x

DSP’s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands and an instruction (from the cache), all in a single cycle.

Instruction Cache

The ADSP-21160x includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, providing looped operations, such as digital filter multiply- accumulates and FFT butterfly processing.

Data Address Generators with Hardware Circular Buffers

The ADSP-21160x DSP’s two data address generators (DAGs) are used for indirect addressing and provide for implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the product contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the processor can conditionally execute a multiply, an add, and subtract, in both processing elements, while branching, all in a single instruction.

MEMORY AND I/O INTERFACE FEATURES

Augmenting the ADSP-2116x family core, the ADSP-21160x adds the following architectural features.

ADSP-21160M/ADSP-21160N

Dual-Ported On-Chip Memory

The ADSP-21160x contains four megabits of on-chip SRAM, organized as two blocks of 2M bits each, which can be configured for different combinations of code and data storage

(

Figure 3 ). Each memory block is dual-ported for single-cycle,

independent accesses by the core processor and I/O processor.

The dual-ported memory in combination with three separate on-chip buses allows two data transfers from the core and one from I/O processor, in a single cycle. The ADSP-21160x memory can be configured as a maximum of 128K words of

32-bit data, 256K words of 16-bit data, 85K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits. All of the memory can be accessed as

16-, 32-, 48-, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the DM bus for transfers, and the other block stores instructions and data, using the PM bus for transfers. Using the DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.

Off-Chip Memory and Peripherals Interface

The ADSP-21160x DSP’s external port provides the processor’s interface to off-chip memory and peripherals. The 4G word offchip address space is included in the processor’s unified address space. The separate on-chip buses—for PM addresses, PM data,

DM addresses, DM data, I/O addresses, and I/O data—are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 64-bit data bus. The lower 32 bits of the external data bus connect to even addresses, and the upper 32 bits of the 64 connect to odd addresses. Every access to external memory is based on an address that fetches a

32-bit word, and with the 64-bit bus, two address locations can be accessed at once. When fetching an instruction from external memory, two 32-bit data locations are being accessed (16 bits are unused).

Figure 4 shows the alignment of various accesses to

external memory.

The external port supports asynchronous, synchronous, and synchronous burst accesses. ZBT synchronous burst SRAM can be interfaced gluelessly. Addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM.

The ADSP-21160x provides programmable memory wait states and external memory acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold, and disable time requirements.

DMA Controller

The ADSP-21160x DSP’s on-chip DMA controller allows zerooverhead data transfers without processor intervention. The

DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the

Rev. B | Page 6 of 60 | February 2010

Internal

Memory

Space

IOP Reg’s

Long Word

Normal Word

0x00 0000

0x02 0000

0x04 0000

Short Word

0x08 0000

0x10 0000

Internal

Memory

Space

(ID = 001)

0x20 0000

Internal

Memory

Space

(ID = 010)

0x30 0000

Internal

Memory

Space

(ID = 011)

0x40 0000

Multiprocessor

Memory

Space

Internal

Memory

Space

(ID = 100)

0x50 0000

Internal

Memory

Space

(ID = 101)

Internal

Memory

Space

(ID = 110)

0x60 0000

0x70 0000

Broadcast

Write to

All DSPs

(ID = 111)

0x7F FFFF

Bank 0

0x80 0000

MS

0

Bank 1

Bank 2

Bank 3

Nonbanked

MS

1

MS

2

MS

3

External

Memory

Space

0xFFFF FFFF

Figure 3. Memory Map core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and external memory, external peripherals, or a host processor.

DMA transfers can also occur between the product’s DSP’s internal memory and its serial ports or link ports. External bus packing to 16-, 32-, 48-, or 64-bit words is performed during

DMA transfers. Fourteen channels of DMA are available on the

ADSP-21160x—six via the link ports, four via the serial ports, and four via the processor’s external port (for either host processor, other ADSP-21160x processors, memory or I/O transfers). Programs can be downloaded to the processor using

DMA transfers. Asynchronous off-chip peripherals can control two DMA channels using DMA Request/Grant lines

(DMAR1–2, DMAG1–2). Other DMA features include interrupt generation upon completion of DMA transfers, twodimensional DMA, and DMA chaining for automatic linked

DMA transfers.

DATA63–0

63 55

BYTE 7

47 39 31 23 15 7

BYTE 0

0

RDH/WRH

RDL/WRL

64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS

64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH

64-BIT TRANS. FOR 40-BIT EXT. PRECISION

32-BIT NORMAL WORD (ODD ADDR)

RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:

32-BIT PACKED

32-BIT NORMAL WD. (EVEN ADDR.)

16-BIT PACKED

EPROM

Figure 4. External Data Alignment Options

Multiprocessing

The ADSP-21160x offers powerful features tailored to multiprocessing DSP systems as shown in M. The external port and link ports provide integrated glueless multiprocessing support.

The external port supports a unified address space (see

Figure 3 )

that allows direct interprocessor accesses of each processor’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-21160x processors and a host processor. Master processor changeover incurs only one cycle of overhead. Bus arbitration is selectable as either fixed or rotating priority. Bus lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is 400M bytes/s (ADSP-21160N) over the external port.

Broadcast writes allow simultaneous transmission of data to all

ADSP-21160x DSPs and can be used to implement reflective semaphores.

Six link ports provide for a second method of multiprocessing communications. Each link port can support communications to another ADSP-21160x. Using the links, a large multiprocessor system can be constructed in a 2D or 3D fashion. Systems can use the link ports and cluster multiprocessing concurrently or independently.

Link Ports

The processor features six 8-bit link ports that provide additional I/O capabilities. With the capability of running at

100 MHz rates, each link port can support 100M bytes/s

(ADSP-21160N). Link port I/O is especially useful for point-topoint interprocessor communication in multiprocessing systems. The link ports can operate independently and

Rev. B | Page 7 of 60 | February 2010

ADSP-21160M/ADSP-21160N simultaneously. Link port data is packed into 48- or 32-bit words, and can be directly read by the core processor or DMAtransferred to on-chip memory. Each link port has its own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as transmit or receive.

Serial Ports

The processor features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate up to half the clock rate of the core, providing each with a maximum data rate of 50M bits/s (ADSP-21160N). Independent transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory via a dedicated DMA.

Each of the serial ports offers a TDM multichannel mode. The serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. They offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding. Serial port clocks and frame syncs can be generated internally or externally.

Host Processor Interface

The ADSP-21160x host interface allows easy connection to standard microprocessor buses, both 16- and 32-bit, with little additional hardware required. The host interface is accessed through the ADSP-21160x DSP’s external port and is memorymapped into the unified address space. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor communicates with the ADSP-21160x DSP’s external bus with host bus request (HBR), host bus grant (HBG), ready (REDY), acknowledge (ACK), and chip select (CS) signals. The host can directly read and write the internal memory of the processor, and can access the DMA channel setup and mailbox registers.

Vector interrupt support provides efficient execution of host commands.

The host processor interface can be used in either multiprocessor or uniprocessor systems. For multiprocessor systems, host access to the SHARC requires that address pins ADDR17,

ADDR18, ADDR19, and ADDR20 be driven low. It is not enough to tie these pins to ground through a resistor (for example, 10 kΩ). These pins must be driven low with a strong enough drive strength (10 Ω to 50 Ω) to overcome the SHARC keeper latches present on these pins. If the drive strength provided is not strong enough, data access failures can occur.

For uniprocessor SHARC systems using this host access feature, address pins ADDR17, ADDR18, ADDR19, and ADDR20 may be tied low (for example, through a 10 kΩ ohm resistor), driven low by a buffer/driver, or left floating. Any of these options is sufficient.

Program Booting

The internal memory of the ADSP-21160x can be booted at system power-up from an 8-bit EPROM, a host processor, or through one of the link ports. Selection of the boot source is

ADSP-21160M/ADSP-21160N controlled by the BMS (Boot Memory Select), EBOOT (EPROM

Boot), and LBOOT (Link/Host Boot) pins. 32-bit and 16-bit host processors can be used for booting.

Phase-Locked Loop

The processor uses an on-chip PLL to generate the internal clock for the core. Ratios of 2:1, 3:1, and 4:1 between the core and CLKIN are supported. The CLK_CFG pins are used to select the ratio. The CLKIN rate is the rate at which the synchronous external port operates.

Power Supplies

The processor has separate power supply connections for the internal (V

DDINT

), external (V

DDEXT

), and analog (AV

DD

and

AGND) power supplies. The internal and analog supplies must meet the V

DDINT

and AV

DD

requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same supply.

The PLL filter, Figure 6 , must be added for each ADSP-21160x

in the system. V

DDINT

is the digital core supply. It is recommended that the capacitors be connected directly to AGND using short thick trace. It is recommended that the capacitors be placed as close to AV

DD

and AGND as possible. The connection from AGND to the (digital) ground plane should be made after the capacitors. The use of a thick trace for AGND is reasonable only because the PLL is a relatively low power circuit—it does not apply to any other ADSP-21160x GND connection.

V

DDINT

10

0.1

F

AGND

0.01

F

AV

DD

Figure 6. Analog Power (AV

DD

) Filter Circuit

DEVELOPMENT TOOLS

The ADSP-21160x is supported with a complete set of

CROSSCORE

®†

software and hardware development tools, including Analog Devices emulators and the VisualDSP++

®‡ development environment. The same emulator hardware that supports other ADSP-2116x processors also fully emulates the

ADSP-21160x.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ integrated development and debugging environment (IDDE) lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the Blackfin development tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs

• Maintain a one-to-one correspondence with the tool’s command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

CROSSCORE is a registered trademark of Analog Devices, Inc.

VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. B | Page 8 of 60 | February 2010

ADSP-21160M/ADSP-21160N

ADSP-21160X #6

ADSP-21160X #5

ADSP-21160X #4

ADSP-21160X #3

CLKIN

ADDR31–0

DATA63–0

RESET

RPBA

3

ID2–0

CONTROL

011

PA

BR1–2, BR4–6

BR3

5

ADSP-21160X #2

CLKIN

RESET

ADDR31–0

DATA63–0

RPBA

3

ID2–0

CONTROL

010

PA

BR1, BR3–6

BR2

5

3

001

ADSP-21160X #1

CLKIN

RESET

RPBA

ID2–0

ADDR31–0

DATA63–0

RDx

WRx

ACK

MS3–0

BMS

PAGE

SBTS

BUS

PRIORITY

RESET

CLOCK

CS

HBR

HBG

REDY

PA

BR2–6

BR1

5

ADDR

DATA

OE

WE

ACK

CS

CS

ADDR

DATA

GLOBAL MEMORY

AND

PERIPHERALS

(OPTIONAL)

BOOT EPROM (OPTIO

ADDR

DATA

HOST PROCESSOR

INTERFACE (OPTIONA

Figure 5. Shared Memory Multiprocessing System

Rev. B | Page 9 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command-line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK.

Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with the drag of the mouse, examine run time stack and heap usage. The

Expert Linker is fully compatible with existing Linker Definition

File (LDF), allowing the developer to move between the graphical and textual environments.

Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test

Access Port of the ADSP-21160x processor to monitor and control the target board processor during emulation. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s

JTAG interface—the emulator does not affect target system loading or timing.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the ADSP-2116x processor family.

Hardware tools include ADSP-2116x processor PC plug-in cards. Third-party software tools include DSP libraries, realtime operating systems, and block diagram design tools.

DESIGNING AN EMULATOR-COMPATIBLE DSP

BOARD (TARGET)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG DSP. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single-processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see Analog Devices JTAG Emulation Technical Reference

(EE-68) on the Analog Devices website (ww.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the

ADSP-21160x architecture and functionality. For detailed information on the Blackfin family core architecture and instruction set, refer to the ADSP-21160 SHARC DSP Hardware Reference and the ADSP-21160 SHARC DSP Instruction Set Reference. For detailed information on the development tools for this processor, see the VisualDSP++ User’s Guide.

Rev. B | Page 10 of 60 | February 2010

ADSP-21160M/ADSP-21160N

PIN FUNCTION DESCRIPTIONS

ADSP-21160x pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to

CLKIN (or to TCK for TRST).

Tie or pull unused inputs to V

DD

or GND, except for the following:

• ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT (ID2–0

= 00x) (Note: These pins have a logic-level hold circuit enabled on the ADSP-21160x DSP with ID2–0 = 00x.)

• PA, ACK, MS3–0, RDx, WRx, CIF, DMARx, DMAGx

(ID2–0 = 00x) (Note: These pins have a pull-up enabled on the ADSP-21160x with ID2–0 = 00x.)

• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note: See

Link Port Buffer Control Register Bit definitions in the

ADSP-21160 SHARC DSP Hardware Reference.)

• DTx, DRx, TCLKx, RCLKx, EMU, TMS, TRST, TDI

(Note: These pins have a pull-up.)

The following symbols appear in the Type column of Table 3

:

A = Asynchronous, G = Ground, I = Input, O = Output,

P = Power Supply, S = Synchronous, (A/D) = Active Drive,

(O/D) = Open Drain, and T = Three-State (when SBTS is asserted, or when the ADSP-21160x is a bus slave).

Table 3. Pin Function Descriptions

Pin

ADDR31–0

Type

I/O/T

DATA63–0

MS3–0

RDL

RDH

WRL

WRH

I/O/T

O/T

I/O/T

I/O/T

I/O/T

I/O/T

Function

External Bus Address. The ADSP-21160x outputs addresses for external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes of the internal memory or IOP registers of other ADSP-21160x DSPs. The ADSP-21160x inputs addresses when a host processor or multiprocessing bus master is reading or writing its internal memory or

IOP registers. A keeper latch on the DSP’s ADDR31–0 pins maintains the input at the level it was last driven (only enabled on the processor with ID2–0 = 00x).

External Bus Data. The ADSP-21160x inputs and outputs data and instructions on these pins. Pullup resistors on unused DATA pins are not necessary. A keeper latch on the DSP’s DATA63-0 pins maintains the input at the level it was last driven (only enabled on the processor with ID2–0 = 00x).

Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of external memory. Memory bank size must be defined in the SYSCON control register. The MS3–0 outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert with the other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted. MS3–0 has a 20 kΩ internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.

Memory Read Low Strobe. RDL is asserted whenever ADSP-21160x reads from the low word of external memory or from the internal memory of other ADSP-21160x DSPs. External devices, including other ADSP-21160x DSPs, must assert RDL for reading from the low word of processor internal memory. In a multiprocessing system, RDL is driven by the bus master. RDL has a 20 kΩ internal pull-up resistor that is enabled on the processor with ID2–0 = 00x.

Memory Read High Strobe. RDH is asserted whenever ADSP-21160x reads from the high word of external memory or from the internal memory of other ADSP-21160x DSPs. External devices, including other ADSP-21160x DSPs, must assert RDH for reading from the high word of

ADSP-21160x internal memory. In a multiprocessing system, RDH is driven by the bus master.

RDH has a 20 kΩ internal pull-up resistor that is enabled on the processor with ID2–0 = 00x.

Memory Write Low Strobe. WRL is asserted when ADSP-21160x writes to the low word of external memory or internal memory of other ADSP-21160x DSPs. External devices must assert WRL for writing to ADSP-21160x DSP’s low word of internal memory. In a multiprocessing system, WRL is driven by the bus master. WRL has a 20 kΩ internal pull-up resistor that is enabled on the processor with ID2–0 = 00x.

Memory Write High Strobe. WRH is asserted when ADSP-21160x writes to the high word of external memory or internal memory of other ADSP-21160x DSPs. External devices must assert WRH for writing to ADSP-21160x DSP’s high word of internal memory. In a multiprocessing system, WRH is driven by the bus master. WRH has a 20 kΩ internal pull-up resistor that is enabled on the processor with ID2–0 = 00x.

Rev. B | Page 11 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Table 3. Pin Function Descriptions (Continued)

Pin

PAGE

BRST

ACK

SBTS

IRQ2–0

FLAG3–0

TIMEXP

HBR

HBG

CS

REDY

DMAR1

DMAR2

Type

O/T

I/O/T

I/O/S

I/S

I/A

I/O/A

O

I/A

I/O

I/A

O (O/D)

I/A

I/A

Function

DRAM Page Boundary. The processor asserts this pin to an external DRAM controller, to signal that an external DRAM page boundary has been crossed. DRAM page size must be defined in the processor’s memory control register (WAIT). DRAM can only be implemented in external memory

Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system, PAGE is output by the bus master. A keeper latch on the DSP’s PAGE pin maintains the output at the level it was last driven (only enabled on the processor with ID2–0 = 00x).

Sequential Burst Access. BRST is asserted by ADSP-21160x or a host to indicate that data associated with consecutive addresses is being read or written. A slave device samples the initial address and increments an internal address counter after each transfer. The incremented address is not pipelined on the bus. If the burst access is a read from the host to the processor, the processor automatically increments the address as long as BRST is asserted. BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for the last data request cycle (denoted by RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s

BRST pin maintains the input at the level it was last driven (only enabled on the processor with

ID2–0 = 00x).

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-21160x deasserts ACK as an output to add wait states to a synchronous access of its internal memory, by a synchronous host or another DSP in a multiprocessor configuration. ACK has a 2 kΩ internal pull-up resistor that is enabled on the processor with ID2–0 = 00x.

Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus address, data, selects, and strobes in a high-impedance state for the following cycle. If the

ADSP-21160x attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host processor and/or ADSP-21160x deadlock or used with a DRAM controller.

Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edgetriggered or level-sensitive.

Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals.

Timer Expired. Asserted for four processor core clock (CCLK) cycles when the timer is enabled and

TCOUNT decrements to zero.

Host Bus Request. Must be asserted by a host processor to request control of the

ADSP-21160x DSP’s external bus. When HBR is asserted in a multiprocessing system, the processor that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the processor places the address, data, select, and strobe lines in a high-impedance state. HBR has priority over all processor bus requests (BR6–1) in a multiprocessing system.

Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of the external bus. HBG is asserted (held low) by the ADSP-21160x until HBR is released. In a multiprocessing system, HBG is output by the processor bus master and is monitored by all others.

After HBR is asserted, and before HBG is given, HBG will float for 1 t

CLK

(1 CLKIN cycle). To avoid erroneous grants, HBG should be pulled up with a 20 kΩ to 50 kΩ external resistor.

Chip Select. Asserted by host processor to select the ADSP-21160x, for asynchronous transfer protocol.

Host Bus Acknowledge. The ADSP-21160x deasserts REDY (low) to add wait states to an asynchronous host access when CS and HBR inputs are asserted.

DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services.

DMAR1 has a 20 kΩ internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.

DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services.

DMAR2 has a 20 kΩ internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.

Rev. B | Page 12 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Table 3. Pin Function Descriptions (Continued)

Pin

ID2–0

DMAG1

DMAG2

BR6–1

RPBA

PA

DTx

DRx

TCLKx

RCLKx

TFSx

RFSx

LxDAT7–0

LxCLK

LxACK

EBOOT

LBOOT

BMS

CLKIN

CLK_CFG3–0 I

I

I

I

I

Type

O/T

O/T

I/O/S

I/S

I/O/T

I

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O/T

Function

Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used by the

ADSP-21160x. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system configuration selection which should be hardwired or only changed at reset.

DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160x to indicate that the requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a 20 kΩ internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.

DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160x to indicate that the requested DMA starts on the next cycle. Driven by bus master only. DMAG2 has a 20 kΩ internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.

Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160x DSPs to arbitrate for bus mastership. An ADSP-21160x only drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-21160x DSPs, the unused BRx pins should be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output.

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every ADSP-21160x. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every processor.

Priority Access. Asserting its PA pin allows an ADSP-21160x bus slave to interrupt background DMA transfers and gain access to the external bus. PA is connected to all ADSP-21160x DSPs in the system.

If access priority is not required in a system, the PA pin should be left unconnected. PA has a 20 kΩ internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.

Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.

Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.

Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.

Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.

Transmit Frame Sync (Serial Ports 0, 1).

Receive Frame Sync (Serial Ports 0, 1).

Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.

Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.

EPROM Boot Select. For a description of how this pin operates, see Table 4

. This signal is a system configuration selection that should be hardwired.

Link Boot. For a description of how this pin operates, see

Table 4

. This signal is a system configuration selection that should be hardwired.

Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins; see

Table 4

. This input is a system configuration selection that should be hardwired.

Local Clock In. CLKIN is the ADSP-21160x clock input. The ADSP-21160x external port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up. CLKIN may not be halted, changed, or operated below the specified frequency.

Core/CLKIN Ratio Control. ADSP-21160x core clock (instruction cycle) rate is equal to n x CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs. For clock configuration definitions, see the RESET & CLKIN section of the System Design chapter of the ADSP-21160 SHARC DSP

Hardware Reference .

Rev. B | Page 13 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Table 3. Pin Function Descriptions (Continued)

Pin

CLKOUT

RESET

TCK

TMS

TDI

TDO

TRST

EMU

CIF

V

DDINT

V

DDEXT

AV

DD

AGND

GND

NC

G

G

Type

O/T

I/A

I/S

P

P

I

I/S

O

I/A

O (O/D)

O/T

P

Function

Local Clock Out. CLKOUT is driven at the CLKIN frequency by the processor. This output can be three-stated by setting the COD bit in the SYSCON register. A keeper latch on the DSP’s CLKOUT pin maintains the output at the level it was last driven (only enabled on the processor with

ID2-0 = 00x). Do not use CLKOUT in multiprocessing systems; use CLKIN instead.

Processor Reset. Resets the ADSP-21160x to a known state and begins execution at the program memory location specified by the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

Test Clock (JTAG). Provides a clock for JTAG boundary scan.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after powerup or held low for proper operation of the ADSP-21160x. TRST has a 20 kΩ internal pull-up resistor.

Emulation Status. Must be connected to the ADSP-21160x emulator target board connector only.

EMU has a 50 kΩ internal pull-up resistor.

Core Instruction Fetch. Signal is active low when an external instruction fetch is performed. Driven by bus master only. Three-state when host is bus master. CIF has a 20 kΩ internal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.

Core Power Supply. Nominally 2.5 V (ADSP-21160M) or 1.9 V (ADSP-21160N) dc and supplies the

DSP’s core processor

I/O Power Supply. Nominally 3.3 V dc.

Analog Power Supply. Nominally 2.5 V (ADSP-21160M) or 1.9 V (ADSP-21160N) dc and supplies the

DSP’s internal PLL (clock generator). This pin has the same specifications as V

DDINT

, except that added filtering circuitry is required. For more information, see Power Supplies on page

8 .

Analog Power Supply Return.

Power Supply Return.

Do Not Connect. Reserved pins that must be left open and unconnected.

Table 4. Boot Mode Selection

0

0

1

0

0

EBOOT

1

0

1

1

0

1

LBOOT

0

BMS

Output

1 (Input)

1 (Input)

0 (Input)

0 (Input) x (Input)

Booting Mode

EPROM (Connect BMS to EPROM chip select.)

Host Processor

Link Port

No Booting. Processor executes from external memory.

Reserved

Reserved

Rev. B | Page 14 of 60 | February 2010

ADSP-21160M/ADSP-21160N

SPECIFICATIONS

OPERATING CONDITIONS—ADSP-21160M

Table 5 shows the recommended operating conditions for the

ADSP-21160M. Specifications are subject to change without notice.

Table 5. Operating Conditions—ADSP-21160M

Parameter

V

DDINT

AV

DD

V

DDEXT

T

CASE

V

IH1

V

IH2

V

IL

Internal (Core) Supply Voltage

Analog (PLL) Supply Voltage

External (I/O) Supply Voltage

Case Operating Temperature

1

High Level Input Voltage,

2

@ V

DDEXT

=Max

High Level Input Voltage,

3

@ V

DDEXT

=Max

Low Level Input Voltage

,2, 3

@ V

DDEXT

=Min

K Grade

Min

2.37

2.37

3.13

0

2.2

2.3

–0.5

Max

2.63

2.63

3.47

85

V

DDEXT

+0.5

V

DDEXT

+0.5

+0.8

Unit

V

V

V

ºC

V

V

V

2

1

See

Environmental Conditions on Page 51

for information on thermal specifications.

Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, PA, BRST,

TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, and RCLK1.

3

Applies to input pins: CLKIN, RESET, and TRST.

Rev. B | Page 15 of 60 | February 2010

ADSP-21160M/ADSP-21160N

ELECTRICAL CHARACTERISTICS—ADSP-21160M

Table 6

shows ADSP-21160M electrical characteristics. These specifications are subject to change without notification.

Table 6. Electrical Characteristics—ADSP-21160M

I

ILPU1

I

ILPU2

I

OZH

I

OZL

I

OZHPD

I

OZLPU1

I

OZLPU2

I

OZHA

I

OZLA

Parameter

V

OH

V

OL

I

IH

I

IL

I

DD-INPEAK

I

DD-INHIGH

I

DD-INLOW

I

DD-IDLE

AI

DD

C

IN

High Level Output Voltage

1

Low Level Output Voltage

1

High Level Input Current

3, 4, 5

Low Level Input Current

3

Low Level Input Current Pull-Up1

4

Low Level Input Current Pull-Up2

5

Three-State Leakage Current

6, 7, 8, 9

Three-State Leakage Current

6

Three-State Leakage Current Pull-Down

9

Three-State Leakage Current Pull-Up1

7

Three-State Leakage Current Pull-Up2

8

Three-State Leakage Current

10

Three-State Leakage Current

10

Supply Current (Internal)

11

Supply Current (Internal)

12

Supply Current (Internal)

Supply Current (Idle)

14

Supply Current (Analog)

Input Capacitance

16, 17

13

15 t

Test Conditions

@ V

DDEXT

=Min, I

OH

@ V

DDEXT

=Min, I

OL

@ V

@ V

@ V

DDEXT

DDEXT

DDEXT

@ V

DDEXT

@ V

DDEXT

@ V

@ V

@ V

@ V

@ V

CCLK t

CCLK t

CCLK t

CCLK

@AV f

IN

DDEXT

DDEXT

DDEXT

DDEXT

DDEXT

DD

=Max, V

IN

=Max, V

=Max, V

=Max, V

=Max, V

=12.5 ns, V

=Max

=1 MHz, T

CASE

IN

IN

=–2.0 mA

2

=4.0 mA

2

=V

DD

Max

=0 V

=0 V

=Max, V

IN

=0 V

@ V

DDEXT

=Max, V

IN

=V

DD

Max

=Max, V

IN

=0 V

=Max, V

IN

=Max, V

IN

=Max, V

IN

IN

IN

=V

DD

Max

=0 V

=0 V

=V

=0 V

DDINT

DD

Max

=Max

=12.5 ns, V

DDINT

=Max

=12.5 ns, V

DDINT

=Max

=12.5 ns, V

DDINT

=Max

=25°C, V

IN

=2.5 V

Min

2.4

Max

0.4

10

10

250

500

10

10

250

250

500

25

4

1400

875

625

400

10

4.7

Unit

V

V

µA

µA

µA

µA

µA

µA

µA

µA

µA

µA mA mA mA mA mA mA pF

1

Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1,

PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS, TDO, and EMU.

2

See Output Drive Currents on page

47 for typical drive current capabilities.

3

Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, and CLK_CFG3-0.

4

Applies to input pins with internal pull-ups: DR0, and DR1.

6

5

Applies to input pins with internal pull-ups: DMARx, TMS, TDI, and TRST.

Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, and TDO.

7

Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, and EMU.

8

Applies to three-statable pins with internal pull-ups: MS3–0,RDx, WRx, DMAGx, PA, and CIF.

9

Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, and LxACK.

10

Applies to ACK pulled up internally with 2 kΩ during reset or ID2–0 = 00x.

11

The test program used to measure I

DD-INPEAK

represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power

measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 47

.

12

I

DD-INHIGH

is a composite average based on a range of high activity code. For more information, see

Power Dissipation on Page 47 .

13

I

DD-INLOW

is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 47

.

14

Idle denotes ADSP-21160M state during execution of IDLE instruction. For more information, see

Power Dissipation on Page 47

.

15

Characterized, but not tested.

16

Applies to all signal pins.

17

Guaranteed, but not tested.

Rev. B | Page 16 of 60 | February 2010

ADSP-21160M/ADSP-21160N

OPERATING CONDITIONS—ADSP-21160N

Table 7 shows recommended operating conditions for the

ADSP-21160N. These specifications are subject to change without notice.

Table 7. Operating Conditions—ADSP-21160N

Parameter

V

DDINT

AV

DD

V

DDEXT

T

CASE

V

IH1

V

IH2

V

IL

Internal (Core) Supply Voltage

Analog (PLL) Supply Voltage

External (I/O) Supply Voltage

Case Operating Temperature

1

High Level Input Voltage,

2

@ V

DDEXT

=Max

High Level Input Voltage,

3

@ V

DDEXT

=Max

Low Level Input Voltage

,2, 3

@ V

DDEXT

=Min

C Grade

Min

1.8

1.8

3.13

– 40

2.0

2.0

–0.5

Max

2.0

2.0

3.47

+100

V

DDEXT

+0.5

V

DDEXT

+0.5

+0.8

K Grade

Min

1.8

1.8

3.13

0

2.0

2.0

–0.5

Max

2.0

2.0

3.47

85

V

DDEXT

+0.5

V

DDEXT

+0.5

+0.8

Unit

V

V

V

ºC

V

V

V

2

1

See

Environmental Conditions on Page 51

for information on thermal specifications.

Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, PA, BRST,

TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, and RCLK1.

3

Applies to input pins: CLKIN, RESET, and TRST.

Rev. B | Page 17 of 60 | February 2010

ADSP-21160M/ADSP-21160N

ELECTRICAL CHARACTERISTICS—ADSP-21160N

Table 8

shows the electrical characteristics. Note that these specifications are subject to change without notification.

Table 8. Electrical Characteristics—ADSP-21160N

Parameter

V

OH

V

OL

I

IH

I

IL

I

IHC

I

ILC

I

IKH

I

IKL

I

IKH-OD

I

IKL-OD

I

ILPU1

I

ILPU2

I

OZH

I

OZL

I

OZHPD

I

OZLPU1

I

OZLPU2

I

OZHA

I

OZLA

I

DD-INPEAK

I

DD-INHIGH

I

DD-INLOW

I

DD-IDLE

AI

DD

C

IN

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

Low Level Input Current

3

CLKIN Low Level Input Current

Keeper Low Load Current

Keeper High Overdrive Current

Keeper Low Overdrive Current

7,

Low Level Input Current Pull-Up1

Low Level Input Current Pull-Up2

Three-State Leakage Current

Supply Current (Internal)

15

Supply Current (Internal)

16

Supply Current (Internal)

17

9

1

7

1

3, 4, 5

CLKIN High Level Input Current

Keeper High Load Current

7

10, 11, 12, 13

Three-State Leakage Current

10

6

6

7, 8,

8, 9

4

5

9

Three-State Leakage Current Pull-Down

13

Three-State Leakage Current Pull-Up1

11

Three-State Leakage Current Pull-Up2

12

Three-State Leakage Current

14

Three-State Leakage Current

14

Supply Current (Idle)

18

Supply Current (Analog)

Input Capacitance

19, 20

Test Conditions

@ V

DDEXT

=Min, I

OH

=–2.0 mA

2

@ V

DDEXT

=Min, I

OL

=4.0 mA

2

@ V

DDEXT

=Max, V

IN

=V

DD

Max

@ V

DDEXT

=Max, V

IN

=0 V

@ V

DDEXT

= Max, V

IN

= V

DDEXT

Max

@ V

DDEXT

= Max, V

IN

= 0 V

@ V

DDEXT

= Max, V

IN

= 2.0 V

@ V

DDEXT

= Max, V

IN

= 0.8 V

@ V

DDEXT

= Max

@ V

DDEXT

= Max

@ V

DDEXT

=Max, V

IN

=0 V

@ V

DDEXT

=Max, V

IN

=0 V

@ V

DDEXT

=Max, V

IN

=V

DD

Max

@ V

DDEXT

=Max, V

IN

=0 V

@ V

DDEXT

=Max, V

IN

=V

DD

Max

@ V

DDEXT

=Max, V

IN

=0 V

@ V

DDEXT

=Max, V

IN

=0 V

@ V

DDEXT

=Max, V

IN

=V

DD

Max

@ V

DDEXT

=Max, V

IN

=0 V t

CCLK

=10.0 ns, V

DDINT

=Max t

CCLK

=10.0 ns, V

DDINT

=Max t

CCLK

=10.0 ns, V

DDINT

=Max t

CCLK

=10.0 ns, V

DDINT

=Max

@AV

DD

=Max f

IN

=1 MHz, T

CASE

=25°C, V

IN

=2.5 V

Min

2.4

–250

50

–300

300

Max

0.4

10

10

25

25

–50

200

250

500

10

10

250

250

500

25

4

960

715

550

450

10

4.7

1

Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1,

PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS, TDO, and EMU.

2

See Output Drive Currents

47 for typical drive current capabilities.

5

4

3

Applies to input pins: SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, and CLK_CFG3-0.

Applies to input pins with internal pull-ups: DR0, and DR1.

Applies to input pins with internal pull-ups: DMARx, TMS, TDI, and TRST.

6

Applies to CLKIN only.

7

Applies to all pins with keeper latches: ADDR31–0, DATA63–0, PAGE, BRST, and CLKOUT.

9

8

Current required to switch from kept high to low, or from kept low to high.

Characterized, but not tested.

10

Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, and TDO.

11

Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, and EMU.

12

Applies to three-statable pins with internal pull-ups: MS3–0,RDx, WRx, DMAGx, PA, and CIF.

13

Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, and LxACK.

14

Applies to ACK pulled up internally with 2 kΩ during reset or ID2–0 = 00x.

15

The test program used to measure I

DD-INPEAK

represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power

measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 47

.

16

I

DD-INHIGH

is a composite average based on a range of high activity code. For more information, see

Power Dissipation on Page 47 .

17

I

DD-INLOW

is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 47

.

18

Idle denotes ADSP-21160N state during execution of IDLE instruction. For more information, see

Power Dissipation on Page 47 .

19

Applies to all signal pins.

20

Guaranteed, but not tested.

µA

µA

µA

µA

µA

µA

µA

µA

µA

Unit

V

V

µA

µA

µA

µA mA mA mA mA

µA

µA

µA mA mA pF

Rev. B | Page 18 of 60 | February 2010

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 9

(ADSP-21160M) and

Table 10 (ADSP-21160N) may cause permanent damage to

the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 9. Absolute Maximum Ratings—ADSP-21160M

Parameter

Internal (Core) Supply Voltage (V

DDINT

)

Analog (PLL) Supply Voltage (A

VDD

)

External (I/O) Supply Voltage (V

DDEXT

)

Input Voltage

Output Voltage Swing

Load Capacitance

Storage Temperature Range

Rating

–0.3 V to +3.0 V

–0.3 V to +3.0 V

–0.3 V to +4.6 V

–0.5 V to V

DDEXT

+ 0.5 V

–0.5 V to V

DDEXT

+ 0.5 V

200 pF

–65°C to +150°C

Table 10. Absolute Maximum Ratings—ADSP-21160N

Parameter

Internal (Core) Supply Voltage (V

DDINT

)

Analog (PLL) Supply Voltage (A

VDD

)

External (I/O) Supply Voltage (V

DDEXT

)

Input Voltage

Output Voltage Swing

Load Capacitance

Storage Temperature Range

Rating

–0.3 V to +2.3 V

–0.3 V to +2.3 V

–0.3 V to +4.6 V

–0.5 V to V

DDEXT

+ 0.5 V

–0.5 V to V

DDEXT

+ 0.5 V

200 pF

–65°C to +150°C

ESD SENSITIVITY

ESD (electrostatic discharge sensitive device)

Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

ADSP-21160M/ADSP-21160N

PACKAGE INFORMATION

The information presented in

Figure 7 provides details about

the package branding for the ADSP-21160M/ADSP-21160N processor. For a complete listing of product availability, see

Ordering Guide on Page 58

.

Z cc vvvvvv.x n.n

# yyww a

ADSP-21160a tppZ-cc vvvvvv.x n.n

#yyww country_of_origin

S

Figure 7. Typical Package Brand

Table 11. Package Brand Information

Brand Key

a

Field Description

ADSP-21160 Model (M or N)

RoHS Compliant Designation

See Ordering Guide

Assembly Lot Code

Silicon Revision

RoHS Compliant Designation

Date Code

Rev. B | Page 19 of 60 | February 2010

ADSP-21160M/ADSP-21160N

TIMING SPECIFICATIONS

The ADSP-21160x DSP’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop

(PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP’s internal clock

(the clock source for the external port logic and I/O pads).

The ADSP-21160x DSP’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, link ports, serial ports, and external port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG3–0 pins. Even though the internal clock is the clock source for the external port, the external port clock always switches at the

CLKIN frequency. To determine switching frequencies for the serial and link ports, divide down the internal clock, using the programmable divider control of each port (TDIVx/RDIVx for the serial ports and LxCLKD1–0 for the link ports).

Note the following definitions of various clock periods that are a function of CLKIN and the appropriate ratio control:

• t

CCLK

= (t

CK

) / CR

• t

LCLK

= (t

CCLK

) × LR

• t

SCLK

= (t

CCLK

)× SR where:

• LCLK = Link Port Clock

• SCLK = Serial Port Clock

• t

CK

= CLKIN Clock Period

• t

CCLK

= (Processor) Core Clock Period

• t

LCLK

= Link Port Clock Period

• t

SCLK

= Serial Port Clock Period

• CR = Core/CLKIN Ratio (2, 3, or 4:1, determined by CLK_CFG3–0 at reset)

• LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1, determined by LxCLKD)

• SR = Serial Port/Core Clock Ratio (wide range, determined by × CLKDIV)

Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times.

See Figure 33 on Page 49

under Test Conditions for voltage reference levels.

Switching characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.

Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

During processor reset (RESET pin low) or software reset (SRST bit in SYSCON register = 1), deassertion (MS3–0, HBG,

DMAGx, RDx, WRx, CIF, PAGE, BRST) and three-state

(FLAG3-0, LxCLK, LxACK, LxDAT7-0, ACK, REDY, PA,

TFSx, RFSx, TCLKx, RCLKx, DTx, BMS, TDO, EMU, DATA) timings differ. These occur asynchronously to CLKIN, and may not meet the specifications published in the timing requirements and switching characteristics tables. The maximum delay for deassertion and three-state is one t

CK

from RESET pin assertion low or setting the SRST bit in SYSCON. During reset the

DSP will not respond to SBTS, HBR, and MMS accesses. HBR asserted before reset will be recognized, but an HBG will not be returned by the DSP until after reset is deasserted and the DSP has completed bus synchronization.

Unless otherwise noted, all timing specifications (Timing

Requirements and Switching Characteristics) listed on pages 21

through 46 apply to both ADSP-21160M and ADSP-21160N.

Power-Up Sequencing

For power-up sequencing, see

Table 12 and Figure 8

. During the power-up sequence of the DSP, differences in the ramp-up rates and activation time between the two power supplies can cause current to flow in the I/O ESD protection circuitry. To prevent this damage to the ESD diode protection circuitry, Analog

Devices recommends including a bootstrap Schottky diode (see

Figure 9

). The bootstrap Schottky diode connected between the

V

DDINT

and V

DDEXT

power supplies protects the ADSP-21160x from partially powering the V

DDEXT

supply. Including a Schottky diode will shorten the delay between the supply ramps and thus prevent damage to the ESD diode protection circuitry. With this technique, if the V

DDINT

rail rises ahead of the V

DDEXT

rail, the

Schottky diode pulls the V

DDEXT

rail along with the V

DDINT

rail.

Rev. B | Page 20 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Table 12. Power-Up Sequencing

Parameter

Timing Requirements t

RSTVDD t

IVDDEVDD t

CLKVDD t

CLKRST t

PLLRST

RESET Low Before V

V

DDINT

on Before V

DDINT

DDEXT

/V

DDEXT

on

CLKIN Running After valid V

DDINT

/V

DDEXT

1

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted t

Switching Characteristics

CORERST

DSP Core Reset Deasserted After RESET Deasserted

Min

0

– 50

0

10

2

20

3

Max

+200

200

Unit

ns ms ms

µs

µs

4096t

CK

3, 4 ms

1

Valid V

DDINT

/V

DDEXT

assumes that the supplies are fully ramped to their V

DDINT

and V depending on the design of the power supply subsystem.

DDEXT

rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,

2

Assumes a stable CLKIN signal after meeting worst-case start-up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start-up time.

4

3

Based on CLKIN cycles.

CORERST is an internal signal only. The 4096 cycle count is dependent on t

SRST

specification. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum.

RESET

V

DDINT

V

DDEXT

CLKIN t

RSTVDD t

IVDDEVDD t

CLKVDD t

CLKRST

CLK_CFG3-0

CORERST t

PLLRST

Figure 8. Power-Up Sequencing

t

CORERST

Rev. B | Page 21 of 60 | February 2010

ADSP-21160M/ADSP-21160N

VDDEXT

VOLTAGE REGULATOR

V

DDEXT

ADSP-21160x

Clock Input

For clock input, see Table 13 and Figure 10

.

Table 13. Clock Input

Parameter

t

Timing Requirements

CK t

CKL t

CKH t

CKRF t

CCLK

CLKIN Period

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V–2.0 V)

Core Clock Period

VDDINT

VOLTAGE REGULATOR

V

DDINT

Figure 9. Dual Voltage Schottky Diode

ADSP-21160M

80 MHz

Min Max

ADSP-21160N

100 MHz

Min Max

Unit

25

10.5

10.5

12.5

80

40

40

3

40

20

7.5

7.5

10

80

40

40

3

30 ns ns ns ns ns

CLKIN t

CK t

CKH

Figure 10. Clock Input

t

CKL

Rev. B | Page 22 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Reset

For reset, see Table 14 and Figure 11 .

Table 14. Reset

Parameter Min Max Unit

t t

Timing Requirements

WRST

RESET Pulsewidth Low

1

SRST

RESET Setup Before CLKIN High

2

4t

8

CK ns ns

1

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is low, assuming stable V

DD

and CLKIN (not including start-up time of external clock oscillator).

2

Only required if multiple ADSP-21160x DSPs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple

ADSP-21160x DSPs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.

CLKIN t

SRST t

WRST

RESET

Figure 11. Reset

Rev. B | Page 23 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Interrupts

For interrupts, see Table 15 and Figure 12

.

Table 15. Interrupts

Parameter

t t t

Timing Requirements

SIR

IRQ2–0 Setup Before CLKIN High

1

HIR

IRQ2–0 Hold After CLKIN High

1

IPW

IRQ2–0 Pulsewidth

2

2

1

Only required for IRQx recognition in the following cycle.

Applies only if t

SIR

and t

HIR

requirements are not met.

CLKIN

IRQ2–0 t

SIR t

IPW

Figure 12. Interrupts

Timer

For timer, see Table 16 and Figure 13

.

Table 16. Timer

Parameter

t

Switching Characteristic

DTEX

CLKIN High to TIMEXP

1

1

For ADSP-21160M, specification is 7 ns, maximum.

CLKIN

TIMEXP t

DTEX

Figure 13. Timer

t

HIR

Min

6

0

2+t

CK

Min

1

Max

Max

9

t

DTEX

Unit

ns ns ns

Unit

ns

Rev. B | Page 24 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Flags

For flags, see Table 17 and Figure 14 .

Table 17. Flags

Parameter

t t t t

Timing Requirements

SFI

FLAG3–0 IN Setup Before CLKIN High

1

HFI

FLAG3–0 IN Hold After CLKIN High

1

DWRFI

FLAG3–0 IN Delay After RDx/WRx Low

1,

2

HFIWR

FLAG3–0 IN Hold After RDx/WRx Deasserted

1

Min

4

1

Max

10

0 t

Switching Characteristics

DFO t

HFO t

DFOE t

DFOD

FLAG3–0 OUT Delay After CLKIN High

FLAG3–0 OUT Hold After CLKIN High

CLKIN High to FLAG3–0 OUT Enable

CLKIN High to FLAG3–0 OUT Disable

3

1

1

2

1

Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N +2.

For ADSP-21160M, specification is 12 ns, maximum.

3

For ADSP-21160M, specification is 5 ns, maximum.

9 t

CK

– t

CCLK

+5 ns ns ns ns

Unit

ns ns ns ns

CLKIN

FLAG3–0

OUT t

DFOE t

DFO t

HFO

FLAG OUTPUT t

DFO t

DFOD

CLKIN

FLAG3–0

IN

RDx

WRx t

DWRFI t

SFI t

HFI t

HFIWR

FLAG INPUT

Figure 14. Flags

Rev. B | Page 25 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN accept for the ACK pin requirements listed in note 6

of Table 18

. These specifications apply when the ADSP-21160x is the bus master accessing external memory space in asynchronous access mode.

Table 18. Memory Read—Bus Master

Parameter

t t t t t t t t

Timing Requirements

DAD

Address, CIF, Selects Delay to Data Valid

1, 2, 3

DRLD

HDA

RDx Low to Data Valid

1, 4

Data Hold from Address, Selects

5

SDS

HDRH

DAAK

DSAK

SAKC

Data Setup to RDx High

1

Data Hold from RDx High

5

ACK Delay from Address, Selects

2, 6

ACK Delay from RDx Low

6

ACK Setup to CLKIN

6

t

HAKC

ACK Hold After CLKIN

Min

0

8

1

0.5t

1

CCLK

+3 t t t

Max

CK t

CK

CK

CK

– 0.25t

CCLK

– 0.5t

CCLK

– 0.5t

CCLK

– 0.75t

– 8.5+W

+W

– 12+W

CCLK

– 11+W

Unit

Switching Characteristics t

DRHA t

DARL t

RW t

RWR

Address, CIF, Selects Hold After RDx High

Address, CIF, Selects to RDx Low

RDx Pulsewidth

2

RDx High to WRx, RDx, DMAGx Low t

0.25t

CK

0.5t

CCLK

0.25t

CCLK

– 0.5t

CCLK

– 1+H

– 3

CCLK

– 1+W

– 1+HI

W = (number of wait states specified in WAIT register) × t

CK

.

HI = t

CK

(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t

CK

(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

ns ns ns ns

1

Data Delay/Setup: User must meet t

DAD

, t

DRLD

, or t

SDS

.

2

The falling edge of MSx, BMS is referenced.

6

5

4

3

For ADSP-21160M, specification is t

CK

–0.25t

CCLK

–11+W ns, maximum.

For ADSP-21160M, specification is 0.75t

CK

–11+W ns, maximum.

Data Hold: User must meet t

HDA capacitive and dc loads.

or t

HDRH

in asynchronous access mode. See Example System Hold Time Calculation on page

49 for the calculation of hold times given

For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access, ACK must be driven low (deasserted) by t

DAAK

, t

DSAK

, or t

SAKC t

HAKC

must be met for both assertion and deassertion of ACK signal.

. For the second and subsequent cycles of an asynchronous external memory access, the t

SAKC

and ns ns ns ns ns ns ns ns ns

Rev. B | Page 26 of 60 | February 2010

ADDRESS

MSx, BMS,

CIF

RD

DATA

ACK

CLKIN

WR, DMAG t

DARL t

DAAK t

DAD t

DRLD t

DSAK t

RW t

SAKC t

SDS t

HAKC

ADSP-21160M/ADSP-21160N

t

HDA t

DRHA t

HDRH t

RWR

Figure 15. Memory Read—Bus Master

Rev. B | Page 27 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN except for the ACK pin requirements listed in note 1

of Table 19

. These specifications apply when the ADSP-21160x is the bus master accessing external memory space in asynchronous access mode.

Table 19. Memory Write—Bus Master

Parameter

t t t t

Timing Requirements

DAAK

ACK Delay from Address, Selects

1, 2

DSAK

ACK Delay from WRx Low

1

SAKC

ACK Setup to CLKIN

1

HAKC

ACK Hold After CLKIN

1

Min

0.5t

CCLK

+3

1 t t

Max

CK

CK

– 0.5t

CCLK

–12+W

– 0.75t

CCLK

– 11+W

Unit

ns ns ns ns t t

Switching Characteristics

DAWH

Address, CIF, Selects to WRx Deasserted

2

t

DAWL

Address, CIF, Selects to WRx Low

2

t

WW

DDWH

WRx Pulsewidth

Data Setup before WRx High

3 t

DWHA

Address Hold after WRx Deasserted t

CK

– 0.25t

CCLK

– 3+W

0.25t

CCLK

– 3 t

CK

– 0.5t

CCLK

– 1+W t

CK

– 0.5t

CCLK

– 1+W

0.25t

CCLK

– 1+H ns ns ns ns t

DWHD t

DATRWH

Data Hold after WRx Deasserted

Data Disable after WRx Deasserted

4

0.25t

CCLK

– 1+H

0.25t

CCLK

– 2+H 0.25t

CCLK

+2+H t

WWR t

DDWR t

WDE

WRx High to WRx, RDx, DMAGx Low

Data Disable before WRx or RDx Low

0.5t

CCLK

0.25t

– 1+HI

CCLK

– 1+I

WRx Low to Data Enabled –0.25t

CCLK

– 1

W = (number of wait states specified in WAIT register) × t

CK

.

H = t

CK

(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

HI = t

CK

(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

I = t

CK

(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

ns ns ns ns ns ns

1

For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory

4

3 access, ACK must be driven low (deasserted) by t

DAAK

or t

DSAK

or t

SAKC

. For the second and subsequent cycles of an asynchronous external memory access, the t

SAKC

and t

HAKC

must be met for both assertion and deassertion of ACK signal

2

The falling edge of MSx, BMS is referenced.

For ADSP-21160M, specification is t

CK

–0.25t

CCLK

–12.5+W ns, minimum.

See

Example System Hold Time Calculation on Page 49 for calculation of hold times given capacitive and dc loads.

Rev. B | Page 28 of 60 | February 2010

ADSP-21160M/ADSP-21160N

ADDRESS

MSx, BMS,

CIF

WR

DATA

ACK

CLKIN

RD, DMAG t

DAWL t

DAAK t t

WDE

DSAK t

DAWH t

WW t

SAKC t

DDWH t

DATRWH

t

DWHD t

HAKC

Figure 16. Memory Write—Bus Master

t

DWHA t

WWR t

DDWR

Rev. B | Page 29 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Synchronous Read/Write—Bus Master

See Table 20

and Figure 17

. Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-21160x (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see Memory Read–Bus Master on page

26

and Memory Write–Bus Master on page

28

).

When accessing a slave ADSP-21160x, these switching characteristics must meet the slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write–Bus

Slave on page

32 ). The slave ADSP-21160x must also meet these

(bus master) timing requirements for data and acknowledge setup and hold times.

Table 20. Synchronous Read/Write—Bus Master

Parameter

t

Timing Requirements

SSDATI t

HSDATI t

SACKC

Data Setup Before CLKIN

Data Hold After CLKIN

ACK Setup Before CLKIN t

HACKC

ACK Hold After CLKIN

Min

5.5

1

0.5t

CCLK

+3

1

Max Unit

t

DWRO t

DRWL t

DDATO t

HDATO t

DACKMO t

ACKMTR t

DCKOO t

CKOP t

CKWH t

CKWL t

Switching Characteristics

DADDO t

HADDO t

DPGO t

DRDO

Address, MSx, BMS, BRST, CIF Delay After CLKIN

Address, MSx, BMS, BRST, CIF Hold After CLKIN

PAGE Delay After CLKIN

RDx High Delay After CLKIN

WRx High Delay After CLKIN

RDx/WRx Low Delay After CLKIN

Data Delay After CLKIN

1

Data Hold After CLKIN

ACK Delay After CLKIN

2, 3

ACK Disable Before CLKIN

2

CLKOUT Delay After CLKIN

CLKOUT Period

CLKOUT Width High

CLKOUT Width Low

4 t t

1.5

1.5

0.25t

0.25t

0.25t

1.5

3

–3

0.5

t

CK

CK

CK

– 1

CCLK

CCLK

CCLK

/2 – 2

/2 – 2

– 1

– 1

– 1

10

11

0.25t

0.25t

CCLK

CCLK

+9

+9

0.25t

CCLK

+9

0.25t

CCLK

+9

9

5 t

CK

5

+1 t

CK

/2+2

2 t

CK

/2+2

2

4

3

2

1

For ADSP-21160M, specification is 12.5 ns, maximum.

Applies to broadcast write, master precharge of ACK.

For ADSP-21160M, specification is 0.25t

CCLK

+3 ns (minimum) and .25t

CCLK

+9 ns (maximum).

For ADSP-21160M, specification is 2 ns, minimum.

5

Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise. For more information, see the System Design chapter in the

ADSP-21160 SHARC DSP Hardware Reference.

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Rev. B | Page 30 of 60 | February 2010

ADSP-21160M/ADSP-21160N

CLKIN

CLKOUT

ADDRESS

MSx, BRST,

CIF

PAGE t

DCKOO t

DADDO

ACK

(IN)

ACK

(OUT)

READ CYCLE

RDx t t

DPGO

DACKMO t

DRWL t

CKWH t

CKOP t

CKWL t t

SACKC

ACKMTR t t

HADDO

HACKC t

DRDO t

SSDATI t

HSDATI

DATA

(IN)

WRITE CYCLE

WRx

DATA

(OUT) t t

DRWL

DDATO t

DWRO t

HDATO

Figure 17. Synchronous Read/Write—Bus Master

Rev. B | Page 31 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Synchronous Read/Write—Bus Slave

See Table 21 and Figure 18 . Use these specifications for

ADSP-21160x bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet these (bus slave) timing requirements.

Table 21. Synchronous Read/Write—Bus Slave

Parameter

t t

Timing Requirements

SADDI

HADDI t

SRWI t

HRWI t

SSDATI t

HSDATI

Address, BRST Setup Before CLKIN

Address, BRST Hold After CLKIN

RDx/WRx Setup Before CLKIN

RDx/WRx Hold After CLKIN

Data Setup Before CLKIN

Data Hold After CLKIN t t

Switching Characteristics

DDATO

Data Delay After CLKIN

1

HDATO t

DACKC

Data Hold After CLKIN

ACK Delay After CLKIN t

HACKO

ACK Hold After CLKIN

1

For ADSP-21160M, specification is 12.5 ns, maximum.

CLKIN

ADDRESS

BRST

ACK

READ ACCESS

RDx

DATA

(OUT)

WRITE ACCESS

WRx

DATA

(IN) t

DACKC t

DDATO t

SADDI t

SRWI t

SRWI t

SSDATI

Figure 18. Synchronous Read/Write—Bus Slave

Min

5

1

5

1

5.5

1

1.5

1.5

t

HADDI t

HRWI t

HSDATI

Max

0.25 t

CCLK

+ 9

10

t

HACKO t

HRWI t

HDATO

ns ns ns ns

Unit

ns ns ns ns ns ns

Rev. B | Page 32 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Multiprocessor Bus Request and Host Bus Request

See Table 22 and

Figure 19 . Use these specifications for passing

of bus mastership between multiprocessing ADSP-21160x DSPs

(BRx) or a host processor, both synchronous and asynchronous

(HBR, HBG).

Table 22. Multiprocessor Bus Request and Host Bus Request

Parameter

t t t t

Timing Requirements

HBGRCSV

SHBRI

HHBRI t

SHBGI

HBG Low to RDx/WRx/CS Valid

1

HBR Setup Before CLKIN

2

HBR Hold After CLKIN

2

HBG Setup Before CLKIN t

HHBGI t

SBRI

HBG Hold After CLKIN High

BRx, PA Setup Before CLKIN

HBRI t

SRPBAI t

HRPBAI

BRx, PA Hold After CLKIN High

RPBA Setup Before CLKIN

RPBA Hold After CLKIN t

Switching Characteristics t

DHBGO t

HHBGO t

DBRO

HBRO

HBG Delay After CLKIN

HBG Hold After CLKIN

3

BRx Delay After CLKIN

BRx Hold After CLKIN t

DPASO t

TRPAS t

DPAMO t

PATR t

DRDYCS t

TRDYHG t

ARDYTR

PA Delay After CLKIN, Slave

PA Disable After CLKIN, Slave

PA Delay After CLKIN, Master

PA Disable Before CLKIN, Master

4

REDY (O/D) or (A/D) Low from CS and HBR Low

5, 6

REDY (O/D) Disable or REDY (A/D) High from HBG

5, 7

REDY (A/D) Disable from CS or HBR High

5

2

1

For ADSP-21160M, specification is 19 ns, maximum.

Only required for recognition in the current cycle.

3

For ADSP-21160M, specification is 2 ns, maximum.

7

6

5

4

For ADSP-21160M, specification is 0.25t

CK

–5 ns, minimum.

(O/D) = open drain, (A/D) = active drive.

For ADSP-21160M, specification is 0.5t

CK ns, maximum.

For ADSP-21160M, specification is t

CK

+25 ns, maximum.

9

1

6

2

6

1

6

1

Min

1.5

1.5

1.5

0.25t

CCLK

– 5.5

t

CK

+15

7

8

Max Unit

6.5 + t

CK

+ t

CCLK

– 12.5CR ns ns ns ns ns ns ns ns ns

8

0.25t

CCLK

0.5t

11

+9

CK

+1.0

ns ns ns ns ns ns ns ns ns ns ns

Rev. B | Page 33 of 60 | February 2010

ADSP-21160M/ADSP-21160N

CLKIN

HBR

HBG (OUT)

BRx

(OUT)

PA (OUT)

(SLAVE)

PA

(OUT)

(MASTER) t

SH B R I t

H H BR I t

H HB G O t

DH B GO t

H B RO t

DB R O t

D PA S O t

D PA M O t

SH B GI

HBG

(IN) t

SB R I

BRx, PA (IN) t

S R PB A I t

H R PB A I

RPBA

HRB

CS

REDY

(O/ D)

REDY

(A/D) t

DR D YC S t

TR D YH G t

H B GR CS V

HBG (OUT)

RDx

WRx

CS

O /D = OPEN DRAIN, A/D = ACTIVE DRI VE

Figure 19. Multiprocessor Bus Request and Host Bus Request

t

P A TR t

H H B GI t

H B R I t

TR PA S t

A R DY TR

Rev. B | Page 34 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Asynchronous Read/Write—Host to ADSP-21160x

Use these specifications (

Table 23 , Table 24

,

Figure 20

, and

Figure 21 ) for asynchronous host processor accesses of an

ADSP-21160x, after the host has asserted CS and HBR (low).

Table 23. Read Cycle

Parameter

t

Timing Requirements

SADRDL t

HADRDH t

WRWH

Address Setup/CS Low Before RDx Low

Address Hold/CS Hold Low After RDx

RDx/WRx High Width t

DRDHRDY t

DRDHRDY

RDx High Delay After REDY (O/D) Disable

RDx High Delay After REDY (A/D) Disable t t t t

Switching Characteristics

SDATRDY

DRDYRDL

RDYPRD

HDARWH

Data Valid Before REDY Disable from Low

REDY (O/D) or (A/D) Low Delay After RDx Low

1

REDY (O/D) or (A/D) Low Pulsewidth for Read

2

Data Disable After RDx High

3

3

2

1

For ADSP-21160M, specification is 7 ns, minimum.

For ADSP-21160M, specification is t

CK ns, minimum.

For ADSP-21160M, specification is 2 ns, minimum.

Table 24. Write Cycle

t t

Parameter

Timing Requirements

SCSWRL

HCSWRH t

SADWRH t

HADWRH t

WWRL t

WRWH t

DWRHRDY t

SDATWH t

HDATWH

CS Low Setup Before WRx Low

CS Low Hold After WRx High

Address Setup Before WRx High

Address Hold After WRx High

WRx Low Width

1

RDx/WRx High Width

WRx High Delay After REDY (O/D) or (A/D) Disable

Data Setup Before WRx High

Data Hold After WRx High t t

Switching Characteristics

DRDYWRL

RDYPWR

REDY (O/D) or (A/D) Low Delay After WRx/CS Low

REDY (O/D) or (A/D) Low Pulsewidth for Write

2

2

1

For ADSP-21160M, specification is 7 ns, minimum.

For ADSP-21160M, specification is 12 ns, minimum

After HBG is returned by the ADSP-21160x, the host can drive the RDx and WRx pins to access the ADSP-21160x DSP’s internal memory or IOP registers. HBR and HBG are assumed low for this timing.

2 t

CK

– 4

1.5

Min

0

5

4

6

2

0

0 t

CCLK

+1

5

Min

5

0

0

2

0

5.75 + 0.5t

CCLK

Max

11

6

Max

11 ns ns ns ns

Unit

ns ns ns ns ns ns ns ns ns

Unit

ns ns ns ns ns ns ns

Rev. B | Page 35 of 60 | February 2010

ADSP-21160M/ADSP-21160N

READ CYCLE

ADDRESS/CS

RDx t

SADRDL t

HADRDH t

WRWH t

HDARWH

DATA (OUT) t

DRDYRDL t

SDATRDY t

RDYPRD t

DRDHRDY

REDY (O/D)

REDY (A/D)

Figure 20. Asynchronous Read—Host to ADSP-21160x

WRITE CYCLE

ADDRESS t

SCSWRL t

SADWRH t

HCSWRH t

HADWRH

CS t

WWRL t

WRWH

WRx t

SDATWH

DATA (IN) t

DRDYWRL t

RDYPWR t

DWRHRDY

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 21. Asynchronous Write—Host to ADSP-21160x

t

HDATWH

Rev. B | Page 36 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Three-State Timing—Bus Master, Bus Slave

See Table 25 and

Figure 22 . These specifications show how the

memory interface is disabled (stops driving) or enabled

(resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.

Table 25. Three-State Timing—Bus Master, Bus Slave

Parameter

Timing Requirements t

STSCK t

HTSCK

SBTS Setup Before CLKIN

SBTS Hold After CLKIN

1

Min

6

2 t

DATTR t

ACKEN t

ACKTR t

CDCEN t

CDCTR t

ATRHBG t

STRHBG t

MIENHG t

MITRA t t t

Switching Characteristics

MIENA

MIENS t

MITRS t

MITRHG

DATEN

Address/Select Enable After CLKIN

Strobes Enable After CLKIN

2

HBG Enable After CLKIN

Address/Select Disable After CLKIN

Strobes Disable After CLKIN

HBG Disable After CLKIN

6

Data Enable After CLKIN

7, 8

2, 4, 5

Data Disable After CLKIN

7, 9

ACK Enable After CLKIN

7

ACK Disable After CLKIN

7

CLKOUT Enable After CLKIN

10

3 t t t

PTRHBG

BTRHBG

MENHBG

CLKOUT Disable After CLKIN

Address, MSx Disable Before HBG Low

11

RDx, WRx, DMAGx Disable Before HBG Low

11

Page Disable Before HBG Low

11

BMS Disable Before HBG Low

11

Memory Interface Enable After HBG High

12, 13 t

1.5

1.5

1.5

0.5

0.25t

CCLK

0.5

0.25t

0.5

1.5

1.5

0.5

CCLK t

CCLK

– 3

+1

1.5t

CK

– 6 t

CK

+ 0.25t

CCLK

– 6

CK

– 6

0.5t

CK

– 6.5

t

CK

– 5

– 4

7

6

5

4

3

2

1

For ADSP-21160M, specification is 1 ns, minimum.

Strobes = RDx, WRx, and DMAGx.

For ADSP-21160M, specification is 0.25t

CCLK

–1 ns (minimum) and 0.25t

CCLK

+4 ns (maximum).

If access aborted by SBTS, then strobes disable before CLKIN [0.25t

CCLK

+ 1.5 (min.), 0.25t

CCLK

+ 5 (max.)]

For ADSP-21160M, specification is 0.25t

CCLK ns (maximum).

For ADSP-21160M, specification is 3.5 ns (minimum).

In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

8

For ADSP-21160M, specification is 1.5 ns (minimum) and 10 ns (maximum).

9

For ADSP-21160M, specification is 1.5 ns (minimum).

10

For ADSP-21160M, specification is 0.5 ns (minimum).

11

Not specified for ADSP-21160M.

12

Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).

13

For ADSP-21160M, specification is t

CK

+5 ns (maximum).

Max

9

9

9

9

0.25t

CCLK

+1.5

8

0.25t

CCLK

+ 7

5

9

5

9 t

CCLK

+1

1.5t

CK

+ 5 t

CK

+ 0.25t

CCLK

+ 5 t

CK

+ 5

0.5t

CK

+ 1.5

t

CK

+6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Unit

ns ns

Rev. B | Page 37 of 60 | February 2010

ADSP-21160M/ADSP-21160N

CLKIN

SBTS

MEMORY

INTERFACE

DATA

ACK

CLKOUT

HBG

MEMORY

INTERFACE t

STSCK t

HTSCK t

MIENA, t

MIENS, t

MIENHG t

DATTR t

ACKTR t

MITRA, t

MITRS, t

MITRHG t

DATEN t

ACKEN t

CDCEN t

CDCTR t

MENHBG

MEMORY INTERFACE = ADDRESS, RDx, WRx, MSx, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)

Figure 22. Three-State Timing—Bus Master, Bus Slave

t

ATRHBG t

STRHBG t

PTRHBG t

BTRHBG

Rev. B | Page 38 of 60 | February 2010

ADSP-21160M/ADSP-21160N

DMA Handshake

See Table 26 and

Figure 23 . These specifications describe the

three DMA handshake modes. In all three modes, DMARx is used to initiate transfers. For handshake mode, DMAGx controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the

ADDR31–0, RDx, WRx, PAGE, MS3–0, ACK, and DMAGx signals. For Paced Master mode, the data transfer is controlled by ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAGx).

For Paced Master mode, the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus

Master timing specifications for ADDR31–0, RDx, WRx,

MS3–0, PAGE, DATA63–0, and ACK also apply.

Table 26. DMA Handshake

Parameter

t t

SDATDGL t

HDATIDG t

DATDRH t t t

Timing Requirements

SDRC

WDR

DMARx Setup Before CLKIN

1

DMARx Width Low (Nonsynchronous)

2, 3

Data Setup After DMAGx Low

4, 5

DMARLL

DMARH

Data Hold After DMAGx High

Data Valid After DMARx High

4, 6

DMARx Low Edge to Low Edge

7

DMARx Width High

2, 8

Min

3

0.5t

CCLK

2

+2.5

t

CK

0.5t

CCLK

+1 t t

Max

CK

CK

– 0.5t

CCLK

+3

–7

Unit

ns ns ns ns ns ns ns t t

Switching Characteristics

DDGL t

WDGH t

WDGL t

HDGC t

VDATDGH

DATRDGH

DMAGx Low Delay After CLKIN

DMAGx High Width

DMAGx Low Width

DMAGx High Delay After CLKIN

Data Valid Before DMAGx High

9

Data Disable After DMAGx High

10

0.25t

CCLK

+1

0.5t

CCLK

– 1+HI t

CK

– 0.5t

CCLK

– 1 t

CK

– 0.25t

CCLK

+1.5

t

CK

– 0.25t

CCLK

– 8

0.25t

CCLK

– 3 t

DGWRL t

DGWRH t

DGWRR t t t

DGRDL t

DRDGH t

DGRDR

DGWR

DADGH

WRx Low Before DMAGx Low

DMAGx Low Before WRx High

WRx High Before DMAGx High

11

RDx Low Before DMAGx Low

RDx Low Before DMAGx High

RDx High Before DMAGx High

11

DMAGx High to WRx, RDx, DMAGx Low

Address/Select Valid to DMAGx High

12 t

–1.5

t

CK

– 0.5t

CCLK

– 2 +W

–1.5

–1.5

CK

– 0.5t

CCLK

–1.5

–2+W

0.5t

CCLK

– 2+HI

15.5

t

DDGHA

Address/Select Hold after DMAGx High 1

W = (number of wait states specified in WAIT register) × t

CK

.

HI = t

CK

(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

t t

0.25t

2

2

2

2

CK

CK

CCLK

+9

– 0.25t

CCLK

– 0.25t

0.25t

CCLK

CCLK

+1.5

+9

+5

2

1

Only required for recognition in the current cycle.

Maximum throughput using DMARx / DMAGx handshaking equals t

WDR

+ t

DMARH

= (0.5t

CCLK

+ 1) + (0.5t

CCLK

+1)=10.0 ns (100 MHz). This throughput limit applies to non-synchronous access mode only.

3

For ADSP-21160M, specification is t

CCLK

+4.5 ns, minimum.

4 t

SDATDGL

is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can be driven t

DATDRH

after DMARx is brought high.

5

For ADSP-21160M, specification is 0.75t

CCLK

–7 ns, maximum.

6

For ADSP-21160M, specification is t

CLK

+10 ns, maximum.

7

Use t

DMARLL

if DMARx transitions synchronous with CLKIN. Otherwise, use t

WDR

and t

DMARH

.

8

For ADSP-21160M, specification is t

CCLK

+4.5 ns, minimum.

9 t

VDATDGH

is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t n equals the number of extra cycles that the access is prolonged.

VDATDGH

10

See Example System Hold Time Calculation on page

49 for calculation of hold times given capacitive and dc loads.

= t

CK

– 0.25t

CCLK

– 8 + (n × t

CK

) where

11

This parameter applies for synchronous access mode only.

12

For ADSP-21160M, specification is 18 ns, minimum.

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Rev. B | Page 39 of 60 | February 2010

ADSP-21160M/ADSP-21160N

CLKIN t

SDRC t

DMARLL

DMARx t

WDR t

DDGL t

SDRC t

DMARH t

HDGC t

WDGL t

WDGH

DMAGx

TRANSFERS BETWEEN ADSP-2116X

INTERNAL MEMORY AND EXTERNAL DEVICE t

DATRDGH t

VDATDGH

DATA

(FROM ADSP-2116X TO EXTERNAL DRIVE) t

SDATDGL t

DATDRH t

HDATIDG

DATA

(FROM EXTERNAL DRIVE TO ADSP-2116X)

TRANSFERS BETWEEN EXTERNAL DEVICE AND

EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

WRx t

DGWRL

(EXTERNAL DEVICE TO EXTERNAL MEMORY) t

DGWRH t

DGWRR

RDx

(EXTERNAL MEMORY TO EXTERNAL DEVICE) t

DGRDL t

DRDGH t

DADGH

ADDR

MSx

* MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER

TIMING SPECIFICATIONS FOR ADDR31–0, RDx, WRx, MS3–0 AND ACK ALSO APPLY HERE.

t

DGRDR t

DDGHA

Figure 23. DMA Handshake

Rev. B | Page 40 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Link Ports—Receive, Transmit

For link ports, see Table 27

,

Table 28 ,

Figure 24 , and

Figure 25 .

Calculation of link receiver data setup and hold, relative to link clock, is required to determine the maximum allowable skew that can be introduced in the transmission path, between

LDATA and LCLK. Setup skew is the maximum delay that can be introduced in LDATA, relative to LCLK (setup skew = t

LCLKTWH

minimum – t

DLDCH

– t

SLDCL

). Hold skew is the

Table 27. Link Ports—Receive

Parameter

t t t t

Timing Requirements

SLDCL

HLDCL t

LCLKIW

Data Setup Before LCLK Low

Data Hold After LCLK Low

1

LCLKRWL

LCLKRWH

LCLK Period

LCLK Width Low

2

LCLK Width High

3 maximum delay that can be introduced in LCLK, relative to

LDATA (hold skew = t tester guardbands.

Min

2.5

3 t

LCLK

4

4

LCLKTWL

minimum + t

Max

t

Switching Characteristics

DLALC

LACK Low Delay After LCLK High

4, 5

9 17

1

For ADSP-21160M, specification is 2.5 ns, minimum.

2

For ADSP-21160M, specification is 6 ns, minimum.

5

4

3

For ADSP-21160M, specification is 6 ns, minimum.

LACK goes low with t

DLALC

relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.

For ADSP-21160M, specification is 12 ns, minimum.

HLDCH

– t

HLDCL

). Calculations made directly from speed specifications result in unrealistically small skew times, because they include multiple

Note that there is a two-cycle effect latency between the link port enable instruction and the DSP enabling the link port.

Unit

ns ns ns ns ns ns

LCLK

LDAT(7:0)

LACK (OUT)

RECEIVE t

LCLKRWH t

SLDCL

IN t

LCLKIW t

HLDCL t

LCLKRWL

Figure 24. Link Ports—Receive

t

DLALC

Rev. B | Page 41 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Table 28. Link Ports—Transmit

Parameter

Timing Requirements t

SLACH t

HLACH

LACK Setup Before LCLK High

LACK Hold After LCLK High

Min

14

–2 t t

Switching Characteristics

DLDCH t

HLDCH t

LCLKTWL t

LCLKTWH

DLACLK

Data Delay After LCLK High

Data Hold After LCLK High

LCLK Width Low

1

LCLK Width High

2

LCLK Low Delay After LACK High

3

–2

0.5t

LCLK

– 0.5

0.5t

LCLK

–0.5

0.5t

LCLK

+4

3

2

1

For ADSP-21160M, specification is 0.5t

LCLK

–1.5 ns (minimum) and 0.5t

LCLK

+1.5 ns (maximum).

For ADSP-21160M, specification is 0.5t

LCLK

–1.5 ns (minimum) and 0.5t

LCLK

+1.5 ns (maximum).

For ADSP-21160M, specification is 0.5t

LCLK

+5 ns (minimum) and 3t

LCLK

+11 ns (maximum).

Max

4

0.5t

LCLK

+0.5

0.5t

LCLK

+0.5

3/2t

LCLK

+11

TRANSMIT t

LCLKTWH t

LCLKTWL

LCLK

LDAT(7:0) t

HLDCH

OUT t

DLDCH

LACK (IN)

LAST NIBBLE/BYTE

TRANSMITTED

FIRST NIBBLE/BYTE

TRANSMITTED

LCLK INACTIVE

(HIGH) t

SLACH t

HLACH

THE t

SLACH

REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE/BYTE TRANSMITTED.

Figure 25. Link Ports—Transmit

t

DLACLK

ns ns ns ns ns

Unit

ns ns

Rev. B | Page 42 of 60 | February 2010

Serial Ports

For serial ports, see Table 29

,

Table 30

,

Table 31 , Table 32

,

Table 33 , Table 34

,

Table 35

,

Figure 26 , and

Figure 27 . To deter-

mine whether communication is possible between two devices

Table 29. Serial Ports—External Clock

Parameter

t t t t t

Timing Requirements

SFSE

TFS/RFS Setup Before TCLK/RCLK

1

HFSE

TFS/RFS Hold After TCLK/RCLK

1

SDRE

Receive Data Setup Before RCLK

1

HDRE

SCLKW

Receive Data Hold After RCLK

1, 2

TCLK/RCLK Width

3 t

SCLK

TCLK/RCLK Period

1

Referenced to sample edge.

3

2

For ADSP-21160M, specification is 4 ns, minimum.

For ADSP-21160M, specification is 14 ns, minimum.

Table 30. Serial Ports—Internal Clock

Parameter

t t t t

Timing Requirements

SFSI

TFS Setup Before TCLK

1

; RFS Setup Before RCLK

1

HFSI

SDRI

TFS/RFS Hold After TCLK/RCLK

1, 2

Receive Data Setup Before RCLK

1

HDRI

Receive Data Hold After RCLK

1

2

1

Referenced to sample edge.

For ADSP-21160M, specification is 1 ns, minimum

Table 31. Serial Ports—External or Internal Clock

Parameter

t t

Switching Characteristics

DFSE

RFS Delay After RCLK (Internally Generated RFS)

1

HOFSE

RFS Hold After RCLK (Internally Generated RFS)

1

1

Referenced to drive edge.

Table 32. Serial Ports—External Clock

Parameter

t

Switching Characteristics

DFSE

TFS Delay After TCLK (Internally Generated TFS)

1 t

HOFSE

TFS Hold After TCLK (Internally Generated TFS)

1

t

DDTE

Transmit Data Delay After TCLK

1

t

HDTE

Transmit Data Hold After TCLK

1

1

Referenced to drive edge.

ADSP-21160M/ADSP-21160N at clock speed n, the following specifications must be confirmed:

1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.

3

0

Min

3.5

4

1.5

6.5

8

2t

CCLK

Min

8 t

CCLK

/2 + 1

6.5

3

Min

3

Min

Max

Max

Max

13

Max

13

16

Unit

ns ns ns ns

Unit

ns ns ns ns

Unit

ns ns ns ns ns ns

Unit

ns ns

Rev. B | Page 43 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Table 33. Serial Ports—Enable and Three-State

Parameter

t t t t

Switching Characteristics

DDTEN

DDTTE

DDTIN

DDTTI

Data Enable from External TCLK

1

Data Disable from External TCLK

1

Data Enable from Internal TCLK

1

Data Disable from Internal TCLK

1

1

Referenced to drive edge.

Table 34. Serial Ports—Internal Clock

Parameter

t

Switching Characteristics t t t t

DFSI

HOFSI

DDTI

HDTI

SCLKIW

TFS Delay After TCLK (Internally Generated TFS)

1

TFS Hold After TCLK (Internally Generated TFS)

1

Transmit Data Delay After TCLK

1

Transmit Data Hold After TCLK

1

TCLK/RCLK Width

2

1

Referenced to drive edge.

2

For ADSP-21160M, specification is 0.5t

SCLK

–2.5 ns (minimum) and 0.5t

SCLK

+2 ns (maximum)

DRIVE

EXTERNAL RFS WITH MCE = 1, MFD = 0

SAMPLE DRIVE

RCLK t

SFSE/I t

HOFSE/I

RFS

TCLK

DT t

DDTE/I t

DDTENFS t

HDTE/I

1ST BIT t

DDTLFSE

DRIVE t

SFSE/I

LATE EXTERNAL TFS

SAMPLE DRIVE t

HOFSE/I

2ND BIT

TFS

DT t

DDTE/I t

DDTLFSE

TDDTENFS t

HDTE/I

1ST BIT 2ND BIT

Figure 26. Serial Ports—External Late Frame Sync

Min

4

0

Min

–1.5

0

0.5t

SCLK

–1.5

Max

10

3

Max

4.5

7.5

0.5t

SCLK

+1.5

Unit

ns ns ns ns ns

Unit

ns ns ns ns

Rev. B | Page 44 of 60 | February 2010

Table 35. Serial Ports—External Late Frame Sync

Parameter

Switching Characteristics t

DDTLFSE t

DDTENFS

Data Delay from Late External TFS or External RFS with MCE = 1,

MFD = 0

1

Data Enable from Late FS or MCE = 1, MFD = 0

1

MCE = 1, TFS enable and TFS valid follow t

DDTLFSE

and t

DDTENFS

.

1

Min

1.0

ADSP-21160M/ADSP-21160N

Max

13

Unit

ns ns

RCLK

RFS

DR t

DATA RECEIVE— INTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE t

SCLKIW

HOFSE

DATA RECEIVE— EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE t

SCLKW

RCLK t

DFSE t

DFSE t

SFSI t

HFSI t

HOFSE t

SFSE t

HFSE

RFS t

SDRI t

HDRI t

SDRE

DR

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

t

HDRE

DATA TRANSMIT— INTERNAL CLOCK

DRIVE

EDGE t

SCLKIW

SAMPLE

EDGE

DATA TRANSMIT— EXTERNAL CLOCK

DRIVE

EDGE t

SCLKW

SAMPLE

EDGE

TCLK

TCLK t

DFSI t

DFSE t

HOFSI t

SFSI t

HFSI t

HOFSE t

SFSE t

HFSE

TFS TFS t

DDTI t

DDTE t

HDTI t

HDTE

DT

DT

TCLK

(EXT)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE DRIVE EDGE

TCLK /

RCLK t

DDTEN t

DDTTE

DT

DRIVE

EDGE

DRIVE

EDGE

TCLK

(INT) t

DDTIN

TCLK /

RCLK t

DDTTI

DT

Figure 27. Serial Ports

Rev. B | Page 45 of 60 | February 2010

ADSP-21160M/ADSP-21160N

JTAG Test Access Port and Emulation

For JTAG Test Access Port and emulation, see

Table 36

and

Figure 28 .

Table 36. JTAG Test Access Port and Emulation

Parameter

t

Timing Requirements

TCK t

STAP t

HTAP t

SSYS t

HSYS t

TRSTW

TCK Period

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low

System Inputs Hold After TCK Low

TRST Pulsewidth

1

1

Min

6

7 t

CK

5

18

4t

CK

Max Unit

ns ns ns ns ns ns t t

Switching Characteristics

DTDO

DSYS

TDO Delay from TCK Low

System Outputs Delay After TCK Low

2

13

30 ns ns

1

System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, PA, BRST, DR0, DR1,

TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, and RESET.

2

System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP,

DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, and BMS.

t

TCK t

STAP t

HTAP

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS t

DTDO t

DSYS t

SSYS t

HSYS

Figure 28. JTAG Test Access Port and Emulation

Rev. B | Page 46 of 60 | February 2010

OUTPUT DRIVE CURRENTS—ADSP-21160M

Figure 29 shows typical I–V characteristics for the output driv-

ers of the ADSP-21160M. The curves represent the current drive capability of the output drivers as a function of output voltage.

120

100

80

60

40

20

0

V

DDEXT

= 3.47V, 0°C

V

DDEXT

= 3.3V, 25°C

V

DDEXT

–20

–40

–60

–80

–100

–120

0

V

DDEXT

= 3.47V, 0°C

V

DDEXT

= 3.3V, 25°C

V

DDEXT

= 3.13V,

85°C

0.5

1 1.5

2 2.5

SOURCE (V

DDEXT

) VOLTAGE – V

= 3.13V,

85°C

3 3.5

Figure 29. ADSP-21160M Typical Drive Currents

OUTPUT DRIVE CURRENTS—ADSP-21160N

Figure 30 shows typical I–V characteristics for the output driv-

ers of the ADSP-21160N. The curves represent the current drive capability of the output drivers as a function of output voltage.

80

60

V

DDEXT

= 3.47V, –45°C

V

DDEXT

= 3.3V, 25°C

40

V

OH

20 V

DDEXT

= 3.11V, 115°C

0

–20

V

OL

V

DDEXT

= 3.11V, 115°C

V

DDEXT

= 3.3V, 25°C

–40

–60

–80

0 0.5

1 1.5

V

DDEXT

2

= 3.47V, –45°C

2.5

SWEEP (V

DDEXT

) VOLTAGE – V

3 3.5

Figure 30. ADSP-21160N Typical Drive Currents

POWER DISSIPATION

Total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers.

ADSP-21160M/ADSP-21160N

Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Using the current specifications (I

DD-INPEAK

, I

DD-INHIGH

, I

DD-INLOW

, and

I

DD-IDLE

) from

Electrical Characteristics—ADSP-21160M on

Page 16

and Electrical Characteristics—ADSP-21160N on

Page 18

and the current-versus-operation information in

Table 37

, engineers can estimate the ADSP-21160x DSP’s internal power supply (V

DDINT

) input current for a specific application, according to the formula:

% Peak × I

DD

-

INPEAK

% High × I

DD

-

INHIGH

% Low × I

DD

-

INLOW

+ % Peak × I

DD

-

IDLE

= I

DDINT

The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on:

• The number of output pins that switch during each cycle (O)

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

• Their voltage swing (V

DD

) and is calculated by:

P

EXT

= O × C × V

DD

2

× f

The load capacitance should include the processor’s package capacitance (C

IN

). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2t

CK

). The write strobe can switch every cycle at a frequency of 1/t

CK

. Select pins switch at 1/(2t

CK

), but selects can switch on each cycle.

Example for ADSP-21160N: Estimate P

EXT

with the following assumptions:

• A system with one bank of external data memory— asynchronous RAM (64-bit)

• Four 64K × 16 RAM chips are used, each with a load of 10 pF

• External data memory writes occur every other cycle, a rate of 1/(2 t

CK

), with 50% of the pins switching

• The bus cycle time is 50 MHz (t

CK

= 20 ns).

The P

EXT

equation is calculated for each class of pins that can drive, as shown in

Table 38 .

A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation:

P

TOTAL

= P

EXT

+ P

INT

+ P

PLL where:

• P

EXT

is from

Table 38

• P

INT

is I

DDINT

× 1.9 V, using the calculation I

DDINT

listed in

Power Dissipation on page

47

• P

PLL

is AI

DD

× 1.9 V, using the value for AI

DD

listed in

Electrical Characteristics—ADSP-21160M on Page 16 and

Electrical Characteristics—ADSP-21160N on Page 18

Rev. B | Page 47 of 60 | February 2010

ADSP-21160M/ADSP-21160N

Table 37. ADSP-21160x Operation Types vs. Input Current

Operation

Instruction Type

Instruction Fetch

Core Memory Access

2

Internal Memory DMA

External Memory DMA

Data Bit Pattern for Core

Memory Access and DMA

Peak Activity

1

Multifunction

Cache

2 per t

CK

Cycle

(DM ⴛ 64 and PM ⴛ 64)

1 per 2 t

CCLK

1 per External Port Cycle (ⴛ64)

Worst Case

Cycles

High Activity

Multifunction

Internal Memory

1 per t

CK

Cycle

(DM ⴛ 64)

1 per 2 t

CCLK

Cycles

1 per External Port Cycle (ⴛ 64)

Random

1

Low Activity

Single Function

Internal Memory

None

None

None

N/A

1

2

1

Peak activity = I

DD-INPEAK

, high activity = I

DD-INHIGH

, and low activity = I

DD-INLOW

. The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.

These assume a 2:1 core clock ratio. For more information on ratios and clocks (t

CK

and t

CCLK

), see the timing ratio definitions on page 20

.

Table 38. External Power Calculations (ADSP-21160N Example)

Pin Type

Address

MS0

WRx

No. of Pins

15

1

2

% Switching

50

0

× C

× 44.7 pF

× 44.7 pF

× 44.7 pF

× f

× 24 MHz

× 24 MHz

× 24 MHz

Data

CLKOUT

64

1

50 × 14.7 pF

× 4.7 pF

× 24 MHz

× 48 MHz

P

EXT

× V

DD

2

× 10.9 V

× 10.9 V

× 10.9 V

× 10.9 V

× 10.9 V

= P

EXT

= 0.088 W

= 0.000 W

= 0.023 W

= 0.123 W

= 0.003 W

= 0.237 W voltage decays ΔV from the measured output high or output low voltage. t

DECAY

is calculated with test loads C

L

and I

L

, and with

Δ V equal to 0.5 V.

Note that the conditions causing a worst-case P

EXT

are different from those causing a worst-case P

INT

. Maximum P

INT

cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.

TEST CONDITIONS

The test conditions for timing parameters appearing in

ADSP-21160x specifications on page

17

include output disable time, output enable time, and capacitive loading.

Output Disable Time

Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ΔV is dependent on the capacitive load, C

L

and the load current, I

L

. This decay time can be approximated by the following equation:

t

DECAY

= (C

L

Δ V)/I

L

The output disable time t

DIS

is the difference between t

MEASURED and t

DECAY

as shown in

Figure 31 . The time t

MEASURED

is the interval from when the reference signal switches to when the output

REFERENCE

SIGNAL

V

OH

(MEASURED) t

DIS

V

OL

(MEASURED) t

MEASURED

V

OH

(MEASURED) –

$V

2.0V

V

OL

(MEASURED) +

$V

1.0V

t

DECAY

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS VOLTAGE

TO BE APPROXIMATELY 1.5V

Figure 31. Output Enable/Disable

t

ENA

Rev. B | Page 48 of 60 | February 2010

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time t

ENA

is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown

in the output enable/disable diagram ( Figure 31 ). If multiple

pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular system, first calculate t

DECAY

using the equation given above. Choose ΔV to be the difference between the ADSP-21160x DSP’s output voltage and the input threshold for the device requiring the hold time. A typical ΔV will be 0.4 V. C

L

is the total bus capacitance

(per data line), and I

L

is the total leakage or three-state current

(per data line). The hold time will be t

DECAY

plus the minimum disable time (i.e., t

DATRWH

for the write cycle).

50

6

TO

OUTPUT

PIN

1.5V

30pF

Figure 32. Equivalent Device Loading for AC Measurements (Includes All

Fixtures)

INPUT

OR

OUTPUT

1.5V

1.5V

Figure 33. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

ADSP-21160M/ADSP-21160N

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 32 ). Figure 34 , Figure 35

, Figure 37

,

and Figure 38

show how output rise time varies with capaci-

tance. Figure 36 and Figure 39

graphically show how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see

Output Disable Time on Page 48

.) The graphs of

Figure 37

,

Figure 38

,

Figure 39 ,

Figure 40 ,

Figure 41

, and Figure 42

may not be linear outside the ranges shown.

30

25

20

RISE TIME

Y = 0.086687X

+ 2.18

15

10

FALL TIME

Y = 0.072781X

+ 1.99

5

0

0 50 100 150

LOAD CAPACITANCE – pF

200

Figure 34. ADSP-21160M Typical Output Rise Time (10%–90%, V

DDEXT

= Max) vs. Load Capacitance

25

20

15

10

5

RISE TIME

Y = 0.0813x

+ 2.312

TBD

FALL TIME

Y = 0.0834x

+ 1.0653

0

0 50 100 150

LOAD CAPACITANCE – pF

200 250

Figure 35. ADSP-21160M Typical Output Rise Time (10%–90%, V

DDEXT

= Min) vs. Load Capacitance

Rev. B | Page 49 of 60 | February 2010

ADSP-21160M/ADSP-21160N

20

15

10

5

Y = 0.085526X

– 3.87

0

–5

0 50 100 150

LOAD CAPACITANCE – pF

200

Figure 36. ADSP-21160M Typical Output Delay or Hold vs. Load Capacitance

(at Max Case Temperature)

14

12

10

8

6

4

2

20

18

16

0

0

Y = 0.0716x

+ 2.9043

RISE TIME

FALL TIME

Y = 0.0751x

+ 1.4882

50 100 150

LOAD CAPACITANCE – pF

200

Figure 37. ADSP-21160N Typical Output Rise Time (20%–80%, V

DDEXT

= Max) vs. Load Capacitance

25

20

15

10

5

RISE TIME

Y = 0.0813x

+ 2.312

FALL TIME

Y = 0.0834x

+ 1.0653

0

0 50 100 150

LOAD CAPACITANCE – pF

200

Figure 38. ADSP-21160N Typical Output Rise Time (20%–80%, V

DDEXT

= Min) vs. Load Capacitance

12

10

8

0

–2

–4

0

6

4

2

Y = 0.0716x

– 3.9037

50 100

LOAD CAPACITANCE – pF

150 200

Figure 39. ADSP-21160N Typical Output Delay or Hold vs. Load Capacitance

(at Max Case Temperature)

Rev. B | Page 50 of 60 | February 2010

ENVIRONMENTAL CONDITIONS

Thermal Characteristics

The ADSP-21160x DSPs are provided in a 400-Ball PBGA (Plastic Ball Grid Array) package.

The ADSP-21160x is specified for a case temperature (T

CASE

).

To ensure that the T

CASE

data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. Use the centerblock of ground pins (for ADSP-21160M, PBGA balls:

H8-13, J8-13, K8-13, L8-13, M8-13, N8-13; for ADSP-21160N,

PBGA balls: F7-14, G7-14, H7-14, J7-14, K7-14, L7-14, M-14,

N7-14, P7-14, R7-15) to provide thermal pathways to the printed circuit board’s ground plane. A heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive.

T

CASE

=

T

AMB

+

( PD × θ

CA

)

• T

CASE

= Case temperature (measured on top surface of package)

• PD = Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation).

• θ

CA

= Value from

Table 39

.

• θ

JB

= 6.46°C/W

Table 39. Airflow Over Package Versus θ

CA

Airflow (Linear Ft./Min.)

θ

CA

(°C/W)

1

1

θ

JC

= 3.6 °C/W

0

12.13

200

9.86

400

8.7

ADSP-21160M/ADSP-21160N

Rev. B | Page 51 of 60 | February 2010

ADSP-21160M/ADSP-21160N

400-BALL PBGA PIN CONFIGURATIONS

Table 40 lists the pin assignments for the PBGA package, and

the pin configurations diagram in

Figure 40

(ADSP-21160M) and

Figure 41 (ADSP-21160N) show the pin assignment

summary.

Table 40. 400-Ball PBGA Pin Assignments

NC

TFS1

RFS1

RCLK0

DT0

L0DAT[4]

DATA[30]

DATA[29]

DATA[23]

DATA[21]

V

DDEXT

V

DDINT

V

DDINT

V

DDINT

V

DDINT

V

DDINT

GND

V

DDINT

V

DDINT

V

DDINT

V

DDINT

V

DDEXT

L1DAT[6]

L1DAT[5]

L1ACK

L1DAT[1]

Pin Name

DATA[14]

DATA[13]

DATA[10]

DATA[8]

DATA[4]

DATA[2]

TDI

TRST

RESET

RPBA

IRQ0

FLAG1

TIMEXP

NC

1

E07

E08

E09

E10

E03

E04

E05

E06

A15

A16

A17

A18

A19

A20

E01

E02

E15

E16

E17

E18

E11

E12

E13

E14

E19

E20

A07

A08

A09

A10

A11

A12

A13

A14

Pin No.

A01

A02

A03

A04

A05

A06

DT1

RCLK1

RFS0

TCLK0

L0DAT[5]

L0DAT[2]

DATA[34]

DATA[33]

DATA[27]

DATA[26]

V

DDEXT

V

DDINT

GND

GND

GND

GND

GND

GND

GND

GND

V

DDINT

V

DDEXT

L1DAT[4]

L1DAT[3]

L1DAT[0]

L2DAT[7]

Pin Name

DATA[22]

DATA[16]

DATA[15]

DATA[9]

DATA[6]

DATA[3]

DATA[0]

TCK

EMU

IRQ2

FLAG3

FLAG0

NC

1

NC

(See Footnotes 1 and 2)

F03

F04

F05

F06

F07

F08

F09

F10

B19

B20

F01

F02

B15

B16

B17

B18

F15

F16

F17

F18

F11

F12

F13

F14

F19

F20

B07

B08

B09

B10

B11

B12

B13

B14

Pin No.

B01

B02

B03

B04

B05

B06

GND

GND

GND

GND

GND

GND

V

DDINT

V

DDEXT

L1DAT[2]

L2DAT[6]

L2DAT[4]

L2CLK

L0DAT[7]

L0DAT[6]

L0ACK

L0DAT[0]

DATA[38]

DATA[35]

DATA[32]

DATA[31]

V

DDEXT

V

DDINT

GND

GND

Pin Name

DATA[24]

DATA[18]

DATA[17]

DATA[11]

DATA[7]

DATA[5]

DATA[1]

TMS

TD0

IRQ1

FLAG2

NC

1

NC

TCLK1

DR1

DR0

Rev. B | Page 52 of 60 | February 2010

G03

G04

G05

G06

G07

G08

G09

G10

C15

C16

C17

C18

C19

C20

G01

G02

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

C07

C08

C09

C10

C11

C12

C13

C14

Pin No.

C01

C02

C03

C04

C05

C06

GND

GND

GND

GND

GND

GND

V

DDINT

V

DDEXT

L2DAT[5]

L2ACK

L2DAT[3]

L2DAT[1]

L0CLK

L0DAT[3]

L0DAT[1]

L1CLK

DATA[40]

DATA[39]

DATA[37]

DATA[36]

V

DDEXT

V

DDINT

GND

GND

Pin Name

DATA[28]

DATA[25]

DATA[20]

DATA[19]

DATA[12]

V

DDEXT

V

DDINT

V

DDEXT

V

DDEXT

V

DDEXT

V

DDEXT

V

DDEXT

V

DDINT

V

DDEXT

TFS0

L1DAT[7]

H03

H04

H05

H06

H07

H08

H09

H10

D15

D16

D17

D18

D19

D20

H01

H02

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

D07

D08

D09

D10

D11

D12

D13

D14

Pin No.

D01

D02

D03

D04

D05

D06

ADSP-21160M/ADSP-21160N

Pin No.

N05

N06

N07

N08

N09

N10

N11

N12

J17

J18

J19

J20

N01

N02

N03

N04

J13

J14

J15

J16

J09

J10

J11

J12

J05

J06

J07

J08

J01

J02

J03

J04

U01

U02

U03

U04

U05

U06

N13

N14

N15

N16

N17

N18

N19

N20

Pin Name

GND

GND

V

DDINT

V

DDEXT

L3DAT[2]

L3DAT[1]

L3DAT[3]

L3ACK

ADDR[4]

ADDR[6]

ADDR[7]

ADDR[10]

ADDR[14]

ADDR[18]

DATA[52]

DATA[55]

V

DDEXT

V

DDINT

GND

GND

GND

GND

GND

GND

CLK_CFG_0

DATA[46]

DATA[45]

DATA[47]

V

DDEXT

V

DDINT

GND

GND

GND

GND

GND

GND

GND

GND

V

DDINT

V

DDEXT

BR6

BR5

BR4

BR3

DATA[49]

DATA[50]

Pin Name

GND

GND

V

DDINT

V

DDEXT

L3DAT[5]

L3DAT[6]

L3DAT[4]

L3CLK

DATA[61]

DATA[62]

ADDR[3]

ADDR[2]

V

DDEXT

V

DDEXT

DATA[48]

DATA[51]

V

DDEXT

V

DDINT

GND

GND

GND

GND

GND

GND

DATA[44]

DATA[43]

DATA[42]

DATA[41]

V

DDEXT

V

DDINT

GND

GND

GND

GND

GND

GND

GND

GND

V

DDINT

V

DDEXT

L2DAT[2]

L2DAT[0]

HBG

HBR

NC

NC

Table 40. 400-Ball PBGA Pin Assignments (Continued)

(See Footnotes 1 and 2)

Pin No.

Pin Name

P09

P10

P11

P12

P05

P06

P07

P08

P01

P02

P03

P04

K17

K18

K19

K20

K13

K14

K15

K16

K09

K10

K11

K12

K01

K02

K03

K04

K05

K06

K07

K08

V01

V02

V03

V04

V05

V06

P17

P18

P19

P20

P13

P14

P15

P16

GND

GND

GND

V

DDEXT

L4DAT[5]

L4DAT[6]

L4DAT[7]

L3DAT[0]

ADDR[5]

ADDR[9]

ADDR[12]

ADDR[15]

ADDR[17]

ADDR[20]

DATA[57]

DATA[60]

V

DDEXT

V

DDINT

GND

GND

GND

GND

GND

GND

CLKIN

CLK_CFG_1

AGND

CLK_CFG_2

V

DDEXT

V

DDINT

GND

GND

GND

GND

GND

GND

GND

GND

V

DDINT

V

DDEXT

BR2

BR1

ACK

REDY

DATA[53]

DATA[54]

Rev. B | Page 53 of 60 | February 2010

Pin No.

R09

R10

R11

R12

R05

R06

R07

R08

R01

R02

R03

R04

L17

L18

L19

L20

L13

L14

L15

L16

L09

L10

L11

L12

L05

L06

L07

L08

L01

L02

L03

L04

W01

W02

W03

W04

W05

W06

R17

R18

R19

R20

R13

R14

R15

R16

Pin Name

AV

DD

CLK_CFG_3

CLKOUT

NC

2

V

DDEXT

V

DDINT

GND

GND

GND

GND

GND

GND

GND

GND

V

DDINT

V

DDEXT

PAGE

SBTS

PA

L3DAT[7]

DATA[56]

DATA[58]

DATA[59]

DATA[63]

V

DDEXT

V

DDINT

V

DDINT

V

DDINT

V

DDINT

V

DDINT

V

DDINT

V

DDINT

V

DDINT

V

DDINT

V

DDINT

V

DDEXT

L4DAT[3]

L4ACK

L4CLK

L4DAT[4]

ADDR[8]

ADDR[11]

ADDR[13]

ADDR[16]

ADDR[19]

ADDR[21]

Pin No.

T09

T10

T11

T12

T05

T06

T07

T08

T01

T02

T03

T04

M17

M18

M19

M20

M09

M10

M11

M12

M13

M14

M15

M16

M01

M02

M03

M04

M05

M06

M07

M08

Y01

Y02

Y03

Y04

Y05

Y06

T17

T18

T19

T20

T13

T14

T15

T16

ADSP-21160M/ADSP-21160N

Table 40. 400-Ball PBGA Pin Assignments (Continued)

Pin Name

V

DDEXT

V

DDEXT

V

DDEXT

V

DDEXT

V

DDEXT

V

DDEXT

V

DDEXT

V

DDEXT

V

DDEXT

V

DDEXT

L5DAT[7]

L4DAT[0]

L4DAT[1]

L4DAT[2]

Pin No.

U15

U16

U17

U18

U19

U20

U07

U08

U09

U10

U11

U12

U13

U14

Pin Name

ADDR[22]

ADDR[25]

ADDR[28]

ID0

ADDR[1]

MS1

CS

RDL

DMAR2

L5DAT[0]

L5DAT[2]

L5ACK

L5DAT[4]

L5DAT[6]

(See Footnotes 1 and 2)

Pin No.

V15

V16

V17

V18

V19

V20

V07

V08

V09

V10

V11

V12

V13

V14

Pin Name

ADDR[23]

ADDR[26]

ADDR[29]

ID1

ADDR[0]

BMS

MS2

CIF

RDH

DMAG2

LBOOT

L5DAT[1]

L5DAT[3]

L5DAT[5]

Pin No.

W15

W16

W17

W18

W19

W20

W07

W08

W09

W10

W11

W12

W13

W14

1

For ADSP-21160M, Pin Name and function is defined as V

DDEXT

. For ADSP-21160N, Pin Name and function is defined as No Connect (NC).

2

For ADSP-21160N, Pin Name and function is defined as GND. For ADSP-21160M, Pin Name and function is defined as No Connect (NC).

Pin Name

ADDR[24]

ADDR[27]

ADDR[30]

ADDR[31]

ID2

BRST

MS0

MS3

WRH

WRL

DMAG1

DMAR1

EBOOT

L5CLK

Pin No.

Y15

Y16

Y17

Y18

Y19

Y20

Y11

Y12

Y13

Y14

Y07

Y08

Y09

Y10

Rev. B | Page 54 of 60 | February 2010

ADSP-21160M/ADSP-21160N

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

KEY:

V

DDINT

V

DDEXT

GND

AGND

1

AV

DD

I/O SIGNALS

NO CONNECTION

1

USE THE CENTER BLOCK OF GROUND PINS (PBGA BALLS: H8-13, J8-13, K8-13, L8-13,

M8-13, N8-13) TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S

GROUND PLANE.

Figure 40. ADSP-21160M 400-Ball PBGA Pin Configurations (Bottom View, Summary)

M

N

P

R

T

G

H

J

K

L

U

V

W

Y

C

D

E

F

A

B

Rev. B | Page 55 of 60 | February 2010

ADSP-21160M/ADSP-21160N

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

KEY:

V

DDINT

V

DDEXT

GND

AGND

1

AV

DD

I/O SIGNALS

NO CONNECTION

1

USE THE CENTER BLOCK OF GROUND PINS (PBGA BALLS: F7-14, G7-14, H7-14, J7-14,

K7-14, L7-14, M7-14, N7-14, P7-14, R7-15) TO PROVIDE THERMAL PATHWAYS TO YOUR

PRINTED CIRCUIT BOARD’S GROUND PLANE.

Figure 41. ADSP-21160N 400-Ball PBGA Pin Configurations (Bottom View, Summary)

C

D

E

A

B

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

Rev. B | Page 56 of 60 | February 2010

ADSP-21160M/ADSP-21160N

OUTLINE DIMENSIONS

The ADSP-21160x processors are available in a

27 mm ⴛ 27 mm, 400-ball PBGA lead-free package.

BALL A1

INDICATOR

2.49

2.32

2.15

27.20

27.00

26.80

SQ

TOP VIEW

24.13

BSC

SQ

DETAIL A

1.27

BSC

0.60

0.55

0.50

BALL A1 PAD CORNER

20 18

19 17

16 14

15 13

12

11

10

9

8

7

6

5

4

3

2

1

K

L

M

N

P

R

T

U

V

W

Y

A

B

C

D

E

F

G

H

J

BOTTOM VIEW

1.19

1.17

1.15

SEATING

PLANE

0.90

0.75

0.60

BALL DIAMETER

DETAIL A

0.70

0.60

0.50

0.20 MAX

COPLANARITY

Figure 42. 400-Ball Plastic Grid Array (PBGA) (B-400) Compliant to JEDEC Standards MS-034-BAL-2 (Dimensions in Millimeters)

SURFACE-MOUNT DESIGN

The following table is provided as an aide to PCB design.

For industry-standard design recommendations, refer to

IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard.

Package

400-Ball Grid Array (PBGA)

Ball Attach Type

Solder Mask Defined (SMD)

Solder Mask Opening

0.63 mm diameter

Ball Pad Size

0.76 mm diameter

Rev. B | Page 57 of 60 | February 2010

ADSP-21160M/ADSP-21160N

ORDERING GUIDE

Model

1

ADSP-21160MKBZ-80

ADSP-21160MKB-80

ADSP-21160NCBZ-100

ADSP-21160NCB-100

ADSP-21160NKBZ-100

ADSP-21160NKB-100

1

Z = RoHS compliant part.

Temperature Range

0°C to +85°C

0°C to +85°C

–40°C to +100°C

–40°C to +100°C

0°C to +85°C

0°C to +85°C

Instruction

Rate

80 MHz

80 MHz

100 MHz

100 MHz

100 MHz

100 MHz

On-Chip

SRAM

4M bits

4M bits

4M bits

4M bits

4M bits

4M bits

Package Description

400-Ball Plastic Ball Grid Array (PBGA)

400-Ball Plastic Ball Grid Array (PBGA)

400-Ball Plastic Ball Grid Array (PBGA)

400-Ball Plastic Ball Grid Array (PBGA)

400-Ball Plastic Ball Grid Array (PBGA)

400-Ball Plastic Ball Grid Array (PBGA)

Package

Option

B-400

B-400

B-400

B-400

B-400

B-400

Rev. B | Page 58 of 60 | February 2010

Rev. B | Page 59 of 60 | February 2010

ADSP-21160M/ADSP-21160N

ADSP-21160M/ADSP-21160N

©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D02426-0-2/10(B)

Rev. B | Page 60 of 60 | February 2010

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