datasheet for EN6347QI by Altera

datasheet for EN6347QI by Altera
Enpirion® Power Datasheet
EN6347QI 4A PowerSoC
Voltage Mode Synchronous
Buck PWM DC-DC Converter
with Integrated Inductor
De sc ript ion
Fe a t ure s
The EN6347QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates
MOSFET
switches,
small-signal
circuits,
compensation, and the inductor in an advanced
4mm x 7mm QFN package.
The EN6347QI is specifically designed to meet
the
precise voltage and fast transient
requirements of present and future highperformance, low-power processor, DSP, FPGA,
memory boards and system level applications in
distributed power architecture.
The device’s
advanced circuit techniques, ultra high switching
frequency, and proprietary integrated inductor
technology deliver high-quality, ultra compact,
non-isolated DC-DC conversion.
The Altera Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified
board
design,
layout
and
manufacturing requirements. In addition, a
reduction in the number of vendors required for
the complete power solution helps to enable an
overall system cost savings.
All Altera Enpirion products are RoHS compliant
and
lead-free
manufacturing
environment
compatible.
•
Integrated Inductor, MOSFETS, Controller
•
Minimal external components.
•
Up to 4A Continuous Output Current
Capability.
•
3 MHz operating frequency. Switching
frequency can be phase locked to an external
clock.
•
High efficiency, up to 95%.
•
Wide input voltage range of 2.5V to 6.6V.
•
Light Load Mode with programmable set
point.
•
Output Enable pin and Power OK signal.
•
Programmable soft-start time.
•
Under Voltage Lockout, Over Current, Short
Circuit and Thermal Protection.
•
RoHS compliant, MSL level 3, 260C reflow.
RA 0402
RB 0402
Applic a t ion
•
Point of load regulation for processors, DSPs,
FPGAs, and ASICs
•
Noise sensitive applications such as A/V, RF
and Gbit I/O
•
Low voltage, distributed power architectures
such as 0.8V, 1.0V, 1.2, 2.5V, 3.3V, 5V rails
•
Blade servers, RAID storage systems,
Css 0402
CA 0402
EN6347QI
LAN/SAN adapter cards, wireless base
stations, industrial automation, test and
Output Cap
47uF /1206
measurement, embedded computing,
Input Cap
22uF/1206
communications, and multi-function printers.
Figure 1: Total Solution Footprint PWM mode
(Not to scale) Total Area ≈ 75 mm 2
•
Ripple sensitive applications
•
Beat frequency sensitive applications
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VOUT
2
NC
3
NC
4
VOUT
VOUT
Part Number
EN6347QI
EVB-EN6347QI
Temp Rating
(°C)
Package
-40 to +85
38-pin QFN T&R
QFN Evaluation Board
NC(SW)
NC(SW)
NC(SW)
AVIN
AGND
VFB
SS
RLLM
POK
ENABLE
LLM/
SYNC
NC(SW)
32
31
30
29
28
27
26
25
NC
24
NC
23
NC
22
NC
5
21
PVIN
6
20
PVIN
39
PGND
7
8
9
10
11
12
13
14
15
16
17
18
19
PGND
PGND
PVIN
EN6347QI
PGND
Orde ring I nform a t ion
33
PGND
Figure 2: Typical Application Schematic (PWM mode)
34
PGND
CSS
35
PGND
RB
1
NC(SW)
36
VOUT
LLM/SYNC
NC(SW)
37
NC(SW)
AGND
1206
PGND
SS
38
47µF
VOUT
PGND
CA
VFB
VOUT
1206
RA
VOUT
AVIN
22µF
NC(SW)
ENA
Pin Assignm e nt s (T op V ie w )
VOUT
VOUT
PVIN
EN6347QI
VIN
Figure 3: Pinout Diagram (Top View)
NOTE: All pins must be soldered to PCB.
Pin De sc ript ion
PIN
NAME
1-2, 12,
34-38
NC(SW)
3-4,
22-25
NC
5-11
VOUT
13-18
PGND
19-21
PVIN
26
LLM/SYNC
27
ENABLE
28
POK
29
RLLM
30
SS
31
VFB
32
33
AGND
AVIN
39
PGND
FUNCTION
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground,
or voltage. Failure to follow this guideline may result in damage to the device.
NO CONNECT – These pins may be internally connected. Do not connect to each other or
to any other electrical signal. Failure to follow this guideline may result in device damage.
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 13-15.
Input/Output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND pins 16-18.
Dual function pin providing LLM Enable and External Clock Synchronization (see
Application Section). At static Logic HIGH, device will allow automatic engagement of light
load mode. At static logic LOW, the device is forced into PWM only. A clocked input to this
pin will synchronize the internal switching frequency to the external signal. If this pin is left
floating, it will pull to a static logic high, enabling LLM.
Input Enable. Applying logic high enables the output and initiates a soft-start. Applying
logic low disables the output.
Power OK is an open drain transistor used for power system state indication. POK is logic
high when VOUT is within -10% of VOUT nominal.
Programmable LLM engage resistor to AGND allows for adjustment of load current at which
Light-Load Mode engages. Can be left open for PWM only operation.
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The
value of this capacitor determines the startup time.
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The midpoint of the divider is connected to VFB. A
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.
Analog Ground. This is the controller ground return. Connect to a quiet ground.
Input power supply for the controller. Connect to input voltage at a quiet point.
Device thermal pad to be connected to the system GND plane. See Layout
Recommendations section.
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Absolut e M a x im um Ra t ings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the
recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may
impair device life. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
-0.5
7.0
V
Pin Voltages – ENABLE, POK, LLM/SYNC
-0.5
VIN +0.3
V
Pin Voltages – VFB, SS, RLLM
-0.5
2.75
V
-65
150
°C
150
°C
260
°C
2000
V
Supply Voltage – PVIN, AVIN, VOUT
Storage Temperature Range
TSTG
Maximum Operating Junction Temperature
TJ-ABS Max
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating - all pins (based on HBM)
Re c om m e nded Ope ra t ing Condit ions
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
2.5
6.6
V
Operating Junction Temperature
TJ-OP
- 40
125
°C
Operating Ambient Temperature
TAMB
- 40
85
°C
260
°C
MAX
UNITS
Input Supply Voltage
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
T he rm a l Cha ra c t e rist ic s
PARAMETER
SYMBOL
MIN
TYP
Thermal Shutdown
TSD
160
°C
Thermal Shutdown Hysteresis
TSDH
35
°C
Thermal Resistance: Junction to Ambient (Note 1)
θJA
30
°C/W
Thermal Resistance: Junction to Case
θJC
3
°C/W
Note 1: Based on 2oz. external copper layers and proper thermal design in line with EIA/JEDEC JESD51-7
standard for high thermal conductivity boards.
Ele c t ric a l Cha ra c t e rist ics
NOTE: VIN=6.6V over operating temperature range unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
Operating Input Voltage
VIN
Under Voltage Lock-out –
VIN Rising
VUVLOR
Voltage above which UVLO is not
asserted
Under Voltage Lock-out –
VIN Falling
VUVLOF
Voltage below which UVLO is
asserted
TYP
2.5
3
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MIN
October 11, 2013
MAX
UNITS
6.6
V
2.3
V
2.075
V
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PARAMETER
SYMBOL
Shut-Down Supply Current
IS
ENABLE=0V
100
µA
Operating Quiescent
Current
IQ
LLM/SYNC = High
650
µA
Feedback Pin Voltage
EN6347QI
VFB
Feedback node voltage at:
VIN = 5V, ILOAD = 0, TA = 25°C
Feedback Pin Voltage
EN6347QI
VFB
Feedback node voltage at:
2.5V ≤ VIN ≤ 6.6V
0A ≤ ILOAD ≤ 4A, TA = -40 to 85°C
Feedback pin Input
Leakage Current (Note 1)
IFB
VFB pin input leakage current
tRISE
Measured from when VIN > VUVLOR &
ENABLE pin voltage crosses its
logic high threshold to when VOUT
reaches its final value. CSS = 15 nF
VOUT Rise Time (Note 1)
TEST CONDITIONS
Soft Start Capacitor Range CSS_RANGE
Output Drop Out
Voltage
Resistance (Note 1)
VDO
RDO
MIN
TYP
MAX
UNITS
V
0.7425
0.75
0.7575
0.735
0.75
0.765
V
5
nA
1.5
ms
68
nF
360
90
mV
mΩ
4
4
A
-5
0.9
1.2
10
VINMIN - VOUT at Full load
Input to Output Resistance
240
60
Continuous Output Current IOUT
PWM mode
LLM mode (Note 2)
0
0.002
Over Current Trip Level
IOCP
VIN = 5V, VOUT = 1.2V
Disable Threshold
VDISABLE
ENABLE pin logic low.
0.0
0.6
V
ENABLE Threshold
VENABLE
ENABLE pin logic high
2.5V ≤ VIN ≤ 6.6V
1.8
VIN
V
ENABLE Lockout Time
TENLOCKOUT
ENABLE pin Input Current
(Note 1)
IENABLE
6.5
ENABLE pin has ~180kΩ pull down
A
3.2
ms
40
µA
3
MHz
Switching Frequency (Free
FSW
Running)
Free Running frequency of
oscillator
External SYNC Clock
Frequency Lock Range
FPLL_LOCK
Range of SYNC clock frequency
SYNC Input Threshold –
Low (LLM/SYNC PIN)
VSYNC_LO
SYNC Clock Logic Level
SYNC Input Threshold –
High (LLM/SYNC PIN)
VSYNC_HI
SYNC Clock Logic Level - (Note 3)
POK Lower Threshold
POKLT
Output voltage as a fraction of
expected output voltage
POK Output low Voltage
VPOKL
With 4mA current sink into POK
0.4
V
POK Output Hi Voltage
VPOKH
2.5V ≤ VIN ≤ 6.6V
VIN
V
POK pin VOH leakage
current (Note 1)
IPOKL
POK high
1
µA
1.8
LLM Logic Low
(LLM/SYNC PIN)
VLLM_LO
LLM Static Logic Level
LLM Logic High
(LLM/SYNC PIN)
VLLM_HI
LLM Static Logic Level
4
October 11, 2013
3.5
MHz
0.8
V
2.5
V
90
Minimum VIN-VOUT to ensure proper
LLM operation
LLM Engage Headroom
05991
2.5
%
800
mV
0.3
1.5
V
V
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PARAMETER
SYMBOL
TEST CONDITIONS
LLM/SYNC Pin Current
MIN
LLM/SYNC Pin is <2.5V
TYP
MAX
<100
UNITS
nA
Note 1: Parameter guaranteed by design.
Note 2: LLM operation is normally only guaranteed above the minimum specified output current. Contact Power
Applications support for designs that need to operate at a lower IOUT.
Note 3: For proper operation of the synchronization circuit, the high-level amplitude of the SYNC signal should not be
above 2.5V.
T ypic a l Pe rform a nc e Cha ra c t e rist ics
PWM/LLM Efficiency vs. Load Performance at Vin=3.3V
PWM/LLM Efficiency vs. Load Performance at Vin=5V
100
100
95
95
90
90
85
85
Vout=3.3
Vout=2.5
80
Vout=1.8
75
Vout=1.2
70
Vout=1
Vout=1
65
Vout=1.2
60
Vout=1.8
70
Vout=1.2
Vout=1
65
Vout=1
60
Vout=1.2
Vout=1.8
Vout=2.5
Vout=3.3
55
Vout=2.5
55
50
#REF!
50
45
45
40
40
35
35
30
0.01
30
0.01
0.1
1
Vout=2.5
Vout=1.8
75
Efficiency (%)
Efficiency (%)
80
10
0.1
Efficiency VIN = 3.3V, VOUT (From top to bottom) =
2.5, 1.8, 1.2, 1.0V
10
Efficiency VIN = 5.0V, VOUT (From top to bottom) =
3.3, 2.5, 1.8, 1.2, 1.0V
500 MHz BW
20 MHz BW limit
PWM Output Ripple: VIN = 3.3V, VOUT = 1.0V, IOUT = 4A
CIN = 22µF, COUT = 47µF/1206 + 10uF/0805
PWM Output Ripple: VIN = 3.3V, VOUT = 1.0V, I OUT = 4A
CIN = 22µF, COUT = 47µF/1206 + 10uF/0805
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500 MHz BW
20 MHz BW limit
PWM Output Ripple: VIN = 5.0V, VOUT = 1.0V, IOUT = 4A
CIN = 22µF, COUT = 47µF/1206 + 10uF/0805
PWM Output Ripple: VIN = 5.0V, VOUT = 1.0V, IOUT = 4A
CIN = 22µF, COUT = 47µF/1206 + 10uF/0805
LLM Output Ripple: VIN = 5.0V, VOUT = 1.0V,
IOUT = 0.1A, CIN = 22µF, COUT = 2x47µF/1206
LLM Output Ripple: VIN = 5.0V, VOUT = 3.0V,
IOUT = 0.1A, CIN = 22µF, COUT = 2x47µF/1206
Load Transient: VIN = 5.0V, VOUT = 1.0V, LLM Enabled
Ch.1: VOUT, Ch.2: IOUT = 0.01↔ 4A
CIN = 22µF, COUT = 2x47µF/1206
Load Transient: VIN = 5.0V, VOUT = 3.0V, LLM Enabled
Ch.1: VOUT, Ch.2: IOUT = 0.01↔ 4A
CIN = 22µF, COUT = 2x47µF/1206
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PWM Load Transient: VIN = 5.0V, VOUT = 1.0V
Ch.1: VOUT, Ch.2: IOUT = 0↔ 4A
CIN = 22µF, COUT = 47µF/1206 + 10µF/0805
PWM Load Transient: VIN = 5.0V, VOUT = 3.0V
Ch.1: VOUT, Ch.2: IOUT = 0↔ 4A
CIN = 22µF, COUT = 47µF/1206 + 10µF/0805
Power Up/Down at No Load: VIN/VOUT = 5V/3.3V,
47nF soft-start capacitor, COUT ≈ 50µF
Ch.1: ENABLE, Ch. 2: VOUT, Ch. 3: POK, Ch.4: IOUT
Power Up/Down into 0.825Ω load: VIN/VOUT = 5V/3.3V,
47nF soft-start capacitor, COUT ≈ 50µF
Ch.1: ENABLE, Ch. 2: VOUT, Ch. 3: POK, Ch.4: IOUT
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Func t iona l Bloc k Dia gra m
RLLM
PVIN
UVLO
Thermal Limit
P-Drive
Current Limit
NC(SW)
VOUT
Mode
Logic
N-Drive
(-)
PWM
Comp
(+)
LLM/SYNC
PGND
Compensation
Network
PLL/Sawtooth
Generator
VFB
(-)
Error
Amp
(+)
Power
Good
Logic
ENABLE
SS
POK
AVIN
Soft Start
Voltage
Reference
Regulated
Voltage
AGND
Figure 4: Functional Block Diagram
Func t iona l De sc ript ion
Synchronous Buck Converter
The
EN6347QI
is
a
synchronous,
programmable power supply with integrated
power MOSFET switches and integrated
inductor. The nominal input voltage range is
2.5V to 6.6V. The output voltage is
programmed using an external resistor divider
network. The control loop is voltage-mode with
a type III compensation network. Much of the
compensation circuitry is internal to the device.
However, a phase lead capacitor is required
along with the output voltage feedback resistor
divider to complete the type III compensation
network. The device uses a low-noise PWM
topology and also integrates a unique light-load
mode (LLM) to improve efficiency at light
output load currents. LLM can be disabled with
05991
a logic pin. Up to 4A of continuous output
current can be drawn from this converter. The
3 MHz switching frequency allows the use of
small size input / output capacitors, and
enables wide loop bandwidth within a small
foot print.
Protection Features:
The power supply has the following protection
features:
•
Over-current protection (to protect the IC
from excessive load current)
•
Thermal shutdown with hysteresis.
•
Under-voltage lockout circuit to keep the
converter output off while the input voltage
is less than 2.3V.
8
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Additional Features:
•
The switching frequency can be phaselocked to an external clock to eliminate or
move beat frequency tones out of band.
•
Soft-start circuit, allowing controlled startup
when the converter is initially powered up.
The soft start time is programmable with an
appropriate choice of soft start capacitor.
•
Power good circuit indicating VOUT is
greater than 90% of programmed value as
long as the feedback loop is closed.
•
To maintain high efficiency at low output
current, the device incorporates automatic
light load mode operation.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device.
When the ENABLE pin is asserted (high) the
device will undergo a normal soft start. A logic
low on this pin will power the device down in a
controlled manner. From the moment ENABLE
goes low, there is a fixed lock out time before
the output will respond to the ENABLE pin reasserted (high). This lock out is activated for
even very short logic low pulses on the
ENABLE pin. See the Electrical Characteristics
Table for technical specifications for this pin.
LLM/SYNC Pin
This is a dual function pin providing LLM
Enable and External Clock Synchronization. At
static Logic HIGH, device will allow automatic
engagement of light load mode. At static logic
LOW, the device is forced into PWM only. A
clocked input to this pin will synchronize the
internal switching frequency – LLM mode is not
available if this input is clocked.. If this pin is
left floating, it will pull to a static logic high,
enabling LLM.
Frequency Synchronization
The switching frequency of the DC/DC
converter can be phase-locked to an external
clock source to move unwanted beat
frequencies out of band. To avail this feature,
the clock source should be connected to the
LLM/SYNC pin. An activity detector recognizes
the presence of an external clock signal and
automatically phase-locks the internal oscillator
to this external clock. Phase-lock will occur as
long as the clock frequency is in the range
specified in the Electrical Characteristics Table.
For proper operation of the synchronization
circuit, the high-level amplitude of the SYNC
signal should not be above 2.5V. Please note
LLM is not available when synchronizing to an
external frequency.
Spread Spectrum Mode
The external clock frequency may be swept
between the limits specified in the Electrical
Characteristics Table at repetition rates of up
to 10 kHz in order to reduce EMI frequency
components.
Soft-Start Operation
During Soft-start, the output voltage is ramped
up gradually upon start-up. The output rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin
(30) and the AGND pin (32).
Rise Time: TR ≈ (CSS* 80kΩ) ± 25%
During start-up of the converter, the reference
voltage to the error amplifier is linearly
increased to its final level by an internal current
source of approximately 10uA. Typical softstart rise time is ~3.8mS with SS capacitor
value of 47nF. The rise time is measured from
when VIN > VUVLOR and ENABLE pin voltage
crosses its logic high threshold to when VOUT
reaches its programmed value. Please note
LLM function is disabled during the soft-start
ramp-up time.
POK Operation
The POK signal is an open drain signal
(requires a pull up resistor to VIN or similar
voltage) from the converter indicating the
output voltage is within the specified range.
The POK signal will be logic high (VIN) when
the output voltage is above 90% of
programmed VOUT . If the output voltage goes
below this threshold, the POK signal will be
logic low.
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Light Load Mode (LLM) Operation
The EN6347QI uses a proprietary light load
mode to provide high efficiency at low output
currents. When the LLM/SYNC pin is high, the
device is in automatic LLM “Detection” mode.
When the LLM/SYNC pin is low, the device is
forced into PWM mode. In automatic LLM
“Detection” mode, when a light load condition
is detected, the device will:
(1) Step VOUT up by approximately 1.0%
above the nominal operating output
voltage setting, VNOM and as low as -0.5%
below VNOM , and then
(2) Shut down unnecessary circuitry, and then
(3) Monitor VOUT .
When VOUT falls below VNOM , the device will
repeat (1), (2), and (3). The voltage step up, or
pre-positioning, improves transient droop when
a load transient causes a transition from LLM
mode to PWM mode. If a load transient
occurs, causing VOUT to fall below the threshold
VMIN, the device will exit LLM operation and
begin normal PWM operation. Figure 5
demonstrates VOUT behavior during transition
into and out of LLM operation.
LLM
Ripple
VMAX
PWM
Ripple
VNOM
VOUT
VMIN
device will remain in PWM mode. If the load
current is below the LLM threshold, the device
will re-enter LLM operation. There may be a
small overshoot or undershoot in VOUT when
the device exits and re-enters LLM.
The load current at which the device will enter
LLM mode is a function of input and output
voltage, and the RLLM pin resistor. Contact
Power Applications
support for details
regarding the optimization of this resistor for
specific operating conditions. For PWM only
operation, the RLLM pin can be left open.
To ensure normal LLM operation, LLM mode
should be enabled and disabled with specific
sequencing. For applications with explicit LLM
pin control, enable LLM after VIN ramp up is
complete. For applications with only ENABLE
control, tie LLM to ENABLE; and enable the
device after VIN ramp up is complete. For
designs with ENABLE and LLM tied to VIN,
make sure the device soft-start time is longer
than the VIN ramp-up time. LLM will start
operating after the soft-start time is completed.
NOTE: For proper LLM operation the
EN6347QI requires a minimum difference
between VIN and VOUT , and a minimum LLM
load requirement as specified in the Electrical
Characteristics Table. For LLM designs
requiring lower voltage headroom or a lower
minimum load, contact Power Applications
support.
Over-Current Protection
Load
Step
IOUT
Figure 5. VOUT behavior in LLM operation.
Many multi-mode DCDC converters suffer from
a condition that occurs when the load current
increases only slowly so that there is no load
transient driving VOUT below the VMIN threshold.
In this condition, the device would never exit
LLM operation. This could adversely affect
efficiency and cause unwanted ripple. To
prevent this from occurring, the EN6347QI
periodically exits LLM mode into PWM mode
and measures the load current. If the load
current is above the LLM threshold current, the
The current limit function is achieved by
sensing the current flowing through the Power
PFET. When the sensed current exceeds the
over current trip point, both power FETs are
turned off for the remainder of the switching
cycle. If the over-current condition is removed,
the over-current protection circuit will enable
normal PWM operation. If the over-current
condition persists, the soft start capacitor will
gradually discharge causing the output voltage
to fall. When the OCP fault is removed, the
output voltage will ramp back up to the desired
voltage. This circuit is designed to provide high
noise immunity.
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Thermal Overload Protection
Compensation
Thermal shutdown circuit will disable device
operation when the Junction temperature
exceeds approximately 150ºC. After a thermal
shutdown
event,
when
the
junction
temperature drops by approx 20ºC, the
converter will re-start with a normal soft-start.
The EN6347QI uses a type 3 compensation
network. As noted earlier, a piece of the
compensation network is the phase lead
capacitor CA in Figure 6. This network is
optimized for use with about 50-100 F of
output capacitance and will provide wide loop
bandwidth and excellent transient performance
for most applications. Voltage mode operation
provides high noise immunity at light load.
Input Under-Voltage Lock-Out
Internal circuits ensure that the converter will
not start switching until the input voltage is
above the specified minimum voltage.
Hysteresis and input de-glitch circuits ensure
high noise immunity and prevent false UVLO
triggers.
In some applications modifications to the
compensation may be required. For more
information,
contact
Power
Applications
support.
Applic a t ion I nform a tion
The EN6347QI output voltage is programmed
using a simple resistor divider network. Figure
6 shows the resistor divider configuration.
VOUT
RA
CA = 10 pF
VFB
RB
Description
10µF, 10V, 10%
X7R, 1206
(2 capacitors needed)
22µF, 10V, 20%
X5R, 1206
(1 capacitor needed)
0.75 * RA
(VOUT − 0.75 V )
Figure 6: VOUT Resistor Divider &
Compensation Capacitor
An additional compensation capacitor CA is
also required in parallel with the upper resistor.
Input Capacitor Selection
The EN6347QI requires about 20uF of input
capacitance. Low-cost, low-ESR ceramic
capacitors should be used as input capacitors
for this converter. The dielectric must be X5R
or X7R rated. Y5V or equivalent dielectric
formulations must not be used as these lose
too much capacitance with frequency,
temperature and bias voltage. In some
applications, lower value capacitors are
needed in parallel with the larger, capacitors in
order to provide high frequency decoupling.
P/N
GRM31CR71A106KA01L
Taiyo Yuden
LMK316B7106KL-T
Murata
GRM31CR61A226ME19L
Taiyo Yuden
LMK316BJ226ML-T
The EN6347QI has been nominally optimized
for use with approximately 50-100 F of output
capacitance. Low ESR ceramic capacitors are
required with X5R or X7R rated dielectric
formulation.
Y5V or equivalent dielectric
formulations must not be used as these lose
too much capacitance with frequency,
temperature and bias voltage.
Output ripple voltage is determined by the
aggregate output capacitor impedance. Output
impedance, denoted as Z, is comprised of
effective series resistance, ESR, and effective
series inductance, ESL:
Z = ESR + ESL
Placing output capacitors in parallel reduces
the impedance and will hence result in lower
PWM ripple voltage. In addition, higher output
capacitance will improve overall regulation and
ripple in light-load mode.
1
1
1
1
=
+
+ ... +
Z Total Z 1 Z 2
Zn
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Output Capacitor Selection
RA = 200 kΩ
RB =
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Typical PWM Ripple Voltages
Output Capacitor
Configuration
Typical Output Ripple (mVp-p)
(as measured on EN6347QI
Evaluation Board)*
1 x 47 µF
25
47 µF + 10 µF
15
* Note: 20 MHz BW limit
Recommended Output Capacitors
Description
47µF, 6.3V, 20%
X5R, 1206
(1 or 2 capacitors needed)
10µF, 10V, 10%
X5R, 1206
(Optional 1 capacitor in
parallel with 47µF above)
MFG
P/N
Murata
GRM31CR60J476ME19L
Taiyo
Yuden
Murata
JMK316BJ476ML-T
Taiyo
Yuden
GRM31CR71A106KA01L
beyond the above recommendations can be
used on the output node of the EN6347QI as
long as the bulk capacitors are far enough from
the VOUT sense point such that they don’t
interfere with the control loop operation.
In some cases
modifications
to the
compensation or output filter capacitance may
be required to optimize device performance
such as transient response, ripple, or hold-up
time. The EN6347QI provides the capability to
modify the control loop response to allow for
customization for such applications. For more
information,
contact
Power
Applications
support.
LMK316BJ226ML-T
Power-Up Sequencing
For best LLM performance, we recommend
using just 2x47uF capacitors mentioned in the
above table, and no 10uF capacitor.
The VOUT sense point should be just after the
last output filter capacitor right next to the
device. Additional bulk output capacitance
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. Tying all three pins
together meets these requirements.
T he rm a l Conside ra t ions
The Altera Enpirion EN6347QI DC-DC
converter is packaged in a 7x4x1.85mm 38-pin
QFN package. The QFN package is
constructed with copper lead frames that have
exposed thermal pads. The recommended
maximum junction temperature for continuous
operation is 125°C. Continuous operation
above 125°C will reduce long -term reliability.
The device has a thermal overload protection
circuit designed to shut it off at a junction
temperature specified in the Electrical
Characteristics Table.
The silicon is mounted on a copper thermal
pad that is exposed at the bottom of the
package. The thermal resistance from the
silicon to the exposed thermal pad is very low.
In order to take advantage of this low
resistance, the exposed thermal pad on the
package should be soldered directly on to a
copper ground pad on the printed circuit board
(PCB). The PCB then acts as a heat sink. In
order for the PCB to be an effective heat sink,
the device thermal pad should be coupled to
copper ground planes or special heat sink
structures designed into the PCB (refer to the
Layout Recommendations section).
The junction temperature, TJ, is calculated from
the ambient temperature, TA, the device power
dissipation, PD, and the device junction-toambient thermal resistance, JA in °C/W, as
follows:
TJ = TA + (PD) ( JA)
The junction temperature, TJ, can also be
expressed in terms of the device case
temperature, TC, and the device junction-tocase thermal resistance, JC in °C/W, as
follows:
TJ = TC + (PD) ( JC)
The device case temperature, TC, is the
temperature at the center of the exposed
thermal pad at the bottom of the package.
The device junction-to-ambient and junction-tocase thermal resistances, JA and JC, are
shown in the Thermal Characteristics Table.
The JC is a function of the device and the QFN
package design. The JA is a function of JC
and the user’s system design parameters that
include the thermal effectiveness of the
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customer PCB and airflow.
The
value shown in the Thermal
JA
Characteristics table on page 3 is for free
convection with the device heat sunk (through
the thermal pad) to a copper plated four-layer
PC board with a full ground and a full power
plane
following
EIA/JEDEC
JESD51-7
Standard. The JA can be reduced with the use
of forced air convection. Because of the strong
dependence on the thermal effectiveness of
the PCB and the system design, the actual JA
value will be a function of the specific
application.
La yout Re c om m e ndat ions
Figure 7 shows critical components and layer 1
traces of a recommended minimum footprint
EN6347QI layout with ENABLE tied to VIN in
PWM mode. Alternate ENABLE configurations,
and other small signal pins need to be
connected and routed according to specific
customer application. Please see the Gerber
files
on
the
Altera Enpirion website
http://www.altera.com/enpirion
for
exact
dimensions and other layers. Please refer to
this
Figure
while reading the layout
recommendations in this section.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EN6347QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EN6347QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: Three PGND pins are
dedicated to the input circuit, and three to the
output circuit. The slit in Figure 7 separating
the input and output GND circuits helps
minimize noise coupling between the converter
input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
Enpirion website http://www.altera.com/enpirion.
Recommendation 4: The large thermal pad
underneath the component must be connected
to the system ground plane through as many
vias as possible.
Figure 7: Top PCB Layer Critical Components
and Copper for Minimum Footprint
The drill diameter of the vias should be
0.33mm, and the vias must have at least 1 oz.
copper plating on the inside wall, making the
finished hole size around 0.20-0.26mm. Do not
use thermal reliefs or spokes to connect the
vias to the ground plane. This connection
provides the path for heat dissipation from the
converter. Please see Figures: 7, 8, and 9.
Recommendation 5: Multiple small vias (the
same size as the thermal vias discussed in
recommendation 4 should be used to connect
ground terminal of the input capacitor and
output capacitors to the system ground plane.
It is preferred to put these vias under the
capacitors along the edge of the GND copper
closest to the +V copper. Please see Figure 7.
These vias connect the input/output filter
capacitors to the GND plane, and help reduce
parasitic inductances in the input and output
current loops. If the vias cannot be placed
under CIN and COUT , then put them just outside
the capacitors along the GND slit separating
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the two components. Do not use thermal reliefs
or spokes to connect these vias to the ground
plane.
Recommendation 6: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 7 this connection is made
at the input capacitor close to the VIN
connection.
Recommendation 7: The layer 1 metal under
the device must not be more than shown in
Figure 7. See the section regarding exposed
metal on bottom of package. As with any
switch-mode DC/DC converter, try not to run
sensitive signal or control lines underneath the
converter package on other layers.
Recommendation 8: The VOUT sense point
should be just after the last output filter
capacitor. Keep the sense trace as short as
possible in order to avoid noise coupling into
the control loop.
Recommendation 9: Keep RA, CA, and RB
close to the VFB pin (see Figures 6 and 7).
The VFB pin is a high-impedance, sensitive
node. Keep the trace to this pin as short as
possible. Whenever possible, connect RB
directly to the AGND pin instead of going
through the GND plane.
De sign Conside ra t ions for Le a d-Fra m e Ba se d M odule s
Exposed Metal on Bottom of Package
Lead frames offers many advantages in
thermal performance, in reduced electrical lead
resistance, and in overall foot print. However,
they do require some special considerations.
In the assembly process lead frame
construction requires that, for mechanical
support, some of the lead-frame cantilevers be
exposed at the point where wire-bond or
internal passives are attached. This results in
several small pads being exposed on the
bottom of the package.
Only the large thermal pad and the perimeter
pads are to be soldered to the PC board. The
PCB top layer under the EN6347QI should be
clear of any metal except for the large thermal
pad. The “grayed-out” region in Figure 8
represents the area that should be clear of any
metal (traces, vias, or planes), on the top layer
of the PCB.
VIN copper covered by
soldermask acceptable near
or under this exposed pad.
Figure 8: Lead-Frame Exposed Metal. Grey area highlights exposed metal below which
there should not be any metal (traces, vias, or planes) on the top layer of PCB.
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Re c om m e nded PCB Foot print
Dimensions in mm
Figure 9: EN6347QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing
specifications.
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Pa c k a ge a nd M e c ha nic a l
Figure 10: EN6347QI Package Dimensions
Cont a c t I nform a t ion
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other
countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's
standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders
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for products or services.
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