Cypress | AutoStore STK17T88 | Specifications | Cypress AutoStore STK17T88 Specifications

STK17T88
32K x 8 AutoStore nvSRAM with
Real Time Clock
Description
■
nvSRAM Combined With Integrated Real-Time Clock
Functions (RTC, Watchdog Timer, Clock Alarm, Power
Monitor)
The Cypress STK17T88 combines a 256 Kb nonvolatile static
RAM (nvSRAM) with a full-featured real-time clock in a reliable,
monolithic integrated circuit.
■
Capacitor or Battery Backup for RTC
■
25, 45 ns Read Access and R/W Cycle Time
The 256 Kb nvSRAM is a fast static RAM with a nonvolatile
QuantumTrap storage element included with each memory cell.
■
Unlimited Read/Write Endurance
■
Automatic Nonvolatile STORE on Power Loss
■
Nonvolatile STORE Under Hardware or Software Control
■
Automatic RECALL to SRAM on Power Up
■
Unlimited RECALL Cycles
■
200K STORE Cycles
■
20-Year Nonvolatile Data Retention
■
Single 3V +20%, -10% Power Supply
■
Commercial and Industrial Temperatures
■
48-Pin 300-mil SSOP Package (RoHS Compliant)
ig
ns
Features
D
es
The SRAM provides the fast access and cycle times, ease of use
and unlimited read and write endurance of a normal SRAM. Data
transfers automatically to the nonvolatile storage cells when
power loss is detected (the STORE operation). On power up,
data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
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The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
Alarm function is programmable for one-time alarms or periodic
minutes, hours, or days alarms. There is also a programmable
watchdog timer for processor control.
om
ROW DECODER
VCC
Quantum Trap
512 X 512
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
STORE/
RECALL
CONTROL
VRTCbat
VRTCcap
HSB
SOFTWARE
DETECT
INPUT BUFFERS
ot
N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCAP
POWER
CONTROL
R
ec
A5
A6
A7
A8
A9
A11
A12
A13
A14
m
en
Logic Block Diagram
A13 – A0
COLUMN I/O
COLUMN DEC
RTC
X1
X2
INT
A 0 A 1 A 2 A 3 A 4 A10
MUX
A14 – A0
G
E
W
Cypress Semiconductor Corporation
Document Number: 001-52040 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 25, 2009
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STK17T88
Contents
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Software STORE..........................................................
Software RECALL ........................................................
Data Protection.............................................................
Noise Considerations ...................................................
Preventing AutoStore ...................................................
Best Practices ..............................................................
Real Time Clock.................................................................
Reading the Clock ........................................................
Setting the Clock ..........................................................
Backup Power ..............................................................
Stopping and Starting the RTC Oscillator ....................
Calibrating The Clock ...................................................
Alarm ............................................................................
Watchdog Timer ...........................................................
Power Monitor ..............................................................
Interrupt Register..........................................................
Flags Register ..............................................................
RTC Register Map..............................................................
Commercial and Industrial
Ordering Information.........................................................
Ordering Codes .................................................................
Package Diagram...............................................................
Document History Page ....................................................
Sales, Solutions, and Legal Information .........................
Worldwide Sales and Design Support..........................
Products .......................................................................
14
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14
15
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15
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16
16
16
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17
18
22
22
23
24
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24
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Features................................................................................ 1
Description........................................................................... 1
Logic Block Diagram........................................................... 1
Contents ............................................................................... 2
Pin Configurations .............................................................. 3
Pin Descriptions .................................................................. 3
Absolute Maximum Ratings ............................................... 4
RF (SSOP-48) Package Thermal
Characteristics................................................................ 4
DC Characteristics (VCC = 2.7V-3.6V) ............................... 4
AC Test Conditions ............................................................. 5
Capacitance ......................................................................... 5
RTC DC Characteristics ...................................................... 6
SRAM READ Cycles #1 and #2........................................... 7
SRAM WRITE Cycles #1 and #2 ......................................... 8
AutoStore/Power Up RECALL ............................................ 9
Software-Controlled STORE/RECALL Cycle................... 10
Hardware STORE Cycle .................................................... 11
Soft Sequence Commands ............................................... 11
Mode Selection .................................................................. 12
nvSRAM Operation............................................................ 13
SRAM READ ................................................................ 13
SRAM WRITE .............................................................. 13
AutoStore Operation..................................................... 13
Hardware STORE (HSB) Operation............................. 13
Hardware Recall (POWER UP).................................... 13
Document Number: 001-52040 Rev. *C
Page 2 of 24
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STK17T88
Pin Configurations
Figure 1. 48-Pin SSOP
47
V CC
NC
3
46
HSB
A 12
A7
4
5
45
44
A6
A5
6
43
W
A 13
A8
7
42
A9
INT
8
41
NC
A4
9
40
A 11
NC
10
39
NC
NC
11
38
NC
NC
V SS
12
37
NC
13
36
NC
14
35
15
34
V SS
NC
V RTCcap
DQ 0
16
33
DQ 6
A3
A2
17
32
G
18
31
A 10
A1
19
30
A0
DQ 1
DQ 2
20
29
21
28
27
X1
22
23
26
DQ 4
DQ 3
X2
24
25
V CC
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E
DQ 7
DQ 5
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V RTCbat
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(TOP)
Relative PCB Area Usage[1]
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ns
48
2
es
1
NC
A 14
D
V CAP
d
Pin Descriptions
I/O Type
Description
A14-A0
Input
DQ7-DQ0
I/O
E
Input
Chip Enable: The active low E input selects the device.
W
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address location
selected on the falling edge of E.
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tristate.
X1
Output
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Pin Name
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Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array or one of 16 bytes
in the clock register map.
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Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC.
R
Crystal Connection, Drives Crystal on Startup.
Input
Power Supply
Capacitor Supplied Backup RTC Supply Voltage (Left unconnected if VRTCbat is used).
VRTCbat
Power Supply
Battery Supplied Backup RTC Supply Voltage (Left unconnected if VRTCcap is used).
Power Supply
Power: 3.0V, +20%, -10%
N
VCC
ot
X2
VRTCcap
Crystal Connection for 32.768 kHz Crystal.
HSB
I/O
Hardware Store Busy: When low this output indicates a store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection Optional).
INT
Output
Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the
power monitor. Programmable to either active high (push/pull) or active low (open-drain)
VCAP
Power Supply
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
VSS
Power Supply
Ground.
NC
No Connect
Unlabeled Pins have no Internal Connections.
Note
1. For detailed package size specifications, see Package Diagram on page 23.
Document Number: 001-52040 Rev. *C
Page 3 of 24
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STK17T88
Absolute Maximum Ratings
Note Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device
at conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to VSS ...........–0.5V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB ......................–0.5V to (VCC + 0.5V)
Temperature under Bias ............................... –55°C to 125°C
Junction Temperature ................................... –55°C to 140°C
Storage Temperature .................................... –65°C to 150°C
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ns
Power Dissipation............................................................. 1W
DC Output Current (1 output at a time, 1s duration).... 15 mA
RF (SSOP-48) Package Thermal Characteristics
Average VCC Current
ICC2
Average VCC Current during
STORE
3
ICC3
Average VCC Current at tAVAV
= 200 ns
3V, 25°C, Typical
10
ICC4
Average VCAP Current during
AutoStore Cycle
ISB
VCC Standby Current
(Standby, Stable CMOS
Levels)
IILK
Input Leakage Current
IOLK
Off-State Output Leakage
Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
Storage Capacitance
Nonvolatile STORE Operations
Data Retention
DATAR
D
Notes
mA
mA
tAVAV = 25 ns
tAVAV = 45 ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care, VCC = Max
Average current for duration of STORE
cycle (tSTORE)
W ≥ (V CC – 0.2V)
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE)
E ≥ (VCC -0.2V)
All Others VIN≤ 0.2V or ≥ (VCC-0.2V)
Standby current level after nonvolatile
cycle complete
VCC = Max
VIN = VSS to VCC
VCC = Max
VIN = VSS to VCC, E or G ≥ VIH
All Inputs
All Inputs
IOUT = – 2 mA
IOUT = 4 mA
3
mA
10
mA
3
3
mA
3
3
mA
±1
±1
μA
±1
±1
μA
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N
VIH
VIL
VOH
VOL
TA
VCC
VCAP
NVC
Units
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ICC1
Industrial
Min
Max
70
55
ew
Commercial
Min
Max
65
50
Parameter
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Symbol
(VCC = 2.7V-3.6V)
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DC Characteristics
es
θjc 6.2 C/W; θja 51.1 [0 fpm], 44.7 [200 fpm], 41.8 C/W [500 fpm]
2.0
VCC + 0.5
2.0
VCC + 0.5
VSS - 0.5
0.8
VSS - 0.5
0.8
2.4
2.4
0.4
0.4
0
70
- 40
85
2.7
3.6
2.7
3.6
17
57
17
57
200
200
20
20
V
V
V
V
°C
V
μF
K
3.0V +20%, -10%
Between VCAP pin and VSS, 5V rated.
Years At 55°C
Note
■
The HSB pin has IOUT=-10 µA for VOH of 2.4V, this parameter is characterized but not tested.
■
The INT is open-drain and does not source or sink high current when interrupt register bit D3 is low.
Document Number: 001-52040 Rev. *C
Page 4 of 24
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STK17T88
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times .................................................. ≤5 ns
Input and Output Timing Reference Levels .................... 1.5V
Output Load..................................See Figure 2 and Figure 3
Capacitance
Symbol
Parameter[2]
Max
Units
Conditions
Input Capacitance
7
pF
ΔV = 0 to 3V
COUT
Output Capacitance
7
pF
ΔV = 0 to 3V
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ns
CIN
Figure 3. AC Output Loading for Tristate Specifications
(THZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ)
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Figure 2. AC Output Loading
Note
2. These parameters are guaranteed but not tested.
Document Number: 001-52040 Rev. *C
Page 5 of 24
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STK17T88
RTC DC Characteristics
Commercial
Symbol
Industrial
Parameter
Units
Min
VRTCbat
Notes
Max
–
300
–
350
nA
From either VRTCcap or VRTCbat
RTC Battery Pin Voltage
1.8
3.3
1.8
3.3
V
Typical = 3.0V during normal operation
VRTCcap
RTC Capacitor Pin Voltage
1.2
2.7
1.2
2.7
V
Typical = 2.4V during normal operation
tOSCS
RTC Oscillator Time to Start
–
10
–
10
sec
At minimum temperature from power up or enable
–
5
–
5
sec
At 25°C from power up or enable
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ns
RTC Backup Current
Min
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Y1
X1
X2
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C2
RF
C1
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Figure 4. RTC Component Configuration
es
IBAK
Max
m
Recommended Values
C2 = 56 pF ± 10% (do not vary from this value)
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Y1 = 32.768 kHz
RF = 10 MO
C1 = 0 (install cap footprint, but leave unloaded)
Document Number: 001-52040 Rev. *C
Page 6 of 24
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STK17T88
SRAM READ Cycles #1 and #2
Symbols
No.
STK17T88-25
STK17T88-45
Min
Min
Parameter
#1
#2
1
Units
Alt.
tELQV
tACS
Chip Enable Access Time
Max
Max
25
45
ns
2
tAVAV[3]
tELEH[5]
tRC
Read Cycle Time
3
tAVQV[4]
tAVQV[6]
tAA
Address Access Time
25
45
ns
tGLQV
tOE
Output Enable to Data Valid
12
20
ns
tAXQX
tOH
Output Hold after Address Change
3
6
tELQX
tLZ
Address Change or Chip Enable to
Output Active
3
7
tEHQZ
tHZ
Address Change or Chip Disable to
Output Inactive
8
tGLQX
tOLZ
Output Enable to Output Active
9
tGHQZ[5]
tOHZ
Output Disable to Output Inactive
10
tELICCL[3]
tPA
Chip Enable to Power Active
tPS
Chip Disable to Power Standby
tEHICCH
[3]
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ns
ns
3
ns
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3
D
10
0
ns
15
0
10
ns
15
0
0
25
ns
ns
ns
45
ns
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11
tAXQX
45
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25
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Figure 5. SRAM READ Cycle #1: Address Controlled[3,4,6]
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tAVAV
en
ADDRESS
5
3
tAVQV
tAXQX
DATA VALID
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DQ (DATA OUT)
2
29
1
11
6
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Figure 6. SRAM READ Cycle #2: E and G Controlled[6]
N
7
3
9
4
8
10
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured ± 200 mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles.
Document Number: 001-52040 Rev. *C
Page 7 of 24
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STK17T88
SRAM WRITE Cycles #1 and #2
Symbols
No.
STK17T88-25
STK17T88-45
Min
Min
Parameter
#1
#2
Units
Alt.
Max
Max
tAVAV
tWC
Write Cycle Time
25
45
ns
13 tWLWH
tWLEH
tWP
Write Pulse Width
20
30
ns
14 tELWH
tELEH
tCW
Chip Enable to End of Write
20
30
ns
15 tDVWH
tDVEH
tDW
Data Setup to End of Write
10
15
ns
16 tWHDX
tEHDX
tDH
Data Hold after End of Write
0
0
ns
17 tAVWH
tAVEH
tAW
Address Setup to End of Write
20
30
ns
18 tAVWL
tAVEL
tAS
Address Setup to Start of Write
0
0
ns
19 tWHAX
tEHAX
tWR
Address Hold after End of Write
0
0
ns
20 tWLQZ
tWZ
Write Enable to Output Disable
21 tWHQX
tOW
Output Active after End of Write
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ns
12 tAVAV
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10
3
ns
ns
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3
15
Figure 7. SRAM WRITE Cycle #1: W Controlled[7, 8]
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12
tAVAV
ADDRESS
19
tWHAX
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14
tELWH
E
en
17
tAVWH
18
tAVWL
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DATA IN
DATA OUT
13
tWLWH
15
tDVWH
DATA VALID
20
tWLQZ
Figure 8. SRAM WRITE Cycle #2: E Controlled[7, 8]
ot
R
21
tWHQX
HIGH IMPEDANCE
PREVIOUS DATA
N
16
tWHDX
12
tAVAV
ADDRESS
18
tAVEL
14
tELEH
19
tEHAX
E
17
tAVEH
13
tWLEH
W
15
tDVEH
DATA IN
DATA OUT
16
tEHDX
DATA VALID
HIGH IMPEDANCE
Notes
7. If W is low when E goes low, the outputs remain in the high impedance state.
8. E or W must be ≥ VIH during address transitions.
Document Number: 001-52040 Rev. *C
Page 8 of 24
[+] Feedback
STK17T88
AutoStore/Power Up RECALL
Symbols
STK17T88
No.
Parameter
Standard
Units
Notes
40
ms
9
STORE Cycle Duration
12.5
ms
10, 11
2.65
V
Alternate
Min
22
tHRECALL
23
tSTORE
24
VSWITCH
Low Voltage Trigger Level
25
VCCRISE
VCC Rise Time
Max
Power up RECALL Duration
μS
150
ig
ns
tHLHZ
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Figure 9. AutoStore Power Up RECALL
23
23
om
m
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25
22
N
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R
ec
22
Note Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH
Notes
9. tHRECALL starts from the time VCC rises above VSWITCH
10. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
11. Industrial Grade devices require 15 ms maximum.
Document Number: 001-52040 Rev. *C
Page 9 of 24
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STK17T88
Software-Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed. [12, 13]
Symbols
No.
STK17T88-35
STK17T88-45
Min
Min
Parameter
E Cont
Alternate
Max
Units
Notes
13
Max
tRC
STORE/RECALL Initiation Cycle Time
25
45
ns
27 tAVEL
tAS
Address Setup Time
0
0
ns
28 tELEH
tCW
Clock Pulse Width
20
30
ns
29 tEHAX
Address Hold Time
1
1
ns
30 tRECALL
RECALL Duration
ig
ns
26 tAVAV
100
us
es
100
D
Figure 10. Software Store/Recall Cycle: E CONTROLLED[13]
26
27
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26
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28
23
30
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29
Notes
12. The software sequence is clocked on the falling edge of E controlled READs
13. The six consecutive addresses must be read in the order listed in the Mode Selection table. W must be high during all six consecutive cycles.
Document Number: 001-52040 Rev. *C
Page 10 of 24
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STK17T88
Hardware STORE Cycle
Symbols
STK17T88
No.
Parameter
Standard
31
tDELAY
32
tHLHX
Alternate
tHLQZ
Min
Max
Hardware STORE to SRAM Disabled
1
70
Hardware STORE Pulse Width
15
Units
Notes
μs
14
ns
ig
ns
Figure 11. Hardware STORE Cycle
es
32
ew
D
23
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31
Parameter
en
Symbol
No.
STK17T88
Min
m
Standard
tSS
Soft Sequence Processing Time
Units
Notes
μs
15, 16
Max
70
om
33
de
Soft Sequence Commands
33
33
N
ot
R
ec
Figure 12. Soft Sequence Command
Notes
14. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete
15. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
16. Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command
Document Number: 001-52040 Rev. *C
Page 11 of 24
[+] Feedback
STK17T88
Mode Selection
W
G
A14-A0
Mode
I/O
Power
H
X
X
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active
0x0FC0
Nonvolatile Store
Output High Z
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
es
ICC2
Active
D
L
17,18,19
17,18,19
ew
H
Notes
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L
ig
ns
E
Notes
17. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
18. While there are 15 addresses on the STK17T88, only the lower 13 are used to control software modes.
19. I/O state depends on the state of G. The I/O table assumes G low.
Document Number: 001-52040 Rev. *C
Page 12 of 24
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STK17T88
nvSRAM Operation
AutoStore Operation
The STK17T88 stores data to nvSRAM using one of three
storage operations. These operations are Hardware Store
(activated by HSB), Software Store (activated by an address
sequence), and AutoStore (on power down).
The STK17T88 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates similar to a standard fast static RAM. Data
in the SRAM can be transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to SRAM (the
RECALL operation). This unique architecture allows all cells to
be stored and recalled in parallel. During the STORE and
RECALL operations SRAM READ and WRITE operations are
inhibited. The STK17T88 supports unlimited read and writes
similar to a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and up to 200K
STORE operations.
AutoStore operation, a unique feature of Cypress QuanumTrap
technology that is a standard feature on the STK17T88.
ig
ns
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 13 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the DC
Characteristics (VCC = 2.7V-3.6V) table for the size of the
capacitor. The voltage on the VCAP pin is driven to 5V by a charge
pump internal to the chip. A pull up should be placed on W to
hold it inactive during power up.
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0.1µF
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W
m
VCAP
10k Ohm
V CC
en
V CC
SRAM WRITE
rN
Hardware STORE (HSB) Operation
Figure 13. AutoStore Mode
V CAP
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. The HSB signal can be monitored by the system to detect
an AutoStore cycle is in progress.
fo
The STK17T88 performs a READ cycle whenever E and G are
low while W and HSB are high. The address specified on pins
A0-14 determine which of the 32,768 data bytes are accessed.
When the READ is initiated by an address transition, the outputs
are valid after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E and G, the outputs are valid at tELQV or at tGLQV,
whichever is later (READ cycle #2). The data outputs repeatedly
respond to address changes within the tAVQV access time
without the need for transitions on any control input pins, and
remain valid until another address change or until E or G is
brought high, or W and HSB is brought low.
es
SRAM READ
A WRITE cycle is performed whenever E and W are low and HSB
is high. The address inputs must be stable prior to entering the
WRITE cycle and must remain stable until either E or W goes
high at the end of the cycle. The data on the common I/O pins
DQ0-7 are written into memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an E
controlled WRITE.
It is recommended that G be kept high during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If G is
left low, internal circuitry turns off the output buffers tWLQZ after
W goes low.
Document Number: 001-52040 Rev. *C
The STK17T88 provides the HSB pin to control and
acknowledge the STORE operations. The HSB pin can be used
to request a hardware STORE cycle. When the HSB pin is driven
low, the STK17T88 conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM took place since the last STORE or RECALL cycle.
The HSB pin has a very resistive pull up and is internally driven
low to indicate a busy condition while the STORE (initiated by
any means) is in progress. This pin must be externally pulled up
if it is used to drive other inputs.
SRAM READ and WRITE operations that are in progress when
HSB is driven low by any means are given time to complete
before the STORE operation is initiated. After HSB goes low, the
STK17T88 continues to allow SRAM operations for tDELAY.
During tDELAY, multiple SRAM READ operations may take place.
If a WRITE is in progress when HSB is pulled low, it is allowed a
time, tDELAY, to complete. However, any SRAM WRITE cycles
requested after HSB goes low are inhibited until HSB returns
high.
During any STORE operation, regardless of how it was initiated,
the STK17T88 continues to drive the HSB pin low, releasing it
only when the STORE is complete. Upon completion of the
STORE operation, the STK17T88 remains disabled until the
HSB pin returns high.
If HSB is not used, it should be left unconnected.
Hardware Recall (POWER UP)
During power up or after any low power condition
(VCC<VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Page 13 of 24
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STK17T88
Software STORE
Noise Considerations
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The STK17T88
software STORE cycle is initiated by executing sequential E
controlled READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data is erased
and the new data is programmed into the nonvolatile elements.
When a STORE cycle is initiated, further memory inputs and
outputs are disabled until the cycle is completed.
The STK17T88 is a high speed memory and so must have a high
frequency bypass capacitor of 0.1 µF connected between both
VCC pins and VSS ground plane with no plane break to chip VSS.
Use leads and traces that are as short as possible. As with all
high speed CMOS ICs, careful routing of power, ground, and
signals reduce circuit noise.
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
Because of the use of nvSRAM to store critical RTC data, the
AutoStore function cannot be disabled on the STK17T88.
Best Practices
■
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Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the
SRAM is again ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the nonvolatile
storage elements.
Data Protection
The STK17T88 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and
WRITE operations. The low voltage condition is detected when
VCC<VSWITCH.
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ew
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprograms these values. Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume an NV array is
in a set programmed state. Routines that check memory
content values to determine first time system configuration,
cold or warm boot status, and so on should always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E6 49 53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (such as AutoStore enabled). While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, and so on).
■
The OSCEN bit in the Calibration register at 0x7FF8 should be
set to ‘1’ to preserve battery life when the system is in storage
(see Stopping and Starting the RTC Oscillator on page 15).
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge time
based on this maximum Vcap value. Customers who want to
use a larger VCAP value to make sure there is extra store charge
and store time should discuss their Vcap size selection with
Cypress to understand any impact on the VCAPvoltage level at
the end of a tRECALL period.
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Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled READ
operations must be performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
D
es
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
After the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence.
After the tSTORE cycle time is fulfilled, the SRAM is again
activated for READ and WRITE operation.
Software RECALL
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Preventing AutoStore
If the STK17T88 is in a WRITE mode (both E and W low) at
power up, after a RECALL, or after a STORE, the WRITE is
inhibited until a negative transition on E or W is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Document Number: 001-52040 Rev. *C
Page 14 of 24
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STK17T88
Real Time Clock
A capacitor has the obvious advantage of being more reliable
and not containing hazardous materials. The capacitor is
recharged every time the power is turned on so that the real time
clock continues to have the same backup time over years of
operation
The clock registers maintain time up to 9,999 years in
one-second increments. The user can set the time to any
calendar time and the clock automatically keeps track of days of
the week and month, leap years, and century transitions. There
are eight registers dedicated to the clock functions which are
used to set time with a write cycle and to read time during a read
cycle. These registers contain the Time of Day in BCD format.
Bits defined as ‘0’ are currently not used and are reserved for
future use by Cypress.
When selecting a battery power source, connect the battery to
the VRTCbat pin and leave the VRTCcap pin unconnected. A 3V
lithium is recommended for this application. The battery capacity
should be chosen for the total anticipated cumulative down-time
required over the life of the system.
ig
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The real time clock is designed with a diode internally connected
to the VRTCbat pin. This prevents the battery from ever being
charged by the circuit.
Reading the Clock
Halt internal updates to the real time clock registers before
reading clock data to prevent reading of data in transition.
Stopping the internal register updates does not affect clock
accuracy.
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Stopping and Starting the RTC Oscillator
The OSCEN bit in the Calibration register at 0x7FF8 enables
RTC oscillator operation. This bit is nonvolatile and shipped to
customers in the “enabled” state (set to ‘0’). OSCEN should be
set to ‘1’ to preserve battery life while the system is in storage.
This turns off the oscillator circuit extending the battery life. If the
OSCEN bit goes from disabled to enabled, it typically takes 5
seconds (10 seconds maximum) for the oscillator to start.
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Write a ‘1’ to the read bit “R” (in the Flags register at 0x7FF0) to
capture the current time in holding registers. Clock updates do
not restart until a ‘0’ is written to the read bit. The RTC registers
can now be read while the internal clock continues to run.
rN
Within 20 ms after a ‘0’ is written to the read bit, all real time clock
registers are simultaneously updated.
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Set the write bit “W” (in the Flags register at 0x7FF0) to ‘1’ to
enable the time to be set. The correct day, date, and time can
then be written into the real time clock registers in 24-hour BCD
format. The time written is referred to as the “Base Time.” This
value is stored in nonvolatile registers and used in calculation of
the current time. Reset the write bit to ‘0’ to transfer the time to
the actual clock counters, The clock starts counting at the new
base time.
fo
Setting the Clock
The STK17T88 has the ability to detect oscillator failure due to
loss of backup power. The failure is recorded by the OSCF
(Oscillator Failed bit) of the Flags register (at address 0x7FF0).
When the device is powered on (VCC goes above VSWITCH) the
OSCEN bit is checked for “enabled” status. If the OSCEN bit is
enabled and the oscillator is not active within 5 ms, the OSCF bit
is set. Check for this condition and then write a ‘0’ to clear the
flag. When the OSCF flag bit, the real time clock registers are
reset to the “Base Time” (see the section Setting the Clock on
page 15, the value last written to the real time clock registers.
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Backup Power
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The RTC is intended to keep time even when system power is
lost. When primary power, VCC, drops below VSWITCH, the real
time clock switches to the backup power supply connected to
either the VRTCcap or VRTCbat pin.
R
The clock oscillator uses a maximum of 300 nanoamps at 2V to
maximize the backup time available from the backup source.
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ot
The user can power the real time clock with either a capacitor or
a battery. Factors to be considered when choosing a backup
power source include the expected duration of power outages
and the cost and reliability trade-off of using a battery versus a
capacitor.
When selecting a capacitor power source, connect the capacitor
to the VRTCcap pin and leave the VRTCbat pin unconnected.
Capacitor backup time values based on maximum current specifications are shown below. Nominal times are approximately
three times longer.
Capacitor Value
Backup Time
0.1 F
72 hours
0.47 F
14 days
1.0 F
30 days
Document Number: 001-52040 Rev. *C
The value of OSCF should be reset to ‘0’ when the real time clock
registers are written for the first time. This initializes the state of
this bit because it may have become set when the system was
first powered on.
To reset OSCF, set the write bit “W” (in the Flags register at
0x7FF0) to ‘1’ to enable writes to the Flags register. Write ‘0’ to
the OSCF bit and then reset the write bit to ‘0’ to disable writes.
Calibrating The Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal specified (usually 35 ppm at 25°C). This error can
equate to 1.53 minutes gain or loss per month. The STK17T88
employs a calibration circuit that can improve the accuracy to
+1/-2 ppm at 25°C. The calibration circuit adds or subtracts
counts from the oscillator divider circuit.
The number of time pulses added or subtracted depends upon
the value loaded into the five calibration bits found in Calibration
register (at 0x7FF8). Adding counts speeds the clock up;
subtracting counts slows the clock down. The calibration bits
occupy the five lower order bits of the register. These bits can be
set to represent any value between 0 and 31 in binary form. Bit
D5 is a Sign bit, where a ‘1’ indicates positive calibration and a
‘0’ indicates negative calibration. Calibration occurs during a 64
minute period. The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128 or lengthened
by 256 oscillator cycles.
Page 15 of 24
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STK17T88
watchdog timer function does not operate unless the oscillator is
running.
If a binary ‘1’ is loaded into the register, only the first 2 minutes
of the 64 minute cycle is modified; if a binary ‘6’ is loaded, the
first 12 are affected, and so on. Therefore each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles
for every 125,829,120 actual oscillator cycles. That is +4.068 or
-2.034 ppm of adjustment per calibration step in the Calibration
register.
The watchdog counter is loaded with a starting value from the
load register and then counts down to zero, setting the watchdog
flag (WDF) and generating an interrupt if the watchdog interrupt
is enabled. The watchdog flag bit is reset when the Flags register
is read. The operating software normally reloads the counter by
setting the watchdog strobe bit (WDS) to ‘1’ within the timing
interval programmed into the load register.
The Calibration register value is determined during system test
by setting the CAL bit in the Flags register (at 0x7FF0) to ‘1’. This
causes the INT pin to toggle at a nominal 512 Hz. This frequency
is measured with a frequency counter. Any deviation measured
from the 512 Hz indicates the degree and direction of the
required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error, requiring a -10 (001010) to be loaded
into the Calibration register. Note that setting or changing the
calibration register does not affect the frequency test output
frequency.
ig
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To use the watchdog timer to reset the processor on timeout, the
INT is tied to processor master reset and Interrupt register is
programmed to 24h to enable interrupts to pulse the reset pin on
timeout.
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To load the watchdog timer, set a new value into the load register
by writing a ‘0’ to the watchdog write bit (WDW) of the watchdog
register (at 0x7FF7). Then load a new value into the load register.
After the new value is loaded, the watchdog write bit is then set
to ‘1’ to disable watchdog writes. The watchdog strobe bit (WDS)
is set to ‘1’ to load this value into the watchdog timer. Note that
setting the load register to zero disables the watchdog timer
function.
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To set or clear CAL, set the write bit “W” (in the Flags register at
0x7FF0) to a ‘1’ to enable writes to the Flags register. Write a
value to CAL and then reset the write bit to ‘0’ to disable writes.
The default Calibration register value from the factory is 00h. The
user calibration value loaded is retained during a power loss.
rN
The system software should initialize the watchdog load register
on power up to the desired value because the register is not
nonvolatile.
Power Monitor
The STK17T88 provides a power monitor function. The power
monitor is based on an internal band-gap reference circuit that
compares the VCC voltage to VSWITCH.
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The alarm function compares a user-programmed alarm
time/date (stored in registers 0x7FF1-5) with the real time clock
time-of-day/date values. When a match occurs, the alarm flag
(AF) is set and an interrupt is generated if the alarm interrupt is
enabled. The alarm flag is automatically reset when the Flags
register is read.
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Alarm
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Each of the alarm registers has a match bit as its MSB. Setting
the match bit to a ‘1’ disables this alarm register from the alarm
comparison. When the match bit is ‘0’, the alarm register is
compared with the equivalent real time clock register. Using the
match bits, an alarm can occur as specifically as one particular
second on one day of the month or as frequently as once per
minute.
ec
Note The product requires the match bit for seconds (0x7FF2,
bit D7) be set to ‘0’ for proper operation of the Alarm Flag and
Interrupt.
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The alarm value should be initialized on power up by software
because the alarm registers are not nonvolatile.
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To set or clear the Alarm registers, set the write bit “W” (in the
Flags register at 0x7FF0) to ‘1’ to enable writes to the Alarm
registers. Write an alarmvalue to the alarm registers and then
reset the write bit to ‘0’ to disable writes.
Watchdog Timer
The watchdog timer is designed to interrupt or reset the
processor should its program get hung in a loop and not respond
in a timely manner. The software must reload the watchdog timer
before it counts down to zero to prevent this interrupt or reset.
The watchdog timer is a free-running-down counter that uses the
32 Hz clock (31.25 ms) derived from the crystal oscillator. The
Document Number: 001-52040 Rev. *C
When the power supply drops below VSWITCH, the real time clock
circuit is switched to the backup supply (battery or capacitor).
When operating from the backup source, no data may be read
or written and the clock functions are not available to the user.
The clock continues to operate in the background. Updated clock
data is available tHRECALL delay after VCC is restored to the
device.
When the power is lost, the PF flag in the Flags register is set to
indicate the power failure and an interrupt is generated if the
power fail interrupt is enabled (Interrupt register=20h). The INT
line is normally tied to the processor master reset input to
perform power-off reset.
Interrupts
The STK17T88 has a Flags register, Interrupt register, and
interrupt logic that can interrupt the microcontroller or general a
power up master reset signal. There are three potential interrupt
sources: the watchdog timer, the power monitor, and the clock
alarm. Each can be individually enabled to drive the INT pin by
setting the appropriate bit in the Interrupt register. In addition,
each has an associated flag bit in the Flags register that the host
processor can read to determine the interrupt source. Two bits in
the interrupt register determine the operation of the INT pin
driver.
Figure 14 is a functional diagram of the interrupt logic.
Page 16 of 24
[+] Feedback
STK17T88
High/Low (H/L). When set to ‘1’, the INT pin is active high and
the driver mode is push-pull. The INT pin can drive high only
when VCC>VSWITCH. When set to ‘0’, the INT pin is active low
and the drive mode is open-drain. The active low (open drain)
output is maintained even when power is lost.
Figure 14. Interrupt Block Diagram
WDF
P/L
PFE
Pin
Driver
H/L
VINT
VCC
Pulse/Level (P/L). When set to ‘1’, the INT pin is driven for
approximately 200 ms when the interrupt occurs. The pulse is
reset when the Flags register is read. When P/L is set to ‘0’, the
INT pin is driven high or low (determined by H/L) until the Flags
register is read.
INT
VSS
AF
Clock
Alarm
The Interrupt register is loaded with the default value 00h at the
factory. Configure the Interrupt register to the desired value for
the desired mode of operation. Once configured, the value is
retained during power failures.
AIE
Interrupt Register
Watchdog Interrupt Enable (WIE). When set to ‘1’, the watchdog
timer drives the INT pin when a watchdog time-out occurs. When
WIE is set to ‘0’, the watchdog time-out only sets the WDF flag
bit.
Flags Register
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Power
Monitor
WIE
PF
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Watchdog
Timer
D
The Flags register has three flag bits: WDF, AF, and PF. These
flags are set by the watchdog time-out, alarm match, or power
fail monitor respectively. The processor can either poll this
register or enable the interrupts to be informed when a flag is set.
The flags are automatically reset when the register is read.
ew
Alarm Interrupt Enable (AIE). When set to ‘1’, the INT pin is
driven when an alarm match occurs. When set to ‘0’, the alarm
match only sets the AF flag bit.
The Flags register is automatically loaded with the value 00h on
power up (with the exception of the OSCF bit).
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Power Fail Interrupt Enable (PFE). When set to ‘1’, the INT pin
is driven by a power fail signal from the power monitor. When set
to ‘0’, only the PF flag is set.
Document Number: 001-52040 Rev. *C
Page 17 of 24
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STK17T88
RTC Register Map
BCD Format Data
D2
10s Years
0
0
0x7FFD
0
0
0x7FFC
0
0
0x7FFB
0
0
0x7FFA
0
0
0
0
0x7FF7
WDS
WDW
0x7FF6
WIE[0]
AIE[0]
0x7FF5
M
0
0
M
Months: 01-12
Day of Month
Day of Month: 01-31
Hours: 00-23
Minutes: 00-59
Seconds
Seconds: 00-59
Calibration [00000]
WDT
PFE[0]
0
H/L [1]
P/L [0]
0
10s Alarm Date
Alarm Day
10s Alarm Hours
10 Alarm Seconds
10s Centuries
AF
PF
Day of week: 01-07
Hours
10 Alarm Minutes
WDF
Months
Day of Week
10s Seconds
0x7FF1
Years: 00-99
rN
0x7FF2
Years
Minutes
Cal
Sign
OSCF
Function/Range
D0
0
Calibration values[20]
Watchdog[20]
Interrupts[20]
0
Alarm, Day of Month: 01-31
Alarm Hours
Alarm, hours: 00-23
Alarm Minutes
Alarm, minutes: 00-59
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M
D1
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0
M
0
10s Hours
OSCEN [0]
0x7FF4
0
10s Minutes
0x7FF8
0x7FF3
10s
Months
10s Day of Month
0x7FF9
0x7FF0
D3
Alarm Seconds
Alarm, seconds: 00-59
Centuries
Centuries: 00-99
d
0x7FFE
D4
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0x7FFF
D5
es
D6
D
D7
CAL[0]
W[0]
R[0]
Flags[20]
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Register
0 - Not implemented, reserved for future use.
en
Default Settings of nonvolatile Calibration and Interrupt registers from factory.
Calibration Register=00h.
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Interrupt Register=00h.
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Configure the desired value at startup or during operation; the value is then retained during a power failure.
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[ ] designates values shipped from the factory. See Stopping and Starting the RTC Oscillator on page 15.
Note
20. A binary value, not a BCD value.
Document Number: 001-52040 Rev. *C
Page 18 of 24
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STK17T88
Register Map Detail
Real Time Clock – Years
0x7FFF
D7
D6
D5
D4
D3
D2
10s Years
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble
contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0 to 99.
Real Time Clock – Months
D7
D6
D5
D4
D3
0
0
0
10s
Month
D2
D1
D0
Months
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ns
0x7FFE
Real Time Clock – Date
D7
D6
0
0
D5
D4
D3
D2
D
0x7FFD
es
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1 to 12.
10s Day of month
D1
D0
Day of month
rN
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Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from
0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1 to 31.
Leap years are automatically adjusted for.
Real Time Clock – Day
D7
D6
D5
D4
D3
0
0
0
0
0
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0x7FFC
D2
D1
D0
Day of week
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Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that
counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not
integrated with the date.
Real Time Clock – Hours
D6
0
0
D5
en
D7
D4
D3
D2
10s Hours
D1
D0
Hours
m
0x7FFB
0x7FFA
D6
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D7
om
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from
0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register
is 0 to 23.
D4
D3
D2
10s Minutes
D1
D0
Minutes
R
0
Real Time Clock – Minutes
D5
N
0x7FF9
ot
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0 to 59.
D7
Real Time Clock – Seconds
D6
0
D5
D4
D3
D2
10s Seconds
D1
D0
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper digit and operates from 0 to 5. The range for the register is 0 to 59.
0x7FF8
Calibration
D7
D6
D5
OSCEN
0
Calibration
Sign
D4
D3
D2
D1
D0
Calibration
OSCEN
Oscillator Enable. When set to ‘1’, the oscillator is disabled. When set to ‘0’, the oscillator is enabled.
Disabling the oscillator saves battery/capacitor power during storage.
Calibration Sign
Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base.
Calibration
These five bits control the calibration of the clock.
Document Number: 001-52040 Rev. *C
Page 19 of 24
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STK17T88
Register Map Detail (continued)
Watchdog Timer
0x7FF7
D7
D6
WDS
WDW
D5
D4
D3
D2
D1
D0
WDT
Watchdog Strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. The bit is cleared automatically when the watchdog timer is reset. The WDS bit is write only. Reading it always returns a ‘0’.
WDW
Watchdog Write Enable. Set this bit to ‘1’ to disable writing of the watchdog time-out value (WDT5-WDT0).
This allows to strobe the watchdog without disturbing the time-out value. Setting this bit to ‘0’ allows bits
5-0 to be written.
WDT
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this register. It
represents a multiplier of the 32 Hz count (31.25 ms). The range or time-out values is 31.25 ms (a setting
of ‘1’) to 2 seconds (setting of 3Fh). Setting the watchdog timer register to ‘0’ disables the timer. These bits
can be written only if the WDW bit was cleared to ‘0’ on a previous cycle.
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WDS
D7
D6
D5
D4
D3
WIE
AIE
PFIE
ABE
H/L
D2
D1
D0
P/L
0
0
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Interrupt
0x7FF6
Watchdog Interrupt Enable. When set to ‘1’ and a watchdog time-out occurs, the watchdog timer drives the
INT pin and sets the WDF flag. When set to ‘0’, the watchdog time-out only sets the WDF flag.
AIE
Alarm Interrupt Enable. When set to ‘1’, the alarm match drives the INT pin and sets the AF flag. When set
to ‘0’, the alarm match only sets the AF flag.
PFIE
Power-Fail Enable. When set to ‘1’, a power failure drives the INT pin and sets the PF flag. When set to ‘0’,
a power failure only sets the PF flag.
Reserved for Future Use
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WIE
High/Low. When set to a ‘1’, the INT pin is driven active high. When set to ‘0’, the INT pin is open drain,
active low.
P/L
Pulse/Level. When set to a ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source for
approximately 200 ms. When set to ‘0’, the INT pin is driven to an active level (as set by H/L) until the Flags
register is read.
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M
Alarm – Day
D5
0
10s Alarm Date
D6
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D7
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0x7FF5
D4
D3
D2
D1
D0
Alarm Date
ec
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. Setting this bit to ‘0’ causes the date value to be used in the alarm match. Setting this bit to ‘1’ causes
the match circuit to ignore the date value.
N
M
0x7FF3
Alarm – Hours
D7
D6
M
0
ot
0x7FF4
R
M
D5
D4
D3
D2
10s Alarm Hours
D1
D0
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. Setting this bit to ‘0’ causes the hours value to be used in the alarm match. Setting this bit to ‘1’
causes the match circuit to ignore the hours value.
Alarm – Minutes
D7
M
D6
D5
10s Alarm Minutes
D4
D3
D2
D1
D0
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
Match. Setting this bit to ‘0’ causes the minutes value to be used in the alarm match. Setting this bit to ‘1’
causes the match circuit to ignore the minutes value.
Document Number: 001-52040 Rev. *C
Page 20 of 24
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STK17T88
Register Map Detail (continued)
Alarm – Seconds
0x7FF2
D7
D6
M
D5
D4
D3
D2
10s Alarm Seconds
D1
D0
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
M
Match. Setting this bit to ‘0’ causes the seconds’ value to be used in the alarm match. Setting this bit to ‘1’
causes the match circuit to ignore the seconds value.
Real Time Clock – Centuries
0x7FF1
Centuries
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10s Centuries
D7
D6
D5
D4
D3
WDF
AF
PF
OSCF
0
D2
D1
D0
D
Flags
0x7FF0
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Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper centuries digit and operates from 0 to 9. The range for the register is 0 to 99
centuries.
W
R
CAL
Watchdog Timer Flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach ‘0’ without
being reset by the user. It is cleared to ‘0’ when the Flags register is read or on power up.
AF
Alarm Flag. This read only bit is set to ‘1’ when the time and date match the values stored in the Alarm
registers with the match bits equal to ‘0’. It is cleared when the Flags register is read or on power up.
PF
Power Fail Flag. This read only bit is set to ‘1’ when power falls below the power-fail threshold VSWITCH. It
is cleared to ‘0’ when the Flags register is read or on power up.
OSCF
Oscillator Fail Flag. Set to ‘1’ on power up only if the oscillator is enabled and not running in the first 5 ms
of operation. This indicates that the RTC backup power failed and the clock value is no longer valid. Reset
this bit to ‘0’ to clear this condition.
CAL
Calibration Mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT
pin resumes normal operation. This bit defaults to ‘0’ (disabled) on power up.
W
Write Time. Setting the W bit to ‘1’ freezes updates of the RTC registers. The user can then write to the
RTC registers, Alarm registers, Calibration register, Interrupt register, and Flags register. Setting the W bit
to ‘0’ disables writes to the registers and causes the contents of the real time clock registers to be transferred
to the timekeeping counters if the time has changed (a new base time is loaded). The bit defaults to ‘0’ on
power up.
R
Read Time. Setting the R bit to ‘1’ captures the current time in holding registers so that clock updates are
not during the reading process. Set the R bit to ‘0’ to enable the holding register to resume clock updates.
The bit defaults to ‘0’ on power up.
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WDF
Document Number: 001-52040 Rev. *C
Page 21 of 24
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STK17T88
Commercial and Industrial Ordering Information
STK17T88 - R F 45 I TR
Packaging Option:
TR = Tape and Reel
Blank = Tube
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Temperature Range:
C - Commercial (0 to 70°C)
I - Industrial (-40 to 85°C)
Lead Finish
Speed:
25 - 25 ns
45 - 45 ns
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F = 100% Sn (Matte Tin) RoHS Compliant
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Package:
R = Plastic 48-pin 330 mil SSOP
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
Access Time (ns)
25
Temperature
Commercial
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
45
Commercial
STK17T88-RF25TR
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
25
Commercial
STK17T88-RF45TR
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
45
Commercial
STK17T88-RF25I
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
25
Industrial
STK17T88-RF45I
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
45
Industrial
STK17T88-RF25ITR
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
25
Industrial
STK17T88-RF45ITR
3.3V 32Kx8 AutoStore nvSRAM+RTC SSOP48-300
45
Industrial
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STK17T88-RF25
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These parts are not recommended for new designs.
Ordering Code
Description
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Ordering Codes
Document Number: 001-52040 Rev. *C
Page 22 of 24
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STK17T88
Package Diagram
51-85061-*C
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Figure 15. 48-Pin SSOP (51-85061)
Document Number: 001-52040 Rev. *C
Page 23 of 24
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STK17T88
Document History Page
Document Title: STK17T88 32K x 8 AutoStore nvSRAM with Real-Time Clock
Document Number: 001- 52040
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
2668660
GVCH/PYRS
03/04/2009
New data sheet
*A
2675319
GVCH
03/17/2009
Corrected typo on page 1 in ‘Description’ section: changed 256KB to
256Kb.
*B
2793420
GVCH/AESA
10/27/09
*C
2814390
GVCH
11/25/2009
Description of change
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Figure 1: Updated pin 43 from A6 to A8.
Updated tRECALL unit from ms to us
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Added note in the Ordering Information section mentioning that these
parts are not recommended for new designs.
Added “Not recommended for new designs” watermark in the PDF..
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Sales, Solutions, and Legal Information
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Worldwide Sales and Design Support
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
psoc.cypress.com
Clocks & Buffers
clocks.cypress.com
wireless.cypress.com
Memories
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PSoC
image.cypress.com
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Image Sensors
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-52040 Rev. *C
Revised November 25, 2009
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