AOZ8904 Ultra-Low Capacitance TVS Diode Array General Description

AOZ8904 Ultra-Low Capacitance TVS Diode Array  General Description

AOZ8904

Ultra-Low Capacitance TVS Diode Array

General Description

The AOZ8904 is a transient voltage suppressor array designed to protect high speed data lines from Electro

Static Discharge (ESD) and lightning.

This device incorporates eight surge rated, low capacitance steering diodes and a Transient Voltage

Suppressor (TVS) in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (±15kV air,

±8kV contact discharge).

The AOZ8904 comes in a Halogen Free and RoHS compliant SOT-23 and SC-70 packages. It is rated over a

-40°C to +85°C ambient temperature range.

Features

ESD protection for high-speed data lines:

– Exceeds: IEC 61000-4-2 (ESD) ±24kV (air),

±24kV (contact)

– IEC 61000-4-5 (Lightning) 4A (8/20µs)

– Human Body Model (HBM) ±24kV

Small package saves board space

Low insertion loss

Protects four I/O lines

Low clamping voltage

Low operating voltage: 5.0V

Applications

USB 2.0 Power and Data Line Protection

Video Graphics Cards

Monitors and Flat Panel Displays

Digital Video Interface (DVI)

Typical Application

USB Host

Controller

R

T

R

T

R

T

R

T

VBUS

AOZ8904

+5V

Downstream

Ports

VBUS

D+

D-

GND

+5V

VBUS

D+

D-

GND

Figure 1. 2 USB High Speed Ports

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Rev. 2.1 January 2011 Page 1 of 11

AOZ8904

Ordering Information

Part Number

AOZ8904CIL

AOZ8904HIL

Ambient Temperature Range

-40°C to +85°C

Package

SOT-23-6

SC-70-6

AOS Green Products used reduced levels of Halogens, and are also RoHS compliant.

Please visit www.aosmd.com/web/quality/rohs_compliant.jsp

for additional information.

Pin Configuration

CH1

1 6

CH4

VN

2 5

VP

Environmental

RoHS Compliant

Green Product

CH2

3

SOT-23-6 / SC-70-6

(Top View)

4

CH3

Absolute Maximum Ratings

Exceeding the Absolute Maximum ratings may damage the device.

Parameter

VP – VN

Peak Pulse Current (I

PP

), t

P

= 8/20µs

Peak Power Dissipation (8 x 20µ[email protected] 25°C)

Storage Temperature (T

S

)

ESD Rating per IEC61000-4-2, contact

(1)

ESD Rating per IEC61000-4-2, air

(2)

ESD Rating per Human Body Model

(2)

Junction Temperature (T

J

)

Notes:

1. IEC 61000-4-2 discharge with C

Discharge

= 150pF, R

Discharge

= 330

.

2. Human Body Discharge per MIL-STD-883, Method 3015 C

Discharge

= 100pF, R

Discharge

= 1.5k

.

Rating

6V

4A

50W

-65°C to +150°C

±24kV

±24kV

±24kV

-40°C to +125°C

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AOZ8904

Electrical Characteristics

T

A

= 25°C unless otherwise specified

Symbol

V

RWM

V

BR

I

R

V

F

V

CL

C j

ΔC j

Parameter Conditions

Reverse Working Voltage Between pin 5 and 2

(4)

Reverse Breakdown Voltage I

T

= 1mA, between pins 5 and 2

(5)

Reverse Leakage Current V

RWM

= 5V, between pins 5 and 2

Diode Forward Voltage

Channel Clamp Voltage

Positive Transients

Negative Transient

I f

= 15mA

I

PP

= 1A, tp = 100ns, any I/O pin to

Ground

(3)(6)(8)

IPP = 5A, tp = 100ns, any I/O pin to

Ground

(3)(6)(8)

Channel Clamp Voltage

Positive Transients

Negative Transient

Channel Clamp Voltage

Positive Transients

Negative Transient

IPP = 12A, tp = 100ns, any I/O pin to

Ground

(3)(6)(8)

Junction Capacitance

Channel Input Capacitance

Matching

V

R

= 0V, f = 1Mhz, any I/O pin to Ground

(3)(7)

V

R

= 0V, f = 1Mhz, between I/O pins

(3)(7)

Min.

Typ.

Max.

Units

6.6

0.7

0.85

5.5

1

0.95

V

V

µA

V

11.00

-2.00

14.00

-3.50

18.00

-5.00

1.25

Notes:

3. These specifications are guaranteed by design.

4. The working peak reverse voltage, V

RWM

, should be equal to or greater than the DC or continuous peak operating voltage level.

5. V

BR

is measured at the pulse test current I

T

.

6. Measurements performed with no external capacitor on V

P

(Pin 5 floating).

7. Measurements performed with V

P

biased to 3.3 Volts (Pin 5 @ 3.3V).

8. Measurements performed using a 100 nSec Transmission Line Pulse (TLP) system.

1.3

0.03

V

V

V

V

V

V pF pF

Rev. 2.1 January 2011

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Page 3 of 11

AOZ8904

Typical Performance Characteristics

7

4

3

6

5

2

1

0

0

17

16

15

14

13

12

11

10

9

0

Clamping Voltage vs. Peak Pulse Current

(tperiod = 100ns, tr = 1ns)

2 4 6 8

Peak Pulse Current, I

PP

(A)

10

Forward Voltage vs. Forward Current

(tperiod = 100nS, tr = 1ns)

2 4 6 8

Forward Current, I

PP

(A)

10

12

12

-8

-9

-10

-5

-6

-7

-2

-3

-4

1

0

-1

1

I/O – Gnd Insertion Loss (S21) vs. Frequency

(Vp = 3.3V)

10 100

Frequency (MHz)

1000

20

0

-20

-40

-60

-80

10

Analog Crosstalk (I/O–I/O) vs. Frequency

-8

-9

-10

-3

-4

-5

-6

-7

1

0

-1

-2

1

I/O – I/O Insertion Loss (S21) vs. Frequency

(Vp = Float)

10 100 1000

Frequency (MHz)

100

Frequency (MHz)

1000

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Page 4 of 11

AOZ8904

Application Information

The AOZ8904 TVS is design to protect four data lines from fast damaging transient over-voltage by clamping it to a reference. When the transient on a protected data line exceed the reference voltage the steering diode is forward bias thus, conducting the harmful ESD transient away from the sensitive circuitry under protection.

PCB Layout Guidelines

Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines.

The location of the protection devices on the PCB is the simplest and most important design rule to follow. The

AOZ8904 devices should be located as close as possible to the noise source. The placement of the AOZ8904 devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8904 devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8904 device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8904 ultra-low capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry.

Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended:

1. Place the TVS near the IO terminals or connectors to restrict transient coupling.

2. Fill unused portions of the PCB with ground plane.

3. Minimize the path length between the TVS and the protected line.

4. Minimize all conductive loops including power and ground loops.

5. The ESD transient return path to ground should be kept as short as possible.

6. Never run critical signals near board edges.

7. Use ground planes whenever possible.

8. Avoid running critical signal traces (clocks, resets, etc.) near PCB edges.

9. Separate chassis ground traces from components and signal traces by at least 4mm.

10. Keep the chassis ground trace length-to-width ratio

<5:1 to minimize inductance.

11. Protect all external connections with TVS diodes.

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Page 5 of 11

TPBIASx

IEEE 1394

PHY

TPAx+

TPAx-

TPBx+

TPBx-

GND

1μ 56Ω 56Ω

56Ω

5.1kΩ

56Ω

270p

IEEE1394 Port Connection

IEEE 1394

Connector

AOZ8904

AOZ8904

Rev. 2.1 January 2011

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Page 6 of 11

AOZ8904

Package Dimensions, SOT-23-6L

D e1

Gauge Plane c

Seating Plane

0.25mm

L

E E1

θ1 e b

A

A1

A2

.010mm

RECOMMENDED LAND PATTERN

0.80

0.95

2.40

0.63

UNIT: mm

Symbols

A

A1

A2 b c

D

E

E1 e e1

L

θ1

Dimensions in millimeters

Min.

0.90

0.00

0.80

Nom.

1.10

0.30

0.08

2.70

2.50

1.50

0.40

0.13

2.90

2.80

0.30

0

°

1.60

0.95 BSC

1.90 BSC

Max.

1.25

0.15

1.20

0.60

8

°

0.50

0.20

3.10

3.10

1.70

Symbols

A

A1

A2 b c

D

E

E1 e e1

L

θ1

Dimensions in inches

Min.

0.035

0.00

0.031

Nom.

0.043

Max.

0.049

0.006

0.047

0.012

0.003

0.106

0.098

0.016

0.005

0.114

0.110

0.020

0.008

0.122

0.122

0.059

0.063

0.037 BSC

0.067

0.012

0

°

0.075 BSC

0.024

8

°

Notes:

1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each.

2. Dimension “L” is measured in gauge plane.

3. Tolerance

±0.100mm (4 mil) unless otherwise specified.

4. Followed from JEDEC MO-178C & MO-193C.

6. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.

Rev. 2.1 January 2011

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Page 7 of 11

AOZ8904

Tape and Reel Dimensions, SOT-23-5&6L

Tape

P1

D0

P2

K0

B0

D1

E2

E1

E

P0

A0

Unit: mm

Package

SOT23-5/6L

LP

A0

3.15

±0.10

B0

3.20

±0.10

K0

1.40

±0.10

D0

1.50

±0.05

D1

1.00

+0.10 / -0

E

8.00

±0.30

E1

1.75

±0.10

E2

3.50

±0.05

P0

4.00

±0.10

Feeding Direction

P1

4.00

±0.10

P2

2.00

±0.05

T

0.23

±0.03

Reel

W1

S

K

R

M

N

J

H

Unit: mm

Tape Size

8mm

Reel Size

ø177.8

M

ø177.8

Max.

N

55.0

Min.

W1 H

8.4

+1.50 / -0.0

13.0

+0.5 / -0.2

S

1.5

Min

K

10.1

Min.

R

12.7

J

4.0

±0.1

Leader/Trailer and Orientation

Trailer Tape

300mm min.

Rev. 2.1 January 2011

Components Tape

Orientation in Pocket

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Leader Tape

500mm min.

Page 8 of 11

AOZ8904

Package Dimensions, SC-70-6L

D e1

E E1 e b

Gauge Plane

θ

0.15mm

L c

A

A2

A1

.010mm

RECOMMENDED LAND PATTERN

0.65

0.65

1.95

0.35

UNIT: mm

Dimensions in millimeters

Symbols

A

A1

A2

D

E b c e e1

E1

L

θ

Min.

0.00

0.7

0.15

0.08

1.85

1.80

Nom.

0.9

2.10

2.30

1.1

0.26

0

°

0.65 BSC

1.30 BSC

1.30

0.36

4

°

Max.

1.10

0.10

1.00

0.30

0.22

2.15

2.40

1.4

0.46

8

°

Dimensions in inches

Symbols

A

A1

A2

D

E b c e e1

E1

L

θ

Min.

0.00

0.028

0.006

0.003

0.073

0.071

Nom.

0.035

0.083

0.091

0.043

0.010

0

°

0.026 BSC

0.051 BSC

0.051

0.014

4

°

0.055

0.018

8

°

Max.

0.043

0.004

0.039

0.012

0.009

0.085

0.094

Notes:

1. All dimensions are in millimeters.

2. Dimensions are inclusive of plating

3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 3 mils.

4. Die is facing up for mold and facing down for trim/form; i.e., reverse trim/form.

5. Dimension L is measured in gauge plane.

6. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.

Rev. 2.1 January 2011

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Page 9 of 11

Tape and Reel Dimensions, SC-70-6L

Carrier Tape

D1

P2

P1

T

E2

E1

E

B0

K0

D0

A0

P0

Feeding Direction

UNIT: mm

Package

SC-70, 6L

(8mm)

A0

2.40

±0.10

B0

2.40

±0.10

K0

1.19

±0.10

D0

1.00

Min.

D1

1.55

±0.05

E

8.00

±0.30

E1

1.75

±0.10

E2

3.50

±0.05

P0

4.00

±0.10

P1

4.00

±0.10

P2

2.00

±0.05

T

0.25

±0.05

AOZ8904

Reel

W1

S

G

M

N

K

V

R

H

W

Tape Size

8mm

Reel Size

ø180

M

ø180.00

±0.50

N

ø60.50

W

9.00

±0.30

W1

11.40

±1.00

H

ø13.00

+0.50/-0.20

K

10.60

S

2.00

±0.50

G

ø9.00

R

5.00

V

18.00

Leader/Trailer and Orientation

Rev. 2.1 January 2011

Trailer Tape

300mm min. or

75 empty pockets

Components Tape

Orientation in Pocket

Leader Tape

500mm min. or

125 empty pockets

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Page 10 of 11

AOZ8904

Part Marking

AOZ8904CIL

(SOT-23)

AKOW Assembly Lot Code

Part Number Code

Underscore Denotes

Greeen Product

Week & Year Code

Otption & Assembly Location Code

AOZ8904HIL

(SC-70)

AWL

Part Number Code

Underscore Denotes

Greeen Product

Assembly Lot & Location Code

Week & Year Code

This datasheet contains preliminary data; supplementary data may be published at a later date.

Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.

LIFE SUPPORT POLICY

ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL

COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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