Introduction_to_CC430

Introduction_to_CC430
Introduction to CC430 – RF1A
Peter Spevak
Introduction to CC430
Introduction to CC430
1.
2.
3.
4.
5.
6.
7.
8.
Brief introduction to CC430
RF System Introduction
Block Diagram of the CC430F6137 & Peripherals
Derivatives of the CC430F61xx & CC430F51xx Family
RF1A Core & 6xx Core
RF1A Radio Interface
RF1A Changes vs. CC1101
Making RF Easy: Tools, Collateral and Support
MCUs and RF opportunities are endless
Worldwide market for wireless
technology in manufacturing
will grow at a 32% CAGR over
the next five years, and
is projected to exceed
$1 billion in 2010
- ARC Advisory Group
4
CC2.4 GHz
TI Low-Power RF at a glance…
Alarm and Security
Sub 1 GHz
Remote Controls
CC2511
CC1110
Sub 1 GHz SoC
CC2530
2.4 GHz Radio
32KB Flash
0.3 uA sleep current
RF4CE
8051 MCU,
32 KB Flash, USB 2.0
Proprietary solution
CC1101 / CC430
IEEE 802.15.4 compliant
System on Chip
RemoTI SW
Sub 1 GHz Transceiver
+ MSP430 MCU,
500 Kbps
-112dBm sensitivity
Metering
CC2505S
CC2530
CC1020
ZigBee
Narrowband
Wireless Audio
PurePath™ Wireless
Coming Soon
12.5 KHz channel spacing
System on Chip
-118dBm sensitivity
IEEE 802.15.4 compliant
+ CC259x Range Extenders
CD Quality
Wireless Audio
CC2591
2.4 GHz Range Extender
+22dBm output power
CC2431
CC2480
Network Processor
Location Tracking
System on Chip
Solutions
fully certified ZigBee 2006
Software Stack
Sport & Gaming
CC2540
CC2500
Bluetooth Low Energy
Coming Soon
2.4 GHz Transceiver
Single-mode BTLE SoC
Home Automation & Lighting
+MSP430 MCU
MSP430 + CCxxxx Radio Solutions
The MSP430 product family supports a variety of wireless protocols
SimpliciTI, TI-MAC (802.15.4), Z-Stack (ZigBee & ZigBee Pro)
TI’s Three RF solutions
RF Systemson-Chip
Application MCU
RF Radio
Application
Wireless
Protocols
Radio
Application MCU+
RF Protocol
Processor
MSP430
RF SoC
(CC430,
CC2430,
CC2510,
CC1110)
MSP430
(F54xx, F24xx,
F26xx)
Transceiver
(CC1101,
CC2500,
CC2520)
Protocol
processor
(CC2480,
CC430)
7
Sub 1-GHz Wireless Applications
Demand for
more intelligence
& cutting the
cable
Looking for
power in new
places
Solar
Thermal
Intersection
of higher
performance,
lower cost and
low power
Motion and vibration
•
•
•
•
•
Property and asset IDs
Networked sensors
Heat cost allocator
Automatic meter reading
Alarm and security
8
What is the CC430?
•
•
•
•
It is a subfamily of the MSP430 with 7 derivatives
CPU core is based on the MSP430F5xx technology
Radio is based on the CC1101 Sub 1GHz transceiver
“CC” points to TI LPW SRD products “430” to MSP430
Microcontrollers.
• Supports 300-348MHz, 387- 464MHz and 779-928MHz
• This includes in EU the so called 868MHz band (852870MHz) the 433MHz band and the US 315MHz and
915MHz (902-928MHz) band.
The CC430 – Integrated System-On-Chip
CC430
Low Power
RF IC
MSP430
MCU
Radio
frequency
Application
and protocol
processor
Low Power
< 1 GHz RF
Transceiver
• High sensitivity
• Low current consumption
• Excellent blocking performance
• Flexible data rate & modulation format
• Backwards compatible
Low-power
RF SoC
MSP430
5xx MCU
• Ultra-low power
• High analog performance
• High level of integration
• Ease of development
• Sensor interface
10
CC430 application spaces
Consumer &
Home area networking
 Watch / heart monitor
combination for monitoring
miles and calories
 Enough processing for
wireless networking and
batteries that last many
years
Remote monitoring
 Low power sensor networks
for distributed status
reporting of integrity,
temperature, humidity,
 Harvest energy from motion,
vibration and heat
Asset
Tracking
 Encryption enables
secure wireless
reporting information
 Location, tamper
detection and
temperature monitoring
TI Low-Power RF – EU Sub 1GHz
Alarm and Security
Sub Metering - AMR
CC1110
Sub 1 GHz SoC
32KB Flash
0.3 uA sleep current
CC1101 / CC430
Sub 1 GHz Transceiver
+ MSP430 MCU,
500 Kbps
-112dBm sensitivity
Smart Metering
CC1020
Narrowband
12.5 KHz channel spacing
-118dBm sensitivity
CC1101 / CC430
Sub 1 GHz Transceiver
+ MSP430 MCU,
500 Kbps
-112dBm sensitivity
CC1110
Sub 1 GHz SoC
32KB Flash
0.3 uA sleep current
Home Automation & Lighting
Sub 1 GHz
Introduction to CC430
1.
2.
3.
4.
5.
6.
7.
8.
Brief introduction to CC430
RF System Introduction
Block Diagram of the CC430F6137 & Peripherals
Derivatives of the CC430F61xx & CC430F51xx Family
RF1A Core & 6xx Core
RF1A Radio Interface
RF1A Changes vs. CC1101
Making RF Easy: Tools, Collateral and Support
Global frequency bands
Short-Range Wireless Comparison
Range
Proprietary Low Power Radio
1000m
•Gaming
•PC Peripherals
•Audio
•Meter Reading
•Building Mgmt.
•Automotive
< 1GHz Standard
100m
• Building Automation
• Residential Control
• Industrial
--- Apps. in both freq. bands --• Tracking
• Sensors
• Home Automation / Security
• Meter Reading
10m
ZigBee/802.15.4
Wi-Fi/802.11
•PC Networking
•Home Networking
•Video Distribution
•Headsets
•PC Peripherals
•PDA/Phone
1m
1k
10k
100k
1M
Different Value Drivers for Different Applications
10M
UWB
•Wireless USB
•Video/audio links
Data Rate
(bps)
Basic Building Blocks of an RF System
•
RF-IC
– Transmitter / Receiver
– Transceiver
•
– Balanced to unbalanced
– Converts a differential signal to a
single-ended signal or vice versa
Microcontroller
– For protocol and applicaiton
processing
– System-on-Chip (SoC): typically
transceiver with integrated uC
•
• Balun
Crystal
– Reference frequency for the LO
and the carrier frequency
– Impedence Matching
• Filter
– Used if needed to pass regulatory
requirements / improve selectivity
• Antenna
Antenna
(50 Ohms)
RF-IC
Crystal
Balun
&
Match
Filter
Important Factors for Radio Range
•
•
•
•
•
•
Antenna (gain, sensitivity to body effects etc.)
Sensitivity
Channel Selectivity
Output power
Radio pollution (selectivity, blocking, IP3)
Environment (Line of sight, obstructions,
reflections, multi-path fading)
Antennas, commonly used
•
PCB antennas
–
–
–
–
•
Little extra cost (PCB)
Size demanding at low frequencies
Good performance possible
Complicated to make good designs
Whip antennas
–
–
–
•
Expensive (unless piece of wire)
Good performance
Hard to fit in may applications
Chip antennas
–
–
–
Expensive
OK performance
Small size
Introduction to CC430
1.
2.
3.
4.
5.
6.
7.
8.
Brief introduction to CC430
RF System Introduction
Block Diagram of the CC430F6137 & Peripherals
Derivatives of the CC430F61xx & CC430F51xx Family
RF1A Core & 6xx Core
RF1A Radio Interface
RF1A Changes vs. CC1101
Making RF Easy: Tools, Collateral and Support
CC430F613x Block Diagram
Shared Reference
• Excellent PSRR and
temperature coefficient
• Selectable internal references
- 1.5, 2.0, 2.5V
• Backwards compatible with
existing reference (ADC12)
• Sampled reference mode
provides tradeoff
power consumption <> accuracy
- Can be used for Comp_B or
LCD_B reference generation
- Not recommended for use
with ADCs / DACs
Comparator_B
• Inverting and non-inverting terminal input multiplexer
• High-speed, normal, and ultra-low power modes
• Internal output to Timer A capture
• Selectable RC filter for comparator output
Comparator_B – Reference Voltage Generator
•
•
•
Selectable reference voltages
Shared reference can provide
1.2 V, 1.5 V, 2.0 V, 2.5 V
Automatic voltage hysteresis
generator
Comparator_B - CAPD
Vcc
VI
VO
Icc
Vcc
CAPD.x = 1
Vss
• CAPD shut down capability to avoid cross currents with analog voltage
levels at I/Os
LCD_B
• Blinking of individual
segments at a
programmable frequency
• Programmable frame rate
• Regulated charge pump
• Software-driven contrast
control
• Integrated drivers to
decouple LCD load from the
bias generation
LCD_B Bias Generation
• Bias voltages V2 to V5 can be
generated using programmable
internal or external VLCD
• Integrated drivers provide
stable node voltage and good
contrast to large LCD segments
• When using an external
resistor ladder:
- VLCD may be sourced from
the internal charge pump
-R33 may serve as a
switched LCD output
AES Encryption Accelerator
• Main features
– En- and decryption
according to
AES FIPS PUB 197
– Off-line key generation
for decryption
– Byte and word-access to
key, input and output data
– AES ready interrupt flag
– Built-in DMA support
– The interpretation of word data can be configured as little-endian
(AESENDIAN = 0) or as big-endian with (AESENDIAN = 1)
ADC12_A Enhanced Features
•
VREF settling time
– 50us vs. 17ms
•
Tighter temp coefficient on internal
reference
– ±50ppm vs. ±100ppm
•
Lower power modes
– Selectable speed vs power
– References automatically shut
down to conserve power
•
•
Higher clock dividers for faster
system clocks
~6 x lower current than ADC12
– 220uA for ADC active
– 100uA for 2.5V VREF active
USCI Enhanced Features
• Interrupts re-designed
–
–
–
–
Separate vectors for USCI_A & USCI_B – no more sharing or bit-testing
Interrupt vector generator register
Simplifies USCI interrupt operations
Reduces code size
Port mapping
• Each output signal is mapped to several
output pins (per device datasheet)
• Each port Px.y (P1 – P3) pin has its own PxMAPy register
• Mapping is runtime re-configurable
– Single configuration per PUC Reset ... OR ...
– PMARECFG bit allows runtime re-configurations
• Port mapping configuration is password protected
• Write access is locked when...
– Invalid password is written while access is granted
– Timeout counter reaches 32
• All mappable pins also support PM_Analog functionality
– Disables port logic to prevent parasitics
CC430 Synchronous Mode
Timer0_A5 connections
Clock from
RF1A
Signals from
RF1A
RF data
RF data clk
other
signals
CC430 Asynchronous Mode
Clock from
RF1A
RF data
from RF1A
RF data
to RF1A
Introduction to CC430
1.
2.
3.
4.
5.
6.
7.
8.
Brief introduction to CC430
RF System Introduction
Block Diagram of the CC430F6137 & Peripherals
Derivatives of the CC430F61xx & CC430F51xx Family
RF1A Core & 6xx Core
RF1A Radio Interface
RF1A Changes vs. CC1101
Making RF Easy: Tools, Collateral and Support
CC430 Derivatives
ADC12_A
Comparator_B
LCD_B
CC430F613x
CC430F612x
ADC12_A
CC430F512x
ADC12_A
Comparator_B
Comparator_B
LCD_B
LCD_B
Comparator_B
CC430 Derivatives – CC430F613x
CC430 Derivatives – CC430F612x
CC430 Derivatives – CC430F513x
CC430 derivatives
With LCD module
•
CC430F6137
(LCD, ADC, Comparator B, 64-Pin)
Without LCD module
•
– 32KB+512B FLASH
– 4KB RAM
•
CC430F6135
(LCD, ADC, Comparator B, 64-Pin)
– 32KB+512B FLASH
– 4KB RAM
•
– 16KB+512B FLASH
– 2KB RAM
•
CC430F6127
(LCD, Comparator B, 64-Pin)
– 32KB+512B FLASH
– 4KB RAM
•
CC430F6125
(LCD, Comparator B, 64-Pin)
– 16KB+512B FLASH
– 2KB RAM
CC430F5137
(ADC, Comparator B, 48-Pin)
CC430F5135
(ADC, Comparator B, 48-Pin)
– 16KB+512B FLASH
– 2KB RAM
•
CC430F5133
(ADC, Comparator B, 48-Pin)
– 8KB+512B FLASH
– 2KB RAM
CC430 - Packages
CC430 – Packages 64-pin RGC
CC430 – Packages 48-pin RGZ
Introduction to CC430
1.
2.
3.
4.
5.
6.
7.
8.
Brief introduction to CC430
RF System Introduction
Block Diagram of the CC430F6137 & Peripherals
Derivatives of the CC430F61xx & CC430F51xx Family
RF1A Core & 6xx Core
RF1A Radio Interface
RF1A Changes vs. CC1101
Making RF Easy: Tools, Collateral and Support
MSP430 CPUXv2
• C-compiler friendly
• CPU registers expanded to 20-bits
• Address instructions
– Direct 20-bit CPU register access
– Atomic instructions
• Instruction compatible with all MSP430’s
• Extension word allows all instructions
– Direct access to 1MB address space
– Bit, byte, word and address-word data
– Repeat instruction function
CC430 Memory Map
• Page-free 16-bit addressing
• User-definable interface to the Boot
Strap Loader (BSL)
• 4 User Info Segments
– INFO_A can be locked
• Factory data brought out to its own
location
– Factory calibration values
• ADC offset, temperature, DCO
– Unique product ID
• Vector table starts at 0xFF80 for
compatibility with previous MSP430’s
• RF1A registers from 0x0F00 – 0x0F3F
CC430 Operating Modes
•
•
•
LPM0 – LPM4 are the same as
previous MSP430 generations
BOR resets device, executes
internal boot code, registers
default
SVS/M generate POR/interrupts
in event of low voltage condition
CC430 Unified Clock System (UCS)
•
Six independent clock sources
–
Low Freq
•
•
•
–
High Freq
•
•
•
•
•
LFXT1
REFO
XT2
ACLK / SMCLK / MCLK can be driven
from any source
MODOSC provided to modules
–
•
RF XT2 (26 MHz)
DCO – optional FLL
MODOSC
FLL reference selectable from three,
divisible low-freq sources
–
–
–
•
LFXT1
VLO
REFO
Flash controller & ADC12
Clocks on demand
Radio Core Operations
Radio Core
Instruction Set
1. Change RF Core State
Command
Strobes
2. Access Configuration
Registers
Read/Write
Instructions
SRES STX SFTX SNOP
SIDLE SRX SFRX SXOFF
REGRD
REGWR
STATREGRD
STATREGWR
...
RXFIFORD TXFIFOWR
(to configure RF Core settings)
Conf. Registers
3. Access TX/RXFIFO
(to access transmit / receive data)
64-byte
RX FIFO
64-byte
TX FIFO
Address from 0x00 to 0x29
Configure RF Core:
•Frequency
•Modulation
Event-driven
Interrupts
•RSSI
•Packet Handling
•GDO
•Etc.
CC430 Radio
CC430 Radio – TX Path
CC430 Radio – TX Path – Power Amplifier
Main Parameters
• Up to +10dBm output power to 50Ohm
• Built in attenuation steps down to -30dBm
• Built-in LDO keeps the output power stable across the
operating range of the transceiver 2.2V – 3.6V
• Output is balanced >> requires a balun for a single ended
antenna
CC430 Radio – TX Path – PA Table
• Used for PA power ramp up and ramp down
• Used for OOK and ASK modulation
• No huge power load changes from 0 to max. causing VCO sweeps over the
close channels
• Cleaner RF environment in RF networks with a lot of TDMA transmission.
• Good for meeting the ETSI requirements on power ramping
CC430 Radio– TX Path - Synthesizer
Purpose of the Synthesizer
• Generate in cooperation with the PLL and VCO the required output
frequency.
Main parameters
• Reference crystal frequency range 26MHz – 27MHz
• Programmed Frequency resolution 397Hz – 412Hz
Main features
• Very high frequency resolution, can be used to correct frequency
tolerance of the reference crystal.
• 1ppm at 868MHz are 868Hz >> resolution better than 0.5ppm
• Enables compensation of the frequency drift due to temperature
CC430 Radio MIB – TX Path - Modulator
Purpose of the Modulator
• Generate frequency modulation schemes, 2-FSK, 2-GFSK and MSK
Main parameters
• Supports programmable data rates in the range 1.2kBaud – 500kBaud
• Defines deviation according to
Main features
• Supports 2-FSK, 2-GFSK and MSK modulation formats.
• For amplitude modulation the PA-Table is used.
• Supports automatic Manchester encoding, when enabled.
CC430 Radio MIB – RX Path
CC430 Radio – RX Path
LNA
• Amplify the RF signal with the lowest possible noise figure
• Highest possible saturation point
Image rejection Mixer
• Converts the high frequency signal down to IF frequency.
• Suppresses the image resulting from mixing the carrier
frequency with the VCO frequency for down conversion.
• This serves the same purpose as SAW filters.
CC430 Radio – RX Path
Copied from CC1101, characterization of CC430 not finished yet.
CC430 Radio – RX Path
Copied from CC1101, characterization of CC430 not finished yet.
Introduction to CC430
1.
2.
3.
4.
5.
6.
7.
8.
Brief introduction to CC430
RF System Introduction
Block Diagram of the CC430F6137 & Peripherals
Derivatives of the CC430F61xx & CC430F51xx Family
RF1A Core & 6xx Core
RF1A Radio Interface
RF1A Changes vs. CC1101
Making RF Easy: Tools, Collateral and Support
CC430 Architecture Overview
XIN XOUT
(32kHz)
MCLK
Unified
Clock
System
P1.x/P2.x
2x8
REF
ACLK
Comp_B
ADC12
SMCLK
Voltage
Reference
DMA
Controller
3 Channel
25MHz
CPUXV2
incl. 16
Registers
Bus
Cntrl
Logic
MAB
P3.x/P4.x
2x8
I/O Ports
P1/P2
2x8 I/Os
I/O Ports
P3/P4
2x8 I/Os
PA
1x16 I/Os
PB
1x16 I/Os
P5.x
1x8
I/O Ports
P5
1x8 I/Os
MDB
Sub-1GHz
Radio
(CC1101)
MDB
Flash
RAM
32kB
16kB
2kB
1kB
SYS
CRC16
Watchdog
Port
Mapping
Controller
MPY32
RF
Interface
CPU Interface
MODEM
MDB
Spy-BiWire
Packet
Handler
Digital RSSI
Carrier Sense
PQI / LQI
CCA
MAB
EEM
(S: 3+1)
JTAG
Interface
RF_XIN RF_XOUT
(26MHz)
MAB
Frequency
Synthesizer
Power
Mgmt
LDO
SVM/SVS
Brownout
Timer0_A5
5 CC
Registers
Timer1_A3
3 CC
Registers
RTC_A
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
(SPI, I2C)
LCD_B
96
Segments
1,2,3,4
Mux
AES128
Security
En-/Decryption
RF/ANALOG
TX & RX
RF_P
RF_N
Interface between MSP430 and CC1101
Test Mode “look
a like mode”
RF_N
FREQ SYNTH
90
RC OSC
MODULATOR
PA
BIAS
RBIAS
RXFIFO
SPI
MSP430 Interface
0
INTERFACE TO MCU
RF_P
TXFIFO
ADC
PACKET HANDLER
LNA
FEC / INTERLEAVER
ADC
DEMODULATOR
RADIO CONTROL
sclk
cen
si
so
MAB
MDB
ifclk
rw
byte
ms
XOSC
RF_XIN
RF_XOUT
Standard/Application
Mode
RF1A Radio Interface
RF1A Interface
MSP430
RF IF Configuration
Registers
Radio Core
Instruction (INSTR)
RF1A Logical Channel
Registers
Instruction Set
Status (STAT)
Command Strobes
Data in (DIN)
Read/Write Instructions
Data Out (DOUT)
Direct FIFO
RF1A Direct FIFO
RF1A Core
Interrupt Vector
RX
FIFO
TX
FIFO
Radio Core
Registers
Event-driven
Interrupts
* Direct FIFO not implemented in PG0.6 *
MSP430 Radio Interface Logic
INSTRB
DINB
INSTRW
DINW
Radio Interface Input Data Processing
GDO0
Direct access to
TX FIFO
TXFIFO
GDOx
CC Radio Core
TX FIFO
RX FIFO
CCIO
Interrupt
Logic
RXFIFO
Direct access to
RX FIFO
Radio Interface Output Data Processing
STATW
STATB
DOUTW
DOUTB
* Direct FIFO not implemented in PG0.6 *
Instruction based radio controller
– Instructions are written byte- or wordwise into INSTR register
– Appropriate number of data
(instruction parameters) are written
into DIN register
– Writing INSTR register initiates status
update at STAT register
– Writing DIN register initiates output
data at DOUT register
Auto-Read feature simplifies the read
accesses
– Saves dummy-writes
– Speeds up processing
– Simplifies usage
RF1A Logical Channels
RF1AINSTRW
RF1AINSTRB
RF1ADINB
RF1ADINW
RF1ASTATW
RF1ASTATB
RF1ADOUTB
RF1ADOUTW
RF1A interface format
- Byte-access registers can be used stand-alone OR grouped to form word-access registers
- Radio core > Big-Endian (LSB last) ; MSP430 > Little-Endian (MSB last)
• By default, conversion from MSP430 to radio core is automatic (  RF1AIFCTL0 )
RF1A Logical Channel Errors
RF1AINSTRW
RF1AINSTRB
RF1ADINB
RF1ADINW
RF1ASTATW
RF1ASTATB
RF1ADOUTB
RF1ADOUTW
- Care must be taken that the exact number of bytes required by the radio are written.
- Care must be taken that the exact number of bytes provided by the radio are read.
E.g. If only one byte is required for a write or provided to be read, do NOT use 16-bit access
- Code should be written such that error flags never occur
RF1A Radio Core Instruction
Instruction
Instruction
Status
Status
Data In
Data In
Data Out
Data Out
8 bits Instruction
R/W B
8 bits Status Byte
A6 - A0
RF_RDYn RF_STATEx FIFO_BYTES_AVAILx
7
6
5
4
3
2
1
0
7
6
R/W
Bit 7
Read or Write Access to Radio Core
RF_RDYn
Bit 7
B
Bit 6
Burst Access to Radio Core
RF_STATEx
Bit 6-4 State of the radio core state machine
B
Bits 5-0 Radio Configuration Registers Address
Which address is between 0x00 and
0x29
5
4
3
2
1
0
Radio Core Ready
FIFO_BYTES_AVAILx Bits 3-0 Number of Bytes available in the
RX FIFO or TX FIFO
RF1A Radio Core Command Strobes
Instruction Byte
Status Byte
Single-Byte Instruction
Initiate Internal Sequence
13 Command Strobes
MSB = 0 -> Status Byte returns
number bytes available in TX FIFO
MSB = 1 -> Status Byte returns
number of bytes available in RX FIFO
Burst bit (B) is always 0
Executed immediately
*Bug in current rev*:
The RF1A core considers all strobe commands are
treated as read-access, which will then only return
RF1A RX FIFO status.
Workaround:
Write to an unused register (such as 0x27/0x28) to
read the RF1A TX FIFO status afterwards.
RF1A Radio Core Command Strobes
Reset RF1A Core
RF1AINSTRB = RF_SRES;
status = RF1ASTATB;
Go to IDLE State
RF1AINSTRB = RF_SIDLE;
status = RF1ASTATB;
Turn on RX Mode
Turn off RX Mode
RF1AINSTRB = RF_SRX;
status = RF1ASTATB;
RF1AINSTRB = RF_SIDLE;
status = RF1ASTATB;
RF1AINSTRB = RF_SFRX;
status = RF1ASTATB;
------------ | ----------------------- | ----------------------- | -----------NOTE:
Entry into a state != IDLE
or SLEEP requires
PMMVCORE >= 0x02.
------------ | ----------------------- | ------------
Turn on TX Mode
(Transmit data in TX FIFO)
RF1AINSTRB = RF_STX;
status = RF1ASTATB;
------------ | ------------
All RF1A instructions (e.g., RF_STX) are defined in cc430x631x.h header file
RF1A Radio Core Access Instructions
All in Interface Registers!
No Timing constraint – automatic
synchronization
Trigger with interrupt flags
Inputs
Outputs
[x1x2aa aaaa]
|
[ ssss ssss ]
[ ----
|
[dddd dddd]
---- ]
x1 > R/W access
x2 > Burst access
a > Instruction address bit
s > Status bit
d > Data bit
- > Don’t care bit
RF1A Radio Core Access Instructions
RF1AINSTR = Instruction + Register Address
Read Status Register
RF1AINSTRB = RF_STATREGRD + RSSI;
RF1ADINB = 0x00; // dummy write to initiate RF1ADOUTB
channel = RF1ADOUTB;
Read Single Register
RF1AINSTRB = RF_SNGLEREGRD + CHANNR;
RF1ADINB = 0x00; // dummy write to initiate RF1ADOUTB
channel = RF1ADOUTB;
Alternatively, RF1AINSTRB and RF1ADINB can be combined
RF1AINSTRW = ((RF_SNGLEREGRD + CHANNR) << 8) + 0x00;
// 0x00 is still a “dummy write” to initiate RF1ADOUTB
channel = RF1ADOUTB;
Write Single Register
RF1AINSTRB = RF_SNGLREGWR + CHANNR ;
RF1ADINB = channel;
Alternatively, RF1AINSTRB and RF1ADINB can be combined
RF1AINSTRW = ((RF_SNGLREGWR + CHANNR) << 8) ) + channel;
RF1A Radio Core Burst Access Instructions
Read Multiple Registers (Read Burst)
Radio core auto-increments the address to the next register
RF1AINSTRB = RF_REGRD + IOCFG2; // address of the 1st register
RF1ADINB = 0x00;
// dummy write to initiate RF1ADOUTB
iocfg2 = RF1ADOUTB; // read register IOCFG2
RF1ADINB = 0x00;
// dummy write
iocfg1 = RF1ADOUTB; // read register IOCFG1 (next address)
RF1ADINB = 0x00;
// dummy write
iocfg0 = RF1ADOUTB; // read register IOCFG0 (next address)
. . .
Efficient Code using For Loop
RF1AINSTRB = RF_REGRD + STARTING_REG_ADRESS;
for (i=0; i< length; i++) // read length bytes
{
RF1ADINB = 0x00;
// dummy write
buffer[i] = RF1ADOUTB; // write DOUTB to buffer
}
All RF1A register definitions (e.g., IOCFG2) are defined in cc430x631x.h header file
RF1A Radio Core Access Instructions
Write Multiple Registers (Write Burst)
Radio core auto-increments the address to the next register
RF1AINSTRB
RF1ADINB =
RF1ADINB =
RF1ADINB =
RF1ADINB =
RF1ADINB =
. . .
= RF_REGWR + MDMCFG4;
mdmcfg4; // write to modem
mdmcfg3; // write to modem
mdmcfg2; // write to modem
mdmcfg1; // write to modem
mdmcfg0; // write to modem
configuration
configuration
configuration
configuration
configuration
reg.
reg.
reg.
reg.
reg.
4
3
2
1
0
Using For Loop
RF1AINSTRB = RF_REGWR + STARTING_REG_ADDRESS;
for (i=0; i< length; i++) // write length bytes to RF1A Registers
RF1ADINB = buffer[i];
// write to configuration register
RF1A Radio Core Auto-Read
- 1-byte auto-read adds one byte to the output FIFO after reading it
- There are also word-access auto-read registers (e.g. - RF1ADOUTW2B)
* 2-byte auto-reads add two bytes to the output FIFO after reading it
RF1A Radio Core Auto-Read Code
Read Status Register
RF1AINSTR1B = RF_STATREGRD + RSSI;
channel = RF1ADOUTB;
Read Single Register
RF1AINSTR1B = RF_SNGLEREGRD + CHANNR;
channel = RF1ADOUTB;
Read Multiple Register
Burst mode
RF1AINSTR1B = RF_REGRD + MDMCFG4;
mdmcfg4 = RF1ADOUT1B; // reads 1 byte MDMCFG4 & initiates 1 auto-read byte
mdmcfg3 = RF1ADOUT2B; // reads 1 byte MDMCFG3 & initiates 2 auto-read bytes
mdmcfg21= RF1ADOUT1W; // reads 2 bytes MDMCFG2-1 & initiates 1 auto-read byte
mdmcfg0 = RF1ADOUTB; // reads 1 byte MDMCFG0 & no more auto-read
Read Multiple Register
Burst mode Using For Loop
RF1AINSTR1B = RF_REGRD + START_REG_ADDRESS;
for (i=0; i<length-1; i++)
// read length-1 bytes using auto-read
buffer[i] = RF1ADOUT1B;
// reads 1 byte & initiates 1 auto-read byte
buffer[length-1] = RF1ADOUTB; // reads 1 byte with no further auto-read
RF1AINSTR21 W
B = Instruction + Register Address
1 or 2 : number of bytes prepared for auto-read (next read)
B or W : number bytes currently read
Radio Core Status Registers
• 12 Status Registers
• Accessible via Status Read Commands
TXFIFO & RXFIFO Examples
Read RXFIFO
RF1AINSTR1B = RF_SNGLREGRD | RXBYTES; //get RXFIFO size & trigger auto-read
length = RF1ADOUTB;
// get RXBYTES length
RF1AINSTR1B = RF_REGRD | RXFIFORD; //RF_REGRD optional (already included)
for (i=0; i<length-1; i++)
// read length-1 bytes using auto-read
buffer[i] = RF1ADOUT1B;
// read 1 byte & initiates 1 auto-read byte
buffer[length-1] = RF1ADOUTB; // read 1 byte with no further auto-read
Write TXFIFO
RF1AINSTRB = RF_REGWR | TXFIFOWR; //RF_REGWR optional (already included)
for (i=0; i< length; i++) // write length bytes to RF1A Registers
RF1ADINB = buffer[i];
// write byte to TXFIFO
CC430 RF Core
Inside the RF Radio Core
Radio Core State Chart
SLEEP
IDLE
Calibrat
e
Settling
FSTXON
TX
TXFIFO_O
V
RX
Radio Core State Machine
- IDLE
Idle state
- RX
Receive mode
- TX
Transmit mode
- FSTXON
Fast TX Ready
- Calibrate
Freq. Synth. is
calibrating
- Settling
PLL is settling
- RXFIFO_OV
RX FIFO Overflow
- TXFIFO_OV
TX FIFO Overflow
RXFIFO_OV
* Section 3.9 in RF1A UG Chapter
Radio Core Configuration Registers
Address from 0x00 to 0x29
Data Rate Programming
• The TX & RX data rate is programmable from
1.2 to 500 kBaud using the following registers:
– MDMCFG3.DRATE_M
– MDMCFG4.DRATE_E
• Given a data rate, the following equations can be used to
find suitable values for DRATE_M & DRATE_E:
NOTE: If DRATE_M is rounds to 256, increment DRATE_E & use DRATE_M = 0
Frequency Programming
• Desired channel spacing is programmed with:
– MDMCFG0.CHANSPC_M (mantissa)
– MDMCFG0.CHANSPC_E (exponent)
– Maximum channel spacing for 26-MHz xtal is 405 kHz
• Base frequency – center of the lowest freq. chann.
– FREQ2, FREQ1, FREQ0 registers
• Desired 8-bit channel number, CHANNR.CHAN, is multiplied by the
channel offset to attain carrier frequency:
• IF frequency
– SMARTRF Studio calculated appropriate IF freq
– Programmed into FSCTRL1.FREQ_IF
Receiver Channel Filter Bandwidth
• Receiver channel filter is programmable to match different
channel width requirements
– Best performance when: signal BW < 80% * channel BW
• Programmable using
– MDMCFG4.CHANBW_E
– MDMCFG4.CHANBW_M
• UG Example:
– With the channel filter bandwidth set to 500 kHz, the signal should
stay within 80% of 500 kHz, which is 400 kHz. Assuming 915-MHz
frequency and ±20-ppm frequency uncertainty for both the
transmitting device and the receiving device, the total frequency
uncertainty is ±40 ppm of 915 MHz, which is ±37 kHz. If the whole
transmitted signal bandwidth is to be received within 400 kHz, the
transmitted signal bandwidth should be maximum 400 kHz – (2 x
37 kHz), which is 326 kHz.
Packet Handling Support
• Built-in support for packet handling protocol:
– Programmable # of preamble bytes
– 8, 16, or 32 sync word bits (programmable quality thresholds)
• Flexible packet length (Variable, fixed, infinite)
• Optional address byte and CRC-filtering
• Data whitening for improved sensitivity
Preamble & Sync Bits
• Preamble and sync word qualifier mode is programmed using
MDMCFG2.SYNC_MODE:
Recommendation:
If ( Data Rate != 500 kbps)
{
4-byte preamble +
4-byte sync word }
Else
{
8-byte preamble +
4-byte sync word }
• The preamble provides bit-synchronization
– Programmable length  MDMCFG1.NUM_PREAMBLE
– Preamble Quality Threshold  PKTCTRL1.PQT x 4
• The sync word provides byte-synchronization
– Programmable value  SYNC1 & SYNC0
– Set SYNC1 to preamble sequence to emulate a 1-byte sync word
– Use SYNC_MODE = {3,7} to repeat sync word (4-byte sync word)
Packet Filtering Methods – Length
• Fixed packet length
– PKTCTRL0.LENGTH_CONFIG = 0
– Desired packet length set in PKTLEN
• Variable packet length
– PKTCTRL0.LENGTH_CONFIG = 1
– The length of incoming packets is configured
by the first byte after the sync word
– Maximum packet length set in PKTLEN
If receive packet
length > PKTLEN,
Reset RX mode
• Infinite packet length
– PKTCTRL0.LENGTH_CONFIG = 2
– Transmission and reception is continuous until manually turned off
– See CC430 User Guide for suggested algorithm
Packet Filtering Methods - Address & CRC
• Address Filtering
– Checks incoming address byte against contents of ADDR register
– If ADDR check fails, packet is discarded & RX mode is restarted
– The PKTCTRL1.ADR_CHK register sets the address filter mode:
• CRC Filtering
– CRC-16 is executed on the entire payload following the sync word
– Enabled by setting PKTCTRL1.CRC_AUTOFLUSH = 1
– If CRC check fails, entire RX_FIFO is flushed,
MCSCM1.RXOFF_MODE is entered (IDLE, FSTXON, TX, RX)
Modulation Formats – FSK variants
• 2-FSK – A change in frequency identifies a zero or a one in the bit
stream [1]. Deviation set in DEVIATN.DEVIATN_M / DEVIATN_E
• GFSK – Gaussian filter shapes input pulses previous to being
modulated in order to reduce out-of-band noise
• MSK – Difference between higher and lower frequency is identical to
half the bit rate
[1] FSK: Signals and Demodulation, Watkins-Johnson Company
Modulation Formats – ASK Variants
• ASK –
Amplitude Shift Keying –
A change in amplitude
identifies a zero or one in
the bit stream
• OOK –
On-off Keying –
‘Extreme’ ASK
• Modulation programmed in
MDMCFG2.MOD_FORMAT
Output Power Programming
• Two levels of programmability
– PATABLE can hold 8 x output power settings
– 3-bit FREND0.PA_POWER value select PATABLE entry for use
• Provides:
– Flexible PA power ramp up and ramp down at
start & end of transmission, respectively
– ASK modulation shaping
• When OOK modulation is used:
– Logic 0  PATABLE[0]
– Logic 1  PATABLE[1]
• All contents in PATABLE except PATABLE[0] erased
when radio enters SLEEP mode.
• Output power directly & significantly affects current
consumption!
Shaping and PA Ramping
• Up to 8 x PATABLE settings
can be used for ASK
modulation
• Counter rate = 8 x symbol rate
• Counter saturates at FREND0.PA_POWER and 0
RSSI – Received Signal Strength Indicator
• Can be read continuously from RSSI status
register until sync word detected
– RSSI update rate is dependent on
BWchannel & AGCCTRL0.FILTER_LENGTH
– When sync word is detected, RSSI value remains locked
in until radio re-enters RX state
• RSSI value
– Provided in 2’s complement
– To attain absolute power level, must convert the value to
decimal & subtract a typical offset value
• Offset value is different for each baud rate & input power applied
CS – Carrier Sense Support
• Asserted on one of two conditions:
– RSSI above a programmable absolute threshold
(hysteresis included for deassertion)
• Selectable with CARRIER_SENSE_ABS_THR
– RSSI increase a programmable number of dB from one
RSSI sample to the next
• Useful for detecting signals with time-varying noise floor
– Threshold selectable with
AGCCTRL1.CARRIER_SENSE_REL_THR
• Used in TX-if-CCA and optional fast-RX
termination algorithms
CCA, LQI & Packet Handling Support
• CCA – Clear Channel Assesment
– Assertion criteria programmed in MCSM1.CCA_MODE
• LQI – Link Quality Indicator
– Relative measure of link quality based on error between ideal signal &
received signal
• The higher the better
• Affected by and not available for all modulation formats
• RSSI, CRC, LQI available as the last two bytes in RX_FIFO when
PKTCTRL1.APPEND_STATUS = 1
RX pkt status byte 1:
RX pkt status byte 2:
RF1A Interrupts
1. Radio Interface Interrupts
2. Radio Core Interrupts
3. Interrupt Handling + Example
RF1A Interrupts
CPU
RF1A Logical
Channel Registers
RF1A Direct FIFO
Registers *
Radio Core
Instruction Set
INSTR
STAT
Command Strobes
DOUT
Read/Write Instructions
DIN
Direct FIFO
Interface Events
TX FIFO
RX FIFO
Conf. &
Stat
Registers
....
Radio IF Interrupt Vector
RF1A Core
Interrupt Vector
Radio Core Interrupts
RF1AIFIV: RF1A Radio Interface Interrupts
RF1AIV: RF1A Radio Core Interrupts
* Direct FIFO not implemented in PG0.6 *
Radio Interface Interrupts
RF1AIFCTL1: controls all Radio Interface Interrupt Enable (IEs) and Flags (IFG)
RF1AIFIV: Radio Interface Interrupt Vector Register
Radio Interface Interrupts - RFERR
RFERRIFG = 1
OPERR = 1
OUTERR = 1
OPOVERR = 1
LVERR = 1
Not enough or too
many operands
were provided for an
instruction
Not enough data
available for the
executed read access
Attempt to overwrite
operands in RF1ADIN
registers that are still being
processed y the radio core.
Written data is ignored
Attempt to activate
the radio core with a
core voltage level
PMMCOREVx < 2
RF1AERR : contains the IFGs
RF1AERRV = error vector generator register to decode the error condition
Radio Core Interrupts
• 15 interrupts including 3 programmable using IOCFGx
– GDO0
– GDO1
– GDO2
• GDOx signals can be routed to HW output pins
• 4 associated bits for each GDOx interrupt signal:
– RFINx query the actual status of a signal
– RFIESx trigger an interrupt on the positive or negative edge
• RFIESx = 0 > positive edge triggered
• RFIESx = 1 > negative edge triggered
– RFIEx enables the interrupt
– RFIFGx is set when the interrupt occurs
Radio Core Interrupts
Introduction to CC430
1.
2.
3.
4.
5.
6.
7.
8.
Brief introduction to CC430
RF System Introduction
Block Diagram of the CC430F6137 & Peripherals
Derivatives of the CC430F61xx & CC430F51xx Family
RF1A Core & 6xx Core
RF1A Radio Interface
RF1A Changes vs. CC1101
Making RF Easy: Tools, Collateral and Support
CC1101-Based Radio Core Changes
RF_N
FREQ SYNTH
90
RC OSC
MODULATOR
PA
BIAS
RBIAS
XOSC
RF_XIN
RF_XOUT
RXFIFO
SPI
MSP430 Interface
0
INTERFACE TO MCU
RF_P
TXFIFO
ADC
PACKET HANDLER
LNA
FEC / INTERLEAVER
ADC
DEMODULATOR
RADIO CONTROL
sclk
cen
si
so
MAB
MDB
ifclk
rw
byte
ms
CC1101 Digital Features not supported
•
•
•
•
Forward Error Correction (FEC)
Interleaving
Wake-On-Radio (WOR)
Direct TX & RX FIFO access
Changes
•
•
•
•
•
•
•
•
•
•
•
•
Instructions can be executed in SLEEP mode
ACLK is clock source for WOR
SXOFF causes the radio to transition to SLEEP instead of XOFF state
SFTX and SFRX can be issued in SLEEP state in addition to IDLE,
TXFIFO_UNDERFLOW and RXFIFO_OVERFLOW
In Register 0x18 MCSMO, bits 2 and 3 (used as PO_TIMEOUT in CC1101)
are reserved
In Register 0x01 IOCFG1 bit 7, GDO_DS is reserved
Registers 0x27 RCCTRL1 an 0x28 RCCTRL0 are reserved
Support of synch. and asynch. operation via Timer_A
The register 0x30 PARTNUM – CHIP ID reads as 0 (0x00)
The register 0x31 VERSION – CHIP ID reads as 6 (0x06)
The following signals are added to the GDOx multiplexers:
30 (0x1E): RSSI_VALID
31 (0x1F): RX_TIMEOUT
The RC_PD bit in register 0x20 WORCTRL is used as a ACLK_PD bit
The PA_PD and LNA_PD signals behave as intended: PA_PD is low only in
TX States, LNA_PD is low only in RX States
Introduction to CC430
1.
2.
3.
4.
5.
6.
7.
8.
Brief introduction to CC430
RF System Introduction
Block Diagram of the CC430F6137 & Peripherals
Derivatives of the CC430F61xx & CC430F51xx Family
RF1A Core & 6xx Core
RF1A Radio Interface
RF1A Changes vs. CC1101
Making RF Easy: Tools, Collateral and Support
Get to market fast
Software & Tools
Easy to use, low cost hardware and software
tools get customers up and running fast:
RF support: RF reference designs,
SmartRF Studio software, RF packet sniffer,
design notes
Support
Extensive community of third party and academia
technology solution providers
Comprehensive collateral, extensive application notes,
code examples and libraries
Global customer support network – TI has the most feet
on the ground
World wide training options ranging from online to hands
on deep dive technical training
106
EM430F6137RF900
Chronos | Advanced Features at Your Disposal
3D Accelerometer
Pressure & Altitude
Sensor
<1GHz RF
CC430F6137 MCU
Temperature
Sensor
Voltage & Battery
Sensor
CR2032 Battery
eZ430
Programmer
96 segment LCD
Buzzer
2-Wire JTAG Access
RF Access
Point
Chronos
Disassembly
Tool
108
Application Notes – Antennae Design
•
•
•
•
•
•
•
•
•
•
•
DN018 - Range Measurements in an Open Field Environment
ISM-Band and Short Range Device Antennas (Rev. A)
ISM-Band and Short Range Device Regulatory Compliance Overview
DN002 -- Practical Sensitivity Testing
AN058 – Antenna Selection Guide
RSSI interpretation and timing
SRD Antennas
LC Filter with Improved High-Frequency Attenuation
AN039 - Using CC1100/CC1150 in European 433/868 MHz bands
AN50 -- Using the CC1101 in the European 868MHz SRD band
Planned
– Modifying the CC430 EVM to operate at 433 MHz
CC430 Software Tools
SMARTRF Studio
• Automatically configure your RF
settings
• Test the RF front-end
– Continuous RX / TX
– Packet RX / TX
No MSP430 code required!

•

SmartRF Packet Sniffer
• Analyze RF packets in real-time
• Greatly simplifies debugging
• Requires the SmartRF04 or
SmartRF05 HW platform
• Supports SimpliciTI
110
RF Protocol Stacks
CC430
MSP430
5xx Core
RF1A Interface
RF1A Core
(CC1101based)
RF & Antenna
Circuitry
RF Protocol Stack
Some RF protocols have physical layer requirements
Some RF protocols are HW platform independent (SimpliciTI)
Timing/Tasks scheduling  Timer/Extra HW Resources from ‘430 Core
Topology, Range consideration, Regulation
111
CC430 Software Stack Solutions
Smart Metering
Lighting Control
6LoWPAN
868/915 MHz
WMBUS
868 MHz
Building & Home Automation
Asset Tracking
• Mesh / star network
• Point-to-point
communication
Personal Health & Fitness
6LoWPAN
868/915 MHz
BlueRobin™
433/868/915 MHz
Dash7
433 MHz
112
6LoWPAN
•
•
•
•
IPv6 over low-power wireless area networks
Defined by IETF standards
Highly efficient use of code and memory
Direct end-to-end Internet integration
– Multiple topology options
• Low-power RF + IPv6 =
The Wireless Embedded Internet
• Benefits of 6LoWPAN include:
– Open, long-lived, reliable standards
– Easy learning curve
– Transparent Internet integration
– Network maintainability
– Global scalability
– End-to-end data flows
• 6LoWPAN enables a broad range of
applications
– Facility, building and home
automation
– Advanced metering infrastructure
– Lighting Control
Source: 6LoWPAN: The Wireless Embedded Internet,
Shelby & Bormann
113
WMBUS
•
Use case: meter <> meter communication
(Gas, Water Meter, Electricity Meter)
•
Enables a simple star network topology that fits
very well to the applications’ requirements.
•
Sub 1 GHz band (868 MHz)
•
Quality and low power consumption of the
transmission critical
(Gas, Water meter, Battery Life)
114
Dash 7 Technology
•
Ultra-Low Power, Low Bandwidth space
•
Range is scalable, 10 - 2000 m (1.2 mi)
•
433 MHz
•
28 kbps
•
Based on the ISO 18000-7 standard
•
Mandated by U.S. Department of Defense, allied militaries
•
Extendable to multi-hop, sensors, security
•
E.g. - Asset tracking, Tire pressure monitoring
Source: Dash7 Alliance
<Add info regarding specialized HW platform>
115
SimpliciTI Networking Protocol
• Key Features
–
–
–
–
SD
Low Power
Low Cost
Low Data Rate
Easy to learn
AP
D
• Device Configurations
–
–
–
–
Access Point (AP)
Repeater (RE)
Sleeping End Device (SD)
End Device (D)
RE
D
SD
• Topologies
– AP Star
– AP Star w/ Repeaters
– Peer2Peer
D
D
D
116
Support
• MSP430 Wiki
– http://wiki.msp430.com/index.php/C
C430_Sampling_Page
• Community: E2E Forum
– http://community.ti.com/
– CC430 Training Videos
• [email protected] or your local TI
contact
• www.ti.com/msp430
• www.ti.com/cc430
• www.ti.com/simpliciTI
117
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