at91sam7x128 256 pc

Features

Incorporates the ARM7TDMI

®

ARM

®

Thumb

®

Processor

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– EmbeddedICE

In-circuit Emulation, Debug Communication Channel Support

Internal High-speed Flash

– 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes

– 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes

– Single Cycle Access at Up to 30 MHz in Worst Case Conditions

– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed

– Page Programming Time: 6 ms, Including Page Auto-erase,

Full Erase Time: 15 ms

– 10,000 Write Cycles, 10-year Data Retention Capability,

Sector Lock Capabilities, Flash Security Bit

– Fast Flash Programming Interface for High Volume Production

Internal High-speed SRAM, Single-cycle Access at Maximum Speed

– 64 Kbytes (AT91SAM7X256)

– 32 Kbytes (AT91SAM7X128)

Memory Controller (MC)

– Embedded Flash Controller, Abort Status and Misalignment Detection

Reset Controller (RSTC)

– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout

Detector

– Provides External Reset Signal Shaping and Reset Source Status

Clock Generator (CKGR)

– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL

Power Management Controller (PMC)

– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and

Idle Mode

– Four Programmable External Clock Signals

Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources

– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt

Protected

Debug Unit (DBGU)

– 2-wire UART and Support for Debug Communication Channel interrupt,

Programmable ICE Access Prevention

Periodic Interval Timer (PIT)

– 20-bit Programmable Counter plus 12-bit Interval Counter

Windowed Watchdog (WDT)

– 12-bit key-protected Programmable Counter

– Provides Reset or Interrupt Signals to the System

– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

Real-time Timer (RTT)

– 32-bit Free-running Counter with Alarm

– Runs Off the Internal RC Oscillator

Two Parallel Input/Output Controllers (PIO)

– Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os

– Input Change Interrupt Capability on Each I/O Line

– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output

AT91 ARM

®

Thumb

®

-based

Microcontrollers

AT91SAM7X256/

AT91SAM7X128

Preliminary

6120D–ATARM–02-Feb-06

Thirteen Peripheral DMA Controller (PDC) Channels

One USB 2.0 Full Speed (12 Mbits per second) Device Port

– On-chip Transceiver, 1352-byte Configurable Integrated FIFOs

One Ethernet MAC 10/100 base-T

– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)

– Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive

One Part 2.0A and Part 2.0B Compliant CAN Controller

– Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter

One Synchronous Serial Controller (SSC)

– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter

– I²S Analog Interface Support, Time Division Multiplex Support

– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)

– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation

– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support

– Full Modem Line Support on USART1

Two Master/Slave Serial Peripheral Interfaces (SPI)

– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects

One Three-channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel

– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

One Four-channel 16-bit Power Width Modulation Controller (PWMC)

One Two-wire Interface (TWI)

– Master Mode Support Only, All Two-wire Atmel EEPROMs Supported

One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os

SAM-BA

Boot Assistance

– Default Boot program

– Interface with SAM-BA Graphic User Interface

IEEE

®

1149.1 JTAG Boundary Scan on All Digital Pins

5V-tolerant I/Os, Including Four High-current Drive I/O lines, Up to 16 mA Each

Power Supplies

– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components

– 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply

– 1.8V VDDCORE Core Power Supply with Brownout Detector

Fully Static Operation: Up to 55 MHz at 1.65V and 85

°

C Worst Case Conditions

Available in a 100-lead LQFP Green Package

2

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

1.

Description

Atmel's AT91SAM7X256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 256/128 Kbyte high-speed Flash and

64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC and a CAN controller. A complete set of system functions minimizes the number of external components.

The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality.

The AT91SAM7X256/128 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.

By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of peripheral functions, including USART, SPI, CAN Controller, Ethernet MAC, Timer Counter, RTT and Analog-to-Digital Converters on a monolithic chip, the AT91SAM7X256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring communication over, for example, Ethernet, CAN wired and Zigbee

wireless networks.

2.

Configuration Summary of the AT91SAM7X256 and AT91SAM7X128

The AT91SAM7X256 and AT91SAM7X128 differ only in memory sizes.

Table 2-1 summarizes

the configurations of the two devices.

Table 2-1.

Device

AT91SAM7X256

AT91SAM7X128

Configuration Summary

Flash

256K bytes

128K bytes

SRAM

64K bytes

32K bytes

3

6120D–ATARM–02-Feb-06

3.

AT91SAM7X256/128 Block Diagram

Figure 3-1.

AT91SAM7X256/128 Block Diagram

TDI

TDO

TMS

TCK

JTAGSEL

TST

FIQ

IRQ0-IRQ1

DRXD

DTXD

PCK0-PCK3

PLLRC

XIN

XOUT

VDDCORE

VDDFLASH

VDDCORE

NRST

JTAG

SCAN

ICE

System Controller

AIC

DBGU

PDC

PDC

PLL

OSC

RCOSC

BOD

POR

PMC

Reset

Controller

ARM7TDMI

Processor

Memory Controller

Embedded

Flash

Controller

Address

Decoder

Abort

Status

Misalignment

Detection

Peripheral Bridge

Peripheral DMA

Controller

13 Channels

DTR1

RI1

SPI0_NPCS0

SPI0_NPCS1

SPI0_NPCS2

SPI0_NPCS3

SPI0_MISO

SPI0_MOSI

SPI0_SPCK

RXD0

TXD0

SCK0

RTS0

CTS0

RXD1

TXD1

SCK1

RTS1

CTS1

DCD1

DSR1

SPI1_NPCS0

SPI1_NPCS1

SPI1_NPCS2

SPI1_NPCS3

SPI1_MISO

SPI1_MOSI

SPI1_SPCK

ADTRG

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

ADVREF

PIOA

PIT

WDT

RTT

PIOB

APB

USART0

PDC

PDC

PDC

USART1

PDC

PDC

SPI0

PDC

PDC

SPI1

PDC

PDC

ADC

1.8 V

Voltage

Regulator

SRAM

64/32 Kbytes

Flash

256/128 Kbytes

ROM

Fast Flash

Programming

Interface

SAM-BA

DMA

FIFO

Ethernet MAC 10/100

FIFO

USB Device

PWMC

PDC

SSC

PDC

Timer Counter

TC0

TC1

TC2

TWI

CAN

VDDIN

GND

VDDOUT

VDDCORE

VDDIO

VDDFLASH

ERASE

PGMRDY

PGMNVALID

PGMNOE

PGMCK

PGMM0-PGMM3

PGMD0-PGMD15

PGMNCMD

PGMEN0-PGMEN1

PWM0

PWM1

PWM2

PWM3

TF

TK

TD

RD

RK

RF

TCLK0

TCLK1

TCLK2

TIOA0

TIOB0

TIOA1

TIOB1

TIOA2

TIOB2

TWD

TWCK

CANRX

CANTX

ETXCK-ERXCK-EREFCK

ETXEN-ETXER

ECRS-ECOL, ECRSDV

ERXER-ERXDV

ERX0-ERX3

ETX0-ETX3

EMDC

EMDIO

EF100

VDDFLASH

DDM

DDP

4

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

4.

Signal Description

Table 4-1.

Signal Name

Signal Description List

VDDIN

VDDOUT

VDDFLASH

VDDIO

VDDCORE

VDDPLL

GND

XIN

XOUT

PLLRC

PCK0 - PCK3

TCK

TDI

TDO

TMS

JTAGSEL

ERASE

NRST

TST

DRXD

DTXD

IRQ0 - IRQ1

FIQ

PA0 - PA30

PB0 - PB30

Function Type

Power

Voltage Regulator and ADC Power

Supply Input

Voltage Regulator Output

Flash and USB Power Supply

I/O Lines Power Supply

Core Power Supply

PLL

Ground

Main Oscillator Input

Main Oscillator Output

PLL Filter

Power

Power

Power

Power

Power

Power

Ground

Clocks, Oscillators and PLLs

Input

Programmable Clock Output

Output

Output

ICE and JTAG

Input

Test Clock

Test Data In

Test Data Out

Test Mode Select

JTAG Selection

Input

Input

Output

Input

Flash Memory

Input

Flash and NVM Configuration Bits Erase

Command

Reset/Test

Input

I/O Microcontroller Reset

Test Mode Select

Debug Receive Data

Debug Transmit Data

External Interrupt Inputs

Fast Interrupt Input

Parallel IO Controller A

Parallel IO Controller B

Input

Debug Unit

Input

Output

AIC

Input

Input

PIO

I/O

I/O

Active

Level Comments

High

Low

High

3V to 3.6V

1.85V

3V to 3.6V

3V to 3.6V

1.65V to 1.95V

1.65V to 1.95V

No pull-up resistor

No pull-up resistor.

No pull-up resistor.

Pull-down resistor.

Pull-down resistor

Pull-Up resistor, Open Drain

Output

Pull-down resistor

Pulled-up input at reset

Pulled-up input at reset

5

6120D–ATARM–02-Feb-06

Table 4-1.

Signal Description List (Continued)

Signal Name

DDM

DDP

SCK0 - SCK1

TXD0 - TXD1

RXD0 - RXD1

RTS0 - RTS1

CTS0 - CTS1

DCD1

DTR1

DSR1

RI1

Function

USB Device Port Data -

USB Device Port Data +

Serial Clock

Transmit Data

Receive Data

Request To Send

Clear To Send

Data Carrier Detect

Data Terminal Ready

Data Set Ready

Ring Indicator

Type

USB Device Port

Analog

Analog

USART

I/O

I/O

Input

Output

Input

Input

Output

Input

TD

RD

TK

RK

TF

RF

Transmit Data

Receive Data

Transmit Clock

Receive Clock

Transmit Frame Sync

Receive Frame Sync

Input

Synchronous Serial Controller

Output

Input

I/O

I/O

I/O

I/O

TCLK0 - TCLK2

TIOA0 - TIOA2

TIOB0 - TIOB2

External Clock Inputs

I/O Line A

I/O Line B

Timer/Counter

Input

I/O

I/O

PWM0 - PWM3 PWM Channels

PWM Controller

Output

SPIx_MISO

SPIx_MOSI

SPIx_SPCK

SPIx_NPCS0

Master In Slave Out

Master Out Slave In

SPI Serial Clock

Serial Peripheral Interface - SPIx

SPI Peripheral Chip Select 0

SPIx_NPCS1-NPCS3 SPI Peripheral Chip Select 1 to 3

I/O

I/O

I/O

I/O

Output

Two-wire Interface

TWD

TWCK

Two-wire Serial Data

Two-wire Serial Clock

I/O

I/O

Active

Level

Low

Low

Comments

6

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

EREFCK

ETXCK

ERXCK

ETXEN

ETX0 - ETX3

ETXER

ERXDV

ECRSDV

ERX0 - ERX3

ERXER

ECRS

ECOL

EMDC

EMDIO

EF100

Table 4-1.

Signal Name

AD0-AD3

AD4-AD7

ADTRG

ADVREF

PGMEN0-PGMEN1

PGMM0-PGMM3

PGMD0-PGMD15

PGMRDY

PGMNVALID

PGMNOE

PGMCK

PGMNCMD

CANRX

CANTX

Signal Description List (Continued)

Function

Analog Inputs

Analog Inputs

ADC Trigger

ADC Reference

Programming Enabling

Programming Mode

Programming Data

Programming Ready

Data Direction

Programming Read

Programming Clock

Programming Command

Type

Analog-to-Digital Converter

Analog

Analog

Input

Analog

Fast Flash Programming Interface

Input

Input

I/O

Output

Output

Input

Input

Input

CAN Input

CAN Output

Reference Clock

Transmit Clock

Receive Clock

Transmit Enable

Transmit Data

Transmit Coding Error

Receive Data Valid

Carrier Sense and Data Valid

CAN Controller

Input

Output

Ethernet MAC 10/100

Input

Input

Input

Output

Output

Output

Input

Input

Receive Data

Receive Error

Carrier Sense

Collision Detected

Management Data Clock

Management Data Input/Output

Force 100 Mbits/sec.

Input

Input

Input

Input

Output

I/O

Output

Active

Level

High

Low

Low

Low

High

Comments

Digital pulled-up inputs at reset

Analog Inputs

RMII only

MII only

MII only

ETX0 - ETX1 only in RMII

MII only

MII only

RMII only

ERX0 - ERX1 only in RMII

MII only

MII only

RMII only

7

6120D–ATARM–02-Feb-06

5.

Package

The AT91SAM7X256/128 is available in 100-lead LQFP package.

5.1

100-lead LQFP Mechanical Overview

Figure 5-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip-

tion is given in the Mechanical Characteristics section of the full datasheet.

Figure 5-1.

100-lead LQFP Package Pinout (Top View)

75

51

76

50

100

1

25

26

5.2

AT91SAM7X256/128 Pinout

Table 5-1.

1

2

15

16

17

18

11

12

13

14

7

8

9

10

5

6

3

4

23

24

25

19

20

21

22

Pinout in 100-lead TQFP Package

ADVREF

GND

AD4

AD5

AD6

AD7

VDDOUT

VDDIN

PB27/AD0

PB28/AD1

PB29/AD2

PB30/AD3

PA8/PGMM0

PA9/PGMM1

VDDCORE

GND

VDDIO

PA10/PGMM2

PA11/PGMM3

PA12/PGMD0

PA13/PGMD1

PA14/PGMD2

PA15/PGMD3

PA16/PGMD4

PA17/PGMD5

26

27

40

41

42

43

36

37

38

39

32

33

34

35

28

29

30

31

48

49

50

44

45

46

47

PA18/PGMD6

PB9

PB8

PB14

PB13

PB6

GND

VDDIO

PB5

PB15

PB17

VDDCORE

PB7

PB12

PB0

PB1

PB2

PB3

PB10

PB11

PA19/PGMD7

PA20/PGMD8

VDDIO

PA21/PGMD9

PA22/PGMD10

8

63

64

65

66

59

60

61

62

55

56

57

58

51

52

53

54

71

72

73

74

75

67

68

69

70

AT91SAM7X256/128 Preliminary

TDI

GND

PB16

PB4

PA23/PGMD11

PA24/PGMD12

NRST

TST

PA25/PGMD13

PA26/PGMD14

VDDIO

VDDCORE

PB18

PB19

PB20

PB21

PB22

GND

PB23

PB24

PB25

PB26

PA27/PGMD15

PA28

PA29

88

89

90

91

84

85

86

87

80

81

82

83

76

77

78

79

96

97

98

99

100

92

93

94

95

TDO

JTAGSEL

TMS

TCK

PA30

PA0/PGMEN0

PA1/PGMEN1

GND

VDDIO

PA3

PA2

VDDCORE

PA4/PGMNCMD

PA5/PGMRDY

PA6/PGMNOE

PA7/PGMNVALID

ERASE

DDM

DDP

VDDFLASH

GND

XIN/PGMCK

XOUT

PLLRC

VDDPLL

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

6.

Power Considerations

6.1

Power Supplies

The AT91SAM7X256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are:

• VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V,

3.3V nominal. In order to decrease current consumption , if the voltage regulator and the

ADC are not used, VDDIN, ADVREF, AD5, AD6 and AD7 should be connected to GND. In this case, VDDOUT should be left unconnected.

• VDDOUT pin. It is the output of the 1.8V voltage regulator.

• VDDIO pin. It powers the I/O lines; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDFLASH pin. It powers the USB transceivers and a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V,

1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly.

• VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the

VDDOUT pin.

No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.

6.2

Power Consumption

The AT91SAM7X256/128 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current.

The dynamic power consumption on VDDCORE is less than 90 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.

6.3

Voltage Regulator

The AT91SAM7X256/128 embeds a voltage regulator that is managed by the System

Controller.

In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current.

The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA static current and draws 1 mA of output current.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or

1 nF) NPO capacitor should be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and GND.

9

6120D–ATARM–02-Feb-06

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.

6.4

Typical Powering Schematics

The AT91SAM7X256/128 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL.

Figure 6-1 shows

the power schematics to be used for USB bus-powered systems.

Figure 6-1.

3.3V System Single Power Supply Schematic

VDDFLASH

Power Source ranges from 4.5V (USB) to 18V

DC/DC Converter

3.3V

VDDIO

VDDIN

Voltage

Regulator

VDDOUT

VDDCORE

VDDPLL

10

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

7.

I/O Lines Considerations

7.1

JTAG Port Pins

TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor.

TDO is an output, driven at up to VDDIO, and has no pull-up resistor.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The

JTAGSEL pin integrates a permanent pull-down resistor of about 15 k

Ω to GND, so that it can be left unconnected for normal operations.

7.2

Test Pin

T h e T S T p i n i s u s e d f o r m a n u f a c t u r i n g t e s t o r f a s t p r o g r a m m i n g m o d e o f t h e

AT91SAM7X256/128 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 k

to GND, so that it can be left unconnected for normal operations.

To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low.

Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.

7.3

Reset Pin

The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset all the components of the system.

The NRST pin integrates a permanent pull-up resistor to VDDIO

.

7.4

ERASE Pin

The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 k

to GND, so that it can be left unconnected for normal operations.

This pin is debounced by the RC oscillator to improve the glitch tolerance. Minimum debouncing time is 200 ms.

7.5

PIO Controller Lines

All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers.

5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset.

11

6120D–ATARM–02-Feb-06

7.6

I/O Lines Current Drawing

The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to

16 mA permanently.

The remaining I/O lines can draw only 8 mA.

However, the total current drawn by all the I/O lines cannot exceed 200 mA.

12

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

8.

Processor and Architecture

8.1

ARM7TDMI Processor

• RISC processor based on ARMv4T Von Neumann architecture

– Runs at up to 55 MHz, providing 0.9 MIPS/MHz

• Two instruction sets

– ARM

®

high-performance 32-bit instruction set

– Thumb

®

high code density 16-bit instruction set

• Three-stage pipeline architecture

– Instruction Fetch (F)

– Instruction Decode (D)

– Execute (E)

8.2

Debug and Test Features

• Integrated EmbeddedICE

(embedded in-circuit emulator)

– Two watchpoint units

– Test access port accessible through a JTAG protocol

– Debug communication channel

• Debug Unit

– Two-pin UART

– Debug communication channel interrupt handling

– Chip ID Register

• IEEE1149.1 JTAG Boundary-scan on all digital pins

8.3

Memory Controller

• Programmable Bus Arbiter

– Handles requests from the ARM7TDMI, the Ethernet MAC and the Peripheral DMA

Controller

• Address decoder provides selection signals for

– Three internal 1 Mbyte memory areas

– One 256 Mbyte embedded peripheral area

• Abort Status Registers

– Source, Type and all parameters of the access leading to an abort are saved

– Facilitates debug by detection of bad pointers

• Misalignment Detector

– Alignment checking of all data accesses

– Abort generation in case of misalignment

• Remap Command

– Remaps the SRAM in place of the embedded non-volatile memory

– Allows handling of dynamic exception vectors

13

6120D–ATARM–02-Feb-06

• Embedded Flash Controller

– Embedded Flash interface, up to three programmable wait states

– Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states

– Key-protected program, erase and lock/unlock sequencer

– Single command for erasing, programming and locking operations

– Interrupt generation in case of forbidden operation

8.4

Peripheral DMA Controller

• Handles data transfer between peripherals and memories

• Thirteen channels

– Two for each USART

– Two for the Debug Unit

– Two for the Serial Synchronous Controller

– Two for each Serial Peripheral Interface

– One for the Analog-to-digital Converter

• Low bus arbitration overhead

– One Master Clock cycle needed for a transfer from memory to peripheral

– Two Master Clock cycles needed for a transfer from peripheral to memory

• Next Pointer management for reducing interrupt latency requirements

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AT91SAM7X256/128 Preliminary

9.

Memory

9.1

AT91SAM7X256

• 256 Kbytes of Flash Memory

– 1024 pages of 256 bytes

– Fast access time, 30 MHz single-cycle access in Worst Case conditions

– Page programming time: 6 ms, including page auto-erase

– Page programming without auto-erase: 3 ms

– Full chip erase time: 15 ms

– 10,000 write cycles, 10-year data retention capability

– 16 lock bits, each protecting 16 sectors of 64 pages

– Protection Mode to secure contents of the Flash

• 64 Kbytes of Fast SRAM

– Single-cycle access at full speed

9.2

AT91SAM7X128

• 128 Kbytes of Flash Memory

– 512 pages of 256 bytes

– Fast access time, 30 MHz single-cycle access in Worst Case conditions

– Page programming time: 6 ms, including page auto-erase

– Page programming without auto-erase: 3 ms

– Full chip erase time: 15 ms

– 10,000 write cycles, 10-year data retention capability

– 8 lock bits, each protecting 8 sectors of 64 pages

– Protection Mode to secure contents of the Flash

• 32 Kbytes of Fast SRAM

– Single-cycle access at full speed

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6120D–ATARM–02-Feb-06

9.3

Memory Mapping

9.3.1

Internal RAM

• The AT91SAM7X256 embeds a high-speed 64-Kbyte SRAM bank

• The AT91SAM7X128 embeds a high-speed 32-Kbyte SRAM bank.

After reset and until the Remap Command is performed, the SRAM is only accessible at address

0x0020 0000. After Remap, the SRAM also becomes available at address 0x0.

9.3.2

9.3.3

Internal ROM

The AT91SAM7X256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains FFPI and SAM-BA program.

Internal Flash

• The AT91SAM7X256 features one bank of 256 Kbytes of Flash

• The AT91SAM7X128 features one bank of 128 Kbytes of Flash.

At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command.

A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the

Flash.

This GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.

Setting the GPNVM Bit 2 selects the boot from the Flash. Asserting ERASE clears the GPNVM

Bit 2 and thus selects the boot from the ROM by default.

Figure 9-1.

Internal Memory Mapping with GPNVM Bit 2 = 0 (default)

256M Bytes

0x0000 0000

0x000F FFFF

0x0010 0000

0x001F FFFF

0x0020 0000

0x002F FFFF

0x0030 0000

ROM Before Remap

SRAM After Remap

Internal FLASH

Internal SRAM

1 M Bytes

1 M Bytes

1 M Bytes

Internal ROM

1 M Bytes

0x003F FFFF

0x0040 0000

252 M Bytes

Undefined Areas

(Abort)

0x0FFF FFFF

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AT91SAM7X256/128 Preliminary

Figure 9-2.

Internal Memory Mapping with GPNVM Bit 2 = 1

256M Bytes

0x0000 0000

0x000F FFFF

0x0010 0000

0x001F FFFF

0x0020 0000

0x002F FFFF

0x0030 0000

Flash Before Remap

SRAM After Remap

Internal FLASH

Internal SRAM

Internal ROM

0x003F FFFF

0x0040 0000

Undefined Areas

(Abort)

0x0FFF FFFF

1 M Bytes

1 M Bytes

1 M Bytes

1 M Bytes

252 M Bytes

9.4

Embedded Flash

9.4.1

Flash Overview

• The Flash of the AT91SAM7X256 is organized in 1024 pages of 256 bytes. It reads as 65,536

32-bit words.

• The Flash of the AT91SAM7X128 is organized in 512 pages of 256 bytes. It reads as 32,768

32-bit words.

The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.

The Flash benefits from the integration of a power reset cell and from the brownout detector.

This prevents code corruption during power supply changes, even in the worst conditions.

When Flash is not used (read or write access), it is automatically placed into standby mode.

9.4.2

Embedded Flash Controller

The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows:

• programming of the access parameters of the Flash (number of wait states, timings, etc.)

• starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc.

• getting the end status of the last command

• getting error status

• programming interrupts on the end of the last commands or on errors

The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode.

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6120D–ATARM–02-Feb-06

9.4.3

9.4.3.1

Lock Regions

AT91SAM7X256

The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7X256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16

Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 16 NVM bits are software programmable through the EFC User Interface. The command

“Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

9.4.3.2

9.4.4

9.4.5

AT91SAM7X128

The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7X128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16

Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 8 NVM bits are software programmable through the EFC User Interface. The command “Set

Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

Security Bit Feature

The AT91SAM7X256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast

Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.

This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User

Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted.

It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.

As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.

Non-volatile Brownout Detector Control

Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state.

These two GPNVM bits can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.

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AT91SAM7X256/128 Preliminary

9.4.6

• GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.

• The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the

GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.

Calibration Bits

Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.

9.5

Fast Flash Programming Interface

The Fast Flash Programming Interface allows programming the device through either a serial

JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.

The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.

The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high.

9.6

SAM-BA Boot Assistant

The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program insitu the on-chip Flash memory.

The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device

Port.

• Communication via the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-detection.

• Communication via the USB Device Port is limited to an 18.432 MHz crystal.

The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).

The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when the GPNVM Bit 2 is set to 0.

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6120D–ATARM–02-Feb-06

10. System Controller

The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset.

Figure 10-1. System Controller Block Diagram

System Controller jtag_nreset

Boundary Scan

TAP Controller

NRST

XIN

XOUT

PLLRC

PA0-PA30

PB0-PB30 irq0-irq1 fiq periph_irq[2..19]

Advanced

Interrupt

Controller int pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq

MCK periph_nreset

Debug

Unit dbgu_irq force_ntrst dbgu_txd dbgu_rxd

MCK debug periph_nreset

Periodic

Interval

Timer pit_irq

SLCK periph_nreset

SLCK debug idle proc_nreset cal gpnvm[0] en

BOD

POR gpnvm[1] flash_wrdis ice_nreset jtag_nreset flash_poe

Real-Time

Timer

Watchdog

Timer bod_rst_en

Reset

Controller wdt_fault

WDRPROC rtt_irq wdt_irq periph_nreset proc_nreset rstc_irq

Voltage

Regulator

Mode

Controller

SLCK nirq nfiq proc_nreset

PCK debug ice_nreset force_ntrst flash_poe flash_wrdis cal gpnvm[0..2] efc_irq

MCK proc_nreset cal security_bit standby

ARM7TDMI

Embedded

Flash

Memory

Controller

Voltage

Regulator

RCOSC

SLCK

OSC

MAINCK

Power

Management

Controller periph_clk[2..18] pck[0-3]

PCK

UDPCK

MCK

UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend

USB Device

Port

PLL

PLLCK int periph_nreset usb_suspend pmc_irq idle periph_clk[4..19] periph_nreset

Embedded

Peripherals periph_nreset periph_clk[2-3] dbgu_rxd

PIO

Controller periph_irq{2-3] irq0-irq1 fiq dbgu_txd periph_irq[4..19] in out enable

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AT91SAM7X256/128 Preliminary

10.1

System Controller Mapping

The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF.

Figure 10-2

shows the mapping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space.

Figure 10-2. System Controller Mapping

Address

0xFFFF F000

Peripheral Peripheral Name Size

AIC Advanced Interrupt Controller 512 Bytes/128 registers

0xFFFF F1FF

0xFFFF F200

DBGU Debug Unit 512 Bytes/128 registers

0xFFFF F3FF

0xFFFF F400

PIOA PIO Controller A 512 Bytes/128 registers

0xFFFF F5FF

0xFFFF F600

PIOB PIO Controller B 512 Bytes/128 registers

0xFFFF F7FF

0xFFFF F800

Reserved

0xFFFF FBFF

0xFFFF FC00

0xFFFF FCFF

0xFFFF FD00

0xFFFF FD0F

0xFFFF FD20

0xFFFF FC2F

0xFFFF FD30

0xFFFF FC3F

0xFFFF FD40

0xFFFF FD4F

0xFFFF FD60

0xFFFF FC6F

0xFFFF FD70

0xFFFF FEFF

0xFFFF FF00

PMC

RSTC

Reserved

RTT

PIT

WDT

Reserved

VREG

Reserved

Power Management Controller

Reset Controller

Real-time Timer

Periodic Interval Timer

Watchdog Timer

256 Bytes/64 registers

16 Bytes/4 registers

16 Bytes/4 registers

16 Bytes/4 registers

16 Bytes/4 registers

Voltage Regulator Mode Controller 4 Bytes/1 register

MC

Memory Controller 256 Bytes/64 registers

0xFFFF FFFF

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6120D–ATARM–02-Feb-06

10.2

Reset Controller

• Based on one power-on reset cell and one brownout detector

• Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog

Reset, Brownout Reset

• Controls the internal resets and the NRST pin output

• Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement.

10.2.1

Brownout Detector and Power-on Reset

The AT91SAM7X256/X128 embeds one brownout detection circuit and a power-on reset cell.

The power-on reset is supplied with and monitors VDDCORE.

Both signals are provided to the Flash to prevent any code corruption during power-up or powerdown sequences or if brownouts occur on the power supplies.

The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device.

The brownout detector monitors the VDDCORE and VDDFLASH levels during operation by comparing them to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE or VDDFLASH.

When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot18-, defined as Vbot18 - hyst/2), the brownout output is immediately activated.

When VDDCORE increases above the trigger level (Vbot18+, defined as Vbot18 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs.

The VDDCORE threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of

± 2% and is factory calibrated.

When the brownout detector is enabled and VDDFLASH decreases to a value below the trigger level (Vbot33-, defined as Vbot33 - hyst/2), the brownout output is immediately activated.

When VDDFLASH increases above the trigger level (Vbot33+, defined as Vbot33 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs.

The VDDFLASH threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 2.80V with an accuracy of

± 3.5% and is factory calibrated.

The brownout detector is low-power, as it consumes less than 28 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash.

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AT91SAM7X256/128 Preliminary

10.3

Clock Generator

The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics:

• RC Oscillator ranges between 22 KHz and 42 KHz

• Main Oscillator frequency ranges between 3 and 20 MHz

• Main Oscillator can be bypassed

• PLL output ranges between 80 and 200 MHz

It provides SLCK, MAINCK and PLLCK.

Figure 10-3. Clock Generator Block Diagram

Clock Generator

Embedded

RC

Oscillator

Slow Clock

SLCK

XIN

XOUT

Main

Oscillator

Main Clock

MAINCK

PLLRC

PLL and

Divider

Status Control

Power

Management

Controller

PLL Clock

PLLCK

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6120D–ATARM–02-Feb-06

10.4

Power Management Controller

The Power Management Controller uses the Clock Generator outputs to provide:

• the Processor Clock PCK

• the Master Clock MCK

• the USB Clock UDPCK

• all the peripheral clocks, independently controllable

• four programmable clock outputs

The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device.

The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt.

Figure 10-4. Power Management Controller Block Diagram

SLCK

MAINCK

PLLCK

Master Clock Controller

Prescaler

/1,/2,/4,...,/64

Processor

Clock

Controller

Idle Mode

Peripherals

Clock Controller

ON/OFF

PCK int

MCK periph_clk[2..18]

SLCK

MAINCK

PLLCK

Programmable Clock Controller

Prescaler

/1,/2,/4,...,/64 pck[0..3]

PLLCK

USB Clock Controller

ON/OFF

Divider

/1,/2,/4

UDPCK

10.5

Advanced Interrupt Controller

• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor

• Individually maskable and vectored interrupt sources

– Source 0 is reserved for the Fast Interrupt Input (FIQ)

– Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.)

– Other sources control the peripheral interrupts or external interrupts

– Programmable edge-triggered or level-sensitive internal sources

– Programmable positive/negative edge-triggered or high/low level-sensitive external sources

• 8-level Priority Controller

– Drives the normal interrupt nIRQ of the processor

– Handles priority of the interrupt sources

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

– Higher priority interrupts can be served during service of lower priority interrupt

• Vectoring

– Optimizes interrupt service routine branch and execution

– One 32-bit vector register per interrupt source

– Interrupt vector register reads the corresponding current interrupt vector

• Protect Mode

– Easy debugging by preventing automatic operations

• Fast Forcing

– Permits redirecting any interrupt source on the fast interrupt

• General Interrupt Mask

– Provides processor synchronization on events without triggering an interrupt

10.6

Debug Unit

• Comprises:

– One two-pin UART

– One Interface for the Debug Communication Channel (DCC) support

– One set of Chip ID Registers

– One Interface providing ICE Access Prevention

• Two-pin UART

– USART-compatible User Interface

– Programmable Baud Rate Generator

– Parity, Framing and Overrun Error

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

• Debug Communication Channel Support

– Offers visibility of COMMRX and COMMTX signals from the ARM Processor

• Chip ID Registers

– Identification of the device revision, sizes of the embedded memories, set of peripherals

– Chip ID is 0x275B 0940 (VERSION 0) for AT91SAM7X256

– Chip ID is 0x275A 0740 (VERSION 0) for AT91SAM7X128

10.7

Period Interval Timer

• 20-bit programmable counter plus 12-bit interval counter

10.8

Watchdog Timer

• 12-bit key-protected Programmable Counter running on prescaled SLCK

• Provides reset or interrupt signals to the system

• Counter may be stopped while the processor is in debug state or in idle mode

10.9

Real-time Timer

• 32-bit free-running counter with alarm running on prescaled SLCK

• Programmable 16-bit prescaler for SLCK accuracy compensation

25

6120D–ATARM–02-Feb-06

10.10 PIO Controllers

• Two PIO Controllers, each controlling 31 I/O lines

• Fully programmable through set/clear registers

• Multiplexing of two peripheral functions per I/O line

• For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)

– Input change interrupt

– Half a clock period glitch filter

– Multi-drive option enables driving in open drain

– Programmable pull-up on each I/O line

– Pin data status register, supplies visibility of the level on the pin at any time

• Synchronous output, provides Set and Clear of several I/O lines in a single write

10.11 Voltage Regulator Controller

The purpose of this controller is to select the Power Mode of the Voltage Regulator between

Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).

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AT91SAM7X256/128 Preliminary

11. Peripherals

11.1

Peripheral Mapping

Each peripheral is allocated 16 Kbytes of address space.

Figure 11-1. User Peripheral Mapping

Peripheral Name

0xF000 0000

Reserved

0xFFF9 FFFF

0xFFFA 0000

0xFFFA 3FFF

0xFFFA 4000

TC0, TC1, TC2

Reserved

0xFFFA FFFF

0xFFFB 0000

0xFFFB 3FFF

0xFFFB 4000

UDP

Reserved

0xFFFB 7FFF

0xFFFB 8000

0xFFFB BFFF

0xFFFB C000

0xFFFB FFFF

0xFFFC 0000

0xFFFC 3FFF

0xFFFC 4000

0xFFFC 7FFF

0xFFFC 8000

0xFFFC BFFF

0xFFFC C000

0xFFFC FFFF

0xFFFD 0000

0xFFFD 3FFF

0xFFFD 4000

0xFFFD 7FFF

0xFFFD 8000

0xFFFD BFFF

0xFFFD C000

0xFFFD FFFF

0xFFFE 0000

0xFFFE 3FFF

0xFFFE 4000

0xFFFE 7FFF

0xFFFE 8000

TWI

Reserved

USART0

USART1

Reserved

PWMC

CAN

SSC

ADC

EMAC

SPI0

SPI1

Reserved

0xFFFE FFFF

Timer/Counter 0, 1 and 2

USB Device Port

Two-Wire Interface

Universal Synchronous Asynchronous

Receiver Transmitter 0

Universal Synchronous Asynchronous

Receiver Transmitter 1

PWM Controller

CAN Controller

Serial Synchronous Controller

Analog-to-Digital Converter

Ethernet MAC

Serial Peripheral Interface 0

Serial Peripheral Interface 1

Size

16 Kbytes

16 Kbytes

16 Kbytes

16 Kbytes

16 Kbytes

16 Kbytes

16 Kbytes

16 Kbytes

16 Kbytes

16 Kbytes

16 Kbytes

16 Kbytes

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6120D–ATARM–02-Feb-06

11.2

Peripheral Multiplexing on PIO Lines

The AT91SAM7X256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set.

Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC

Controller.

Table 11-1 on page 29

and Table 11-2 on page 30 defines how the I/O lines of the peripherals A,

B or the analog inputs are multiplexed on the PIO Controller A and PIO Controller B. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application.

Note that some peripheral functions that are output only, may be duplicated in the table.

At reset, all I/O lines are automatically configured as input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected.

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AT91SAM7X256/128 Preliminary

11.3

PIO Controller A Multiplexing

Table 11-1.

Multiplexing on PIO Controller A

PIO Controller A

Peripheral B

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PA30

PA15

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

I/O Line

PA0

PA1

PA2

PA3

PA4

PA5

PA6

SPI0_NPCS3

SPI0_MISO

SPI0_MOSI

SPI0_SPCK

CANRX

CANTX

TF

TK

TD

RD

RK

RF

DRXD

DTXD

FIQ

IRQ0

Peripheral A

RXD0

TXD0

SCK0

RTS0

CTS0

RXD1

TXD1

SCK1

RTS1

CTS1

TWD

TWCK

SPI_NPCS0

SPI0_NPCS1

SPI0_NPCS2

SPI1_NPCS1

SPI1_NPCS2

SPI1_NPCS3

SPI0_NPCS1

SPI0_NPCS2

SPI0_NPCS3

PCK1

IRQ1

TCLK2

SPI1_NPCS0

SPI1_SPCK

SPI1_MOSI

SPI1_MISO

SPI1_NPCS1

SPI1_NPCS2

PCK3

SPI1_NPCS3

PCK2

Comments

High-Drive

High-Drive

High-Drive

High-Drive

Application Usage

Function Comments

29

6120D–ATARM–02-Feb-06

11.4

PIO Controller B Multiplexing

Table 11-2.

Multiplexing on PIO Controller B

PIO Controller A

PB23

PB24

PB25

PB26

PB27

PB28

PB29

PB30

PB15

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

I/O Line

PB0

PB1

PB2

PB3

PB4

PB5

PB6

Peripheral B

PCK0

SPI1_NPCS1

SPI1_NPCS2

TCLK0

SPI0_NPCS1

SPI0_NPCS2

ERXDV/ECRSDV

ECOL

ERXCK

EF100

PWM0

PWM1

PWM2

PWM3

TIOA0

TIOB0

TIOA1

TIOB1

TIOA2

TIOB2

PCK1

PCK2

Peripheral A

ETXCK/EREFCK

ETXEN

ETX0

ETX1

ECRS

ERX0

ERX1

ERXER

EMDC

EMDIO

ETX2

ETX3

ETXER

ERX2

ERX3

SPI1_NPCS3

SPI0_NPCS3

ADTRG

TCLK1

PCK0

PCK1

PCK2

DCD1

DSR1

DTR1

RI1

PWM0

PWM1

PWM2

PWM3

Comments

Application Usage

Function Comments

AD0

AD1

AD2

AD3

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AT91SAM7X256/128 Preliminary

11.5

Peripheral Identifiers

The AT91SAM7X256/128 embeds a wide range of peripherals.

Table 11-3

defines the Peripheral Identifiers of the AT91SAM7X256/128. Unique peripheral identifiers are defined for both the

Advanced Interrupt Controller and the Power Management Controller.

Table 11-3.

Peripheral Identifiers

15

16

17

18 - 29

30

31

11

12

13

14

7

8

9

10

5

6

3

4

1

2

Peripheral ID

0

US0

US1

SSC

TWI

PWMC

UDP

TC0

TC1

Peripheral Mnemonic

AIC

SYSIRQ

(1)

PIOA

PIOB

SPI0

SPI1

TC2

CAN

EMAC

ADC

(1)

Reserved

AIC

AIC

Peripheral Name

Advanced Interrupt Controller

Parallel I/O Controller A

Parallel I/O Controller B

Serial Peripheral Interface 0

Serial Peripheral Interface 1

USART 0

USART 1

Synchronous Serial Controller

Two-wire Interface

Pulse Width Modulation Controller

USB device Port

Timer/Counter 0

Timer/Counter 1

Timer/Counter 2

CAN Controller

Ethernet MAC

Analog-to Digital Converter

Advanced Interrupt Controller

Advanced Interrupt Controller

External

Interrupt

FIQ

IRQ0

IRQ1

Note: 1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The

System Controller and ADC are continuously clocked.

31

6120D–ATARM–02-Feb-06

11.6

Ethernet MAC

• DMA Master on Receive and Transmit Channels

• Compatible with IEEE Standard 802.3

• 10 and 100 Mbit/s operation

• Full- and half-duplex operation

• Statistics Counter Registers

• MII/RMII interface to the physical layer

• Interrupt generation to signal receive and transmit completion

• 28-byte transmit FIFO and 28-byte receive FIFO

• Automatic pad and CRC generation on transmitted frames

• Automatic discard of frames received with errors

• Address checking logic supports up to four specific 48-bit addresses

• Support Promiscuous Mode where all valid received frames are copied to memory

• Hash matching of unicast and multicast destination addresses

• Physical layer management through MDIO interface

• Half-duplex flow control by forcing collisions on incoming frames

• Full-duplex flow control with recognition of incoming pause frames

• Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames

• Multiple buffers per receive and transmit frame

• Jumbo frames up to 10240 bytes supported

11.7

Serial Peripheral Interface

• Supports communication with external serial devices

– Four chip selects with external decoder allow communication with up to 15 peripherals

– Serial memories, such as DataFlash

®

and 3-wire EEPROMs

– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and

Sensors

– External co-processors

• Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select

– Programmable phase and polarity per chip select

– Programmable transfer delays per chip select, between consecutive transfers and between clock and data

– Programmable delay between consecutive transfers

– Selectable mode fault detection

– Maximum frequency at up to Master Clock

11.8

Two-wire Interface

• Master Mode only

• Compatibility with standard two-wire serial memories

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AT91SAM7X256/128 Preliminary

• One, two or three bytes for slave address

• Sequential read/write operations

11.9

USART

• Programmable Baud Rate Generator

• 5- to 9-bit full-duplex synchronous or asynchronous serial communications

– 1, 1.5 or 2 stop bits in Asynchronous Mode

– 1 or 2 stop bits in Synchronous Mode

– Parity generation and error detection

– Framing error detection, overrun error detection

– MSB or LSB first

– Optional break generation and detection

– By 8 or by 16 over-sampling receiver frequency

– Hardware handshaking RTS - CTS

– Modem Signals Management DTR-DSR-DCD-RI on USART1

– Receiver time-out and transmitter timeguard

– Multi-drop Mode with address generation and detection

• RS485 with driver control signal

• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

• IrDA modulation and demodulation

– Communication at up to 115.2 Kbps

• Test Modes

– Remote Loopback, Local Loopback, Automatic Echo

11.10 Serial Synchronous Controller

• Provides serial synchronous communication links used in audio and telecom applications

• Contains an independent receiver and transmitter and a common clock divider

• Offers a configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal

11.11 Timer Counter

• Three 16-bit Timer Counter Channels

– Three output compare or two input capture

• Wide range of functions including:

– Frequency measurement

– Event counting

– Interval measurement

– Pulse generation

33

6120D–ATARM–02-Feb-06

– Delay timing

– Pulse Width Modulation

– Up/down capabilities

• Each channel is user-configurable and contains:

– Three external clock inputs

• Five internal clock inputs, as defined in Table 11-4

Table 11-4.

Timer Counter Clocks Assignment

TC Clock input Clock

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

MCK/2

MCK/8

MCK/32

MCK/128

MCK/1024

– Two multi-purpose input/output signals

– Two global registers that act on all three TC channels

11.12 Pulse Width Modulation Controller

• Four channels, one 16-bit counter per channel

• Common clock generator, providing thirteen different clocks

– One Modulo n counter providing eleven clocks

– Two independent linear dividers working on modulo n counter outputs

• Independent channel programming

– Independent enable/disable commands

– Independent clock selection

– Independent period and duty cycle, with double buffering

– Programmable selection of the output waveform polarity

– Programmable center or left aligned output waveform

11.13 USB Device Port

• USB V2.0 full-speed compliant,12 Mbits per second

• Embedded USB V2.0 full-speed transceiver

• Embedded 1352-byte dual-port RAM for endpoints

• Six endpoints

– Endpoint 0: 8 bytes

– Endpoint 1 and 2: 64 bytes ping-pong

– Endpoint 3: 64 bytes

– Endpoint 4 and 5: 256 bytes ping-pong

– Ping-pong Mode (two memory banks) for bulk endpoints

• Suspend/resume logic

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AT91SAM7X256/128 Preliminary

11.14 CAN Controller

• Fully compliant with CAN 2.0A and 2.0B

• Bit rates up to 1Mbit/s

• Eight object oriented mailboxes each with the following properties:

– CAN Specification 2.0 Part A or 2.0 Part B Programmable for each Message

– Object configurable to receive (with overwrite or not) or transmit

– Local tag and mask filters up to 29-bit identifier/channel

– 32-bit access to data registers for each mailbox data object

– Uses a 16-bit time stamp on receive and transmit message

– Hardware concatenation of ID unmasked bitfields to speedup family ID processing

– 16-bit internal timer for time stamping and network synchronization

– Programmable reception buffer length up to 8 mailbox objects

– Priority management between transmission mailboxes

– Autobaud and listening mode

– Low power mode and programmable wake-up on bus activity or by the application

– Data, remote, error and overload frame handling

11.15 Analog-to-Digital Converter

• 8-channel ADC

• 10-bit 384 Ksamples/sec. Successive Approximation Register ADC

• -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity

• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs

• External voltage reference for better accuracy on low voltage inputs

• Individual enable and disable of each channel

• Multiple trigger sources

– Hardware or software trigger

– External trigger pin

– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger

• Sleep Mode and conversion sequencer

– Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels

• Four of eight analog inputs shared with digital signals

35

6120D–ATARM–02-Feb-06

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AT91SAM7X256/128 Preliminary

12. ARM7TDMI Processor Overview

12.1

Overview

The ARM7TDMI core executes both the 32-bit ARM

®

and 16-bit Thumb

®

instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of

Fetch, Decode, and Execute stages.

The main features of the ARM7tDMI processor are:

• ARM7TDMI Based on ARMv4T Architecture

• Two Instruction Sets

– ARM

®

High-performance 32-bit Instruction Set

– Thumb

®

High Code Density 16-bit Instruction Set

• Three-Stage Pipeline Architecture

– Instruction Fetch (F)

– Instruction Decode (D)

– Execute (E)

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6120D–ATARM–02-Feb-06

12.2

ARM7TDMI Processor

For further details on ARM7TDMI, refer to the following ARM documents:

ARM Architecture Reference Manual (DDI 0100E)

ARM7TDMI Technical Reference Manual (DDI 0210B)

12.2.1

12.2.2

12.2.3

12.2.4

Instruction Type

Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).

Data Type

ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries.

Unaligned data access behavior depends on which instruction is used where.

ARM7TDMI Operating Mode

The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes:

User: The normal ARM program execution state

FIQ: Designed to support high-speed data transfer or channel process

IRQ: Used for general-purpose interrupt handling

Supervisor: Protected mode for the operating system

Abort mode: Implements virtual memory and/or memory protection

System: A privileged user mode for the operating system

Undefined: Supports software emulation of hardware coprocessors

Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources.

ARM7TDMI Registers

The ARM7TDMI processor has a total of 37registers:

• 31 general-purpose 32-bit registers

• 6 status registers

These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer.

At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing.

Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction.

R14 holds the return address after a subroutine call.

R13 is used (by software convention) as a stack pointer.

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AT91SAM7X256/128 Preliminary

Table 12-1.

ARM7TDMI ARM Modes and Registers Layout

User and

System Mode

R12

R13

R14

PC

R8

R9

R10

R11

R4

R5

R6

R7

R0

R1

R2

R3

Supervisor

Mode

R8

R9

R10

R11

R12

R13_SVC

R14_SVC

PC

R4

R5

R6

R7

R0

R1

R2

R3

Abort Mode

R4

R5

R6

R7

R0

R1

R2

R3

R8

R9

R10

R11

R12

R13_ABORT

R14_ABORT

PC

Undefined

Mode

R4

R5

R6

R7

R0

R1

R2

R3

R8

R9

R10

R11

R12

R13_UNDEF

R14_UNDEF

PC

CPSR CPSR

SPSR_SVC

Interrupt

Mode

R8

R9

R10

R11

R12

R13_IRQ

R14_IRQ

PC

R4

R5

R6

R7

R0

R1

R2

R3

CPSR

SPSR_ABORT

CPSR

SPSR_UNDEF

CPSR

SPSR_IRQ

12.2.4.1

Mode-specific banked registers

Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a generalpurpose register to be specified.

Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor.

Modes and Exception Handling

All exceptions have banked registers for R14 and R13.

After an exception, R14 holds the return address for exception processing. This address is used to return after the exception is processed, as well as to address the instruction that caused the exception.

R13 is banked across exception modes to provide each exception handler with a private stack pointer.

The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers.

39

6120D–ATARM–02-Feb-06

Fast Interrupt

Mode

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

PC

R4

R5

R6

R7

R0

R1

R2

R3

CPSR

SPSR_FIQ

12.2.4.2

A seventh processing mode, System Mode, does not have any banked registers. It uses the

User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions.

Status Registers

All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds:

• four ALU flags (Negative, Zero, Carry, and Overflow)

• two interrupt disable bits (one for each type of interrupt)

• one bit to indicate ARM or Thumb execution

• five bits to encode the current processor mode

All five exception modes also have a Saved Program Status Register (SPSR) that holds the

CPSR of the task immediately preceding the exception.

12.2.4.3

12.2.5

Exception Types

The ARM7TDMI

supports five types of exception and a privileged processing mode for each type.

The types of exceptions are:

• fast interrupt (FIQ)

• normal interrupt (IRQ)

• memory aborts (used to implement memory protection or virtual memory)

• attempted execution of an undefined instruction

• software interrupts (SWIs)

Exceptions are generated by internal and external sources.

More than one exception can occur in the same time.

When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state.

To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways:

• by using a data-processing instruction with the S-bit set, and the PC as the destination

• by using the Load Multiple with Restore CPSR instruction (LDM)

ARM Instruction Set Overview

The ARM instruction set is divided into:

• Branch instructions

• Data processing instructions

• Status register transfer instructions

• Load and Store instructions

• Coprocessor instructions

• Exception-generating instructions

ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]).

Table 12-2

gives the ARM instruction mnemonic list.

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AT91SAM7X256/128 Preliminary

12.2.6

Table 12-2.

ARM Instruction Mnemonic List

Mnemonic Operation

MUL

SMULL

SMLAL

MSR

B

BX

LDR

LDRSH

MOV

ADD

SUB

RSB

CMP

TST

AND

EOR

LDRSB

LDRH

LDRB

LDRBT

LDRT

LDM

SWP

MCR

LDC

Move

Add

Subtract

Reverse Subtract

Compare

Test

Logical AND

Logical Exclusive OR

Multiply

Sign Long Multiply

Signed Long Multiply Accumulate

Move to Status Register

Branch

Branch and Exchange

Load Word

Load Signed Halfword

Load Signed Byte

Load Half Word

Load Byte

Load Register Byte with Translation

Load Register with Translation

Load Multiple

Swap Word

Move To Coprocessor

Load To Coprocessor

Mnemonic Operation

ORR

MLA

UMULL

UMLAL

MRS

BL

SWI

STR

CDP

MVN

ADC

SBC

RSC

CMN

TEQ

BIC

STRH

STRB

STRBT

STRT

STM

SWPB

MRC

STC

Coprocessor Data Processing

Move Not

Add with Carry

Subtract with Carry

Reverse Subtract with Carry

Compare Negated

Test Equivalence

Bit Clear

Logical (inclusive) OR

Multiply Accumulate

Unsigned Long Multiply

Unsigned Long Multiply Accumulate

Move From Status Register

Branch and Link

Software Interrupt

Store Word

Store Half Word

Store Byte

Store Register Byte with Translation

Store Register with Translation

Store Multiple

Swap Byte

Move From Coprocessor

Store From Coprocessor

Thumb Instruction Set Overview

The Thumb instruction set is a re-encoded subset of the ARM instruction set.

The Thumb instruction set is divided into:

• Branch instructions

• Data processing instructions

• Load and Store instructions

• Load and Store Multiple instructions

• Exception-generating instruction

In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the

41

6120D–ATARM–02-Feb-06

Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers

8 to 15.

Table 12-3

gives the Thumb instruction mnemonic list.

Table 12-3.

Thumb Instruction Mnemonic List

Mnemonic Operation Mnemonic

ASR

MUL

B

BX

LDR

LDRH

LDRB

LDRSH

LDMIA

PUSH

MOV

ADD

SUB

CMP

TST

AND

EOR

LSL

Move

Add

Subtract

Compare

Test

Logical AND

Logical Exclusive OR

Logical Shift Left

Arithmetic Shift Right

Multiply

Branch

Branch and Exchange

Load Word

Load Half Word

Load Byte

Load Signed Halfword

Load Multiple

Push Register to stack

BL

SWI

STR

STRH

STRB

LDRSB

STMIA

POP

MVN

ADC

SBC

CMN

NEG

BIC

ORR

LSR

ROR

Operation

Move Not

Add with Carry

Subtract with Carry

Compare Negated

Negate

Bit Clear

Logical (inclusive) OR

Logical Shift Right

Rotate Right

Branch and Link

Software Interrupt

Store Word

Store Half Word

Store Byte

Load Signed Byte

Store Multiple

Pop Register from stack

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AT91SAM7X256/128 Preliminary

13. Debug and Test Features

13.1

Description

The AT91SAM7X Series features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin

UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug

Communication Channel.

A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.

13.2

Block Diagram

Figure 13-1. Debug and Test Block Diagram

TMS

TCK

TDI

Boundary

TAP

ICE/JTAG

TAP

Reset and

Test

JTAGSEL

TDO

POR

TST

ARM7TDMI

ICE

PDC

DBGU

DTXD

DRXD

43

6120D–ATARM–02-Feb-06

13.3

Application Examples

13.3.1

Debug Environment

Figure 13-2

shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program.

Figure 13-2. Application Debug Environment Example

Host Debugger

ICE/JTAG

Interface

ICE/JTAG

Connector

AT91SAMSxx

RS232

Connector

AT91SAM7Sxx-based Application Board

Terminal

44

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

13.3.2

Test Environment

Figure 13-3 shows a test environment example. Test vectors are sent and interpreted by the

tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain.

Figure 13-3. Application Test Environment Example

Test Adaptor

Tester

JTAG

Interface

ICE/JTAG

Connector

Chip n Chip 2

AT91SAM7Xxx

Chip 1

AT91SAM7Xxx-based Application Board In Test

13.4

Debug and Test Pin Description

Table 13-1.

Debug and Test Pin List

Pin Name Function

Reset/Test

NRST

TST

TCK

TDI

TDO

TMS

JTAGSEL

DRXD

DTXD

Microcontroller Reset

Test Mode Select

ICE and JTAG

Test Clock

Test Data In

Test Data Out

Test Mode Select

JTAG Selection

Debug Unit

Debug Receive Data

Debug Transmit Data

Type

Input/Output

Input

Active Level

Low

High

Input

Input

Output

Input

Input

Input

Output

45

6120D–ATARM–02-Feb-06

13.5

Functional Description

13.5.1

13.5.2

Test Pin

One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test.

EmbeddedICE

(Embedded In-circuit Emulator)

The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port. The internal state of the

ARM7TDMI is examined through an ICE/JTAG port.

The ARM7TDMI processor contains hardware extensions for advanced debugging features:

• In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system.

• In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI processor.

There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the EmbeddedICE. The scan chains are controlled by the ICE/JTAG port.

EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.

For further details on the EmbeddedICE, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).

13.5.3

13.5.4

Debug Unit

The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum.

The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel. The

Debug Unit allows blockage of access to the system through the ICE interface.

A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration.

The AT91SAM7X256 Debug Unit Chip ID value is 0x275B 0940 on 32-bit width.

The AT91SAM7X128 Debug Unit Chip ID value is 0x275A 0740 on 32-bit width.

For further details on the Debug Unit, see the Debug Unit section.

IEEE 1149.1 JTAG Boundary Scan

IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.

IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds

46

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13.5.4.1

AT91SAM7X256/128 Preliminary

with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1

JTAG-compliant.

It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed.

A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.

JTAG Boundary-scan Register

The Boundary-scan Register (BSR) contains 187 bits that correspond to active pins and associated control signals.

Each AT91SAM7X input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad.

Table 13-2.

AT91SAM7X JTAG Boundary Scan Register

Bit

Number Pin Name Pin Type

175

174

173

172

179

178

177

176

183

182

181

180

187

186

185

184

167

166

165

164

171

170

169

168

PA30/IRQ0/PCK2

PA0/RXD0

PA1/TXD0

PA3/RTS0/SPI1_NPCS2

PA2/SCK0/SPI1_NPCS1

PA4/CTS0/SPI1_NPCS3

PA5/RXD1

PA6/TXD1

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

Associated BSR

Cells

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

CONTROL

INPUT

OUTPUT

47

6120D–ATARM–02-Feb-06

Table 13-2.

AT91SAM7X JTAG Boundary Scan Register (Continued)

Bit

Number

163

Pin Name Pin Type

PA7/SCK1/SPI0_NPCS1 IN/OUT

134

133

132

131

130

138

137

136

135

142

141

140

139

146

145

144

143

150

149

148

147

154

153

152

151

158

157

156

155

162

161

160

159

ERASE IN

PB27/TIOA2/PWM0/AD0 IN/OUT

PB28/TIOB2/PWM1/AD1 IN/OUT

PB29/PCK1/PWM2/AD2 IN/OUT

PB30/PCK2/PWM3/AD3 IN/OUT

PA8/RTS1/SPI0_NPCS2 IN/OUT

PA9/CTS1/SPI0_NPCS3 IN/OUT

PA10/TWD IN/OUT

PA11/TWCK IN/OUT

PA12/SPI0_NPCS0 IN/OUT

PA13/SPI0_NPCS1/PCK1 IN/OUT

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

Associated BSR

Cells

CONTROL

INPUT

OUTPUT

INPUT

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

Table 13-2.

AT91SAM7X JTAG Boundary Scan Register (Continued)

Bit

Number

129

Pin Name Pin Type

PA14/SPI0_NPCS2/IRQ1 IN/OUT

100

99

98

97

104

103

102

101

108

107

106

105

112

111

110

109

116

115

114

113

120

119

118

117

124

123

122

121

128

127

126

125 PA15/SPI0_NPCS3/TCLK2 IN/OUT

PA16/SPI0_MISO IN/OUT

PA17/SPI0_MOSI IN/OUT

PA18/SPI0_SPCK IN/OUT

PB9/EMDIO

PB8/EMDC

PB14/ERX3/SPI0_NPCS2

PB13/ERX2/SPI0_NPCS1

PB6/ERX1

PB5/ERX0

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

Associated BSR

Cells

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

49

Table 13-2.

AT91SAM7X JTAG Boundary Scan Register (Continued)

Bit

Number

96

Pin Name Pin Type

PB15/ERXDV/ECRSDV IN/OUT

67

66

65

64

71

70

69

68

75

74

73

72

79

78

77

76

83

82

81

80

87

86

85

84

91

90

89

88

95

94

93

92 PB17/ERXCK/SPI0_NPCS3

PB7/ERXER

PB12/ETXER/TCLK0

PB0/ETXCK/EREFCK/PCK0

PB1/ETXEN

PB2/ETX0

PB3/ETX1

PB10/ETX2/SPI1_NPCS1

PB11/ETX3/SPI1_NPCS2

PA19/CANRX

IN/OUT

IN/OUT

IN/OUT

PB0/ETXCK/ERE

FCK/PCK0

PB1/ETXEN

PB2/ETX0

PB3/ETX1

IN/OUT

IN/OUT

IN/OUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

Associated BSR

Cells

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

50

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

Table 13-2.

AT91SAM7X JTAG Boundary Scan Register (Continued)

Bit

Number

63

Pin Name Pin Type

PA20/CANTX IN/OUT

34

33

32

31

38

37

36

35

42

41

40

39

46

45

44

43

50

49

48

47

54

53

52

51

58

57

56

55

62

61

60

59 PA21/TF/SPI1_NPCS0

PA22/TK/SPI1_SPCK

PB16/ECOL/SPI1_NPCS3

PB4/ECRS

PA23/TD/SPI1_MOSI

PA24/RD/SPI1_MISO

PA25/RK/SPI1_NPCS1

PA26/RF/SPI1_NPCS2

PB18/EF100/ADTRG

PB19/PWM0/TCLK1

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

Associated BSR

Cells

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

51

Table 13-2.

AT91SAM7X JTAG Boundary Scan Register (Continued)

Bit

Number

30

Pin Name Pin Type

PB20/PWM1/PCK0 IN/OUT

7

6

9

8

13

12

11

10

3

2

5

4

1

17

16

15

14

21

20

19

18

25

24

23

22

29

28

27

26 PB21/PWM2/PCK2

PB22/PWM3/PCK2

PB23/TIOA0/DCD1

PB24/TIOB0/DSR1

PB25/TIOA1/DTR1

PB26/TIOB1/RI1

PA27DRXD/PCK3

PA28/DTXD

PA29/FIQ/SPI1_NPCS3

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

IN/OUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

Associated BSR

Cells

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

OUTPUT

CONTROL

INPUT

52

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

13.5.5

ID Code Register

Access: Read-only

31 30

VERSION

29

23

15

7

28 27

22 21 20

PART NUMBER

19

12 11 14

PART NUMBER

13

6 5 4

MANUFACTURER IDENTITY

3

• VERSION[31:28]: Product Version Number

Set to 0x0.

• PART NUMBER[27:12]: Product Part Number

AT91SAM7X256: 0x5B17

AT91SAM7X128: 0x5B16

• MANUFACTURER IDENTITY[11:1]

Set to 0x01F.

Bit[0] Required by IEEE Std. 1149.1.

Set to 0x1.

AT91SAM7X256: JTAG ID Code value is 05B1_003F

AT91SAM7X128: JTAG ID Code value is 05B0_F03F

26

PART NUMBER

25

18 17

10 9

MANUFACTURER IDENTITY

2 1

24

16

8

0

1

53

6120D–ATARM–02-Feb-06

54

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

14. Reset Controller (RSTC)

14.1

Overview

The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last.

The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.

A brownout detection is also available to prevent the processor from falling into an unpredictable state.

14.2

Block Diagram

Figure 14-1. Reset Controller Block Diagram

Reset Controller

bod_rst_en brown_out

Brownout

Manager bod_reset

Reset

State

Manager rstc_irq

Main Supply

POR

Startup

Counter

NRST user_reset nrst_out

NRST

Manager exter_nreset proc_nreset periph_nreset

WDRPROC wd_fault

SLCK

55

6120D–ATARM–02-Feb-06

14.3

Functional Description

The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:

• proc_nreset: Processor reset line. It also resets the Watchdog Timer.

• periph_nreset: Affects the whole set of embedded peripherals.

• nrst_out: Drives the NRST pin.

These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required.

The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.

14.3.1

NRST Manager

The NRST Manager samples the NRST input pin and drives this pin low when required by the

Reset State Manager.

Figure 14-2

shows the block diagram of the NRST Manager.

Figure 14-2. NRST Manager

RSTC_SR

URSTS

NRSTL

RSTC_MR

URSTEN

RSTC_MR

URSTIEN

Other interrupt sources rstc_irq user_reset

NRST

RSTC_MR

ERSTL nrst_out

External Reset Timer exter_nreset

14.3.1.1

14.3.1.2

56

NRST Signal or Interrupt

The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager.

However, the NRST Manager can be programmed to not trigger a reset when an assertion of

NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.

The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR.

As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.

The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.

NRST External Reset Control

The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

14.3.2

AT91SAM7X256/128 Preliminary

2

(ERSTL+1)

Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.

This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset.

Brownout Manager

Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal.

The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read.

The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR.

At factory, the brownout reset is disabled.

Figure 14-3. Brownout Manager bod_rst_en bod_reset brown_out

RSTC_SR

BODSTS

RSTC_MR

BODIEN

Other interrupt sources rstc_irq

57

6120D–ATARM–02-Feb-06

14.3.3

Reset States

14.3.3.1

The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released.

Power-up Reset

When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow

Clock oscillator is stable before starting up the device.

The startup time, as shown in

Figure 14-4 , is hardcoded to comply with the Slow Clock Oscillator

startup time. After the startup time, the reset signals are released and the field RSTTYP in

RSTC_SR reports a Power-up Reset.

When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately.

Figure 14-4. Power-up Reset

SLCK

MCK

Main Supply

POR output proc_nreset periph_nreset

Startup Time

Processor Startup

= 3 cycles

Any

Freq.

NRST

(nrst_out)

EXTERNAL RESET LENGTH

= 2 cycles

58

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

14.3.3.2

User Reset

The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in

RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.

The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted.

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, the RSTTYP field of the Status Register

(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.

T h e N R S T M a n a g e r g u a r a n t e e s t h a t t h e N R S T l i n e i s a s s e r t e d f o r

EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.

Figure 14-5. User Reset State

SLCK

MCK

NRST

Any

Freq.

Resynch.

2 cycles

Resynch.

2 cycles

Processor Startup

= 3 cycles proc_nreset

RSTTYP periph_nreset

Any XXX 0x4 = User Reset

NRST

(nrst_out)

>= EXTERNAL RESET LENGTH

59

6120D–ATARM–02-Feb-06

14.3.3.3

Brownout Reset

When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted.

The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered.

When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value

0x5, thus indicating that the last reset is a Brownout Reset.

Figure 14-6. Brownout Reset State

SLCK

MCK brown_out or bod_reset

Any

Freq.

Resynch.

2 cycles

Processor Startup

= 3 cycles proc_nreset

RSTTYP periph_nreset

Any

XXX

0x5 = Brownout Reset

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

60

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

14.3.3.4

AT91SAM7X256/128 Preliminary

Software Reset

The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at

1:

• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.

• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.

• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field

ERSTL in the Mode Register (RSTC_MR).

The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow

Clock cycles.

The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.

If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field

ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.

If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field

RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in

RSTTYP.

As soon as a software operation is detected, the bit SRCMP (Software Reset Command in

Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.

Figure 14-7. Software Reset

SLCK

MCK

Write RSTC_CR

Any

Freq.

Resynch.

1 cycle

Processor Startup

= 3 cycles proc_nreset if PROCRST=1

RSTTYP periph_nreset if PERRST=1

NRST

(nrst_out) if EXTRST=1

Any

XXX

0x3 = Software Reset

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

SRCMP in RSTC_SR

61

6120D–ATARM–02-Feb-06

14.3.3.5

Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.

When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in

WDT_MR:

• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.

• If WDRPROC = 1, only the processor reset is asserted.

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog

Reset, and the Watchdog is enabled by default and with a period set to a maximum.

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.

Figure 14-8. Watchdog Reset

SLCK

MCK wd_fault

Any

Freq.

Processor Startup

= 3 cycles

Only if

WDRPROC = 0 proc_nreset

RSTTYP periph_nreset

NRST

(nrst_out)

Any XXX 0x2 = Watchdog Reset

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

62

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

14.3.4

14.3.5

Reset State Priorities

The Reset State Manager manages the following priorities between the different reset sources, given in descending order:

• Power-up Reset

• Brownout Reset

• Watchdog Reset

• Software Reset

• User Reset

Particular cases are listed below:

• When in User Reset:

– A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.

– A software reset is impossible, since the processor reset is being activated.

• When in Software Reset:

– A watchdog event has priority over the current state.

– The NRST has no effect.

• When in Watchdog Reset:

– The processor reset is active and so a Software Reset cannot be programmed.

– A User Reset cannot be entered.

Reset Controller Status Register

The Reset Controller status register (RSTC_SR) provides several status fields:

• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.

• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.

• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.

• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR

register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure

14-9

). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the

URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the

RSTC_SR status register resets the URSTS bit and clears the interrupt.

• BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled

(bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt.

63

6120D–ATARM–02-Feb-06

Figure 14-9. Reset Controller Status and Interrupt

MCK

Peripheral Access

2 cycle resynchronization

NRST

NRSTL

URSTS rstc_irq if (URSTEN = 0) and

(URSTIEN = 1)

2 cycle resynchronization read

RSTC_SR

64

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

14.4

Reset Controller (RSTC) User Interface

Table 14-1.

Reset Controller (RSTC) Register Mapping

Offset Register Name

0x00

0x04

0x08

Control Register

Status Register

Mode Register

RSTC_CR

RSTC_SR

RSTC_MR

Access

Write-only

Read-only

Read/Write

-

0x0000_0000

0x0000_0000

6120D–ATARM–02-Feb-06

65

14.4.1

Reset Controller Control Register

Register Name:

RSTC_CR

Access Type:

31

Write-only

30 29 28 27 26 25

KEY

23

15

22

14

21

13

20

12

19

11

18

10

7

6

5

4

3

EXTRST

2

PERRST

• PROCRST: Processor Reset

0 = No effect.

1 = If KEY is correct, resets the processor.

• PERRST: Peripheral Reset

0 = No effect.

1 = If KEY is correct, resets the peripherals.

• EXTRST: External Reset

0 = No effect.

1 = If KEY is correct, asserts the NRST pin.

• KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

17

9

1

24

16

8

0

PROCRST

66

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

14.4.2

Reset Controller Status Register

Register Name:

RSTC_SR

Access Type:

31

Read-only

30

29

23

15

22

14

21

13

28

20

12

27

19

11

26

18

10

25

17

SRCMP

9

RSTTYP

7

6

5

4

3

2

1

BODSTS

• URSTS: User Reset Status

0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.

1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.

• BODSTS: Brownout Detection Status

0 = No brownout high-to-low transition happened since the last read of RSTC_SR.

1 = A brownout high-to-low transition has been detected since the last read of RSTC_SR.

• RSTTYP: Reset Type

Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.

24

16

NRSTL

8

0

URSTS

0

0

0

1

1

RSTTYP

0

1

1

0

0

0

0

1

0

1

Reset Type

Power-up Reset

Watchdog Reset

Software Reset

User Reset

Brownout Reset

Comments

VDDCORE rising

Watchdog fault occurred

Processor reset required by the software

NRST pin detected low

BrownOut reset occurred

• NRSTL: NRST Pin Level

Registers the NRST Pin Level at Master Clock (MCK).

• SRCMP: Software Reset Command in Progress

0 = No software command is being performed by the reset controller. The reset controller is ready for a software command.

1 = A software reset command is being performed by the reset controller. The reset controller is busy.

67

6120D–ATARM–02-Feb-06

14.4.3

Reset Controller Mode Register

Register Name:

RSTC_MR

Access Type:

31

Read/Write

30 29 28 27 26 25 24

KEY

23

15

22

14

21

13

20

12

19

11

18

10

17

9

16

BODIEN

8

ERSTL

7

6

5

4

URSTIEN

3

2

1

0

URSTEN

• URSTEN: User Reset Enable

0 = The detection of a low level on the pin NRST does not generate a User Reset.

1 = The detection of a low level on the pin NRST triggers a User Reset.

• URSTIEN: User Reset Interrupt Enable

0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.

1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.

• BODIEN: Brownout Detection Interrupt Enable

0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq.

1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq.

• ERSTL: External Reset Length

This field defines the external reset length. The external reset is asserted during a time of 2

(ERSTL+1)

Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds.

• KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

68

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

15. Real-time Timer (RTT)

15.1

Overview

The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value.

15.2

Block Diagram

Figure 15-1. Real-time Timer

RTT_MR

RTTRST

RTT_MR

RTPRES

RTT_MR

RTTINCIEN

SLCK reload

16-bit

Divider

RTT_MR

RTTRST

0

1 0

RTT_SR set

RTTINC reset rtt_int

32-bit

Counter read

RTT_SR

RTT_MR

ALMIEN

RTT_VR CRTV

RTT_SR reset

ALMS set

= rtt_alarm

RTT_AR ALMV

15.3

Functional Description

The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by

Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field

RTPRES of the Real-time Mode Register (RTT_MR).

Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 2

32

seconds, corresponding to more than 136 years, then roll over to 0.

The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow

Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear.

69

6120D–ATARM–02-Feb-06

The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time

Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value.

The current value of the counter is compared with the value written in the alarm register

RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in

RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset.

The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz.

Reading the RTT_SR status register resets the RTTINC and ALMS fields.

Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.

Figure 15-2. RTT Counting

APB cycle

APB cycle

MCK

RTPRES - 1

Prescaler

0

RTT

RTTINC (RTT_SR)

ALMS (RTT_SR)

APB Interface

0

...

ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 read RTT_SR

70

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

15.4

Real-time Timer (RTT) User Interface

Table 15-1.

Real-time Timer (RTT) Register Mapping

Offset Register

0x00

0x04

0x08

0x0C

Mode Register

Alarm Register

Value Register

Status Register

AT91SAM7X256/128 Preliminary

Name

RTT_MR

RTT_AR

RTT_VR

RTT_SR

Access

Read/Write

Read/Write

Read-only

Read-only

Reset Value

0x0000_8000

0xFFFF_FFFF

0x0000_0000

0x0000_0000

6120D–ATARM–02-Feb-06

71

15.4.1

Real-time Timer Mode Register

Register Name:

RTT_MR

Access Type: Read/Write

31

30

29

23

15

22

14

21

13

28

20

12

RTPRES

11

27

19

26

18

RTTRST

10

25

17

RTTINCIEN

9

7 6 5 4

RTPRES

3 2 1

• RTPRES: Real-time Timer Prescaler Value

Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows:

RTPRES = 0: The Prescaler Period is equal to 2 16

RTPRES

0: The Prescaler Period is equal to RTPRES.

• ALMIEN: Alarm Interrupt Enable

0 = The bit ALMS in RTT_SR has no effect on interrupt.

1 = The bit ALMS in RTT_SR asserts interrupt.

• RTTINCIEN: Real-time Timer Increment Interrupt Enable

0 = The bit RTTINC in RTT_SR has no effect on interrupt.

1 = The bit RTTINC in RTT_SR asserts interrupt.

• RTTRST: Real-time Timer Restart

1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.

0

24

16

ALMIEN

8

72

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

15.4.2

Real-time Timer Alarm Register

Register Name:

RTT_AR

Access Type:

31

Read/Write

30 29 28 27

ALMV

23 22 21 20 19

ALMV

15 14 13 12 11

ALMV

7 6 5 4 3

ALMV

• ALMV: Alarm Value

Defines the alarm value (ALMV+1) compared with the Real-time Timer.

15.4.3

Real-time Timer Value Register

Register Name:

RTT_VR

Access Type:

31

Read-only

30 29 28 27

CRTV

23 22 21 20 19

CRTV

15 14 13 12 11

CRTV

7 6 5 4 3

CRTV

• CRTV: Current Real-time Value

Returns the current value of the Real-time Timer.

26

18

10

2

26

18

10

2

25

17

9

1

25

17

9

1

24

16

8

0

24

16

8

0

73

6120D–ATARM–02-Feb-06

15.4.4

Real-time Timer Status Register

Register Name:

RTT_SR

Access Type:

31

Read-only

30

29

23

15

22

14

21

13

28

20

12

27

19

11

7

6

5

4

3

2

• ALMS: Real-time Alarm Status

0 = The Real-time Alarm has not occurred since the last read of RTT_SR.

1 = The Real-time Alarm occurred since the last read of RTT_SR.

• RTTINC: Real-time Timer Increment

0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.

1 = The Real-time Timer has been incremented since the last read of the RTT_SR.

26

18

10

25

17

9

1

RTTINC

8

0

ALMS

24

16

74

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

16. Periodic Interval Timer (PIT)

16.1

Overview

The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time.

16.2

Block Diagram

Figure 16-1. Periodic Interval Timer

PIT_MR

PIV

= ?

0

0

0 1

PIT_SR set

PITS reset

PIT_MR

PITIEN pit_irq

0 1

12-bit

Adder read PIT_PIVR

MCK

20-bit

Counter

Prescaler

MCK/16

CPIV PIT_PIVR

PICNT

PIT_PIIR

CPIV PICNT

75

6120D–ATARM–02-Feb-06

16.3

Functional Description

The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.

The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at

Master Clock /16.

The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to

0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in

PIT_MR).

Writing a new PIV value in PIT_MR does not reset/restart the counters.

When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register

(PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR.

When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register

(PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.

The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on

reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 16-2

illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again.

The PIT is stopped when the core enters debug state.

76

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

Figure 16-2. Enabling/Disabling PIT with PITEN

APB cycle

15

MCK Prescaler 0

PITEN

CPIV

PICNT

PITS (PIT_SR)

APB Interface

0 1

0

PIV - 1 PIV

MCK

1

0

APB cycle

0 restarts MCK Prescaler

1 read PIT_PIVR

77

6120D–ATARM–02-Feb-06

16.4

Periodic Interval Timer (PIT) User Interface

Table 16-1.

Periodic Interval Timer (PIT) Register Mapping

Offset Register Name

0x00

0x04

0x08

0x0C

Mode Register

Status Register

Periodic Interval Value Register

Periodic Interval Image Register

PIT_MR

PIT_SR

PIT_PIVR

PIT_PIIR

Access

Read/Write

Read-only

Read-only

Read-only

0x000F_FFFF

0x0000_0000

0x0000_0000

0x0000_0000

78

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

16.4.1

Periodic Interval Timer Mode Register

Register Name:

PIT_MR

Access Type:

31

Read/Write

30

29

28

23

15

22

14

21

13

20

12

27

19

11

26

18

10

PIV

25

PITIEN

17

9

24

PITEN

16

8

PIV

7 6 5 4 3 2 1 0

PIV

• PIV: Periodic Interval Value

Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to

(PIV + 1).

• PITEN: Period Interval Timer Enabled

0 = The Periodic Interval Timer is disabled when the PIV value is reached.

1 = The Periodic Interval Timer is enabled.

• PITIEN: Periodic Interval Timer Interrupt Enable

0 = The bit PITS in PIT_SR has no effect on interrupt.

1 = The bit PITS in PIT_SR asserts interrupt.

16.4.2

Periodic Interval Timer Status Register

Register Name:

PIT_SR

Access Type:

31

Read-only

30

29

28

27

26

25

24

23

15

22

14

21

13

20

12

19

11

7

6

5

4

3

• PITS: Periodic Interval Timer Status

0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR.

1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.

2

18

10

17

9

1

16

8

0

PITS

79

6120D–ATARM–02-Feb-06

16.4.3

Periodic Interval Timer Value Register

Register Name:

PIT_PIVR

Access Type:

31

Read-only

30 29 28 27 26

PICNT

23 22 21 20 19 18

PICNT

15 14 13 12 11 10

CPIV

7 6 5 4 3 2

CPIV

Reading this register clears PITS in PIT_SR.

• CPIV: Current Periodic Interval Value

Returns the current value of the periodic interval timer.

• PICNT: Periodic Interval Counter

Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.

CPIV

25

17

9

1

16.4.4

Periodic Interval Timer Image Register

Register Name:

PIT_PIIR

Access Type:

31

Read-only

30 29 28 27 26

PICNT

23 22 21 20 19 18

PICNT

15 14 13 12 11 10

CPIV

7 6 5 4 3 2

CPIV

• CPIV: Current Periodic Interval Value

Returns the current value of the periodic interval timer.

• PICNT: Periodic Interval Counter

Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.

CPIV

25

17

9

1

80

AT91SAM7X256/128 Preliminary

8

0

24

16

24

16

8

0

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

17. Watchdog Timer (WDT)

17.1

Overview

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds

(slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.

17.2

Block Diagram

Figure 17-1. Watchdog Timer Block Diagram write WDT_MR

WDT_MR

WV

WDT_CR

WDRSTT reload

1 0

WDT_MR

WDD

<= WDD

12-bit Down

Counter

Current

Value

= 0 set

WDUNF reset read WDT_SR or reset set

WDERR reset reload

1/128

SLCK

WDT_MR

WDRSTEN wdt_fault

(to Reset Controlle r) wdt_int

WDFIEN

WDT_MR

81

6120D–ATARM–02-Feb-06

17.3

Functional Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset.

The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow

Clock of 32.768 kHz).

After a Processor Reset, the value of WV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset).

This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires.

The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters.

In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The

Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow

Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode

Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register

(WDT_SR).

To prevent a software deadlock that continuously triggers the Watchdog, the reload of the

Watchdog must occur in a window defined by 0 and WDD in the WDT_MR:

0 WDT WDD; writing WDRSTT restarts the Watchdog Timer.

Any attempt to restart the Watchdog Timer in the range [WDV; WDD] results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the

“wdt_fault” signal to the Reset Controller is asserted.

Note that this feature can be disabled by programming a WDD value greater than or equal to the

WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the

WDD and WDV values are equal).

The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.

If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted.

Writing the WDT_MR reloads and restarts the down counter.

While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.

82

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

Figure 17-2. Watchdog Behavior

FFF

WDV

Forbidden

Window

WDD

Permitted

Window

0

Watchdog

Fault

Normal behavior

WDT_CR = WDRSTT

AT91SAM7X256/128 Preliminary

Watchdog Error

Watchdog Underflow if WDRSTEN is 1 if WDRSTEN is 0

83

6120D–ATARM–02-Feb-06

17.4

Watchdog Timer (WDT) User Interface

Table 17-1.

Watchdog Timer (WDT) Register Mapping

Offset Register

0x00

0x04

0x08

Control Register

Mode Register

Status Register

Name

WDT_CR

WDT_MR

WDT_SR

Access

Write-only

Read/Write Once

Read-only

Reset Value

-

0x3FFF_2FFF

0x0000_0000

17.4.1

Watchdog Timer Control Register

Register Name:

Access Type:

WDT_CR

Write-only

31 30 29 28 27 26 25

KEY

23

15

22

14

21

13

20

12

19

11

18

10

7

6

5

4

3

2

• WDRSTT: Watchdog Restart

0: No effect.

1: Restarts the Watchdog.

• KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

17

9

1

24

16

8

0

WDRSTT

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

17.4.2

Watchdog Timer Mode Register

Register Name:

Access Type:

WDT_MR

Read/Write Once

31

30

29

WDIDLEHLT

28

WDDBGHLT

23 22 21 20

WDD

27

19

26

18

WDD

25

17

24

16

15

WDDIS

7

14

WDRPROC

6

13

WDRSTEN

5

12

WDFIEN

4

WDV

11

3

10

2

WDV

9

1

• WDV: Watchdog Counter Value

Defines the value loaded in the 12-bit Watchdog Counter.

• WDFIEN: Watchdog Fault Interrupt Enable

0: A Watchdog fault (underflow or error) has no effect on interrupt.

1: A Watchdog fault (underflow or error) asserts interrupt.

• WDRSTEN: Watchdog Reset Enable

0: A Watchdog fault (underflow or error) has no effect on the resets.

1: A Watchdog fault (underflow or error) triggers a Watchdog reset.

• WDRPROC: Watchdog Reset Processor

0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.

1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.

• WDD: Watchdog Delta Value

Defines the permitted range for reloading the Watchdog Timer.

If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.

If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.

• WDDBGHLT: Watchdog Debug Halt

0: The Watchdog runs when the processor is in debug state.

1: The Watchdog stops when the processor is in debug state.

• WDIDLEHLT: Watchdog Idle Halt

0: The Watchdog runs when the system is in idle mode.

1: The Watchdog stops when the system is in idle state.

• WDDIS: Watchdog Disable

0: Enables the Watchdog Timer.

1: Disables the Watchdog Timer.

8

0

85

6120D–ATARM–02-Feb-06

17.4.3

Watchdog Timer Status Register

Register Name:

Access Type:

WDT_SR

Read-only

31

30

29

23

15

22

14

21

13

28

20

12

27

19

11

7

6

5

4

3

• WDUNF: Watchdog Underflow

0: No Watchdog underflow occurred since the last read of WDT_SR.

1: At least one Watchdog underflow occurred since the last read of WDT_SR.

• WDERR: Watchdog Error

0: No Watchdog error occurred since the last read of WDT_SR.

1: At least one Watchdog error occurred since the last read of WDT_SR.

10

2

26

18

25

17

9

1

WDERR

24

16

8

0

WDUNF

86

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

18. Voltage Regulator Mode Controller (VREG)

18.1

Overview

The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator

Mode Register. Its offset is 0x60 with respect to the System Controller offset.

This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage

Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake up the Voltage Regulator in Normal Mode.

6120D–ATARM–02-Feb-06

87

18.2

Voltage Regulator Power Controller (VREG) User Interface

Table 18-1.

Voltage Regulator Power Controller Register Mapping

Offset Register Name

0x60 Voltage Regulator Mode Register VREG_MR

Access

Read/Write

18.2.1

Voltage Regulator Mode Register

Register Name:

VREG_MR

Access Type:

31

Read/Write

30

29

23

15

22

14

21

13

7

6

5

4

• PSTDBY: Periodic Interval Value

0 = Voltage regulator in normal mode.

1 = Voltage regulator in standby mode (low-power mode).

28

20

12

27

19

11

3

26

18

10

2

0x0

25

17

9

1

24

16

8

0

PSTDBY

88

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

19. Memory Controller (MC)

19.1

Overview

The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the

ARM7TDMI processor and the Peripheral DMA Controller. It features a bus arbiter, an address decoder, an abort status, a misalignment detector and an Embedded Flash Controller.

19.2

Block Diagram

Figure 19-1. Memory Controller Block Diagram

Memory Controller

ASB

ARM7TDMI

Processor

Abort

Embedded

Flash

Controller

Internal

Flash

Abort

Status

Internal

RAM

Address

Decoder

EMAC

DMA

Bus

Arbiter

Misalignment

Detector

User

Interface

Peripheral

DMA

Controller

Peripheral 0

Peripheral 1

Peripheral N

APB

Bridge

APB

From Master to Slave

89

6120D–ATARM–02-Feb-06

19.3

Functional Description

The Memory Controller handles the internal ASB bus and arbitrates the accesses of up to three masters.

It is made up of:

• A bus arbiter

• An address decoder

• An abort status

• A misalignment detector

• An Embedded Flash Controller

The MC handles only little-endian mode accesses. The masters work in little-endian mode only.

19.3.1

19.3.2

Bus Arbiter

The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the three masters. The EMAC has the highest priority; the Peripheral DMA Controller has the medium priority; the ARM processor has the lowest one.

Address Decoder

The Memory Controller features an Address Decoder that first decodes the four highest bits of the 32-bit address bus and defines three separate areas:

• One 256-Mbyte address space for the internal memories

• One 256-Mbyte address space reserved for the embedded peripherals

• An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if accessed

Figure 19-2

shows the assignment of the 256-Mbyte memory areas.

Figure 19-2. Memory Areas

256M Bytes

0x0000 0000

0x0FFF FFFF

0x1000 0000

Internal Memories

14 x 256MBytes

3,584 Mbytes

Undefined

(Abort)

256M Bytes

0xEFFF FFFF

0xF000 0000

0xFFFF FFFF

Peripherals

90

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6120D–ATARM–02-Feb-06

19.3.2.1

AT91SAM7X256/128 Preliminary

Internal Memory Mapping

Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories.

The allocated memories are accessed all along the 1-Mbyte address space and so are repeated n times within this address space, n equaling 1M bytes divided by the size of the memory.

When the address of the access is undefined within the internal memory area, the Address

Decoder returns an Abort to the master.

Figure 19-3. Internal Memory Mapping

0x0000 0000

Internal Memory Area 0

0x000F FFFF

0x0010 0000

Internal Memory Area 1

Internal Flash

0x001F FFFF

0x0020 0000

256M Bytes

Internal Memory Area 2

Internal SRAM

0x002F FFFF

0x0030 0000

Internal Memory Area 3

Internal SRAM

0x003F FFFF

0x0040 0000

Undefined Areas

(Abort)

0x0FFF FFFF

1M Bytes

1M Bytes

1M Bytes

1M Bytes

252M bytes

19.3.2.2

19.3.3

Internal Memory Area 0

The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in particular, the Reset Vector at address 0x0.

Before execution of the remap command, the on-chip Flash is mapped into Internal Memory

Area 0, so that the ARM7TDMI reaches an executable instruction contained in Flash. After the remap command, the internal SRAM at address 0x0020 0000 is mapped into Internal Memory

Area 0. The memory mapped into Internal Memory Area 0 is accessible in both its original location and at address 0x0.

Remap Command

After execution, the Remap Command causes the Internal SRAM to be accessed through the

Internal Memory Area 0.

As the ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, and Fast Interrupt) are mapped from address 0x0 to address 0x20, the Remap Command allows the user to redefine dynamically these vectors under software control.

The Remap Command is accessible through the Memory Controller User Interface by writing the

MC_RCR (Remap Control Register) RCB field to one.

The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset.

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6120D–ATARM–02-Feb-06

19.3.4

19.3.5

19.3.6

Abort Status

There are two reasons for an abort to occur:

• access to an undefined address

• an access to a misaligned address.

When an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access. However, only the ARM7TDMI can take an abort signal into account, and only under the condition that it was generating an access. The Peripheral DMA Controller and the EMAC do not handle the abort input signal. Note that the connections are not represented in

Figure 19-1

.

To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status register set.

The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in

MC_ASR and include:

• the size of the request (field ABTSZ)

• the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)

• whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned address (bit MISADD)

• the source of the access leading to the last abort (bits MST_EMAC, MST_PDC and

MST_ARM)

• whether or not an abort occurred for each master since the last read of the register (bits

SVMST_EMAC, SVMST_PDC and SVMST_ARM) unless this information is loaded in MST bits

In the case of a Data Abort from the processor, the address of the data access is stored. This is useful, as searching for which address generated the abort would require disassembling the instructions and full knowledge of the processor context.

In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipelined in the ARM processor. The ARM processor takes the prefetch abort into account only if the read instruction is executed and it is probable that several aborts have occurred during this time.

Thus, in this case, it is preferable to use the content of the Abort Link register of the ARM processor.

Embedded Flash Controller

The Embedded Flash Controller is added to the Memory Controller and ensures the interface of the flash block with the 32-bit internal bus. It allows an increase of performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages with the programming, erasing, locking and unlocking sequences thanks to a full set of commands.

Misalignment Detector

The Memory Controller features a Misalignment Detector that checks the consistency of the accesses.

For each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-word (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. Note that the accesses of the ARM processor when it is fetching instructions are not checked.

The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particularly difficult to detect in the debug phase.

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As the requested address is saved in the Abort Status Register and the address of the instruction generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified.

6120D–ATARM–02-Feb-06

93

19.4

Memory Controller (MC) User Interface

Base Address: 0xFFFFFF00

Table 19-1.

Memory Controller (MC) Register Mapping

Offset Register

0x00

0x04

0x08

0x10-0x5C

0x60

MC Remap Control Register

MC Abort Status Register

MC Abort Address Status Register

Reserved

EFC Configuration Registers

Name

MC_RCR

MC_ASR

MC_AASR

Access

Write-only

Read-only

Read-only

Reset State

0x0

0x0

See

Section 20. ”Embedded Flash Controller (EFC)”, on page 99

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19.4.1

MC Remap Control Register

Register Name: MC_RCR

Access Type:

Offset:

Write-only

0x0

31

30

29

23

15

7

22

14

6

21

13

5

12

4

28

20

11

3

27

19

10

2

26

18

1

9

25

17

8

0

RCB

24

16

• RCB: Remap Command Bit

0: No effect.

1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices.

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19.4.2

MC Abort Status Register

Register Name: MC_ASR

Access Type:

Reset Value:

Offset:

Read-only

0x0

0x04

31

30

29

23

15

7

22

14

6

21

13

5

12

4

28

20

27

19

11

3

26

SVMST_ARM

18

MST_ARM

10

ABTTYP

2

• UNDADD: Undefined Address Abort Status

0: The last abort was not due to the access of an undefined address in the address space.

1: The last abort was due to the access of an undefined address in the address space.

• MISADD: Misaligned Address Abort Status

0: The last aborted access was not due to an address misalignment.

1: The last aborted access was due to an address misalignment.

• ABTSZ: Abort Size Status

25

SVMST_PDC

17

MST_PDC

9

SVMST_EMAC

ABTSZ

24

16

MST_EMAC

8

1

MISADD

0

UNDADD

ABTSZ

1

1

0

0

• ABTTYP: Abort Type Status

0

1

0

1

Abort Size

Byte

Half-word

Word

Reserved

0

0

1

1

0

1

0

1

Data Read

Data Write

Code Fetch

Reserved

• MST_EMAC: EMAC Abort Source

0: The last aborted access was not due to the EMAC.

1: The last aborted access was due to the EMAC.

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• MST_PDC: PDC Abort Source

0: The last aborted access was not due to the PDC.

1: The last aborted access was due to the PDC.

• MST_ARM: ARM Abort Source

0: The last aborted access was not due to the ARM.

1: The last aborted access was due to the ARM.

• SVMST_EMAC: Saved EMAC Abort Source

0: No abort due to the EMAC occurred since the last read of MC_ASR or it is notified in the bit MST_EMAC.

1: At least one abort due to the EMAC occurred since the last read of MC_ASR.

• SVMST_PDC: Saved PDC Abort Source

0: No abort due to the PDC occurred since the last read of MC_ASR or it is notified in the bit MST_PDC.

1: At least one abort due to the PDC occurred since the last read of MC_ASR.

• SVMST_ARM: Saved ARM Abort Source

0: No abort due to the ARM occurred since the last read of MC_ASR or it is notified in the bit MST_ARM.

1: At least one abort due to the ARM occurred since the last read of MC_ASR.

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19.4.3

MC Abort Address Status Register

Register Name: MC_AASR

Access Type:

Reset Value:

Offset:

Read-only

0x0

0x08

31 30 29 28

ABTADD

23 22 21 20

ABTADD

15 14 13 12

ABTADD

7 6 5 4

• ABTADD: Abort Address

This field contains the address of the last aborted access.

ABTADD

27

19

11

3

10

2

26

18

9

1

25

17

8

0

24

16

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20. Embedded Flash Controller (EFC)

20.0.1

Overview

The Embedded Flash Controller (EFC) is a part of the Memory Controller and ensures the interface of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for

Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands.

20.1

Functional Description

20.1.1

Embedded Flash Organization

The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several interfaces:

• One memory plane organized in several pages of the same size

• Two 32-bit read buffers used for code read optimization (see

”Read Operations” on page

100

).

• One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 MByte address space, so that

each word can be written to its final address (see ”Write Operations” on page 102

).

• Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit.

• Several general-purpose NVM bits. Each bit controls a specific feature in the device. Refer to the product definition section to get the GP NVM assignment.

The Embedded Flash size, the page size and the lock region organization are described in the product definition section.

Table 20-1.

Product Specific Lock and General-purpose NVM Bits

AT91SAM7X256 AT91SAM7X128 Denomination

3

16

3

8

Number of General-purpose NVM bits

Number of Lock Bits

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6120D–ATARM–02-Feb-06

Figure 20-1. Embedded Flash Memory Mapping

Start Address

Flash Memory

Lock Region 0

Lock Region 1

Page 0

Lock Bit 0

Lock Bit 1

Page (m-1)

Lock Region (n-1)

32-bit wide

Lock Bit n-1

Page ( (n-1)*m )

Page (n*m-1)

20.1.2

Read Operations

An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added in order to start access at following address during the second read, thus increasing perfor-

mance when the processor is running in Thumb mode (16-bit instruction set). See Figure 20-2 ,

Figure 20-3

and Figure 20-4

.

This optimization concerns only Code Fetch and not Data.

The read operations can be performed with or without wait state. Up to 3 wait states can be pro-

grammed in the field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see ”MC

Flash Mode Register” on page 110 ). Defining FWS to be 0 enables the single-cycle access of

the embedded Flash.

The Flash memory is accessible through 8-, 16- and 32-bit reads.

As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it.

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Figure 20-2. Code Read Optimization in Thumb Mode for FWS = 0

Master Clock

ARM Request (16-bit)

Code Fetch

@Byte 0

Flash Access

@Byte 2 @Byte 4

Bytes 0-3 Bytes 4-7

@Byte 6 @Byte 8

@Byte 10 @Byte 12

Bytes 8-11 Bytes 12-15

@Byte 14 @Byte 16

Bytes 16-19

Buffer (32 bits)

Bytes 0-3

Bytes 4-7 Bytes 8-11 Bytes 12-15

Data To ARM

Bytes 0-1

Bytes 2-3 Bytes 4-5 Bytes 6-7

Bytes 8-9 Bytes 10-11 Bytes 12-13

Bytes 14-15

Note: When FWS is equal to 0, all accesses are performed in a single-cycle access .

Figure 20-3. Code Read Optimization in Thumb Mode for FWS = 1

1 Wait State Cycle

1 Wait State Cycle 1 Wait State Cycle

Master Clock

1 Wait State Cycle

ARM Request (16-bit)

Code Fetch

@Byte 0

Flash Access

@Byte 2

Bytes 0-3

@Byte 4 @Byte 6

Bytes 4-7

@Byte 8 @Byte 10

Bytes 8-11

@Byte 12 @Byte 14

Bytes 12-15

Buffer (32 bits)

Bytes 0-3

Bytes 4-7 Bytes 8-11

Data To ARM

Bytes 0-1 Bytes 2-3

Bytes 4-5

Bytes 6-7

Bytes 8-9 Bytes 10-11 Bytes 12-13

Note: When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for the first one).

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Figure 20-4. Code Read Optimization in Thumb Mode for FWS = 3

3 Wait State Cycles 3 Wait State Cycles

Master Clock

3 Wait State Cycles 3 Wait State Cycles

ARM Request (16-bit)

Code Fetch

@Byte 0

Flash Access

Buffer (32 bits)

Bytes 0-3

@2 @4

Bytes 4-7

Bytes 0-3

@6

@8

Bytes 8-11

Bytes 4-7

@10 @12

Bytes 12-15

Bytes 8-11

Data To ARM

0-1 2-3 4-5

6-7

8-9 10-11 12-13

Note: When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle, the third access FWS cycles, the fourth access one cycle, etc.

20.1.3

Write Operations

The internal memory area reserved for the embedded Flash can also be written through a writeonly latch buffer. Write operations take into account only the 8 lowest address bits and thus wrap around within the internal memory area address space and appear to be repeated 1024 times within it.

Write operations can be prevented by programming the Memory Protection Unit of the product.

Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.

Write operations are performed in the number of wait states equal to the number of wait states

for read operations + 1, except for FWS = 3 (see ”MC Flash Mode Register” on page 110 ).

20.1.4

Flash Commands

The EFC offers a command set to manage programming the memory flash, locking and unlocking lock sectors, consecutive programming and locking, and full Flash erasing.

Table 20-2.

Set of Commands

Command

Write page

Set Lock Bit

Write Page and Lock

Clear Lock Bit

Erase all

Set General-purpose NVM Bit

Clear General-purpose NVM Bit

Set Security Bit

Value

0x01

0x02

0x03

0x04

0x08

0x0B

0x0D

0x0F

Mnemonic

WP

SLB

WPL

CLB

EA

SGPB

CGPB

SSB

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AT91SAM7X256/128 Preliminary

To run one of these commands, the field FCMD of the MC_FCR register has to be written with the command number. As soon as the MC_FCR register is written, the FRDY flag is automatically cleared. Once the current command is achieved, then the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.

All the commands are protected by the same keyword, which has to be written in the eight highest bits of the MC_FCR register.

Writing MC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the memory plane; however, the PROGE flag is set in the MC_FSR register.

This flag is automatically cleared by a read access to the MC_FSR register.

When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane; however, the LOCKE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register.

6120D–ATARM–02-Feb-06

103

Figure 20-5. Command State Chart

Read Status: MC_FSR

Check if FRDY flag set

No

Yes

Write FCMD and PAGENB in MC_FCR

Read Status: MC_FSR

Check if FRDY flag set

No

Yes

Check if LOCKE flag set

Yes

Locking region violation

No

Check if PROGE flag set

Yes

Bad keyword violation and/or Invalid command

No

Command Successful

In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle

Number (FMCN) in the Flash Mode Register MC_FMR must be correctly programmed (see

”MC

Flash Mode Register” on page 110

).

20.1.4.1

Flash Programming

Several commands can be used to program the Flash.

The Flash technology requires that an erase must be done before programming. The entire memory plane can be erased at the same time, or a page can be automatically erased by clearing the NEBP bit in the MC_FMR register before writing the command in the MC_FCR register.

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AT91SAM7X256/128 Preliminary

By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps if it has been erased before (see

Figure 20-6 ).

Figure 20-6. Example of Partial Page Programming:

32 bits wide

32 bits wide 32 bits wide

16 words

16 words

16 words

16 words

FF FF FF FF

...

FF FF FF FF

FF FF FF FF

FF FF FF FF

FF FF FF FF

FF FF FF FF

...

FF FF FF FF

FF FF FF FF

FF FF FF FF

...

FF FF FF FF

FF FF FF FF

Step 1.

Erase All Flash

Page 7 erased

FF FF FF FF

...

FF FF FF FF

FF FF FF FF

CA FE CA FE

...

CA FE CA FE

CA FE CA FE

FF FF FF FF

...

FF FF FF FF

FF FF FF FF

FF FF FF FF

...

FF FF FF FF

FF FF FF FF

FF FF FF FF

...

FF FF FF FF

FF FF FF FF

CA FE CA FE

...

CA FE CA FE

CA FE CA FE

DE CA DE CA

...

DE CA DE CA

DE CA DE CA

FF FF FF FF

...

FF FF FF FF

FF FF FF FF

Step 2.

Step 3.

Programming of the second part of Page 7 Programming of the third part of Page 7

(NEBP = 1)

(NEBP = 1)

After programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using

WPL.

Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds to the page size. The latch buffer wraps around within the internal memory area address space and appears to be repeated by the number of pages in it.

Note: Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.

Data are written to the latch buffer before the programming command is written to the Flash

Command Register MC_FCR. The sequence is as follows:

• Write the full page, at any page address, within the internal memory area address space using only 32-bit access.

• Programming starts as soon as the page number and the programming command are written to the Flash Command Register. The FRDY bit in the Flash Programming Status Register

(MC_FSR) is automatically cleared.

• When programming is completed, the bit FRDY in the Flash Programming Status Register

(MC_FSR) rises. If an interrupt was enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.

Two errors can be detected in the MC_FSR register after a programming sequence:

• Programming Error: A bad keyword and/or an invalid command have been written in the

MC_FCR register.

• Lock Error: The page to be programmed belongs to a locked region. A command must be previously run to unlock the corresponding region.

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20.1.4.2

20.1.4.3

Erase All Command

The entire memory can be erased if the Erase All Command (EA) in the Flash Command Register MC_FCR is written.

Erase All operation is allowed only if there are no lock bits set. Thus, if at least one lock region is locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has been written at 1 in MC_FMR, the interrupt line rises.

When programming is complete, the bit FRDY bit in the Flash Programming Status Register

(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.

Two errors can be detected in the MC_FSR register after a programming sequence:

• Programming Error: A bad keyword and/or an invalid command have been written in the

MC_FCR register.

• Lock Error: At least one lock region to be erased is protected. The erase command has been refused and no page has been erased. A Clear Lock Bit command must be executed previously to unlock the corresponding lock regions.

Lock Bit Protection

Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages.

After production, the device may have some embedded Flash lock regions locked. These locked regions are reserved for a default application. Refer to the product definition section for the default embedded Flash mapping. Locked sectors can be unlocked to be erased and then programmed with another application or other data.

The lock sequence is:

• The Flash Command register must be written with the following value:

(0x5A << 24) | (lockPageNumber << 8 & PAGEN) | SLB lockPageNumber is a page of the corresponding lock region.

• When locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.

A programming error, where a bad keyword and/or an invalid command have been written in the

MC_FCR register, may be detected in the MC_FSR register after a programming sequence.

It is possible to clear lock bits that were set previously. Then the locked region can be erased or programmed. The unlock sequence is:

• The Flash Command register must be written with the following value:

(0x5A << 24) | (lockPageNumber << 8 & PAGEN) | CLB lockPageNumber is a page of the corresponding lock region.

• When the unlock completes, the bit FRDY in the Flash Programming Status Register

(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.

A programming error, where a bad keyword and/or an invalid command have been written in the

MC_FCR register, may be detected in the MC_FSR register after a programming sequence.

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20.1.4.4

20.1.4.5

AT91SAM7X256/128 Preliminary

The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR reads 0. The Lock command programs the lock bit to 0; the corresponding bit LOCKSx in

MC_FSR reads 1.

Note: Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed.

General-purpose NVM Bits

General-purpose NVM bits do not interfere with the embedded Flash memory plane. These general-purpose bits are dedicated to protect other parts of the product. They can be set (activated) or cleared individually. Refer to the product definition section for the general-purpose NVM bit action.

The activation sequence is:

• Start the Set General Purpose Bit command (SGPB) by writing the Flash Command Register with the SEL command and the number of the general-purpose bit to be set in the PAGEN field.

• When the bit is set, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises.

If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the

Memory Controller is activated.

Two errors can be detected in the MC_FSR register after a programming sequence:

• Programming Error: A bad keyword and/or an invalid command have been written in the

MC_FCR register

• If the general-purpose bit number is greater than the total number of general-purpose bits, then the command has no effect.

It is possible to deactivate a general-purpose NVM bit set previously. The clear sequence is:

• Start the Clear General-purpose Bit command (CGPB) by writing the Flash Command

Register with CGPB and the number of the general-purpose bit to be cleared in the PAGEN field.

• When the clear completes, the bit FRDY in the Flash Programming Status Register

(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.

Two errors can be detected in the MC_FSR register after a programming sequence:

• Programming Error: a bad keyword and/or an invalid command have been written in the

MC_FCR register

• If the number of the general-purpose bit set in the PAGEN field is greater than the total number of general-purpose bits, then the command has no effect.

The Clear General-purpose Bit command programs the general-purpose NVM bit to 1; the corresponding bit GPNVM0 to GPNVMx in MC_FSR reads 0. The Set General-purpose Bit command programs the general-purpose NVM bit to 0; the corresponding bit GPNVMx in MC_FSR reads

1.

Note: Access to the Flash in read mode is permitted when a Set, Clear or Get General-purpose NVM Bit command is performed.

Security Bit

The goal of the security bit is to prevent external access to the internal bus system. JTAG, Fast

Flash Programming and Flash Serial Test Interface features are disabled. Once set, this bit can be reset only by an external hardware ERASE request to the chip. Refer to the product definition

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6120D–ATARM–02-Feb-06

section for the pin name that controls the ERASE. In this case, the full memory plane is erased and all lock and general-purpose NVM bits are cleared. The security bit in the MC_FSR is cleared only after these operations. The activation sequence is:

• Start the Set Security Bit command (SSB) by writing the Flash Command Register.

• When the locking completes, the bit FRDY in the Flash Programming Status Register

(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.

When the security bit is active, the SECURITY bit in the MC_FSR is set.

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20.2

Embedded Flash Controller (EFC) User Interface

The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00.

Table 20-3.

Embedded Flash Controller (EFC) Register Mapping

Offset

0x60

Register

MC Flash Mode Register

Name

MC_FMR

0x64

0x68

0x6C

MC Flash Command Register

MC Flash Status Register

Reserved

MC_FCR

MC_FSR

Access

Read/Write

Write-only

Read-only

Reset State

0x0

6120D–ATARM–02-Feb-06

109

20.2.1

Register Name:

Access Type:

Offset:

MC Flash Mode Register

MC_FMR

Read/Write

0x60

31

30

29

23 22 21

28

20

27

19

26

18

25

17

24

16

FMCN

15

14

13

12

11

10

9

FWS

8

7

NEBP

6

5

4

3

PROGE

• FRDY: Flash Ready Interrupt Enable

0: Flash Ready does not generate an interrupt.

1: Flash Ready generates an interrupt.

• LOCKE: Lock Error Interrupt Enable

0: Lock Error does not generate an interrupt.

1: Lock Error generates an interrupt.

• PROGE: Programming Error Interrupt Enable

0: Programming Error does not generate an interrupt.

1: Programming Error generates an interrupt.

• NEBP: No Erase Before Programming

0: A page erase is performed before programming.

1: No erase is performed before programming.

• FWS: Flash Wait State

This field defines the number of wait states for read and write operations:

2

LOCKE

1

0

FRDY

FWS

0

1

2

3

Read Operations

1 cycle

2 cycles

3 cycles

4 cycles

Write Operations

2 cycles

3 cycles

4 cycles

4 cycles

• FMCN: Flash Microsecond Cycle Number

Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the number of Master Clock cycles in one microsecond.

When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up.

Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds.

Warning: In order to guarantee valid operations on the flash memory, the field Flash Microsecond Cycle Number (FMCN)

must be correctly programmed.

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20.2.2

Register Name:

Access Type:

Offset:

MC Flash Command Register

MC_FCR

Write-only

0x64

31 30 29

23

15

22

14

21

13

28 27

KEY

20

4

19

12

PAGEN

11

3

26

18

10

25 24

17

PAGEN

16

9 8

7

6

5

• FCMD: Flash Command

This field defines the Flash commands:

FCMD

0000

0001

0010

0011

0100

1000

1011

1101

1111

Others

2

FCMD

1 0

Operations

No command.

Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR.

Write Page Command (WP):

Starts the programming of the page specified in the PAGEN field.

Set Lock Bit Command (SLB):

Starts a set lock bit sequence of the lock region specified in the PAGEN field.

Write Page and Lock Command (WPL):

The lock sequence of the lock region associated with the page specified in the field PAGEN occurs automatically after completion of the programming sequence.

Clear Lock Bit Command (CLB):

Starts a clear lock bit sequence of the lock region specified in the PAGEN field.

Erase All Command (EA):

Starts the erase of the entire Flash.

If at least one page is locked, the command is cancelled.

Set General-purpose NVM Bit (SGPB):

Activates the general-purpose NVM bit corresponding to the number specified in the PAGEN field.

Clear General Purpose NVM Bit (CGPB):

Deactivates the general-purpose NVM bit corresponding to the number specified in the

PAGEN field.

Set Security Bit Command (SSB):

Sets security bit.

Reserved.

Raises the Programming Error Status flag in the Flash Status Register MC_FSR.

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• PAGEN: Page Number

Write Page Command

Write Page and Lock Command

Erase All Command

Command

Set/Clear Lock Bit Command

PAGEN Description

PAGEN defines the page number to be written.

PAGEN defines the page number to be written and its associated lock region.

This field is meaningless

PAGEN defines one page number of the lock region to be locked or unlocked.

Set/Clear General Purpose NVM Bit Command PAGEN defines the general-purpose bit number.

Set Security Bit Command This field is meaningless

Note: Depending on the command, all the possible unused bits of PAGEN are meaningless.

• KEY: Write Protection Key

This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.

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20.2.3

Register Name:

Access Type:

Offset:

MC Flash Status Register

MC_FSR

Read-only

0x68

31

LOCKS15

30

LOCKS14

29

LOCKS13

23

LOCKS7

15

22

LOCKS6

14

28

LOCKS12

21 20

LOCKS5 LOCKS4

13

12

27

LOCKS11

19

LOCKS3

11

26

LOCKS10

18

LOCKS2

10

GPNVM2

25

LOCKS9

17

LOCKS1

9

GPNVM1

7

6

5

4

SECURITY

3

PROGE

2

LOCKE

1

• FRDY: Flash Ready Status

0: The EFC is busy and the application must wait before running a new command.

1: The EFC is ready to run a new command.

• LOCKE: Lock Error Status

0: No programming of at least one locked lock region has happened since the last read of MC_FSR.

1: Programming of at least one locked lock region has happened since the last read of MC_FSR.

• PROGE: Programming Error Status

0: No invalid commands and no bad keywords were written in the Flash Command Register MC_FCR.

1: An invalid command and/or a bad keyword was/were written in the Flash Command Register MC_FCR.

• SECURITY: Security Bit Status

0: The security bit is inactive.

1: The security bit is active.

• GPNVMx: General-purpose NVM Bit Status

0: The corresponding general-purpose NVM bit is inactive.

1: The corresponding general-purpose NVM bit is active.

• LOCKSx: Lock Region x Lock Status

0: The corresponding lock region is not locked.

1: The corresponding lock region is locked

MC_FSR, LOCKSx Product Specific Map

AT91SAM7X256 AT91SAM7X128 Denomination

16

LOCKS0

LOCKS1

LOCKS2

LOCKS3

LOCKS4

LOCKS5

8

LOCKS0

LOCKS1

LOCKS2

LOCKS3

LOCKS4

LOCKS5

Number of Lock Bits

Lock Region 0 Lock Status

Lock Region 1 Lock Status

Lock Region 2 Lock Status

Lock Region 3 Lock Status

Lock Region 4 Lock Status

Lock Region 5 Lock Status

24

LOCKS8

16

LOCKS0

8

GPNVM0

0

FRDY

113

6120D–ATARM–02-Feb-06

MC_FSR, LOCKSx Product Specific Map (Continued)

AT91SAM7X256 AT91SAM7X128 Denomination

LOCKS6

LOCKS7

LOCKS6

LOCKS7

Lock Region 6 Lock Status

Lock Region 7 Lock Status

LOCKS8

LOCKS9

LOCKS10

LOCKS11

Lock Region 8 Lock Status

Lock Region 9 Lock Status

Lock Region 10 Lock Status

Lock Region 11 Lock Status

LOCKS12

LOCKS13

LOCKS14

LOCKS15

Lock Region 12 Lock Status

Lock Region 13 Lock Status

Lock Region 14 Lock Status

Lock Region 15 Lock Status

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21. Fast Flash Programming Interface (FFPI)

21.1

Overview

The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. The serial interface uses the standard IEEE 1149.1 JTAG protocol. It offers an optimized access to all the embedded Flash functionalities.

Although the Fast Flash Programming Mode is a dedicated mode for high volume programming, this mode not designed for in-situ programming.

21.2

Parallel Fast Flash Programming

21.2.1

Device Configuration

In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected.

Figure 21-1. Parallel Programming Interface

VDDIO

VDDIO

VDDIO

TST

PGMEN0

PGMEN1

NCMD

RDY

NOE

NVALID

MODE[3:0]

DATA[15:0]

0 - 50MHz

PGMNCMD

PGMRDY

PGMNOE

PGMNVALID

PGMM[3:0]

PGMD[15:0]

XIN

VDDCORE

VDDIO

VDDPLL

VDDFLASH

GND

115

6120D–ATARM–02-Feb-06

Table 21-1.

Signal Description List

Signal Name

VDDFLASH

VDDIO

VDDCORE

VDDPLL

GND

XIN

TST

PGMEN0

PGMEN1

PGMNCMD

PGMRDY

PGMNOE

PGMNVALID

PGMM[3:0]

PGMD[15:0]

21.2.2

Function Type

Power

Flash Power Supply

I/O Lines Power Supply

Core Power Supply

PLL Power Supply

Ground

Clocks

Main Clock Input.

This input can be tied to GND. In this case, the device is clocked by the internal

RC oscillator.

Test

Test Mode Select

Test Mode Select

Test Mode Select

Power

Power

Power

Power

Ground

Input

Input

Input

Input

PIO

Valid command available

0: Device is busy

1: Device is ready for a new command

Output Enable (active high)

0: DATA[15:0] is in input mode

1: DATA[15:0] is in output mode

Specifies DATA type (See

Table 21-2

)

Bi-directional data bus

Input

Output

Input

Output

Input

Input/Output

Active

Level Comments

High

High

High

Low

High

Low

Low

32KHz to 50MHz

Must be connected to VDDIO

Must be connected to VDDIO

Must be connected to VDDIO

Pulled-up input at reset

Pulled-up input at reset

Pulled-up input at reset

Pulled-up input at reset

Pulled-up input at reset

Pulled-up input at reset

Signal Names

Depending on the MODE settings, DATA is latched in different internal registers.

Table 21-2.

Mode Coding

MODE[3:0] Symbol

0000

0001

0010

0011

0100

0101

Default

CMDE

ADDR0

ADDR1

ADDR2

ADDR2

DATA

IDLE

Data

Command Register

Address Register LSBs

Address Register MSBs

Data Register

No register

116

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AT91SAM7X256/128 Preliminary

21.2.3

21.2.4

When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register.

Table 21-3.

Command Bit Coding

DATA[15:0]

0x0011

Symbol

READ

0x0034

0x0044

0x0025

0x0054

0x0035

0x002F

0x001F

0x001E

0x0012

0x0022

0x0032

0x0042

0x0013

0x0014

0x0024

0x0015

SFB

CFB

GFB

SSE

GSE

RRAM

WRAM

GVE

WP

WPL

EWP

EWPL

EA

SLB

CLB

GLB

Command Executed

Read Flash

Write Page Flash

Write Page and Lock Flash

Erase Page and Write Page

Erase Page and Write Page then Lock

Erase All

Set Lock Bit

Clear Lock Bit

Get Lock Bit

Set General Purpose NVM bit

Clear General Purpose NVM bit

Get General Purpose NVM bit

Set Security Bit

Get Security Bit

Read Memory

Write Memory

Get Version

Entering Programming Mode

The following algorithm puts the device in Parallel Programming Mode:

• Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL.

• Apply XIN clock within T

POR_RESET

if an external clock is available.

• Wait for T

POR_RESET

• Start a read or write handshaking.

Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32 kHz) is connected to XIN, then the device switches on the external clock.

Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer handshake.

Programmer Handshaking

An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal.

The handshaking is achieved once NCMD signal is high and RDY is high.

117

6120D–ATARM–02-Feb-06

21.2.4.1

Write Handshaking

For details on the write handshaking sequence, refer to

Figure 21-2 and Table 21-4

.

Figure 21-2. Parallel Programming Timing, Write Sequence

NCMD

RDY

NOE

NVALID

DATA[15:0]

1

MODE[3:0]

2

3

4

5

Table 21-4.

Write Handshake

Step

3

4

1

2

5

6

21.2.4.2

Programmer Action

Sets MODE and DATA signals

Clears NCMD signal

Waits for RDY low

Releases MODE and DATA signals

Sets NCMD signal

Waits for RDY high

Device Action

Waits for NCMD low

Latches MODE and DATA

Clears RDY signal

Executes command and polls NCMD high

Executes command and polls NCMD high

Sets RDY

Data I/O

Input

Input

Input

Input

Input

Input

Read Handshaking

For details on the read handshaking sequence, refer to

Figure 21-3 and Table 21-5 .

118

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AT91SAM7X256/128 Preliminary

Figure 21-3. Parallel Programming Timing, Read Sequence

NCMD

RDY

NOE

NVALID

DATA[15:0]

1

MODE[3:0]

2

3

Adress IN

ADDR

4

5

Z

12

13

6

7

9

8

Data OUT

11

10

X IN

6

10

11

12

13

7

8

9

Table 21-5.

Read Handshake

Step Programmer Action

3

4

1

2

5

Sets MODE and DATA signals

Clears NCMD signal

Waits for RDY low

Sets DATA signal in tristate

Clears NOE signal

21.2.5

Waits for NVALID low

Reads value on DATA Bus

Sets NOE signal

Waits for NVALID high

Sets DATA in ouput mode

Sets NCMD signal

Waits for RDY high

Device Action

Waits for NCMD low

Latch MODE and DATA

Clears RDY signal

Waits for NOE Low

Sets DATA bus in output mode and outputs the flash contents.

Clears NVALID signal

Waits for NOE high

Sets DATA bus in input mode

Sets NVALID signal

Waits for NCMD high

Sets RDY signal

Output

Output

Output

X

Input

Input

Input

DATA I/O

Input

Input

Input

Input

Tristate

Output

Device Operations

Several commands on the Flash memory are available. These commands are summarized in

Table 21-3 on page 117 . Each command is driven by the programmer through the parallel inter-

face running several read/write handshaking sequences.

When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash.

119

6120D–ATARM–02-Feb-06

21.2.5.1

21.2.5.2

120

Flash Read Command

This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased.

Table 21-6.

Read Command

Step Handshake Sequence

n n+1 n+2 n+3 n+4 n+5

...

7

...

5

6

3

4

1

2

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Read handshaking

Read handshaking

...

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Read handshaking

Read handshaking

...

DATA

...

ADDR0

ADDR1

ADDR2

ADDR3

DATA

DATA

...

MODE[3:0]

CMDE

ADDR0

ADDR1

ADDR2

ADDR3

DATA

DATA[15:0]

READ

32-bit Memory Address First byte

32-bit Flash Address

32-bit Flash Address

32-bit Flash Address Last Byte

*Memory Address++

*Memory Address++

...

32-bit Memory Address First byte

32-bit Flash Address

32-bit Flash Address

32-bit Flash Address Last Byte

*Memory Address++

*Memory Address++

...

Flash Write Command

This command is used to write the Flash contents.

The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the

Flash:

• before access to any page other than the current one

• when a new command is validated (MODE = CMDE)

The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased.

4

5

2

3

6

Table 21-7.

Write Command

Step

1

Handshake Sequence

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

MODE[3:0]

CMDE

ADDR0

ADDR1

ADDR2

ADDR3

DATA

DATA[15:0]

WP or WPL or EWP or EWPL

32-bit Memory Address First byte

32-bit Flash Address

32-bit Flash Address

32-bit Flash Address Last Byte

*Memory Address++

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

21.2.5.3

21.2.5.4

AT91SAM7X256/128 Preliminary

Table 21-7.

Write Command (Continued)

Step

n+2 n+3 n+4 n+5

7

...

n n+1

Handshake Sequence

Write handshaking

...

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

MODE[3:0]

DATA

...

ADDR0

ADDR1

ADDR2

ADDR3

DATA

DATA

DATA[15:0]

*Memory Address++

...

32-bit Memory Address First byte

32-bit Flash Address

32-bit Flash Address

32-bit Flash Address Last Byte

*Memory Address++

*Memory Address++

...

...

...

...

The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command.

However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using

Flash write commands and writes to the last page of the lock region using a Flash write and lock command.

The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command.

However, before programming the load buffer, the page is erased.

The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.

Flash Full Erase Command

This command is used to erase the Flash memory planes.

All lock regions must be unlocked before the Full Erase command by using the CLB command.

Otherwise, the erase command is aborted and no page is erased.

Table 21-8.

Full Erase Command

Step

1

Handshake Sequence

Write handshaking

2 Write handshaking

MODE[3:0]

CMDE

DATA

DATA[15:0]

EA

0

Flash Lock Commands

Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set

Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is activated.

In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are also cleared by the EA command.

121

6120D–ATARM–02-Feb-06

21.2.5.5

Table 21-9.

Set and Clear Lock Bit Command

Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SLB or CLB

2 Write handshaking DATA Bit Mask

Lock bits can be read using Get Lock Bit command (GLB). The n th

lock bit is active when the bit n of the bit mask is set..

Table 21-10. Get Lock Bit Command

Step Handshake Sequence

1 Write handshaking

2 Read handshaking

MODE[3:0]

CMDE

DATA

DATA[15:0]

GLB

Lock Bit Mask Status

0 = Lock bit is cleared

1 = Lock bit is set

Flash General-purpose NVM Commands

General-purpose NVM bits (GP NVM bits) can be set using the Set Fuse command (SFB). This command also activates GP NVM bits. A bit mask is provided as argument to the command.

When bit 0 of the bit mask is set, then the first GP NVM bit is activated.

In the same way, the Clear Fuse command (CFB) is used to clear general-purpose NVM bits.

All the general-purpose NVM bits are also cleared by the EA command. The general-purpose

NVM bit is deactived when the corresponding bit in the pattern value is set to 1.

Table 21-11. Set/Clear GP NVM Command

Step Handshake Sequence

1

2

Write handshaking

Write handshaking

MODE[3:0]

CMDE

DATA

DATA[15:0]

SFB or CFB

GP NVM bit pattern value

General-purpose NVM bits can be read using the Get Fuse Bit command (GFB). The n th

GP

NVM bit is active when bit n of the bit mask is set..

Table 21-12. Get GP NVM Bit Command

Step

1

Handshake Sequence

Write handshaking

MODE[3:0]

CMDE

2 Read handshaking DATA

DATA[15:0]

GFB

GP NVM Bit Mask Status

0 = GP NVM bit is cleared

1 = GP NVM bit is set

122

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21.2.5.6

21.2.5.7

21.2.5.8

AT91SAM7X256/128 Preliminary

Flash Security Bit Command

A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the

Erase pin can erase the security bit once the contents of the Flash have been erased.

Table 21-13. Set Security Bit Command

Step Handshake Sequence

1

2

Write handshaking

Write handshaking

MODE[3:0]

CMDE

DATA

DATA[15:0]

SSE

0

Memory Read Command

This command (RRAM) is used to perform a read access to any memory location. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased.

Table 21-14. Read Command

Step

1

Handshake Sequence

Write handshaking n+1 n+2 n+3 n+4 n+5

...

...

n

6

7

4

5

2

3

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Read handshaking

Read handshaking

...

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Read handshaking

Read handshaking

...

...

ADDR0

ADDR1

ADDR2

ADDR3

DATA

DATA

...

MODE[3:0]

CMDE

ADDR0

ADDR1

ADDR2

ADDR3

DATA

DATA

DATA[15:0]

RRAM

32-bit Memory Address First byte

32-bit Flash Address

32-bit Flash Address

32-bit Flash Address Last Byte

*Memory Address++

*Memory Address++

...

32-bit Memory Address First byte

32-bit Flash Address

32-bit Flash Address

32-bit Flash Address Last Byte

*Memory Address++

*Memory Address++

...

Memory Write Command

This command is used to perform a write access to any memory location.

The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased.

123

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21.2.5.9

Table 21-15. Write Command

Step Handshake Sequence

n n+1 n+2 n+3 n+4 n+5

...

7

...

5

6

3

4

1

2

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

...

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

Write handshaking

...

DATA

...

ADDR0

ADDR1

ADDR2

ADDR3

DATA

DATA

...

MODE[3:0]

CMDE

ADDR0

ADDR1

ADDR2

ADDR3

DATA

DATA[15:0]

WRAM

32-bit Memory Address First byte

32-bit Flash Address

32-bit Flash Address

32-bit Flash Address Last Byte

*Memory Address++

*Memory Address++

...

32-bit Memory Address First byte

32-bit Flash Address

32-bit Flash Address

32-bit Flash Address Last Byte

*Memory Address++

*Memory Address++

...

Get Version Command

The Get Version (GVE) command retrieves the version of the FFPI interface.

Table 21-16. Get Version Command

Step Handshake Sequence

1

2

Write handshaking

Write handshaking

MODE[3:0]

CMDE

DATA

DATA[15:0]

GVE

Version

124

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

21.3

Serial Fast Flash Programming

The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test

Access Port and Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a description of the TAP controller states.

In this mode, data read/written from/to the embedded Flash of the device are transmitted through the JTAG interface of the device.

21.3.1

Device Configuration

In Serial Fast Flash Programming Mode, the device is in a specific test mode. Only a distinct set of pins is significant. Other pins must be left unconnected.

Figure 21-4. Serial Programming

VDDIO

VDDIO

VDDIO

TST

PGMEN0

PGMEN1

TDI

TDO

TMS

TCK

VDDCORE

VDDIO

VDDPLL

VDDFLASH

GND

0-50MHz

XIN

Table 21-17. Signal Description List

Signal Name

VDDFLASH

VDDIO

VDDCORE

VDDPLL

GND

XIN

Function Type

Power

Flash Power Supply

I/O Lines Power Supply

Core Power Supply

Power

Power

Power

PLL Power Power Supply

Ground

Clocks

Main Clock Input.

This input can be tied to GND. In this case, the device is clocked by the internal

RC oscillator.

Power

Ground

Input

Active

Level Comments

32 kHz to 50 MHz

6120D–ATARM–02-Feb-06

125

Table 21-17. Signal Description List (Continued)

Signal Name Function Type

Active

Level Comments

Test

TCK

TDI

TDO

TMS

21.3.2

TST

PGMEN0

PGMEN1

Test Mode Select

Test Mode Select

Test Mode Select

Input

Input

Input

High

High

High

Must be connected to VDDIO.

Must be connected to VDDIO

Must be connected to VDDIO

JTAG

JTAG TCK

JTAG Test Data In

JTAG Test Data Out

JTAG Test Mode Select

Input

Input

Output

Input -

-

-

Pulled-up input at reset

Pulled-up input at reset

Pulled-up input at reset

Entering Serial Programming Mode

The following algorithm puts the device in Serial Programming Mode:

• Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL.

• Apply XIN clock within T

POR_RESET

+ 32(T

SCLK

) if an external clock is available.

• Wait for T

POR_RESET

.

• Reset the TAP controller clocking 5 TCK pulses with TMS set.

• Shift 0x2 into the IR register ( IR is 4 bits long, LSB first) without going through the Run-Test-

Idle state.

• Shift 0x2 into the DR register ( DR is 4 bits long, LSB first) without going through the Run-

Test-Idle state.

• Shift 0xC into the IR register ( IR is 4 bits long, LSB first) without going through the Run-Test-

Idle state.

Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32 kHz) is connected to XIN, then the device will switch on the external clock.

Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer handshake.

Table 21-18. Reset TAP controller and go to Select-DR-Scan

TDI TMS TAP Controller State

X

X

Xt

X

X

X

X

1

0

1

1

1

1

1

Test-Logic Reset

Run-Test/Idle

Select-DR-Scan

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AT91SAM7X256/128 Preliminary

21.3.3

Read/Write Handshake

Two registers of the device are accessible through the JTAG:

• Debug Comms Control Register: DCCR

• Debug Comms Data Register: DCDR

Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A register is read by scanning its address into the address field and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data. The 32-bit data field is ignored.

Figure 21-5. TAP 8-bit DR Register

TDI r/w

4

Address

0 31

Data

0

TDO

5

32

Address

Decoder

Debug Comms Control Register

Debug Comms Control Register

A read or write takes place when the TAP controller enters UPDATE-DR state.

• The address of the Debug Comms Control Register is 0x04.

• The address of the Debug Comms Data Register is 0x05.

The Debug Comms Control Register is read-only and allows synchronized handshaking between the processor and the debugger.

• Bit 1 (W): Denotes whether the programmer can read a data through the Debug Comms Data

Register. If the device is busy W = 0, then the programmer must poll until W = 1.

• Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data

Register. If R = 1, data previously placed there through the scan chain has not been collected by the device and so the programmer must wait.

21.3.4

21.3.4.1

Device Operations

Several commands on the Flash memory are available. These commands are summarized in

Table 21-3 on page 117 . Commands are run by the programmer through the serial interface that

is reading and writing the Debug Comms Registers.

Flash Read Command

This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at

127

6120D–ATARM–02-Feb-06

21.3.4.2

any valid address in the memory plane. This address must be word-aligned. The address is automatically incremented.

Table 21-19. Read Command

Read/Write

Write

DR Data

(Number of Words to Read) << 16 | READ

Write

Read

Read

...

Read

Address

Memory [address]

Memory [address+4]

...

Memory [address+(Number of Words to Read - 1)* 4]

Flash Write Command

This command is used to write the Flash contents. The address transmitted must be a valid

Flash address in the memory plane.

The Flash memory plane is organized into several pages. Data to be written is stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the

Flash:

• before access to any page than the current one

• at the end of the number of words transmitted

The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased.

Table 21-20. Write Command

Read/Write DR Data

Write

Write

Write

Write

Write

Write

(Number of Words to Write) << 16 | (WP or WPL or EWP or EWPL)

Address

Memory [address]

Memory [address+4]

Memory [address+8]

Memory [address+(Number of Words to Write - 1)* 4]

Flash Write Page and Lock command (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using

Flash write commands and writes to the last page of the lock region using a Flash write and lock command.

Flash Erase Page and Write command (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased.

Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL commands.

128

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21.3.4.3

21.3.4.4

21.3.4.5

AT91SAM7X256/128 Preliminary

Flash Full Erase Command

This command is used to erase the Flash memory planes.

All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB command.

Table 21-21. Full Erase Command

Read/Write DR Data

Write EA

Flash Lock Commands

Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set

Lock command (SLB). With this command, several lock bits can be activated at the same time.

Bit 0 of Bit Mask corresponds to the first lock bit and so on.

In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits can also be cleared by the EA command.

Table 21-22. Set and Clear Lock Bit Command

Read/Write DR Data

Write

Write

SLB or CLB

Bit Mask

Lock bits can be read using Get Lock Bit command (GLB). When a bit set in the Bit Mask is returned, then the corresponding lock bit is active.

Table 21-23. Get Lock Bit Command

Read/Write

Write

DR Data

GLB

Read Bit Mask

Flash General-purpose NVM Commands

General-purpose NVM bits (GP NVM) can be set with the Set Fuse command (SFB). Using this command, several GP NVM bits can be activated at the same time. Bit 0 of Bit Mask corresponds to the first fuse bit and so on.

In the same way, the Clear Fuse command (CFB) is used to clear GP NVM bits. All the generalpurpose NVM bits are also cleared by the EA command.

Table 21-24. Set and Clear General-purpose NVM Bit Command

Read/Write DR Data

Write

Write

SFB or CFB

Bit Mask

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21.3.4.6

21.3.4.7

21.3.4.8

GP NVM bits can be read using Get Fuse Bit command (GFB). When a bit set in the Bit Mask is returned, then the corresponding fuse bit is set.

Table 21-25. Get General-purpose NVM Bit Command

Read/Write

Write

DR Data

GFB

Read Bit Mask

Flash Security Bit Command

Security bits can be set using Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. Only an event on the

Erase pin can erase the security bit once the contents of the Flash have been erased.

Table 21-26. Set Security Bit Command

Read/Write DR Data

Write SSE

Memory Read Command

This command is used to perform a read access to any memory location. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. An internal address buffer is automatically increased.

Table 21-27. Read Command

Read/Write DR Data

Write

Write

Read

Read

...

Read

(Number of Words to Read) << 16 | RRAM

Address

Memory [address]

Memory [address+4]

...

Memory [address+(Number of Words to Read - 1)* 4]

Memory Write Command

This command is used to perform a write access to any memory location.

The Memory Write command (WRAM) is optimized for consecutive writes. An internal address buffer is automatically increased.

Table 21-28. Write Command

Read/Write

Write

DR Data

(Number of Words to Write) << 16 | (WRAM)

Write

Write

Address

Memory [address]

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Table 21-28. Write Command

Read/Write DR Data

Write

Write

Write

Memory [address+4]

Memory [address+8]

Memory [address+(Number of Words to Write - 1)* 4]

Get Version Command

The Get Version (GVE) command retrieves the version of the FFPI interface.

Table 21-29. Get Version Command

Read/Write DR Data

Write

Read

GVE

Version

6120D–ATARM–02-Feb-06

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22. AT91SAM Boot Program

22.1

Description

The Boot Program integrates different programs permitting download and/or upload into the different memories of the product.

First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port.

SAM-BA

Boot is then executed. It waits for transactions either on the USB device, or on the

DBGU serial port.

22.2

Flow Diagram

The Boot Program implements the algorithm in Figure 22-1 .

Figure 22-1. Boot Program Algorithm Flow Diagram

AutoBaudrate

Sequence

Run SAM-BA Boot

Device

Setup

OR

USB Enumeration

Successful

Run SAM-BA Boot

22.3

Device Initialization

Initialization follows the steps described below:

1.

FIQ initialization

1.

Stack setup for ARM supervisor mode

2.

Setup the Embedded Flash Controller

3.

External Clock detection

4.

Main oscillator frequency detection if no external clock detected

5.

Switch Master Clock on Main Oscillator

6.

Copy code into SRAM

7.

C variable initialization

8.

PLL setup: PLL is initialized to generate a 48 MHz clock necessary to use the USB

Device

9.

Disable of the Watchdog and enable of the user reset

10. Initialization of the USB Device Port

11. Jump to SAM-BA Boot sequence (see ”SAM-BA Boot” on page 133

)

22.4

SAM-BA Boot

The SAM-BA boot principle is to:

– Wait for USB Device enumeration

– Execute the AutoBaudrate sequence in parallel (see Figure 22-2 )

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Figure 22-2. AutoBaudrate Flow Diagram

Device

Setup

Character '0x80' received ?

Yes

Character '0x80' received ?

Yes

Character '#' received ?

Yes

Send Character '>'

No

No

No

1st measurement

2nd measurement

Test Communication

UART operational

Run SAM-BA Boot

– Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in

Table 22-1 .

Table 22-1.

Commands Available through the SAM-BA Boot

Command Action Argument(s) Example

G

V

S

R

W w

H h

O o

write a byte read a byte write a half word read a half word write a word read a word send a file receive a file go display version

Address, Value#

Address,#

Address, Value#

Address,#

Address, Value#

Address,#

Address,#

Address, NbOfBytes#

Address#

No argument

O200001,CA#

o200001,#

H200002,CAFE#

h200002,#

W200000,CAFEDECA#

w200000,#

S200000,#

R200000,1234#

G200200#

V#

• Write commands: Write a byte (O), a halfword (H) or a word (W) to the target.

Address: Address in hexadecimal.

Value: Byte, halfword or word to write in hexadecimal.

Output: ‘>’.

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22.4.1

22.4.2

• Read commands: Read a byte (o), a halfword (h) or a word (w) from the target.

Address: Address in hexadecimal

Output: The byte, halfword or word read in hexadecimal following by ‘>’

• Send a file (S): Send a file to a specified address

Address: Address in hexadecimal

Output: ‘>’.

Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution.

• Receive a file (R): Receive data into a file from a specified address

Address: Address in hexadecimal

NbOfBytes

: Number of bytes in hexadecimal to receive

Output: ‘>’

• Go (G): Jump to a specified address and execute the code

Address: Address to jump in hexadecimal

Output: ‘>’

• Get Version (V): Return the SAM-BA boot version

Output: ‘>’

DBGU Serial Port

Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1.

The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work.

Xmodem Protocol

The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error.

Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like:

<SOH><blk #><255-blk #><--128 data bytes--><checksum> in which:

– <SOH> = 01 hex

– <blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H

(not to 01)

– <255-blk #> = 1’s complement of the blk#.

– <checksum> = 2 bytes CRC16

Figure 22-3 shows a transmission using this protocol.

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Figure 22-3. Xmodem Transfer Example

Host

C

SOH 01 FE Data[128] CRC CRC

ACK

SOH 02 FD Data[128] CRC CRC

ACK

SOH 03 FC Data[100] CRC CRC

ACK

EOT

ACK

Device

22.4.3

22.4.3.1

USB Device Port

A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration.

The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows

®

, from Windows 98SE to Windows XP. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports.

The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID.

Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document

“USB Basic Application”, literature number 6123, for more details.

Enumeration Process

The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification.

Table 22-2.

Handled Standard Requests

Request

GET_DESCRIPTOR

Definition

Returns the current device configuration value.

SET_ADDRESS

SET_CONFIGURATION

GET_CONFIGURATION

Sets the device address for all future device access.

Sets the device configuration.

Returns the current device configuration value.

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22.4.3.2

Table 22-2.

Handled Standard Requests (Continued)

Request Definition

GET_STATUS

SET_FEATURE

CLEAR_FEATURE

Returns status for the specified recipient.

Used to set or enable a specific feature.

Used to clear or disable a specific feature.

The device also handles some class requests defined in the CDC class.

Table 22-3.

Handled Class Requests

Request Definition

SET_LINE_CODING

GET_LINE_CODING

SET_CONTROL_LINE_STATE

Configures DTE rate, stop bits, parity and number of character bits.

Requests current DTE rate, stop bits, parity and number of character bits.

RS-232 signal used to tell the DCE device the DTE device is now present.

Unhandled requests are STALLed.

Communication Endpoints

There are two communication endpoints and endpoint 0 is used for the enumeration process.

Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint.

SAM-BA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver.

If the command requires a response, the host can send IN transactions to pick up the response.

22.5

Hardware and Software Constraints

• SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available size for the user code is 57344 bytes for

AT91SAM7X256 and 24576 bytes for AT91SAM7X128.

• USB requirements:

– 18.432 MHz Quartz

Table 22-4.

User Area Addresses

Device Start Address

AT91SAM7X256

AT91SAM7X128

0x202000

0x202000

End Address

0x210000

0x208000

Size (bytes)

57344

24576

Table 22-5.

Pins Driven during Boot Program Execution

Peripheral

DBGU

Pin

DRXD

DBGU DTXD

PIO Line

PA27

PA28

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23. Peripheral DMA Controller (PDC)

23.1

Overview

The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral

DMA Contoller avoids processor intervention and removes the processor interrupt-handling overhead. This significantly reduces the number of clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and makes it more power efficient.

The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral. One channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each UART, USART, SSC and SPI.

The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains:

• A 32-bit memory pointer register

• A 16-bit transfer count register

• A 32-bit register for next memory pointer

• A 16-bit register for next transfer count

The peripheral triggers PDC transfers using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral.

23.2

Block Diagram

Figure 23-1. Block Diagram

Peripheral DMA Controller

Peripheral

THR PDC Channel 0

RHR

PDC Channel 1 Control

Memory

Controller

Status & Control

Control

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6120D–ATARM–02-Feb-06

23.3

Functional Description

23.3.1

Configuration

The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to.

Per peripheral, it contains four 32-bit Pointer Registers (RPR, RNPR, TPR, and TNPR) and four

16-bit Counter Registers (RCR, RNCR, TCR, and TNCR).

The size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel.

The memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. It is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC Transfer Control Register. These control bits enable reading the pointer and counter registers safely without any risk of their changing between both reads.

The PDC sends status flags to the peripheral visible in its status-register (ENDRX, ENDTX,

RXBUFF, and TXBUFE).

ENDRX flag is set when the PERIPH_RCR register reaches zero.

RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.

ENDTX flag is set when the PERIPH_TCR register reaches zero.

TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.

These status flags are described in the peripheral status register.

23.3.2

Memory Pointers

Each peripheral is connected to the PDC by a receiver data channel and a transmitter data channel. Each channel has an internal 32-bit memory pointer. Each memory pointer points to a location anywhere in the memory space (on-chip memory or external bus interface memory).

Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4, respectively for peripheral transfers.

If a memory pointer is reprogrammed while the PDC is in operation, the transfer address is changed, and the PDC performs transfers using the new address.

23.3.3

Transfer Counters

There is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its associated channel. These counters are decremented after each data transfer. When the counter reaches zero, the transfer is complete and the PDC stops transferring data.

If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag.

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23.3.4

23.3.5

If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value.

Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to re-enable the triggers.

For each channel, two status bits indicate the end of the current buffer (ENDRX, ENTX) and the end of both current and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the peripheral status register and can trigger an interrupt request to the AIC.

The peripheral end flag is automatically cleared when one of the counter-registers (Counter or

Next Counter Register) is written.

Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero.

Data Transfers

The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals.

When the peripheral receives an external character, it sends a Receive Ready signal to the PDC which then requests access to the system bus. When access is granted, the PDC starts a read of the peripheral Receive Holding Register (RHR) and then triggers a write in the memory.

After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decremented. When the memory block size is reached, a signal is sent to the peripheral and the transfer stops.

The same procedure is followed, in reverse, for transmit transfers.

Priority of PDC Transfer Requests

The Peripheral DMA Controller handles transfer requests from the channel according to priorities fixed for each product.These priorities are defined in the product datasheet.

If simultaneous requests of the same type (receiver or transmitter) occur on identical peripherals, the priority is determined by the numbering of the peripherals.

If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests.

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23.4

Peripheral DMA Controller (PDC) User Interface

Table 23-1.

Peripheral DMA Controller (PDC) Register Mapping

Offset

0x100

0x104

0x108

0x10C

0x110

0x114

0x118

0x11C

0x120

0x124

Register

Receive Pointer Register

Receive Counter Register

Transmit Pointer Register

Transmit Counter Register

Receive Next Pointer Register

Receive Next Counter Register

Transmit Next Pointer Register

Transmit Next Counter Register

PDC Transfer Control Register

PDC Transfer Status Register

Register Name

PERIPH

(1)

_RPR

PERIPH_RCR

PERIPH_TPR

PERIPH_TCR

PERIPH_RNPR

PERIPH_RNCR

PERIPH_TNPR

PERIPH_TNCR

PERIPH_PTCR

PERIPH_PTSR

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Write-only

Read-only

0x0

0x0

-

0x0

Reset

0x0

0x0

0x0

0x0

0x0

0x0

Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc).

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23.4.1

PDC Receive Pointer Register

Register Name:

PERIPH_RPR

Access Type:

Read/Write

31 30 29

23

15

7

22

14

6

21

13

5

• RXPTR: Receive Pointer Address

Address of the next receive transfer.

23.4.2

PDC Receive Counter Register

Register Name:

PERIPH_RCR

Access Type:

Read/Write

31 30 29

23

15

7

22

14

6

21

13

5

• RXCTR: Receive Counter Value

Number of receive transfers to be performed.

28

RXPTR

27

20 19

RXPTR

12 11

RXPTR

4 3

RXPTR

28 27

--

20 19

--

12

RXCTR

11

4 3

RXCTR

26

18

10

2

26

18

10

2

25

17

9

1

25

17

9

1

24

16

8

0

24

16

8

0

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23.4.3

PDC Transmit Pointer Register

Register Name:

PERIPH_TPR

Access Type:

Read/Write

31 30 29

23

15

7

22

14

6

21

13

5

• TXPTR: Transmit Pointer Address

Address of the transmit buffer.

28

TXPTR

27

20 19

TXPTR

12 11

TXPTR

4 3

TXPTR

26

18

10

2

25

17

9

1

23.4.4

PDC Transmit Counter Register

Register Name:

PERIPH_TCR

Access Type:

Read/Write

31 30 29 28 27 26 25

--

23 22 21 20 19 18 17

--

15 14 13 12 11 10 9

TXCTR

7 6 5 4 3 2 1

TXCTR

• TXCTR: Transmit Counter Value

TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral DMA transfer is stopped.

24

16

8

0

24

16

8

0

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23.4.5

PDC Receive Next Pointer Register

Register Name:

PERIPH_RNPR

Access Type:

Read/Write

31 30 29 28 27 26 25

RXNPTR

23 22 21 20 19 18

RXNPTR

15 14 13 12 11 10

RXNPTR

7 6 5 4 3 2

RXNPTR

• RXNPTR: Receive Next Pointer Address

RXNPTR is the address of the next buffer to fill with received data when the current buffer is full.

17

9

1

24

16

8

0

23.4.6

PDC Receive Next Counter Register

Register Name:

PERIPH_RNCR

Access Type:

Read/Write

31 30 29 28

23

15

7

22

14

6

21

13

5

27

--

20 19

--

12

RXNCR

11

4 3

RXNCR

• RXNCR: Receive Next Counter Value

RXNCR is the size of the next buffer to receive.

10

2

26

18

9

1

25

17

8

0

24

16

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23.4.7

PDC Transmit Next Pointer Register

Register Name:

PERIPH_TNPR

Access Type:

Read/Write

31 30 29 28 27 26

TXNPTR

23 22 21 20 19 18

TXNPTR

15 14 13 12 11 10

TXNPTR

7 6 5 4 3 2

TXNPTR

• TXNPTR: Transmit Next Pointer Address

TXNPTR is the address of the next buffer to transmit when the current buffer is empty.

23.4.8

PDC Transmit Next Counter Register

Register Name:

PERIPH_TNCR

Access Type:

Read/Write

31 30 29 28

23

15

7

22

14

6

21

13

5

27

--

20 19

--

12

TXNCR

11

4 3

TXNCR

• TXNCR: Transmit Next Counter Value

TXNCR is the size of the next buffer to transmit.

10

2

26

18

25

17

9

1

9

1

25

17

24

16

8

0

8

0

24

16

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23.4.9

PDC Transfer Control Register

Register Name:

Access Type:

PERIPH_PTCR

Write

only

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

• RXTEN: Receiver Transfer Enable

0 = No effect.

1 = Enables the receiver PDC transfer requests if RXTDIS is not set.

• RXTDIS: Receiver Transfer Disable

0 = No effect.

1 = Disables the receiver PDC transfer requests.

27

19

11

3

• TXTEN: Transmitter Transfer Enable

0 = No effect.

1 = Enables the transmitter PDC transfer requests.

• TXTDIS: Transmitter Transfer Disable

0 = No effect.

1 = Disables the transmitter PDC transfer requests

26

18

10

2

25

17

9

TXTDIS

1

RXTDIS

24

16

8

TXTEN

0

RXTEN

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23.4.10

PDC Transfer Status Register

Register Name:

PERIPH_PTSR

Access Type:

Read-only

31

30

29

23

15

7

22

14

6

21

13

5

• RXTEN: Receiver Transfer Enable

0 = Receiver PDC transfer requests are disabled.

1 = Receiver PDC transfer requests are enabled.

• TXTEN: Transmitter Transfer Enable

0 = Transmitter PDC transfer requests are disabled.

1 = Transmitter PDC transfer requests are enabled.

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

1

24

16

8

TXTEN

0

RXTEN

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24. Advanced Interrupt Controller (AIC)

24.1

Overview

The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts.

The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins.

The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated.

Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or highlevel or low-level sensitive.

The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt.

24.2

Block Diagram

Figure 24-1. Block Diagram

FIQ

IRQ0-IRQn

Embedded

AIC

Up to

Thirty-two

Sources

ARM

Processor nFIQ nIRQ

Peripheral

APB

24.3

Application Block Diagram

Figure 24-2. Description of the Application Block

Standalone

Applications

OS Drivers

OS-based Applications

RTOS Drivers

Hard Real Time Tasks

General OS Interrupt Handler

Advanced Interrupt Controller

Embedded Peripherals

External Peripherals

(External Interrupts)

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24.4

AIC Detailed Block Diagram

Figure 24-3. AIC Detailed Block Diagram

FIQ

PIO

Controller

External

Source

Input

Stage

Advanced Interrupt Controller

Fast

Interrupt

Controller

IRQ0-IRQn

PIOIRQ

Fast

Forcing

Interrupt

Priority

Controller

Embedded

Peripherals

Internal

Source

Input

Stage

User Interface

ARM

Processor nFIQ nIRQ

Processor

Clock

Power

Management

Controller

Wake Up

APB

24.5

I/O Line Description

Table 24-1.

I/O Line Description

Pin Name Pin Description

FIQ

IRQ0 - IRQn

Fast Interrupt

Interrupt 0 - Interrupt n

Type

Input

Input

24.6

Product Dependencies

24.6.1

I/O Lines

The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path.

24.6.2

24.6.3

Power Management

The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior.

The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the

ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.

Interrupt Sources

The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the

Interrupt Source 0 cannot be used.

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The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines, such as the System Timer, the Real Time Clock, the

Power Management Controller and the Memory Controller. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals.

The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller.

The PIO Controllers are considered as user peripherals in the scope of interrupt handling.

Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31.

The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.

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24.7

Functional Description

24.7.1

24.7.1.1

Interrupt Source Control

Interrupt Source Mode

The Advanced Interrupt Controller independently programs each interrupt source. The SRC-

TYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source.

The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user.

The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes.

24.7.1.2

Interrupt Source Enabling

Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt

Disable Command Register). This set of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts.

24.7.1.3

24.7.1.4

Interrupt Clearing and Setting

All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in level-sensitive mode has no effect.

The clear operation is perfunctory, as the software must perform an action to reinitialize the

“memorization” circuitry activated when the source is programmed in edge-triggered mode.

However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt.

The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector

Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is

affected by this operation. ( See “Priority Controller” on page 155.

) The automatic clear reduces

the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature

enabled as it is considered uniquely as an FIQ source. ( See “Fast Forcing” on page 159.

)

The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.

Interrupt Status

For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not.

The AIC_ISR register reads the number of the current interrupt (see ”Priority Controller” on page

155

) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor.

Each status referred to above can be used to optimize the interrupt handling of the systems.

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24.7.1.6

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Internal Interrupt Source Input Stage

Figure 24-4. Internal Interrupt Source Input Stage

Source i

AIC_SMRI

(SRCTYPE)

Level/

Edge

AIC_IPR

AIC_IMR

Edge

Detector

Set Clear

Fast Interrupt Controller or

Priority Controller

AIC_IECR

FF

AIC_ISCR

AIC_ICCR

AIC_IDCR

External Interrupt Source Input Stage

Figure 24-5. External Interrupt Source Input Stage

High/Low

AIC_SMRi

SRCTYPE

Level/

Edge

AIC_IPR

AIC_IMR

Source i

Fast Interrupt Controller or

Priority Controller

AIC_IECR

Pos./Neg.

Edge

Detector

Set Clear

FF

AIC_ISCR

AIC_ICCR

AIC_IDCR

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24.7.2

24.7.2.1

Interrupt Latencies

Global interrupt latencies depend on several parameters, including:

• The time the software masks the interrupts.

• Occurrence, either at the processor level or at the AIC level.

• The execution time of the instruction in progress when the interrupt occurs.

• The treatment of higher priority interrupts and the resynchronization of the hardware signals.

This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress.

The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.

External Interrupt Edge Triggered Source

Figure 24-6. External Interrupt Edge Triggered Source

MCK

IRQ or FIQ

(Positive Edge)

IRQ or FIQ

(Negative Edge) nIRQ

Maximum IRQ Latency = 4 Cycles

24.7.2.2

nFIQ

Maximum FIQ Latency = 4 Cycles

External Interrupt Level Sensitive Source

Figure 24-7. External Interrupt Level Sensitive Source

MCK

IRQ or FIQ

(High Level)

IRQ or FIQ

(Low Level) nIRQ

Maximum IRQ

Latency = 3 Cycles nFIQ

Maximum FIQ

Latency = 3 cycles

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Internal Interrupt Edge Triggered Source

Figure 24-8. Internal Interrupt Edge Triggered Source

MCK nIRQ

24.7.2.4

Maximum IRQ Latency = 4.5 Cycles

Peripheral Interrupt

Becomes Active

Internal Interrupt Level Sensitive Source

Figure 24-9. Internal Interrupt Level Sensitive Source

MCK nIRQ

Maximum IRQ Latency = 3.5 Cycles

Peripheral Interrupt

Becomes Active

24.7.3

24.7.3.1

Normal Interrupt

Priority Controller

An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast

Forcing).

Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest.

As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SVR

(Source Vector Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The

read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software.

The current priority level is defined as the priority level of the current interrupt.

If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first.

The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in

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24.7.3.2

24.7.3.3

24.7.3.4

progress, it is delayed until the software indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the

exit point of the interrupt handling.

Interrupt Nesting

The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level.

When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written.

The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels.

Interrupt Vectoring

The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads

AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned.

This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction:

LDR PC,[PC,# -&F20]

When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler.

This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt.

However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system’s general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system.

Interrupt Handlers

This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits.

It is assumed that:

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1.

The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled.

2.

The instruction at the ARM interrupt exception vector address is required to work with the vectoring

LDR PC, [PC, # -&F20]

When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:

1.

The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18.

In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four.

2.

The ARM core enters Interrupt mode, if it has not already done so.

3.

When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects:

– Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt.

– De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ.

– Automatically clears the interrupt, if it has been programmed to be edge-triggered.

– Pushes the current level and the current interrupt number on to the stack.

– Returns the value written in the AIC_SVR corresponding to the current interrupt.

4.

The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction

SUB PC,

LR, #4

may be used.

5.

Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing reassertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs.

6.

The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1.

Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase.

7.

The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner.

8.

The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the “I” bit is set in the core.

SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq.

Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked).

157

24.7.4

24.7.4.1

Fast Interrupt

Fast Interrupt Source

The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to an FIQ pin of the product, either directly or through a PIO Controller.

24.7.4.2

Fast Interrupt Control

The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive

Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt

Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of

AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.

24.7.4.3

24.7.4.4

Fast Interrupt Vectoring

The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction:

LDR PC,[PC,# -&F20]

When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode.

Fast Interrupt Handlers

This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits.

Assuming that:

1.

The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled.

2.

The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt:

LDR PC, [PC, # -&F20]

3.

The user does not need nested fast interrupts.

When nFIQ is asserted, if the bit "F" of CPSR is 0, the sequence is:

1.

The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four.

2.

The ARM core enters FIQ mode.

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3.

When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor.

4.

The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed.

5.

The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to

R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0.

6.

Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four

(with instruction

SUB PC, LR, #4

for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the

SPSR.

Note: The "F" bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask

FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked).

Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction.

Fast Forcing

The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal

Interrupt source on the fast interrupt controller.

Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source.

When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages.

When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler.

If the interrupt source is programmed in level-sensitive mode and an active level is sampled,

Fast Forcing results in the assertion of the nFIQ line to the core.

If the interrupt source is programmed in edge-triggered mode and an active edge is detected,

Fast Forcing results in the assertion of the nFIQ line to the core.

The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR).

The Fast Interrupt Vector Register (AIC_FVR) reads the contents of the Source Vector Register

0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not

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clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR).

All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command

Register. In doing so, they are cleared independently and thus lost interrupts are prevented.

The read of AIC_IVR does not clear the source that has the fast forcing feature enabled.

The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources.

Figure 24-10. Fast Forcing

Source 0

_

FIQ

Input Stage

AIC_IPR

Automatic Clear AIC_IMR nFIQ

Source n

Input Stage

Automatic Clear

Read FVR if Fast Forcing is disabled on Sources 1 to 31.

AIC_FFSR

AIC_IPR

AIC_IMR

Priority

Manager nIRQ

Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n.

24.7.5

Protect Mode

The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR.

This has undesirable consequences:

• If an enabled interrupt with a higher priority than the current one is pending, it is stacked.

• If there is no enabled pending interrupt, the spurious vector is returned.

In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state.

This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode.

When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the

Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written.

An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the

AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to

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24.7.6

24.7.7

not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context.

To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC:

1.

Calculates active interrupt (higher than current or spurious).

2.

Determines and returns the vector of the active interrupt.

3.

Memorizes the interrupt.

4.

Pushes the current priority level onto the internal stack.

5.

Acknowledges the interrupt.

However, while the Protect Mode is activated, only operations 1 to 3 are performed when

AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written.

Software that has been written and debugged using the Protect Mode runs correctly in Normal

Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code.

Spurious Interrupt

The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when:

• An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time.

• An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the

Watchdog.)

• An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source.

The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in

AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt.

General Interrupt Mask

The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor.

Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR

(Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution.

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24.8

Advanced Interrupt Controller (AIC) User Interface

24.8.1

Base Address

The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only an ± 4-Kbyte offset.

Table 24-2.

Advanced Interrupt Controller (AIC) Register Mapping

Offset Register Name Access Reset Value

0x100

0x104

0x108

0x10C

0x110

0x114

0x118

0x11C

0000

0x04

---

0x7C

0x80

0x84

---

0xFC

0x120

0x124

0x128

0x12C

0x130

0x134

0x138

0x13C

0x140

0x144

Source Mode Register 0

Source Mode Register 1

---

Source Mode Register 31

Source Vector Register 0

Source Vector Register 1

---

Source Vector Register 31

Interrupt Vector Register

Fast Interrupt Vector Register

Interrupt Status Register

Interrupt Pending Register

Interrupt Mask Register

Core Interrupt Status Register

Reserved

Reserved

Interrupt Enable Command Register

Interrupt Disable Command Register

Interrupt Clear Command Register

Interrupt Set Command Register

End of Interrupt Command Register

Spurious Interrupt Vector Register

Debug Control Register

Reserved

Fast Forcing Enable Register

Fast Forcing Disable Register

AIC_SMR0

AIC_SMR1

---

AIC_SMR31

AIC_SVR0

AIC_SVR1

---

AIC_SVR31

AIC_IVR

AIC_FVR

AIC_ISR

AIC_IPR

AIC_IMR

AIC_CISR

---

---

AIC_IECR

AIC_IDCR

AIC_ICCR

AIC_ISCR

AIC_EOICR

AIC_SPU

AIC_DCR

---

AIC_FFER

AIC_FFDR

Read/Write

Read/Write

---

Read/Write

Read/Write

Read/Write

---

Read/Write

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

---

---

Write-only

Write-only

Write-only

Write-only

Write-only

Read/Write

Read/Write

---

Write-only

Write-only

0x148 Fast Forcing Status Register AIC_FFSR Read-only 0x0

Note: 1.

The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending.

0x0

0x0

---

---

0x0

0x0

0x0

0x0

(1)

0x0

0x0

---

0x0

0x0

0x0

---

0x0

---

0x0

0x0

---

---

---

---

---

---

---

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24.8.2

AIC Source Mode Register

Register Name: AIC_SMR0..AIC_SMR31

Access Type:

Read/Write

Reset Value: 0x0

15

7

31

23

14

6

30

22

SRCTYPE

13

5

29

21

12

4

28

20

11

3

27

19

• PRIOR: Priority Level

Programs the priority level for all sources except FIQ source (source 0).

The priority level can be between 0 (lowest) and 7 (highest).

The priority level is not used for the FIQ in the related SMR register AIC_SMRx.

• SRCTYPE: Interrupt Source Type

The active level or edge is not programmable for the internal interrupt sources.

10

2

26

18

1

1

0

0

SRCTYPE

0

1

0

1

Internal Interrupt Sources

High level Sensitive

Positive edge triggered

High level Sensitive

Positive edge triggered

25

17

9

1

PRIOR

External Interrupt Sources

Low level Sensitive

Negative edge triggered

High level Sensitive

Positive edge triggered

8

0

24

16

163

6120D–ATARM–02-Feb-06

24.8.3

AIC Source Vector Register

Register Name:

AIC_SVR0..AIC_SVR31

Access Type:

Reset Value:

Read/Write

0x0

31 30 29 28 27 26 25

VECTOR

23 22 21 20 19 18 17

VECTOR

15 14 13 12 11 10 9

VECTOR

7 6 5 4 3 2 1

VECTOR

• VECTOR: Source Vector

The user may store in these registers the addresses of the corresponding handler for each interrupt source.

8

0

24

16

24.8.4

AIC Interrupt Vector Register

Register Name: AIC_IVR

Access Type:

Reset Value:

Read-only

0

31 30 29 28 27 26 25 24

IRQV

23 22 21 20 19 18 17 16

IRQV

15 14 13 12 11 10 9 8

IRQV

7 6 5 4 3 2 1 0

IRQV

• IRQV: Interrupt Vector Register

The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt.

The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read.

When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU.

164

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AT91SAM7X256/128 Preliminary

24.8.5

AIC FIQ Vector Register

Register Name: AIC_FVR

Access Type:

Reset Value:

Read-only

0

31 30 29 28 27 26 25 24

FIQV

23 22 21 20 19 18 17 16

FIQV

15 14 13 12 11 10 9 8

FIQV

7 6 5 4 3 2 1 0

FIQV

• FIQV: FIQ Vector Register

The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the Fast Interrupt Vector Register reads the value stored in AIC_SPU.

24.8.6

AIC Interrupt Status Register

Register Name: AIC_ISR

Access Type:

Reset Value:

Read-only

0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

• IRQID: Current Interrupt Identifier

The Interrupt Status Register returns the current interrupt source number.

11

3

27

19

26

18

10

2

IRQID

9

1

25

17

8

0

24

16

165

6120D–ATARM–02-Feb-06

24.8.7

AIC Interrupt Pending Register

Register Name: AIC_IPR

Access Type:

Reset Value:

Read-only

0

31

PID31

23

PID23

15

PID15

7

PID7

30

PID30

22

PID22

14

PID14

6

PID6

29

PID29

21

PID21

13

PID13

5

PID5

• FIQ, SYS, PID2-PID31: Interrupt Pending

0 = Corresponding interrupt is not pending.

1 = Corresponding interrupt is pending.

28

PID28

20

PID20

12

PID12

4

PID4

24.8.8

AIC Interrupt Mask Register

Register Name: AIC_IMR

Access Type:

Reset Value:

Read-only

0

31

PID31

23

PID23

15

PID15

7

PID7

30

PID30

22

PID22

14

PID14

6

PID6

29

PID29

21

PID21

13

PID13

5

PID5

• FIQ, SYS, PID2-PID31: Interrupt Mask

0 = Corresponding interrupt is disabled.

1 = Corresponding interrupt is enabled.

28

PID28

20

PID20

12

PID12

4

PID4

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

25

PID25

17

PID17

9

PID9

1

SYS

24

PID24

16

PID16

8

PID8

0

FIQ

25

PID25

17

PID17

9

PID9

1

SYS

24

PID24

16

PID16

8

PID8

0

FIQ

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24.8.9

AIC Core Interrupt Status Register

Register Name: AIC_CISR

Access Type:

Reset Value:

Read-only

0

15

7

31

23

14

6

30

22

13

5

29

21

• NFIQ: NFIQ Status

0 = nFIQ line is deactivated.

1 = nFIQ line is active.

• NIRQ: NIRQ Status

0 = nIRQ line is deactivated.

1 = nIRQ line is active.

12

4

28

20

24.8.10

AIC Interrupt Enable Command Register

Register Name: AIC_IECR

Access Type: Write-only

31

PID31

23

PID23

15

PID15

7

PID7

30

PID30

22

PID22

14

PID14

6

PID6

29

PID29

21

PID21

13

PID13

5

PID5

28

PID28

20

PID20

12

PID12

4

PID4

• FIQ, SYS, PID2-PID3: Interrupt Enable

0 = No effect.

1 = Enables corresponding interrupt.

AT91SAM7X256/128 Preliminary

27

PID27

19

PID19

11

PID11

3

PID3

11

3

27

19

26

PID26

18

PID18

10

PID10

2

PID2

10

2

26

18

25

PID25

17

PID17

9

PID9

1

SYS

9

1

NIRQ

25

17

24

PID24

16

PID16

8

PID8

0

FIQ

8

0

NIFQ

24

16

167

6120D–ATARM–02-Feb-06

24.8.11

AIC Interrupt Disable Command Register

Register Name: AIC_IDCR

Access Type: Write-only

31

PID31

23

PID23

15

PID15

7

PID7

30

PID30

22

PID22

14

PID14

6

PID6

29

PID29

21

PID21

13

PID13

5

PID5

28

PID28

20

PID20

12

PID12

4

PID4

• FIQ, SYS, PID2-PID31: Interrupt Disable

0 = No effect.

1 = Disables corresponding interrupt.

24.8.12

AIC Interrupt Clear Command Register

Register Name: AIC_ICCR

Access Type: Write-only

31

PID31

23

PID23

15

PID15

7

PID7

30

PID30

22

PID22

14

PID14

6

PID6

29

PID29

21

PID21

13

PID13

5

PID5

28

PID28

20

PID20

12

PID12

4

PID4

• FIQ, SYS, PID2-PID31: Interrupt Clear

0 = No effect.

1 = Clears corresponding interrupt.

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

25

PID25

17

PID17

9

PID9

1

SYS

24

PID24

16

PID16

8

PID8

0

FIQ

25

PID25

17

PID17

9

PID9

1

SYS

24

PID24

16

PID16

8

PID8

0

FIQ

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AT91SAM7X256/128 Preliminary

24.8.13

AIC Interrupt Set Command Register

Register Name: AIC_ISCR

Access Type: Write-only

31

PID31

23

PID23

15

PID15

7

PID7

30

PID30

22

PID22

14

PID14

6

PID6

29

PID29

21

PID21

13

PID13

5

PID5

28

PID28

20

PID20

12

PID12

4

PID4

• FIQ, SYS, PID2-PID31: Interrupt Set

0 = No effect.

1 = Sets corresponding interrupt.

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

25

PID25

17

PID17

9

PID9

1

SYS

24

PID24

16

PID16

8

PID8

0

FIQ

24.8.14

AIC End of Interrupt Command Register

Register Name: AIC_EOICR

Access Type: Write-only

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

10

2

26

18

1

9

25

17

0

8

24

16

The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.

Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment.

169

6120D–ATARM–02-Feb-06

24.8.15

AIC Spurious Interrupt Vector Register

Register Name: AIC_SPU

Access Type:

Reset Value:

Read/Write

0

31 30 29 28 27 26 25 24

SIQV

23 22 21 20 19 18 17 16

SIQV

15 14 13 12 11 10 9 8

SIQV

7 6 5 4 3 2 1 0

SIQV

• SIQV: Spurious Interrupt Vector Register

The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.

24.8.16

AIC Debug Control Register

Register Name: AIC_DEBUG

Access Type:

Reset Value:

Read/Write

0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

• PROT: Protection Mode

0 = The Protection Mode is disabled.

1 = The Protection Mode is enabled.

• GMSK: General Mask

0 = The nIRQ and nFIQ lines are normally controlled by the AIC.

1 = The nIRQ and nFIQ lines are tied to their inactive state.

11

3

27

19

10

2

26

18

25

17

9

1

GMSK

24

16

8

0

PROT

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AT91SAM7X256/128 Preliminary

24.8.17

AIC Fast Forcing Enable Register

Register Name: AIC_FFER

Access Type: Write-only

31

PID31

23

PID23

15

PID15

7

PID7

30

PID30

22

PID22

14

PID14

6

PID6

29

PID29

21

PID21

13

PID13

5

PID5

28

PID28

20

PID20

12

PID12

4

PID4

• SYS, PID2-PID31: Fast Forcing Enable

0 = No effect.

1 = Enables the fast forcing feature on the corresponding interrupt.

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

25

PID25

17

PID17

9

PID9

1

SYS

24

PID24

16

PID16

8

PID8

0

24.8.18

AIC Fast Forcing Disable Register

Register Name: AIC_FFDR

Access Type: Write-only

31

PID31

23

PID23

15

PID15

7

PID7

30

PID30

22

PID22

14

PID14

6

PID6

29

PID29

21

PID21

13

PID13

5

PID5

28

PID28

20

PID20

12

PID12

4

PID4

• SYS, PID2-PID31: Fast Forcing Disable

0 = No effect.

1 = Disables the Fast Forcing feature on the corresponding interrupt.

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

25

PID25

17

PID17

9

PID9

1

SYS

24

PID24

16

PID16

8

PID8

0

171

6120D–ATARM–02-Feb-06

24.8.19

AIC Fast Forcing Status Register

Register Name: AIC_FFSR

Access Type: Read-only

31

PID31

23

PID23

15

PID15

7

PID7

30

PID30

22

PID22

14

PID14

6

PID6

29

PID29

21

PID21

13

PID13

5

PID5

28

PID28

20

PID20

12

PID12

4

PID4

27

PID27

19

PID19

11

PID11

3

PID3

• SYS, PID2-PID31: Fast Forcing Status

0 = The Fast Forcing feature is disabled on the corresponding interrupt.

1 = The Fast Forcing feature is enabled on the corresponding interrupt.

26

PID26

18

PID18

10

PID10

2

PID2

25

PID25

17

PID17

9

PID9

1

SYS

24

PID24

16

PID16

8

PID8

0

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AT91SAM7X256/128 Preliminary

25. Clock Generator

25.1

Description

The Clock Generator is made up of 1 PLL, a Main Oscillator, and an RC Oscillator.

It provides the following clocks:

• SLCK, the Slow Clock, which is the only permanent clock within the system

• MAINCK is the output of the Main Oscillator

• PLLCK is the output of the Divider and PLL block

The Clock Generator User Interface is embedded within the Power Management Controller one and is described in

Section 26.9

. However, the Clock Generator registers are named

CKGR_.

25.2

Slow Clock RC Oscillator

The slow clock is the output of the RC Oscillator and is the only clock considered permanent in a system that includes the Power Management Controller. It is mandatory in the operations of the PMC.

The user has to take the possible drifts of the RC Oscillator into account. More details are given in the DC Characteristics section of the product datasheet.

25.3

Main Oscillator

Figure 25-1 shows the Main Oscillator block diagram.

Figure 25-1. Main Oscillator BlockD iagram

MOSCEN

XIN

XOUT

Main

Oscillator

MAINCK

Main Clock

SLCK

Slow Clock

OSCOUNT

Main

Oscillator

Counter

Main Clock

Frequency

Counter

MOSCS

MAINF

MAINRDY

25.3.1

Main Oscillator Connections

The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in

Figure 25-2 . The 1 k

resistor is only required for crystals with frequencies lower than 8 MHz. The oscillator contains 25 pF capacitors on each XIN and XOUT pin. Consequently, CL1 and CL2 can be removed when a

173

6120D–ATARM–02-Feb-06

crystal with a load capacitance of 12.5 pF is used. For further details on the electrical characteristics of the Main Oscillator, see the DC Characteristics section of the product datasheet.

Figure 25-2. Typical Crystal Connection

XIN XOUT GND

1K

C

L1

C

L2

25.3.2

25.3.3

25.3.4

Main Oscillator Startup Time

The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the frequency rises.

Main Oscillator Control

To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected.

The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR).

When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is automatically cleared, indicating the main clock is off.

When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main oscillator.

When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscillator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8 from the OSCOUNT value. Since the

OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms.

When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor.

Main Clock Frequency Counter

The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency connected to the Main Oscillator. Generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application.

The Main Clock frequency counter starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the

MOSCS bit is set. Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in

CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock

174

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AT91SAM7X256/128 Preliminary

25.3.5

cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the

Main Oscillator can be determined.

Main Oscillator Bypass

The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly.

25.4

Divider and PLL Block

The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLL minimum input frequency when programming the divider.

Figure 25-3 shows the block diagram of the divider and PLL block.

Figure 25-3. Divider and PLL Block Diagram

DIV MUL OUT

Divider

MAINCK

PLL PLLCK

SLCK

PLLRC

PLLCOUNT

PLL

Counter

LOCK

25.4.1

PLL Filter

The PLL requires connection to an external second-order filter through the PLLRC pin.

Figure

25-4 shows a schematic of these filters.

Figure 25-4. PLL Capacitors and Resistors

PLLRC

PLL

R

C2

C1

GND

Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time.

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25.4.2

Divider and Phase Lock Loop Programming

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.

The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV and MUL.

The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.

Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in

PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_PLLR are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow

Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter.

The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel.

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26. Power Management Controller (PMC)

26.1

Description

The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor.

The Power Management Controller provides the following clocks:

• MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the AIC and the Memory Controller.

• Processor Clock (PCK), switched off when entering processor in idle mode.

• Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC,

SPI, TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet.

• UDP Clock (UDPCK), required by USB Device Port operations.

• Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins.

26.2

Master Clock Controller

The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller.

The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLL.

The Master Clock Controller is made up of a clock selector and a prescaler.

The Master Clock selection is made by writing the CSS field (Clock Source Selection) in

PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler.

Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in

PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a highspeed clock to a lower one to inform the software when the change is actually done.

Figure 26-1. Master Clock Controller

PMC_MCKR

CSS

SLCK

MAINCK

PLLCK

PMC_MCKR

PRES

Master Clock

Prescaler

MCK

To the Processor

Clock Controller (PCK)

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26.3

Processor Clock Controller

The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle

Mode. The Processor Clock can be enabled and disabled by writing the System Clock Enable

(PMC_SCER) and System Clock Disable Registers (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR).

The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product.

When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus.

26.4

USB Clock Controller

The USB Source Clock is the PLL output. If using the USB, the user must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in CKGR_PLLR.

When the PLL output is stable, i.e., the LOCK bit is set:

• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR.

The UDP bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48 MHz signal and the Master Clock. The Master Clock may be controlled via the

Peripheral Clock Controller.

Figure 26-2. USB Clock Controller

USBDIV

USB

Source

Clock

Divider

/1,/2,/4

UDP

UDP Clock (UDPCK)

26.5

Peripheral Clock Controller

The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock Controller. The user can individually enable and disable the Master Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and

Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR).

When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset.

In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.

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AT91SAM7X256/128 Preliminary

The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and

PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral.

26.6

Programmable Clock Output Controller

The PMC controls 4 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers.

PCKx can be independently selected between the Slow clock, the PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.

Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of

PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register).

Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers.

As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed.

26.7

Programming Sequence

1.

Enabling the Main Oscillator:

The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the CKGR_MOR register.

Once this register has been correctly configured, the user must wait for MOSCS field in the

PMC_SR register to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register.

Code Example: write_register(CKGR_MOR,0x00000701)

Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles.

So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.

2.

Checking the Main Oscillator Frequency (Optional):

In some situations the user may need an accurate measure of the main oscillator frequency. This measure can be accomplished via the CKGR_MCFR register.

Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow clock cycles.

179

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

3.

Setting PLL and divider:

All parameters needed to configure PLL and the divider are located in the CKGR_PLLR register.

The DIV field is used to control divider itself. A value between 0 and 255 can be programmed. Divider output is divider input divided by DIV parameter. By default DIV parameter is set to 0 which means that divider is turned off.

The OUT field is used to select the PLL B output frequency range.

The MUL field is the PLL multiplier factor. This parameter can be programmed between 0 and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is

PLL input frequency multiplied by (MUL + 1).

The PLLCOUNT field specifies the number of slow clock cycles before LOCK bit is set in the PMC_SR register after CKGR_PLLR register has been written.

Once the PMC_PLL register has been written, the user must wait for the LOCK bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCK has been enabled in the

PMC_IER register. All parameters in CKGR_PLLR can be programmed in a single write operation. If at some stage one of the following parameters, MUL, DIV is modified, LOCK bit will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is constrained to wait for LOCK bit to be set before using the PLL output clock.

The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the

USB clock(s).

Code Example: write_register(CKGR_PLLR,0x00040805)

If PLL and divider are enabled, the PLL input clock is the main clock. PLL output clock is

PLL input clock multiplied by 5. Once CKGR_PLLR has been written, LOCK bit will be set after eight slow clock cycles.

4.

Selection of Master Clock and Processor Clock

The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.

The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow clock.

The PRES field is used to control the Master Clock prescaler. The user can choose between different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES parameter is set to 1 which means that master clock is equal to slow clock.

Once PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register.

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

All parameters in PMC_MCKR can be programmed in a single write operation. If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks.

Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in

CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again,

LOCK goes high and MCKRDY is set.

While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see

Section 26.8.2

.

”Clock Switching Waveforms” on page 183

.

Code Example: write_register(PMC_MCKR,0x00000011)

The Master Clock is main clock divided by 16.

The Processor Clock is the Master Clock.

5.

Selection of Programmable clocks

Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and

PMC_SCSR.

Programmable clocks can be enabled and/or disabled via the PMC_SCER and

PMC_SCDR registers. Depending on the system used, 4 programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled.

PMC_PCKx registers are used to configure Programmable clocks.

The CSS field is used to select the programmable clock divider source. Four clock options are available: main clock, slow clock, PLLCK. By default, the clock source selected is slow clock.

The PRES field is used to control the Programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES parameter is set to 1 which means that master clock is equal to slow clock.

Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write operation.

If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set.

Code Example:

181

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AT91SAM7X256/128 Preliminary

write_register(PMC_PCK0,0x00000015)

Programmable clock 0 is main clock divided by 32.

6.

Enabling Peripheral Clocks

Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER and PMC_PCDR.

Depending on the system used, 15 peripheral clocks can be enabled or disabled. The

PMC_PCSR provides a clear view as to which peripheral clock is enabled.

Note: Each enabled peripheral clock corresponds to Master Clock.

Code Examples: write_register(PMC_PCER,0x00000110)

Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010)

Peripheral clock 4 is disabled.

182

AT91SAM7X256/128 Preliminary

26.8

Clock Switching Details

26.8.1

Master Clock Switching Timings

Table 26-1

gives the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added.

Table 26-1.

Clock Switching Timings (Worst Case)

From Main Clock SLCK

To

PLL Clock

Main Clock

SLCK

4 x SLCK +

2.5 x Main Clock

3 x PLL Clock +

4 x SLCK +

1 x Main Clock

3 x PLL Clock +

5 x SLCK

PLL Clock

0.5 x Main Clock +

4.5 x SLCK

0.5 x Main Clock +

4 x SLCK +

PLLCOUNT x SLCK +

2.5 x PLLx Clock

2.5 x PLL Clock +

5 x SLCK +

PLLCOUNT x SLCK

2.5 x PLL Clock +

4 x SLCK +

PLLCOUNT x SLCK

26.8.2

Clock Switching Waveforms

Figure 26-3. Switch Master Clock from Slow Clock to PLL Clock

Slow Clock

PLL Clock

LOCK

MCKRDY

Master Clock

Write PMC_MCKR

183

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

Figure 26-4. Switch Master Clock from Main Clock to Slow Clock

Slow Clock

Main Clock

MCKRDY

Master Clock

Write PMC_MCKR

Figure 26-5. Change PLL Programming

Main Clock

PLL Clock

LOCK

MCKRDY

Master Clock

Write CKGR_PLLR

Main Clock

184

6120D–ATARM–02-Feb-06

Figure 26-6. Programmable Clock Output Programming

PLL Clock

AT91SAM7X256/128 Preliminary

PCKRDY

PCKx Output

Write PMC_PCKx

Write PMC_SCER

PLL Clock is selected

PCKx is enabled

Write PMC_SCDR

PCKx is disabled

185

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26.9

Power Management Controller (PMC) User Interface

Table 26-2.

Register Mapping

Offset Register

0x0020

0x0024

0x0028

0x002C

0x0030

0x0034

0x0038

0x003C

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0040

0x0044

...

0x0060

0x0064

0x0068

System Clock Enable Register

System Clock Disable Register

System Clock Status Register

Reserved

Peripheral Clock Enable Register

Peripheral Clock Disable Register

Peripheral Clock Status Register

Reserved

Main Oscillator Register

Main Clock Frequency Register

Reserved

PLL Register

Master Clock Register

Application Clock Register

Reserved

Reserved

Programmable Clock 0 Register

Programmable Clock 1 Register

...

Interrupt Enable Register

Interrupt Disable Register

Status Register

Name

PMC_SCER

PMC_SCDR

PMC _SCSR

PMC _PCER

PMC_PCDR

PMC_PCSR

CKGR_MOR

CKGR_MCFR

CKGR_PLLR

PMC_MCKR

PMC_ACKR

PMC_PCK0

PMC_PCK1

...

PMC_IER

PMC_IDR

PMC_SR

...

Access

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Read/Write

Read-only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Write-only

Write-only

Read-only

...

Reset Value

0x01

0x0

0x0

0x0

0x3F00

0x0

0x0

0x0

0x0

--

--

0x08

0x006C Interrupt Mask Register

0x0070 - 0x00FC Reserved

PMC_IMR

Read-only

0x0

186

6120D–ATARM–02-Feb-06

26.9.1

PMC System Clock Enable Register

Register Name:

Access Type:

PMC_SCER

Write-only

31

30

29

23

15

7

UDP

22

14

6

21

13

5

• PCK: Processor Clock Enable

0 = No effect.

1 = Enables the Processor clock.

• UDP: USB Device Port Clock Enable

0 = No effect.

1 = Enables the 48 MHz clock of the USB Device Port.

• PCKx: Programmable Clock x Output Enable

0 = No effect.

1 = Enables the corresponding Programmable Clock output.

28

20

12

4

AT91SAM7X256/128 Preliminary

27

19

11

PCK3

3

26

18

10

PCK2

2

25

17

9

PCK1

1

24

16

8

PCK0

0

PCK

187

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

26.9.2

PMC System Clock Disable Register

Register Name:

Access Type:

PMC_SCDR

Write-only

31

23

15

7

UDP

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

PCK3

3

• PCK: Processor Clock Disable

0 = No effect.

1 = Disables the Processor clock. This is used to enter teh processor in Idle Mode.

• UDP: USB Device Port Clock Disable

0 = No effect.

1 = Disables the 48 MHz clock of the USB Device Port.

• PCKx: Programmable Clock x Output Disable

0 = No effect.

1 = Disables the corresponding Programmable Clock output.

26

18

10

PCK2

2

25

17

9

PCK1

1

24

16

8

PCK0

0

PCK

188

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

26.9.3

PMC System Clock Status Register

Register Name:

Access Type:

PMC_SCSR

Read-only

31

30

29

23

15

7

UDP

22

14

6

21

13

5

28

20

12

4

• PCK: Processor Clock Status

0 = The Processor clock is disabled.

1 = The Processor clock is enabled.

• UDP: USB Device Port Clock Status

0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled.

1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled.

• PCKx: Programmable Clock x Output Status

0 = The corresponding Programmable Clock output is disabled.

1 = The corresponding Programmable Clock output is enabled.

27

19

11

PCK3

3

26

18

10

PCK2

2

25

17

9

PCK1

1

24

16

8

PCK0

0

PCK

189

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AT91SAM7X256/128 Preliminary

26.9.4

PMC Peripheral Clock Enable Register

Register Name:

Access Type:

PMC_PCER

Write-only

31

PID31

30

PID30

29

PID29

28

PID28

23

PID23

15

PID15

7

PID7

22

PID22

14

PID14

6

PID6

21

PID21

13

PID13

5

PID5

20

PID20

12

PID12

4

PID4

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

25

PID25

17

PID17

9

PID9

1

-

• PIDx: Peripheral Clock x Enable

0 = No effect.

1 = Enables the corresponding peripheral clock.

Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.

24

PID24

16

PID16

8

PID8

0

-

26.9.5

PMC Peripheral Clock Disable Register

Register Name:

Access Type:

PMC_PCDR

Write-only

31

PID31

30

PID30

29

PID29

28

PID28

23

PID23

15

PID15

7

PID7

22

PID22

14

PID14

6

PID6

21

PID21

13

PID13

5

PID5

20

PID20

12

PID12

4

PID4

• PIDx: Peripheral Clock x Disable

0 = No effect.

1 = Disables the corresponding peripheral clock.

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

25

PID25

17

PID17

9

PID9

1

-

24

PID24

16

PID16

8

PID8

0

-

190

6120D–ATARM–02-Feb-06

26.9.6

PMC Peripheral Clock Status Register

Register Name:

Access Type:

PMC_PCSR

Read-only

31

PID31

30

PID30

29

PID29

28

PID28

23

PID23

15

PID15

7

PID7

22

PID22

14

PID14

6

PID6

21

PID21

13

PID13

5

PID5

20

PID20

12

PID12

4

PID4

• PIDx: Peripheral Clock x Status

0 = The corresponding peripheral clock is disabled.

1 = The corresponding peripheral clock is enabled.

AT91SAM7X256/128 Preliminary

27

PID27

19

PID19

11

PID11

3

PID3

26

PID26

18

PID18

10

PID10

2

PID2

25

PID25

17

PID17

9

PID9

1

24

PID24

16

PID16

8

PID8

0

6120D–ATARM–02-Feb-06

191

AT91SAM7X256/128 Preliminary

26.9.7

PMC Clock Generator Main Oscillator Register

Register Name:

Access Type:

CKGR_MOR

Read/Write

31

23

15

30

22

14

29

21

13

28

20

12

OSCOUNT

11

27

19

26

18

10

25

17

9

7

6

5

4

3

2

1

OSCBYPASS

• MOSCEN: Main Oscillator Enable

A crystal must be connected between XIN and XOUT.

0 = The Main Oscillator is disabled.

1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0.

When MOSCEN is set, the MOSCS flag is set once the Main Oscillator startup time is achieved.

• OSCBYPASS: Oscillator Bypass

0 = No effect.

1 = The Main Oscillator is bypassed . MOSCEN must be set to 0. An external clock must be connected on XIN.

When OSCBYPASS is set, the MOSCS flag in PMC_SR is automatically set.

Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag.

• OSCOUNT: Main Oscillator Start-up Time

Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time.

0

MOSCEN

24

16

8

192

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

26.9.8

PMC Clock Generator Main Clock Frequency Register

Register Name:

Access Type:

CKGR_MCFR

Read-only

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

MAINF

7 6 5 4 3

MAINF

• MAINF: Main Clock Frequency

Gives the number of Main Clock cycles within 16 Slow Clock periods.

• MAINRDY: Main Clock Ready

0 = MAINF value is not valid or the Main Oscillator is disabled.

1 = The Main Oscillator has been enabled previously and MAINF value is available.

2

26

18

10

25

17

9

1

24

16

MAINRDY

8

0

193

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

26.9.9

PMC Clock Generator PLL Register

Register Name:

Access Type:

CKGR_PLLR

Read/Write

31

30

29

USBDIV

28

23 22 21 20

27

19

26

18

25

MUL

17

MUL

15

OUT

14 13 12 11

PLLCOUNT

10 9

7 6 5 4 3 2 1

DIV

Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.

• DIV: Divider

DIV

0

1

2 - 255

Divider Selected

Divider output is 0

Divider is bypassed

Divider output is the selected clock divided by DIV.

• PLLCOUNT: PLL Counter

Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.

• OUT: PLL Clock Frequency Range

1

1

0

0

OUT

0

1

0

1

PLL Clock Frequency Range

Refer to the DC Characteristics section of the product datasheet

Reserved

Refer to the DC Characteristics section of the product datasheet

Reserved

• MUL: PLL Multiplier

0 = The PLL is deactivated.

1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1.

• USBDIV: Divider for USB Clock

USBDIV

0

0

1

1

0

1

0

1

Divider for USB Clock(s)

Divider output is PLL clock output.

Divider output is PLL clock output divided by 2.

Divider output is PLL clock output divided by 4.

Reserved.

24

16

8

0

194

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

26.9.10

PMC Master Clock Register

Register Name:

Access Type:

PMC_MCKR

Read/Write

31

30

29

23

15

7

22

14

6

21

13

5

• CSS: Master Clock Selection

CSS

1

1

0

0

• PRES: Master Clock Prescaler

1

1

0

1

1

0

0

0

0

1

1

0

1

PRES

0

0

1

28

20

12

4

0

1

0

1

27

19

11

3

PRES

1

0

1

0

1

0

1

0

26

18

10

2

25

17

9

1

CSS

0

24

16

8

Clock Source Selection

Slow Clock is selected

Main Clock is selected

Reserved

PLL Clock is selected.

Master Clock

Selected clock

Selected clock divided by 2

Selected clock divided by 4

Selected clock divided by 8

Selected clock divided by 16

Selected clock divided by 32

Selected clock divided by 64

Reserved

195

6120D–ATARM–02-Feb-06

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26.9.11

PMC Programmable Clock Register

Register Name:

Access Type:

PMC_PCKx

Read/Write

31

30

29

23

15

7

22

14

6

21

13

5

• CSS: Master Clock Selection

28

20

12

4

CSS

1

1

0

0

• PRES: Programmable Clock Prescaler

0

1

0

1

1

1

0

1

1

0

0

0

0

1

1

0

1

PRES

0

0

1

27

19

11

3

PRES

Clock Source Selection

Slow Clock is selected

Main Clock is selected

Reserved

PLL Clock is selected

1

0

1

0

1

0

1

0

26

18

10

2

25

17

9

1

CSS

24

16

8

0

Master Clock

Selected clock

Selected clock divided by 2

Selected clock divided by 4

Selected clock divided by 8

Selected clock divided by 16

Selected clock divided by 32

Selected clock divided by 64

Reserved

196

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

26.9.12

PMC Interrupt Enable Register

Register Name:

Access Type:

PMC_IER

Write-only

31

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

• MOSCS: Main Oscillator Status Interrupt Enable

• LOCK: PLL Lock Interrupt Enable

• MCKRDY: Master Clock Ready Interrupt Enable

• PCKRDYx: Programmable Clock Ready x Interrupt Enable

0 = No effect.

1 = Enables the corresponding interrupt.

27

19

11

PCKRDY3

3

MCKRDY

26

18

10

PCKRDY2

2

LOCK

25

17

9

PCKRDY1

1

24

16

8

PCKRDY0

0

MOSCS

197

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

26.9.13

PMC Interrupt Disable Register

Register Name:

Access Type:

PMC_IDR

Write-only

31

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

• MOSCS: Main Oscillator Status Interrupt Disable

• LOCK: PLL Lock Interrupt Disable

• MCKRDY: Master Clock Ready Interrupt Disable

• PCKRDYx: Programmable Clock Ready x Interrupt Disable

0 = No effect.

1 = Disables the corresponding interrupt.

27

19

11

PCKRDY3

3

MCKRDY

26

18

10

PCKRDY2

2

LOCK

25

17

9

PCKRDY1

1

24

16

8

PCKRDY0

0

MOSCS

198

6120D–ATARM–02-Feb-06

26.9.14

PMC Status Register

Register Name:

Access Type:

PMC_SR

Read-only

31

30

23

15

7

22

14

6

29

21

13

5

• MOSCS: MOSCS Flag Status

0 = Main oscillator is not stabilized.

1 = Main oscillator is stabilized.

• LOCK: PLL Lock Status

0 = PLL is not locked

1 = PLL is locked.

• MCKRDY: Master Clock Status

0 = Master Clock is not ready.

1 = Master Clock is ready.

• PCKRDYx: Programmable Clock Ready Status

0 = Programmable Clock x is not ready.

1 = Programmable Clock x is ready.

28

20

12

4

AT91SAM7X256/128 Preliminary

27

19

11

PCKRDY3

3

MCKRDY

26

18

10

PCKRDY2

2

LOCK

25

17

9

PCKRDY1

1

24

16

8

PCKRDY0

0

MOSCS

199

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

26.9.15

PMC Interrupt Mask Register

Register Name:

Access Type:

PMC_IMR

Read-only

31

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

• MOSCS: Main Oscillator Status Interrupt Mask

• LOCK: PLL Lock Interrupt Mask

• MCKRDY: Master Clock Ready Interrupt Mask

• PCKRDYx: Programmable Clock Ready x Interrupt Mask

0 = The corresponding interrupt is enabled.

1 = The corresponding interrupt is disabled.

27

19

11

PCKRDY3

3

MCKRDY

26

18

10

PCKRDY2

2

LOCK

25

17

9

PCKRDY1

1

24

16

8

PCKRDY0

0

MOSCS

200

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

27. Debug Unit (DBGU)

27.1

Overview

The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems.

The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. Moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum.

The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the

In-circuit Emulator of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control.

Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals.

Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via the In-circuit Emulator. This permits protection of the code, stored in ROM.

201

6120D–ATARM–02-Feb-06

27.2

Block Diagram

Figure 27-1. Debug Unit Functional Block Diagram

Peripheral

Bridge

Peripheral DMA Controller

APB

Debug Unit

Transmit

Power

Management

Controller

MCK

Baud Rate

Generator

Receive

Parallel

Input/

Output ice_nreset

ARM

Processor nTRST

COMMRX

COMMTX

DCC

Handler

ICE

Access

Handler force_ntrst

Chip ID

Interrupt

Control dbgu_irq

Table 27-1.

Debug Unit Pin Description

Pin Name

DRXD

Description

Debug Receive Data

DTXD Debug Transmit Data

Type

Input

Output

Figure 27-2. Debug Unit Application Example

Boot Program Debug Monitor Trace Manager

Debug Unit

Programming Tool

RS232 Drivers

Debug Console Trace Console

DTXD

DRXD

202

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27.3

Product Dependencies

27.3.1

I/O Lines

Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.

27.3.2

27.3.3

Power Management

Depending on product integration, the Debug Unit clock may be controllable through the Power

Management Controller. In this case, the programmer must first configure the PMC to enable the

Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.

Interrupt Source

Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer

interrupt lines and other system peripheral interrupts, as shown in Figure 27-1

. This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered.

203

6120D–ATARM–02-Feb-06

27.4

UART Operations

The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with parity). It has no clock pin.

The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART.

27.4.1

Baud Rate Generator

The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter.

The baud rate clock is the master clock divided by 16 times the value (CD) written in

DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is

Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x

65536).

Baud Rate

= ----------------------

16

×

CD

Figure 27-3. Baud Rate Generator

CD

MCK

CD

16-bit Counter

OUT

0

>1

1

0

Divide by 16

Baud Rate

Clock

Receiver

Sampling Clock

27.4.2

27.4.2.1

Receiver

Receiver Reset, Enable and Disable

After device reset, the Debug Unit receiver is disabled and must be enabled before being used.

The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.

The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation.

The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit

RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost.

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27.4.2.2

AT91SAM7X256/128 Preliminary

Start Detection and Data Sampling

The Debug Unit only supports asynchronous operations, and this affects only its receiver. The

Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is

7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.

When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected.

Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.

Figure 27-4. Start Bit Detection

Sampling Clock

DRXD

27.4.2.3

True Start

Detection

D0

Baud Rate

Clock

Figure 27-5. Character Reception

Example: 8-bit, parity enabled 1 stop

0.5 bit period

1 bit period

DRXD

Sampling D0 D1

True Start Detection

D2 D3 D4 D5 D6 D7

Parity Bit

Stop Bit

Receiver Ready

When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read.

Figure 27-6. Receiver Ready

DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P

S D0 D1 D2 D3 D4 D5 D6 D7 P

RXRDY

Read DBGU_RHR

205

6120D–ATARM–02-Feb-06

27.4.2.4

27.4.2.5

27.4.2.6

Receiver Overrun

If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in

DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1.

Figure 27-7. Receiver Overrun

DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop

S D0 D1 D2 D3 D4 D5 D6 D7 P stop

RXRDY

OVRE

RSTSTA

Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set.

The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA

(Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1.

Figure 27-8. Parity Error

DRXD

S D0 D1 D2 D3 D4 D5 D6 D7 P stop

RXRDY

PARE

Wrong Parity Bit

RSTSTA

Receiver Framing Error

When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1.

Figure 27-9. Receiver Framing Error

DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop

RXRDY

FRAME

Stop Bit

Detected at 0

RSTSTA

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27.4.3

27.4.3.1

Transmitter

Transmitter Reset, Enable and Disable

After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1.

From this command, the transmitter waits for a character to be written in the Transmit Holding

Register DBGU_THR before actually starting the transmission.

The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding

Register, the characters are completed before the transmitter is actually stopped.

The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters.

27.4.3.2

Transmit Format

The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register.

One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field

PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.

Figure 27-10. Character Transmission

Example: Parity enabled

Baud Rate

Clock

DTXD

27.4.3.3

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7 Parity

Bit

Stop

Bit

Transmitter Control

When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register

DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift

Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty.

When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in

DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed.

207

6120D–ATARM–02-Feb-06

Figure 27-11. Transmitter Control

DBGU_THR

Data 0

Shift Register

DTXD

S Data 0

Data 0

P stop

S

TXRDY

TXEMPTY

Data 1

Data 1

Data 1

P stop

Write Data 0 in DBGU_THR

Write Data 1 in DBGU_THR

27.4.4

27.4.5

Peripheral Data Controller

Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a

Peripheral Data Controller (PDC) channel.

The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug

Unit status register DBGU_SR and can generate an interrupt.

The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR.

Test Modes

The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR.

The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the

DTXD line.

The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state.

The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.

208

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Figure 27-12. Test Modes

Automatic Echo

Receiver RXD

Transmitter

Disabled

TXD

Local Loopback

Receiver

Transmitter

Remote Loopback

Receiver

V

DD

Disabled

Disabled

RXD

Disabled

V

DD

TXD

RXD

Transmitter

Disabled

TXD

27.4.6

Debug Communication Channel Support

The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.

The Debug Communication Channel contains two registers that are accessible through the ICE

Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side.

As a reminder, the following instructions are used to read and write the Debug Communication

Channel:

MRC p14, 0, Rd, c1, c0, 0

Returns the debug communication data read register into Rd

MCR p14, 0, Rd, c1, c0, 0

Writes the value in Rd to the debug communication data write register.

The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger.

209

6120D–ATARM–02-Feb-06

27.4.7

27.4.8

Chip Identifier

The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and

DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields:

• EXT - shows the use of the extension identifier register

• NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size

• ARCH - identifies the set of embedded peripheral

• SRAMSIZ - indicates the size of the embedded SRAM

• EPROC - indicates the embedded ARM processor

• VERSION - gives the revision of the silicon

The second register is device-dependent and reads 0 if the bit EXT is 0.

ICE Access Prevention

The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller.

On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access.

This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.

210

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27.5

Debug Unit User Interface

Table 27-2.

Debug Unit Memory Map

Offset Register

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

Control Register

Mode Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Status Register

Receive Holding Register

Transmit Holding Register

0x0020 Baud Rate Generator Register

0x0024 - 0x003C Reserved

0x0040

0x0044

Chip ID Register

Chip ID Extension Register

0x0048 Force NTRST Register

0x004C - 0x00FC Reserved

0x0100 - 0x0124 PDC Area

AT91SAM7X256/128 Preliminary

Name

DBGU_CR

DBGU_MR

DBGU_IER

DBGU_IDR

DBGU_IMR

DBGU_SR

DBGU_RHR

DBGU_THR

DBGU_BRGR

DBGU_CIDR

DBGU_EXID

DBGU_FNR

Write-only

Read/Write

Write-only

Write-only

Read-only

Read-only

Read-only

Write-only

Read/Write

Read-only

Read-only

Read/Write

0x0

0x0

0x0

0x0

0x0

211

6120D–ATARM–02-Feb-06

27.5.1

Name:

Debug Unit Control Register

Access Type:

DBGU_CR

Write-only

31

30

29

23

15

7

TXDIS

22

14

6

TXEN

21

13

5

RXDIS

28

20

12

4

RXEN

27

19

11

3

RSTTX

26

18

10

2

RSTRX

25

17

9

1

24

16

8

RSTSTA

0

• RSTRX: Reset Receiver

0 = No effect.

1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.

• RSTTX: Reset Transmitter

0 = No effect.

1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.

• RXEN: Receiver Enable

0 = No effect.

1 = The receiver is enabled if RXDIS is 0.

• RXDIS: Receiver Disable

0 = No effect.

1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped.

• TXEN: Transmitter Enable

0 = No effect.

1 = The transmitter is enabled if TXDIS is 0.

• TXDIS: Transmitter Disable

0 = No effect.

1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and

RSTTX is not set, both characters are completed before the transmitter is stopped.

• RSTSTA: Reset Status Bits

0 = No effect.

1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.

212

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27.5.2

Name:

Debug Unit Mode Register

Access Type:

DBGU_MR

Read/Write

31

30

29

23

15

22

14

7

CHMODE

6

21

13

5

• PAR: Parity Type

0

0

0

0

1

1

1 x

PAR

0

0

• CHMODE: Channel Mode

CHMODE

1

1

0

0

0

1

0

1

0

1

0

1 x

Mode Description

Normal Mode

Automatic Echo

Local Loopback

Remote Loopback

28

20

12

4

27

19

11

3

Parity Type

Even parity

Odd parity

Space: parity forced to 0

Mark: parity forced to 1

No parity

26

18

10

PAR

2

25

17

9

1

24

16

8

0

213

6120D–ATARM–02-Feb-06

27.5.3

Name:

Debug Unit Interrupt Enable Register

Access Type:

DBGU_IER

Write-only

31

COMMRX

30

COMMTX

29

28

23

15

7

PARE

22

14

6

FRAME

21

13

5

OVRE

20

12

RXBUFF

4

ENDTX

• RXRDY: Enable RXRDY Interrupt

• TXRDY: Enable TXRDY Interrupt

• ENDRX: Enable End of Receive Transfer Interrupt

• ENDTX: Enable End of Transmit Interrupt

• OVRE: Enable Overrun Error Interrupt

• FRAME: Enable Framing Error Interrupt

• PARE: Enable Parity Error Interrupt

• TXEMPTY: Enable TXEMPTY Interrupt

• TXBUFE: Enable Buffer Empty Interrupt

• RXBUFF: Enable Buffer Full Interrupt

• COMMTX: Enable COMMTX (from ARM) Interrupt

• COMMRX: Enable COMMRX (from ARM) Interrupt

0 = No effect.

1 = Enables the corresponding interrupt.

27

19

11

TXBUFE

3

ENDRX

26

18

10

2

25

17

9

TXEMPTY

1

TXRDY

24

16

8

0

RXRDY

214

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6120D–ATARM–02-Feb-06

27.5.4

Name:

Debug Unit Interrupt Disable Register

Access Type:

DBGU_IDR

Write-only

31

COMMRX

30

COMMTX

29

28

23

15

7

PARE

22

14

6

FRAME

21

13

5

OVRE

20

12

RXBUFF

4

ENDTX

• RXRDY: Disable RXRDY Interrupt

• TXRDY: Disable TXRDY Interrupt

• ENDRX: Disable End of Receive Transfer Interrupt

• ENDTX: Disable End of Transmit Interrupt

• OVRE: Disable Overrun Error Interrupt

• FRAME: Disable Framing Error Interrupt

• PARE: Disable Parity Error Interrupt

• TXEMPTY: Disable TXEMPTY Interrupt

• TXBUFE: Disable Buffer Empty Interrupt

• RXBUFF: Disable Buffer Full Interrupt

• COMMTX: Disable COMMTX (from ARM) Interrupt

• COMMRX: Disable COMMRX (from ARM) Interrupt

0 = No effect.

1 = Disables the corresponding interrupt.

AT91SAM7X256/128 Preliminary

27

19

11

TXBUFE

3

ENDRX

26

18

10

2

25

17

9

TXEMPTY

1

TXRDY

24

16

8

0

RXRDY

215

6120D–ATARM–02-Feb-06

27.5.5

Name:

Debug Unit Interrupt Mask Register

Access Type:

DBGU_IMR

Read-only

31

COMMRX

30

COMMTX

29

23

15

7

PARE

22

14

6

FRAME

21

13

5

OVRE

28

20

12

RXBUFF

4

ENDTX

• RXRDY: Mask RXRDY Interrupt

• TXRDY: Disable TXRDY Interrupt

• ENDRX: Mask End of Receive Transfer Interrupt

• ENDTX: Mask End of Transmit Interrupt

• OVRE: Mask Overrun Error Interrupt

• FRAME: Mask Framing Error Interrupt

• PARE: Mask Parity Error Interrupt

• TXEMPTY: Mask TXEMPTY Interrupt

• TXBUFE: Mask TXBUFE Interrupt

• RXBUFF: Mask RXBUFF Interrupt

• COMMTX: Mask COMMTX Interrupt

• COMMRX: Mask COMMRX Interrupt

0 = The corresponding interrupt is disabled.

1 = The corresponding interrupt is enabled.

27

19

11

TXBUFE

3

ENDRX

26

18

10

2

25

17

9

TXEMPTY

1

TXRDY

24

16

8

0

RXRDY

216

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AT91SAM7X256/128 Preliminary

27.5.6

Name:

Debug Unit Status Register

Access Type:

DBGU_SR

Read-only

31

COMMRX

30

COMMTX

29

23

15

7

PARE

22

14

6

FRAME

21

13

5

OVRE

28

20

12

RXBUFF

4

ENDTX

27

19

11

TXBUFE

3

ENDRX

26

18

10

2

25

17

9

TXEMPTY

1

TXRDY

24

16

8

0

RXRDY

• RXRDY: Receiver Ready

0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.

1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read.

• TXRDY: Transmitter Ready

0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled.

1 = There is no character written to DBGU_THR not yet transferred to the Shift Register.

• ENDRX: End of Receiver Transfer

0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive.

1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active.

• ENDTX: End of Transmitter Transfer

0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive.

1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active.

• OVRE: Overrun Error

0 = No overrun error has occurred since the last RSTSTA.

1 = At least one overrun error has occurred since the last RSTSTA.

• FRAME: Framing Error

0 = No framing error has occurred since the last RSTSTA.

1 = At least one framing error has occurred since the last RSTSTA.

• PARE: Parity Error

0 = No parity error has occurred since the last RSTSTA.

1 = At least one parity error has occurred since the last RSTSTA.

• TXEMPTY: Transmitter Empty

0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled.

1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter.

• TXBUFE: Transmission Buffer Empty

0 = The buffer empty signal from the transmitter PDC channel is inactive.

1 = The buffer empty signal from the transmitter PDC channel is active.

217

6120D–ATARM–02-Feb-06

• RXBUFF: Receive Buffer Full

0 = The buffer full signal from the receiver PDC channel is inactive.

1 = The buffer full signal from the receiver PDC channel is active.

• COMMTX: Debug Communication Channel Write Status

0 = COMMTX from the ARM processor is inactive.

1 = COMMTX from the ARM processor is active.

• COMMRX: Debug Communication Channel Read Status

0 = COMMRX from the ARM processor is inactive.

1 = COMMRX from the ARM processor is active.

218

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AT91SAM7X256/128 Preliminary

27.5.7

Name:

Debug Unit Receiver Holding Register

Access Type:

DBGU_RHR

Read-only

31

30

29

28

23

15

7

22

14

6

21

13

5

20

12

4

RXCHR

27

19

11

3

• RXCHR: Received Character

Last received character if RXRDY is set.

26

18

10

2

25

17

9

1

24

16

8

0

27.5.8

Name:

Debug Unit Transmit Holding Register

Access Type:

DBGU_THR

Write-only

31

23

30

22

29

21

28

20

15

7

14

6

13

5

12

4

11

3

27

19

TXCHR

• TXCHR: Character to be Transmitted

Next character to be transmitted after the current character if TXRDY is not set.

10

2

26

18

9

1

25

17

8

0

24

16

219

6120D–ATARM–02-Feb-06

27.5.9

Name:

Debug Unit Baud Rate Generator Register

Access Type:

DBGU_BRGR

Read/Write

31

30

29

28

23

15

22

14

21

13

20

12

7 6 5 4

CD

CD

• CD: Clock Divisor

CD

0

1

2 to 65535

Baud Rate Clock

Disabled

MCK

MCK / (CD x 16)

27

19

11

3

26

18

10

2

25

17

9

1

24

16

8

0

220

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AT91SAM7X256/128 Preliminary

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

27.5.10

Debug Unit Chip ID Register

Name:

DBGU_CIDR

Access Type:

Read-only

30 31

EXT

23 22

29

NVPTYP

21

ARCH

15 14 13

NVPSIZ2

7 6

EPROC

5

• VERSION: Version of the Device

• EPROC: Embedded Processor

28

20

12

4

0

0

1

1

EPROC

0

1

0

0

1

0

0

1

• NVPSIZ: Nonvolatile Program Memory Size

Processor

ARM946E-S

ARM7TDMI

ARM920T

ARM926EJ-S

NVPSIZ

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

27

19

11

3

Size

None

8K bytes

16K bytes

32K bytes

Reserved

64K bytes

Reserved

128K bytes

Reserved

256K bytes

512K bytes

Reserved

1024K bytes

Reserved

2048K bytes

Reserved

26

ARCH

18

SRAMSIZ

10

2

VERSION

NVPSIZ

25

17

9

1

24

16

8

0

221

6120D–ATARM–02-Feb-06

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

• NVPSIZ2 Second Nonvolatile Program Memory Size

NVPSIZ2

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

• SRAMSIZ: Internal SRAM Size

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

SRAMSIZ

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

1

0

1

1

0

0

1

0

1

1

0

1

0

0

0

0

1

1

0

1

0

1

1

0

0

1

1

0

0

0

1

1

0

1

0

1

1

0

1

0

1

0

1

0

0

1

0

Size

Reserved

1K bytes

2K bytes

Reserved

112K bytes

4K bytes

80K bytes

160K bytes

8K bytes

16K bytes

32K bytes

64K bytes

128K bytes

256K bytes

96K bytes

512K bytes

222

AT91SAM7X256/128 Preliminary

Size

None

8K bytes

16K bytes

32K bytes

Reserved

64K bytes

Reserved

128K bytes

Reserved

256K bytes

512K bytes

Reserved

1024K bytes

Reserved

2048K bytes

Reserved

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

• ARCH: Architecture Identifier

ARCH

0x60

0x70

0x71

0x72

0x73

0x75

0x19

Hex

0xF0

0x40

0x63

0x55

0x42

0x92

0x34

Bin

1111 0001

0100 0000

0110 0011

0101 0101

0100 0010

1001 0010

0011 0100

0101 0000

0111 0000

0111 0001

0111 0010

0111 0011

0111 0101

0001 1001

• NVPTYP: Nonvolatile Program Memory Type

Architecture

AT75Cxx Series

AT91x40 Series

AT91x63 Series

AT91x55 Series

AT91x42 Series

AT91x92 Series

AT91x34 Series

AT91SAM7Axx Series

AT91SAM7Sxx Series

AT91SAM7XCxx Series

AT91SAM7SExx Series

AT91SAM7Lxx Series

AT91SAM7Xxx Series

AT91SAM9xx Series

1

0

0

0

0

NVPTYP

0

0

0

1

1

0

0

0

1

1

Memory

ROM

ROMless or on-chip Flash

SRAM emulating ROM

Embedded Flash Memory

ROM and Embedded Flash Memory

NVPSIZ is ROM size

NVPSIZ2 is Flash size

• EXT: Extension Flag

0 = Chip ID has a single register definition without extension

1 = An extended Chip ID exists.

223

6120D–ATARM–02-Feb-06

27.5.11

Debug Unit Chip ID Extension Register

Name:

DBGU_EXID

Access Type:

Read-only

31 30 29 28

23

15

7

22

14

6

21

13

5

20

12

4

EXID

27

19

EXID

11

EXID

3

EXID

• EXID: Chip ID Extension

Reads 0 if the bit EXT in DBGU_CIDR is 0.

27.5.12

Debug Unit Force NTRST Register

Name:

DBGU_FNR

Access T ype:

Read/Write

31

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

27

19

11

3

• FNTRST: Force NTRST

0 = NTRST of the ARM processor’s TAP controller is driven by the ice_nreset signal.

1 = NTRST of the ARM processor’s TAP controller is held low.

26

18

10

2

10

2

26

18

9

1

25

17

25

17

9

1

24

16

8

0

FNTRST

8

0

24

16

224

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

28. Parallel Input/Output Controller (PIO)

28.1

Overview

The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product.

Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User

Interface.

Each I/O line of the PIO Controller features:

• An input change interrupt enabling level change detection on any I/O line.

• A glitch filter providing rejection of pulses lower than one-half of clock cycle.

• Multi-drive capability similar to an open drain I/O line.

• Control of the the pull-up of the I/O line.

• Input visibility and output control.

The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.

225

6120D–ATARM–02-Feb-06

28.2

Block Diagram

Figure 28-1. Block Diagram

PIO Interrupt

PIO Controller

AIC

PIO Clock

PMC

Data, Enable

Embedded

Peripheral

Data, Enable

Up to 32 peripheral IOs

Up to 32 peripheral IOs

Embedded

Peripheral

APB

28.3

Application Block Diagram

Figure 28-2. Application Block Diagram

Keyboard Driver Control & Command

Driver

Keyboard Driver

PIO Controller

General Purpose I/Os

On-Chip Peripheral Drivers

On-Chip Peripherals

External Devices

PIN 0

PIN 1

Up to 32 pins

PIN 31

226

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

28.4

Product Dependencies

28.4.1

Pin Multiplexing

Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.

28.4.2

28.4.3

28.4.4

External Interrupt Lines

The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO

Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the

PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs.

Power Management

The Power Management Controller controls the PIO Controller clock in order to save power.

Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled.

However, when the clock is disabled, not all of the features of the PIO Controller are available.

Note that the Input Change Interrupt and the read of the pin level require the clock to be validated.

After a hardware reset, the PIO clock is disabled by default.

The user must configure the Power Management Controller before any access to the input line information.

Interrupt Generation

For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the

PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers.

The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.

227

6120D–ATARM–02-Feb-06

28.5

Functional Description

The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in

Figure 28-3 . In this description each signal shown

represents but one of up to 32 possible indexes.

Figure 28-3. I/O Line Control Logic

PIO_OER[0]

PIO_OSR[0]

PIO_ODR[0]

PIO_PUER[0]

PIO_PUSR[0]

PIO_PUDR[0]

1

Peripheral A

Output Enable 0

Peripheral B

Output Enable

PIO_ASR[0]

PIO_ABSR[0]

PIO_BSR[0]

Peripheral A

Output

1

0

Peripheral B

Output

1

PIO_PER[0]

PIO_PSR[0]

PIO_PDR[0]

PIO_SODR[0]

PIO_ODSR[0]

PIO_CODR[0]

0

0

1

PIO_MDER[0]

PIO_MDSR[0]

PIO_MDDR[0]

0

1

1

0

Pad

Glitch

Filter

PIO_IFER[0]

PIO_IFSR[0]

PIO_IFDR[0]

1

PIO_PDSR[0]

0

Edge

Detector

PIO_IER[0]

PIO_ISR[0]

PIO_IMR[0]

PIO_IDR[0]

PIO_ISR[31]

PIO_IER[31]

PIO_IMR[31]

PIO_IDR[31]

Peripheral A

Input

Peripheral B

Input

(Up to 32 possible inputs)

PIO Interrupt

228

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

28.5.1

28.5.2

28.5.3

28.5.4

Pull-up Resistor Control

Each I/O line is designed with an embedded pull-up resistor. The value of this resistor is about

10 k

(see the product electrical characteristics for more details about this value). The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.

Control of the pull-up resistor is possible regardless of the configuration of the I/O line.

After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.

I/O Line or Peripheral Function Selection

When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of

0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the

PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller.

If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral),

PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit.

After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.

Peripheral A or B Selection

The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected.

For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected.

Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input.

After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A.

However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.

Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR.

Output Control

When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at

0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not.

229

6120D–ATARM–02-Feb-06

28.5.5

28.5.6

28.5.7

When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register).

The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at

1, the corresponding I/O line is driven by the PIO controller.

The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data

Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller.

Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line.

Synchronous Data Output

Controlling all parallel busses using several PIOs requires two successive write operations in the

PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output

Data Status Register). Only bits unmasked by PIO_OSWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable

Register) and cleared by writing to PIO_OWDR (Output Write Disable Register).

After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at

0x0.

Multi Drive Control (Open Drain)

Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line.

The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and

PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver

Status Register) indicates the pins that are configured to support external drivers.

After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.

Output Line Timings

Figure 28-4

shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set.

Figure 28-4 also shows when the feedback in PIO_PDSR is available.

230

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

Figure 28-4. Output Line Timings

MCK

Write PIO_SODR

Write PIO_ODSR at 1

Write PIO_CODR

Write PIO_ODSR at 0

PIO_ODSR

APB Access

2 cycles

PIO_PDSR

APB Access

2 cycles

28.5.8

28.5.9

Inputs

The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.

Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise

PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.

Input Glitch Filtering

Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in

Figure 28-5

.

The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register),

PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing

PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.

When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals.

It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled.

231

6120D–ATARM–02-Feb-06

Figure 28-5. Input Glitch Filter Timing

MCK up to 1.5 cycles

Pin Level

PIO_PDSR if PIO_IFSR = 0

PIO_PDSR if PIO_IFSR = 1

1 cycle 1 cycle 1 cycle

2 cycles up to 2.5 cycles

1 cycle

1 cycle up to 2 cycles

28.5.10

Input Change Interrupt

The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable

Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask

Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function.

When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt

Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller.

When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled.

Figure 28-6. Input Change Interrupt Timings

MCK

Pin Level

PIO_ISR

Read PIO_ISR APB Access

APB Access

232

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

28.6

I/O Lines Programming Example

The programing example as shown in

Table 28-1 below is used to define the following

configuration.

• 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor

• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor

• Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts

• Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter

• I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor

• I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor

• I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor

Table 28-1.

Programming Example

Register

PIO_PER

PIO_PDR

PIO_OER

PIO_ODR

PIO_IFER

PIO_IFDR

PIO_SODR

PIO_CODR

PIO_IER

PIO_IDR

PIO_MDER

PIO_MDDR

PIO_PUDR

PIO_PUER

PIO_ASR

PIO_BSR

PIO_OWER

PIO_OWDR

Value to be Written

0x0000 FFFF

0x0FFF 0000

0x0000 00FF

0x0FFF FF00

0x0000 0F00

0x0FFF F0FF

0x0000 0000

0x0FFF FFFF

0x0F00 0F00

0x00FF F0FF

0x0000 000F

0x0FFF FFF0

0x00F0 00F0

0x0F0F FF0F

0x0F0F 0000

0x00F0 0000

0x0000 000F

0x0FFF FFF0

233

6120D–ATARM–02-Feb-06

28.7

Parallel Input/Output Controller (PIO) User Interface

Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns

1 systematically.

Table 28-2.

Parallel Input/Output Controller (PIO) Register Mapping

Offset Register Name

0x0040

0x0044

0x0048

0x004C

0x0050

0x0054

0x0058

0x005C

0x0060

0x0064

0x0068

0x006C

0x0020

0x0024

0x0028

0x002C

0x0030

0x0034

0x0038

0x003C

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

PIO Enable Register

PIO Disable Register

PIO Status Register

(1)

Reserved

Output Enable Register

Output Disable Register

Output Status Register

Reserved

Glitch Input Filter Enable Register

Glitch Input Filter Disable Register

Glitch Input Filter Status Register

Reserved

Set Output Data Register

Clear Output Data Register

Output Data Status Register

(2)

Pin Data Status Register

(3)

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Interrupt Status Register

(4)

Multi-driver Enable Register

Multi-driver Disable Register

Multi-driver Status Register

Reserved

Pull-up Disable Register

Pull-up Enable Register

Pad Pull-up Status Register

Reserved

PIO_PER

PIO_PDR

PIO_PSR

PIO_OER

PIO_ODR

PIO_OSR

PIO_IFER

PIO_IFDR

PIO_IFSR

PIO_SODR

PIO_CODR

PIO_ODSR

PIO_PDSR

PIO_IER

PIO_IDR

PIO_IMR

PIO_ISR

PIO_MDER

PIO_MDDR

PIO_MDSR

PIO_PUDR

PIO_PUER

PIO_PUSR

Access

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Read-only

Write-only

Write-only

Read-only

Read-only

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Reset Value

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

0x00000000

0x00000000

0x00000000

0x00000000

234

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

Table 28-2.

Parallel Input/Output Controller (PIO) Register Mapping (Continued)

Offset

0x0070

0x0074

0x0078

0x007C - 0x009C

Register

Peripheral A Select Register

(5)

Peripheral B Select Register

(5)

AB Status Register

(5)

Reserved

Name

PIO_ASR

PIO_BSR

PIO_ABSR

Access

Write-only

Write-only

Read-only

Reset Value

0x00000000

0x00A0

0x00A4

Output Write Enable

Output Write Disable

PIO_OWER

PIO_OWDR

Write-only

Write-only

0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000

0x00AC - 0x00FC Reserved

Notes: 1. Reset value of PIO_PSR depends on the product implementation.

2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.

3. Reset value of PIO_PDSR depends on the level of the I/O lines.

4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred.

5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register.

235

6120D–ATARM–02-Feb-06

28.7.1

Name:

PIO Controller PIO Enable Register

Access Type:

PIO_PER

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

• P0-P31: PIO Enable

0 = No effect.

1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).

25

P25

17

P17

9

P9

1

P1

28.7.2

Name:

PIO Controller PIO Disable Register

Access Type:

PIO_PDR

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

• P0-P31: PIO Disable

0 = No effect.

1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

236

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

28.7.3

Name:

PIO Controller PIO Status Register

Access Type:

PIO_PSR

Read-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

28

P28

20

P20

12

P12

4

P4

• P0-P31: PIO Status

0 = PIO is inactive on the corresponding I/O line (peripheral is active).

1 = PIO is active on the corresponding I/O line (peripheral is inactive).

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

28.7.4

Name:

PIO Controller Output Enable Register

Access Type:

PIO_OER

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Enable

0 = No effect.

1 = Enables the output on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

237

6120D–ATARM–02-Feb-06

28.7.5

Name:

PIO Controller Output Disable Register

Access Type:

PIO_ODR

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Disable

0 = No effect.

1 = Disables the output on the I/O line.

28.7.6

Name:

PIO Controller Output Status Register

Access Type:

PIO_OSR

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Status

0 = The I/O line is a pure input.

1 = The I/O line is enabled in output.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

238

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

28.7.7

Name:

PIO Controller Input Filter Enable Register

Access Type:

PIO_IFER

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Filter Enable

0 = No effect.

1 = Enables the input glitch filter on the I/O line.

28.7.8

Name:

PIO Controller Input Filter Disable Register

Access Type:

PIO_IFDR

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Filter Disable

0 = No effect.

1 = Disables the input glitch filter on the I/O line.

AT91SAM7X256/128 Preliminary

27

P27

19

P19

11

P11

3

P3

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

239

6120D–ATARM–02-Feb-06

28.7.9

Name:

PIO Controller Input Filter Status Register

Access Type:

PIO_IFSR

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Filer Status

0 = The input glitch filter is disabled on the I/O line.

1 = The input glitch filter is enabled on the I/O line.

28.7.10

PIO Controller Set Output Data Register

Name:

PIO_SODR

Access Type:

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Set Output Data

0 = No effect.

1 = Sets the data to be driven on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

240

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

28.7.11

PIO Controller Clear Output Data Register

Name:

PIO_CODR

Access Type:

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Set Output Data

0 = No effect.

1 = Clears the data to be driven on the I/O line.

28.7.12

PIO Controller Output Data Status Register

Name:

PIO_ODSR

Access Type:

Read-only or Read/Write

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Data Status

0 = The data to be driven on the I/O line is 0.

1 = The data to be driven on the I/O line is 1.

AT91SAM7X256/128 Preliminary

27

P27

19

P19

11

P11

3

P3

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

241

6120D–ATARM–02-Feb-06

28.7.13

PIO Controller Pin Data Status Register

Name:

PIO_PDSR

Access Type:

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Data Status

0 = The I/O line is at level 0.

1 = The I/O line is at level 1.

28.7.14

PIO Controller Interrupt Enable Register

Name:

PIO_IER

Access Type:

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Change Interrupt Enable

0 = No effect.

1 = Enables the Input Change Interrupt on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

242

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

28.7.15

PIO Controller Interrupt Disable Register

Name:

PIO_IDR

Access Type:

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Change Interrupt Disable

0 = No effect.

1 = Disables the Input Change Interrupt on the I/O line.

28.7.16

PIO Controller Interrupt Mask Register

Name:

PIO_IMR

Access Type:

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Change Interrupt Mask

0 = Input Change Interrupt is disabled on the I/O line.

1 = Input Change Interrupt is enabled on the I/O line.

AT91SAM7X256/128 Preliminary

27

P27

19

P19

11

P11

3

P3

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

243

6120D–ATARM–02-Feb-06

28.7.17

PIO Controller Interrupt Status Register

Name:

PIO_ISR

Access Type:

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

• P0-P31: Input Change Interrupt Status

0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.

1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.

24

P24

16

P16

8

P8

0

P0

28.7.18

PIO Multi-driver Enable Register

Name:

PIO_MDER

Access Type:

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Multi Drive Enable.

0 = No effect.

1 = Enables Multi Drive on the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

244

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

28.7.19

PIO Multi-driver Disable Register

Name:

PIO_MDDR

Access Type:

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Multi Drive Disable.

0 = No effect.

1 = Disables Multi Drive on the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

28.7.20

PIO Multi-driver Status Register

Name:

PIO_MDSR

Access Type:

Read-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

• P0-P31: Multi Drive Status.

0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level.

1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only.

26

P26

18

P18

10

P10

2

P2

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

245

6120D–ATARM–02-Feb-06

28.7.21

PIO Pull Up Disable Register

Name:

PIO_PUDR

Access Type:

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Pull Up Disable.

0 = No effect.

1 = Disables the pull up resistor on the I/O line.

28

P28

20

P20

12

P12

4

P4

28.7.22

PIO Pull Up Enable Register

Name:

PIO_PUER

Access Type:

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Pull Up Enable.

0 = No effect.

1 = Enables the pull up resistor on the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

246

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

28.7.23

PIO Pull Up Status Register

Name:

PIO_PUSR

Access Type:

Read-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Pull Up Status.

0 = Pull Up resistor is enabled on the I/O line.

1 = Pull Up resistor is disabled on the I/O line.

28

P28

20

P20

12

P12

4

P4

28.7.24

PIO Peripheral A Select Register

Name:

PIO_ASR

Access Type:

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Peripheral A Select.

0 = No effect.

1 = Assigns the I/O line to the Peripheral A function.

28

P28

20

P20

12

P12

4

P4

AT91SAM7X256/128 Preliminary

27

P27

19

P19

11

P11

3

P3

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

247

6120D–ATARM–02-Feb-06

28.7.25

PIO Peripheral B Select Register

Name:

PIO_BSR

Access Type:

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Peripheral B Select.

0 = No effect.

1 = Assigns the I/O line to the peripheral B function.

28

P28

20

P20

12

P12

4

P4

28.7.26

PIO Peripheral A B Status Register

Name:

PIO_ABSR

Access Type:

Read-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Peripheral A B Status.

0 = The I/O line is assigned to the Peripheral A.

1 = The I/O line is assigned to the Peripheral B.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

248

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

28.7.27

PIO Output Write Enable Register

Name:

PIO_OWER

Access Type:

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Output Write Enable.

0 = No effect.

1 = Enables writing PIO_ODSR for the I/O line.

28

P28

20

P20

12

P12

4

P4

28.7.28

PIO Output Write Disable Register

Name:

PIO_OWDR

Access Type:

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Output Write Disable.

0 = No effect.

1 = Disables writing PIO_ODSR for the I/O line.

28

P28

20

P20

12

P12

4

P4

AT91SAM7X256/128 Preliminary

27

P27

19

P19

11

P11

3

P3

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

24

P24

16

P16

8

P8

0

P0

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28.7.29

PIO Output Write Status Register

Name:

PIO_OWSR

Access Type:

Read-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Output Write Status.

0 = Writing PIO_ODSR does not affect the I/O line.

1 = Writing PIO_ODSR affects the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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29. Serial Peripheral Interface (SPI)

29.1

Overview

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.

The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master.

Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master

Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time.

A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS).

The SPI system consists of two data lines and two control lines:

• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s).

• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer.

• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.

• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

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29.2

Block Diagram

Figure 29-1. Block Diagram

PDC

APB

PMC

MCK

DIV

SPI Interface PIO

MCK

(1)

N

Interrupt Control

SPI Interrupt

Note: 1. N = 32

29.3

Application Block Diagram

Figure 29-2. Application Block Diagram: Single Master/Multiple Slave Implementation

SPI Master

SPCK

MISO

MOSI

NPCS0

NPCS1

NPCS2

NPCS3

NC

MISO

MOSI

NSS

SPCK

MISO

MOSI

NSS

SPCK

MISO

MOSI

NSS

SPCK

Slave 0

Slave 1

Slave 2

SPCK

MISO

MOSI

NPCS0/NSS

NPCS1

NPCS2

NPCS3

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29.4

Signal Description

Table 29-1.

Signal Description

Pin Name

MISO

MOSI

SPCK

NPCS1-NPCS3

NPCS0/NSS

Pin Description

Master In Slave Out

Master Out Slave In

Serial Clock

Peripheral Chip Selects

Peripheral Chip Select/Slave Select

Master

Input

Output

Output

Output

Output

Type

Slave

Output

Input

Input

Unused

Input

29.5

Product Dependencies

29.5.1

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.

The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions.

29.5.2

29.5.3

Power Management

The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock.

Interrupt

The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).

Handling the SPI interrupt requires programming the AIC before configuring the SPI.

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29.6

Functional Description

29.6.1

Modes of Operation

The SPI operates in Master Mode or in Slave Mode.

Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register.

The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter.

If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a

Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes.

The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.

29.6.2

Data Transfer

Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave.

Table 29-2

shows the four modes and corresponding parameter settings.

Table 29-2.

SPI Bus Protocol Mode

SPI Mode

0

1

2

3

CPOL

0

0

1

1

NCPHA

1

0

1

0

Figure 29-3 and Figure 29-4

show examples of data transfers.

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Figure 29-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)

SPCK cycle (for reference)

1 2 3 4 5

SPCK

(CPOL = 0)

7 8

SPCK

(CPOL = 1)

MOSI

(from master)

MISO

(from slave)

MSB 6

MSB 6

5

5

4

4

3

3

2

2 1

1 LSB

LSB

*

NSS

(to slave)

* Not defined, but normally MSB of previous character received.

Figure 29-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)

1 2 3 4

SPCK cycle (for reference)

SPCK

(CPOL = 0)

5 6 7 8

SPCK

(CPOL = 1)

MOSI

(from master)

MISO

(from slave)

NSS

(to slave)

MSB 6

*

MSB 6

5

5

4

4

3

3

* Not defined but normally LSB of previous character transmitted.

2

2 1

1 LSB

LSB

255

6120D–ATARM–02-Feb-06

29.6.3

Master Mode Operations

When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK).

The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate.

After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception.

No transfer is started when writing into the SPI_TDR if the PCS field does not select a slave. The

PCS field is set by writing the SPI_TDR in variable mode, or the SPI_MR in fixed mode, depending on the value of PCS field.

If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts.

The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit

(Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in

SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel.

The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay

(DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time.

The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit

(Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared.

If the SPI_RDR (Receive Data Register) has not been read before new data is received, the

Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, no data is loaded in

SPI_RDR. The user has to read the status register to clear the OVRES bit.

Figure 29-5 on page 257

shows a block diagram of the SPI when operating in Master Mode. Figure 29-6 on page 258 shows a flow chart describing how transfers are handled.

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29.6.3.1

Master Mode Block Diagram

Figure 29-5. Master Mode Block Diagram

FDIV

SPI_CSR0..3

SCBR

MCK

0

Baud Rate Generator

MCK/N

1

SPI

Clock

SPCK

SPI_CSR0..3

BITS

NCPHA

CPOL

LSB

SPI_RDR

Shift Register

RD

MSB

RDRF

OVRES

MISO

MOSI

SPI_MR

PCS

PS

0

SPI_TDR

TD

SPI_CSR0..3

CSAAT

TDRE

SPI_RDR

PCS

PCSDEC

Current

Peripheral

SPI_TDR

PCS

1

NPCS3

NPCS2

NPCS1

NPCS0

MSTR

MODF

NPCS0

MODFDIS

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29.6.3.2

Master Mode Flow Diagram

Figure 29-6. Master Mode Flow Diagram S

SPI Enable

- NPCS defines the current Chip Select

- CSAAT, DLYBS, DLYBCT refer to the fields of the

Chip Select Register corresponding to the Current Chip Select

- When NPCS is 0xF, CSAAT is 0.

1

TDRE ?

0

1

CSAAT ?

0

PS ?

1

Variable peripheral

NPCS = SPI_TDR(PCS)

0

Fixed

peripheral

NPCS = SPI_MR(PCS)

PS ?

1

Variable peripheral

0

Fixed

peripheral yes

SPI_TDR(PCS)

= NPCS ?

no

NPCS = 0xF

SPI_MR(PCS)

= NPCS ?

no

NPCS = 0xF

Delay DLYBCS

NPCS = SPI_TDR(PCS)

Delay DLYBCS

NPCS = SPI_MR(PCS),

SPI_TDR(PCS)

Delay DLYBS

Serializer = SPI_TDR(TD)

TDRE = 1

Data Transfer

SPI_RDR(RD) = Serializer

RDRF = 1

Delay DLYBCT

1

TDRE ?

1

CSAAT ?

0

NPCS = 0xF

Delay DLYBCS

0

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29.6.3.3

29.6.3.4

Clock Generation

The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock divided by 32, by a value between 2 and 255. The selection between Master Clock or Master

Clock divided by N is done by the FDIV value set in the Mode Register

This allows a maximum operating baud rate at up to Master Clock/2 and a minimum operating baud rate of MCK divided by 255*32.

Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.

At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.

The divisor can be defined independently for each chip select, as it has to be programmed in the

SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.

Transfer Delays

Figure 29-7 shows a chip select transfer change and consecutive transfers on the same chip

select. Three delays can be programmed to modify the transfer waveforms:

• The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.

• The delay before SPCK, independently programmable for each chip select by writing the field

DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.

• The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select

These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.

Figure 29-7. Programmable Delays

Chip Select 1

Chip Select 2

SPCK

DLYBCS DLYBS DLYBCT DLYBCT

29.6.3.5

Peripheral Selection

The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.

The peripheral selection can be performed in two different ways:

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6120D–ATARM–02-Feb-06

29.6.3.6

29.6.3.7

• Fixed Peripheral Select: SPI exchanges data with only one peripheral

• Variable Peripheral Select: Data can be exchanged with more than one peripheral

Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS fields of the

Chip Select Registers have no effect.

Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data.

The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed.

The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor.

Peripheral Chip Select Decoding

The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip

Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCS-

DEC bit at 1 in the Mode Register (SPI_MR).

When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low.

When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS).

As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded.

The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the

PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.

Peripheral Deselection

When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers.

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To facilitate interfacing with such devices, the Chip Select Register can be programmed with the

CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required.

Figure 29-8

shows different peripheral deselection cases and the effect of the CSAAT bit.

Figure 29-8. Peripheral Deselection

CSAAT = 0 CSAAT = 1

TDRE

NPCS[0..3] A

DLYBCT

DLYBCS

PCS = A

A A

DLYBCT

A

DLYBCS

PCS = A

A

Write SPI_TDR

TDRE

NPCS[0..3] A

DLYBCT

DLYBCS

PCS=A

A

Write SPI_TDR

TDRE

NPCS[0..3]

A

DLYBCT

DLYBCS

PCS = B

Write SPI_TDR

B

A

DLYBCT

A

DLYBCS

PCS = A

A

DLYBCT

PCS = B

DLYBCS

A

B

29.6.3.8

Mode Fault Detection

A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. As this pin is generally configured in opendrain, it is important that a pull up resistor is connected on the NPCS0 line, so that a high level is guaranteed and no spurious mode fault is detected.

When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1.

By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).

261

6120D–ATARM–02-Feb-06

29.6.4

SPI Slave Mode

When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).

The SPI waits for NSS to go active before receiving the serial clock from an external master.

When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the

SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode.

The bits are shifted out on the MISO line and sampled on the MOSI line.

When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If RDRF is already high when the data is transferred, the Overrun bit rises and the data transfer to SPI_RDR is aborted.

When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred.

If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0.

When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the

TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in

SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers.

Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted.

Figure 29-9

shows a block diagram of the SPI when operating in Slave Mode.

Figure 29-9. Slave Mode Functional Block Diagram

SPCK

NSS

SPI

Clock

MOSI

SPIEN

SPIENS

SPIDIS

SPI_CSR0

BITS

NCPHA

CPOL

LSB

SPI_RDR

Shift Register

RD

MSB

RDRF

OVRES

MISO

FLOAD

SPI_TDR

TD

TDRE

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29.7

Serial Peripheral Interface (SPI) User Interface

Table 29-3.

Serial Peripheral Interface (SPI) Register Mapping

Offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

Control Register

Mode Register

Receive Data Register

Transmit Data Register

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

0x20 - 0x2C

0x30

0x34

0x38

Reserved

Chip Select Register 0

Chip Select Register 1

Chip Select Register 2

0x3C Chip Select Register 3

0x004C - 0x00FC Reserved

0x100 - 0x124 Reserved for the PDC

SPI_CR

SPI_MR

SPI_RDR

SPI_TDR

SPI_SR

SPI_IER

SPI_IDR

SPI_IMR

SPI_CSR0

SPI_CSR1

SPI_CSR2

SPI_CSR3

Write-only

Read/Write

Read-only

Write-only

Read-only

Write-only

Write-only

Read-only

Read/Write

Read/Write

Read/Write

Read/Write

Reset

---

0x0

0x0

---

0x000000F0

---

---

0x0

0x0

0x0

0x0

0x0

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6120D–ATARM–02-Feb-06

29.7.1

SPI Control Register

Name: SPI_CR

Access Type: Write-only

31

30

23

15

7

SWRST

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

1

SPIDIS

24

LASTXFER

16

8

0

SPIEN

• SPIEN: SPI Enable

0 = No effect.

1 = Enables the SPI to transfer and receive data.

• SPIDIS: SPI Disable

0 = No effect.

1 = Disables the SPI.

All pins are set in input mode and no data is received or transmitted.

If a transfer is in progress, the transfer is finished before the SPI is disabled.

If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.

• SWRST: SPI Software Reset

0 = No effect.

1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.

• LASTXFER: Last Transfer

0 = No effect.

1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

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29.7.2

SPI Mode Register

Name: SPI_MR

Access Type: Read/Write

31 30 29

23

15

7

LLB

22

14

6

21

13

5

28

DLYBCS

20

12

4

MODFDIS

27

19

11

3

FDIV

26

18

10

2

PCSDEC

PCS

25

17

9

1

PS

24

16

8

0

MSTR

• MSTR: Master/Slave Mode

0 = SPI is in Slave mode.

1 = SPI is in Master mode.

• PS: Peripheral Select

0 = Fixed Peripheral Select.

1 = Variable Peripheral Select.

• PCSDEC: Chip Select Decode

0 = The chip selects are directly connected to a peripheral device.

1 = The four chip select lines are connected to a 4- to 16-bit decoder.

When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:

SPI_CSR0 defines peripheral chip select signals 0 to 3.

SPI_CSR1 defines peripheral chip select signals 4 to 7.

SPI_CSR2 defines peripheral chip select signals 8 to 11.

SPI_CSR3 defines peripheral chip select signals 12 to 15.

• FDIV: Clock Selection

0 = The SPI operates at MCK.

1 = The SPI operates at MCK/N.

• MODFDIS: Mode Fault Detection

0 = Mode fault detection is enabled.

1 = Mode fault detection is disabled.

• LLB: Local Loopback Enable

0 = Local loopback path disabled.

1 = Local loopback path enabled.

LLB controls the local loopback on the data serializer for testing in Master Mode only.

• PCS: Peripheral Chip Select

This field is only used if Fixed Peripheral Select is active (PS = 0).

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6120D–ATARM–02-Feb-06

If PCSDEC = 0:

PCS = xxx0

PCS = xx01

PCS = x011

PCS = 0111

PCS = 1111

(x = don’t care)

If PCSDEC = 1:

NPCS[3:0] = 1110

NPCS[3:0] = 1101

NPCS[3:0] = 1011

NPCS[3:0] = 0111 forbidden (no peripheral is selected)

NPCS[3:0] output signals = PCS.

• DLYBCS: Delay Between Chip Selects

This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times.

If DLYBCS is less than or equal to six, six MCK periods (or 6*N MCK periods if FDIV is set) will be inserted by default.

Otherwise, the following equation determines the delay:

If FDIV is 0:

Delay Between Chip Selects

=

MCK

If FDIV is 1:

Delay Between Chip Selects

=

DLYBCS

MCK

×

N

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29.7.3

SPI Receive Data Register

Name: SPI_RDR

Access Type: Read-only

31

30

29

23

15

22

14

21

13

28

20

12

27

19

11

26

18

10

PCS

25

17

9

24

16

8

RD

7 6 5 4 3 2 1 0

RD

• RD: Receive Data

Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.

• PCS: Peripheral Chip Select

In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.

267

6120D–ATARM–02-Feb-06

29.7.4

SPI Transmit Data Register

Name: SPI_TDR

Access Type: Write-only

31

30

29

23

15

22

14

21

13

28

20

12

27

19

11

26

18

10

PCS

25

17

9

24

LASTXFER

16

8

TD

7 6 5 4 3 2 1 0

TD

• TD: Transmit Data

Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.

PCS: Peripheral Chip Select

This field is only used if Variable Peripheral Select is active (PS = 1).

If PCSDEC = 0:

PCS = xxx0

PCS = xx01

PCS = x011

PCS = 0111

PCS = 1111

NPCS[3:0] = 1110

NPCS[3:0] = 1101

NPCS[3:0] = 1011

NPCS[3:0] = 0111 forbidden (no peripheral is selected)

(x = don’t care)

If PCSDEC = 1:

NPCS[3:0] output signals = PCS

• LASTXFER: Last Transfer

0 = No effect.

1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

268

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

29.7.5

SPI Status Register

Name: SPI_SR

Access Type: Read-only

31

23

15

7

TXBUFE

30

22

14

6

RXBUFF

29

21

13

5

ENDTX

28

20

12

4

ENDRX

27

19

11

3

OVRES

26

18

10

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

SPIENS

8

NSSR

0

RDRF

• RDRF: Receive Data Register Full

0 = No data has been received since the last read of SPI_RDR

1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR.

• TDRE: Transmit Data Register Empty

0 = Data has been written to SPI_TDR and not yet transferred to the serializer.

1 = The last data written in the Transmit Data Register has been transferred to the serializer.

TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.

• MODF: Mode Fault Error

0 = No Mode Fault has been detected since the last read of SPI_SR.

1 = A Mode Fault occurred since the last read of the SPI_SR.

• OVRES: Overrun Error Status

0 = No overrun has been detected since the last read of SPI_SR.

1 = An overrun has occurred since the last read of SPI_SR.

An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.

• ENDRX: End of RX buffer

0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR or SPI_RNCR.

1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR or SPI_RNCR.

• ENDTX: End of TX buffer

0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR or SPI_TNCR.

1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR or SPI_TNCR.

• RXBUFF: RX Buffer Full

0 = SPI_RCR or SPI_RNCR has a value other than 0.

1 = Both SPI_RCR and SPI_RNCR has a value of 0.

269

6120D–ATARM–02-Feb-06

• TXBUFE: TX Buffer Empty

0 = SPI_TCR or SPI_TNCR has a value other than 0.

1 = Both SPI_TCR and SPI_TNCR has a value of 0.

• NSSR: NSS Rising

0 = No rising edge detected on NSS pin since last read.

1 = A rising edge occurred on NSS pin since last read.

• TXEMPTY: Transmission Registers Empty

0 = As soon as data is written in SPI_TDR.

1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

• SPIENS: SPI Enable Status

0 = SPI is disabled.

1 = SPI is enabled.

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AT91SAM7X256/128 Preliminary

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AT91SAM7X256/128 Preliminary

29.7.6

SPI Interrupt Enable Register

Name: SPI_IER

Access Type: Write-only

31

23

15

7

TXBUFE

30

22

14

6

RXBUFF

29

21

13

5

ENDTX

28

20

12

4

ENDRX

• RDRF: Receive Data Register Full Interrupt Enable

• TDRE: SPI Transmit Data Register Empty Interrupt Enable

• MODF: Mode Fault Error Interrupt Enable

• OVRES: Overrun Error Interrupt Enable

• ENDRX: End of Receive Buffer Interrupt Enable

• ENDTX: End of Transmit Buffer Interrupt Enable

• RXBUFF: Receive Buffer Full Interrupt Enable

• TXBUFE: Transmit Buffer Empty Interrupt Enable

• TXEMPTY: Transmission Registers Empty Enable

• NSSR: NSS Rising Interrupt Enable

0 = No effect.

1 = Enables the corresponding interrupt.

27

19

11

3

OVRES

26

18

10

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

8

NSSR

0

RDRF

271

6120D–ATARM–02-Feb-06

29.7.7

SPI Interrupt Disable Register

Name: SPI_IDR

Access Type: Write-only

31

23

15

7

TXBUFE

30

22

14

6

RXBUFF

29

21

13

5

ENDTX

28

20

12

4

ENDRX

• RDRF: Receive Data Register Full Interrupt Disable

• TDRE: SPI Transmit Data Register Empty Interrupt Disable

• MODF: Mode Fault Error Interrupt Disable

• OVRES: Overrun Error Interrupt Disable

• ENDRX: End of Receive Buffer Interrupt Disable

• ENDTX: End of Transmit Buffer Interrupt Disable

• RXBUFF: Receive Buffer Full Interrupt Disable

• TXBUFE: Transmit Buffer Empty Interrupt Disable

• TXEMPTY: Transmission Registers Empty Disable

• NSSR: NSS Rising Interrupt Disable

0 = No effect.

1 = Disables the corresponding interrupt.

27

19

11

3

OVRES

26

18

10

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

8

NSSR

0

RDRF

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

29.7.8

SPI Interrupt Mask Register

Name: SPI_IMR

Access Type: Read-only

31

23

15

7

TXBUFE

30

22

14

6

RXBUFF

29

21

13

5

ENDTX

28

20

12

4

ENDRX

• RDRF: Receive Data Register Full Interrupt Mask

• TDRE: SPI Transmit Data Register Empty Interrupt Mask

• MODF: Mode Fault Error Interrupt Mask

• OVRES: Overrun Error Interrupt Mask

• ENDRX: End of Receive Buffer Interrupt Mask

• ENDTX: End of Transmit Buffer Interrupt Mask

• RXBUFF: Receive Buffer Full Interrupt Mask

• TXBUFE: Transmit Buffer Empty Interrupt Mask

• TXEMPTY: Transmission Registers Empty Mask

• NSSR: NSS Rising Interrupt Mask

0 = The corresponding interrupt is not enabled.

1 = The corresponding interrupt is enabled.

27

19

11

3

OVRES

26

18

10

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

8

NSSR

0

RDRF

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6120D–ATARM–02-Feb-06

29.7.9

SPI Chip Select Register

Access Type: Read/Write

31 30 29 28 27 26 25 24

DLYBCT

23 22 21 20 19 18 17 16

DLYBS

15 14 13 12 11 10 9 8

SCBR

7 6

BITS

5 4 3

CSAAT

2

1

NCPHA

0

CPOL

• CPOL: Clock Polarity

0 = The inactive state value of SPCK is logic level zero.

1 = The inactive state value of SPCK is logic level one.

CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.

• NCPHA: Clock Phase

0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.

1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.

• CSAAT: Chip Select Active After Transfer

0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.

1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select.

• BITS: Bits Per Transfer

The BITS field determines the number of data bits transferred. Reserved values should not be used.

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

BITS

0000

0001

0010

0011

0100

0101

Bits Per Transfer

8

9

10

11

12

13

14

15

16

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

• SCBR: Serial Clock Baud Rate

In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The

Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:

If FDIV is 0:

SPCK Baudrate

=

SCBR

If FDIV is 1:

SPCK Baudrate

=

(

N

×

SCBR

)

Note: N = 32

Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.

At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.

• DLYBS: Delay Before SPCK

This field defines the delay from NPCS valid to the first valid SPCK transition.

When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.

Otherwise, the following equations determine the delay:

If FDIV is 0:

Delay Before SPCK

=

MCK

If FDIV is 1:

Delay Before SPCK

=

N

×

DLYBS

MCK

Note: N = 32

• DLYBCT: Delay Between Consecutive Transfers

This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.

The delay is always inserted after each transfer and before removing the chip select if needed.

When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.

Otherwise, the following equation determines the delay:

275

6120D–ATARM–02-Feb-06

If FDIV is 0:

Delay Between Consecutive Transfers

=

32

×

DLYBCT

MCK

+

2

MCK

If FDIV is 1:

Note: N = 32

Delay Between Consecutive Transfers

=

32

×

N

×

MCK

+

N

×

SCBR

2

MCK

276

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

30. Two-wire Interface (TWI)

30.1

Overview

The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel two-wire bus Serial EEPROM. The TWI is programmable as a master with sequential or single-byte access. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.

30.2

Block Diagram

Figure 30-1. Block Diagram

APB Bridge

PIO

PMC

MCK

Two-wire

Interface

TWI

Interrupt

AIC

30.3

Application Block Diagram

Figure 30-2. Application Block Diagram

Host with

TWI

Interface

TWD

TWCK

AT24LC16

U1

Slave 1

AT24LC16

U2

Slave 2

LCD Controller

U3

Slave 3

R

TWCK

TWD

R

VDD

277

6120D–ATARM–02-Feb-06

30.4

Product Dependencies

30.4.1

30.4.2

30.4.3

30.4.4

I/O Lines Description

Table 30-1.

I/O Lines Description

Pin Name Pin Description

TWD

TWCK

Two-wire Serial Data

Two-wire Serial Clock

Type

Input/Output

Input/Output

I/O Lines

Both TWD and TWCK are bi-directional lines, connected to a positive supply voltage via a cur-

rent source or pull-up resistor (see Figure 30-2 on page 277 ). When the bus is free, both lines

are high. The output stages of devices connected to the bus must have an open-drain or opencollector to perform the wired-AND function.

TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps:

• Program the PIO controller to:

– Dedicate TWD and TWCK as peripheral lines.

– Define TWD and TWCK as open-drain.

Power Management

• Enable the peripheral clock.

The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock.

Interrupt

The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI.

278

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AT91SAM7X256/128 Preliminary

30.5

Functional Description

30.5.1

Transfer format

The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must

be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure

30-4 on page 279

).

Each transfer begins with a START condition and terminates with a STOP condition (see

Figure

30-3 on page 279

).

• A high-to-low transition on the TWD line while TWCK is high defines the START condition.

• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.

Figure 30-3. START and STOP Conditions

TWD

TWCK

Start Stop

Figure 30-4. Transfer Format

TWD

TWCK

30.5.2

30.5.3

Start Address R/W Ack Data Ack Data Ack Stop

Modes of Operation

The TWI has two modes of operation:

• Master transmitter mode

• Master receiver mode

The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it generates the clock according to the value programmed in the Clock Waveform Generator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks.

Transmitting Data

After the master initiates a Start condition, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction (write or read). If this bit is 0, it indicates a write operation

(transmit operation). If the bit is 1, it indicates a request for data read (receive operation).

The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and

279

6120D–ATARM–02-Feb-06

sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register

(TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in the control register starts the transmission. The data is shifted in the internal shifter and when an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see

Figure 30-

6 below). The master generates a stop condition to end the transfer.

The read sequence begins by setting the START bit. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.

The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address).

The three internal address bytes are configurable through the Master Mode register

(TWI_MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR).

Figure 30-5. Master Write with One, Two or Three Bytes Internal Address and One Data Byte

TWD

Three bytes internal address

S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA

TWD

Two bytes internal address

S DADR W

TWD

One byte internal address

S DADR W

A

A

IADR(15:8)

IADR(7:0)

A

A

IADR(7:0)

DATA

A

A

P

DATA A

P

A P

Figure 30-6. Master Write with One Byte Internal Address and Multiple Data Bytes

TWD S DADR W

A IADR(7:0) A

DATA A

DATA

TXCOMP

Write THR

TXRDY

Write THR

Write THR

A

Write THR

DATA A

P

Figure 30-7. Master Read with One, Two or Three Bytes Internal Address and One Data Byte

TWD

Three bytes internal address

S DADR

W

A IADR(23:16) A

IADR(15:8)

A

IADR(7:0) A S DADR

DATA

TWD

Two bytes internal address

S DADR W

TWD

One byte internal address

S DADR W

A IADR(15:8) A

A

IADR(7:0) A

IADR(7:0) A

S DADR R

S

A

DADR

DATA

R A

N P

DATA

R A

N P

N P

280

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AT91SAM7X256/128 Preliminary

Figure 30-8. Master Read with One Byte Internal Address and Multiple Data Bytes

TWD

S DADR W A IADR(7:0) A S DADR R A DATA A

DATA N P

TXCOMP

Write START Bit

Write STOP Bit

RXRDY

Read RHR Read RHR

• S = Start

• P = Stop

• W = Write

• R = Read

• A = Acknowledge

• N = Not Acknowledge

• DADR= Device Address

• IADR = Internal Address

Figure 30-9 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the

use of internal addresses to access the device.

Figure 30-9. Internal Address Usage

S

T

A

R

T

Device

Address

0

M

S

B

W

R

I

T

E

FIRST

WORD ADDRESS

SECOND

WORD ADDRESS

L

S

B

R

/

W

A

C

K

M

S

B

A

C

K

L

S

B

A

C

K

DATA

A

C

K

S

T

O

P

281

6120D–ATARM–02-Feb-06

30.5.4

Read/Write Flowcharts

The following flowcharts shown in Figure 30-10

and in Figure 30-11 on page 283

give examples for read and write operations in Master Mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.

Figure 30-10. TWI Write in Master Mode

START

Set TWI clock:

TWI_CWGR = clock

Set the control register:

- Master enable

TWI_CR = MSEN

Set the Master Mode register:

- Device slave address

- Internal address size

- Transfer direction bit

Write ==> bit MREAD = 0

Internal address size = 0?

Yes

Load transmit register

TWI_THR = Data to send

Start the transfer

TWI_CR = START

Read status register

Set theinternal address

TWI_IADR = address

TWI_THR = data to send

TXRDY = 0?

Yes

Yes

Data to send?

Stop the transfer

TWI_CR = STOP

Read status register

TXCOMP = 0?

Yes

END

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AT91SAM7X256/128 Preliminary

Figure 30-11. TWI Read in Master Mode

Yes

START

Set TWI clock:

TWI_CWGR = clock

Set the control register:

- Master enable

- Slave disable

TWI_CR = MSEN

Set the Master Mode register:

- Device slave address

- Internal address size

- Transfer direction bit

Read ==> bit MREAD = 0

Internal address size = 0?

Yes

Start the transfer

TWI_CR = START

Read status register

RXRDY = 0?

Data to read?

Stop the transfer

TWI_CR = STOP

Read status register

TXCOMP = 0?

END

Yes

Yes

Set the internal address

TWI_IADR = address

283

6120D–ATARM–02-Feb-06

30.6

TWI User Interface

30.6.1

Register Mapping

Table 30-2.

Two-wire Interface (TWI) User Interface

Offset Register

0x0000

0x0004

0x0008

0x000C

0x0010

0x0020

0x0024

0x0028

0x002C

0x0030

0x0034

0x0038 - 0x00FC

Control Register

Master Mode Register

Reserved

Internal Address Register

Clock Waveform Generator Register

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Receive Holding Register

Transmit Holding Register

Reserved

Name

TWI_CR

TWI_MMR

-

TWI_IADR

TWI_CWGR

TWI_SR

TWI_IER

TWI_IDR

TWI_IMR

TWI_RHR

TWI_THR

Access

Write-only

Read/Write

-

Read/Write

Read/Write

Read-only

Write-only

Write-only

Read-only

Read-only

Read/Write

Reset Value

N/A

0x0000

-

0x0000

0x0000

0x0008

N/A

N/A

0x0000

0x0000

0x0000

284

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AT91SAM7X256/128 Preliminary

30.6.2

Register Name:

Access Type:

31

TWI Control Register

23

15

7

SWRST

TWI_CR

Write-only

30

22

14

6

13

5

29

21

12

4

28

20

27

19

11

3

MSDIS

26

18

10

2

MSEN

25

17

9

1

STOP

24

16

8

0

START

• START: Send a START Condition

0 = No effect.

1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.

This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register.

• STOP: Send a STOP Condition

0 = No effect.

1 = STOP Condition is sent just after completing the current byte transmission in master read or write mode.

In single data byte master read or write, the START and STOP must both be set.

In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission.

In master read mode, if a NACK bit is received, the STOP is automatically performed.

In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.

• MSEN: TWI Master Transfer Enabled

0 = No effect.

1 = If MSDIS = 0, the master data transfer is enabled.

• MSDIS: TWI Master Transfer Disabled

0 = No effect.

1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if they contain data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.

• SWRST: Software Reset

0 = No effect.

1 = Equivalent to a system reset.

285

6120D–ATARM–02-Feb-06

30.6.3

TWI Master Mode Register

Register Name: TWI_MMR

Address Type:

31

Read/Write

30

29

22 21 23

15

7

14

6

13

5

28

20

12

MREAD

4

27

19

DADR

11

3

• IADRSZ: Internal Device Address Size

Table 30-3.

IADRSZ[9:8]

1

1

0

0

0

1

0

1

No internal device address (Byte command protocol)

One-byte internal device address

Two-byte internal device address

Three-byte internal device address

26

18

10

2

• MREAD: Master Read Direction

0 = Master write direction.

1 = Master read direction.

• DADR: Device Address

The device address is used in Master Mode to access slave devices in read or write mode.

25

17

1

9

IADRSZ

8

0

24

16

286

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

30.6.4

TWI Internal Address Register

Register Name: TWI_IADR

Access Type:

31

Read/Write

30

29

23 22 21

28

20

IADR

15 14 13 12

IADR

7 6 5 4

IADR

• IADR: Internal Address

0, 1, 2 or 3 bytes depending on IADRSZ.

– Low significant byte address in 10-bit mode addresses.

27

19

11

3

26

18

10

2

25

17

9

1

24

16

8

0

287

6120D–ATARM–02-Feb-06

30.6.5

TWI Clock Waveform Generator Register

Register Name: TWI_CWGR

Access Type:

31

Read/Write

30

29

28

23

15

22

14

21

13

20

12

7 6 5 4

CHDIV

27

19

11

3

CLDIV

• CLDIV: Clock Low Divider

The SCL low period is defined as follows:

T low

=

( (

CLDIV

×

2

CKDIV

)

+

3

) ×

T

MCK

• CHDIV: Clock High Divider

The SCL high period is defined as follows:

T high

=

( (

CHDIV

×

2

CKDIV

)

+ 3

) ×

T

MCK

• CKDIV: Clock Divider

The CKDIV is used to increase both SCL high and low periods.

10

2

26

18

25

17

CKDIV

9

1

8

0

24

16

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30.6.6

TWI Status Register

Register Name: TWI_SR

Access Type:

31

Read-only

30

23

15

7

UNRE

22

14

6

OVRE

13

5

29

21

12

4

28

20

11

3

27

19

26

18

10

2

TXRDY

25

17

9

1

RXRDY

24

16

8

NACK

0

TXCOMP

• TXCOMP: Transmission Completed

0 = In master, during the length of the current frame. In slave, from START received to STOP received.

1 = When both holding and shift registers are empty and STOP condition has been sent (in Master), or when MSEN is set

(enable TWI).

• RXRDY: Receive Holding Register Ready

0 = No character has been received since the last TWI_RHR read operation.

1 = A byte has been received in theTWI_RHR since the last read.

• TXRDY: Transmit Holding Register Ready

0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.

1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).

• OVRE: Overrun Error

0 = TWI_RHR has not been loaded while RXRDY was set

1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.

• UNRE: Underrun Error

0 = No underrun error

1 = No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a

STOP bit in Master Mode. Reset by read in TWI_SR when TXCOMP is set.

• NACK: Not Acknowledged

0 = Each data byte has been correctly received by the far-end side TWI slave component.

1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.

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6120D–ATARM–02-Feb-06

30.6.7

TWI Interrupt Enable Register

Register Name: TWI_IER

Access Type:

31

Write-only

30

29

23

15

7

UNRE

22

14

6

OVRE

21

13

5

• TXCOMP: Transmission Completed

• RXRDY: Receive Holding Register Ready

• TXRDY: Transmit Holding Register Ready

• OVRE: Overrun Error

• UNRE: Underrun Error

• NACK: Not Acknowledge

0 = No effect.

1 = Enables the corresponding interrupt.

12

4

28

20

11

3

27

19

26

18

10

2

TXRDY

25

17

9

1

RXRDY

24

16

8

NACK

0

TXCOMP

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30.6.8

TWI Interrupt Disable Register

Register Name: TWI_IDR

Access Type:

31

Write-only

30

29

23

15

7

UNRE

22

14

6

OVRE

21

13

5

• TXCOMP: Transmission Completed

• RXRDY: Receive Holding Register Ready

• TXRDY: Transmit Holding Register Ready

• OVRE: Overrun Error

• UNRE: Underrun Error

• NACK: Not Acknowledge

0 = No effect.

1 = Disables the corresponding interrupt.

12

4

28

20

AT91SAM7X256/128 Preliminary

11

3

27

19

26

18

10

2

TXRDY

25

17

9

1

RXRDY

24

16

8

NACK

0

TXCOMP

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6120D–ATARM–02-Feb-06

30.6.9

TWI Interrupt Mask Register

Register Name: TWI_IMR

Access Type:

31

Read-only

30

29

23

15

7

UNRE

22

14

6

OVRE

21

13

5

• TXCOMP: Transmission Completed

• RXRDY: Receive Holding Register Ready

• TXRDY: Transmit Holding Register Ready

• OVRE: Overrun Error

• UNRE: Underrun Error

• NACK: Not Acknowledge

0 = The corresponding interrupt is disabled.

1 = The corresponding interrupt is enabled.

12

4

28

20

11

3

27

19

26

18

10

2

TXRDY

25

17

9

1

RXRDY

24

16

8

NACK

0

TXCOMP

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30.6.10

TWI Receive Holding Register

Register Name: TWI_RHR

Access Type:

31

Read-only

30

29

23

15

7

22

14

6

21

13

5

12

4

28

20

RXDATA

11

3

27

19

• RXDATA: Master or Slave Receive Holding Data

10

2

26

18

9

1

25

17

8

0

24

16

6120D–ATARM–02-Feb-06

293

30.6.11

TWI Transmit Holding Register

Register Name: TWI_THR

Access Type:

31

Read/Write

30

29

23

15

7

22

14

6

21

13

5

12

4

28

20

TXDATA

11

3

27

19

• TXDATA: Master or Slave Transmit Holding Data

10

2

26

18

9

1

25

17

8

0

24

16

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31. Universal Synchronous Asynchronous Receiver Transmitter (USART)

31.1

Overview

The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver timeout enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission.

The USART features three test modes: remote loopback, local loopback and automatic echo.

The USART supports specific operating modes providing interfaces on RS485 buses, with

ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports.

The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS.

The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor.

295

6120D–ATARM–02-Feb-06

31.2

Block Diagram

Figure 31-1. USART Block Diagram

Peripheral DMA

Controller

Channel Channel

USART

AIC USART

Interrupt

Receiver

Transmitter

PMC

MCK

DIV

MCK/DIV

SLCK

Modem

Signals

Control

APB

Baud Rate

Generator

User Interface

PIO

Controller

RXD

RTS

TXD

CTS

DTR

DSR

DCD

RI

SCK

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AT91SAM7X256/128 Preliminary

31.3

Application Block Diagram

Figure 31-2. Application Block Diagram

PPP

Modem

Driver

Serial

Driver

Field Bus

Driver

EMV

Driver

IrLAP

IrDA

Driver

USART

RS232

Drivers

Modem

PSTN

31.4

I/O Lines Description

Table 31-1.

I/O Line Description

Name Description

SCK

TXD

RXD

RI

DSR

DCD

DTR

CTS

RTS

Serial Clock

Transmit Serial Data

Receive Serial Data

Ring Indicator

Data Set Ready

Data Carrier Detect

Data Terminal Ready

Clear to Send

Request to Send

RS232

Drivers

RS485

Drivers

Serial

Port

Differential

Bus

Smart

Card

Slot

IrDA

Transceivers

Type

I/O

I/O

Input

Input

Input

Input

Output

Input

Output

Active Level

Low

Low

Low

Low

Low

Low

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6120D–ATARM–02-Feb-06

31.5

Product Dependencies

31.5.1

I/O Lines

The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller.

All the pins of the modems may or may not be implemented on the USART within a product.

Frequently, only the USART1 is fully equipped with all the modem signals. For the other

USARTs of the product not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART.

31.5.2

Power Management

The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off.

Configuring the USART does not require the USART clock to be enabled.

31.5.3

Interrupt

The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.

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31.6

Functional Description

The USART is capable of managing several types of serial synchronous or asynchronous communications.

It supports the following communication modes:

• 5- to 9-bit full-duplex asynchronous serial communication

– MSB- or LSB-first

– 1, 1.5 or 2 stop bits

– Parity even, odd, marked, space or none

– By 8 or by 16 over-sampling receiver frequency

– Optional hardware handshaking

– Optional modem signals management

– Optional break management

– Optional multidrop serial communication

• High-speed 5- to 9-bit full-duplex synchronous serial communication

– MSB- or LSB-first

– 1 or 2 stop bits

– Parity even, odd, marked, space or none

– By 8 or by 16 over-sampling frequency

– Optional hardware handshaking

– Optional modem signals management

– Optional break management

– Optional multidrop serial communication

• RS485 with driver control signal

• ISO7816, T0 or T1 protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

• InfraRed IrDA Modulation and Demodulation

• Test modes

– Remote loopback, local loopback, automatic echo

31.6.1

Baud Rate Generator

The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.

The Baud Rate Generator clock source can be selected by setting the USCLKS field in the

Mode Register (US_MR) between:

• the Master Clock MCK

• a division of the Master Clock, the divider being product dependent, but generally set to 8

• the external clock, available on the SCK pin

The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud

Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive.

299

6120D–ATARM–02-Feb-06

If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK.

Figure 31-3. Baud Rate Generator

USCLKS

CD

CD

MCK

MCK/DIV

SCK

Reserved

2

3

0

1

16-bit Counter

0

>1

1

0

0

OVER

FIDI

Sampling

Divider

0

SCK

SYNC

1

Baud Rate

Clock

1

SYNC

USCLKS = 3

Sampling

Clock

31.6.1.1

Baud Rate in Asynchronous Mode

If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).

The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR.

If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock.

The following formula performs the calculation of the Baud Rate.

Baudrate

=

(

SelectedClock

8 2 –

Over

)

CD

)

This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1.

Baud Rate Calculation Example

Table 31-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source

clock frequencies. This table also shows the actual resulting baud rate and the error.

Table 31-2.

Baud Rate Example (OVER = 0)

Source Clock

Expected Baud

Rate Calculation Result

MHz

3 686 400

4 915 200

5 000 000

7 372 800

Bit/s

38 400

38 400

38 400

38 400

6.00

8.00

8.14

12.00

CD

6

8

8

12

Actual Baud Rate

Bit/s

38 400.00

38 400.00

39 062.50

38 400.00

Error

0.00%

0.00%

1.70%

0.00%

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Table 31-2.

Baud Rate Example (OVER = 0) (Continued)

Source Clock

8 000 000

Expected Baud

Rate

38 400

Calculation Result

13.02

12 000 000

12 288 000

14 318 180

14 745 600

18 432 000

24 000 000

24 576 000

25 000 000

32 000 000

32 768 000

33 000 000

40 000 000

50 000 000

60 000 000

70 000 000

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

52.08

53.33

53.71

65.10

81.38

97.66

113.93

19.53

20.00

23.30

24.00

30.00

39.06

40.00

40.69

52

53

54

65

30

39

40

40

CD

13

20

20

23

24

81

98

114

Actual Baud Rate

38 461.54

37 500.00

38 400.00

38 908.10

38 400.00

38 400.00

38 461.54

38 400.00

38 109.76

38 461.54

38 641.51

38 194.44

38 461.54

38 580.25

38 265.31

38 377.19

0.00%

0.16%

0.00%

0.76%

0.16%

0.63%

0.54%

0.16%

Error

0.16%

2.40%

0.00%

1.31%

0.00%

0.47%

0.35%

0.06%

The baud rate is calculated with the following formula:

BaudRate

=

MCK

CD

×

16

The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.

Error

= 1 –

ExpectedBaudRate

ActualBaudRate

31.6.1.2

Fractional Baud Rate in Asynchronous Mode

The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART functional mode. The fractional Baud Rate is calculated using the following formula:

Baudrate

=

(

Over

)

CD

+

8

301

6120D–ATARM–02-Feb-06

The modified architecture is presented below:

Figure 31-4. Fractional Baud Rate Generator

FP

USCLKS

MCK

MCK/DIV

SCK

Reserved

2

3

0

1

31.6.1.3

31.6.1.4

CD

Modulus

Control

16-bit Counter

FP glitch-free

logic

0

CD

>1

1

0

1

0

SCK

FIDI

OVER

Sampling

Divider

0

SYNC

Baud Rate

Clock

1

Sampling

Clock

SYNC

USCLKS = 3

Baud Rate in Synchronous Mode

If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR.

BaudRate

=

CD

In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in

US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock.

When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.

Baud Rate in ISO 7816 Mode

The ISO7816 specification defines the bit rate with the following formula:

B

=

Di f

Fi

× where:

• B is the bit rate

• Di is the bit-rate adjustment factor

• Fi is the clock frequency division factor

• f is the ISO7816 clock frequency (Hz)

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Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 31-3 .

Table 31-3.

Binary and Decimal Values for D

DI field 0001 0010 0011

Di (decimal) 1 2 4

0100

8

0101

16

0110

32

1000

12

1001

20

Fi is a binary value encoded on a 4-bit field, named FI, as represented in

Table 31-4 .

Table 31-4.

Binary and Decimal Values for F

FI field 0000 0001 0010 0011

Fi (decimal 372 372 558 744

0100

1116

0101

1488

0110

1860

1001

512

1010

768

1011

1024

1100

1536

1101

2048

Table 31-5

shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock.

Table 31-5.

Possible Values for the Fi/Di Ratio

Fi/Di

1

372

372

558

558

774

744

1116

1116

32

12

20

8

16

2

4

186

93

46.5

23.25

11.62

31

18.6

279

139.5

69.75

34.87

17.43

46.5

372

186

93

46.5

23.25

62

558

279

139.5

69.75

34.87

93

1488

1488

744

372

186

93

46.5

124

1806

1860

930

465

232.5

116.2

58.13

155

512

512

256

128

64

32

16

42.66

96

48

24

64

768

768

384

192

1024

1024

512

256

128

64

32

85.33

1536

1536

768

384

192

96

48

128

27.9

37.2

55.8

74.4

93 25.6

38.4

51.2

76.8

102.4

If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the

Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud

Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR.

2048

2048

1024

512

256

128

64

170.6

This clock is then divided by the value programmed in the FI_DI_RATIO field in the

FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value.

The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1).

Figure 31-5

shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock.

303

6120D–ATARM–02-Feb-06

Figure 31-5. Elementary Time Unit (ETU)

FI_DI_RATIO

ISO7816 Clock Cycles

ISO7816 Clock on SCK

ISO7816 I/O Line on TXD

1 ETU

31.6.2

Receiver and Transmitter Control

After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.

After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the

Control Register (US_CR). However, the transmitter registers can be programmed before being enabled.

The Receiver and the Transmitter can be enabled together or independently.

At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register

(US_CR). The reset commands have the same effect as a hardware reset on the corresponding logic. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped.

The user can also independently disable the receiver or the transmitter by setting RXDIS and

TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the

USART waits until the end of reception of the current character, then the reception is stopped.

If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register

(US_THR). If a timeguard is programmed, it is handled normally.

31.6.3

31.6.3.1

Synchronous and Asynchronous Modes

Transmitter Operations

The transmitter performs the same in both synchronous and asynchronous operating modes

(SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock.

The number of data bits is selected by the CHRL field and the MODE9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field.

The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first.

The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only.

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Figure 31-6. Character Transmit

Example: 8-bit, Parity Enabled One Stop

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7 Parity

Bit

Stop

Bit

The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter

Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY raises.

Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in US_THR while TXRDY is active has no effect and the written character is lost.

Figure 31-7. Transmitter Status

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop Start

Bit Bit Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Write

US_THR

TXRDY

TXEMPTY

31.6.3.2

Manchester Encoder

When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or

10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder.

Figure 31-8 illustrates this coding scheme.

305

6120D–ATARM–02-Feb-06

306

Figure 31-8. NRZ to Manchester Encoding

1 0 1 NRZ encoded data

Manchester encoded data

Txd

1 0 0 0 1

The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to

15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE,

ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length.

Figure 31-9 illustrates and defines the

valid patterns. To improve flexibility, the encoding scheme can be configured using the

TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition.

Figure 31-9. Preamble Patterns, Default Polarity Assumed

Manchester encoded data

Txd

SFD DATA

8 bit width "ALL_ONE" Preamble

Manchester encoded data

Txd

SFD

DATA

8 bit width "ALL_ZERO" Preamble

Manchester encoded data

Txd

SFD

DATA

8 bit width "ZERO_ONE" Preamble

Manchester encoded data

Txd

SFD

DATA

8 bit width "ONE_ZERO" Preamble

A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined pattern that indicates the beginning of a valid data.

Figure 31-10

illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit,

(ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start

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Drift Compensation

AT91SAM7X256/128 Preliminary

of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the SYNC field in the US_MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the SYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in US_MR register must be set to 1. In this case, the SYNC field in US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is modified and includes sync information.

Figure 31-10. Start Frame Delimiter

Preamble Length is set to 0

SFD

Manchester encoded data

Txd

DATA

One bit start frame delimiter

SFD

Manchester encoded data

Txd

DATA

Manchester encoded data

Txd

SFD

Command Sync start frame delimiter

DATA

Data Sync start frame delimiter

Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken.

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6120D–ATARM–02-Feb-06

Figure 31-11. Bit Resynchronization

Oversampling

16x Clock

RXD

Sampling point

Synchro.

Error

Synchro.

Jump

Expected edge

Tolerance

Sync

Jump

Synchro.

Error

31.6.3.3

Asynchronous Receiver

If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR).

The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.

If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is

8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.

The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. The number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit.

Figure 31-12 and Figure 31-13

illustrate start detection and character reception when USART operates in asynchronous mode.

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31.6.3.4

AT91SAM7X256/128 Preliminary

Figure 31-12. Asynchronous Start Detection

Baud Rate

Clock

Sampling

Clock (x16)

RXD

Sampling

1 2 3 4 5 6 7 8

Start

Detection

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

D0

Sampling

RXD

Sampling

1 2 3 4 5 6 7 0 1 2 3 4

Start

Rejection

Figure 31-13. Asynchronous Character Reception

Example: 8-bit, Parity Enabled

Baud Rate

Clock

RXD

Start

Detection

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

D0 D1 D2 D3 D4 D5 D6 D7

Parity

Bit

Stop

Bit

Manchester Decoder

When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data.

An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in

US_MAN register. Depending on the desired application the preamble pattern matching is to

be defined via the RX_PP field in US_MAN. See Figure 31-9 for available preamble patterns.

Unlike preamble, the start frame delimiter is shared between Manchester Encoder and

Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is

sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 31-14 .. The

sample pulse rejection mechanism applies.

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Figure 31-14. Asynchronous Start Bit Detection

Sampling

Clock

(16 x)

Manchester encoded data

Txd

1 2 3 4

Start

Detection

The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time.

If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing.

Figure 31-15

illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is

cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. See Figure 31-16

for an example of Manchester error detection during data phase.

Figure 31-15. Preamble Pattern Mismatch

Preamble Mismatch

Manchester coding error

Preamble Mismatch invalid pattern

Manchester encoded data

Txd

SFD DATA

Preamble Length is set to 8

Figure 31-16. Manchester Error Flag

Preamble Length is set to 4

Manchester encoded data

Txd

SFD

Elementary character bit time

Entering USART character area sampling points

Preamble subpacket and Start Frame Delimiter were successfully decoded

Manchester

Coding Error detected

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31.6.3.5

When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register.

The decoder does not perform pipelining of incoming data stream. Thus when unipolar mode is enabled, it is highly recommended to assure consistency between start frame delimiter (or preamble) waveform and default active level. Example: when the line idles, the logic level is one; to synchronize and avoid confusion, a zero-to-one transition is mandatory.

Radio Interface: Manchester Encoded USART Application

This section describes low data rate RF transmission systems and their integration with a

Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes.

The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in

Figure 31-17

.

Figure 31-17. Manchester Encoded Characters RF Transmission

Fup frequency Carrier

Upstream

Emitter

Fdown frequency Carrier

Downstream

Receiver

ASK/FSK

Upstream Receiver

LNA

VCO

RF filter

Demod control bi-dir line

ASK/FSK downstream transmitter

PA

RF filter

Mod

VCO control

Serial

Configuration

Interface

Manchester decoder

Manchester encoder

USART

Receiver

USART

Emitter

The USART module is configured as a Manchester encoder/decoder. It is also highly recommended to use PIO interface to access RF receiver configuration registers. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the

RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See

Figure 31-18

for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the mod-

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6120D–ATARM–02-Feb-06

ulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See

Figure 31-19 .

From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration.

Figure 31-18. ASK Modulator Output

1

NRZ stream

Manchester encoded data default polarity unipolar output

ASK Modulator

Output

Uptstream Frequency F0

Txd

0 0 1

Figure 31-19. FSK Modulator Output

1

NRZ stream

Manchester encoded data default polarity unipolar output

FSK Modulator

Output

Uptstream Frequencies

[F0, F0+offset]

Txd

0 0 1

31.6.3.6

Synchronous Receiver

In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability.

Configuration fields and bits are the same as in asynchronous mode.

Figure 31-20 illustrates a character reception in synchronous mode.

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Figure 31-20. Synchronous Mode Character Reception

Example: 8-bit, Parity Enabled 1 Stop

Baud Rate

Clock

RXD

Sampling

Start D0 D1 D2 D3 D4 D5 D6 D7

Parity Bit

Stop Bit

31.6.3.7

Receiver Operations

When a character reception is completed, it is transferred to the Receive Holding Register

(US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.

Figure 31-21. Receiver Status

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop Start

Bit Bit Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

RSTSTA = 1

Write

US_CR

Read

US_RHR

RXRDY

OVRE

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31.6.3.8

Parity

The USART supports five parity modes selected by programming the PAR field in the Mode

Register (US_MR). The PAR field also enables the Multidrop mode, see

”Multidrop Mode” on page 315 . Even and odd parity bit generation and error detection are supported.

If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters.

The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error.

Table 31-6

shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even.

Table 31-6.

Parity Bit Examples

Character

A

Hexa

0x41

A

A

A

A

0x41

0x41

0x41

0x41

Binary

0100 0001

0100 0001

0100 0001

0100 0001

0100 0001

Parity Bit

1

0

1

0

None

Parity Mode

Odd

Even

Mark

Space

None

When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.

Figure 31-22

illustrates the parity bit status setting and clearing.

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Figure 31-22. Parity Error

Baud Rate

Clock

RXD

Write

US_CR

PARE

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Bad

Parity

Bit

Stop

Bit

RXRDY

RSTSTA = 1

31.6.3.9

Multidrop Mode

If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the

USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.

If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1.

To handle parity error, the PARE bit is cleared when the Control Register is written with the bit

RSTSTA at 1.

The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0.

31.6.3.10

Transmitter Timeguard

The timeguard feature enables the USART interface with slow remote devices.

The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit.

The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated.

Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits.

As illustrated in Figure 31-23 , the behavior of TXRDY and TXEMPTY status bits is modified by

the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted.

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Figure 31-23. Timeguard Operations

TG = 4

TG = 4

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Write

US_THR

TXRDY

TXEMPTY

31.6.3.11

Table 31-7

indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate.

Table 31-7.

Maximum Timeguard Length Depending on Baud Rate

Baud Rate Bit time

Bit/sec

1 200

µs

833

9 600 104

14400 69.4

19200

28800

33400

56000

57600

115200

17.4

8.7

52.1

34.7

29.9

17.9

Timeguard

ms

212.50

26.56

17.71

13.28

8.85

7.63

4.55

4.43

2.21

Receiver Time-out

The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the

Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame.

The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at

0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in

US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises.

The user can either:

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• Obtain an interrupt when a time-out is detected after having received at least one character. This is performed by writing the Control Register (US_CR) with the STTTO

(Start Time-out) bit at 1.

• Obtain a periodic interrupt while no character is received. This is performed by writing

US_CR with the RETTO (Reload and Start Time-out) bit at 1.

If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected.

If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.

Figure 31-24 shows the block diagram of the Receiver Time-out feature.

Figure 31-24. Receiver Time-out Block Diagram

Baud Rate

Clock

TO

16-bit

Value

STTTO

1

D Q

Clock 16-bit Time-out

Counter

= TIMEOUT

Load 0

Clear

Character

Received

RETTO

Table 31-8 gives the maximum time-out period for some standard baud rates.

Table 31-8.

Maximum Time-out Period

Baud Rate

bit/sec

Bit Time

µs

600

1 200

2 400

4 800

9 600

14400

19200

28800

33400

56000

57600

200000

1 667

833

417

208

104

69

52

35

30

18

17

5

Time-out

ms

109 225

54 613

27 306

13 653

6 827

4 551

3 413

2 276

1 962

1 170

1 138

328

317

31.6.3.12

Framing Error

The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.

A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The

FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.

Figure 31-25. Framing Error Status

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

RSTSTA = 1

Write

US_CR

FRAME

RXRDY

31.6.3.13

Transmit Break

The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed.

A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the

Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low.

Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed.

The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes.

The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed.

Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored.

A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored.

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After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period.

After holding the TXD line for this period, the transmitter resumes normal operations.

Figure 31-26 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STP-

BRK) commands on the TXD line.

Figure 31-26. Break Transmission

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

STTBRK = 1

Break Transmission

STPBRK = 1

End of Break

Write

US_CR

TXRDY

TXEMPTY

31.6.3.14

31.6.3.15

Receive Break

The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low.

When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1.

An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.

Hardware Handshaking

The USART features a hardware handshaking out-of-band flow control. The RTS and CTS

pins are used to connect with the remote device, as shown in Figure 31-27

.

Figure 31-27. Connection with a Remote Device for Hardware Handshaking

USART

TXD

RXD

CTS

RTS

Remote

Device

RXD

TXD

RTS

CTS

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Setting the USART to operate with hardware handshaking is performed by writing the

USART_MODE field in the Mode Register (US_MR) to the value 0x2.

The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case.

Figure 31-28

shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low.

Figure 31-28. Receiver Behavior when Operating with Hardware Handshaking

RXD

Write

US_CR

RXEN = 1

RXDIS = 1

RTS

RXBUFF

Figure 31-29 shows how the transmitter operates if hardware handshaking is enabled. The

CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls.

Figure 31-29. Transmitter Behavior when Operating with Hardware Handshaking

CTS

TXD

31.6.4

31.6.4.1

ISO7816 Mode

The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported.

Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the

Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T

= 1.

ISO7816 Mode Overview

The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is

determined by a division of the clock provided to the remote device (see ”Baud Rate Generator” on page 299 ).

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The USART connects to a smart card as shown in Figure 31-30 . The TXD line becomes bidi-

rectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock.

Figure 31-30. Connection of a Smart Card to the USART

USART

CLK

SCK

I/O

TXD

Smart

Card

31.6.4.2

When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit

LSB or MSB first.

The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results.

The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR).

Protocol T = 0

In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the

I/O line during the guard time.

If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in

Figure 31-31 .

If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as

shown in Figure 31-32

. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time.

When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status

Register (US_SR) so that the software can handle the error.

321

6120D–ATARM–02-Feb-06

Figure 31-31. T = 0 Protocol without Parity Error

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity

Bit

Guard

Time 1

Guard

Time 2

Next

Start

Bit

Figure 31-32. T = 0 Protocol with Parity Error

Baud Rate

Clock

I/O

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Error

Parity

Bit

Guard

Time 1

Guard

Time 2

Start

Bit

D0

Repetition

D1

Receive Error Counter

The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading

US_NER automatically clears the NB_ERRORS field.

Receive NACK Inhibit

The USART can also be configured to inhibit an error. This can be achieved by setting the

INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR).

The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1.

Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding

Register, as if no error occurred. However, the RXRDY bit does not raise.

Transmit Character Repetition

When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the

MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions.

If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION.

When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared.

The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1.

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AT91SAM7X256/128 Preliminary

Disable Successive Receive NACK

The receiver can limit the number of successive NACKs sent back to the remote transmitter.

This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as

MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set.

31.6.4.3

Protocol T = 1

When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR).

31.6.5

IrDA Mode

The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in

Figure 31-33 . The modulator and demodulator are compli-

ant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4

Kb/s to 115.2 Kb/s.

The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register

(US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated.

Figure 31-33. Connection to IrDA Transceivers

Receiver

USART

Demodulator

RXD RX

IrDA

Transceivers

TX

Transmitter

Modulator

TXD

The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed.

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6120D–ATARM–02-Feb-06

31.6.5.1

IrDA Modulation

For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration

are shown in Table 31-9 .

Table 31-9.

IrDA Pulse Duration

Baud Rate

2.4 Kb/s

9.6 Kb/s

19.2 Kb/s

38.4 Kb/s

57.6 Kb/s

115.2 Kb/s

Pulse Duration (3/16)

78.13 µs

19.53 µs

9.77 µs

4.88 µs

3.26 µs

1.63 µs

Figure 31-34 shows an example of character transmission.

Figure 31-34. IrDA Modulation

Transmitter

Output

Start

Bit

0

1

0

1

Data Bits

0

0

1 1

0

Stop

Bit

1

TXD

31.6.5.2

Bit Period

3

16

Bit Period

IrDA Baud Rate

Table 31-10 gives some examples of CD values, baud rate error and pulse duration. Note that

the requirement on the maximum acceptable error of ±1.87% must be met.

Table 31-10. IrDA Baud Rate Error

Peripheral Clock Baud Rate

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

115 200

115 200

115 200

115 200

57 600

57 600

57 600

57 600

38 400

38 400

18

22

4

22

CD

2

11

36

43

6

33

Baud Rate Error

0.00%

1.38%

1.25%

1.38%

0.00%

1.38%

1.25%

0.93%

0.00%

1.38%

Pulse Time

1.63

1.63

1.63

1.63

3.26

3.26

3.26

3.26

4.88

4.88

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AT91SAM7X256/128 Preliminary

Table 31-10. IrDA Baud Rate Error (Continued)

Peripheral Clock Baud Rate CD

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

38 400

38 400

19 200

19 200

19 200

19 200

9 600

9 600

9 600

9 600

2 400

2 400

2 400

107

130

24

130

53

65

12

65

213

260

96

521

853

Baud Rate Error

0.63%

0.16%

0.00%

0.16%

0.31%

0.16%

0.00%

0.16%

0.16%

0.16%

0.00%

0.03%

0.04%

Pulse Time

4.88

4.88

9.77

9.77

9.77

9.77

19.53

19.53

19.53

19.53

78.13

78.13

78.13

31.6.5.3

IrDA Demodulator

The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.

Figure 31-35 illustrates the operations of the IrDA demodulator.

Figure 31-35. IrDA Demodulator Operations

MCK

RXD

Counter

Value

Receiver

Input

6 5 4 3 2 6

Pulse

Rejected

6 5 4 3 2 1 0

Pulse

Accepted

Driven Low During 16 Baud Rate Clock Cycles

As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in

US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly.

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6120D–ATARM–02-Feb-06

31.6.6

RS485 Mode

The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in

Figure 31-36 .

Figure 31-36. Typical Connection to a RS485 Bus

USART

RXD

TXD

RTS

Differential

Bus

The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1.

The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion.

Figure 31-37 gives an example of the RTS waveform during a character transmis-

sion when the timeguard is enabled.

Figure 31-37. Example of RTS Drive with Timeguard

TG = 4

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Write

US_THR

TXRDY

TXEMPTY

RTS

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AT91SAM7X256/128 Preliminary

31.6.7

Modem Mode

The USART features modem mode, which enables control of the signals: DTR (Data Terminal

Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data

Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI.

Setting the USART in modem mode is performed by writing the USART_MODE field in the

Mode Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available.

Table 31-11

gives the correspondence of the USART signals with modem connection standards.

Table 31-11. Circuit References

USART Pin

TXD

V24

2

RTS

DTR

RXD

CTS

DSR

DCD

RI

6

8

22

3

5

4

20

104

106

107

109

125

CCITT

103

105

108.2

Direction

From terminal to modem

From terminal to modem

From terminal to modem

From modem to terminal

From terminal to modem

From terminal to modem

From terminal to modem

From terminal to modem

The control of the RTS and DTR output pins is performed by witting the Control Register

(US_CR) with the RTSDIS, RTSEN, DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable commands force the corresponding pin to its active level, i.e. low.

The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when

US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled.

31.6.8

31.6.8.1

Test Modes

The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally.

Normal Mode

Normal mode connects the RXD pin on the receiver input and the transmitter output on the

TXD pin.

327

6120D–ATARM–02-Feb-06

Figure 31-38. Normal Mode Configuration

Receiver

RXD

TXD

Transmitter

31.6.8.2

Automatic Echo Mode

Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin,

it is sent to the TXD pin, as shown in Figure 31-39

. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active.

Figure 31-39. Automatic Echo Mode Configuration

RXD

Receiver

TXD

Transmitter

31.6.8.3

Local Loopback Mode

Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in

Figure 31-40

. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state.

Figure 31-40. Local Loopback Mode Configuration

RXD

Receiver

TXD

Transmitter

1

31.6.8.4

Remote Loopback Mode

Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in

Figure 31-

41 . The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-

bit retransmission.

328

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AT91SAM7X256/128 Preliminary

Figure 31-41. Remote Loopback Mode Configuration

Receiver

1

RXD

TXD

Transmitter

6120D–ATARM–02-Feb-06

329

31.7

USART User Interface

Table 31-12. USART Memory Map

Offset Register

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020

0x0024

0x0028

0x2C - 0x3C

0x0040

0x0044

0x0048

0x004C

0x0050

0x5C - 0xFC

0x100 - 0x128

Control Register

Mode Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Channel Status Register

Receiver Holding Register

Transmitter Holding Register

Baud Rate Generator Register

Receiver Time-out Register

Transmitter Timeguard Register

Reserved

FI DI Ratio Register

Number of Errors Register

Reserved

IrDA Filter Register

Manchester Encoder Decoder Register

Reserved

Reserved for PDC Registers

Name

US_CR

US_MR

US_IER

US_IDR

US_IMR

US_CSR

US_RHR

US_THR

US_BRGR

US_RTOR

US_TTGR

US_FIDI

US_NER

US_IF

US_MAN

Write-only

Read/Write

Write-only

Write-only

Read-only

Read-only

Read-only

Write-only

Read/Write

Read/Write

Read/Write

Read/Write

Read-only

Read/Write

Read/Write

0x0

0x0

0x0

0x174

0x0

0x0

0x0

0x0

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AT91SAM7X256/128 Preliminary

31.7.1

Name:

USART Control Register

US_CR

Access Type:

31

Write-only

30

29

23

15

RETTO

7

TXDIS

22

14

RSTNACK

6

TXEN

21

13

RSTIT

5

RXDIS

28

20

12

SENDA

4

RXEN

27

19

RTSDIS

11

STTTO

3

RSTTX

26

18

RTSEN

10

STPBRK

2

RSTRX

25

17

DTRDIS

9

STTBRK

1

24

16

DTREN

8

RSTSTA

0

• RSTRX: Reset Receiver

0: No effect.

1: Resets the receiver.

• RSTTX: Reset Transmitter

0: No effect.

1: Resets the transmitter.

• RXEN: Receiver Enable

0: No effect.

1: Enables the receiver, if RXDIS is 0.

• RXDIS: Receiver Disable

0: No effect.

1: Disables the receiver.

• TXEN: Transmitter Enable

0: No effect.

1: Enables the transmitter if TXDIS is 0.

• TXDIS: Transmitter Disable

0: No effect.

1: Disables the transmitter.

• RSTSTA: Reset Status Bits

0: No effect.

1: Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR.

• STTBRK: Start Break

0: No effect.

1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted.

331

6120D–ATARM–02-Feb-06

• STPBRK: Stop Break

0: No effect.

1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.

No effect if no break is being transmitted.

• STTTO: Start Time-out

0: No effect

1: Starts waiting for a character before clocking the time-out counter.

• SENDA: Send Address

0: No effect.

1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.

• RSTIT: Reset Iterations

0: No effect.

1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.

• RSTNACK: Reset Non Acknowledge

0: No effect

1: Resets NACK in US_CSR.

• RETTO: Rearm Time-out

0: No effect

1: Restart Time-out

• DTREN: Data Terminal Ready Enable

0: No effect.

1: Drives the pin DTR at 0.

• DTRDIS: Data Terminal Ready Disable

0: No effect.

1: Drives the pin DTR to 1.

• RTSEN: Request to Send Enable

0: No effect.

1: Drives the pin RTS to 0.

• RTSDIS: Request to Send Disable

0: No effect.

1: Drives the pin RTS to 1.

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AT91SAM7X256/128 Preliminary

31.7.2

Name:

USART Mode Register

US_MR

Access Type:

31

ONEBIT

Read/Write

30

29

MAN

23

22

VAR_SYNC

15

CHMODE

14

7 6

CHRL

21

DSNACK

28

FILTER

20

INACK

13

NBSTOP

12

5 4

USCLKS

• USART_MODE

USART_MODE

0

0

0

0

0

1

0

0

0

1 1

• USCLKS: Clock Selection

1

1

0

1

1

0

0

0

0

0

1

1

0

0

0

1

1

0 x

0

0

1

1

USCLKS

0

1

0

1

Selected Clock

MCK

MCK / DIV

Reserved

SCK

1

0

1

0

0

1

0

1

0 x

27

19

OVER

11

3

26

18

CLKO

10

PAR

25

MAX_ITERATION

17

MODE9

9

2

USART_MODE

1

24

16

MSBF

8

SYNC

0

Mode of the USART

Normal

RS485

Hardware Handshaking

Modem

IS07816 Protocol: T = 0

Reserved

IS07816 Protocol: T = 1

Reserved

IrDA

Reserved

333

6120D–ATARM–02-Feb-06

• CHRL: Character Length.

1

1

0

0

CHRL

0

1

0

1

Character Length

5 bits

6 bits

7 bits

8 bits

• SYNC: Synchronous Mode Select

0: USART operates in Asynchronous Mode.

1: USART operates in Synchronous Mode.

• PAR: Parity Type

0

0

0

0

1

1

0

1

1

1

PAR

0

0

0

1

0

1 x x

• NBSTOP: Number of Stop Bits

Parity Type

Even parity

Odd parity

Parity forced to 0 (Space)

Parity forced to 1 (Mark)

No parity

Multidrop mode

0

0

1

NBSTOP

0

1

0

Asynchronous (SYNC = 0)

1 stop bit

1.5 stop bits

2 stop bits

1 1 Reserved

• CHMODE: Channel Mode

Synchronous (SYNC = 1)

1 stop bit

Reserved

2 stop bits

Reserved

0

0

1

1

CHMODE

0

1

0

1

Mode Description

Normal Mode

Automatic Echo. Receiver input is connected to the TXD pin.

Local Loopback. Transmitter output is connected to the Receiver Input..

Remote Loopback. RXD pin is internally connected to the TXD pin.

• MSBF: Bit Order

0: Least Significant Bit is sent/received first.

1: Most Significant Bit is sent/received first.

• MODE9: 9-bit Character Length

0: CHRL defines character length.

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AT91SAM7X256/128 Preliminary

1: 9-bit character length.

• CKLO: Clock Output Select

0: The USART does not drive the SCK pin.

1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.

• OVER: Oversampling Mode

0: 16x Oversampling.

1: 8x Oversampling.

• INACK: Inhibit Non Acknowledge

0: The NACK is generated.

1: The NACK is not generated.

• DSNACK: Disable Successive NACK

0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).

1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag

ITERATION is asserted.

• VAR_SYNC: Variable synchronization of command/data sync Start Frame Delimiter

0: User defined configuration of command or data sync field depending on SYNC value.

1: The sync field is updated when a character is written into US_THR register.

• MAX_ITERATION

Defines the maximum number of iterations in mode ISO7816, protocol T= 0.

• FILTER: Infrared Receive Line Filter

0: The USART does not filter the receive line.

1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).

• MAN: Manchester Encoder/Decoder Enable

0: Manchester Encoder/Decoder are disabled.

1: Manchester Encoder/Decoder are enabled.

• ONEBIT: Start Frame Delimiter selector

0: Start Frame delimiter is COMMAND or DATA SYNC.

1: Start Frame delimiter is One Bit.

335

6120D–ATARM–02-Feb-06

31.7.3

Name:

USART Interrupt Enable Register

US_IER

Access Type:

31

Write-only

30

29

23

15

22

14

21

13

NACK

28

20

MANE

12

RXBUFF

7

PARE

6

FRAME

5

OVRE

4

ENDTX

• RXRDY: RXRDY Interrupt Enable

• TXRDY: TXRDY Interrupt Enable

• RXBRK: Receiver Break Interrupt Enable

• ENDRX: End of Receive Transfer Interrupt Enable

• ENDTX: End of Transmit Interrupt Enable

• OVRE: Overrun Error Interrupt Enable

• FRAME: Framing Error Interrupt Enable

• PARE: Parity Error Interrupt Enable

• TIMEOUT: Time-out Interrupt Enable

• TXEMPTY: TXEMPTY Interrupt Enable

• ITERATION: Iteration Interrupt Enable

• TXBUFE: Buffer Empty Interrupt Enable

• RXBUFF: Buffer Full Interrupt Enable

• NACK: Non Acknowledge Interrupt Enable

• RIIC: Ring Indicator Input Change Enable

• DSRIC: Data Set Ready Input Change Enable

• DCDIC: Data Carrier Detect Input Change Interrupt Enable

• CTSIC: Clear to Send Input Change Interrupt Enable

• MANE: Manchester Error Interrupt Enable

0: No effect.

1: Enables the corresponding interrupt.

27

19

CTSIC

11

TXBUFE

3

ENDRX

26

18

DCDIC

10

ITERATION

2

RXBRK

25

17

DSRIC

9

TXEMPTY

1

TXRDY

24

16

RIIC

8

TIMEOUT

0

RXRDY

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AT91SAM7X256/128 Preliminary

31.7.4

Name:

USART Interrupt Disable Register

US_IDR

Access Type:

31

Write-only

30

29

23

15

22

14

21

13

NACK

28

20

MANE

12

RXBUFF

7

PARE

6

FRAME

5

OVRE

4

ENDTX

• RXRDY: RXRDY Interrupt Disable

• TXRDY: TXRDY Interrupt Disable

• RXBRK: Receiver Break Interrupt Disable

• ENDRX: End of Receive Transfer Interrupt Disable

• ENDTX: End of Transmit Interrupt Disable

• OVRE: Overrun Error Interrupt Disable

• FRAME: Framing Error Interrupt Disable

• PARE: Parity Error Interrupt Disable

• TIMEOUT: Time-out Interrupt Disable

• TXEMPTY: TXEMPTY Interrupt Disable

• ITERATION: Iteration Interrupt Disable

• TXBUFE: Buffer Empty Interrupt Disable

• RXBUFF: Buffer Full Interrupt Disable

• NACK: Non Acknowledge Interrupt Disable

• RIIC: Ring Indicator Input Change Disable

• DSRIC: Data Set Ready Input Change Disable

• DCDIC: Data Carrier Detect Input Change Interrupt Disable

• CTSIC: Clear to Send Input Change Interrupt Disable

• MANE: Manchester Error Interrupt Disable

0: No effect.

1: Disables the corresponding interrupt.

27

19

CTSIC

11

TXBUFE

3

ENDRX

26

18

DCDIC

10

ITERATION

2

RXBRK

25

17

DSRIC

9

TXEMPTY

1

TXRDY

24

16

RIIC

8

TIMEOUT

0

RXRDY

337

6120D–ATARM–02-Feb-06

31.7.5

Name:

USART Interrupt Mask Register

US_IMR

Access Type:

31

Read-only

30

29

23

15

7

PARE

22

14

6

FRAME

21

13

NACK

5

OVRE

28

20

MANE

12

RXBUFF

4

ENDTX

• RXRDY: RXRDY Interrupt Mask

• TXRDY: TXRDY Interrupt Mask

• RXBRK: Receiver Break Interrupt Mask

• ENDRX: End of Receive Transfer Interrupt Mask

• ENDTX: End of Transmit Interrupt Mask

• OVRE: Overrun Error Interrupt Mask

• FRAME: Framing Error Interrupt Mask

• PARE: Parity Error Interrupt Mask

• TIMEOUT: Time-out Interrupt Mask

• TXEMPTY: TXEMPTY Interrupt Mask

• ITERATION: Iteration Interrupt Mask

• TXBUFE: Buffer Empty Interrupt Mask

• RXBUFF: Buffer Full Interrupt Mask

• NACK: Non Acknowledge Interrupt Mask

• RIIC: Ring Indicator Input Change Mask

• DSRIC: Data Set Ready Input Change Mask

• DCDIC: Data Carrier Detect Input Change Interrupt Mask

• CTSIC: Clear to Send Input Change Interrupt Mask

• MANE: Manchester Error Interrupt Mask

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

27

19

CTSIC

11

TXBUFE

3

ENDRX

26

18

DCDIC

10

ITERATION

2

RXBRK

25

17

DSRIC

9

TXEMPTY

1

TXRDY

24

16

RIIC

8

TIMEOUT

0

RXRDY

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31.7.6

Name:

USART Channel Status Register

US_CSR

Access Type:

31

Read-only

30

29

23

CTS

15

7

PARE

22

DCD

14

6

FRAME

21

DSR

13

NACK

5

OVRE

28

27

20 19

RI CTSIC

12

RXBUFF

11

TXBUFE

4

ENDTX

3

ENDRX

26

18

DCDIC

10

ITERATION

2

RXBRK

25

17

DSRIC

9

TXEMPTY

1

TXRDY

24

MANERR

16

RIIC

8

TIMEOUT

0

RXRDY

• RXRDY: Receiver Ready

0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.

1: At least one complete character has been received and US_RHR has not yet been read.

• TXRDY: Transmitter Ready

0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.

1: There is no character in the US_THR.

• RXBRK: Break Received/End of Break

0: No Break received or End of Break detected since the last RSTSTA.

1: Break Received or End of Break detected since the last RSTSTA.

• ENDRX: End of Receiver Transfer

0: The End of Transfer signal from the Receive PDC channel is inactive.

1: The End of Transfer signal from the Receive PDC channel is active.

• ENDTX: End of Transmitter Transfer

0: The End of Transfer signal from the Transmit PDC channel is inactive.

1: The End of Transfer signal from the Transmit PDC channel is active.

• OVRE: Overrun Error

0: No overrun error has occurred since the last RSTSTA.

1: At least one overrun error has occurred since the last RSTSTA.

• FRAME: Framing Error

0: No stop bit has been detected low since the last RSTSTA.

1: At least one stop bit has been detected low since the last RSTSTA.

• PARE: Parity Error

0: No parity error has been detected since the last RSTSTA.

1: At least one parity error has been detected since the last RSTSTA.

339

6120D–ATARM–02-Feb-06

• TIMEOUT: Receiver Time-out

0: There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.

1: There has been a time-out since the last Start Time-out command.

• TXEMPTY: Transmitter Empty

0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.

1: There is at least one character in either US_THR or the Transmit Shift Register.

• ITERATION: Max number of Repetitions Reached

0: Maximum number of repetitions has not been reached since the last RSIT.

1: Maximum number of repetitions has been reached since the last RSIT.

• TXBUFE: Transmission Buffer Empty

0: The signal Buffer Empty from the Transmit PDC channel is inactive.

1: The signal Buffer Empty from the Transmit PDC channel is active.

• RXBUFF: Reception Buffer Full

0: The signal Buffer Full from the Receive PDC channel is inactive.

1: The signal Buffer Full from the Receive PDC channel is active.

• NACK: Non Acknowledge

0: No Non Acknowledge has not been detected since the last RSTNACK.

1: At least one Non Acknowledge has been detected since the last RSTNACK.

• RIIC: Ring Indicator Input Change Flag

0: No input change has been detected on the RI pin since the last read of US_CSR.

1: At least one input change has been detected on the RI pin since the last read of US_CSR.

• DSRIC: Data Set Ready Input Change Flag

0: No input change has been detected on the DSR pin since the last read of US_CSR.

1: At least one input change has been detected on the DSR pin since the last read of US_CSR.

• DCDIC: Data Carrier Detect Input Change Flag

0: No input change has been detected on the DCD pin since the last read of US_CSR.

1: At least one input change has been detected on the DCD pin since the last read of US_CSR.

• CTSIC: Clear to Send Input Change Flag

0: No input change has been detected on the CTS pin since the last read of US_CSR.

1: At least one input change has been detected on the CTS pin since the last read of US_CSR.

• RI: Image of RI Input

0: RI is at 0.

1: RI is at 1.

• DSR: Image of DSR Input

0: DSR is at 0

1: DSR is at 1.

• DCD: Image of DCD Input

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AT91SAM7X256/128 Preliminary

0: DCD is at 0.

1: DCD is at 1.

• CTS: Image of CTS Input

0: CTS is at 0.

1: CTS is at 1.

• MANERR: Manchester Error

0: No Manchester error has been detected since the last RSTSTA.

1: At least one Manchester error has been detected since the last RSTSTA.

6120D–ATARM–02-Feb-06

341

31.7.7

Name:

USART Receive Holding Register

US_RHR

Access Type:

31

Read-only

30

29

23

15

RXSYNH

7

22

14

6

21

13

5

28

20

12

4

RXCHR

11

3

27

19

• RXCHR: Received Character

Last character received if RXRDY is set.

• RXSYNH: Received Sync

0: Last Character received is a Data.

1: Last Character received is a Command.

26

18

10

2

31.7.8

Name:

USART Transmit Holding Register

US_THR

Access Type:

31

Write-only

30

29

23

15

TXSYNH

7

22

14

6

21

13

5

12

4

28

20

TXCHR

27

19

11

3

10

2

26

18

• TXCHR: Character to be Transmitted

Next character to be transmitted after the current character if TXRDY is not set.

• TXSYNH: Sync Field to be transmitted

0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.

1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.

9

1

25

17

25

17

9

1

24

16

8

RXCHR

0

24

16

8

TXCHR

0

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AT91SAM7X256/128 Preliminary

31.7.9

Name:

USART Baud Rate Generator Register

US_BRGR

Access Type:

31

Read/Write

30

29

28

23

15

22

14

21

13

20

12

27

19

11

26

18

10

CD

7 6 5 4 3 2

CD

• CD: Clock Divider

CD

0

OVER = 0

1 to 65535

Baud Rate =

Selected Clock/16/CD

• FP: Fractional Part

0: Fractional divider is disabled.

USART_MODE

ISO7816

SYNC = 0

SYNC = 1

OVER = 1

Baud Rate Clock Disabled

Baud Rate =

Selected Clock/8/CD

Baud Rate =

Selected Clock /CD

1 - 7: Baudrate resolution, defined by FP x 1/8.

25

17

FP

9

1

24

16

8

0

USART_MODE =

ISO7816

Baud Rate = Selected

Clock/CD/FI_DI_RATIO

343

6120D–ATARM–02-Feb-06

31.7.10

USART Receiver Time-out Register

Name:

US_RTOR

Access Type:

Read/Write

31

30

29

23

15

22

14

21

13

28

20

12

27

19

11

TO

7 6 5 4 3 2

TO

• TO: Time-out Value

0: The Receiver Time-out is disabled.

1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.

26

18

10

31.7.11

USART Transmitter Timeguard Register

Name:

US_TTGR

Access Type:

31

Read/Write

30

29

28

23

15

7

22

14

6

21

13

5

20

12

4

11

3

27

19

10

2

26

18

TG

• TG: Timeguard Value

0: The Transmitter Timeguard is disabled.

1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.

9

1

25

17

25

17

9

1

8

0

24

16

24

16

8

0

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31.7.12

USART FI DI RATIO Register

Name:

US_FIDI

Access Type:

Reset Value :

31

Read/Write

0x174

30

29

23

15

7

22

14

6

21

13

5

28

20

12

11

4

FI_DI_RATIO

3

27

19

26

18

10

2

25

17

9

FI_DI_RATIO

1

• FI_DI_RATIO: FI Over DI Ratio Value

0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.

1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.

24

16

8

0

31.7.13

USART Number of Errors Register

Name:

US_NER

Access Type:

31

Read-only

30

29

23

15

7

22

14

6

21

13

5

28

20

12

11

4

NB_ERRORS

3

27

19

10

2

26

18

9

1

25

17

• NB_ERRORS: Number of Errors

Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.

8

0

24

16

345

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31.7.14

USART Manchester Configuration Register

Name:

US_MAN

Access Type:

31

Read/Write

30

DRIFT

29

28

RX_MPOL

23

15

7

22

14

6

21

13

5

20

12

TX_MPOL

4

• TX_PL: Transmitter Preamble Length

0: The Transmitter Preamble pattern generation is disabled

1 - 15: The Preamble Length is TX_PL x Bit Period

• TX_PP: Transmitter Preamble Pattern

11

3

27

19

10

2

26

18

RX_PL

TX_PL

9

1

1

1

0

0

TX_PP

0

1

0

1

Preamble Pattern default polarity assumed (TX_MPOL field not set)

ALL_ONE

ALL_ZERO

ZERO_ONE

ONE_ZERO

• TX_MPOL: Transmitter Manchester Polarity

0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.

1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.

• RX_PL: Receiver Preamble Length

0: The receiver preamble pattern detection is disabled

1 - 15: The detected preamble length is RX_PL x Bit Period

• RX_PP: Receiver Preamble Pattern detected

0

0

1

1

RX_PP

0

1

0

1

Preamble Pattern default polarity assumed (RX_MPOL field not set)

ALL_ONE

ALL_ZERO

ZERO_ONE

ONE_ZERO

25

RX_PP

24

17 16

TX_PP

8

0

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AT91SAM7X256/128 Preliminary

• RX_MPOL: Receiver Manchester Polarity

0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.

1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.

• DRIFT: Drift compensation

0: The USART can not recover from an important clock drift

1: The USART can recover from clock drift. The 16X clock mode must be enabled.

6120D–ATARM–02-Feb-06

347

31.7.15

USART IrDA FILTER Register

Name:

US_IF

Access Type:

31

Read/Write

30

29

23

15

7

22

14

6

21

13

5

• IRDA_FILTER: IrDA Filter

Sets the filter of the IrDA demodulator.

28

20

12

4

IRDA_FILTER

3

27

19

11

26

18

10

2

25

17

9

1

24

16

8

0

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AT91SAM7X256/128 Preliminary

32. Synchronous Serial Controller (SSC)

32.1

Overview

The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.

The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the

TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal.

The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention.

Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following:

• CODEC’s in master or slave mode

• DAC through dedicated serial interface, particularly I2S

• Magnetic card reader

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6120D–ATARM–02-Feb-06

32.2

Block Diagram

Figure 32-1. Block Diagram

ASB

APB Bridge

PDC

APB

PMC

MCK

SSC Interface

PIO

Interrupt Control

SSC Interrupt

32.3

Application Block Diagram

Figure 32-2. Application Block Diagram

OS or RTOS Driver

Serial AUDIO Codec

Power

Management

Interrupt

Management

Test

Management

SSC

Time Slot

Management

Frame

Management

Line Interface

RF

RK

RD

TF

TK

TD

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AT91SAM7X256/128 Preliminary

32.4

Pin Name List

Table 32-1.

I/O Lines Description

Pin Name Pin Description

RF

RK

RD

TF

TK

TD

Receiver Frame Synchro

Receiver Clock

Receiver Data

Transmitter Frame Synchro

Transmitter Clock

Transmitter Data

Type

Input/Output

Input/Output

Input

Input/Output

Input/Output

Output

32.5

Product Dependencies

32.5.1

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.

Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode.

Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode.

32.5.2

32.5.3

Power Management

The SSC is not continuously clocked. The SSC interface may be clocked through the Power

Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock.

Interrupt

The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).

Handling interrupts requires programming the AIC before configuring the SSC.

All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register.

32.6

Functional Description

This chapter contains the functional description of the following: SSC Functional Block, Clock

Management, Data format, Start, Transmitter, Receiver and Frame Sync.

The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2.

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6120D–ATARM–02-Feb-06

Figure 32-3. SSC Functional Block Diagram

MCK

Clock

Divider

APB

Transmitter

Clock Output

Controller

TK Input

Transmit Clock

Controller

TX clock

Frame Sync

Controller

RX clock

TF

RF

Start

Selector

TX PDC

Transmit Shift Register

Transmit Holding

Register

Load Shift

Transmit Sync

Holding Register

TK

TF

TD

User

Interface

PDC

Interrupt Control

Receiver

Clock Output

Controller

RK Input

Receive Clock

Controller

RX Clock

Frame Sync

Controller

TX Clock

RF

TF

Start

Selector

Receive Shift Register

RX PDC

Receive Holding

Register

Load Shift

Receive Sync

Holding Register

RK

RF

RD

AIC

32.6.1

Clock Management

The transmitter clock can be generated by:

• an external clock received on the TK I/O pad

• the receiver clock

• the internal clock divider

The receiver clock can be generated by:

• an external clock received on the RK I/O pad

• the transmitter clock

• the internal clock divider

Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.

This allows the SSC to support many Master and Slave Mode data transfers.

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32.6.1.1

Clock Divider

Figure 32-4. Divided Clock Block Diagram

MCK

/ 2

Clock Divider

SSC_CMR

12-bit Counter

Divided Clock

The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive.

When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of

Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the

Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd.

Figure 32-5. Divided Clock Generation

Master Clock

Divided Clock

DIV = 1

Divided Clock Frequency = MCK/2

Master Clock

Divided Clock

DIV = 3

Divided Clock Frequency = MCK/6

32.6.1.2

Table 32-2.

Maximum

MCK / 2

Minimum

MCK / 8190

Transmitter Clock Management

The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in

SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR.

The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select

353

6120D–ATARM–02-Feb-06

TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results.

Figure 32-6. Transmitter Clock Management

SSC_TCMR.CKS

TK

SSC_TCMR.CKO

Receiver Clock

Divider Clock

TK

0 Transmitter Clock

1

SSC_TCMR.CKI

32.6.1.3

Receiver Clock Management

The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in

SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR.

The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion

(CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results.

Figure 32-7. Receiver Clock Management

SSC_RCMR.CKS

SSC_RCMR.CKO

RK

Transmitter Clock

Divider Clock

0 Receiver Clock

1

SSC_RCMR.CKI

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AT91SAM7X256/128 Preliminary

32.6.1.4

Serial Clock Ratio Considerations

The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is:

– Master Clock divided by 2 if Receiver Frame Synchro is input

– Master Clock divided by 3 if Receiver Frame Synchro is output

In addition, the maximum clock speed allowed on the TK pin is:

– Master Clock divided by 6 if Transmit Frame Synchro is input

– Master Clock divided by 2 if Transmit Frame Synchro is output

32.6.2

Transmitter Operations

A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission.

The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See

“Start” on page 356.

The frame synchronization is configured setting the Transmit Frame Mode Register

(SSC_TFMR). See “Frame Sync” on page 358.

To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the

SSC_THR register then transferred to the shift register according to the data format selected.

When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register.

Figure 32-8. Transmitter Block Diagram

SSC_CR.TXEN

SSC_SR.TXEN

SSC_CR.TXDIS

SSC_TFMR.DATDEF

RF

TF

Transmitter Clock

Start

Selector

SSC_TFMR.MSBF

Transmit Shift Register

1

0

SSC_TFMR.FSDEN

SSC_TCMR.STTDLY

0 1

SSC_TFMR.DATLEN

SSC_THR SSC_TSHR

SSC_TCMR.STTDLY

SSC_TFMR.FSDEN

SSC_TFMR.DATNB

SSC_TFMR.FSLEN

TD

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6120D–ATARM–02-Feb-06

32.6.3

Receiver Operations

A received frame is triggered by a start event and can be followed by synchronization data before data transmission.

The start event is configured setting the Receive Clock Mode Register (SSC_RCMR).

See

“Start” on page 356.

The frame synchronization is configured setting the Receive Frame Mode Register

(SSC_RFMR).

See “Frame Sync” on page 358.

The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected.

When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register.

If another transfer occurs before read of the RHR register, the status flag OVERUN is set in

SSC_SR and the receiver shift register is transferred in the RHR register.

Figure 32-9. Receiver Block Diagram

SSC_CR.RXEN

SSC_SR.RXEN

SSC_CR.RXDIS

RF TF

Receiver Clock

Start

Selector

SSC_RFMR.MSBF

SSC_RFMR.DATNB

Receive Shift Register

RD

32.6.4

SSC_RCMR.STTDLY

Start

SSC_RSHR SSC_RHR

SSC_RFMR.FSLEN

SSC_RFMR.DATLEN

The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the

Receive Start Selection (START) field of SSC_RCMR.

Under the following conditions the start event is independently programmable:

• Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled.

• Synchronously with the transmitter/receiver

• On detection of a falling/rising edge on TF/RF

• On detection of a low level/high level on TF/RF

• On detection of a level change or an edge on TF/RF

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AT91SAM7X256/128 Preliminary

A start can be programmed in the same manner on either side of the Transmit/Receive Clock

Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive).

Moreover, the Receiver can start when data is detected in the bit stream with the Compare

Functions.

Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame

Mode Register (TFMR/RFMR).

Figure 32-10. Transmit Start Mode

TK

TF

(Input)

Start = Low Level on TF

TD

(Output)

Start = Falling Edge on TF

TD

(Output)

Start = High Level on TF

TD

(Output)

Start = Rising Edge on TF TD

(Output)

Start = Level Change on TF

TD

(Output)

Start = Any Edge on TF

TD

(Output)

X

X

X

X

BO

X

BO

X

BO

B1

BO

B1

B1

BO

B1

BO

BO

B1

BO

B1

B1

STTDLY

STTDLY

STTDLY

STTDLY

B1

STTDLY

STTDLY

Figure 32-11. Receive Pulse/Edge Start Modes

RK

RF

(Input)

Start = Low Level on RF

RD

(Input)

Start = Falling Edge on RF

RD

(Input)

Start = High Level on RF

Start = Rising Edge on RF

RD

(Input)

RD

(Input)

Start = Level Change on RF

RD

(Input)

Start = Any Edge on RF

RD

(Input)

X BO B1

STTDLY

X BO B1

STTDLY

X

X

X

BO B1

STTDLY

BO

BO B1

B1 BO

STTDLY

B1

STTDLY

X BO B1 BO B1

STTDLY

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6120D–ATARM–02-Feb-06

32.6.5

32.6.5.1

32.6.5.2

Frame Sync

The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode

Register (SSC_TFMR) are used to select the required waveform.

• Programmable low or high levels during data transfer are supported.

• Programmable high levels before the start of data transfers or toggling are also supported.

If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and

SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time.

The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.

Frame Sync Data

Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.

During the Frame Sync signal, the Receiver can sample the RD line and store the data in the

Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR.

Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift

Register.

The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync

Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the

Transmit Register, then shifted out.

Frame Sync Edge Detection

T h e F r a m e S y n c E d g e d e t e c t i o n i s p r o g r a m m e d b y t h e F S E D G E f i e l d i n

SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF).

32.6.6

Receive Compare Modes

Figure 32-12. Receive Compare Modes

RK

RD

(Input)

B0 B1 B2 CMP0 CMP1 CMP2 CMP3

Start

FSLEN

Up to 16 Bits

(4 in This Example)

Ignored

STDLY DATLEN

358

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

32.6.6.1

32.6.7

Compare Functions

Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last FSLEN bits received at the FSLEN lower bit of the data contained in the

Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in

SSC_RCMR.

Data Format

The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register

(SSC_RFMR). In either case, the user can independently select:

• the event that starts the data transfer (START)

• the delay in number of bit periods between the start event and the first data bit (

STTDLY

)

• the length of the data (DATLEN)

• the number of data to be transferred for each start event (DATNB).

• the length of synchronization transferred for each start event (FSLEN)

• the bit sense: most or lowest significant bit first (MSBF).

Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync

Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR.

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6120D–ATARM–02-Feb-06

Table 32-3.

Data Frame Registers

Transmitter Receiver

SSC_TFMR

SSC_TFMR

SSC_TFMR

SSC_TFMR

SSC_TFMR

SSC_TFMR

SSC_TCMR

SSC_TCMR

SSC_RFMR

SSC_RFMR

SSC_RFMR

SSC_RFMR

SSC_RCMR

SSC_RCMR

Field

DATLEN

DATNB

MSBF

FSLEN

DATDEF

FSDEN

PERIOD

STTDLY

Length

Up to 32

Up to 16

Up to 16

0 or 1

Up to 512

Up to 255

Comment

Size of word

Number of words transmitted in frame

Most significant bit first

Size of Synchro data register

Data default value ended

Enable send SSC_TSHR

Frame size

Size of transmit start delay

Figure 32-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes

Start

PERIOD

TF/RF

(1)

FSLEN

TD

(If FSDEN = 1)

Sync Data Default

From SSC_TSHR FromDATDEF

TD

(If FSDEN = 0)

RD

Default

From DATDEF

Ignored

Sync Data

To SSC_RSHR

Data

From SSC_THR

Data

From SSC_THR

Data

To SSC_RHR

STTDLY DATLEN

Start

Data

From SSC_THR

Data

From SSC_THR

Data

To SSC_RHR

DATLEN

Default

FromDATDEF

Sync Data

Default

From DATDEF

Ignored

Sync Data

DATNB

Note: 1. Example of input on falling edge of TF/RF.

360

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6120D–ATARM–02-Feb-06

Figure 32-14. Transmit Frame Format in Continuous Mode

Start

AT91SAM7X256/128 Preliminary

TD

Data

From SSC_THR

DATLEN

Data

From SSC_THR

DATLEN

Default

Start: 1. TXEMPTY set to 1

2. Write into the SSC_THR

Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode.

Figure 32-15. Receive Frame Format in Continuous Mode

Start = Enable Receiver

32.6.8

Loop Mode

RD

Data

To SSC_RHR

DATLEN

Note: 1. STTDLY is set to 0.

Data

To SSC_RHR

DATLEN

The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.

32.6.9

Interrupt

Most bits in SSC_SR have a corresponding bit in interrupt management registers.

The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable

Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC.

361

6120D–ATARM–02-Feb-06

Figure 32-16. Interrupt Block Diagram

SSC_IMR

SSC_IER

Set

SSC_IDR

Clear

PDC

TXBUFE

ENDTX

Transmitter

TXRDY

TXEMPTY

TXSYNC

RXBUFF

ENDRX

Interrupt

Control

SSC Interrupt

Receiver

RXRDY

OVRUN

RXSYNC

32.7

SSC Application Examples

The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here.

Figure 32-17. Audio Application Block Diagram

Clock SCK

TK

Word Select WS

TF

Data SD

TD

SSC

RD

Clock SCK

RF

Word Select WS

RK

Data SD

I2S

RECEIVER

MSB

Left Channel

LSB

MSB

Right Channel

362

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6120D–ATARM–02-Feb-06

Figure 32-18. Codec Application Block Diagram

Serial Data Clock (SCLK)

TK

Frame sync (FSYNC)

TF

Serial Data Out

TD

SSC

Serial Data In

RD

RF

RK

Serial Data Clock (SCLK)

Frame sync (FSYNC)

AT91SAM7X256/128 Preliminary

CODEC

First Time Slot

Dstart Dend

Serial Data Out

Serial Data In

Figure 32-19. Time Slot Application Block Diagram

SCLK

TK

FSYNC

TF

Data Out

TD

SSC

Data in

RD

RF

RK

CODEC

First

Time Slot

CODEC

Second

Time Slot

Serial Data Clock (SCLK)

Frame sync (FSYNC)

Serial Data Out

Serial Data in

First Time Slot

Dstart

Second Time Slot

Dend

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AT91SAM7X256/128 Preliminary

32.8

Synchronous Serial Controller (SSC) User Interface

Table 32-4.

Register Mapping

Offset

0x0

0x4

Register

Control Register

Clock Mode Register

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x8

0xC

0x10

0x14

0x18

0x1C

0x20

0x24

Reserved

Reserved

Receive Clock Mode Register

Receive Frame Mode Register

Transmit Clock Mode Register

Transmit Frame Mode Register

Receive Holding Register

Transmit Holding Register

Reserved

Reserved

Receive Sync. Holding Register

Transmit Sync. Holding Register

Receive Compare 0 Register

Receive Compare 1 Register

Status Register

Interrupt Enable Register

0x48

0x4C

Interrupt Disable Register

Interrupt Mask Register

0x50-0xFC Reserved

0x100- 0x124 Reserved for Peripheral Data Controller (PDC)

Register Name

SSC_CR

SSC_CMR

SSC_RCMR

SSC_RFMR

SSC_TCMR

SSC_TFMR

SSC_RHR

SSC_THR

SSC_RSHR

SSC_TSHR

SSC_RC0R

SSC_RC1R

SSC_SR

SSC_IER

SSC_IDR

SSC_IMR

Access

Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read

Write

Read

Read/Write

Read/Write

Read/Write

Read

Write

Write

Read

0x0

0x0

0x0

0x0

0x0

Reset

0x0

0x0

0x0

0x0

0x0

0x000000CC

0x0

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32.8.1

SSC Control Register

Name:

Access Type:

SSC_CR

Write-only

31

30

29

23

15

SWRST

22

14

21

13

28

20

12

27

19

11

26

18

10

25

17

9

TXDIS

7

6

5

4

3

2

1

RXDIS

0

RXEN

• RXEN: Receive Enable

0: No effect.

1: Enables Receive if RXDIS is not set.

• RXDIS: Receive Disable

0: No effect.

1: Disables Receive. If a character is currently being received, disables at end of current character reception.

• TXEN: Transmit Enable

0: No effect.

1: Enables Transmit if TXDIS is not set.

• TXDIS: Transmit Disable

0: No effect.

1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission.

• SWRST: Software Reset

0: No effect.

1: Performs a software reset. Has priority on any other bit in SSC_CR.

24

16

8

TXEN

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AT91SAM7X256/128 Preliminary

32.8.2

SSC Clock Mode Register

Name:

Access Type:

SSC_CMR

Read/Write

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

26

18

10

25

17

9

24

16

8

DIV

7 6 5 4 3 2 1 0

DIV

• DIV: Clock Divider

0: The Clock Divider is not active.

Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.

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32.8.3

SSC Receive Clock Mode Register

Name:

Access Type:

SSC_RCMR

Read/Write

31 30 29

23

15

22

14

21

13

28

PERIOD

27

20

STDDLY

19

11 12

STOP

4 3

CKO

7

CKG

6 5

CKI

• CKS: Receive Clock Selection

CKS

0x0

0x1

0x2

0x3

Selected Receive Clock

Divided Clock

TK Clock signal

RK pin

Reserved

26

18

10

2

START

25

17

9

1

CKS

24

16

8

0

• CKO: Receive Clock Output Mode Selection

CKO Receive Clock Output Mode

0x0

0x1

0x2

0x3-0x7

None

Continuous Receive Clock

Receive Clock only during data transfers

Reserved

RK pin

Input-only

Output

Output

• CKI: Receive Clock Inversion

0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge.

1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge.

CKI affects only the Receive Clock and not the output clock signal.

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AT91SAM7X256/128 Preliminary

• CKG: Receive Clock Gating Selection

CKG

0x0

0x1

0x2

0x3

Receive Clock Gating

None, continuous clock

Receive Clock enabled only if RF Low

Receive Clock enabled only if RF High

Reserved

• START: Receive Start Selection

START

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9-0xF

Receive Start

Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.

Transmit start

Detection of a low level on RF signal

Detection of a high level on RF signal

Detection of a falling edge on RF signal

Detection of a rising edge on RF signal

Detection of any level change on RF signal

Detection of any edge on RF signal

Compare 0

Reserved

• STOP: Receive Stop Selection

0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0.

1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.

• STTDLY: Receive Start Delay

If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.

When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.

Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG

(Receive Sync Data) reception.

• PERIOD: Receive Period Divider Selection

This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no

PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.

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32.8.4

SSC Receive Frame Mode Register

Name:

Access Type:

SSC_RFMR

Read/Write

31

30

29

22 23

15

14

21

FSOS

13

28

20

27

19

26

18

FSLEN

25

17

24

FSEDGE

16

12

11 10

DATNB

9 8

7

MSBF

6

5

LOOP

4 3 2

DATLEN

1 0

• DATLEN: Data Length

0: Forbidden value (1-bit data length not supported).

Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the

PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and

15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.

• LOOP: Loop Mode

0: Normal operating mode.

1: RD is driven by TD, RF is driven by TF and TK drives RK.

• MSBF: Most Significant Bit First

0: The lowest significant bit of the data register is sampled first in the bit stream.

1: The most significant bit of the data register is sampled first in the bit stream.

• DATNB: Data Number per Frame

This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).

• FSLEN: Receive Frame Sync Length

This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive

Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register.

Pulse length is equal to (FSLEN + 1) Receive Clock periods. Thus, if FSLEN is 0, the Receive Frame Sync signal is generated during one Receive Clock period.

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• FSOS: Receive Frame Sync Output Selection

FSOS

0x0

0x1

0x2

0x3

0x4

0x5

0x6-0x7

Selected Receive Frame Sync Signal

None

Negative Pulse

Positive Pulse

Driven Low during data transfer

Driven High during data transfer

Toggling at each start of data transfer

Reserved

• FSEDGE: Frame Sync Edge Detection

Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.

FSEDGE Frame Sync Edge Detection

0x0 Positive Edge Detection

0x1 Negative Edge Detection

RF Pin

Input-only

Output

Output

Output

Output

Output

Undefined

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32.8.5

SSC Transmit Clock Mode Register

Name:

Access Type:

SSC_TCMR

Read/Write

31 30 29

23

15

22

14

21

13

7

CKG

6 5

CKI

• CKS: Transmit Clock Selection

CKS Selected Transmit Clock

0x0

0x1

0x2

0x3

Divided Clock

RK Clock signal

TK Pin

Reserved

4

28

PERIOD

27

20

STTDLY

19

12

11

3

CKO

26

18

10

2

START

25

17

9

1

CKS

24

16

8

0

• CKO: Transmit Clock Output Mode Selection

CKO Transmit Clock Output Mode

0x0

0x1

0x2

0x3-0x7

None

Continuous Transmit Clock

Transmit Clock only during data transfers

Reserved

TK pin

Input-only

Output

Output

• CKI: Transmit Clock Inversion

0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge.

1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge.

CKI affects only the Transmit Clock and not the output clock signal.

• CKG: Transmit Clock Gating Selection

CKG

0x0

0x1

0x2

0x3

Transmit Clock Gating

None, continuous clock

Transmit Clock enabled only if TF Low

Transmit Clock enabled only if TF High

Reserved

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• START: Transmit Start Selection

START Transmit Start

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8 - 0xF

Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.

Receive start

Detection of a low level on TF signal

Detection of a high level on TF signal

Detection of a falling edge on TF signal

Detection of a rising edge on TF signal

Detection of any level change on TF signal

Detection of any edge on TF signal

Reserved

• STTDLY: Transmit Start Delay

If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.

Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG.

• PERIOD: Transmit Period Divider Selection

This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.

372

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32.8.6

SSC Transmit Frame Mode Register

Name:

Access Type:

SSC_TFMR

Read/Write

31

30

29

28

22 20 23

FSDEN

15

14

21

FSOS

13

12

27

19

11

26

18

10

FSLEN

25

17

9

24

FSEDGE

16

8

DATNB

7

MSBF

6

5

DATDEF

4 3 2

DATLEN

1 0

• DATLEN: Data Length

0: Forbidden value (1-bit data length not supported).

Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the

PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15

(included), half-words are transferred, and for any other value, 32-bit words are transferred.

• DATDEF: Data Default Value

This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the

PIO Controller, the pin is enabled only if the SCC TD output is 1.

• MSBF: Most Significant Bit First

0: The lowest significant bit of the data register is shifted out first in the bit stream.

1: The most significant bit of the data register is shifted out first in the bit stream.

• DATNB: Data Number per frame

This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).

• FSLEN: Transmit Frame Sync Length

This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync

Data Register if FSDEN is 1.

Pulse length is equal to (FSLEN + 1) Transmit Clock periods, i.e., the pulse length can range from 1 to 16 Transmit Clock periods. If FSLEN is 0, the Transmit Frame Sync signal is generated during one Transmit Clock period.

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• FSOS: Transmit Frame Sync Output Selection

FSOS

0x0

0x1

0x2

0x3

0x4

0x5

0x6-0x7

Selected Transmit Frame Sync Signal

None

Negative Pulse

Positive Pulse

Driven Low during data transfer

Driven High during data transfer

Toggling at each start of data transfer

Reserved

• FSDEN: Frame Sync Data Enable

0: The TD line is driven with the default value during the Transmit Frame Sync signal.

1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.

• FSEDGE: Frame Sync Edge Detection

Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).

FSEDGE Frame Sync Edge Detection

0x0 Positive Edge Detection

0x1 Negative Edge Detection

TF Pin

Input-only

Output

Output

Output

Output

Output

Undefined

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32.8.7

SSC Receive Holding Register

Name:

Access Type:

SSC_RHR

Read-only

31 30 29 28 27 26

RDAT

23 22 21 20 19 18

RDAT

15 14 13 12 11 10

RDAT

7 6 5 4 3 2

RDAT

• RDAT: Receive Data

Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.

25

17

9

1

24

16

8

0

32.8.8

Name:

SSC Transmit Holding Register

Access Type:

SSC_THR

Write-only

31 30 29 28 27 26

TDAT

23 22 21 20 19 18

TDAT

15 14 13 12 11 10

TDAT

7 6 5 4 3 2

TDAT

• TDAT: Transmit Data

Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.

25

17

9

1

24

16

8

0

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32.8.9

SSC Receive Synchronization Holding Register

Name:

Access Type:

SSC_RSHR

Read-only

31

30

29

28

23

15

22

14

21

13

20

12

RSDAT

27

19

11

7 6 5 4 3

RSDAT

• RSDAT: Receive Synchronization Data

26

18

10

2

25

17

9

1

24

16

8

0

32.8.10

SSC Transmit Synchronization Holding Register

Name:

SSC_TSHR

Access Type:

Read/Write

31

30

29

28

23

15

22

14

21

13

20

12

TSDAT

27

19

11

7 6 5 4 3

TSDAT

• TSDAT: Transmit Synchronization Data

26

18

10

2

25

17

9

1

24

16

8

0

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32.8.11

SSC Receive Compare 0 Register

Name:

Access Type:

SSC_RC0R

Read/Write

31

30

29

23

15

22

14

21

13

7 6 5

28

20

12

CP0

4

CP0

27

19

11

3

• CP0: Receive Compare Data 0

26

18

10

2

25

17

9

1

24

16

8

0

6120D–ATARM–02-Feb-06

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32.8.12

SSC Receive Compare 1 Register

Name:

Access Type:

SSC_RC1R

Read/Write

31

30

29

23

15

22

14

21

13

7 6 5

28

20

12

CP1

4

CP1

27

19

11

3

• CP1: Receive Compare Data 1

26

18

10

2

25

17

9

1

24

16

8

0

6120D–ATARM–02-Feb-06

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AT91SAM7X256/128 Preliminary

32.8.13

SSC Status Register

Name:

Access Type:

SSC_SR

Read-only

31

30

29

23

15

22

14

21

13

28

20

12

27

19

11

RXSYN

26

18

10

TXSYN

25

17

RXEN

9

CP1

24

16

TXEN

8

CP0

7

RXBUFF

6

ENDRX

5

OVRUN

4

RXRDY

3

TXBUFE

2

ENDTX

1

TXEMPTY

0

TXRDY

• TXRDY: Transmit Ready

0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).

1: SSC_THR is empty.

• TXEMPTY: Transmit Empty

0: Data remains in SSC_THR or is currently transmitted from TSR.

1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.

• ENDTX: End of Transmission

0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.

1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.

• TXBUFE: Transmit Buffer Empty

0: SSC_TCR or SSC_TNCR have a value other than 0.

1: Both SSC_TCR and SSC_TNCR have a value of 0.

• RXRDY: Receive Ready

0: SSC_RHR is empty.

1: Data has been received and loaded in SSC_RHR.

• OVRUN: Receive Overrun

0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.

1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.

• ENDRX: End of Reception

0: Data is written on the Receive Counter Register or Receive Next Counter Register.

1: End of PDC transfer when Receive Counter Register has arrived at zero.

• RXBUFF: Receive Buffer Full

0: SSC_RCR or SSC_RNCR have a value other than 0.

1: Both SSC_RCR and SSC_RNCR have a value of 0.

• CP0: Compare 0

0: A compare 0 has not occurred since the last read of the Status Register.

1: A compare 0 has occurred since the last read of the Status Register.

• CP1: Compare 1

0: A compare 1 has not occurred since the last read of the Status Register.

1: A compare 1 has occurred since the last read of the Status Register.

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AT91SAM7X256/128 Preliminary

• TXSYN: Transmit Sync

0: A Tx Sync has not occurred since the last read of the Status Register.

1: A Tx Sync has occurred since the last read of the Status Register.

• RXSYN: Receive Sync

0: An Rx Sync has not occurred since the last read of the Status Register.

1: An Rx Sync has occurred since the last read of the Status Register.

• TXEN: Transmit Enable

0: Transmit is disabled.

1: Transmit is enabled.

• RXEN: Receive Enable

0: Receive is disabled.

1: Receive is enabled.

6120D–ATARM–02-Feb-06

380

32.8.14

SSC Interrupt Enable Register

Name:

Access Type:

SSC_IER

Write-only

31

30

29

23

15

22

14

21

13

7

RXBUFF

6

ENDRX

5

OVRUN

4

RXRDY

• TXRDY: Transmit Ready Interrupt Enable

0: No effect.

1: Enables the Transmit Ready Interrupt.

• TXEMPTY: Transmit Empty Interrupt Enable

0: No effect.

1: Enables the Transmit Empty Interrupt.

• ENDTX: End of Transmission Interrupt Enable

0: No effect.

1: Enables the End of Transmission Interrupt.

• TXBUFE: Transmit Buffer Empty Interrupt Enable

0: No effect.

1: Enables the Transmit Buffer Empty Interrupt

• RXRDY: Receive Ready Interrupt Enable

0: No effect.

1: Enables the Receive Ready Interrupt.

• OVRUN: Receive Overrun Interrupt Enable

0: No effect.

1: Enables the Receive Overrun Interrupt.

• ENDRX: End of Reception Interrupt Enable

0: No effect.

1: Enables the End of Reception Interrupt.

• RXBUFF: Receive Buffer Full Interrupt Enable

0: No effect.

1: Enables the Receive Buffer Full Interrupt.

• CP0: Compare 0 Interrupt Enable

0: No effect.

1: Enables the Compare 0 Interrupt.

• CP1: Compare 1 Interrupt Enable

0: No effect.

1: Enables the Compare 1 Interrupt.

28

20

12

AT91SAM7X256/128 Preliminary

27

19

11

RXSYN

3

TXBUFE

26

18

10

TXSYN

2

ENDTX

25

17

9

CP1

1

TXEMPTY

24

16

8

CP0

0

TXRDY

381

6120D–ATARM–02-Feb-06

• TXSYN: Tx Sync Interrupt Enable

0: No effect.

1: Enables the Tx Sync Interrupt.

• RXSYN: Rx Sync Interrupt Enable

0: No effect.

1: Enables the Rx Sync Interrupt.

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

382

32.8.15

SSC Interrupt Disable Register

Name:

Access Type:

SSC_IDR

Write-only

31

30

29

23

15

22

14

21

13

7

RXBUFF

6

ENDRX

5

OVRUN

4

RXRDY

• TXRDY: Transmit Ready Interrupt Disable

0: No effect.

1: Disables the Transmit Ready Interrupt.

• TXEMPTY: Transmit Empty Interrupt Disable

0: No effect.

1: Disables the Transmit Empty Interrupt.

• ENDTX: End of Transmission Interrupt Disable

0: No effect.

1: Disables the End of Transmission Interrupt.

• TXBUFE: Transmit Buffer Empty Interrupt Disable

0: No effect.

1: Disables the Transmit Buffer Empty Interrupt.

• RXRDY: Receive Ready Interrupt Disable

0: No effect.

1: Disables the Receive Ready Interrupt.

• OVRUN: Receive Overrun Interrupt Disable

0: No effect.

1: Disables the Receive Overrun Interrupt.

• ENDRX: End of Reception Interrupt Disable

0: No effect.

1: Disables the End of Reception Interrupt.

• RXBUFF: Receive Buffer Full Interrupt Disable

0: No effect.

1: Disables the Receive Buffer Full Interrupt.

• CP0: Compare 0 Interrupt Disable

0: No effect.

1: Disables the Compare 0 Interrupt.

• CP1: Compare 1 Interrupt Disable

0: No effect.

1: Disables the Compare 1 Interrupt.

28

20

12

AT91SAM7X256/128 Preliminary

27

19

11

RXSYN

3

TXBUFE

26

18

10

TXSYN

2

ENDTX

25

17

9

CP1

1

TXEMPTY

24

16

8

CP0

0

TXRDY

383

6120D–ATARM–02-Feb-06

• TXSYN: Tx Sync Interrupt Enable

0: No effect.

1: Disables the Tx Sync Interrupt.

• RXSYN: Rx Sync Interrupt Enable

0: No effect.

1: Disables the Rx Sync Interrupt.

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

384

32.8.16

SSC Interrupt Mask Register

Name:

Access Type:

SSC_IMR

Read-only

31

30

29

23

15

22

14

21

13

7

RXBUF

6

ENDRX

5

OVRUN

4

RXRDY

• TXRDY: Transmit Ready Interrupt Mask

0: The Transmit Ready Interrupt is disabled.

1: The Transmit Ready Interrupt is enabled.

• TXEMPTY: Transmit Empty Interrupt Mask

0: The Transmit Empty Interrupt is disabled.

1: The Transmit Empty Interrupt is enabled.

• ENDTX: End of Transmission Interrupt Mask

0: The End of Transmission Interrupt is disabled.

1: The End of Transmission Interrupt is enabled.

• TXBUFE: Transmit Buffer Empty Interrupt Mask

0: The Transmit Buffer Empty Interrupt is disabled.

1: The Transmit Buffer Empty Interrupt is enabled.

• RXRDY: Receive Ready Interrupt Mask

0: The Receive Ready Interrupt is disabled.

1: The Receive Ready Interrupt is enabled.

• OVRUN: Receive Overrun Interrupt Mask

0: The Receive Overrun Interrupt is disabled.

1: The Receive Overrun Interrupt is enabled.

• ENDRX: End of Reception Interrupt Mask

0: The End of Reception Interrupt is disabled.

1: The End of Reception Interrupt is enabled.

• RXBUFF: Receive Buffer Full Interrupt Mask

0: The Receive Buffer Full Interrupt is disabled.

1: The Receive Buffer Full Interrupt is enabled.

• CP0: Compare 0 Interrupt Mask

0: The Compare 0 Interrupt is disabled.

1: The Compare 0 Interrupt is enabled.

• CP1: Compare 1 Interrupt Mask

0: The Compare 1 Interrupt is disabled.

1: The Compare 1 Interrupt is enabled.

28

20

12

AT91SAM7X256/128 Preliminary

27

19

11

RXSYN

3

TXBUFE

26

18

10

TXSYN

2

ENDTX

25

17

9

CP1

1

TXEMPTY

24

16

8

CP0

0

TXRDY

385

6120D–ATARM–02-Feb-06

• TXSYN: Tx Sync Interrupt Mask

0: The Tx Sync Interrupt is disabled.

1: The Tx Sync Interrupt is enabled.

• RXSYN: Rx Sync Interrupt Mask

0: The Rx Sync Interrupt is disabled.

1: The Rx Sync Interrupt is enabled.

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

386

AT91SAM7X256/128 Preliminary

33. Timer/Counter (TC)

33.1

Overview

The Timer/Counter (TC) includes three identical 16-bit Timer/Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.

Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts.

The Timer/Counter block has two global registers which act upon all three TC channels.

The Block Control Register allows the three channels to be started simultaneously with the same instruction.

The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained.

33.2

Block Diagram

Figure 33-1. Timer/Counter Block Diagram

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

TCLK0

TCLK1

TCLK2

TIOA1

TIOA2 XC0

XC1

XC2

TC0XC0S

Timer/Counter

Channel 0

TIOA

TIOB

TIOA0

TIOB0

SYNC

INT0

Parallel I/O

Controller

TCLK0

TCLK1

TCLK2

TIOA0

TIOB0

TCLK0

TCLK1

TIOA0

TIOA2

TCLK2

XC0

XC1

XC2

TC1XC1S

Timer/Counter

Channel 1

TIOA

TIOB

TIOA1

TIOB1

SYNC

INT1

TIOA1

TIOB1

TCLK0

TCLK1

TCLK2

TIOA0

TIOA1

XC0

XC1

XC2

TC2XC2S

Timer/Counter

Channel 2

TIOA

TIOB

TIOA2

TIOB2

SYNC

INT2

TIOA2

TIOB2

Timer Counter

Advanced

Interrupt

Controller

387

6120D–ATARM–02-Feb-06

Table 33-1.

Signal Name Description

Channel Signal

XC0, XC1, XC2

TIOA

TIOB

INT

SYNC

Description

External Clock Inputs

Capture Mode: Timer/Counter Input

Waveform Mode: Timer/Counter Output

Capture Mode: Timer/Counter Input

Waveform Mode: Timer/Counter Input/output

Interrupt Signal Output

Synchronization Input Signal

33.3

Pin Name List

Table 33-2.

TC pin list

Pin Name

TCLK0-TCLK2

TIOA0-TIOA2

TIOB0-TIOB2

Description

External Clock Input

I/O Line A

I/O Line B

Type

Input

I/O

I/O

33.4

Product Dependencies

33.4.1

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.

The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions.

33.4.2

33.4.3

Power Management

The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer/Counter clock.

Interrupt

The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the

TC interrupt requires programming the AIC before configuring the TC.

388

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AT91SAM7X256/128 Preliminary

33.5

Functional Description

33.5.1

TC Description

The three channels of the Timer/Counter are independent and identical in operation. The regis-

ters for channel programming are listed in Table 33-4 on page 402 .

33.5.1.1

33.5.1.2

16-bit Counter

Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.

The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to

0x0000 on the next valid edge of the selected clock.

Clock Selection

At block level, input clock signals of each channel can either be connected to the external inputs

TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or

TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 33-2

.

Each channel can independently select an internal or external clock source for its counter:

• Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3,

TIMER_CLOCK4, TIMER_CLOCK5

• External clock signals: XC0, XC1 or XC2

This selection is made by the TCCLKS bits in the TC Channel Mode Register.

The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock.

The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).

Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock

389

6120D–ATARM–02-Feb-06

Figure 33-2. Clock Selection

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

XC1

XC2

TCCLKS

BURST

1

CLKI

Selected

Clock

33.5.1.3

Clock Control

The clock of each counter can be controlled in two different ways: it can be enabled/disabled

and started/stopped. See Figure 33-3 .

• The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if

LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register.

• The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode

(LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in

TC_CMR). The start and the stop commands have effect only if the clock is enabled.

390

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

Figure 33-3. Clock Control

Selected

Clock

Q S

R

Trigger

CLKSTA CLKEN CLKDIS

Q S

R

33.5.1.4

33.5.1.5

Stop

Event

Disable

Event

Counter

Clock

TC Operating Modes

Each channel can independently operate in two different modes:

• Capture Mode provides measurement on signals.

• Waveform Mode provides wave generation.

The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register.

In Capture Mode, TIOA and TIOB are configured as inputs.

In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger.

Trigger

A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode.

The following triggers are common to both modes:

• Software Trigger: Each channel has a software trigger, available by setting SWTRG in

TC_CCR.

• SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.

• Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR.

The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR.

391

6120D–ATARM–02-Feb-06

33.5.2

33.5.2.1

Capture Operating Mode

This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register).

Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs.

Figure 33-4

shows the configuration of the TC channel when programmed in Capture Mode.

Capture Registers A and B

Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA.

The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the

LDRB parameter defines the TIOA edge for the loading of Register B.

RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA.

RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.

Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten.

33.5.2.2

If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected.

Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock.

Trigger Conditions

In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.

The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The

ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.

392

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6120D–ATARM–02-Feb-06

Figure 33-4. Capture Mode

AT91SAM7X256/128 Preliminary

CPCS

LOVRS

COVFS

LDRBS

LDRAS

ETRGS

TC1_SR TC1_IMR

6120D–ATARM–02-Feb-06

393

33.5.3

33.5.3.1

Waveform Operating Mode

Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel

Mode Register).

In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses.

In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).

Figure 33-5

shows the configuration of the TC channel when programmed in Waveform Operating Mode.

Waveform Selection

Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of

TC_CV varies.

With any selection, RA, RB and RC can all be used as compare registers.

RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output

(if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.

394

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6120D–ATARM–02-Feb-06

Figure 33-5. Waveform Mode

AT91SAM7X256/128 Preliminary

Output Controller Output Controller

CPCS

CPBS

CPAS

COVFS

ETRGS

TC1_SR TC1_IMR

395

33.5.3.2

WAVSEL = 00

When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See

Figure 33-6 .

An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See

Figure 33-7

.

RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR).

Figure 33-6. WAVSEL= 00 without trigger

Counter Value

0xFFFF

Counter cleared by compare match with 0xFFFF

R

C

R

B

R

A

Time

Waveform Examples

TIOB

TIOA

396

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AT91SAM7X256/128 Preliminary

Figure 33-7. WAVSEL= 00 with trigger

Counter Value

0xFFFF

Counter cleared by compare match with 0xFFFF

Counter cleared by trigger

R

C

R

B

R

A

Time

Waveform Examples

TIOB

TIOA

33.5.3.3

WAVSEL = 10

When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then

incremented and so on. See Figure 33-8 .

It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See

Figure 33-9 .

In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR).

397

6120D–ATARM–02-Feb-06

Figure 33-8. WAVSEL = 10 Without Trigger

Counter Value

0xFFFF

Counter cleared by compare match with RC

R

C

R

B

R

A

Waveform Examples

TIOB

Time

TIOA

Figure 33-9. WAVSEL = 10 With Trigger

Counter Value

0xFFFF

Counter cleared by compare match with RC

R

C

Counter cleared by trigger

R

B

R

A

Time

Waveform Examples

TIOB

TIOA

33.5.3.4

WAVSEL = 01

When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on.

See Figure 33-10

.

A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while

TC_CV is decrementing, TC_CV then increments. See Figure 33-11

.

398

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

RC Compare cannot be programmed to generate a trigger in this configuration.

At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).

Figure 33-10. WAVSEL = 01 Without Trigger

Counter Value Counter decremented by compare match with 0xFFFF

0xFFFF

R

C

R

B

R

A

Time

Waveform Examples

TIOB

TIOA

Figure 33-11. WAVSEL = 01 With Trigger

Counter Value Counter decremented by compare match with 0xFFFF

0xFFFF

Counter decremented by trigger

R

C

R

B

Counter incremented by trigger

R

A

Time

Waveform Examples

TIOB

TIOA

33.5.3.5

WAVSEL = 11

When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the

value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 33-12

.

399

6120D–ATARM–02-Feb-06

A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while

TC_CV is decrementing, TC_CV then increments. See Figure 33-13

.

RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPC-

DIS = 1).

Figure 33-12. WAVSEL = 11 Without Trigger

Counter Value

0xFFFF

Counter decremented by compare match with RC

R

C

R

B

R

A

Time

Waveform Examples

TIOB

TIOA

Figure 33-13. WAVSEL = 11 With Trigger

Counter Value

0xFFFF

Counter decremented by compare match with RC

R

C

Counter decremented by trigger

R

B

Counter incremented by trigger

R

A

Waveform Examples

TIOB

Time

TIOA

33.5.3.6

400

External Event/Trigger Conditions

An external event can be programmed to be detected on one of the clock sources (XC0, XC1,

XC2) or TIOB. The external event selected can then be used as a trigger.

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

33.5.3.7

AT91SAM7X256/128 Preliminary

The parameter EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If

EEVTEDG is cleared (none), no external event is defined.

If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the TC channel can only generate a waveform on TIOA.

When an external event is defined, it can be used as a trigger by setting bit ENETRG in

TC_CMR.

As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC

Compare can also be used as a trigger depending on the parameter WAVSEL.

Output Controller

The output controller defines the output level changes on TIOA and TIOB following an event.

TIOB control is used only if TIOB is defined as output (not as an external event).

The following events control TIOA and TIOB: software trigger, external event and RC compare.

RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in

TC_CMR.

401

6120D–ATARM–02-Feb-06

33.6

Timer/Counter (TC) User Interface

33.6.1

Global Register Mapping

Table 33-3.

Timer/Counter (TC) Global Register Map

Offset Channel/Register

0x00

0x40

0x80

0xC0

0xC4

TC Channel 0

TC Channel 1

TC Channel 2

TC Block Control Register

TC Block Mode Register

Name

TC_BCR

TC_BMR

Access

See Table 33-4

See Table 33-4

See Table 33-4

Write-only

Read/Write

Reset Value

0

TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC block. TC channels are controlled by the registers listed in

Table 33-4

. The offset of each of the

channel registers in

Table 33-4

is in relation to the offset of the corresponding channel as mentioned in

Table 33-4

.

33.6.2

Channel Memory Mapping

Table 33-4.

Timer/Counter (TC) Channel Memory Mapping

Offset

0x00

Register

Channel Control Register

Name

TC_CCR

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

Channel Mode Register

Reserved

Reserved

Counter Value

Register A

Register B

Register C

0x20

0x24

0x28

Status Register

Interrupt Enable Register

Interrupt Disable Register

0x2C Interrupt Mask Register

0x30-0xFC Reserved

TC_CMR

TC_CV

TC_RA

TC_RB

TC_RC

TC_SR

TC_IER

TC_IDR

TC_IMR

Note: 1.

Read only if WAVE = 0

Write-only

Read/Write

Read-only

Read/Write

(1)

Read/Write

(1)

Read/Write

Read-only

Write-only

Write-only

Read-only

0

0

0

0

0

0

0

402

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

33.6.3

TC Block Control Register

Register Name:

TC_BCR

Access Type:

Write-only

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

10

2

26

18

1

9

25

17

• SYNC: Synchro Command

0 = No effect.

1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.

24

16

8

0

SYNC

6120D–ATARM–02-Feb-06

403

33.6.4

TC Block Mode Register

Register Name:

TC_BMR

Access Type:

Read/Write

15

7

31

23

14

6

30

22

13

5

29

21

TC2XC2S

12

4

28

20

• TC0XC0S: External Clock Signal 0 Selection

1

1

0

0

TC0XC0S

0

1

0

1

Signal Connected to XC0

TCLK0 none

TIOA1

TIOA2

• TC1XC1S: External Clock Signal 1 Selection

11

3

27

19

TCXC1S

10

2

26

18

0

0

1

1

TC1XC1S

0

1

0

1

Signal Connected to XC1

TCLK1 none

TIOA0

TIOA2

• TC2XC2S: External Clock Signal 2 Selection

1

1

0

0

TC2XC2S

0

1

0

1

Signal Connected to XC2

TCLK2 none

TIOA0

TIOA1

9

1

25

17

TC0XC0S

8

0

24

16

404

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

33.6.5

TC Channel Control Register

Register Name:

TC_CCR

Access Type:

Write-only

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

• CLKEN: Counter Clock Enable Command

0 = No effect.

1 = Enables the clock if CLKDIS is not 1.

• CLKDIS: Counter Clock Disable Command

0 = No effect.

1 = Disables the clock.

• SWTRG: Software Trigger Command

0 = No effect.

1 = A software trigger is performed: the counter is reset and the clock is started.

26

18

10

2

SWTRG

25

17

9

1

CLKDIS

24

16

8

0

CLKEN

405

6120D–ATARM–02-Feb-06

33.6.6

TC Channel Mode Register: Capture Mode

Register Name:

TC_CMR

Access Type:

Read/Write

31

23

15

WAVE = 0

7

LDBDIS

30

22

14

CPCTRG

6

LDBSTOP

13

5

29

21

BURST

12

4

28

20

• TCCLKS: Clock Selection

27

19

11

3

CLKI

26

18

LDRB

10

ABETRG

2

25

17

LDRA

9

ETRGEDG

1

TCCLKS

24

16

8

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

• CLKI: Clock Invert

0 = Counter is incremented on rising edge of the clock.

1 = Counter is incremented on falling edge of the clock.

• BURST: Burst Signal Selection

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

XC1

XC2

BURST

1

1

0

0

0

1

0

1

The clock is not gated by an external signal.

XC0 is ANDed with the selected clock.

XC1 is ANDed with the selected clock.

XC2 is ANDed with the selected clock.

• LDBSTOP: Counter Clock Stopped with RB Loading

0 = Counter clock is not stopped when RB loading occurs.

1 = Counter clock is stopped when RB loading occurs.

• LDBDIS: Counter Clock Disable with RB Loading

0 = Counter clock is not disabled when RB loading occurs.

1 = Counter clock is disabled when RB loading occurs.

406

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

• ETRGEDG: External Trigger Edge Selection

1

1

0

0

ETRGEDG

0

1

0

1

Edge

none rising edge falling edge each edge

• ABETRG: TIOA or TIOB External Trigger Selection

0 = TIOB is used as an external trigger.

1 = TIOA is used as an external trigger.

• CPCTRG: RC Compare Trigger Enable

0 = RC Compare has no effect on the counter and its clock.

1 = RC Compare resets the counter and starts the counter clock.

• WAVE

0 = Capture Mode is enabled.

1 = Capture Mode is disabled (Waveform Mode is enabled).

• LDRA: RA Loading Selection

LDRA

1

1

0

0

0

1

0

1

• LDRB: RB Loading Selection

Edge

none rising edge of TIOA falling edge of TIOA each edge of TIOA

0

0

1

1

LDRB

0

1

0

1

Edge

none rising edge of TIOA falling edge of TIOA each edge of TIOA

407

6120D–ATARM–02-Feb-06

33.6.7

TC Channel Mode Register: Waveform Mode

Register Name:

TC_CMR

Access Type:

Read/Write

29 31 30

BSWTRG

23

15

WAVE = 1

ASWTRG

7

CPCDIS

22

14

6

CPCSTOP

WAVSEL

21

13

5

28

BEEVT

20

AEEVT

BURST

12

ENETRG

4

• TCCLKS: Clock Selection

1

1

1

1

0

0

0

0

TCCLKS

0

0

0

0

1

1

1

1

0

1

0

1

0

1

0

1

• CLKI: Clock Invert

0 = Counter is incremented on rising edge of the clock.

1 = Counter is incremented on falling edge of the clock.

• BURST: Burst Signal Selection

Clock Selected

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

XC1

XC2

27

19

11

3

CLKI

BURST

1

1

0

0

0

1

0

1

The clock is not gated by an external signal.

XC0 is ANDed with the selected clock.

XC1 is ANDed with the selected clock.

XC2 is ANDed with the selected clock.

• CPCSTOP: Counter Clock Stopped with RC Compare

0 = Counter clock is not stopped when counter reaches RC.

1 = Counter clock is stopped when counter reaches RC.

• CPCDIS: Counter Clock Disable with RC Compare

0 = Counter clock is not disabled when counter reaches RC.

1 = Counter clock is disabled when counter reaches RC.

BCPC

ACPC

EEVT

26

18

10

2

408

AT91SAM7X256/128 Preliminary

25 24

BCPB

17

ACPA

9

1

TCCLKS

EEVTEDG

16

8

0

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

• EEVTEDG: External Event Edge Selection

EEVTEDG

1

1

0

0

0

1

0

1

• EEVT: External Event Selection

Edge

none rising edge falling edge each edge

0

0

1

1

EEVT

0

1

0

1

Signal selected as external event

TIOB

XC0

XC1

XC2

TIOB Direction

input

(1)

output output output

Note: 1.

If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.

• ENETRG: External Event Trigger Enable

0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the

TIOA output.

1 = The external event resets the counter and starts the counter clock.

• WAVSEL: Waveform Selection

0

1

0

1

WAVSEL

1

1

0

0

Effect

UP mode without automatic trigger on RC Compare

UP mode with automatic trigger on RC Compare

UPDOWN mode without automatic trigger on RC Compare

UPDOWN mode with automatic trigger on RC Compare

• WAVE = 1

0 = Waveform Mode is disabled (Capture Mode is enabled).

1 = Waveform Mode is enabled.

• ACPA: RA Compare Effect on TIOA

1

1

0

0

ACPA

0

1

0

1

Effect

none set clear toggle

409

6120D–ATARM–02-Feb-06

• ACPC: RC Compare Effect on TIOA

1

1

0

0

ACPC

0

1

0

1

Effect

none set clear toggle

• AEEVT: External Event Effect on TIOA

0

0

1

1

AEEVT

0

1

0

1

Effect

none set clear toggle

• ASWTRG: Software Trigger Effect on TIOA

ASWTRG

1

1

0

0

0

1

0

1

• BCPB: RB Compare Effect on TIOB

Effect

none set clear toggle

BCPB

0

0

1

1

0

1

0

1

• BCPC: RC Compare Effect on TIOB

Effect

none set clear toggle

1

1

0

0

BCPC

0

1

0

1

Effect

none set clear toggle

410

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

• BEEVT: External Event Effect on TIOB

1

1

0

0

BEEVT

0

1

0

1

Effect

none set clear toggle

• BSWTRG: Software Trigger Effect on TIOB

0

0

1

1

BSWTRG

0

1

0

1

Effect

none set clear toggle

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

411

33.6.8

TC Counter Value Register

Register Name:

TC_CV

Access Type:

Read-only

31

23

15

30

22

14

29

21

13

7 6 5

• CV: Counter Value

CV contains the counter value in real time.

28

20

12

4

CV

CV

27

19

11

3

26

18

10

2

25

17

9

1

24

16

8

0

412

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

33.6.9

TC Register A

Register Name:

TC_RA

Access Type:

Read-only if WAVE = 0, Read/Write if WAVE = 1

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

RA

7 6 5 4 3

RA

• RA: Register A

RA contains the Register A value in real time.

26

18

10

2

25

17

9

1

24

16

8

0

6120D–ATARM–02-Feb-06

413

33.6.10

TC Register B

Register Name:

TC_RB

Access Type:

Read-only if WAVE = 0, Read/Write if WAVE = 1

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

RB

7 6 5 4 3

RB

• RB: Register B

RB contains the Register B value in real time.

33.6.11

TC Register C

Register Name:

TC_RC

Access Type:

Read/Write

31

23

15

30

22

14

29

21

13

7 6 5

• RC: Register C

RC contains the Register C value in real time.

28

20

12

4

RC

RC

27

19

11

3

26

18

10

2

26

18

10

2

25

17

9

1

24

16

8

0

25

17

9

1

24

16

8

0

414

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

33.6.12

TC Status Register

Register Name:

TC_SR

Access Type:

Read-only

31

23

15

7

ETRGS

30

22

14

6

LDRBS

29

21

13

5

LDRAS

28

20

12

4

CPCS

27

19

11

3

CPBS

26

18

MTIOB

10

2

CPAS

25

17

MTIOA

9

1

LOVRS

24

16

CLKSTA

8

0

COVFS

• COVFS: Counter Overflow Status

0 = No counter overflow has occurred since the last read of the Status Register.

1 = A counter overflow has occurred since the last read of the Status Register.

• LOVRS: Load Overrun Status

0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.

1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0.

• CPAS: RA Compare Status

0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.

1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.

• CPBS: RB Compare Status

0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.

1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.

• CPCS: RC Compare Status

0 = RC Compare has not occurred since the last read of the Status Register.

1 = RC Compare has occurred since the last read of the Status Register.

• LDRAS: RA Loading Status

0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.

1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.

• LDRBS: RB Loading Status

0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.

1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.

• ETRGS: External Trigger Status

0 = External trigger has not occurred since the last read of the Status Register.

1 = External trigger has occurred since the last read of the Status Register.

• CLKSTA: Clock Enabling Status

0 = Clock is disabled.

1 = Clock is enabled.

415

6120D–ATARM–02-Feb-06

• MTIOA: TIOA Mirror

0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.

1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.

• MTIOB: TIOB Mirror

0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.

1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

416

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

33.6.13

TC Interrupt Enable Register

Register Name:

TC_IER

Access Type:

Write-only

31

23

15

7

ETRGS

30

22

14

6

LDRBS

29

21

13

5

LDRAS

• COVFS: Counter Overflow

0 = No effect.

1 = Enables the Counter Overflow Interrupt.

• LOVRS: Load Overrun

0 = No effect.

1 = Enables the Load Overrun Interrupt.

• CPAS: RA Compare

0 = No effect.

1 = Enables the RA Compare Interrupt.

• CPBS: RB Compare

0 = No effect.

1 = Enables the RB Compare Interrupt.

• CPCS: RC Compare

0 = No effect.

1 = Enables the RC Compare Interrupt.

• LDRAS: RA Loading

0 = No effect.

1 = Enables the RA Load Interrupt.

• LDRBS: RB Loading

0 = No effect.

1 = Enables the RB Load Interrupt.

• ETRGS: External Trigger

0 = No effect.

1 = Enables the External Trigger Interrupt.

28

20

12

4

CPCS

AT91SAM7X256/128 Preliminary

27

19

11

3

CPBS

10

2

CPAS

26

18

25

17

9

1

LOVRS

24

16

8

0

COVFS

417

6120D–ATARM–02-Feb-06

33.6.14

TC Interrupt Disable Register

Register Name:

TC_IDR

Access Type:

Write-only

31

30

29

23

15

22

14

21

13

7

ETRGS

6

LDRBS

5

LDRAS

4

CPCS

• COVFS: Counter Overflow

0 = No effect.

1 = Disables the Counter Overflow Interrupt.

• LOVRS: Load Overrun

0 = No effect.

1 = Disables the Load Overrun Interrupt (if WAVE = 0).

• CPAS: RA Compare

0 = No effect.

1 = Disables the RA Compare Interrupt (if WAVE = 1).

• CPBS: RB Compare

0 = No effect.

1 = Disables the RB Compare Interrupt (if WAVE = 1).

• CPCS: RC Compare

0 = No effect.

1 = Disables the RC Compare Interrupt.

• LDRAS: RA Loading

0 = No effect.

1 = Disables the RA Load Interrupt (if WAVE = 0).

• LDRBS: RB Loading

0 = No effect.

1 = Disables the RB Load Interrupt (if WAVE = 0).

• ETRGS: External Trigger

0 = No effect.

1 = Disables the External Trigger Interrupt.

28

20

12

11

3

CPBS

27

19

10

2

CPAS

26

18

25

17

9

1

LOVRS

24

16

8

0

COVFS

418

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

33.6.15

TC Interrupt Mask Register

Register Name:

TC_IMR

Access Type:

Read-only

31

23

15

7

ETRGS

30

22

14

6

LDRBS

29

21

13

5

LDRAS

• COVFS: Counter Overflow

0 = The Counter Overflow Interrupt is disabled.

1 = The Counter Overflow Interrupt is enabled.

• LOVRS: Load Overrun

0 = The Load Overrun Interrupt is disabled.

1 = The Load Overrun Interrupt is enabled.

• CPAS: RA Compare

0 = The RA Compare Interrupt is disabled.

1 = The RA Compare Interrupt is enabled.

• CPBS: RB Compare

0 = The RB Compare Interrupt is disabled.

1 = The RB Compare Interrupt is enabled.

• CPCS: RC Compare

0 = The RC Compare Interrupt is disabled.

1 = The RC Compare Interrupt is enabled.

• LDRAS: RA Loading

0 = The Load RA Interrupt is disabled.

1 = The Load RA Interrupt is enabled.

• LDRBS: RB Loading

0 = The Load RB Interrupt is disabled.

1 = The Load RB Interrupt is enabled.

• ETRGS: External Trigger

0 = The External Trigger Interrupt is disabled.

1 = The External Trigger Interrupt is enabled.

28

20

12

4

CPCS

AT91SAM7X256/128 Preliminary

27

19

11

3

CPBS

10

2

CPAS

26

18

25

17

9

1

LOVRS

24

16

8

0

COVFS

419

6120D–ATARM–02-Feb-06

420

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

34. Pulse Width Modulation Controller (PWM)

34.1

Overview

The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.

All PWM macrocell accesses are made through APB mapped registers.

Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.

34.2

Block Diagram

Figure 34-1. Pulse Width Modulation Controller Block Diagram

PWM

Controller

PWMx

Channel

Clock

Selector

Period

Update

Duty Cycle

Counter

Comparator

PWMx

PWMx

PIO

PMC

MCK

PWM0

Channel

Clock

Selector

Period

Update

Duty Cycle

Counter

Comparator

Clock Generator APB Interface Interrupt Generator

APB

AIC

PWM0

PWM0

421

6120D–ATARM–02-Feb-06

34.3

I/O Lines Description

Each channel outputs one waveform on one external I/O line.

Table 34-1.

I/O Line Description

Name

PWMx

Description

PWM Waveform Output for channel x

Type

Output

34.4

Product Dependencies

34.4.1

I/O Lines

The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the

PIO controller.

All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs.

34.4.2

Power Management

The PWM is not continuously clocked. The programmer must first enable the PWM clock in the

Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off.

Configuring the PWM does not require the PWM clock to be enabled.

34.4.3

Interrupt Sources

The PWM interrupt line is connected on one of the internal sources of the Advanced Interrupt

Controller. Using the PWM interrupt requires the AIC to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode.

422

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

34.5

Functional Description

The PWM macrocell is primarily composed of a clock generator module and 4 channels.

• Clocked by the system clock, MCK, the clock generator module provides 13 clocks.

• Each channel can independently choose one of the clock generator outputs.

• Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers.

34.5.1

PWM Clock Generator

Figure 34-2. Functional View of the Clock Generator Block Diagram

MCK modulo n counter

MCK

MCK/2

MCK/4

MCK/8

MCK/16

MCK/32

MCK/64

MCK/128

MCK/256

MCK/512

MCK/1024

Divider A clkA

PREA DIVA

PWM_MR

Divider B clkB

6120D–ATARM–02-Feb-06

PREB DIVB

PWM_MR

Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC).

The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks.

The clock generator is divided in three blocks:

• a modulo n counter which provides 11 clocks: F

MCK

, F

MCK

/2, F

MCK

/4, F

MCK

/8, F

MCK

/16,

F

MCK

/32, F

MCK

/64, F

MCK

/128, F

MCK

/256, F

MCK

/512, F

MCK

/1024

• two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB

423

Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM

Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA

(DIVB) field value in the PWM Mode register (PWM_MR).

After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off.

At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Management

Controller.

34.5.2

34.5.2.1

PWM Channel

Block Diagram

Figure 34-3. Functional View of the Channel Block Diagram

Inputs from clock generator

Channel

Clock

Selector

Internal

Counter

Comparator

PWMx output waveform

Inputs from

APB Bus

34.5.2.2

Each of the 4 channels is composed of three blocks:

• A clock selector which selects one of the clocks provided by the clock generator described in

Section 34.5.1 ”PWM Clock Generator”, on page 423 .

• An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events.

The size of the internal counter is 16 bits.

• A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration.

Waveform Properties

The different properties of output waveforms are:

• the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0.

• the waveform period. This channel parameter is defined in the CPRD field of the

PWM_CPRDx register.

- If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be claculated:

By using the Master Clock (MCK) divided by an X given prescaler value

(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:

(

X

×

CPRD

MCK

)

424

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:

(

CRPD

×

DIVA

MCK

)

or

(

CRPD

×

DIVAB

MCK

)

If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated:

By using the Master Clock (MCK) divided by an X given prescaler value

(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will

( be:

2

X

×

CPRD

)

MCK

By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,

( respectively:

2

CPRD

×

DIVA

MCK

)

or

(

2

×

CPRD

×

MCK

)

• the waveform duty cycle. This channel parameter is defined in the CDTY field of the

PWM_CDTYx register.

If the waveform is left aligned then: duty cycle

=

(

period

– 1 fchannel_x_clock

×

CDTY

)

period

If the waveform is center aligned, then: uty cycle

=

( (

period

2

)

– 1

( fchannel_x_clock

period

2

)

×

CDTY

)

• the waveform polarity. At the beginning of the period, the signal can be at high or low level.

This property is defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.

• the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned.

Figure 34-4. Non Overlapped Center Aligned Waveforms

(1)

No overlap

PWM0

PWM1

Period

Note: 1. See

Figure 34-5 on page 427

for a detailed description of center aligned waveforms.

425

When center aligned, the internal channel counter increases up to CPRD and decreases down to 0. This ends the period.

When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.

Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel.

Waveforms are fixed at 0 when:

CDTY = CPRD and CPOL = 0

CDTY = 0 and CPOL = 1

Waveforms are fixed at 1 (once the channel is enabled) when:

CDTY = 0 and CPOL = 0

CDTY = CPRD and CPOL = 1

The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled.

426

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Figure 34-5. Waveform Properties

PWM_MCKx

CHIDx(PWM_SR)

CHIDx(PWM_ENA)

CHIDx(PWM_DIS)

PWM_CCNTx

CPRD(PWM_CPRDx)

CDTY(PWM_CDTYx)

Period

Output Waveform PWMx

CPOL(PWM_CMRx) = 0

Output Waveform PWMx

CPOL(PWM_CMRx) = 1

CHIDx(PWM_ISR)

PWM_CCNTx

CPRD(PWM_CPRDx)

CDTY(PWM_CDTYx)

Period

Output Waveform PWMx

CPOL(PWM_CMRx) = 0

Output Waveform PWMx

CPOL(PWM_CMRx) = 1

CHIDx(PWM_ISR)

Center Aligned

CALG(PWM_CMRx) = 1

Left Aligned

CALG(PWM_CMRx) = 0

427

6120D–ATARM–02-Feb-06

34.5.3

34.5.3.1

PWM Controller Operations

Initialization

Before enabling the output channel, this channel must have been configured by the software application:

• Configuration of the clock generator if DIVA and DIVB are required

• Selection of the clock for each channel (CPRE field in the PWM_CMRx register)

• Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)

• Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in

PWM_CPRDx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained below.

• Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register).

Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx as explained below.

• Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register)

• Enable Interrupts (Writing CHIDx in the PWM_IER register)

• Enable the PWM channel (Writing CHIDx in the PWM_ENA register)

It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the PWM_ENA register.

• In such a situation, all channels may have the same clock selector configuration and the same period specified.

34.5.3.2

34.5.3.3

Source Clock Selection Criteria

The large number of source clocks can make selection difficult. The relationship between the value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.

For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.

Changing the Duty Cycle or the Period

It is possible to modulate the output waveform duty cycle or period.

To prevent an unexpected output waveform when modifying the waveform parameters while the channel is still enabled, PWM_CPRDx and PWM_CDTYx registers are double buffered. The user can write a new period value or duty cycle value in the update register (PWM_CUPDx).

This register holds the new value until the end of the current cycle and updates the value for the next cycle. According to the CPD field in the PWM_CMRx register, PWM_CUPDx either updates the PWM_CPRDx or PWM_CDTYx.

428

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

Figure 34-6. Synchronized Period or Duty Cycle Update

User's Writing

PWM_CUPDx Value

1

0

PWM_CMRx. CPD

PWM_CPRDx PWM_CDTYx

End of Cycle

To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level.

The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the enabled channel(s). See

Figure 34-7

.

The second method uses an Interrupt Service Routine associated with the PWM channel.

Note: Reading the PWM_ISR register automatically clears CHIDx flags.

Figure 34-7. Polling Method

PWM_ISR Read

Acknowledgement and clear previous register state

Writing in CPD field

Update of the Period or Duty Cycle

CHIDx = 1

YES

Writing in PWM_CUPDx

The last write has been taken into account

Note: Polarity and alignment can be modified only when the channel is disabled.

429

34.5.3.4

Interrupts

Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the

PWM_ISR register occurs.

A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.

430

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...

0x220

0x224

0x228

0x22C

0x230

...

Offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x4C - 0xFC

0x100 - 0x1FC

0x200

0x204

0x208

0x20C

0x210

AT91SAM7X256/128 Preliminary

34.6

Pulse Width Modulation Controller (PWM) User Interface

Table 34-2.

Pulse Width Modulation Controller (PWM) Register Mapping

Register Name

PWM Mode Register PWM_MR

PWM Enable Register

PWM Disable Register

PWM_ENA

PWM_DIS

PWM Status Register

PWM Interrupt Enable Register

PWM Interrupt Disable Register

PWM Interrupt Mask Register

PWM_SR

PWM_IER

PWM_IDR

PWM_IMR

PWM_ISR

PWM Interrupt Status Register

Reserved

Reserved

Channel 0 Mode Register

Channel 0 Duty Cycle Register

Channel 0 Period Register

Channel 0 Counter Register

Channel 0 Update Register

PWM_CMR0

PWM_CDTY0

PWM_CPRD0

PWM_CCNT0

PWM_CUPD0

Reserved

Channel 1 Mode Register

Channel 1 Duty Cycle Register

Channel 1 Period Register

Channel 1 Counter Register

Channel 1 Update Register

...

PWM_CMR1

PWM_CDTY1

PWM_CPRD1

PWM_CCNT1

PWM_CUPD1

...

Access

Read/Write

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Read-only

Read/Write

Read/Write

Read/Write

Read-only

Write-only

Read/Write

Read/Write

Read/Write

Read-only

Write-only

...

Peripheral

Reset Value

0

0

-

-

-

0

-

0

0x0

0x0

0x0

0x0

-

...

0x0

0x0

0x0

0x0

-

431

6120D–ATARM–02-Feb-06

34.6.1

PWM Mode Register

Register Name:

PWM_MR

Access Type:

31

Read/Write

30

29

23

15

7

22

14

6

21

13

5

12

4

28

20

27

DIVB

19

11

3

DIVA

26

PREB

25

18 17

10

PREA

2

9

1

24

16

8

0

• DIVA, DIVB: CLKA, CLKB Divide Factor

DIVA, DIVB

0

1

2-255

• PREA, PREB

0

0

0

0

0

0

0

1

1

0

1

0

0

1

0

1

1

0

1

0

0

PREA, PREB

0 0

0

1

0

1

1

0

0

1

1

0

Other

1

0

1

0

0

1

0

1

0

1

0

CLKA, CLKB

CLKA, CLKB clock is turned off

CLKA, CLKB clock is clock selected by PREA, PREB

CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.

MCK.

MCK/2

MCK/4

MCK/8

MCK/16

MCK/32

MCK/64

MCK/128

MCK/256

MCK/512

MCK/1024

Reserved

Divider Input Clock

432

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6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

34.6.2

PWM Enable Register

Register Name:

PWM_ENA

Access Type:

31

Write-only

30

29

23

15

22

14

7

6

• CHIDx: Channel ID

0 = No effect.

1 = Enable PWM output for channel x.

5

21

13

34.6.3

PWM Disable Register

Register Name:

PWM_DIS

Access Type:

31

Write-only

30

29

23

15

22

14

7

6

• CHIDx: Channel ID

0 = No effect.

1 = Disable PWM output for channel x.

5

21

13

12

4

28

20

11

3

CHID3

27

19

26

18

10

2

CHID2

9

1

CHID1

25

17

8

0

CHID0

24

16

28

20

12

4

27

19

11

3

CHID3

26

18

10

2

CHID2

25

17

9

1

CHID1

24

16

8

0

CHID0

433

6120D–ATARM–02-Feb-06

34.6.4

PWM Status Register

Register Name:

PWM_SR

Access Type:

31

Read-only

30

29

23

15

22

14

21

13

7

6

5

• CHIDx: Channel ID

0 = PWM output for channel x is disabled.

1 = PWM output for channel x is enabled.

34.6.5

PWM Interrupt Enable Register

Register Name:

PWM_IER

Access Type:

31

Write-only

30

29

23

15

22

14

7

6

5

• CHIDx: Channel ID.

0 = No effect.

1 = Enable interrupt for PWM channel x.

21

13

12

4

28

20

28

20

12

4

11

3

CHID3

27

19

26

18

10

2

CHID2

9

1

CHID1

25

17

8

0

CHID0

24

16

27

19

11

3

CHID3

26

18

10

2

CHID2

25

17

9

1

CHID1

24

16

8

0

CHID0

434

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6120D–ATARM–02-Feb-06

34.6.6

PWM Interrupt Disable Register

Register Name:

PWM_IDR

Access Type:

31

Write-only

30

29

23

15

22

14

21

13

7

6

5

• CHIDx: Channel ID.

0 = No effect.

1 = Disable interrupt for PWM channel x.

12

4

28

20

AT91SAM7X256/128 Preliminary

11

3

CHID3

27

19

26

18

10

2

CHID2

9

1

CHID1

25

17

8

0

CHID0

24

16

435

6120D–ATARM–02-Feb-06

34.6.7

PWM Interrupt Mask Register

Register Name:

PWM_IMR

Access Type:

31

Read-only

30

29

23

15

22

14

21

13

7

6

5

• CHIDx: Channel ID.

0 = Interrupt for PWM channel x is disabled.

1 = Interrupt for PWM channel x is enabled.

34.6.8

PWM Interrupt Status Register

Register Name:

PWM_ISR

Access Type:

31

Read-only

30

29

12

4

28

20

11

3

CHID3

27

19

26

18

10

2

CHID2

23

15

22

14

21

13

28

20

12

27

19

11

26

18

10

7

6

5

4

3

CHID3

2

CHID2

1

CHID1

• CHIDx: Channel ID

0 = No new channel period has been achieved since the last read of the PWM_ISR register.

1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.

25

17

9

9

1

CHID1

25

17

Note: Reading PWM_ISR automatically clears CHIDx flags.

8

0

CHID0

24

16

24

16

8

0

CHID0

436

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AT91SAM7X256/128 Preliminary

34.6.9

PWM Channel Mode Register

Register Name:

PWM_CMRx

Access Type:

31

Read/Write

30

29

23

15

22

14

7

6

• CPRE: Channel Pre-scaler

21

13

5

12

4

28

20

11

3

27

19

26

18

10

CPD

2

CPRE

9

CPOL

1

25

17

CPRE Channel Pre-scaler

1

1

0

1

1

1

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

1

0

0

1

0

0

1

1

0

1

0

0

1

1

0

0

0

1

0

0

1

0

0

1

1

1

0

1

0

0

0

MCK

MCK/2

MCK/4

MCK/8

MCK/16

MCK/32

MCK/64

MCK/128

MCK/256

MCK/512

MCK/1024

CLKA

CLKB

Reserved Other

• CALG: Channel Alignment

0 = The period is left aligned.

1 = The period is center aligned.

• CPOL: Channel Polarity

0 = The output waveform starts at a low level.

1 = The output waveform starts at a high level.

• CPD: Channel Update Period

0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.

1 = Writing to the PWM_CUPDx will modify the period at the next period start event.

24

16

8

CALG

0

437

6120D–ATARM–02-Feb-06

34.6.10

PWM Channel Duty Cycle Register

Register Name:

PWM_

CDTY x

Access Type:

31

Read/Write

30 29 28 27 26 25

CDTY

23 22 21 20 19 18 17

CDTY

15 14 13 12 11 10 9

CDTY

7 6 5 4 3 2 1

CDTY

Only the first 16 bits (internal channel counter size) are significative.

• CDTY: Channel Duty Cycle

Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).

34.6.11

PWM Channel Period Register

Register Name:

PWM_CPRDx

Access Type:

31

Read/Write

30 29 28 27 26 25

CPRD

23 22 21 20 19 18 17

CPRD

15 14 13 12 11

CPRD

7 6 5 4

CPRD

Only the first 16 bits (internal channel counter size) are significative.

3

10

2

9

1

24

16

8

0

24

16

8

0

• CPRD: Channel Period

If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated:

– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,

256, 512, or 1024). The resulting period formula will be:

(

X

×

CPRD

MCK

)

– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:

438

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

(

CRPD

×

DIVA

MCK

)

or

(

CRPD

×

DIVAB

MCK

)

If the waveform is center-aligned, then the output waveform period depends on the counter source clockand can be calculated:

– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,

(

256, 512, or 1024). The resulting period formula will be:

2

X

×

CPRD

)

MCK

– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:

(

2

CPRD

×

DIVA

)

or

(

2

×

CPRD

× )

MCK MCK

6120D–ATARM–02-Feb-06

439

34.6.12

PWM Channel Counter Register

Register Name:

PWM_CCNTx

Access Type:

31

Read-only

30 29 28 27 26 25 24

CNT

23 22 21 20 19 18 17 16

CNT

15 14 13 12 11 10 9

CNT

7 6 5 4 3 2 1

CNT

• CNT: Channel Counter Register

Internal counter value. This register is reset when:

– the channel is enabled (writing CHIDx in the PWM_ENA register).

– the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.

34.6.13

PWM Channel Update Register

Register Name:

PWM_CUPDx

Access Type:

31

Write-only

30 29 28 27 26 25

CUPD

23 22 21 20 19 18 17

CUPD

8

0

24

16

15 14 13 12 11 10 9 8

CUPD

7 6 5 4 3 2 1 0

CUPD

This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.

Only the first 16 bits (internal channel counter size) are significative.

CPD (PWM_CMRx Register)

0

1

The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the beginning of the next period.

The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning of the next period.

440

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AT91SAM7X256/128 Preliminary

35. USB Device Port (UDP)

35.1

Description

The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification.

Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the

USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of

DPR.

Table 35-1.

USB Endpoint Description

3

4

1

3

5

Endpoint

Number

0

Mnemonic

EP0

EP1

EP2

EP3

EP4

EP5

Dual-Bank

No

Yes

Yes

No

Yes

Yes

Max. Endpoint Size

8

64

64

64

256

256

Endpoint Type

Control/Bulk/Interrupt

Bulk/Iso/Interrupt

Bulk/Iso/Interrupt

Control/Bulk/Interrupt

Bulk/Iso/Interrupt

Bulk/Iso/Interrupt

Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an interrupt. Depending on the product, an external signal can be used to send a wake-up to the USB host controller.

441

6120D–ATARM–02-Feb-06

35.2

Block Diagram

Figure 35-1. Block Diagram

Atmel Bridge

MCK

UDPCK

APB to

MCU

Bus udp_int f r a t e c e

U s

I e r n

USB Device

W r a p p e r

Dual

Port

RAM

FIFO e r p p

W r a

12 MHz

Serial

Interface

Engine

SIE txoen eopn txd rxdm rxd rxdp

Embedded

USB

Transceiver

DP

DM

Master Clock

Domain

Suspend/Resume Logic

Recovered 12 MHz

Domain external_resume

Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers.

The UDP peripheral requires two clocks: one peripheral clock used by the MCK domain and a

48 MHz clock used by the 12 MHz domain.

A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).

The signal external_resume is optional. It allows the UDP peripheral to wake-up once in system mode. The host is then notified that the device asks for a resume. This optional feature must be also negotiated with the host during the enumeration.

35.3

Product Dependencies

For further details on the USB Device hardware implementation, see the specific Product Properties document.

The USB physical transceiver is integrated into the product. The bidirectional differential signals

DP and DM are available from the product boundary.

Two I/O lines may be used by the application:

• One to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the board pull-up on DP must be disabled in order to prevent feeding current to the host.

• One to control the board pull-up on DP. Thus, when the device is ready to communicate with the host, it activates its DP pull-up through this control line.

442

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35.3.1

35.3.2

35.3.3

I/O Lines

DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the USB device peripheral.

To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to assign this I/O in input PIO mode.

To reserve an I/O line to control the board pull-up, the programmer must first program the PIO controller to assign this I/O in output PIO mode.

Power Management

The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of ± 0.25%.

Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz domain).

Interrupt

The USB device interface has an interrupt line connected to the Advanced Interrupt Controller

(AIC).

Handling the USB device interrupt requires programming the AIC before configuring the UDP.

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35.4

Typical Connection

Figure 35-2. Board Schematic to Interface USB Device Peripheral

15 k

PAm

UDP_CNX

22 k

3V3

1.5 k

47 k

UDP_PUP

PAn

System

Reset

27

33 pF

DM

DP

27

15 pF

15 pF

2 1

3

Type B

Connector

4

UDP_ CNX is an input signal used to check if the host is connected

UDP_ PUP is an output signal used to disable pull-up on DP by driving it to 0.

Figure 35-2

shows automatic activation of pull-up after reset.

100 nF

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35.5

Functional Description

35.5.1

USB V2.0 Full-speed Introduction

The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with an USB device through a set of communication flows.

Figure 35-3. Example of USB V2.0 Full-speed Communication Control

USB Host V2.0

Software Client 1 Software Client 2

Data Flow: Control Transfer

Data Flow: Isochronous In Transfer

Data Flow: Isochronous Out Transfer

EP0

EP1

EP2

USB Device 2.0

Block 1

Data Flow: Control Transfer

Data Flow: Bulk In Transfer

Data Flow: Bulk Out Transfer

EP0

EP4

EP5

USB Device 2.0

Block 2

35.5.1.1

USB V2.0 Full-speed Transfer Types

A communication flow is carried over one of four transfer types defined by the USB device.

Table 35-2.

USB Communication Flow

Transfer

Control

Direction

Bidirectional

Bandwidth

Not guaranteed

Isochronous

Interrupt

Bulk

Unidirectional

Unidirectional

Unidirectional

Guaranteed

Not guaranteed

Not guaranteed

Endpoint Size

8, 16, 32, 64

1 - 1023

8, 16, 32, 64

Error Detection

Yes

Yes

Yes

Yes

Retrying

Automatic

No

Yes

Yes

35.5.1.2

USB Bus Transactions

Each transfer results in one or more transactions over the USB bus. There are five kinds of transactions flowing across the bus in packets:

1.

Setup Transaction

2.

Data IN Transaction

3.

Data OUT Transaction

4.

Status IN Transaction

5.

Status OUT Transaction

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35.5.1.3

USB Transfer Event Definitions

As indicated below, transfers are sequential events carried out on the USB bus.

Table 35-3.

USB Transfer Events

Control Transfers

(1) (3)

Interrupt IN Transfer

(device toward host)

• Setup transaction > Data IN transactions >

Status OUT transaction

• Setup transaction > Data OUT transactions >

Status IN transaction

• Setup transaction > Status IN transaction

• Data IN transaction > Data IN transaction

• Data OUT transaction > Data OUT transaction

Interrupt OUT Transfer

(host toward device)

Isochronous IN Transfer

(2)

(device toward host)

Isochronous OUT Transfer

(2)

(host toward device)

• Data IN transaction > Data IN transaction

• Data OUT transaction > Data OUT transaction

Bulk IN Transfer

(device toward host)

• Data IN transaction > Data IN transaction

Bulk OUT Transfer

(host toward device)

• Data OUT transaction > Data OUT transaction

Notes: 1. Control transfer must use endpoints with no ping-pong attributes.

2. Isochronous transfers must use endpoints with ping-pong attributes.

3. Control transfers can be aborted using a stall handshake.

35.5.2

35.5.2.1

Handling Transactions with USB V2.0 Device Peripheral

Setup Transaction

Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next

Data IN transaction which follows the setup transaction. A status transaction ends the control transfer.

When a setup transfer is received by the USB endpoint:

• The USB device automatically acknowledges the setup packet

• RXSETUP is set in the UDP_ CSRx register

• An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint.

Thus, firmware must detect the RXSETUP polling the UDP_ CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data

OUT transfer and overwrite the setup packet in the FIFO.

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Figure 35-4. Setup Transaction Followed by a Data OUT Transaction

Setup Received Setup Handled by Firmware Data Out Received

USB

Bus Packets

Setup

PID

Data Setup

ACK

PID

Data OUT

PID

Data OUT

NAK

PID

Data OUT

PID

Data OUT

ACK

PID

RXSETUP Flag

Interrupt Pending

Set by USB Device Cleared by Firmware

Set by USB

Device Peripheral

RX_Data_BKO

(UDP_CSRx)

FIFO (DPR)

Content

35.5.2.2

35.5.2.3

XX Data Setup XX Data OUT

Data IN Transaction

Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes.

Using Endpoints Without Ping-pong Attributes

To perform a Data IN transaction using a non ping-pong endpoint:

1.

The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_ CSRx register (TXPKTRDY must be cleared).

2.

The microcontroller writes data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_ FDRx register,

3.

The microcontroller notifies the USB peripheral it has finished by setting the TXPK-

TRDY in the endpoint’s UDP_ CSRx register.

4.

The microcontroller is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_ CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set.

TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set.

Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the

Data IN protocol layer.

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Figure 35-5. Data IN Transfer for Non Ping-pong Endpoint

Prevous Data IN TX

Microcontroller Load Data in FIFO

USB Bus Packets Data IN

PID

Data IN 1

ACK

PID

Data IN

PID

NAK

PID

Data IN

PID

Data is Sent on USB Bus

Data IN 2

ACK

PID

TXPKTRDY Flag

(UDP_CSRx)

TXCOMP Flag

(UDP_CSRx)

FIFO (DPR)

Content

Cleared by USB Device

Interrupt Pending

Set by the Firmware

Data Payload Written in FIFO

Cleared by Firmware

Start to Write Data

Payload in FIFO

Data IN 1 Load In Progress Data IN 2

Interrupt Pending

Load In

Progress

35.5.2.4

Using Endpoints With Ping-pong Attribute

The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. To be able to guarantee a constant bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the

USB device.

Figure 35-6. Bank Swapping Data IN Transfer for Ping-pong Endpoints

Microcontroller

USB Device USB Bus

1st Data Payload

Write

Bank 0

Endpoint 1

Read

Read and Write at the Same Time

2nd Data Payload

Bank 1

Endpoint 1

Bank 0

Endpoint 1

Data IN Packet

1st Data Payload

3rd Data Payload

Bank 0

Endpoint 1

Bank 1

Endpoint 1

Data IN Packet

2nd Data Payload

Bank 0

Endpoint 1

Data IN Packet

3rd Data Payload

When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions:

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1.

The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_ CSRx register.

2.

The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_ FDRx register.

3.

The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the

FIFO by setting the TXPKTRDY in the endpoint’s UDP_ CSRx register.

4.

Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_ FDRx register.

5.

The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_ CSRx register is set. An interrupt is pending while TXCOMP is being set.

6.

Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent rising TXPKTRDY in the endpoint’s UDP_ CSRx register.

7.

At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent

.

Figure 35-7. Data IN Transfer for Ping-pong Endpoint

USB Bus

Packets

Microcontroller

Load Data IN Bank 0

Microcontroller Load Data IN Bank 1

USB Device Send Bank 0

Data IN

PID

Data IN

ACK

PID

Data IN

PID

Microcontroller Load Data IN Bank 0

USB Device Send Bank 1

Data IN

ACK

PID

TXPKTRDY Flag

(UDP_MCSRx)

TXCOMP Flag

(UDP_CSRx)

Cleared by USB Device,

Data Payload Fully Transmitted

Set by Firmware,

Data Payload Written in FIFO Bank 0

Set by USB

Device

Set by Firmware,

Data Payload Written in FIFO Bank 1

Interrupt Pending

Interrupt Cleared by Firmware

Set by USB Device

FIFO (DPR)

Bank 0

Written by

Microcontroller

Read by USB Device

Written by

Microcontroller

FIFO (DPR)

Bank 1

Written by

Microcontroller

Read by USB Device

6120D–ATARM–02-Feb-06

Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set is too long, some Data IN packets may be NACKed, reducing the bandwidth.

449

35.5.2.5

Data OUT Transaction

Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes.

35.5.2.6

Data OUT Transaction Without Ping-pong Attributes

To perform a Data OUT transaction, using a non ping-pong endpoint:

1.

The host generates a Data OUT packet.

2.

This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host.

3.

The microcontroller is notified that the USB device has received a data payload polling

RX_DATA_BK0 in the endpoint’s UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.

4.

The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_ CSRx register.

5.

The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available by reading the endpoint’s UDP_ FDRx register.

6.

The microcontroller notifies the USB device that it has finished the transfer by clearing

RX_DATA_BK0 in the endpoint’s UDP_ CSRx register.

7.

A new Data OUT packet can be accepted by the USB device.

Figure 35-8. Data OUT Transfer for Non Ping-pong Endpoints

Host Sends Data Payload

Microcontroller Transfers Data

Host Sends the Next Data Payload Host Resends the Next Data Payload

USB Bus

Packets

Data OUT

PID

Data OUT 1

ACK

PID

Data OUT2

PID

Data OUT2

NAK

PID

Data OUT

PID

Data OUT2

ACK

PID

RX_DATA_BK0

(UDP_CSRx)

FIFO (DPR)

Content

Data OUT 1

Written by USB Device

Interrupt Pending

Set by USB Device

Data OUT 1

Microcontroller Read

Cleared by Firmware,

Data Payload Written in FIFO

Data OUT 2

Written by USB Device

An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO.

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35.5.2.7

AT91SAM7X256/128 Preliminary

Using Endpoints With Ping-pong Attributes

During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device.

Figure 35-9. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints

Microcontroller

Write

USB Device

Write and Read at the Same Time

Read

Bank 0

Endpoint 1

1st Data Payload

Bank 0

Endpoint 1

Bank 1

Endpoint 1

2nd Data Payload

Bank 1

Endpoint 1

Bank 0

Endpoint 1

3rd Data Payload

Bank 0

Endpoint 1

USB Bus

Data IN Packet

1st Data Payload

Data IN Packet

2nd Data Payload

Data IN Packet

3rd Data Payload

When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions:

1.

The host generates a Data OUT packet.

2.

This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO

Bank 0.

3.

The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1.

4.

The microcontroller is notified that the USB device has received a data payload, polling

RX_DATA_BK0 in the endpoint’s UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.

5.

The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_ CSRx register.

6.

The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s

UDP_ FDRx register.

7.

The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_ CSRx register.

8.

A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0.

9.

If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint’s UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set.

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10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s UDP_

FDRx register.

11. The microcontroller notifies the USB device it has finished the transfer by clearing

RX_DATA_BK1 in the endpoint’s UDP_ CSRx register.

12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO

Bank 0.

Figure 35-10. Data OUT Transfer for Ping-pong Endpoint

Host Sends First Data Payload

Microcontroller Reads Data 1 in Bank 0,

Host Sends Second Data Payload

Microcontroller Reads Data2 in Bank 1,

Host Sends Third Data Payload

USB Bus

Packets

Data OUT

PID

Data OUT 1

ACK

PID

Data OUT

PID

Data OUT 2

ACK

PID

Data OUT

PID

Data OUT 3

A

P

Cleared by Firmware

RX_DATA_BK0 Flag

(UDP_CSRx)

Set by USB Device,

Data Payload Written in FIFO Endpoint Bank 0

RX_DATA_BK1 Flag

(UDP_CSRx)

Interrupt Pending

Set by USB Device,

Data Payload Written in FIFO Endpoint Bank 1

Interrupt Pending

Cleared by Firmware

FIFO (DPR)

Bank 0

Data OUT1

Write by USB Device

Data OUT 1

Read By Microcontroller

Data OUT 3

Write In Progress

FIFO (DPR)

Bank 1

Data OUT 2

Write by USB Device

Data OUT 2

Read By Microcontroller

Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set.

Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set.

35.5.2.8

Status Transaction

A status transaction is a special type of host-to-device transaction used only in a control transfer.

The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction.

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Figure 35-11. Control Read and Write Sequences

Setup Stage Data Stage Status Stage

Control Read

Setup TX

Setup Stage

Data OUT TX Data OUT TX

Data Stage

Status IN TX

Status Stage

Control Write

Setup TX

Setup Stage

Data IN TX

Status Stage

Data IN TX

Status OUT TX

No Data

Control

Setup TX Status IN TX

35.5.2.9

Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specifi-

cation, Rev. 2.0, for more information on the protocol layer.

2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data).

Status IN Transfer

Once a control request has been processed, the device returns a status to the host. This is a zero length Data IN transaction.

1.

The microcontroller waits for TXPKTRDY in the UDP_ CSRx endpoint’s register to be cleared. (At this step, TXPKTRDY must be cleared because the previous transaction was a setup transaction or a Data OUT transaction.)

2.

Without writing anything to the UDP_ FDRx endpoint’s register, the microcontroller sets

TXPKTRDY. The USB device generates a Data IN packet using DATA1 PID.

3.

This packet is acknowledged by the host and TXPKTRDY is set in the UDP_ CSRx endpoint’s register.

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Figure 35-12. Data Out Followed by Status IN Transfer.

Host Sends the Last

Data Payload to the Device

Device Sends a Status IN to the Host

USB Bus

Packets

Data OUT

PID

Data OUT

NAK

PID

Data IN

PID

ACK

PID

Interrupt Pending

Cleared by Firmware

RX_DATA_BKO

(UDP_CSRx)

Set by USB Device

TXPKTRDY

(UDP_CSRx)

Set by Firmware

Cleared by USB Device

35.5.2.10

Status OUT Transfer

Once a control request has been processed and the requested data returned, the host acknowledges by sending a zero length packet. This is a zero length Data OUT transaction.

1.

The USB device receives a zero length packet. It sets RX_DATA_BK0 flag in the UDP_

CSRx register and acknowledges the zero length packet.

2.

The microcontroller is notified that the USB device has received a zero length packet sent by the host polling RX_DATA_BK0 in the UDP_ CSRx register. An interrupt is pending while RX_DATA_BK0 is set. The number of bytes received in the endpoint’s

UDP_ BCR register is equal to zero.

3.

The microcontroller must clear RX_DATA_BK0.

Figure 35-13. Data IN Followed by Status OUT Transfer

Device Sends the Last

Data Payload to Host

Device Sends a

Status OUT to Host

USB Bus

Packets

Data IN

PID

Data IN

ACK

PID

Data OUT

PID

ACK

PID

Interrupt Pending

RX_DATA_BKO

(UDP_CSRx)

Set by USB Device

Cleared by Firmware

TXCOMP

(UDP_CSRx)

Set by USB Device Cleared by Firmware

35.5.2.11

Stall Handshake

A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)

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• A functional stall is used when the halt feature associated with the endpoint is set. (Refer to

Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.)

• To abort the current request, a protocol stall is used, but uniquely with control transfer.

The following procedure generates a stall packet:

1.

The microcontroller sets the FORCESTALL flag in the UDP_ CSRx endpoint’s register.

2.

The host receives the stall packet.

3.

The microcontroller is notified that the device has sent the stall by polling the

STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt.

When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set.

Figure 35-14. Stall Handshake (Data IN Transfer)

USB Bus

Packets

Data IN PID Stall PID

FORCESTALL

STALLSENT

Set by Firmware

Cleared by Firmware

Interrupt Pending

Cleared by Firmware

Set by

USB Device

Figure 35-15. Stall Handshake (Data OUT Transfer)

USB Bus

Packets

Data OUT PID

Data OUT Stall PID

FORCESTALL

Set by Firmware

Interrupt Pending

STALLSENT

Set by USB Device

Cleared by Firmware

455

35.5.3

Controlling Device States

A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Speci-

fication, Rev 2.0.

Figure 35-16. USB Device State Diagram

Attached

Hub Reset or

Deconfigured

Hub

Configured

Bus Inactive

Powered

Bus Activity

Power

Interruption

Reset

Reset

Bus Inactive

Default

Bus Activity

Address

Assigned

Bus Inactive

Address

Bus Activity

Device

Deconfigured

Device

Configured

Bus Inactive

Configured

Bus Activity

Suspended

Suspended

Suspended

Suspended

Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0).

After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 uA on the USB bus.

While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a

USB mouse.

The wake-up feature is not mandatory for all devices and must be negotiated with the host.

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35.5.3.1

35.5.3.2

35.5.3.3

35.5.3.4

35.5.3.5

35.5.3.6

AT91SAM7X256/128 Preliminary

From Powered State to Default State

After its connection to a USB host, the USB device waits for an end-of-bus reset. The USB host stops driving a reset state once it has detected the device’s pull-up on DP. The unmasked flag

ENDBURSES is set in the register UDP_ISR and an interrupt is triggered. The UDP software enables the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer.

From Default State to Address State

After a set address standard device request, the USB host peripheral enters the address state.

Before this, it achieves the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared.

To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STATE, sets its new address, and sets the FEN bit in the UDP_FADDR register.

From Address State to Configured State

Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the

EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register.

Enabling Suspend

When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the

UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register.

This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode.

As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board.

The USB device peripheral clocks may be switched off. However, the transceiver and the USB peripheral must not be switched off, otherwise the resume is not detected.

Receiving a Host Resume

In suspend mode, the USB transceiver and the USB peripheral must be powered to detect the

RESUME. However, the USB device peripheral may not be clocked as the WAKEUP signal is asynchronous.

Once the resume is detected on the bus, the signal WAKEUP in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register.

Sending an External Resume

The External Resume is negotiated with the host and enabled by setting the ESR bit in the

UDP_ GLB_STATE. An asynchronous event on the ext_resume_pin of the peripheral generates a WAKEUP interrupt. On early versions of the USP peripheral, the K-state on the USB line is generated immediately. This means that the USB device must be able to answer to the host very

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quickly. On recent versions, the software sets the RMWUPE bit in the UDP_GLB_STATE register once it is ready to communicate with the host. The K-state on the bus is then generated.

The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register.

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35.6

USB Device Port (UDP) User Interface

Table 35-4.

UDP Memory Map

Offset

0x000

0x004

0x008

0x00C

0x010

0x014

0x018

0x01C

0x020

0x024

0x028

0x02C

0x030

.

.

.

See Notes:

(1)

0x050

Register

Frame Number Register

Global State Register

Function Address Register

Reserved

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Interrupt Status Register

Interrupt Clear Register

Reserved

Reset Endpoint Register

Reserved

.

.

.

Endpoint 0 Control and Status Register

Endpoint 5 Control and Status Register

Endpoint 0 FIFO Data Register

Name

UDP_ FRM_NUM

UDP_ GLB_STAT

UDP_ FADDR

UDP_ IER

UDP_ IDR

UDP_ IMR

UDP_ ISR

UDP_ ICR

UDP_ RST_EP

UDP_CSR0

Access

Read

Read/Write

Read/Write

Write

Write

Read

Read

Write

Read/Write

Read/Write

UDP_CSR5

UDP_ FDR0

Read/Write

Read/Write

.

.

.

See Notes:

(2)

0x070

0x074

.

.

.

Endpoint 5 FIFO Data Register

Reserved

Transceiver Control Register

UDP_ FDR5

UDP_ TXVC

Read/Write

Read/Write

0x078 - 0xFC Reserved – –

Notes: 1. The addresses of the UDP_ CSRx registers are calculated as: 0x030 + 4(Endpoint Number - 1).

2. The addresses of the UDP_ FDRx registers are calculated as: 0x050 + 4(Endpoint Number - 1).

Reset State

0x0000_0000

0x0000_0010

0x0000_0100

0x0000_1200

0x0000_XX00

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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6120D–ATARM–02-Feb-06

35.6.1

UDP Frame Number Register

Register Name:

UDP_ FRM_NUM

Access Type:

31

---

Read-only

30

---

29

---

23

15

22

14

21

13

28

---

20

12

27

---

19

11

26

---

18

10

25

---

17

FRM_OK

9

FRM_NUM

24

---

16

FRM_ERR

8

7 6 5 4

FRM_NUM

3 2 1 0

• FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats

This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.

Value Updated at the SOF_EOP (Start of Frame End of Packet).

• FRM_ERR: Frame Error

This bit is set at SOF_EOP when the SOF packet is received containing an error.

This bit is reset upon receipt of SOF_PID.

• FRM_OK: Frame OK

This bit is set at SOF_EOP when the SOF packet is received without any error.

This bit is reset upon receipt of SOF_PID (Packet Identification).

In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for

EOP.

Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L.

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35.6.2

UDP Global State Register

Register Name:

UDP_ GLB_STAT

Access Type:

31

Read/Write

30

29

23

22

21

28

20

27

19

26

18

25

17

24

16

15

7

14

6

13

5

12

4

RMWUPE

11

3

RSMINPR

10

2

ESR

9

1

CONFG

8

0

FADDEN

This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0.

• FADDEN: Function Address Enable

Read:

0 = Device is not in address state.

1 = Device is in address state.

Write:

0 = No effect, only a reset can bring back a device to the default state.

1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_ FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting

FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.

• CONFG: Configured

Read:

0 = Device is not in configured state.

1 = Device is in configured state.

Write:

0 = Sets device in a non configured state

1 = Sets device in configured state.

The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.

• ESR: Enable Send Resume

0 = Disables the Remote Wake Up sequence.

1 = Remote Wake Up can be processed and the pin send_resume is enabled.

• RSMINPR: A Resume Has Been Sent to the Host

Read:

0 = No effect.

1 = A Resume has been received from the host during Remote Wake Up feature.

461

6120D–ATARM–02-Feb-06

• RMWUPE: Remote Wake Up Enable

0 = Must be cleared after receiving any HOST packet or SOF interrupt.

1 = Enables the K-state on the USB cable if ESR is enabled.

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35.6.3

UDP Function Address Register

Register Name:

UDP_ FADDR

Access Type:

31

Read/Write

30

29

23

22

21

28

20

27

19

26

18

25

17

24

16

15

14

13

12

11

10

9

1

8

FEN

0 7

6 5 4 3

FADD

2

• FADD[6:0]: Function Address Value

The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification,

Rev. 2.0 for more information. After power up or reset, the function address value is set to 0.

• FEN: Function Enable

Read:

0 = Function endpoint disabled.

1 = Function endpoint enabled.

Write:

0 = Disables function endpoint.

1 = Default value.

The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host.

463

6120D–ATARM–02-Feb-06

35.6.4

UDP Interrupt Enable Register

Register Name:

UDP_ IER

Access Type:

31

Write-only

30

29

23

15

22

14

21

13

WAKEUP

7

6

5

EP5INT

• EP0INT: Enable Endpoint 0 Interrupt

• EP1INT: Enable Endpoint 1 Interrupt

• EP2INT: Enable Endpoint 2Interrupt

• EP3INT: Enable Endpoint 3 Interrupt

• EP4INT: Enable Endpoint 4 Interrupt

• EP5INT: Enable Endpoint 5 Interrupt

0 = No effect.

1 = Enables corresponding Endpoint Interrupt.

• RXSUSP: Enable UDP Suspend Interrupt

0 = No effect.

1 = Enables UDP Suspend Interrupt.

• RXRSM: Enable UDP Resume Interrupt

0 = No effect.

1 = Enables UDP Resume Interrupt.

• EXTRSM: Enable External Resume Interrupt

0 = No effect.

1 = Enables External Resume Interrupt.

• SOFINT: Enable Start Of Frame Interrupt

0 = No effect.

1 = Enables Start Of Frame Interrupt.

• WAKEUP: Enable UDP bus Wakeup Interrupt

0 = No effect.

1 = Enables USB bus Interrupt.

4

EP4INT

28

20

12

27

19

11

SOFINT

3

EP3INT

26

18

10

EXTRSM

2

EP2INT

25

17

9

RXRSM

1

EP1INT

24

16

8

RXSUSP

0

EP0INT

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35.6.5

UDP Interrupt Disable Register

Register Name:

UDP_ IDR

Access Type:

31

Write-only

30

29

23

15

22

14

21

13

WAKEUP

7

6

5

EP5INT

• EP0INT: Disable Endpoint 0 Interrupt

• EP1INT: Disable Endpoint 1 Interrupt

• EP2INT: Disable Endpoint 2 Interrupt

• EP3INT: Disable Endpoint 3 Interrupt

• EP4INT: Disable Endpoint 4 Interrupt

• EP5INT: Disable Endpoint 5 Interrupt

0 = No effect.

1 = Disables corresponding Endpoint Interrupt.

• RXSUSP: Disable UDP Suspend Interrupt

0 = No effect.

1 = Disables UDP Suspend Interrupt.

• RXRSM: Disable UDP Resume Interrupt

0 = No effect.

1 = Disables UDP Resume Interrupt.

• EXTRSM: Disable External Resume Interrupt

0 = No effect.

1 = Disables External Resume Interrupt.

• SOFINT: Disable Start Of Frame Interrupt

0 = No effect.

1 = Disables Start Of Frame Interrupt

• WAKEUP: Disable USB Bus Interrupt

0 = No effect.

1 = Disables USB Bus Wakeup Interrupt.

4

EP4INT

28

20

12

AT91SAM7X256/128 Preliminary

27

19

11

SOFINT

3

EP3INT

26

18

10

EXTRSM

2

EP2INT

25

17

9

RXRSM

1

EP1INT

24

16

8

RXSUSP

0

EP0INT

465

6120D–ATARM–02-Feb-06

35.6.6

UDP Interrupt Mask Register

Register Name:

UDP_ IMR

Access Type:

31

Read-only

30

29

23

22

21

28

20

27

19

26

18

25

17

24

16

15

7

14

6

13

WAKEUP

5

EP5INT

12

4

EP4INT

11

SOFINT

3

EP3INT

10

EXTRSM

2

EP2INT

9

RXRSM

1

EP1INT

8

RXSUSP

0

EP0INT

• EP0INT: Mask Endpoint 0 Interrupt

• EP1INT: Mask Endpoint 1 Interrupt

• EP2INT: Mask Endpoint 2 Interrupt

• EP3INT: Mask Endpoint 3 Interrupt

• EP4INT: Mask Endpoint 4 Interrupt

• EP5INT: Mask Endpoint 5 Interrupt

0 = Corresponding Endpoint Interrupt is disabled.

1 = Corresponding Endpoint Interrupt is enabled.

• RXSUSP: Mask UDP Suspend Interrupt

0 = UDP Suspend Interrupt is disabled.

1 = UDP Suspend Interrupt is enabled.

• RXRSM: Mask UDP Resume Interrupt.

0 = UDP Resume Interrupt is disabled.

1 = UDP Resume Interrupt is enabled.

• EXTRSM: Mask External Resume Interrupt

0 = External Resume Interrupt is disabled.

1 = External Resume Interrupt is enabled.

• SOFINT: Mask Start Of Frame Interrupt

0 = Start of Frame Interrupt is disabled.

1 = Start of Frame Interrupt is enabled.

• WAKEUP: USB Bus WAKEUP Interrupt

0 = USB Bus Wakeup Interrupt is disabled.

1 = USB Bus Wakeup Interrupt is enabled.

Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_ IMR is enabled.

466

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AT91SAM7X256/128 Preliminary

35.6.7

UDP Interrupt Status Register

Register Name:

UDP_ ISR

Access Type:

31

Read-only

30

29

23

15

22

14

21

13

WAKEUP

28

20

12

ENDBUSRE

S

27

19

11

SOFINT

26

18

10

EXTRSM

25

17

9

RXRSM

24

16

8

RXSUSP

7

6

5

EP5INT

4

EP4INT

3

EP3INT

2

EP2INT

1

EP1INT

0

EP0INT

• EP0INT: Endpoint 0 Interrupt Status

0 = No Endpoint0 Interrupt pending.

1 = Endpoint0 Interrupt has been raised.

Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR0:

RXSETUP set to 1

RX_DATA_BK0 set to 1

RX_DATA_BK1 set to 1

TXCOMP set to 1

STALLSENT set to 1

EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_ CSR0 bit.

• EP1INT: Endpoint 1 Interrupt Status

0 = No Endpoint1 Interrupt pending.

1 = Endpoint1 Interrupt has been raised.

Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR1:

RXSETUP set to 1

RX_DATA_BK0 set to 1

RX_DATA_BK1 set to 1

TXCOMP set to 1

STALLSENT set to 1

EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding UDP_ CSR1 bit.

• EP2INT: Endpoint 2 Interrupt Status

0 = No Endpoint2 Interrupt pending.

1 = Endpoint2 Interrupt has been raised.

Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR2:

RXSETUP set to 1

RX_DATA_BK0 set to 1

RX_DATA_BK1 set to 1

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6120D–ATARM–02-Feb-06

TXCOMP set to 1

STALLSENT set to 1

EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding UDP_ CSR2 bit.

• EP3INT: Endpoint 3 Interrupt Status

0 = No Endpoint3 Interrupt pending.

1 = Endpoint3 Interrupt has been raised.

Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR3:

RXSETUP set to 1

RX_DATA_BK0 set to 1

RX_DATA_BK1 set to 1

TXCOMP set to 1

STALLSENT set to 1

EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding UDP_ CSR3 bit.

• EP4INT: Endpoint 4 Interrupt Status

0 = No Endpoint4 Interrupt pending.

1 = Endpoint4 Interrupt has been raised.

Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR4:

RXSETUP set to 1

RX_DATA_BK0 set to 1

RX_DATA_BK1 set to 1

TXCOMP set to 1

STALLSENT set to 1

EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding UDP_ CSR4 bit.

• EP5INT: Endpoint 5 Interrupt Status

0 = No Endpoint5 Interrupt pending.

1 = Endpoint5 Interrupt has been raised.

Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR5:

RXSETUP set to 1

RX_DATA_BK0 set to 1

RX_DATA_BK1 set to 1

TXCOMP set to 1

STALLSENT set to 1

EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding UDP_ CSR5 bit.

• RXSUSP: UDP Suspend Interrupt Status

0 = No UDP Suspend Interrupt pending.

1 = UDP Suspend Interrupt has been raised.

The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.

• RXRSM: UDP Resume Interrupt Status

0 = No UDP Resume Interrupt pending.

1 =UDP Resume Interrupt has been raised.

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The USB device sets this bit when a UDP resume signal is detected at its port.

After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ ICR register.

• EXTRSM: External Resume Interrupt Status

0 = No External Resume Interrupt pending.

1 = External Resume Interrupt has been raised.

This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected.

If RMWUPE = 1, a resume state is sent in the USB bus.

• SOFINT: Start of Frame Interrupt Status

0 = No Start of Frame Interrupt pending.

1 = Start of Frame Interrupt has been raised.

This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.

• ENDBUSRES: End of BUS Reset Interrupt Status

0 = No End of Bus Reset Interrupt pending.

1 = End of Bus Reset Interrupt has been raised.

This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration.

• WAKEUP: UDP Resume Interrupt Status

0 = No Wakeup Interrupt pending.

1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.

After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ ICR register.

469

6120D–ATARM–02-Feb-06

35.6.8

UDP Interrupt Clear Register

Register Name:

UDP_ ICR

Access Type:

31

Write-only

30

29

23

15

22

14

21

13

WAKEUP

28

20

12

ENDBURSES

7

6

5

• RXSUSP: Clear UDP Suspend Interrupt

0 = No effect.

1 = Clears UDP Suspend Interrupt.

• RXRSM: Clear UDP Resume Interrupt

0 = No effect.

1 = Clears UDP Resume Interrupt.

• EXTRSM: Clear External Resume Interrupt

0 = No effect.

1 = Clears External Resume Interrupt.

• SOFINT: Clear Start Of Frame Interrupt

0 = No effect.

1 = Clears Start Of Frame Interrupt.

• ENDBURSES: Clear End of Bus Reset Interrupt

0 = No effect.

1 = Clears End of Bus Reset Interrupt.

• WAKEUP: Clear Wakeup Interrupt

0 = No effect.

1 = Clears Wakeup Interrupt.

4

27

19

11

SOFINT

3

26

18

10

EXTRSM

2

25

17

9

RXRSM

1

24

16

8

RXSUSP

0

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AT91SAM7X256/128 Preliminary

35.6.9

UDP Reset Endpoint Register

Register Name:

UDP_ RST_EP

Access Type:

31

Read/Write

30

29

23

22

21

28

20

27

19

26

18

25

17

24

16

15

7

14

6

13

5

EP5

12

4

EP4

11

3

EP3

10

2

EP2

9

1

EP1

8

0

EP0

• EP0: Reset Endpoint 0

• EP1: Reset Endpoint 1

• EP2: Reset Endpoint 2

• EP3: Reset Endpoint 3

• EP4: Reset Endpoint 4

• EP5: Reset Endpoint 5

This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter

5.8.5 in the USB Serial Bus Specification, Rev.2.0.

Warning: This flag must be cleared at the end of the reset. It does not clear UDP_ CSRx flags.

0 = No reset.

1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_ CSRx register.

471

6120D–ATARM–02-Feb-06

35.6.10

UDP Endpoint Control and Status Register

Register Name:

UDP_ CSRx [x = 0..5]

Access Type:

31

Read/Write

30

29

28

23

15

EPEDS

22

14

21

13

27

20

RXBYTECNT

19

12

11

DTGLE

26

18

25

RXBYTECNT

17

24

16

10 9

EPTYPE

8

7

DIR

6

RX_DATA_

BK1

5

FORCE

STALL

4

TXPKTRDY

3

STALLSENT

ISOERROR

2

RXSETUP

1

RX_DATA_

BK0

0

TXCOMP

• TXCOMP: Generates an IN packet with data previously written in the DPR

This flag generates an interrupt while it is set to one.

Write (Cleared by the firmware):

0 = Clear the flag, clear the interrupt.

1 = No effect.

Read (Set by the USB peripheral):

0 = Data IN transaction has not been acknowledged by the Host.

1 = Data IN transaction is achieved, acknowledged by the Host.

After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction.

• RX_DATA_BK0: Receive Data Bank 0

This flag generates an interrupt while it is set to one.

Write (Cleared by the firmware):

0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0.

1 = No effect.

Read (Set by the USB peripheral):

0 = No data packet has been received in the FIFO's Bank 0

1 = A data packet has been received, it has been stored in the FIFO's Bank 0.

When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0.

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• RXSETUP: Sends STALL to the Host (Control Endpoints)

This flag generates an interrupt while it is set to one.

Read:

0 = No setup packet available.

1 = A setup data packet has been sent by the host and is available in the FIFO.

Write:

0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO.

1 = No effect.

This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_

FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware.

Ensuing Data OUT transaction is not accepted while RXSETUP is set.

• STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints) / ISOERROR (Isochronous Endpoints)

This flag generates an interrupt while it is set to one.

STALLSENT: This ends a STALL handshake.

Read:

0 = The host has not acknowledged a STALL.

1 = Host has acknowledged the stall.

Write:

0 = Resets the STALLSENT flag, clears the interrupt.

1 = No effect.

This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains.

Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake.

ISOERROR: A CRC error has been detected in an isochronous transfer.

Read:

0 = No error in the previous isochronous transfer.

1 = CRC error has been detected, data available in the FIFO are corrupted.

Write:

0 = Resets the ISOERROR flag, clears the interrupt.

1 = No effect.

• TXPKTRDY: Transmit Packet Ready

This flag is cleared by the USB device.

This flag is set by the USB device firmware.

Read:

0 = Data values can be written in the FIFO.

1 = Data values can not be written in the FIFO.

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6120D–ATARM–02-Feb-06

Write:

0 = No effect.

1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent.

This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_ FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host.

• FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints)

Write-only

0 = No effect.

1 = Sends STALL to the host.

Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake.

Control endpoints: During the data stage and status stage, this indicates that the microcontroller cannot complete the request.

Bulk and interrupt endpoints: Notifies the host that the endpoint is halted.

The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.

• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes)

This flag generates an interrupt while it is set to one.

Write (Cleared by the firmware):

0 = Notifies USB device that data have been read in the FIFO’s Bank 1.

1 = No effect.

Read (Set by the USB peripheral):

0 = No data packet has been received in the FIFO's Bank 1.

1 = A data packet has been received, it has been stored in FIFO's Bank 1.

When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1.

• DIR: Transfer Direction (only available for control endpoints)

Read/Write

0 = Allows Data OUT transactions in the control data stage.

1 = Enables Data IN transactions in the control data stage.

Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage.

This bit must be set before UDP_ CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage.

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• EPTYPE[2:0]: Endpoint Type

Read/Write

000

001

101

010

110

011

111

Control

Isochronous OUT

Isochronous IN

Bulk OUT

Bulk IN

Interrupt OUT

Interrupt IN

• DTGLE: Data Toggle

Read-only

0 = Identifies DATA0 packet.

1 = Identifies DATA1 packet.

Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.

• EPEDS: Endpoint Enable Disable

Read:

0 = Endpoint disabled.

1 = Endpoint enabled.

Write:

0 = Disables endpoint.

1 = Enables endpoint.

• RXBYTECNT[10:0]: Number of Bytes Available in the FIFO

Read-only

When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_ FDRx register.

475

6120D–ATARM–02-Feb-06

35.6.11

UDP FIFO Data Register

Register Name:

UDP_ FDRx [x = 0..5]

Access Type:

31

Read/Write

30

29

23

22

21

28

20

27

19

26

18

25

17

24

16

15

14

13

12

11

10

9

1

8

0 7 6 5 4

FIFO_DATA

3 2

• FIFO_DATA[7:0]: FIFO Data Value

The microcontroller can push or pop values in the FIFO through this register.

RXBYTECNT in the corresponding UDP_ CSRx register is the number of bytes to be read from the FIFO (sent by the host).

The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information.

35.6.12

UDP Transceiver Control Register

Register Name:

UDP_ TXVC

Access Type:

31

Read/Write

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

TXVDIS

7

6

5

4

3

2

1

0

• TXVDIS: Transceiver Disable

When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field.

To enable the transceiver, TXVDIS must be cleared.

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36. Analog-to-digital Converter (ADC)

36.1

Overview

The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates an 8-to-1 analog multiplexer, making possible the analog-todigital conversions of up to eight analog lines. The conversions extend from 0V to ADVREF.

The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable.

The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These features reduce both power consumption and processor intervention.

Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time.

36.2

Block Diagram

Figure 36-1. Analog-to-Digital Converter Block Diagram

Timer

Counter

Channels

ADC

ADTRG

Trigger

Selection

ADC Interrupt

Control

Logic

AIC

VDDANA

ADVREF

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

PIO

Successive

Approximation

Register

Analog-to-Digital

Converter

User

Interface

PDC

ASB

Peripheral Bridge

APB

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36.3

Signal Description

Table 36-1.

ADC Pin Description

Pin Name Description

VDDIN

ADVREF

AD0 - AD 7

ADTRG

Analog power supply

Reference voltage

Analog input channels

External trigger

36.4

Product Dependencies

36.4.1

Power Management

The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the

ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into Sleep Mode, the Power Management Controller has no effect on the ADC behavior.

36.4.2

36.4.3

36.4.4

36.4.5

36.4.6

Interrupt Sources

The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt

Controller. Using the ADC interrupt requires the AIC to be programmed first.

Analog Inputs

The pins AD0 to AD7 can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND.

I/O Lines

The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function.

Timer Triggers

Timer Counters may or may not be used as hardware triggers depending on user requirements.

Thus, some or all of the timer counters may be non-connected.

Conversion Performances

For performance and electrical characteristics of the ADC, see Section 39.7 ”ADC Characteristics”, on page 606 .

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36.5

Functional Description

36.5.1

Analog-to-digital Conversion

The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-

bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the ”ADC

Mode Register” on page 485

and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR).

The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to

63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in the Product definition section.

36.5.2

36.5.3

36.5.4

Conversion Reference

The conversion is performed on a full range between 0V and the reference voltage pin ADVREF.

Analog inputs between these voltages convert to values based on a linear conversion.

Conversion Resolution

The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit

LOWRES in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the bit LOWRES, the

ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding

ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.

Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized.

Conversion Results

When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data

Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register

(ADC_LCDR).

The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either

EOC and DRDY can trigger an interrupt.

Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit and the EOC bit corresponding to the last converted channel.

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Figure 36-2. EOCx and DRDY Flag Behavior

Write the ADC_CR

with START = 1

Read the ADC_CDRx

Write the ADC_CR

with START = 1

CHx

(ADC_CHSR)

EOCx

(ADC_SR)

Conversion Time

Conversion Time

Read the ADC_LCDR

DRDY

(ADC_SR)

If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (ADC_SR).

In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun

Error) in ADC_SR.

The OVRE and GOVRE flags are automatically cleared when ADC_SR is read.

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Figure 36-3. GOVRE and OVREx Flag Behavior

ADTRG

CH0

(ADC_CHSR)

CH1

(ADC_CHSR)

ADC_LCDR

ADC_CDR0

ADC_CDR1

Undefined Data

Undefined Data

Undefined Data

Data A

Conversion

EOC0

(ADC_SR)

EOC1

(ADC_SR)

Conversion

Data A

Data B

Conversion

Data B

Read ADC_SR

Data C

Data C

Read ADC_CDR0

Read ADC_CDR1

GOVRE

(ADC_SR)

DRDY

(ADC_SR)

OVRE0

(ADC_SR)

36.5.5

Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.

Conversion Triggers

Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1.

The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRG-

SEL in the Mode Register (ADC_MR). The selected hardware trigger is enabled with the bit

TRGEN in the Mode Register (ADC_MR).

If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode.

Only one start command is necessary to initiate a conversion sequence on all the channels. The

ADC hardware logic automatically performs the conversions on the active channels, then waits

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36.5.6

36.5.7

for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers enable the analog channels to be enabled or disabled independently.

If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly.

Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger.

Sleep Mode and Conversion Sequencer

The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by setting the bit SLEEP in the Mode

Register ADC_MR.

The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption.

When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account.

The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the PDC.

Note: The reference voltage pins always remain connected in normal mode as in sleep mode.

ADC Timings

Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register ADC_MR.

In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR.

Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the SHTIM field. See the section DC

Characteristics in the product datasheet.

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36.6

Analog-to-digital Converter (ADC) User Interface

Table 36-2.

Analog-to-Digital Converter (ADC) Register Mapping

Offset Register

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x40

0x44

0x48

0x4C

0x50 - 0xFC

Control Register

Mode Register

Reserved

Reserved

Channel Enable Register

Channel Disable Register

Channel Status Register

Status Register

Last Converted Data Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Channel Data Register 0

Channel Data Register 1

Channel Data Register 2

Channel Data Register 3

Channel Data Register 4

Channel Data Register 5

Channel Data Register 6

Channel Data Register 7

Reserved

Name

ADC_CR

ADC_MR

ADC_CHER

ADC_CHDR

ADC_CHSR

ADC_SR

ADC_LCDR

ADC_IER

ADC_IDR

ADC_IMR

ADC_CDR0

ADC_CDR1

ADC_CDR2

ADC_CDR3

ADC_CDR4

ADC_CDR5

ADC_CDR6

ADC_CDR7

Write-only

Read/Write

Write-only

Write-only

Read-only

Read-only

Read-only

Write-only

Write-only

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

Read-only

0x00000000

0x00000000

0x000C0000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

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36.6.1

ADC Control Register

Register Name:

ADC_CR

Access Type:

Write-only

31

30

23

15

7

22

14

6

29

21

13

5

• SWRST: Software Reset

0 = No effect.

1 = Resets the ADC simulating a hardware reset.

• START: Start Conversion

0 = No effect.

1 = Begins analog-to-digital conversion.

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

1

START

24

16

8

0

SWRST

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36.6.2

ADC Mode Register

Register Name:

ADC_MR

Access Type:

Read/Write

31

30

23

15

7

22

14

6

5

SLEEP

29

21

13

• TRGEN: Trigger Enable

28

20

27 26

19 18

STARTUP

11

PRESCAL

10

SHTIM

3 2

TRGSEL

25

17

9

1

TRGEN

0

1

Selected TRGEN

Hardware triggers are disabled. Starting a conversion is only possible by software.

Hardware trigger selected by TRGSEL field is enabled.

• TRGSEL: Trigger Selection

1

1

0

1

1

0

0

0

• LOWRES: Resolution

TRGSEL

0

0

1

0

1

1

0

1

1

0

1

0

1

0

1

0

12

4

LOWRES

24

16

0

TRGEN

Selected TRGSEL

TIOA Ouput of the Timer Counter Channel 0

TIOA Ouput of the Timer Counter Channel 1

TIOA Ouput of the Timer Counter Channel 2 (Reserved on AT91SAM7S32)

Reserved

Reserved

Reserved

External trigger

Reserved

8

LOWRES

0

1

Selected Resolution

10-bit resolution

8-bit resolution

• SLEEP: Sleep Mode

SLEEP

0

1

Selected Mode

Normal Mode

Sleep Mode

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• PRESCAL: Prescaler Rate Selection

ADCClock = MCK / ( (PRESCAL+1) * 2 )

• STARTUP: Start Up Time

Startup Time = (STARTUP+1) * 8 / ADCClock

• SHTIM: Sample & Hold Time

Sample & Hold Time = (SHTIM+1) / ADCClock

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36.6.3

ADC Channel Enable Register

Register Name:

ADC_CHER

Access Type:

Write-only

31

30

29

23

15

7

CH7

22

14

6

CH6

21

13

5

CH5

• CHx: Channel x Enable

0 = No effect.

1 = Enables the corresponding channel.

36.6.4

ADC Channel Disable Register

Register Name:

ADC_CHDR

Access Type:

Write-only

31

30

29

23

15

7

CH7

22

14

6

CH6

21

13

5

CH5

• CHx: Channel x Disable

0 = No effect.

1 = Disables the corresponding channel.

28

20

12

4

CH4

28

20

12

4

CH4

27

19

11

3

CH3

27

19

11

3

CH3

26

18

10

2

CH2

26

18

10

2

CH2

25

17

9

1

CH1

25

17

9

1

CH1

24

16

8

0

CH0

24

16

8

0

CH0

Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.

487

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36.6.5

ADC Channel Status Register

Register Name:

ADC_CHSR

Access Type:

Read-only

31

30

29

23

15

7

CH7

22

14

6

CH6

21

13

5

CH5

• CHx: Channel x Status

0 = Corresponding channel is disabled.

1 = Corresponding channel is enabled.

28

20

12

4

CH4

27

19

11

3

CH3

26

18

10

2

CH2

25

17

9

1

CH1

24

16

8

0

CH0

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36.6.6

ADC Status Register

Register Name:

ADC_SR

Access Type:

Read-only

31

30

23

15

OVRE7

7

EOC7

22

14

OVRE6

6

EOC6

29

21

13

OVRE5

5

EOC5

28

20

12

OVRE4

4

EOC4

27

19

RXBUFF

11

OVRE3

3

EOC3

26

18

ENDRX

10

OVRE2

2

EOC2

• EOCx: End of Conversion x

0 = Corresponding analog channel is disabled, or the conversion is not finished.

1 = Corresponding analog channel is enabled and conversion is complete.

• OVREx: Overrun Error x

0 = No overrun error on the corresponding channel since the last read of ADC_SR.

1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR.

25

17

GOVRE

9

OVRE1

1

EOC1

• DRDY: Data Ready

0 = No data has been converted since the last read of ADC_LCDR.

1 = At least one data has been converted and is available in ADC_LCDR.

• GOVRE: General Overrun Error

0 = No General Overrun Error occurred since the last read of ADC_SR.

1 = At least one General Overrun Error has occurred since the last read of ADC_SR.

• ENDRX: End of RX Buffer

0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR.

1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR.

• RXBUFF: RX Buffer Full

0 = ADC_RCR or ADC_RNCR have a value other than 0.

1 = Both ADC_RCR and ADC_RNCR have a value of 0.

24

16

DRDY

8

OVRE0

0

EOC0

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36.6.7

ADC Last Converted Data Register

Register Name:

ADC_LCDR

Access Type:

Read-only

31

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

1

LDATA

24

16

8

0

LDATA

• LDATA: Last Data Converted

The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.

36.6.8

ADC Interrupt Enable Register

Register Name:

ADC_IER

Access Type:

Write-only

31

30

29

23

15

OVRE7

7

EOC7

22

14

OVRE6

6

EOC6

21

13

OVRE5

5

EOC5

• EOCx: End of Conversion Interrupt Enable x

• OVREx: Overrun Error Interrupt Enable x

28

20

12

OVRE4

4

EOC4

• DRDY: Data Ready Interrupt Enable

• GOVRE: General Overrun Error Interrupt Enable

• ENDRX: End of Receive Buffer Interrupt Enable

• RXBUFF: Receive Buffer Full Interrupt Enable

0 = No effect.

1 = Enables the corresponding interrupt.

27

19

RXBUFF

11

OVRE3

3

EOC3

26

18

ENDRX

10

OVRE2

2

EOC2

25

17

GOVRE

9

OVRE1

1

EOC1

24

16

DRDY

8

OVRE0

0

EOC0

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36.6.9

ADC Interrupt Disable Register

Register Name:

ADC_IDR

Access Type:

Write-only

31

30

29

23

15

OVRE7

7

EOC7

22

14

OVRE6

6

EOC6

21

13

OVRE5

5

EOC5

• EOCx: End of Conversion Interrupt Disable x

• OVREx: Overrun Error Interrupt Disable x

28

20

12

OVRE4

4

EOC4

• DRDY: Data Ready Interrupt Disable

• GOVRE: General Overrun Error Interrupt Disable

• ENDRX: End of Receive Buffer Interrupt Disable

• RXBUFF: Receive Buffer Full Interrupt Disable

0 = No effect.

1 = Disables the corresponding interrupt.

AT91SAM7X256/128 Preliminary

27

19

RXBUFF

11

OVRE3

3

EOC3

26

18

ENDRX

10

OVRE2

2

EOC2

25

17

GOVRE

9

OVRE1

1

EOC1

24

16

DRDY

8

OVRE0

0

EOC0

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36.6.10

ADC Interrupt Mask Register

Register Name:

ADC_IMR

Access Type:

Read-only

31

30

29

23

15

OVRE7

7

EOC7

22

14

OVRE6

6

EOC6

21

13

OVRE5

5

EOC5

• EOCx: End of Conversion Interrupt Mask x

• OVREx: Overrun Error Interrupt Mask x

28

20

12

OVRE4

4

EOC4

• DRDY: Data Ready Interrupt Mask

• GOVRE: General Overrun Error Interrupt Mask

• ENDRX: End of Receive Buffer Interrupt Mask

• RXBUFF: Receive Buffer Full Interrupt Mask

0 = The corresponding interrupt is disabled.

1 = The corresponding interrupt is enabled.

27

19

RXBUFF

11

OVRE3

3

EOC3

26

18

ENDRX

10

OVRE2

2

EOC2

25

17

GOVRE

9

OVRE1

1

EOC1

24

16

DRDY

8

OVRE0

0

EOC0

36.6.11

ADC Channel Data Register

Register Name:

ADC_CDRx

Access Type:

Read-only

31

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

1

DATA

24

16

8

0

DATA

• DATA: Converted Data

The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.

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37. Controller Area Network (CAN)

37.1

Description

The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by

ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The

CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/sec.

CAN controller accesses are made through configuration registers. 8 independent message objects (mailboxes) are implemented.

Any mailbox can be programmed as a reception buffer block (even non-consecutive buffers).

For the reception of defined messages, one or several message objects can be masked without participating in the buffer feature. An interrupt is generated when the buffer is full.

According to the mailbox configuration, the first message received can be locked in the CAN controller registers until the application acknowledges it, or this message can be discarded by new received messages.

Any mailbox can be programmed for transmission. Several transmission mailboxes can be enabled in the same time. A priority can be defined for each mailbox independently.

An internal 16-bit timer is used to stamp each received and sent message. This timer starts counting as soon as the CAN controller is enabled. This counter can be reset by the application or automatically after a reception in the last mailbox in Time Triggered Mode.

The CAN controller offers optimized features to support the Time Triggered Communication

(TTC) protocol.

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37.2

Block Diagram

Figure 37-1. CAN Block Diagram

Controller Area Network

CAN Protocol Controller

PIO

Control

&

Status

Error Counter

Mailbox

Priority

Encoder

MB0

MB1

MCK

PMC

MBx

(x = number of mailboxes - 1)

User Interface

CAN Interrupt

CANRX

CANTX

Internal Bus

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37.3

Application Block Diagram

Figure 37-2. Application Block Diagram

Layers

CAN-based Profiles

CAN-based Application Layer

CAN Data Link Layer

CAN Physical Layer

Implementation

Software

Software

CAN Controller

Transceiver

37.4

I/O Lines Description

Table 37-1.

I/O Lines Description

Name Description

CANRX

CANTX

CAN Receive Serial Data

CAN Transmit Serial Data

Type

Input

Output

37.5

Product Dependencies

37.5.1

I/O Lines

The pins used for interfacing the CAN may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired CAN pins to their peripheral function. If I/O lines of the CAN are not used by the application, they can be used for other purposes by the PIO Controller.

37.5.2

Power Management

The programmer must first enable the CAN clock in the Power Management Controller (PMC) before using the CAN.

A Low-power Mode is defined for the CAN controller: If the application does not require CAN operations, the CAN clock can be stopped when not needed and be restarted later. Before stopping the clock, the CAN Controller must be in Low-power Mode to complete the current transfer. After restarting the clock, the application must disable the Low-power Mode of the

CAN controller.

37.5.3

Interrupt

The CAN interrupt line is connected on one of the internal sources of the Advanced Interrupt

Controller. Using the CAN interrupt requires the AIC to be programmed first. Note that it is not recommended to use the CAN interrupt line in edge-sensitive mode.

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37.6

CAN Controller Features

37.6.1

CAN Protocol Overview

The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports real-time control with a very high level of security with bit rates up to 1 Mbit/s.

The CAN protocol supports four different frame types:

• Data frames: They carry data from a transmitter node to the receiver nodes. The overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame.

• Remote frames: A destination node can request data from the source by sending a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node then sends a data frame as a response to this node request.

• Error frames: An error frame is generated by any node that detects a bus error.

• Overload frames: They provide an extra delay between the preceding and the successive data frames or remote frames.

The Atmel CAN controller provides the CPU with full functionality of the CAN protocol V2.0

Part A and V2.0 Part B. It minimizes the CPU load in communication overhead. The Data Link

Layer and part of the physical layer are automatically handled by the CAN controller itself.

The CPU reads or writes data or messages via the CAN controller mailboxes. An identifier is assigned to each mailbox. The CAN controller encapsulates or decodes data messages to build or to decode bus data frames. Remote frames, error frames and overload frames are automatically handled by the CAN controller under supervision of the software application.

37.6.2

37.6.2.1

Mailbox Organization

The CAN module has 8 buffers, also called channels or mailboxes. An identifier that corresponds to the CAN identifier is defined for each active mailbox. Message identifiers can match the standard frame identifier or the extended frame identifier. This identifier is defined for the first time during the CAN initialization, but can be dynamically reconfigured later so that the mailbox can handle a new message family. Several mailboxes can be configured with the same ID.

Each mailbox can be configured in receive or in transmit mode independently. The mailbox object type is defined in the MOT field of the CAN_MMRx register.

Message Acceptance Procedure

If the MIDE field in the CAN_MIDx register is set, the mailbox can handle the extended format identifier; otherwise, the mailbox handles the standard format identifier. Once a new message is received, its ID is masked with the CAN_MAMx value and compared with the CAN_MIDx value. If accepted, the message ID is copied to the CAN_MIDx register.

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Figure 37-3. Message Acceptance Procedure

CAN_MIDx

CAN_MAMx

Message Received

& &

==

Message Accepted

Yes

No

Message Refused

CAN_MFIDx

If a mailbox is dedicated to receiving several messages (a family of messages) with different

IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the

CAN_MIDx. To speed up the decoding, masked bits are grouped in the family ID register

(CAN_MFIDx).

For example, if the following message IDs are handled by the same mailbox:

ID0 000011101000100100010010000100 0 11 00b

ID1 000011101000100100010010000100 0 11 01b

ID2 000011101000100100010010000100 0 11 10b

ID3 000011101000100100010010000100 0 11 11b

ID4 000011101000100100010010000100 1 11 00b

ID5 000011101000100100010010000100 1 11 01b

ID6 000011101000100100010010000100 1 11 10b

ID7 000011101000100100010010000100 1 11 11b

The CAN_MIDx and CAN_MAMx of Mailbox x must be initialized to the corresponding values:

CAN_MIDx = 000011101000100100010010000100 x 11 xxb

CAN_MAMx = 111111111111111111111111111111 0 11 00b

If Mailbox x receives a message with ID6, then CAN_MIDx and CAN_MFIDx are set:

CAN_MIDx = 000011101000100100010010000100 1 11 10b

CAN_MFIDx = 00000000000000000000000000000000110b

If the application associates a handler for each message ID, it may define an array of pointers to functions: void (*pHandler[8])(void);

When a message is received, the corresponding handler can be invoked using CAN_MFIDx register and there is no need to check masked bits: unsigned int MFID0_register;

MFID0_register = Get_CAN_MFID0_Register();

// Get_CAN_MFID0_Register() returns the value of the CAN_MFID0 register pHandler[MFID0_register]();

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37.6.2.2

Receive Mailbox

When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID. If such a mailbox is found, then the message is stored in its data registers. Depending on the configuration, the mailbox is disabled as long as the message has not been acknowledged by the application

(Receive only), or, if new messages with the same ID are received, then they overwrite the previous ones (Receive with overwrite).

It is also possible to configure a mailbox in Consumer Mode. In this mode, after each transfer request, a remote frame is automatically sent. The first answer received is stored in the corresponding mailbox data registers.

Several mailboxes can be chained to receive a buffer. They must be configured with the same

ID in Receive Mode, except for the last one, which can be configured in Receive with Overwrite Mode. The last mailbox can be used to detect a buffer overflow.

Mailbox Object Type

Receive

Receive with overwrite

37.6.2.3

Consumer

Description

The first message received is stored in mailbox data registers. Data remain available until the next transfer request.

The last message received is stored in mailbox data register. The next message always overwrites the previous one. The application has to check whether a new message has not overwritten the current one while reading the data registers.

A remote frame is sent by the mailbox. The answer received is stored in mailbox data register.

This extends Receive mailbox features. Data remain available until the next transfer request.

Transmit Mailbox

When transmitting a message, the message length and data are written to the transmit mailbox with the correct identifier. For each transmit mailbox, a priority is assigned. The controller automatically sends the message with the highest priority first (set with the field PRIOR in

CAN_MMRx register).

It is also possible to configure a mailbox in Producer Mode. In this mode, when a remote frame is received, the mailbox data are sent automatically. By enabling this mode, a producer can be done using only one mailbox instead of two: one to detect the remote frame and one to send the answer.

Mailbox Object Type

Transmit

Producer

Description

The message stored in the mailbox data registers will try to win the bus arbitration immediately

or later according to or not the Time Management Unit configuration (see Section 37.6.3

).

The application is notified that the message has been sent or aborted.

The message prepared in the mailbox data registers will be sent after receiving the next remote frame. This extends transmit mailbox features.

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37.6.3

Time Management Unit

The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR register). It is automatically cleared in the following cases:

• after a reset

• when the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and

SLEEP bit set in the CAN_SR)

• after a reset of the CAN controller (CANEN bit in the CAN_MR register)

• in Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of the MRDY signal in the CAN_MSR last_mailbox_number

register).

The application can also reset the internal timer by setting TIMRST in the CAN_TCR register.

The current value of the internal timer is always accessible by reading the CAN_TIM register.

When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR register is set. TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register.

Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated while TOVF is set.

In a CAN network, some CAN devices may have a larger counter. In this case, the application can also decide to freeze the internal counter when the timer reaches FFFFh and to wait for a restart condition from another device. This feature is enabled by setting TIMFRZ in the

CAN_MR register. The CAN_TIM register is frozen to the FFFFh value. A clear condition described above restarts the timer. A timer overflow (TOVF) interrupt is triggered.

To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP register after each start of frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in the CAN_MR register is set, the value is captured at each End Of Frame, else it is captured at each Start Of Frame. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the

CAN_SR register.

The time management unit can operate in one of the two following modes:

• Timestamping mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame

• Time Triggered mode: A mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger.

Timestamping Mode is enabled by clearing TTM field in the CAN_MR register. Time Triggered

Mode is enabled by setting TTM field in the CAN_MR register.

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37.6.4

37.6.4.1

CAN 2.0 Standard Features

CAN Bit Timing Configuration

All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments.

The CAN protocol specification partitions the nominal bit time into four different segments:

Figure 37-4. Partition of the CAN Bit Time

NOMINAL BIT TIME

PROP_SEG

PHASE_SEG1

PHASE_SEG2

SYNC_SEG

Sample Point

TIME QUANTUM:

The TIME QUANTUM (TQ) is a fixed unit of time derived from the MCK period. The total number of TIME QUANTA in a bit time is programmable from 8 to 25.

SYNC SEG: SYNChronization Segment.

This part of the bit time is used to synchronize the various nodes on the bus. An edge is expected to lie within this segment. It is 1 TQ long.

PROP SEG: PROPagation Segment.

This part of the bit time is used to compensate for the physical delay times within the network.

It is twice the sum of the signal’s propagation time on the bus line, the input comparator delay, and the output driver delay. It is programmable to be 1,2,..., 8 TQ long.

This parameter is defined in the PROPAG field of the

”CAN Baudrate Register”

.

PHASE SEG1, PHASE SEG2: PHASE Segment 1 and 2.

The Phase-Buffer-Segments are used to compensate for edge phase errors. These segments can be lengthened (PHASE SEG1) or shortened (PHASE SEG2) by resynchronization.

Phase Segment 1 is programmable to be 1,2,..., 8 TQ long.

Phase Segment 2 length has to be at least as long as the Information Processing Time (IPT) and may not be more than the length of Phase Segment 1.

These parameters are defined in the PHASE1 and PHASE2 fields of the

”CAN Baudrate

Register” .

INFORMATION PROCESSING TIME:

The Information Processing Time (IPT) is the time required for the logic to determine the bit level of a sampled bit. The IPT begins at the sample point, is measured in TQ and is fixed at

2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PHASE SEG2 shall not be less than the IPT.

SAMPLE POINT:

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The SAMPLE POINT is the point in time at which the bus level is read and interpreted as the value of that respective bit. Its location is at the end of PHASE_SEG1.

SJW: ReSynchronization Jump Width.

The ReSynchronization Jump Width defines the limit to the amount of lengthening or shortening of the Phase Segments.

SJW is programmable to be the minimum of PHASE SEG1 and 4 TQ.

If the SMP field in the CAN_BR register is set, then the incoming bit stream is sampled three times with a period of half a CAN clock period, centered on sample point.

In the CAN controller, the length of a bit on the CAN bus is determined by the parameters

(BRP, PROPAG, PHASE1 and PHASE2).

t

BIT

= t

CSC

+ t

PRS

+ t

PHS1

+ t

PHS2

The time quantum is calculated as follows: t

CSC

=

(

BRP

+

1

) ⁄

MCK t

PRS t

PHS1

=

= t

CSC

× t

CSC

×

(

PROPAG + 1

)

(

PHASE1

+

1

) t

PHS2

= t

CSC

× (

PHASE2 + 1

)

To compensate for phase shifts between clock oscillators of different controllers on the bus, the CAN controller must resynchronize on any relevant signal edge of the current transmission. The resynchronization shortens or lengthens the bit time so that the position of the sample point is shifted with regard to the detected edge. The resynchronization jump width

(SJW) defines the maximum of time by which a bit period may be shortened or lengthened by resynchronization.

t

SJW

= t

CSC

× (

SJW

+

1

)

Figure 37-5. CAN Bit Timing

MCK

CAN Clock t

CSC t

PRS t

PHS1 t

PHS2

SYNC_

SEG

NOMINAL BIT TIME

PHASE_SEG1 PROP_SEG PHASE_SEG2

Sample Point

Example of bit timing determination for CAN baudrate of 500 Kbit/s:

MCK = 48MHz

CAN baudrate= 500kbit/s => bit time= 2us

Transmission Point

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Delay of the bus driver: 50 ns

Delay of the receiver: 30ns

Delay of the bus line (20m): 110ns

The total number of time quanta in a bit time must be comprised between 8 and 25. If we fix the bit time to 16 time quanta:

Tcsc = 1 time quanta = bit time / 16 = 125 ns

=> BRP = (Tcsc x MCK) - 1 = 5

The propagation segment time is equal to twice the sum of the signal’s propagation time on the bus line, the receiver delay and the output driver delay:

Tprs = 2 * (50+30+110) ns = 380 ns = 3 Tcsc

=> PROPAG = Tprs/Tcsc - 1 = 2

The remaining time for the two phase segments is:

Tphs1 + Tphs2 = bit time - Tcsc - Tprs = (16 - 1 - 3)Tcsc

Tphs1 + Tphs2 = 12 Tcsc

Because this number is even, we choose Tphs2 = Tphs1 (else we would choose

Tphs2 = Tphs1 + Tcsc)

Tphs1 = Tphs2 = (12/2) Tcsc = 6 Tcsc

=> PHASE1 = PHASE2 = Tphs1/Tcsc - 1 = 5

The resynchronization jump width must be comprised between 1 Tcsc and the minimum of 4 Tcsc and Tphs1. We choose its maximum value:

Tsjw = Min(4 Tcsc,Tphs1) = 4 Tcsc

=> SJW = Tsjw/Tcsc - 1 = 3

Finally: CAN_BR = 0x00053255

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CAN Bus Synchronization

Two types of synchronization are distinguished: “hard synchronization” at the start of a frame and “resynchronization” inside a frame. After a hard synchronization, the bit time is restarted with the end of the SYNC_SEG segment, regardless of the phase error. Resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge.

The effect of resynchronization is the same as that of hard synchronization when the magnitude of the phase error of the edge causing the resynchronization is less than or equal to the programmed value of the resynchronization jump width (t

SJW

).

When the magnitude of the phase error is larger than the resynchronization jump width and

• the phase error is positive, then PHASE_SEG1 is lengthened by an amount equal to the resynchronization jump width.

• the phase error is negative, then PHASE_SEG2 is shortened by an amount equal to the resynchronization jump width.

Figure 37-6. CAN Resynchronization

THE PHASE ERROR IS POSITIVE

(the transmitter is slower than the receiver)

Received data bit

Nominal

Sample point

Sample point after resynchronization

Nominal bit time

(before resynchronization)

SYNC_

SEG

PROP_SEG PHASE_SEG1 PHASE_SEG2

SYNC_

SEG

Phase error (max Tsjw)

Bit time with resynchronization

SYNC_

SEG

Phase error

PROP_SEG PHASE_SEG1 PHASE_SEG2

SYNC_

SEG

Received data bit

Nominal bit time

(before resynchronization)

THE PHASE ERROR IS NEGATIVE

(the transmitter is faster than the receiver)

PHASE_SEG2

SYNC_

SEG after resynchronization

PROP_SEG

Sample point

PHASE_SEG1

Nominal

Sample point

PHASE_SEG2

SYNC_

SEG

Bit time with resynchronization

Phase error

PHASE_

SEG2

SYNC_

SEG

PROP_SEG PHASE_SEG1 PHASE_SEG2

SYNC_

SEG

Phase error (max Tsjw)

Autobaud Mode

The autobaud feature is enabled by setting the ABM field in the CAN_MR register. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It can not send any message. The errors flags are updated. The bit timing can be adjusted until no error occurs (good configuration found). In this mode, the error counters are frozen. To go back to the standard mode, the ABM bit must be cleared in the CAN_MR register.

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37.6.4.2

Error Detection

There are five different error types that are not mutually exclusive. Each error concerns only specific fields of the CAN data frame (refer to the Bosch CAN specification for their correspondence):

• CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data

Field. This CRC sequence is transmitted in the CRC field of the Data or Remote Frame.

• Bit-stuffing error (SERR bit in the CAN_SR register): If a node detects a sixth consecutive equal bit level during the bit-stuffing area of a frame, it generates an Error Frame starting with the next bit-time.

• Bit error (BERR bit in CAN_SR register): A bit error occurs if a transmitter sends a dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a dominant bit on the bus line. An error frame is generated and starts with the next bit time.

• Form Error (FERR bit in the CAN_SR register): If a transmitter detects a dominant bit in one of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form error has occurred and an error frame is generated.

• Acknowledgment error (AERR bit in the CAN_SR register): The transmitter checks the

Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit, contains a dominant bit. If this is the case, at least one other node has received the frame correctly. If not, an Acknowledge Error has occurred and the transmitter will start in the next bit-time an Error Frame transmission.

Fault Confinement

To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The counters are incremented upon detected errors and respectively are decremented upon correct transmissions or receptions. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error

Active flags. The controller changes to the Error Passive state if there is an accumulation of errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state transition to Bus Off.

Figure 37-7. Line Error Mode

Init

TEC > 127 or

REC > 127

ERROR

PASSIVE

ERROR

ACTIVE

128 occurences of 11 consecutive recessive bits or

CAN controller reset

TEC < 127 and

REC < 127

BUS OFF

TEC > 255

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An error active unit takes part in bus communication and sends an active error frame when the

CAN controller detects an error.

An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further transmission.

A bus off unit is not allowed to have any influence on the bus.

For fault confinement, two errors counters (TEC and REC) are implemented. These counters are accessible via the CAN_ECR register. The state of the CAN controller is automatically updated according to these counter values. If the CAN controller is in Error Active state, then the ERRA bit is set in the CAN_SR register. The corresponding interrupt is pending while the interrupt is not masked in the CAN_IMR register. If the CAN controller is in Error Passive

Mode, then the ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is set in the CAN_IMR register. If the CAN is in Bus-off Mode, then the BOFF bit is set in the CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF bit is set in the CAN_IMR register.

When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the WARN bit in CAN_SR register, but the node remains error active. The corresponding interrupt is pending while the interrupt is set in the CAN_IMR register.

Refer to the Bosch CAN specification v2.0 for details on fault confinement.

37.6.4.3

37.6.5

Overload

The overload frame is provided to request a delay of the next data or remote frame by the receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive overload frame”) related to the intermission field respectively.

Reactive overload frames are transmitted after detection of the following error conditions:

• Detection of a dominant bit during the first two bits of the intermission field

• Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter

The CAN controller can generate a request overload frame automatically after each message sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the CAN_MR register.

Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in the CAN_MR register is not set. An overload flag is generated in the same way as an error flag, but error counters do not increment.

Low-power Mode

In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are inactive.

In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP signal in the CAN_SR register is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Lowpower Mode is disabled and the WAKEUP bit is set in the CAN_SR register only after detection of 11 consecutive recessive bits on the bus.

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37.6.5.1

Enabling Low-power Mode

A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN controller enters Low-power Mode once all pending transmit messages are sent.

When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while SLEEP is set.

The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The

WAKEUP signal is automatically cleared once SLEEP is set.

Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is important to note that those messages with higher priority than the last message transmitted can be received between the LPM command and entry in Low-power Mode.

Once in Low-power Mode, the CAN controller clock can be switched off by programming the chip’s Power Management Controller (PMC). The CAN controller drains only the static current.

Error counters are disabled while the SLEEP signal is set to one.

Thus, to enter Low-power Mode, the software application must:

– Set LPM field in the CAN_MR register

– Wait for SLEEP signal rising

Now the CAN Controller clock can be disabled. This is done by programming the Power Management Controller (PMC).

Figure 37-8. Enabling Low-power Mode

Arbitration lost

Mailbox 1

CAN BUS

LPM

(CAN_MR)

SLEEP

(CAN_SR)

LPEN= 1

WAKEUP

(CAN_SR)

MRDY

(CAN_MSR1)

MRDY

(CAN_MSR3)

CAN_TIM

Mailbox 3

0x0

37.6.5.2

Disabling Low-power Mode

The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is done by an external module that may be embedded in the chip. When it is notified of a CAN bus activity, the software application disables Low-power Mode by programming the CAN controller.

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To disable Low-power Mode, the software application must:

– Enable the CAN Controller clock. This is done by programming the Power

Management Controller (PMC).

– Clear the LPM field in the CAN_MR register

The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive

“recessive” bits. Once synchronized, the WAKEUP signal in the CAN_SR register is set.

Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while WAKEUP is set. The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. WAKEUP signal is automatically cleared once SLEEP is set.

If no message is being sent on the bus, then the CAN controller is able to send a message eleven bit times after disabling Low-power Mode.

If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized with the bus activity in the next interframe. The previous message is lost (see

Figure 37-9 ).

Figure 37-9. Disabling Low-power Mode

Bus Activity Detected

Message lost

Message x

Interframe synchronization

CAN BUS

LPM

(CAN_MR)

SLEEP

(CAN_SR)

WAKEUP

(CAN_SR)

MRDY

(CAN_MSRx)

37.7

Functional Description

37.7.1

CAN Controller Initialization

After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller (AIC).

The CAN controller must be initialized with the CAN network parameters. The CAN_BR register defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller is enabled by setting the CANEN field in the CAN_MR register.

The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage, the internal CAN controller state machine is reset, error counters are reset to 0, error flags are reset to 0.

Once the CAN controller is enabled, bus synchronization is done automatically by scanning eleven recessive bits. The WAKEUP bit in the CAN_SR register is automatically set to 1 when the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset).

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The CAN controller can start listening to the network in Autobaud Mode. In this case, the error counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags, the CAN_BR register values synchronized with the network. Once no error has been detected, the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR register.

Figure 37-10. Possible Initialization Procedure

Enable CAN Controller Clock

(PMC)

Enable CAN Controller Interrupt Line

(AIC)

Configure a Mailbox in Reception Mode

Change CAN_BR value

(ABM == 1 and CANEN == 1)

Errors ?

(CAN_SR or CAN_MSRx)

Yes

No

ABM = 0 and CANEN = 0

CANEN = 1 (ABM == 0)

End of Initialization

37.7.2

CAN Controller Interrupt Handling

There are two different types of interrupts. One type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources.

All interrupt sources can be masked by writing the corresponding field in the CAN_IDR register. They can be unmasked by writing to the CAN_IER register. After a power-up reset, all interrupt sources are disabled (masked). The current mask status can be checked by reading the CAN_IMR register.

The CAN_SR register gives all interrupt source states.

The following events may initiate one of the two interrupts:

• Message object interrupt

– Data registers in the mailbox object are available to the application. In Receive

Mode, a new message was received. In Transmit Mode, a message was transmitted successfully.

– A sent transmission was aborted.

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• System interrupts

– Bus-off interrupt: The CAN module enters the bus-off state.

– Error-passive interrupt: The CAN module enters Error Passive Mode.

– Error-active Mode: The CAN module is neither in Error Passive Mode nor in Busoff mode.

– Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its error counter value exceeds 96.

– Wake-up interrupt: This interrupt is generated after a wake-up and a bus synchronization.

– Sleep interrupt: This interrupt is generated after a Low-power Mode enable once all pending messages in transmission have been sent.

– Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over.

– Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register.

All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the

CAN_SR register.

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37.7.3

37.7.3.1

CAN Controller Message Handling

Receive Handling

Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is stored in the mailbox data register. In Receive with Overwrite

Mode, the last message received is stored in the mailbox.

Simple Receive Mailbox

A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance Mask must be set before the Receive Mode is enabled.

After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register.

Message data are stored in the mailbox data register until the software application notifies that data processing has ended. This is done by asking for a new transfer command, setting the

MTCR flag in the CAN_MCRx register. This automatically clears the MRDY signal.

The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by the mailbox. This flag is set when messages are received while MRDY is set in the

CAN_MSRx register. This flag is cleared by reading the CAN_MSRs register. A receive mailbox prevents from overwriting the first message by new ones while MRDY flag is set in the

CAN_MSRx register. See Figure 37-11

.

Figure 37-11. Receive Mailbox

Message ID = CAN_MIDx

CAN BUS

MRDY

(CAN_MSRx)

MMI

(CAN_MSRx)

Message 1 Message 2 lost Message 3

(CAN_MDLx

CAN_MDHx)

MTCR

(CAN_MCRx)

Message 1

Reading CAN_MDHx & CAN_MDLx

Reading CAN_MSRx

Writing CAN_MCRx

Message 3

Note: In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler instruction.

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Receive with Overwrite Mailbox

A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before

Receive Mode is enabled.

After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt is masked depending on the mailbox flag in the CAN_IMR global register.

If a new message is received while the MRDY flag is set, this new message is stored in the mailbox data register, overwriting the previous message. The MMI flag in the CAN_MSRx register notifies the software that a message has been dropped by the mailbox. This flag is cleared when reading the CAN_MSRx register.

The CAN controller may store a new message in the CAN data registers while the application reads them. To check that CAN_MDHx and CAN_MDLx do not belong to different messages, the application must check the MMI field in the CAN_MSRx register before and after reading

CAN_MDHx and CAN_MDLx. If the MMI flag is set again after the data registers have been

read, the software application has to re-read CAN_MDHx and CAN_MDLx (see Figure 37-12 ).

Figure 37-12. Receive with Overwrite Mailbox

Message ID = CAN_MIDx

CAN BUS

MRDY

(CAN_MSRx)

MMI

(CAN_MSRx)

(CAN_MDLx

CAN_MDHx)

MTCR

(CAN_MCRx)

Message 1 Message 2

Message 1

Message 3

Message 2

Message 4

Message 3 Message 4

Reading CAN_MSRx

Reading CAN_MDHx & CAN_MDLx

Writing CAN_MCRx

Chaining Mailboxes

Several mailboxes may be used to receive a buffer split into several messages with the same

ID. In this case, the mailbox with the lowest number is serviced first. In the receive and receive with overwrite modes, the field PRIOR in the CAN_MMRx register has no effect. If Mailbox 0 and Mailbox 5 accept messages with the same ID, the first message is received by Mailbox 0 and the second message is received by Mailbox 5. Mailbox 0 must be configured in Receive

Mode (i.e., the first message received is considered) and Mailbox 5 must be configured in

Receive with Overwrite Mode. Mailbox 0 cannot be configured in Receive with Overwrite

Mode; otherwise, all messages are accepted by this mailbox and Mailbox 5 is never serviced.

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If several mailboxes are chained to receive a buffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in Receive Mode. The first message received is handled by the first mailbox, the second one is refused by the first mailbox and accepted by the second mailbox, the last message is accepted by the last mailbox

and refused by previous ones (see Figure 37-13

).

Figure 37-13. Chaining Three Mailboxes to Receive a Buffer Split into Three Messages

Buffer split in 3 messages

CAN BUS

MRDY

(CAN_MSRx)

MMI

(CAN_MSRx)

MRDY

(CAN_MSRy)

MMI

(CAN_MSRy)

MRDY

(CAN_MSRz)

MMI

(CAN_MSRz)

Message s1 Message s2 Message s3

Reading CAN_MSRx, CAN_MSRy and CAN_MSRz

Reading CAN_MDH & CAN_MDL for mailboxes x, y and z

Writing MBx MBy MBz in CAN_TCR

If the number of mailboxes is not sufficient (the MMI flag of the last mailbox raises), the user must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see

Figure 37-14 ).

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Figure 37-14. Chaining Three Mailboxes to Receive a Buffer Split into Four Messages

Buffer split in 4 messages

CAN BUS

MRDY

(CAN_MSRx)

MMI

(CAN_MSRx)

MRDY

(CAN_MSRy)

MMI

(CAN_MSRy)

MRDY

(CAN_MSRz)

MMI

(CAN_MSRz)

37.7.3.2

Message s1 Message s2 Message s3

Message s4

Reading CAN_MSRx, CAN_MSRy and CAN_MSRz

Reading CAN_MDH & CAN_MDL for mailboxes x, y and z

Writing MBx MBy MBz in CAN_TCR

Transmission Handling

A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled.

After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers. The message is sent once the software asks for a transfer command setting the MTCR bit and the message data length in the CAN_MCRx register.

The MRDY flag remains at zero as long as the message has not been sent or aborted. It is important to note that no access to the mailbox data register is allowed while the MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register.

It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field. The answer to the remote frame is handled by another reception mailbox. In this case, the device acts as a consumer but with the help of two mailboxes. It is possible to handle the remote frame emission and the answer reception using only one mailbox configured in Consumer Mode. Refer to the section

”Remote Frame Handling” on page 514 .

Several messages can try to win the bus arbitration in the same time. The message with the highest priority is sent first. Several transfer request commands can be generated at the same time by setting MBx bits in the CAN_TCR register. The priority is set in the PRIOR field of the

CAN_MMRx register. Priority 0 is the highest priority, priority 15 is the lowest priority. Thus it is possible to use a part of the message ID to set the PRIOR field. If two mailboxes have the same priority, the message of the mailbox with the lowest number is sent first. Thus if mailbox

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0 and mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first.

Setting the MACR bit in the CAN_MCRx register aborts the transmission. Transmission for several mailboxes can be aborted by writing MBx fields in the CAN_MACR register. If the message is being sent when the abort command is set, then the application is notified by the

MRDY bit set and not the MABT in the CAN_MSRx register. Otherwise, if the message has not been sent, then the MRDY and the MABT are set in the CAN_MSR register.

When the bus arbitration is lost by a mailbox message, the CAN controller tries to win the next bus arbitration with the same message if this one still has the highest priority. Messages to be sent are re-tried automatically until they win the bus arbitration. This feature can be disabled by setting the bit DRPT in the CAN_MR register. In this case if the message was not sent the first time it was transmitted to the CAN transceiver, it is automatically aborted. The MABT flag is set in the CAN_MSRx register until the next transfer command.

Figure 37-15 shows three MBx message attempts being made (MRDY of MBx set to 0).

The first MBx message is sent, the second is aborted and the last one is trying to be aborted but too late because it has already been transmitted to the CAN transceiver.

Figure 37-15. Transmitting Messages

CAN BUS

MRDY

(CAN_MSRx)

MABT

(CAN_MSRx)

MTCR

(CAN_MCRx)

MACR

(CAN_MCRx)

Reading CAN_MSRx

Writing CAN_MDHx &

CAN_MDLx

MBx message

Abort MBx message

MBx message

Try to Abort MBx message

37.7.3.3

Remote Frame Handling

Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages.

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6120D–ATARM–02-Feb-06

Figure 37-16. Producer / Consumer Model

Producer

Request

AT91SAM7X256/128 Preliminary

PUSH MODEL

CAN Data Frame

Consumer

Indication(s)

PULL MODEL

Producer

Indications

CAN Remote Frame

Consumer

Request(s)

Response

CAN Data Frame

Confirmation(s)

In Pull Mode, a consumer transmits a remote frame to the producer. When the producer receives a remote frame, it sends the answer accepted by one or many consumers. Using transmit and receive mailboxes, a consumer must dedicate two mailboxes, one in Transmit

Mode to send remote frames, and at least one in Receive Mode to capture the producer’s answer. The same structure is applicable to a producer: one reception mailbox is required to get the remote frame and one transmit mailbox to answer.

Mailboxes can be configured in Producer or Consumer Mode. A lonely mailbox can handle the remote frame and the answer. With 8 mailboxes, the CAN controller can handle 8 independent producers/consumers.

Producer Configuration

A mailbox is in Producer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled.

After Producer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the

CAN_MCRx register. Data is sent after the reception of a remote frame as soon as it wins the bus arbitration.

The MRDY flag remains at zero as long as the message has not been sent or aborted. No access to the mailbox data register can be done while MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register.

If a remote frame is received while no data are ready to be sent (signal MRDY set in the

CAN_MSRx register), then the MMI signal is set in the CAN_MSRx register. This bit is cleared by reading the CAN_MSRx register.

The MRTR field in the CAN_MSRx register has no meaning. This field is used only when using

Receive and Receive with Overwrite modes.

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After a remote frame has been received, the mailbox functions like a transmit mailbox. The message with the highest priority is sent first. The transmitted message may be aborted by

setting the MACR bit in the CAN_MCR register. Please refer to the section ”Transmission

Handling” on page 513 .

Figure 37-17. Producer Handling

Remote Frame CAN BUS

MRDY

(CAN_MSRx)

MMI

(CAN_MSRx)

MTCR

(CAN_MCRx)

Message 1 Remote Frame

Reading CAN_MSRx

Remote Frame

Message 2

(CAN_MDLx

CAN_MDHx)

Message 1 Message 2

Consumer Configuration

A mailbox is in Consumer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled.

After Consumer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first transfer request command. The software application sends a remote frame by setting the MTCR bit in the CAN_MCRx register or the MBx bit in the global

CAN_TCR register. The application is notified of the answer by the MRDY flag set in the

CAN_MSRx register. The application can read the data contents in the CAN_MDHx and

CAN_MDLx registers. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register.

The MRTR bit in the CAN_MCRx register has no effect. This field is used only when using

Transmit Mode.

After a remote frame has been sent, the consumer mailbox functions as a reception mailbox.

The first message received is stored in the mailbox data registers. If other messages intended for this mailbox have been sent while the MRDY flag is set in the CAN_MSRx register, they will be lost. The application is notified by reading the MMI field in the CAN_MSRx register. The read operation automatically clears the MMI flag.

If several messages are answered by the Producer, the CAN controller may have one mailbox in consumer configuration, zero or several mailboxes in Receive Mode and one mailbox in

Receive with Overwrite Mode. In this case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR register.

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Figure 37-18. Consumer Handling

Remote Frame

CAN BUS

MRDY

(CAN_MSRx)

MMI

(CAN_MSRx)

MTCR

(CAN_MCRx)

Message x

Remote Frame

Message y

(CAN_MDLx

CAN_MDHx)

Message x Message y

37.7.4

CAN Controller Timing Modes

Using the free running 16-bit internal timer, the CAN controller can be set in one of the two following timing modes:

• Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame.

• Time Triggered Mode: The mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger.

Timestamping Mode is enabled by clearing the TTM bit in the CAN_MR register. Time Triggered Mode is enabled by setting the TTM bit in the CAN_MR register.

37.7.4.1

Timestamping Mode

Each mailbox has its own timestamp value. Each time a message is sent or received by a mailbox, the 16-bit value MTIMESTAMP of the CAN_TIMESTP register is transferred to the

LSB bits of the CAN_MSRx register. The value read in the CAN_MSRx register corresponds to the internal timer value at the Start Of Frame or the End Of Frame of the message handled by the mailbox.

Figure 37-19. Mailbox Timestamp

Start of Frame End of Frame

Message 1

CAN BUS

CAN_TIM

TEOF

(CAN_MR)

TIMESTAMP

(CAN_TSTP)

MTIMESTAMP

(CAN_MSRx)

MTIMESTAMP

(CAN_MSRy)

Timestamp 1

Timestamp 1

Message 2

Timestamp 2

Timestamp 2

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37.7.4.2

Time Triggered Mode

In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window.

Figure 37-20. Time Triggered Principle

Time Cycle

Reference

Message

Reference

Message

Time Windows for Messages

Global Time

Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Triggered Mode, as in Timestamp Mode, the CAN_TIMESTP field captures the values of the internal counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at 0.

Synchronization by a Reference Message

In Time Triggered Mode, the internal timer counter is automatically reset when a new message is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the rising edge of the MRDY signal in the CAN_MSRx register. This allows synchronization of the internal timer counter with the reception of a reference message and the start a new time window.

Transmitting within a Time Window

A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the

CAN_MMRx register. At each internal timer clock cycle, the value of the CAN_TIM is compared with each mailbox time mark. When the internal timer counter reaches the

MTIMEMARK value, an internal timer event for the mailbox is generated for the mailbox.

In Time Triggered Mode, transmit operations are delayed until the internal timer event for the mailbox. The application prepares a message to be sent by setting the MTCR in the

CAN_MCRx register. The message is not sent until the CAN_TIM value is less than the

MTIMEMARK value defined in the CAN_MMRx register.

If the transmit operation is failed, i.e., the message loses the bus arbitration and the next transmit attempt is delayed until the next internal time trigger event. This prevents overlapping the next time window, but the message is still pending and is retried in the next time window when

CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting the DRPT field in the CAN_MR register.

Freezing the Internal Timer Counter

The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. The TOVF bit in the CAN_SR register is set when the counter

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is frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register.

Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated when TOVF is set.

Figure 37-21. Time Triggered Operations

End of Frame

Message x

Arbitration Lost

Message y

Arbitration Win

CAN BUS

Reference

Message

Message y

Internal Counter Reset

CAN_TIM

Cleared by software

MRDY

(CAN_MSRlast_mailbox_number)

Timer Event x

MRDY

(CAN_MSRx)

MTIMEMARKx == CAN_TIM

MTIMEMARKy == CAN_TIM

Timer Event y

MRDY

(CAN_MSRy)

Time Window

Basic Cycle

CAN BUS

CAN_TIM

Reference

Message

End of Frame

Internal Counter Reset

Message x

Message x

Arbitration Win

Cleared by software

MRDY

(CAN_MSRlast_mailbox_number)

Timer Event x

MRDY

(CAN_MSRx)

MTIMEMARKx == CAN_TIM

Time Window

Basic Cycle

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37.8

Controller Area Network (CAN) User Interface

Table 37-2.

CAN Memory Map

Offset Register

0x0210

0x0214

0x0218

0x021C

0x0220

0x0224

0x0228

0x022C

0x0230

0x0234

0x0238

0x023C

...

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

Mode Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Status Register

Baudrate Register

Timer Register

Timestamp Register

0x0020

0x0024

Error Counter Register

Transfer Command Register

0x0028 Abort Command Register

0x0100 - 0x01FC Reserved

0x0200

0x0204

0x0208

0x020C

Mailbox 0 Mode Register

Mailbox 0 Acceptance Mask Register

Mailbox 0 ID Register

Mailbox 0 Family ID Register

Mailbox 0 Status Register

Mailbox 0 Data Low Register

Mailbox 0 Data High Register

Mailbox 0 Control Register

Mailbox 1 Mode Register

Mailbox 1 Acceptance Mask Register

Mailbox 1 ID register

Mailbox 1 Family ID Register

Mailbox 1 Status Register

Mailbox 1 Data Low Register

Mailbox 1 Data High Register

Mailbox 1 Control Register

...

CAN_MID0

CAN_MFID0

CAN_MSR0

CAN_MDL0

CAN_MDH0

CAN_MCR0

CAN_MMR1

CAN_MAM1

CAN_MID1

CAN_MFID1

CAN_MSR1

CAN_MDL1

CAN_MDH1

CAN_MCR1

...

Name

CAN_MR

CAN_IER

CAN_IDR

CAN_IMR

CAN_SR

CAN_BR

CAN_TIM

CAN_TIMESTP

CAN_ECR

CAN_TCR

CAN_ACR

CAN_MMR0

CAN_MAM0

Read-only

Read/Write

Read/Write

Write-only

Read/Write

Read/Write

Read/Write

Read-only

Read-only

Read/Write

Read/Write

Write-only

...

Read-Write

Write-only

Write-only

Read-only

Read-only

Read/Write

Read-only

Read-only

Read-only

Write-only

Write-only

Read/Write

Read/Write

Read/Write

Read-only

0x0

0x0

0x0

0x0

0x0

0x0

0x0

-

0x0

0x0

0x0

-

-

0x0

0x0

0x0

0x0

0x0

-

-

0x0

0x0

0x0

0x0

0x0

-

-

0x0

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37.8.1

CAN Mode Register

Name:

Access Type:

CAN_MR

Read/Write

31

30

29

23

15

22

14

21

13

28

20

12

27

19

11

26

18

10

25

17

9

24

16

8

7

DRPT

6

TIMFRZ

5

TTM

4

TEOF

3

OVL

2

ABM

1

LPM

0

CANEN

• CANEN: CAN Controller Enable

0 = The CAN Controller is disabled.

1 = The CAN Controller is enabled.

• LPM: Disable/Enable Low Power Mode

w Power Mode.

1 = Enable Low Power M

CAN controller enters Low Power Mode once all pending messages have been transmitted.

• ABM: Disable/Enable Autobaud/Listen mode

0 = Disable Autobaud/listen mode.

1 = Enable Autobaud/listen mode.

• OVL: Disable/Enable Overload Frame

0 = No overload frame is generated.

1 = An overload frame is generated after each successful reception for mailboxes configured in Receive with/without overwrite Mode, Producer and Consumer.

• TEOF: Timestamp messages at each end of Frame

0 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each Start Of Frame.

1 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each End Of Frame.

• TTM: Disable/Enable Time Triggered Mode

0 = Time Triggered Mode is disabled.

1 = Time Triggered Mode is enabled.

• TIMFRZ: Enable Timer Freeze

0 = The internal timer continues to be incremented after it reached 0xFFFF.

1 = The internal timer stops incrementing after reaching 0xFFFF. It is restarted after a timer reset. See ”Freezing the Internal Timer Counter” on page 518

.

• DRPT: Disable Repeat

0 = When a transmit mailbox loses the bus arbitration, the transfer request remains pending.

1 = When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx.

521

6120D–ATARM–02-Feb-06

37.8.2

CAN Interrupt Enable Register

Name:

Access Type:

CAN_IER

Write-only

31

30

29

23

TSTP

15

22

TOVF

14

21

WAKEUP

13

7

MB7

6

MB6

5

MB5

• MBx: Mailbox x Interrupt Enable

0 = No effect.

1 = Enable Mailbox x interrupt.

• ERRA: Error Active mode Interrupt Enable

0 = No effect.

1 = Enable ERRA interrupt.

• WARN: Warning Limit Interrupt Enable

0 = No effect.

1 = Enable WARN interrupt.

• ERRP: Error Passive mode Interrupt Enable

0 = No effect.

1 = Enable ERRP interrupt.

• BOFF: Bus-off mode Interrupt Enable

0 = No effect.

1 = Enable BOFF interrupt.

• SLEEP: Sleep Interrupt Enable

0 = No effect.

1 = Enable SLEEP interrupt.

• WAKEUP: Wakeup Interrupt Enable

0 = No effect.

1 = Enable SLEEP interrupt.

• TOVF: Timer Overflow Interrupt Enable

0 = No effect.

1 = Enable TOVF interrupt.

• TSTP: TimeStamp Interrupt Enable

0 = No effect.

1 = Enable TSTP interrupt.

• CERR: CRC Error Interrupt Enable

0 = No effect.

1 = Enable CRC Error interrupt.

4

MB4

28

BERR

20

SLEEP

12

AT91SAM7X256/128 Preliminary

27

FERR

19

BOFF

11

3

MB3

26

AERR

18

ERRP

10

2

MB2

25

SERR

17

WARN

9

1

MB1

24

CERR

16

ERRA

8

0

MB0

522

6120D–ATARM–02-Feb-06

• SERR: Stuffing Error Interrupt Enable

0 = No effect.

1 = Enable Stuffing Error interrupt.

• AERR: Acknowledgment Error Interrupt Enable

0 = No effect.

1 = Enable Acknowledgment Error interrupt.

• FERR: Form Error Interrupt Enable

0 = No effect.

1 = Enable Form Error interrupt.

• BERR: Bit Error Interrupt Enable

0 = No effect.

1 = Enable Bit Error interrupt.

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

523

37.8.3

CAN Interrupt Disable Register

Name:

Access Type:

CAN_IDR

Write-only

31

30

29

23

TSTP

15

22

TOVF

14

21

WAKEUP

13

7

MB7

6

MB6

5

MB5

• MBx: Mailbox x Interrupt Disable

0 = No effect.

1 = Disable Mailbox x interrupt.

• ERRA: Error Active Mode Interrupt Disable

0 = No effect.

1 = Disable ERRA interrupt.

• WARN: Warning Limit Interrupt Disable

0 = No effect.

1 = Disable WARN interrupt.

• ERRP: Error Passive mode Interrupt Disable

0 = No effect.

1 = Disable ERRP interrupt.

• BOFF: Bus-off mode Interrupt Disable

0 = No effect.

1 = Disable BOFF interrupt.

• SLEEP: Sleep Interrupt Disable

0 = No effect.

1 = Disable SLEEP interrupt.

• WAKEUP: Wakeup Interrupt Disable

0 = No effect.

1 = Disable WAKEUP interrupt.

• TOVF: Timer Overflow Interrupt

0 = No effect.

1 = Disable TOVF interrupt.

• TSTP: TimeStamp Interrupt Disable

0 = No effect.

1 = Disable TSTP interrupt.

• CERR: CRC Error Interrupt Disable

0 = No effect.

1 = Disable CRC Error interrupt.

4

MB4

28

BERR

20

SLEEP

12

AT91SAM7X256/128 Preliminary

27

FERR

19

BOFF

11

3

MB3

26

AERR

18

ERRP

10

2

MB2

25

SERR

17

WARN

9

1

MB1

24

CERR

16

ERRA

8

0

MB0

524

6120D–ATARM–02-Feb-06

• SERR: Stuffing Error Interrupt Disable

0 = No effect.

1 = Disable Stuffing Error interrupt.

• AERR: Acknowledgment Error Interrupt Disable

0 = No effect.

1 = Disable Acknowledgment Error interrupt.

• FERR: Form Error Interrupt Disable

0 = No effect.

1 = Disable Form Error interrupt.

• BERR: Bit Error Interrupt Disable

0 = No effect.

1 = Disable Bit Error interrupt.

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

525

37.8.4

CAN Interrupt Mask Register

Name:

Access Type:

CAN_IMR

Read-only

31

23

TSTP

15

30

22

TOVF

14

29

21

WAKEUP

13

7

MB7

6

MB6

5

MB5

• MBx: Mailbox x Interrupt Mask

0 = Mailbox x interrupt is disabled.

1 = Mailbox x interrupt is enabled.

• ERRA: Error Active mode Interrupt Mask

0 = ERRA interrupt is disabled.

1 = ERRA interrupt is enabled.

• WARN: Warning Limit Interrupt Mask

0 = Warning Limit interrupt is disabled.

1 = Warning Limit interrupt is enabled.

• ERRP: Error Passive Mode Interrupt Mask

0 = ERRP interrupt is disabled.

1 = ERRP interrupt is enabled.

• BOFF: Bus-off Mode Interrupt Mask

0 = BOFF interrupt is disabled.

1 = BOFF interrupt is enabled.

• SLEEP: Sleep Interrupt Mask

0 = SLEEP interrupt is disabled.

1 = SLEEP interrupt is enabled.

• WAKEUP: Wakeup Interrupt Mask

0 = WAKEUP interrupt is disabled.

1 = WAKEUP interrupt is enabled.

• TOVF: Timer Overflow Interrupt Mask

0 = TOVF interrupt is disabled.

1 = TOVF interrupt is enabled.

• TSTP: Timestamp Interrupt Mask

0 = TSTP interrupt is disabled.

1 = TSTP interrupt is enabled.

• CERR: CRC Error Interrupt Mask

0 = CRC Error interrupt is disabled.

1 = CRC Error interrupt is enabled.

28

BERR

20

SLEEP

12

4

MB4

AT91SAM7X256/128 Preliminary

27

FERR

19

BOFF

11

3

MB3

26

AERR

18

ERRP

10

2

MB2

25

SERR

17

WARN

9

1

MB1

24

CERR

16

ERRA

8

0

MB0

526

6120D–ATARM–02-Feb-06

• SERR: Stuffing Error Interrupt Mask

0 = Bit Stuffing Error interrupt is disabled.

1 = Bit Stuffing Error interrupt is enabled.

• AERR: Acknowledgment Error Interrupt Mask

0 = Acknowledgment Error interrupt is disabled.

1 = Acknowledgment Error interrupt is enabled.

• FERR: Form Error Interrupt Mask

0 = Form Error interrupt is disabled.

1 = Form Error interrupt is enabled.

• BERR: Bit Error Interrupt Mask

0 = Bit Error interrupt is disabled.

1 = Bit Error interrupt is enabled.

AT91SAM7X256/128 Preliminary

6120D–ATARM–02-Feb-06

527

AT91SAM7X256/128 Preliminary

37.8.5

CAN Status Register

Name:

Access Type:

CAN_SR

Read-only

31

OVLSY

30

TBSY

29

RBSY

23

TSTP

15

22

TOVF

14

21

WAKEUP

13

28

BERR

20

SLEEP

12

27

FERR

19

BOFF

11

26

AERR

18

ERRP

10

25

SERR

17

WARN

9

24

CERR

16

ERRA

8

7

MB7

6

MB6

5

MB5

4

MB4

3

MB3

2

MB2

1

MB1

0

MB0

• MBx: Mailbox x Event

0 = No event occurred on Mailbox x.

1 = An event occurred on Mailbox x.

An event corresponds to MRDY, MABT fields in the CAN_MSRx register.

• ERRA: Error Active mode

0 = CAN controller is not in error active mode

1 = CAN controller is in error active mode

This flag is set depending on TEC and REC counter values. It is set when node is neither in error passive mode nor in bus off mode.

This flag is automatically reset when above condition is not satisfied.

• WARN: Warning Limit

0 = CAN controller Warning Limit is not reached.

1 = CAN controller Warning Limit is reached.

This flag is set depending on TEC and REC counters values. It is set when at least one of the counters values exceeds 96.

This flag is automatically reset when above condition is not satisfied.

• ERRP: Error Passive mode

0 = CAN controller is not in error passive mode

1 = CAN controller is in error passive mode

This flag is set depending on TEC and REC counters values.

A node is error passive when TEC counter is greater or equal to 128 (decimal) or when the REC counter is greater or equal to 128 (decimal) and less than 256.

This flag is automatically reset when above condition is not satisfied.

• BOFF: Bus Off mode

0 = CAN controller is not in bus-off mode

1 = CAN controller is in bus-off mode

This flag is set depending on TEC counter value. A node is bus off when TEC counter is greater or equal to 256 (decimal).

This flag is automatically reset when above condition is not satisfied.

• SLEEP: CAN controller in Low power Mode

0 = CAN controller is not in low power mode.

1 = CAN controller is in low power mode.

528

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

This flag is automatically reset when Low power mode is disabled

• WAKEUP: CAN controller is not in Low power Mode

0 = CAN controller is in low power mode.

1 = CAN controller is not in low power mode.

When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the CAN Controller enters Low Power mode.

• TOVF: Timer Overflow

0 = The timer has not rolled-over FFFFh to 0000h.

1 = The timer rolls-over FFFFh to 0000h.

This flag is automatically cleared by reading CAN_SR register.

• TSTP Timestamp

0 = No bus activity has been detected.

1 = A start of frame or an end of frame has been detected (according to the TEOF field in the CAN_MR register).

This flag is automatically cleared by reading the CAN_SR register.

• CERR: Mailbox CRC Error

0 = No CRC error occurred during a previous transfer.

1 = A CRC error occurred during a previous transfer.

A CRC error has been detected during last reception.

This flag is automatically cleared by reading CAN_SR register.

• SERR: Mailbox Stuffing Error

0 = No stuffing error occurred during a previous transfer.

1 = A stuffing error occurred during a previous transfer.

A form error results from the detection of more than five consecutive bit with the same polarity.

This flag is automatically cleared by reading CAN_SR register.

• AERR: Acknowledgment Error

0 = No acknowledgment error occurred during a previous transfer.

1 = An acknowledgment error occurred during a previous transfer.

An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs.

This flag is automatically cleared by reading CAN_SR register.

• FERR: Form Error

0 = No form error occurred during a previous transfer

1 = A form error occurred during a previous transfer

A form error results from violations on one or more of the fixed form of the following bit fields:

– CRC delimiter

– ACK delimiter

– End of frame

– Error delimiter

– Overload delimiter

This flag is automatically cleared by reading CAN_SR register.

• BERR: Bit Error

0 = No bit error occurred during a previous transfer.

1 = A bit error occurred during a previous transfer.

529

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

A bit error is set when the bit value monitored on the line is different from the bit value sent.

This flag is automatically cleared by reading CAN_SR register.

• RBSY: Receiver busy

0 = CAN receiver is not receiving a frame.

1 = CAN receiver is receiving a frame.

Receiver busy. This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame (remote, data, overload or error frame). It is automatically reset when CAN is not receiving.

• TBSY: Transmitter busy

0 = CAN transmitter is not transmitting a frame.

1 = CAN transmitter is transmitting a frame.

Transmitter busy. This status bit is set by hardware while CAN transmitter is generating a frame (remote, data, overload or error frame). It is automatically reset when CAN is not transmitting.

• OVLSY: Overload busy

0 = CAN transmitter is not transmitting an overload frame.

1 = CAN transmitter is transmitting a overload frame.

It is automatically reset when the bus is not transmitting an overload frame.

6120D–ATARM–02-Feb-06

530

AT91SAM7X256/128 Preliminary

37.8.6

CAN Baudrate Register

Name:

Access Type:

CAN_BR

Read/Write

31

30

29

22 21 23

15

14

13

28

20

27

19

BRP

11

26

18

25

17

24

SMP

16

SJW

12 10 9

PROPAG

8

7

6 5

PHASE1

4 3

2 1

PHASE2

0

Any modification on one of the fields of the CANBR register must be done while CAN module is disabled.

To compute the different Bit Timings, please refer to the Section 37.6.4.1 ”CAN Bit Timing Configuration” on page 500 .

• PHASE2: Phase 2 segment

This phase is used to compensate the edge phase error.

t

PHS2

= t

CSC

× (

PHASE2 + 1

)

Warning: PHASE2 value must be different from 0.

• PHASE1: Phase 1 segment

This phase is used to compensate for edge phase error.

t

PHS1

= t

CSC

× (

PHASE1 + 1

)

• PROPAG: Programming time segment

This part of the bit time is used to compensate for the physical delay times within the network.

t

PRS

= t

CSC

× (

PROPAG

+

1

)

• SJW: Re-synchronization jump width

To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lengthened by re-synchronization.

t

SJW

= t

CSC

× (

SJW + 1

)

• BRP: Baudrate Prescaler.

This field allows user to program the period of the CAN system clock to determine the individual bit timing.

Tcsc = (BRP + 1) / MCK

• SMP: Sampling Mode

0 = The incoming bit stream is sampled once at sample point.

1 = The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.

SMP Sampling Mode is automatically disabled if BRP = 0.

531

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.7

CAN Timer Register

Name:

Access Type:

CAN_TIM

Read-only

31

30

23

15

TIMER15

22

14

TIMER14

29

21

13

TIMER13

28

20

12

TIMER12

27

19

11

TIMER11

7

TIMER7

6

TIMER6

5

TIMER5

4

TIMER4

• TIMERx: Timer

This field represents the internal CAN controller 16-bit timer value.

3

TIMER3

26

18

10

TIMER10

2

TIMER2

25

17

9

TIMER9

1

TIMER1

24

16

8

TIMER8

0

TIMER0

6120D–ATARM–02-Feb-06

532

AT91SAM7X256/128 Preliminary

37.8.8

CAN Timestamp Register

Name:

Access Type:

CAN_TIMESTP

Read-only

31

23

30

22

29

21

28

20

27

19

26

18

25

17

24

16

15

MTIMESTAMP

15

14

MTIMESTAMP

14

13

MTIMESTAMP

13

12

MTIMESTAMP

12

11

MTIMESTAMP

11

10

MTIMESTAMP

10

9

MTIMESTAMP

9

8

MTIMESTAMP

8

7

MTIMESTAMP

7

6

MTIMESTAMP

6

5

MTIMESTAMP

5

4

MTIMESTAMP

4

3

MTIMESTAMP

3

2

MTIMESTAMP

2

1

MTIMESTAMP

1

0

MTIMESTAMP

0

• MTIMESTAMPx: Timestamp

This field represents the internal CAN controller 16-bit timer value.

If the TEOF bit is cleared in the CAN_MR register, the internal Timer Counter value is captured in the MTIMESTAMP field at each start of frame. Else the value is captured at each end of frame. When the value is captured, the TSTP flag is set in the CAN_SR register. If the TSTP mask in the CAN_IMR register is set, an interrupt is generated while TSTP flag is set in the CAN_SR register. This flag is cleared by reading the CAN_SR register.

Note: The CAN_TIMESTP register is reset when the CAN is disabled then enabled thanks to the CANEN bit in the CAN_MR.

533

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.9

CAN Error Counter Register

Name:

Access Type:

CAN_ECR

Read-only

31

30

29

23 22 21

28

20

27

19

26

18

25

17

24

16

TEC

15

14

13

12

11

10

9

8

7 6 5 4 3 2 1 0

REC

• REC: Receive Error Counter

When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG.

When a receiver detects a dominant bit as the first bit after sending an ERROR FLAG, REC is increased by 8.

When a receiver detects a BIT ERROR while sending an ACTIVE ERROR FLAG, REC is increased by 8.

Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or

OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVER-

LOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits, each receiver increases its REC by 8.

After successful reception of a message, REC is decreased by 1 if it was between 1 and 127. If REC was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127.

• TEC: Transmit Error Counter

When a transmitter sends an ERROR FLAG, TEC is increased by 8 except when

– the transmitter is error passive and detects an ACKNOWLEDGMENT ERROR because of not detecting a dominant ACK and does not detect a dominant bit while sending its PASSIVE ERROR FLAG.

– the transmitter sends an ERROR FLAG because a STUFF ERROR occurred during arbitration and should have been recessive and has been sent as recessive but monitored as dominant.

When a transmitter detects a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG, the TEC will be increased by 8.

Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or

OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVER-

LOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits every transmitter increases its TEC by 8.

After a successful transmission the TEC is decreased by 1 unless it was already 0.

534

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.10

CAN Transfer Command Register

Name:

Access Type:

CAN_TCR

Write-only

31

TIMRST

30

29

23

15

22

14

21

13

28

20

12

7

MB7

6

MB6

5

MB5

4

MB4

This register initializes several transfer requests at the same time.

• MBx: Transfer Request for Mailbox x

3

MB3

27

19

11

10

2

MB2

26

18

9

1

MB1

25

17

8

0

MB0

24

16

Mailbox Object Type

Receive

Receive with overwrite

Transmit

Consumer

Producer

Description

It receives the next message.

This triggers a new reception.

Sends data prepared in the mailbox as soon as possible.

Sends a remote frame.

Sends data prepared in the mailbox after receiving a remote frame from a consumer.

This flag clears the MRDY and MABT flags in the corresponding CAN_MSRx register.

When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn, starting with the mailbox with the highest priority. If several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e., MB0 will be transferred before MB1).

• TIMRST: Timer Reset

Resets the internal timer counter. If the internal timer counter is frozen, this command automatically re-enables it. This command is useful in Time Triggered mode.

535

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.11

CAN Abort Command Register

Name:

Access Type:

CAN_ACR

Write-only

31

30

29

23

15

22

14

21

13

28

20

12

7

MB7

6

MB6

5

MB5

4

MB4

This register initializes several abort requests at the same time.

• MBx: Abort Request for Mailbox x

3

MB3

27

19

11

10

2

MB2

26

18

Mailbox Object Type

Receive

Receive with overwrite

Transmit

Consumer

Producer

Description

No action

No action

Cancels transfer request if the message has not been transmitted to the

CAN transceiver.

Cancels the current transfer before the remote frame has been sent.

Cancels the current transfer. The next remote frame is not serviced.

It is possible to set MACR field (in the CAN_MCRx register) for each mailbox.

9

1

MB1

25

17

8

0

MB0

24

16

536

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.12

CAN Message Mode Register

Name:

Access Type:

CAN_MMRx

Read/Write

31

23

30

22

29

21

28

20

27

19

26

18

PRIOR

25

MOT

17

24

16

15

MTIMEMARK

15

14

MTIMEMARK

14

13

MTIMEMARK

13

12

MTIMEMARK

12

11

MTIMEMARK

11

10

MTIMEMARK

10

9

MTIMEMARK9

8

MTIMEMARK8

7

MTIMEMARK7

6

MTIMEMARK6

5

MTIMEMARK5

4

MTIMEMARK4

3

MTIMEMARK3

2

MTIMEMARK2

1

MTIMEMARK1

0

MTIMEMARK0

• MTIMEMARK: Mailbox Timemark

This field is active in Time Triggered Mode. Transmit operations are allowed when the internal timer counter reaches the

Mailbox Timemark. See

”Transmitting within a Time Window” on page 518 .

In Timestamp Mode, MTIMEMARK is set to 0.

• PRIOR: Mailbox Priority

This field has no effect in receive and receive with overwrite modes. In these modes, the mailbox with the lowest number is serviced first.

When several mailboxes try to transmit a message at the same time, the mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 is serviced before

MBx 15 if they have the same priority).

• MOT: Mailbox Object Type

This field allows the user to define the type of the mailbox. All mailboxes are independently configurable. Five different types are possible for each mailbox:

0

0

0

0

1

1

1

MOT

0

0

1

1

0

0

1

0

1

0

1

0

1

X

Mailbox Object Type

Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.

Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.

Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.

Transmit mailbox. Mailbox is configured for transmission.

Consumer Mailbox. Mailbox is configured in reception but behaves as a

Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.

Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.

Reserved

537

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.13

CAN Message Acceptance Mask Register

Name:

Access Type:

CAN_MAMx

Read/Write

31

30

29

MIDE

28

23 22 21 20

MIDvA

27

19

26

MIDvA

18

25

17

MIDvB

24

16

15 14 13 12 11 10 9 8

MIDvB

7 6 5 4 3 2 1 0

MIDvB

To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to

CAN_MAMx registers.

• MIDvB: Complementary bits for identifier in extended frame mode

Acceptance mask for corresponding field of the message IDvB register of the mailbox.

• MIDvA: Identifier for standard frame mode

Acceptance mask for corresponding field of the message IDvA register of the mailbox.

• MIDE: Identifier Version

0= Compares IDvA from the received frame with the CAN_MIDx register masked with CAN_MAMx register.

1= Compares IDvA and IDvB from the received frame with the CAN_MIDx register masked with CAN_MAMx register.

538

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.14

CAN Message ID Register

Name:

Access Type:

CAN_MIDx

Read/Write

31

30

29

MIDE

23 22 21

MIDvA

28

20

27

19

26

MIDvA

18

25

17

MIDvB

24

16

15 14 13 12 11 10 9 8

MIDvB

7 6 5 4 3 2 1 0

MIDvB

To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to

CAN_MIDx registers.

• MIDvB: Complementary bits for identifier in extended frame mode

If MIDE is cleared, MIDvB value is 0.

• MIDE: Identifier Version

This bit allows the user to define the version of messages processed by the mailbox. If set, mailbox is dealing with version

2.0 Part B messages; otherwise, mailbox is dealing with version 2.0 Part A messages.

• MIDvA: Identifier for standard frame mode

539

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.15

CAN Message Family ID Register

Name:

Access Type:

CAN_MFIDx

Read-only

31

30

29

23 22 21

28

20

27

19

26

MFID

18

25

17

24

16

MFID

15 14 13 12 11 10 9 8

MFID

7 6 5 4 3 2 1 0

MFID

• MFID: Family ID

This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx register. This field is useful to speed up message ID decoding. The message acceptance procedure is described below.

As an example:

CAN_MIDx = 0x305A4321

CAN_MAMx = 0x3FF0F0FF

CAN_MFIDx = 0x000000A3

540

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.16

CAN Message Status Register

Name:

Access Type:

CAN_MSRx

Read only

31

30

29

28

20

MRTR

27

19

26

18

25

17

24

MMI

16 23

MRDY

22

MABT

21

– MDLC

15

MTIMESTAMP

15

14

MTIMESTAMP

14

13

MTIMESTAMP

13

12

MTIMESTAMP

12

11

MTIMESTAMP

11

10

MTIMESTAMP

10

9

MTIMESTAMP

9

8

MTIMESTAMP

8

7

MTIMESTAMP

7

6

MTIMESTAMP

6

5

MTIMESTAMP

5

4

MTIMESTAMP

4

3

MTIMESTAMP

3

2

MTIMESTAMP

2

1

MTIMESTAMP

1

0

MTIMESTAMP

0

These register fields are updated each time a message transfer is received or aborted.

MMI is cleared by reading the CAN_MSRx register.

MRDY, MABT are cleared by writing MTCR or MACR in the CAN_MCRx register.

Warning: MRTR and MDLC state depends partly on the mailbox object type.

• MTIMESTAMP: Timer value

This field is updated only when time-triggered operations are disabled (TTM cleared in CAN_MR register). If the TEOF field in the CAN_MR register is cleared, TIMESTAMP is the internal timer value at the start of frame of the last message received or sent by the mailbox. If the TEOF field in the CAN_MR register is set, TIMESTAMP is the internal timer value at the end of frame of the last message received or sent by the mailbox.

In Time Triggered Mode, MTIMESTAMP is set to 0.

• MDLC: Mailbox Data Length Code

Mailbox Object Type

Receive

Receive with overwrite

Transmit

Consumer

Producer

Description

Length of the first mailbox message received

Length of the last mailbox message received

No action

Length of the mailbox message received

Length of the mailbox message to be sent after the remote frame reception

541

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

• MRTR: Mailbox Remote Transmission Request

Mailbox Object Type Description

Receive The first frame received has the RTR bit set.

Receive with overwrite The last frame received has the RTR bit set.

Transmit

Consumer

Producer

Reserved

Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 1.

Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 0.

• MABT: Mailbox Message Abort

An interrupt is triggered when MABT is set.

0 = Previous transfer is not aborted.

1 = Previous transfer has been aborted.

This flag is cleared by writing to CAN_MCRx register

Mailbox Object Type Description

Receive Reserved

Receive with overwrite Reserved

Transmit

Consumer

Producer

Previous transfer has been aborted

The remote frame transfer request has been aborted.

The response to the remote frame transfer has been aborted.

542

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

• MRDY: Mailbox Ready

An interrupt is triggered when MRDY is set.

0 = Mailbox data registers can not be read/written by the software application. CAN_MDx are locked by the CAN_MDx.

1 = Mailbox data registers can be read/written by the software application.

This flag is cleared by writing to CAN_MCRx register.

Mailbox Object Type Description

Receive

Receive with overwrite

Transmit

At least one message has been received since the last mailbox transfer order. Data from the first frame received can be read in the CAN_MDxx registers.

After setting the MOT field in the CAN_MMR, MRDY is reset to 0.

At least one frame has been received since the last mailbox transfer order. Data from the last frame received can be read in the CAN_MDxx registers.

After setting the MOT field in the CAN_MMR, MRDY is reset to 0.

Mailbox data have been transmitted.

After setting the MOT field in the CAN_MMR, MRDY is reset to 1.

Consumer

Producer

At least one message has been received since the last mailbox transfer order. Data from the first message received can be read in the CAN_MDxx registers.

After setting the MOT field in the CAN_MMR, MRDY is reset to 0.

A remote frame has been received, mailbox data have been transmitted.

After setting the MOT field in the CAN_MMR, MRDY is reset to 1.

• MMI: Mailbox Message Ignored

0 = No message has been ignored during the previous transfer

1 = At least one message has been ignored during the previous transfer

Cleared by reading the CAN_MSRx register.

Mailbox Object Type

Receive

Receive with overwrite

Transmit

Consumer

Producer

Description

Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message.

Set when at least two messages intended for the mailbox have been sent. The last one is available in the mailbox data register. Previous ones have been lost.

Reserved

A remote frame has been sent by the mailbox but several messages have been received. The first one is available in the mailbox data register. Others have been ignored. Another mailbox with a lower priority may have accepted the message.

A remote frame has been received, but no data are available to be sent.

543

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.17

CAN Message Data Low Register

Name:

Access Type:

CAN_MDLx

Read/Write

31 30 29 28 27 26 25 24

MDL

23 22 21 20 19 18 17 16

MDL

15 14 13 12 11 10 9 8

MDL

7 6 5 4 3 2 1 0

MDL

• MDL: Message Data Low Value

When MRDY field is set in the CAN_MSRx register, the lower 32 bits of a received message can be read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message.

In Receive with overwrite, the CAN controller may modify MDL value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set.

544

6120D–ATARM–02-Feb-06

AT91SAM7X256/128 Preliminary

37.8.18

CAN Message Data High Register

Name:

Access Type:

CAN_MDHx

Read/Write

31 30 29 28 27 26 25 24

MDH

23 22 21 20 19 18 17 16

MDH

15 14 13 12 11 10 9 8

MDH

7 6 5 4 3 2 1 0

MDH

• MDH: Message Data High Value

When MRDY field is set in the CAN_MSRx register, the upper 32 bits of a received message are read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message.

In Receive with overwrite, the CAN controller may modify MDH value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set.

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37.8.19

CAN Message Control Register

Name:

Access Type:

CAN_MCRx

Write-only

31

30

29

23

MTCR

22

MACR

21

15

14

13

7

6

5

• MDLC: Mailbox Data Length Code

28

20

MRTR

12

4

11

3

27

19

26

18

10

2

MDLC

9

1

25

17

0

8

24

16

Mailbox Object Type

Receive

Receive with overwrite

Transmit

Consumer

Producer

Description

No action.

No action.

Length of the mailbox message.

No action.

Length of the mailbox message to be sent after the remote frame reception.

• MRTR: Mailbox Remote Transmission Request

Mailbox Object Type

Receive

Receive with overwrite

Transmit

Consumer

Producer

Description

No action

No action

Set the RTR bit in the sent frame

No action, the RTR bit in the sent frame is set automatically

No action

Consumer situations can be handled automatically by setting the mailbox object type in Consumer. This requires only one mailbox.

It can also be handled using two mailboxes, one in reception, the other in transmission. The MRTR and the MTCR bits must be set in the same time.

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• MACR: Abort Request for Mailbox x

Mailbox Object Type

Receive

Receive with overwrite

Transmit

Consumer

Producer

Description

No action

No action

Cancels transfer request if the message has not been transmitted to the

CAN transceiver.

Cancels the current transfer before the remote frame has been sent.

Cancels the current transfer. The next remote frame will not be serviced.

It is possible to set MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR register.

• MTCR: Mailbox Transfer Command

Mailbox Object Type

Receive

Receive with overwrite

Transmit

Consumer

Producer

Description

Allows the reception of the next message.

Triggers a new reception.

Sends data prepared in the mailbox as soon as possible.

Sends a remote transmission frame.

Sends data prepared in the mailbox after receiving a remote frame from a

Consumer.

This flag clears the MRDY and MABT flags in the CAN_MSRx register.

When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn. The mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 will be serviced before MBx 15 if they have the same priority).

It is possible to set MTCR for several mailboxes at the same time by writing to the CAN_TCR register.

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