Configuring Stratix III Devices

Configuring Stratix III Devices
11. Configuring Stratix III Devices
SIII51011-2.0
This chapter contains complete information about Stratix® III supported configuration
schemes, how to execute the required configuration schemes, and all necessary option
pin settings.
Stratix III devices use SRAM cells to store configuration data. Because SRAM memory
is volatile, you must download configuration data to the Stratix III device each time
the device powers up. You can configure Stratix III devices using one of four
configuration schemes:
■
Fast passive parallel (FPP)
■
Fast active serial (AS)
■
Passive serial (PS)
■
Joint Test Action Group (JTAG)
All configuration schemes use an external controller (for example, a MAX® II device
or microprocessor), a configuration device, or a download cable. Refer to
“Configuration Features” on page 11–3 for more information.
Configuration Devices
The Altera® serial configuration devices (EPCS128, EPCS64, and EPCS16) support a
single-device and multi-device configuration solution for Stratix III devices and are
used in the fast AS configuration scheme. Serial configuration devices offer a
low-cost, low-pin count configuration solution.
f
For information about serial configuration devices, refer to the Serial Configuration
Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet in volume 2 of the
Configuration Handbook.
All minimum timing information in this handbook covers the entire Stratix III family.
Some devices may work at less than the minimum timing stated in this handbook due
to process variation.
Configuration Schemes
Select the configuration scheme by driving the Stratix III device MSEL pins either high
or low, as detailed in Table 11–1. The MSEL pins are powered by the VCCPGM power
supply of the bank they reside in. The MSEL[2..0] pins have 5-kΩ internal
pull-down resistors that are always active. During power-on reset (POR) and
reconfiguration, the MSEL pins must be at LVTTL VIL and VIH levels to be considered a
logic low and logic high.
1
© March 2011
To avoid any problems with detecting an incorrect configuration scheme, hard-wire
the MSEL[] pins to VCCPGM and GND, without any pull-up or pull-down resistors. Do
not drive the MSEL[] pins with a microprocessor or another device.
Altera Corporation
Stratix III Device Handbook, Volume 1
11–2
Chapter 11: Configuring Stratix III Devices
Configuration Devices
Table 11–1. Stratix III Configuration Schemes
Configuration Scheme
MSEL2
MSEL1
MSEL0
Fast passive parallel (FPP)
0
0
0
Passive serial (PS)
0
1
0
Fast AS (40 MHz) (1)
0
1
1
Remote system upgrade fast AS (40 MHz)
(1)
0
1
1
FPP with design security feature,
decompression, or both enabled (2)
0
0
1
(3)
(3)
(3)
JTAG-based configuration (4)
Notes to Table 11–1:
(1) To support fast AS configuration for Stratix III, you must use EPCS16, EPCS64, or EPCS128 devices. For more
information, refer to Serial Configuration Devices Data Sheet chapter.
(2) These modes are only supported when using a MAX® II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is ×4 the data rate.
(3) Do not leave the MSEL pins floating. Connect them to VCCPGM or ground. These pins support the non-JTAG
configuration scheme used in production. If you only use JTAG configuration, connect the MSEL pins to ground.
(4) JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pin settings
are ignored.
Table 11–2 lists the uncompressed raw binary file (.rbf) configuration file sizes for
Stratix III devices.
Table 11–2. Stratix III Uncompressed Raw Binary File (.rbf) Sizes
Device
Data Size (Bits)
EP3SL50
22, 178, 792
EP3SL70
22, 178, 792
EP3SL110
47, 413, 312
EP3SL150
47, 413, 312
EP3SL200
93, 324, 656
EP3SL340
117, 387, 664
EP3SE50
25, 891, 968
EP3SE80
48, 225, 392
EP3SE110
48, 225, 392
EP3SE260
93, 324, 656
Use the data in Table 11–2 to estimate the file size before design compilation. Different
configuration file formats, such as a hexadecimal (.hex) or tabular text file (.ttf)
format, have different file sizes. Refer to the Quartus ® II software for the different
types of configuration file and the file sizes. However, for any specific version of the
Quartus II software, any design targeted for the same device will have the same
uncompressed configuration file size. If you are using compression, the file size can
vary after each compilation because the compression ratio is dependent on the design.
f
For more information about setting device configuration options or creating
configuration files, refer to the Device Configuration Options and Configuration File
Formats chapters in volume 2 of the Configuration Handbook.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Configuration Features
11–3
Configuration Features
Stratix III devices offer design security, decompression, and remote system upgrade
features. Design security using configuration bitstream encryption is available in
Stratix III devices, which protects your designs. Stratix III devices can receive a
compressed configuration bitstream and decompress this data in real-time, reducing
storage requirements and configuration time. You can make real-time system
upgrades from remote locations of your Stratix III designs with the remote system
upgrade feature.
Table 11–3 summarizes which configuration features you can use in each
configuration scheme.
Table 11–3. Stratix III Configuration Features
Configuration
Scheme
Configuration Method
Decompression
Design Security
Remote System
Upgrade
v (1)
v (1)
—
FPP
MAX II device or a microprocessor with
flash memory
Fast AS
Serial configuration device
v
v
v (2)
PS
MAX II device or a microprocessor with
flash memory
v
v
—
Download cable
v
v
—
MAX II device or a microprocessor with
flash memory
—
—
—
Download cable
—
—
—
JTAG
Notes to Table 11–3:
(1) In these modes, the host system must send a DCLK that is ×4 the data rate.
(2) Remote system upgrade is only available in the fast AS configuration scheme. Only remote update mode is supported when using the fast AS
configuration scheme. Local update mode is not supported.
If your system already contains a common flash interface (CFI) flash memory, you can
use it for the Stratix III device configuration storage as well. The MAX II parallel flash
loader (PFL) feature in MAX II devices provides an efficient method to program CFI
flash memory devices through the JTAG interface, and the logic to control
configuration from the flash memory device to the Stratix III device. Both PS and FPP
configuration modes are supported using the PFL feature.
© March 2011
f
For more information about PFL, refer to AN 386: Using the MAX II Parallel Flash
Loader with the Quartus II Software.
f
For more information about programming Altera serial configuration devices, refer to
“Programming Serial Configuration Devices” on page 11–25.
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Stratix III Device Handbook, Volume 1
11–4
Chapter 11: Configuring Stratix III Devices
Configuration Features
Configuration Data Decompression
Stratix III devices support configuration data decompression, which saves
configuration memory space and time. This feature allows you to store compressed
configuration data in configuration devices or other memory and transmit this
compressed bitstream to Stratix III devices. During configuration, the Stratix III
device decompresses the bitstream in real time and programs its SRAM cells.
1
Preliminary data indicates that compression typically reduces the configuration
bitstream size by 35 to 55%, based on the designs used.
Stratix III devices support decompression in the FPP (when using a MAX II
device/microprocessor + flash), fast AS, and PS configuration schemes. The Stratix III
decompression feature is not available in the JTAG configuration scheme.
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When using FPP mode, the intelligent host must provide a DCLK that is ×4 the data
rate. Therefore, the configuration data must be valid for four DCLK cycles.
In PS mode, use the Stratix III decompression feature, because sending compressed
configuration data reduces configuration time.
When you enable compression, the Quartus II software generates configuration files
with compressed configuration data. This compressed file reduces the storage
requirements in the configuration device or flash memory, and decreases the time
needed to transmit the bitstream to the Stratix III device. The time required by a
Stratix III device to decompress a configuration file is less than the time needed to
transmit the configuration data to the device.
There are two ways to enable compression for Stratix III bitstreams: before design
compilation (in the Compiler Settings menu) and after design compilation (in the
Convert Programming Files window).
To enable compression in the project's Compiler Settings menu, perform the following
steps:
1. On the Assignments menu, click Device. The Settings dialog box appears.
2. In the Family list, select Stratix III and then click the Device and Pin Options
button.
3. On the Configuration tab, turn on the Generate compressed bitstreams
option(Figure 11–1).
Stratix III Device Handbook, Volume 1
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Altera Corporation
Chapter 11: Configuring Stratix III Devices
Configuration Features
11–5
Figure 11–1. Enabling Compression for Stratix III Bitstreams in Compiler Settings
You can also enable compression when creating programming files from the Convert
Programming Files window.
1. On the File menu, click Convert Programming Files.
2. In the (.pof, .sram, .hex, .rbf, or .ttf) list, select the programming file type.
3. For POF output files, select a configuration device from (.pof, .sram, .hex, .rbf, or
.ttf).
4. Under Input files to convert, select SOF Data.
5. Select Add File and add a Stratix III device SOF or SOFs.
6. Select the name of the file you added to the SOF Data area and click Properties.
7. Check the Compression check box.
When multiple Stratix III devices are cascaded, you can selectively enable the
compression feature for each device in the chain if you are using a serial configuration
scheme. Figure 11–2 shows a chain of two Stratix III devices. The first Stratix III device
has compression enabled, and receives a compressed bitstream from the configuration
device. The second Stratix III device has the compression feature disabled, and
receives uncompressed data.
In a multi-device FPP configuration chain (with a MAX II device/microprocessor +
flash), all Stratix III devices in the chain must either enable or disable the
decompression feature. You cannot selectively enable the compression feature for
each device in the chain because of the DATA and DCLK relationship.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
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Chapter 11: Configuring Stratix III Devices
Configuration Features
Figure 11–2. Compressed and Uncompressed Configuration Data in the Same Configuration File
Serial Configuration Data
Serial Configuration
Device
Uncompressed
Configuration
Data
Compressed
Configuration
Data
Decompression
Controller
Stratix III
FPGA
Stratix III
FPGA
nCE
nCEO
nCE
nCEO
N.C.
GND
To generate programming files for this setup in the Quartus II software, on the File
menu, click Convert Programming Files.
Design Security Using Configuration Bitstream Encryption
Stratix III devices support decryption of configuration bitstreams using the advanced
encryption standard (AES) algorithm—the most advanced encryption algorithm
available today. Both non-volatile and volatile key programming are supported using
Stratix III devices. When using the design security feature, a 256-bit security key is
stored in the Stratix III device. To successfully configure a Stratix III device that has
the design security feature enabled, the device must be configured with a
configuration file that was encrypted using the same 256-bit security key. Non-volatile
key programming does not require any external devices, such as a battery backup, for
storage. However, for certain applications, you can store the security keys in volatile
memory in the Stratix III device. An external battery is needed for this volatile key
storage.
1
f
When using a serial configuration scheme such as PS or fast AS, configuration time is
the same whether or not the design security feature is enabled. If the FPP scheme is
used with the design security or decompression feature, a ×4 DCLK is required. This
results in a slower configuration time when compared to the configuration time of a
Stratix III device that has neither the design security nor the decompression feature
enabled.
For more information about this feature, refer to the Design Security in Stratix III
Devices chapter in volume 1 of the Stratix III Device Handbook.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Configuration Features
11–7
Remote System Upgrade
f
Stratix III devices contain the remote update feature. For more information about this
feature, refer to the Remote System Upgrades with Stratix III Devices in volume 1 of the
Stratix III Device Handbook.
Power-On Reset Circuit
The POR circuit keeps the entire system in reset until the power supply voltage levels
have stabilized on power-up. On power-up, the device does not release nSTATUS
until VCCPT, VCCL, VCC, VCCPD, and VCCPGM are above the device’s POR trip point. On
power down, brown-out occurs if VCC or V CCL ramps down below the POR trip point
and VCC, VCCPD, or VCCPGM drops below the threshold voltage.
In Stratix III devices, a pin-selectable option (PORSEL) is provided that allows you to
select a typical POR time setting of 12 ms or 100 ms. In both cases, you can extend the
POR time by using an external component to assert the nSTATUS pin low.
VCCPGM Pins
Stratix III devices offer a new power supply, V CCPGM, for all the dedicated configuration
pins and dual function pins. The configuration voltages supported are 1.8 V, 2.5 V,
3.0 V, and 3.3 V. Stratix III devices do not support the 1.5 V configuration.
Use this pin to power all dedicated configuration inputs, dedicated configuration
outputs, dedicated configuration bi-directional pins, and some of the dual functional
pins that you use for configuration. With VCCPGM, configuration input buffers do not
have to share power lines with the regular I/O buffer in Stratix III devices.
The operating voltage for the configuration input pin is independent of the I/O
bank’s power supply V CCIO during the configuration. Therefore, no configuration
voltage constraints on VCCIO are needed in Stratix III devices.
VCCPD Pins
Stratix III devices have a dedicated programming power supply, VCCPD, which must be
connected to 3.3 V/3.0 V/2.5 V to power the I/O pre-drivers, the JTAG input and
output pins (TCK, TMS, TDI, TDO, and TRST), and the design security circuitry.
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© March 2011
VCCPGM and VCCPD must ramp up from 0 V to the desired voltage level within 100 ms. If
these supplies are not ramped up within this specified time, your Stratix III device
will not configure successfully. If your system does not allow ramp-up time of 100 ms
or less, you must hold nCONFIG low until all power supplies are stable.
For more information about the configuration pins power supply, refer to “Device
Configuration Pins” on page 11–43.
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Stratix III Device Handbook, Volume 1
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Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
Fast Passive Parallel Configuration
Fast passive parallel (FPP) configuration in Stratix III devices is designed to meet the
continuously increasing demand for faster configuration times. Stratix III devices are
designed with the capability of receiving byte-wide configuration data per clock
cycle. Table 11–4 lists the MSEL pin settings when using the FPP configuration scheme.
Table 11–4. Stratix III MSEL Pin Settings for FPP Configuration Schemes
Configuration Scheme
MSEL2
MSEL1
MSEL0
Fast Passive Parallel (FPP)
0
0
0
FPP with the design security feature, decompression feature, or
both enabled (1)
0
0
1
Note to Table 11–4:
(1) These modes are only supported when using a MAX II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is ×4 the data rate.
You can perform FPP configuration of Stratix III devices using an intelligent host,
such as a MAX II device, or a microprocessor.
FPP Configuration Using a MAX II Device as an External Host
FPP configuration using compression and an external host provides the fastest
method to configure Stratix III devices. In this configuration scheme, you can use a
MAX II device as an intelligent host that controls the transfer of configuration data
from a storage device, such as flash memory, to the target Stratix III device. You can
store configuration data in .rbf, .hex, or .ttf format. When using the MAX II device as
an intelligent host, a design that controls the configuration process, such as fetching
the data from flash memory and sending it to the device, must be stored in the MAX II
device.
1
If you are using the Stratix III decompression feature, design security feature or both,
the external host must be able to send a DCLK frequency that is four times the data
rate.
The ×4 DCLK signal does not require an additional pin and is sent on the DCLK pin.
The maximum DCLK frequency is 100 MHz, which results in a maximum data rate of
200 Mbps. If you are not using the Stratix III decompression or design security
features, the data rate is the same as the DCLK frequency.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
11–9
Figure 11–3 shows the configuration interface connections between the Stratix III
device and a MAX II device for single device configuration.
Figure 11–3. Single Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
VCCPGM (1) VCCPGM (1)
10 kΩ
10 kΩ
Stratix III Device
MSEL[2..0]
CONF_DONE
GND
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCEO
nCE
GND
N.C.
DATA[7..0]
nCONFIG
DCLK
Note to Figure 11–3:
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix III device. VCCPGM should be
high enough to meet the V IH specification of the I/O on the external host. It is recommended to power up all
configuration system’s I/O with VCCPGM.
Upon power-up, the Stratix III device goes through a POR. The POR delay is
dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is
approximately 100 ms. When PORSEL is driven high, the POR time is approximately
12 ms. During POR, the device resets, holds nSTATUS low, and tri-states all user I/O
pins. After the device successfully exits POR, all user I/O pins continue to be
tri-stated. If nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are on (after
POR) before and during configuration. If nIO_pullup is driven high, the weak
pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and initialization.
While nCONFIG or nSTATUS is low, the device is in the reset stage. To initiate
configuration, the MAX II device must drive the nCONFIG pin from low to high.
1
VCC, VCCIO, VCCPGM, and VCCPD of the banks where the configuration and JTAG pins
reside must be fully powered to the appropriate voltage levels to begin the
configuration process.
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the MAX II device places
the configuration data one byte at a time on the DATA[7..0] pins.
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© March 2011
Stratix III devices receive configuration data on the DATA[7..0] pins and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If
you are using the Stratix III decompression feature, design security feature, or both,
the configuration data is latched on the rising edge of every fourth DCLK cycle. After
the configuration data is latched in, it is processed during the following three DCLK
cycles.
Altera Corporation
Stratix III Device Handbook, Volume 1
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Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
Data is continuously clocked into the target device until CONF_DONE goes high. A
low-to-high transition on CONF_DONE indicates configuration is complete and
initialization of the device can begin. The CONF_DONE pin must have an external
10-kΩ pull-up resistor for the device to initialize.
In Stratix III devices, the initialization clock source is either the internal oscillator
(typically 10 MHz) or the optional CLKUSR pin. By default, the internal oscillator is
the clock source for initialization. If you use the internal oscillator, the Stratix III
device receives enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to the device
after configuration is complete does not affect device operation.
You can also synchronize initialization of multiple devices or delay initialization with
the CLKUSR option. You can turn on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software from the General tab of the Device and
Pin Options dialog box. Supplying a clock on CLKUSR does not affect the
configuration process. After the CONF_DONE pin transitions high, CLKUSR is enabled
after the time specified as tCD2CU. When this time period elapses, Stratix III devices
require 4,436 clock cycles to initialize properly and enter user mode. Stratix III devices
support a CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of initialization and
the start of user mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software on the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high because of an
external 10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin goes low.
When initialization is complete, the INIT_DONE pin is released and pulled high. The
MAX II device must be able to detect this low-to-high transition, which signals the
device has entered user mode. When initialization is complete, the device enters user
mode. In user mode, the user I/O pins no longer have weak pull-up resistors and
function as assigned in your design.
To ensure DCLK and DATA[7..0] are not left floating at the end of configuration, the
MAX II device must drive them either high or low, whichever is convenient on your
board. During configuration, DATA[7..0] pins are powered by V CCPGM. After
entering user mode, these pins are available as user I/O pins that are powered by
VCCIO. When you select the FPP scheme as a default in the Quartus II software, these
I/O pins are tri-stated in user mode. To change this default option in the Quartus II
software, select the Dual-Purpose Pins tab of the Device and Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified frequency to
ensure correct configuration. No maximum DCLK period exists, which means you can
pause configuration by halting DCLK for an indefinite amount of time.
1
If you are using the Stratix III decompression feature, design security feature, or both
and need to stop DCLK, it can only be stopped three clock cycles after the last data byte
was latched into the Stratix III device. If you are using the Stratix III device without
decompression or design security feature, the DCLK can only be stopped two clock
cycles after the last data byte was latched into the Stratix III device.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
11–11
By stopping DCLK, the configuration circuit allows enough clock cycles to process the
last byte of latched configuration data. When the clock restarts, the MAX II device
must provide data on the DATA[7..0] pins prior to sending the first DCLK rising
edge.
If an error occurs during configuration, the device drives its nSTATUS pin low,
resetting itself internally. The low signal on the nSTATUS pin also alerts the MAX II
device that there is an error. If the Auto-restart configuration after error option
(available in the Quartus II software on the General tab of the Device and Pin
Options dialog box) is turned on, the device releases nSTATUS after a reset time-out
period (maximum of 100 μs). After nSTATUS is released and pulled high by a pull-up
resistor, the MAX II device can try to reconfigure the target device without needing to
pulse nCONFIG low. If this option is turned off, the MAX II device must generate a
low-to-high transition (with a low pulse of at least 2 μs) on nCONFIG to restart the
configuration process.
1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the tSTATUS specification.
The MAX II device can also monitor the CONF_DONE and INIT_DONE pins to ensure
successful configuration. The MAX II device must monitor the CONF_DONE pin to
detect errors and determine when programming completes. If all configuration data is
sent, but the CONF_DONE or INIT_DONE signals have not gone high, the MAX II
device will reconfigure the target device.
1
If you use the optional CLKUSR pin and the nCONFIG is pulled low to restart
configuration during device initialization, you must ensure CLKUSR continues
toggling during the time nSTATUS is low (maximum of 100 µs).
When the device is in user mode, transitioning the nCONFIG pin low to high initiates
a reconfiguration. The nCONFIG pin should be low for at least 2 μs. When nCONFIG is
pulled low, the device also pulls nSTATUS and CONF_DONE low and all I/O pins are
tri-stated. After nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
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Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
Figure 11–4 shows how to configure multiple devices using a MAX II device. This
circuit is similar to the FPP configuration circuit for a single device, except the
Stratix III devices are cascaded for multi-device configuration.
Figure 11–4. Multi-Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
VCCPGM (1) VCCPGM (1)
10 kΩ
10 kΩ
Stratix III Device 2
Stratix III Device 1
MSEL[2..0]
MSEL[2..0]
CONF_DONE
CONF_DONE
GND
nSTATUS
nCE
External Host
(MAX II Device or
Microprocessor)
nCEO
GND
nSTATUS
nCE
nCEO
N.C.
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Note to Figure 11–4:
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix III devices on the chain. V CCPGM should be high enough to
meet the V IH specification of the I/O on the external host. It is recommended to power up all configuration system’s I/O with V CCPGM.
In a multi-device FPP configuration, the first device’s nCE pin is connected to GND
while its nCEO pin is connected to nCE of the next device in the chain. The last
device’s nCE input comes from the previous device, while its nCEO pin is left floating.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the second device’s nCE pin, which prompts the
second device to begin configuration. The second device in the chain begins
configuration within one clock cycle; therefore, the transfer of data destinations is
transparent to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[7..0], and CONF_DONE) are connected to every device in the chain. The
configuration signals may require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device. Because all device CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time.
All nSTATUS and CONF_DONE pins are tied together. If any device detects an error,
configuration stops for the entire chain and you must reconfigure the entire chain. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUS pin low. This behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the devices release
their nSTATUS pins after a reset time-out period (maximum of 100 μs). After all
nSTATUS pins are released and pulled high, the MAX II device tries to reconfigure the
chain without pulsing nCONFIG low. If this option is turned off, the MAX II device
must generate a low-to-high transition (with a low pulse of at least 2 μs) on nCONFIG
to restart the configuration process.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
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11–13
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the tSTATUS specification.
In a multi-device FPP configuration chain, all Stratix III devices in the chain must
either enable or disable the decompression feature, design security feature, or both.
You cannot selectively enable the decompression feature, design security feature, or
both for each device in the chain because of the DATA and DCLK relationship. If the
chain contains devices that do not support design security, you should use a serial
configuration scheme.
If a system has multiple devices that contain the same configuration data, tie all
device nCE inputs to GND, and leave nCEO pins floating. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every
device in the chain. Configuration signals may require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered for every fourth device. Devices must be the same density and package. All
devices start and complete configuration at the same time. Figure 11–5 shows a
multi-device FPP configuration when both Stratix III devices are receiving the same
configuration data.
Figure 11–5. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same Data
Memory
ADDR DATA[7..0]
VCCPGM (1) VCCPGM (1)
10 kΩ
Stratix III Device
10 kΩ
Stratix III Device
MSEL[2..0]
CONF_DONE
nSTATUS
nCE
External Host
(MAX II Device or
Microprocessor)
GND
MSEL[2..0]
CONF_DONE
GND
nCEO
nSTATUS
nCE
N.C. (2)
GND
nCEO
N.C. (2)
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Notes to Figure 11–5:
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix III devices on the chain. V CCPGM should be high enough to
meet the V IH specification of the I/O on the external host. It is recommended to power up all configuration system’s I/O with V CCPGM.
(2) The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple devices.
You can use a single configuration chain to configure Stratix III devices with other
Altera devices that support FPP configuration, such as other types of Stratix devices.
To ensure that all devices in the chain complete configuration at the same time, or that
an error flagged by one device initiates reconfiguration in all devices, tie all of the
device CONF_DONE and nSTATUS pins together.
f
© March 2011
For more information about configuring multiple Altera devices in the same
configuration chain, refer to Configuring Mixed Altera FPGA Chains in the Configuration
Handbook.
Altera Corporation
Stratix III Device Handbook, Volume 1
11–14
Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
FPP Configuration Timing
Figure 11–6 shows the timing waveform for FPP configuration using a MAX II device
as an external host. This waveform shows the timing when the decompression and
the design security feature are not enabled.
Figure 11–6. FPP Configuration Timing Waveform (Note 1), (2)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (3)
tSTATUS
tCF2ST0
t
(7)
CLK
CONF_DONE (4)
tCF2CD
tST2CK
tCH tCL
(5)
DCLK
tDH
DATA[7..0]
Byte 0
Byte 1
(6)
Byte 2
Byte 3
User Mode
Byte n-2 Byte n-1 Byte n
tDSU
User I/O
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 11–6:
(1) You should use this timing waveform when the decompression and design security features are not used.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(3) Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay.
(4) Upon power-up, before and during configuration, CONF_DONE is low.
(5) You should not leave DCLK floating after configuration. You should drive it high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings.
(7) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
Table 11–5 defines the timing parameters for Stratix III devices for FPP configuration
when the decompression and the design security features are not enabled.
Table 11–5. FPP Timing Parameters for Stratix III Devices (Note 1) (Part 1 of 2)
Symbol
Parameter
Minimum
Maximum
Units
tCF 2CD
nCONFIG low to CONF_DONE low
—
800
ns
tCF 2ST0
nCONFIG low to nSTATUS low
—
800
ns
tCF G
nCONFIG low pulse width
2
—
μs
tSTATUS
nSTATUS low pulse width
10
100 (2)
μs
tCF 2ST1
nCONFIG high to nSTATUS high
—
100 (2)
μs
tCF 2CK
nCONFIG high to first rising edge on DCLK
100
—
μs
tST2C K
nSTATUS high to first rising edge of DCLK
2
—
μs
tDSU
Data setup time before rising edge on DCLK
5
—
ns
tDH
Data hold time after rising edge on DCLK
0
—
ns
tCH
DCLK high time
4
—
ns
tCL
DCLK low time
4
—
ns
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
11–15
Table 11–5. FPP Timing Parameters for Stratix III Devices (Note 1) (Part 2 of 2)
Symbol
Parameter
Minimum
Maximum
Units
tCLK
DCLK period
10
—
ns
fM AX
DCLK frequency
—
100
MHz
tR
Input rise time
—
40
ns
t
Input fall time
—
40
ns
tCD2UM
CONF_DONE high to user mode (3)
20
100
μs
tCD2C U
CONF_DONE high to CLKUSR enabled
—
—
—
—
4 × maximum
DCLK period
tCD2CU + (4,436
CONF_DONE high to user mode with CLKUSR option on
tCD2UM C
× CLKUSR
period)
Notes to Table 11–5:
(1) Use these timing parameters when the decompression and design security features are not used.
(2) This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for starting up the device.
Figure 11–7 shows the timing waveform for FPP configuration when using a MAX II
device as an external host. This waveform shows the timing when the decompression
feature, design security feature, or both are enabled.
Figure 11–7. FPP Configuration Timing Waveform with Decompression or Design Security Feature Enabled (Note 1), (2)
tCF2ST1
tCFG
nCONFIG
(3) nSTATUS
tCF2CK
tSTATUS
tCF2ST0
(8)
(4) CONF_DONE
tCF2CD
tCL
tST2CK
DCLK
tCH
1
2
3
4
1
2
3
4
(7)
1
3
(5)
4
tCLK
DATA[7..0]
tDSU
User I/O
Byte 0
Byte 1
tDH
tDH
(7)
Byte 2
Byte (n-1) Byte n
(6)
User Mode
User Mode
High-Z
INIT_DONE
tCD2UM
Notes to Figure 11–7:
(1) Use this timing waveform when the decompression feature, design security feature, or both are used.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(3) Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay.
(4) Upon power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. Drive it high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings.
(7) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to sending
the first DCLK rising edge.
(8) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–16
Chapter 11: Configuring Stratix III Devices
Fast Passive Parallel Configuration
Table 11–6 defines the timing parameters for Stratix III devices for FPP configuration
when the decompression feature, design security feature, or both are enabled.
Table 11–6. FPP Timing Parameters for Stratix III Devices with Decompression or Design Security Feature Enabled
(Note 1)
Symbol
Parameter
Minimum
Maximum
Units
tCF 2CD
nCONFIG low to CONF_DONE low
—
800
ns
tCF 2ST0
nCONFIG low to nSTATUS low
—
800
ns
tCF G
nCONFIG low pulse width
2
—
μs
tSTATUS
nSTATUS low pulse width
10
100 (2)
μs
tCF 2ST1
nCONFIG high to nSTATUS high
—
100 (2)
μs
tCF 2CK
nCONFIG high to first rising edge on DCLK
100
—
μs
tST2C K
nSTATUS high to first rising edge of DCLK
2
—
μs
tDSU
Data setup time before rising edge on DCLK
5
—
ns
tDH
Data hold time after rising edge on DCLK
30
—
ns
tCH
DCLK high time
4
—
ns
tCL
DCLK low time
4
—
ns
tCLK
DCLK period
10
—
ns
fM AX
DCLK frequency
—
100
MHz
tDATA
Data rate
—
200
Mbps
tR
Input rise time
—
40
ns
t
Input fall time
—
40
ns
tCD2UM
CONF_DONE high to user mode (3)
20
100
μs
tCD2C U
CONF_DONE high to CLKUSR enabled
—
—
tCD2UM C
CONF_DONE high to user mode with CLKUSR option on
—
—
4 × maximum
DCLK period
tCD2C U + (4,436 ×
CLKUSR period)
Notes to Table 11–6:
(1) Use these timing parameters when the decompression and design security features are used.
(2) This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for starting up the device.
f
Device configuration options and how to create configuration files are discussed
further in the Device Configuration Options and Configuration File Formats chapters in
volume 2 of the Configuration Handbook.
FPP Configuration Using a Microprocessor
In this configuration scheme, a microprocessor can control the transfer of
configuration data from a storage device, such as flash memory, to the target Stratix III
device.
1
All information in “FPP Configuration Using a MAX II Device as an External Host”
on page 11–8 is also applicable when using a microprocessor as an external host. Refer
to this section for all configuration and timing information.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
11–17
Fast Active Serial Configuration (Serial Configuration Devices)
In the fast AS configuration scheme, Stratix III devices are configured using a serial
configuration device. These configuration devices are low-cost devices with
non-volatile memory that feature a simple four-pin interface and a small form factor.
These features make serial configuration devices an ideal low-cost configuration
solution.
f
For more information about serial configuration devices, refer to the Serial
Configuration Devices Data Sheet in the Configuration Handbook.
Serial configuration devices provide a serial interface to access configuration data.
During device configuration, Stratix III devices read configuration data through the
serial interface, decompress data if necessary, and configure their SRAM cells. This
scheme is referred to as the AS configuration scheme, because the Stratix III device
controls the configuration interface. This scheme contrasts with the PS configuration
scheme, where the configuration device controls the interface.
1
The Stratix III decompression and design security features are fully available when
configuring your Stratix III device using fast AS mode.
Table 11–7 lists the MSEL pin settings for the AS configuration scheme.
Table 11–7. Stratix III MSEL Pin Settings for AS Configuration Schemes (Note 1)
Configuration Scheme
MSEL2
MSEL1
MSEL0
Fast AS (40 MHz)
0
1
1
Remote system upgrade fast AS (40 MHz)
0
1
1
Note to Table 11–7:
(1) Use EPCS16, EPCS64, or EPCS128 devices.
Serial configuration devices have a four-pin interface: serial clock input (DCLK), serial
data output (DATA), AS data input (ASDI), and an active-low chip select (nCS). This
four-pin interface connects to Stratix III device pins, as shown in Figure 11–8.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–18
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
Figure 11–8. Single Device Fast AS Configuration
VCCPGM (1) VCCPGM (1) VCCPGM (1)
10 kΩ
10 kΩ
10 kΩ
Serial Configuration
Device
Stratix III FPGA
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
VCCPGM
DATA
DATA0
DCLK
DCLK
MSEL2
nCS
nCSO
MSEL1
ASDO
MSEL0
ASDI
(2)
N.C.
GND
Notes to Figure 11–8:
(1) Connect the pull-up resistors to VCCPGM at 3.3-V supply.
(2) Stratix III devices use the ASDO-to-ASDI path to control the configuration device.
Upon power-up, the Stratix III devices go through a POR. The POR delay is
dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is
approximately 100 ms. If PORSEL is driven high, the POR time is approximately
12 ms. During POR, the device will reset, hold nSTATUS and CONF_DONE low, and
tri-state all user I/O pins. After the device successfully exits POR, all user I/O pins
continue to be tri-stated. If nIO_pullup is driven low during power-up and
configuration, the user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If nIO_pullup is
driven high, the weak pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and initialization.
While nCONFIG or nSTATUS are low, the device is in reset. After POR, the Stratix III
device releases nSTATUS, which is pulled high by an external 10-kΩ pull-up resistor
and enters configuration mode.
1
To begin configuration, power the VCC, VCCIO, VCCPGM, and VCCPD voltages (for the banks
where the configuration and JTAG pins reside) to the appropriate voltage levels.
The serial clock (DCLK) generated by the Stratix III device controls the entire
configuration cycle and provides the timing for the serial interface. Stratix III devices
use an internal oscillator to generate DCLK. Using the MSEL[] pins, you can select to
use a 40 MHz oscillator.
In fast AS configuration schemes, Stratix III devices drive out control signals on the
falling edge of DCLK. The serial configuration device responds to the instructions by
driving out configuration data on the falling edge of DCLK. Then the data is latched
into the Stratix III device on the following falling edge of DCLK.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
11–19
In configuration mode, Stratix III devices enable the serial configuration device by
driving the nCSO output pin low, which connects to the chip select (nCS) pin of the
configuration device. The Stratix III device uses the serial clock (DCLK) and serial data
output (ASDO) pins to send operation commands, read address signals, or both to the
serial configuration device. The configuration device provides data on its serial data
output (DATA) pin, which connects to the DATA0 input of the Stratix III devices.
After all configuration bits are received by the Stratix III device, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-kΩ resistor.
Initialization begins only after the CONF_DONE signal reaches a logic high level. All AS
configuration pins (DATA0, DCLK, nCSO, and ASDO) have weak internal pull-up
resistors that are always active. After configuration, these pins are set as input
tri-stated and are driven high by the weak internal pull-up resistors. The CONF_DONE
pin must have an external 10-kΩ pull-up resistor for the device to initialize.
In Stratix III devices, the initialization clock source is either the 10 MHz (typical)
internal oscillator (separate from the active serial internal oscillator) or the optional
CLKUSR pin. By default, the internal oscillator is the clock source for initialization. If
you use the internal oscillator, the Stratix III device has enough clock cycles for proper
initialization. You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software on the
General tab of the Device and Pin Options dialog box. When you enable the user
supplied start-up clock option, the CLKUSR pin is the initialization clock source.
Supplying a clock on CLKUSR does not affect the configuration process. When all
configuration data has been accepted and CONF_DONE goes high, CLKUSR is enabled
after 600 ns. After this time period elapses, Stratix III devices require 4,436 clock cycles
to initialize properly and enter user mode. Stratix III devices support a CLKUSR fMAX of
100 MHz.
An optional INIT_DONE pin is available, which signals the end of initialization and
the start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software on the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it will be high due to an
external 10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. When the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin goes low.
When initialization is complete, the INIT_DONE pin is released and pulled high. This
low-to-high transition signals that the device has entered user mode. When
initialization is complete, the device enters user mode. In user mode, the user I/O
pins no longer have weak pull-up resistors and function as assigned in your design.
If an error occurs during configuration, Stratix III devices assert the nSTATUS signal
low, indicating a data frame error, and the CONF_DONE signal stays low. If the
Auto-restart configuration after error option (available in the Quartus II software on
the General tab of the Device and Pin Options dialog box) is turned on, the Stratix III
device resets the configuration device by pulsing nCSO, releases nSTATUS after a reset
time-out period (maximum of 100 μs), and retries configuration. If this option is
turned off, the system must monitor nSTATUS for errors and then pulse nCONFIG low
for at least 2 μs to restart configuration.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–20
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the tSTATUS specification.
When the Stratix III device is in user mode, you can initiate reconfiguration by pulling
the nCONFIG pin low. The nCONFIG pin should be low for at least 2 μs. When
nCONFIG is pulled low, the device also pulls nSTATUS and CONF_DONE low and all
I/O pins are tri-stated. When nCONFIG returns to a logic high level and nSTATUS is
released by the Stratix III device, reconfiguration begins.
You can configure multiple Stratix III devices using a single serial configuration
device. You can cascade multiple Stratix III devices using the chip-enable (nCE) and
chip-enable-out (nCEO) pins. The first device in the chain must have its nCE pin
connected to ground. You must connect its nCEO pin to the nCE pin of the next device
in the chain. When the first device captures all of its configuration data from the
bitstream, it drives the nCEO pin low, enabling the next device in the chain. You must
leave the nCEO pin of the last device unconnected. The nCONFIG, nSTATUS,
CONF_DONE, DCLK, and DATA0 pins of each device in the chain are connected (refer to
Figure 11–9).
This first Stratix III device in the chain is the configuration master and controls
configuration of the entire chain. You must connect its MSEL pins to select the AS
configuration scheme. The remaining Stratix III devices are configuration slaves. You
must connect their MSEL pins to select the PS configuration scheme. Any other Altera
device that supports PS configuration can also be part of the chain as a configuration
slave. Figure 11–9 shows the pin connections for this setup.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
11–21
Figure 11–9. Multi-Device Fast AS Configuration
VCCPGM (1) VCCPGM (1) VCCPGM (1)
10 kΩ
10 kΩ
10 kΩ
Serial Configuration
Device
Stratix III FPGA Master
Stratix III FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
VCCPGM
DATA
DATA0
DCLK
DCLK
MSEL2
nCS
nCSO
MSEL1
ASDI
ASDO
MSEL0
VCCPGM
DATA0
DCLK
GND
N.C.
MSEL2
MSEL1
MSEL0
GND
Buffers (2)
Notes to Figure 11–9:
(1) Connect the pull-up resistors to VCCPGM at 3.3-V supply.
(2) Connect the repeater buffers between the Stratix III master and slave device(s) for DATA[0] and DCLK. This prevents any potential signal
integrity and clock skew problems.
As shown in Figure 11–9, the nSTATUS and CONF_DONE pins on all target devices are
connected with external pull-up resistors. These pins are open-drain bi-directional
pins on the devices. When the first device asserts nCEO (after receiving all of its
configuration data), it releases its CONF_DONE pin. The subsequent devices in the
chain keep this shared CONF_DONE line low until they have received their
configuration data. When all target devices in the chain have received their
configuration data and released CONF_DONE, the pull-up resistor drives a high level
on this line and all devices simultaneously enter initialization mode.
If an error occurs at any point during configuration, the nSTATUS line is driven low
by the failing device. If you enable the Auto-restart configuration after error option,
reconfiguration of the entire chain begins after a reset time-out period (maximum of
100 µs). If the Auto-restart configuration after error option is turned off, the external
system must monitor nSTATUS for errors and then pulse nCONFIG low to restart
configuration. The external system can pulse nCONFIG if it is under system control
rather than tied to VCCPGM.
© March 2011
1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the tSTATUS specification.
1
While you can cascade Stratix III devices, you cannot cascade or chain together serial
configuration devices.
Altera Corporation
Stratix III Device Handbook, Volume 1
11–22
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
If the configuration bitstream size exceeds the capacity of a serial configuration
device, you must select a larger configuration device, enable the compression feature,
or both. When configuring multiple devices, the size of the bitstream is the sum of the
individual devices’ configuration bitstreams.
A system may have multiple devices that contain the same configuration data. In
active serial chains, you can implement this by storing one copy of the SOF in the
serial configuration device. The same copy of the SOF configures the master Stratix III
device and all remaining slave devices concurrently. All Stratix III devices must be the
same density and package. The master device is set up in active serial mode and the
slave devices are set up in passive serial mode.
To configure four identical Stratix III devices with the same SOF, you could set up the
chain similar to the example shown in Figure 11–10. The first device is the master
device, and its MSEL pins should be set to select AS configuration. The other three
slave devices are set up for concurrent configuration, and their MSEL pins should be
set to select PS configuration. The nCE input pins from the master and slave are
connected to GND, and the DATA and DCLK pins connect in parallel to all four devices.
During the configuration cycle, the master device reads its configuration data from
the serial configuration device and transmits the second copy of the configuration
data to all three slave devices, configuring all of them simultaneously.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
11–23
Figure 11–10. Multi-Device Fast AS Configuration When the Devices Receive the Same Data Using a Single SOF
Stratix III
FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C.
VCCPGM (1) VCCPGM (1) VCCPGM (1)
DATA0
10 kΩ
10 kΩ
MSEL2
DCLK
10 kΩ
VCCPGM
MSEL1
MSEL0
GND
Stratix III
FPGA Master
Serial Configuration
Device
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
Stratix III
FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
N.C.
nCEO
N.C.
GND
GND
DATA
DATA0
DCLK
DCLK
nCS
nCSO
ASDI
ASDO
VCCPGM
MSEL2
DATA0
MSEL2
DCLK
MSEL1
VCCPGM
MSEL1
MSEL0
MSEL0
GND
GND
Stratix III
FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
Buffers (2)
nCEO
DATA0
MSEL2
DCLK
N.C.
VCCPGM
MSEL1
MSEL0
GND
Notes to Figure 11–10:
(1) Connect the pull-up resistors to VCCPGM at 3.3-V supply.
(2) Connect the repeater buffers between the Stratix III master and slave device(s) for DATA[0] and DCLK. This prevents any potential signal
integrity and clock skew problems.
Estimating Active Serial Configuration Time
Active serial configuration time is dominated by the time it takes to transfer data from
the serial configuration device to the Stratix III device. This serial interface is clocked
by the Stratix III DCLK output (generated from an internal oscillator). Because the
Stratix III device only supports fast AS configuration, the DCLK frequency needs to be
set to 40 MHz (25 ns). The minimum configuration time estimate for an EP3SL50
device (15 MBits of uncompressed data) is shown in Equation 11–1 and Example 11–1.
Equation 11–1.
RBF Size × (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum configuration
time
Example 11–1.
15 Mbits × (25 ns / 1 bit) = 375 ms
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–24
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
Enabling compression reduces the amount of configuration data that is transmitted to
the Stratix III device, which also reduces configuration time. On average, compression
reduces configuration time, depending on the design.
Figure 11–11 shows the timing waveform for AS configuration.
Figure 11–11. Fast AS Configuration Timing
tPOR
nCONFIG
nSTATUS
CONF_DONE
nCSO
tCL
DCLK
tCH
tDH
Read Address
ASDO
tDSU
DATA0
bit N
bit N - 1
bit 1
bit 0
tCD2UM
INIT_DONE
User I/O
User Mode
Table 11–8 defines the timing parameters for Stratix III devices for fast AS
configuration.
Table 11–8. Fast AS Timing Parameters for Stratix III Devices
Symbol
Parameter
Min
Typ
Max Units
fCLK
DCLK frequency from Stratix III
15
25
40
MHz
tCF 2ST1
nCONFIG high to nSTATUS high
—
—
100
μs
tDSU
Data setup time before falling edge on DCLK
7
—
—
ns
tDH
Data hold time after falling edge on DCLK
0
—
—
ns
tCH
DCLK high time
10
—
—
ns
tCL
DCLK low time
10
—
—
ns
tCD2UM
CONF_DONE high to user mode
20
—
100
μs
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
11–25
Programming Serial Configuration Devices
Serial configuration devices are non-volatile, flash-memory-based devices. You can
program these devices in-system using the USB-Blaster™ or ByteBlaster™ II
download cable. Alternatively, you can program them using the Altera programming
unit (APU), supported third-party programmers, or a microprocessor with the
SRunner software driver.
You can perform in-system programming of serial configuration devices by using the
conventional AS programming interface or JTAG interface solution.
Because serial configuration devices do not support the JTAG interface, the
conventional method to program them is by using the AS programming interface. The
configuration data used to program serial configuration devices is downloaded by
using the programming hardware.
During in-system programming, the download cable disables device access to the AS
interface by driving the nCE pin high. Stratix III devices are also held in reset by a low
level on nCONFIG. After programming is complete, the download cable releases nCE
and nCONFIG, allowing the pull-down and pull-up resistors to drive GND and
VCCPGM, respectively. Figure 11–12 shows the download cable connections to the serial
configuration device.
Altera has developed the Serial FlashLoader (SFL), which is an in-system
programming solution for serial configuration devices using the JTAG interface. This
solution requires the Stratix III device to be a bridge between the JTAG interface and
the serial configuration device.
© March 2011
f
For more information about the SFL, refer to AN 370: Using the Serial FlashLoader with
the Quartus II Software.
f
For more information about the USB-Blaster download cable, refer to the USB-Blaster
Download Cable User Guide. For more information about the ByteBlaster II cable, refer
to the ByteBlaster II Download Cable User Guide.
Altera Corporation
Stratix III Device Handbook, Volume 1
11–26
Chapter 11: Configuring Stratix III Devices
Fast Active Serial Configuration (Serial Configuration Devices)
Figure 11–12. In-System Programming of Serial Configuration Devices
VCCPGM (1) VCCPGM (1) VCCPGM (1)
10 kΩ
10 kΩ
10 kΩ
Stratix III FPGA
CONF_DONE
nSTATUS
Serial
Configuration
Device
N.C.
nCEO
nCONFIG
nCE
10 kΩ
VCCPGM
DATA
DATA0
DCLK
DCLK
nCS
nCSO
MSEL1
ASDI
ASDO
MSEL0
MSEL2
GND
Pin 1
VCCPGM (2)
USB-Blaster, ByteBlaser II, or EthernetBlaster
(AS Mode)
10-Pin Male Header
Notes to Figure 11–12:
(1) Connect the pull-up resistors to VCCPGM at 3.3-V supply.
(2) Power up the USB-Blaster, ByteBlaster II, or EthernetBlaster cable’s VCC(TRGT) with VCCPGM.
You can program serial configuration devices with the Quartus II software using the
Altera programming hardware and the appropriate configuration device
programming adapter.
In production environments, you can program serial configuration devices using
multiple methods. You can use Altera programming hardware or other third-party
programming hardware to program blank serial configuration devices before they are
mounted onto PCBs. Alternatively, you can use an on-board microprocessor to
program the serial configuration device in-system using C-based software drivers
provided by Altera.
You can program a serial configuration device in-system by an external
microprocessor using SRunner. SRunner is a software driver developed for embedded
serial configuration device programming that can be easily customized to fit in
different embedded systems. SRunner is able to read a raw programming data (.rpd)
file and write to the serial configuration devices. The serial configuration device
programming time using SRunner is comparable to the programming time with the
Quartus II software.
f
For more information about SRunner, refer to AN 418: SRunner: An Embedded Solution
for EPCS Programming and the source code on the Altera website at www.altera.com.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
f
11–27
For more information about programming serial configuration devices and fast AS
Configuration Timing, refer to the Serial Configuration Devices (EPCS1, EPCS4,
EPCS16, EPCS64, and EPCS128) Data Sheet in the Configuration Handbook.
Passive Serial Configuration
You can program PS configuration of Stratix III devices using an intelligent host, such
as a MAX II device or microprocessor with flash memory, or a download cable. In the
PS scheme, an external host (a MAX II device, embedded processor, or host PC)
controls configuration. Configuration data is clocked into the target Stratix III device
by using the DATA0 pin at each rising edge of DCLK.
1
The Stratix III decompression and design security features are fully available when
configuring your Stratix III device using PS mode.
Table 11–9 lists the MSEL pin settings when using the PS configuration scheme.
Table 11–9. Stratix III MSEL Pin Settings for PS Configuration Scheme
Configuration Scheme
MSEL2
MSEL1
MSEL0
0
1
0
PS
PS Configuration Using a MAX II Device as an External Host
In this configuration scheme, you can use a MAX II device as an intelligent host that
controls the transfer of configuration data from a storage device, such as flash
memory, to the target Stratix III device. You can store configuration data in .rbf, .hex,
or .ttf format. Figure 11–13 shows the configuration interface connections between a
Stratix III device and a MAX II device for single device configuration.
Figure 11–13. Single Device PS Configuration Using an External Host
Memory
ADDR
DATA0
VCCPGM (1) VCCPGM (1)
10 k Ω
10 k Ω
Stratix III Device
CONF_DONE
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
nCEO
GND
DATA0
MSEL2
nCONFIG
MSEL1
DCLK
N.C.
VCCPGM
MSEL0
GND
Note to Figure 11–13:
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix III device. VCCPGM must be
high enough to meet the V IH specification of the I/O on the external host. It is recommended to power up all
configuration systems’ I/O with V CCPGM.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–28
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
Upon power-up, Stratix III devices go through a POR. The POR delay is dependent on
the PORSEL pin setting. When PORSEL is driven low, the POR time is approximately
100 ms. When PORSEL is driven high, the POR time is approximately 12 ms. During
POR, the device resets, holds nSTATUS low, and tri-states all user I/O pins. When the
device successfully exits POR, all user I/O pins continue to be tri-stated. If
nIO_pullup is driven low during power-up and configuration, the user I/O pins
and dual-purpose I/O pins will have weak pull-up resistors that are on (after POR)
before and during configuration. If nIO_pullup is driven high, the weak pull-up
resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and initialization.
While nCONFIG or nSTATUS are low, the device is in reset. To initiate configuration,
the MAX II device must generate a low-to-high transition on the nCONFIG pin.
1
VCC, VCCIO, VCCPGM, and VCCPD of the banks where the configuration and JTAG pins
reside must be fully powered to the appropriate voltage levels to begin the
configuration process.
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. When
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the MAX II device should
place the configuration data one bit at a time on the DATA0 pin. If you are using
configuration data in .rbf, .hex, or .ttf format, you must send the least significant bit
(LSB) of each data byte first. For example, if the RBF contains the byte sequence 02
1B EE 01 FA, the serial bitstream you must transmit to the device is 0100-0000
1101-1000 0111-0111 1000-0000 0101-1111.
The Stratix III device receives configuration data on the DATA0 pin and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Data is continuously clocked into the target device until CONF_DONE goes high. After
the device has received all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-kΩ pull-up resistor. A
low-to-high transition on CONF_DONE indicates configuration is complete and
initialization of the device can begin. The CONF_DONE pin must have an external
10-kΩ pull-up resistor for the device to initialize.
In Stratix III devices, the initialization clock source is either the internal oscillator
(typically 10 MHz) or the optional CLKUSR pin. By default, the internal oscillator is
the clock source for initialization. If you use the internal oscillator, the Stratix III
device has enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to the device
after configuration is complete does not affect device operation.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software on the
General tab of the Device and Pin Options dialog box. If you supply a clock on
CLKUSR, it will not affect the configuration process. After all configuration data has
been accepted and CONF_DONE goes high, CLKUSR will be enabled after the time
specified as tCD2CU. After this time period elapses, Stratix III devices require 4,436 clock
cycles to initialize properly and enter user mode. Stratix III devices support a CLKUSR
fMAX of 100 MHz.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
11–29
An optional INIT_DONE pin is available, which signals the end of initialization and
the start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software on the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it will be high due to an
external 10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. When the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin will go low.
When initialization is complete, the INIT_DONE pin will be released and pulled high.
The MAX II device must be able to detect this low-to-high transition, which signals
the device has entered user mode. When initialization is complete, the device enters
user mode. In user mode, the user I/O pins will no longer have weak pull-up resistors
and will function as assigned in your design.
To ensure DCLK and DATA0 are not left floating at the end of configuration, the
MAX II device must drive them either high or low, whichever is convenient on your
board. The DATA[0] pin is available as a user I/O pin after configuration. When you
choose the PS scheme as a default in the Quartus II software, this I/O pin is tri-stated
in user mode and should be driven by the MAX II device. To change this default
option in the Quartus II software, click the Dual-Purpose Pins tab of the Device and
Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified frequency to
ensure correct configuration. No maximum DCLK period exists, which means you can
pause configuration by halting DCLK for an indefinite amount of time.
If an error occurs during configuration, the device drives its nSTATUS pin low,
resetting itself internally. The low signal on the nSTATUS pin also alerts the MAX II
device that there is an error. If the Auto-restart configuration after error option
(available in the Quartus II software on the General tab of the Device and Pin
Options dialog box) is turned on, the Stratix III device releases nSTATUS after a reset
time-out period (maximum of 100 μs). After nSTATUS is released and pulled high by a
pull-up resistor, the MAX II device can attempt to reconfigure the target device
without needing to pulse nCONFIG low. If this option is turned off, the MAX II device
must generate a low-to-high transition (with a low pulse of at least 2 μs) on nCONFIG
to restart the configuration process.
1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the tSTATUS specification.
The MAX II device can also monitor the CONF_DONE and INIT_DONE pins to ensure
successful configuration. The CONF_DONE pin must be monitored by the MAX II
device to detect errors and determine when programming completes. If all
configuration data is sent, but CONF_DONE or INIT_DONE have not gone high, the
MAX II device must reconfigure the target device.
1
© March 2011
If you use the optional CLKUSR pin and nCONFIG is pulled low to restart
configuration during device initialization, you must ensure that CLKUSR continues
toggling during the time nSTATUS is low (maximum of 100 µs).
Altera Corporation
Stratix III Device Handbook, Volume 1
11–30
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
When the device is in user mode, you can initiate a reconfiguration by transitioning
the nCONFIG pin low-to-high. The nCONFIG pin must be low for at least 2 μs. When
nCONFIG is pulled low, the device also pulls nSTATUS and CONF_DONE low and all
I/O pins are tri-stated. When nCONFIG returns to a logic high level and nSTATUS is
released by the device, reconfiguration begins.
Figure 11–14 shows how to configure multiple devices using a MAX II device. This
circuit is similar to the PS configuration circuit for a single device, except Stratix III
devices are cascaded for multi-device configuration.
Figure 11–14. Multi-Device PS Configuration Using an External Host
Memory
ADDR
DATA0
VCCPGM (1) VCCPGM (1)
10 k Ω
10 k Ω
Stratix III Device 1
Stratix III Device 2
CONF_DONE
CONF_DONE
nSTATUS
nCE
External Host
(MAX II Device or
Microprocessor)
GND
DATA0
nSTATUS
nCE
nCEO
MSEL2
VCCPGM
nCEO
MSEL2
DATA0
nCONFIG
MSEL1
nCONFIG
MSEL1
DCLK
MSEL0
DCLK
MSEL0
N.C.
VCCPGM
GND
GND
Note to Figure 11–14:
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix III devices on the chain. VCCPGM must be high enough to
meet the V IH specification of the I/O on the external host. It is recommended to power up all configuration systems’ I/O with VCCPGM.
In multi-device PS configuration, the first device’s nCE pin is connected to GND while
its nCEO pin is connected to nCE of the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEO pin is left floating. After the first
device completes configuration in a multi-device configuration chain, its nCEO pin
drives low to activate the second device’s nCE pin, which prompts the second device
to begin configuration. The second device in the chain begins configuration within
one clock cycle. Therefore, the transfer of data destinations is transparent to the
MAX II device. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and
CONF_DONE) are connected to every device in the chain. Configuration signals can
require buffering to ensure signal integrity and prevent clock skew problems. Ensure
that the DCLK and DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user mode at the
same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device detects an
error, configuration stops for the entire chain and you must reconfigure the entire
chain. For example, if the first device flags an error on nSTATUS, it resets the chain by
pulling its nSTATUS pin low. This behavior is similar to a single device detecting an
error.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
11–31
If the Auto-restart configuration after error option is turned on, the devices release
their nSTATUS pins after a reset time-out period (maximum of 100 μs). After all
nSTATUS pins are released and pulled high, the MAX II device can attempt to
reconfigure the chain without needing to pulse nCONFIG low. If this option is turned
off, the MAX II device must generate a low-to-high transition (with a low pulse of at
least 2 μs) on nCONFIG to restart the configuration process.
1
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the tSTATUS specification.
In your system, you can have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied to GND,
while nCEO pins are left floating. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices will start
and complete configuration at the same time. Figure 11–15 shows multi-device PS
configuration when both Stratix III devices are receiving the same configuration data.
Figure 11–15. Multiple-Device PS Configuration When Both Devices Receive the Same Data
Memory
VCCPGM (1) VCCPGM (1)
ADDR
DATA0
10 k Ω
10 k Ω
Stratix III Device
Stratix III Device
CONF_DONE
CONF_DONE
nSTATUS
nCE
External Host
(MAX II Device or
Microprocessor)
nCEO
GND
DATA0
MSEL2
N.C. (2)
nSTATUS
nCE
VCCPGM GND
DATA0
nCEO
MSEL2
nCONFIG
MSEL1
nCONFIG
MSEL1
DCLK
MSEL0
DCLK
MSEL0
GND
N.C. (2)
VCCPGM
GND
Notes to Figure 11–15:
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix III devices on the chain. VCCPGM must be high enough to
meet the V IH specification of the I/O on the external host. It is recommended to power up all configuration systems’ I/O with VCCPGM.
(2) The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple devices.
You can use a single configuration chain to configure Stratix III devices with other
Altera devices. To ensure that all devices in the chain complete configuration at the
same time, or that an error flagged by one device initiates reconfiguration in all
devices, all of the device CONF_DONE and nSTATUS pins must be tied together.
f
© March 2011
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in the
Configuration Handbook.
Altera Corporation
Stratix III Device Handbook, Volume 1
11–32
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
PS Configuration Timing
Figure 11–16 shows the timing waveform for PS configuration when using a MAX II
device as an external host.
Figure 11–16. PS Configuration Timing Waveform (Note 1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
(5)
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
Bit 0 Bit 1 Bit 2 Bit 3
DATA
(4)
Bit n
tDSU
High-Z
User I/O
User Mode
INIT_DONE
tCD2UM
Notes to Figure 11–16:
(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay.
(3) Upon power-up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You should drive it high or low, whichever is more convenient. DATA[0] is available as a user
I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings.
(5) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
Table 11–10 defines the timing parameters for Stratix III devices for PS configuration.
Table 11–10. PS Timing Parameters for Stratix III Devices (Part 1 of 2)
Symbol
Parameter
Minimum
Maximum
Units
tCF 2CD
nCONFIG low to CONF_DONE low
—
800
ns
tCF 2ST0
nCONFIG low to nSTATUS low
—
800
ns
tCF G
nCONFIG low pulse width
2
—
μs
tSTATUS
nSTATUS low pulse width
10
100 (1)
μs
tCF 2ST1
nCONFIG high to nSTATUS high
—
100 (1)
μs
tCF 2CK
nCONFIG high to first rising edge on DCLK
100
—
μs
tST2C K
nSTATUS high to first rising edge of DCLK
2
—
μs
tDSU
Data setup time before rising edge on DCLK
5
—
ns
tDH
Data hold time after rising edge on DCLK
0
—
ns
tCH
DCLK high time
4
—
ns
tCL
DCLK low time
4
—
ns
tCLK
DCLK period
10
—
ns
fM AX
DCLK frequency
—
100
MHz
tR
Input rise time
—
40
ns
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
11–33
Table 11–10. PS Timing Parameters for Stratix III Devices (Part 2 of 2)
Symbol
Parameter
Minimum
Maximum
Units
t
Input fall time
—
40
ns
tCD2UM
CONF_DONE high to user mode (2)
20
100
μs
tCD2C U
CONF_DONE high to CLKUSR enabled
4 × maximum
DCLK period
—
—
tCD2UM C
CONF_DONE high to user mode with CLKUSR option on
tCD2CU +
(4,436 × CLKUSR period)
—
—
Notes to Table 11–10:
(1) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.
f
Device configuration options and how to create configuration files are discussed
further in the Device Configuration Options and Configuration File Formats chapters in
volume 2 of the Configuration Handbook.
PS Configuration Using a Microprocessor
In this PS configuration scheme, a microprocessor can control the transfer of
configuration data from a storage device, such as flash memory, to the target Stratix III
device.
f
1
You can do a PS configuration using MicroBlaster™ Passive Serial Software Driver.
For more information, refer to AN423: Configuring the MicroBlaster Passive Serial
Software Driver.
For all configuration and timing information, refer to “PS Configuration Using a
MAX II Device as an External Host” on page 11–27. This section is also applicable
when using a microprocessor as an external host.
PS Configuration Using a Download Cable
In this section, the generic term download cable includes the Altera USB-Blaster USB
port download cable, MasterBlaster™ serial/USB communications cable,
ByteBlaster II parallel port download cable, ByteBlasterMV™ parallel port download
cable, and the EthernetBlaster download cable.
In PS configuration with a download cable, an intelligent host (such as a PC) transfers
data from a storage device to the device by using the USB-Blaster, MasterBlaster,
ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–34
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
Upon power-up, the Stratix III devices go through a POR. The POR delay is
dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is
approximately 100 ms. If PORSEL is driven high, the POR time is approximately
12 ms. During POR, the device will reset, hold nSTATUS low, and tri-state all user I/O
pins. After the device successfully exits POR, all user I/O pins continue to be
tri-stated. If nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins will have weak pull-up resistors which are on
(after POR) before and during configuration. If nIO_pullup is driven high, the weak
pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration and initialization.
While nCONFIG or nSTATUS are low, the device is in reset. To initiate configuration in
this scheme, the download cable generates a low-to-high transition on the nCONFIG
pin.
1
To begin configuration, power the VCC, VCCIO, VCCPGM, and VCCPD voltages (for the banks
where the configuration and JTAG pins reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. The programming hardware or download cable then
places the configuration data one bit at a time on the device's DATA0 pin. The
configuration data is clocked into the target device until CONF_DONE goes high. The
CONF_DONE pin must have an external 10-kΩ pull-up resistor in order for the device
to initialize.
When using a download cable, setting the Auto-restart configuration after error
option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs. Additionally, the
Enable user-supplied start-up clock (CLKUSR) option has no affect on the device
initialization since this option is disabled in the SOF when programming the device
using the Quartus II programmer and download cable. Therefore, if you turn on the
CLKUSR option, you do not need to provide a clock on CLKUSR when you are
configuring the device with the Quartus II programmer and a download cable.
Figure 11–17 shows PS configuration for Stratix III devices using a USB-Blaster,
MasterBlaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
11–35
Figure 11–17. PS Configuration Using a Download Cable
VCCPGM (1) VCCPGM (1)
10 kΩ
(2)
VCCPGM (1) VCCPGM (1)
10 kΩ
VCCPGM (1)
10 kΩ
Stratix III Device
VCCPGM
MSEL2
10 kΩ
CONF_DONE
nSTATUS
MSEL1
10 kΩ
(2)
MSEL0
GND
nCE
GND
DCLK
DATA0
nCONFIG
nCEO
N.C.
Download Cable
10-Pin Male Header
(PS Mode)
Pin 1
VCCPGM
GND
VIO (3)
Shield
GND
Notes to Figure 11–17:
(1) You should connect the pull-up resistor to the same supply voltage (VCC PGM ) as the USB-Blaster, MasterBlaster (VIO pin), ByteBlaster II,
ByteBlasterMV, or EthernetBlaster cable.
(2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures
that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the
pull-up resistors on DATA0 and DCLK.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device's V C CP GM. Refer to the MasterBlaster
Serial/USB Communications Cable Data Sheet for this value. In the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable, this pin
is a no connect.
You can use a download cable to configure multiple Stratix III devices by connecting
each device's nCEO pin to the subsequent device's nCE pin. The first device's nCE pin
is connected to GND while its nCEO pin is connected to the nCE of the next device in
the chain. The last device's nCE input comes from the previous device, while its nCEO
pin is left floating. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0,
and CONF_DONE) are connected to every device in the chain. Because all CONF_DONE
pins are tied together, all devices in the chain initialize and enter user mode at the
same time.
In addition, because the nSTATUS pins are tied together, the entire chain halts
configuration if any device detects an error. The Auto-restart configuration after
error option does not affect the configuration cycle because you must manually restart
configuration in the Quartus II software when an error occurs.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–36
Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
Figure 11–18 shows how to configure multiple Stratix III devices with a download
cable.
Figure 11–18. Multi-Device PS Configuration using a Download Cable
VCCPGM (1)
10 kΩ
VCCPGM (1) VCCPGM
10 kΩ
VCCPGM (1)
GND
GND
VCCPGM
(2)
Pin 1
VCCPGM
GND
VIO (3)
nCEO
nCE
10 kΩ
VCCPGM (1)
10 kΩ
CONF_DONE
nSTATUS
DCLK
MSEL2
MSEL1
MSEL0
(2)
10 kΩ
Stratix III Device 1
Download Cable
10-Pin Male Header
(PS Mode)
VCCPGM (1)
DATA0
nCONFIG
GND
Stratix III Device 2
MSEL2
MSEL1
MSEL0
CONF_DONE
nSTATUS
DCLK
GND
nCEO
N.C.
nCE
DATA0
nCONFIG
Notes to Figure 11–18:
(1) Connect the pull-up resistor to the same supply voltage (VC CPGM ) as the USB-Blaster, MasterBlaster (VIO pin), ByteBlaster II, ByteBlasterMV, or
EthernetBlaster cable.
(2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This is to
ensure that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need
the pull-up resistors on DATA0 and DCLK.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device's VC CP GM. Refer to the MasterBlaster
Serial/USB Communications Cable Data Sheet for this value. In the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable, this pin
is a no connect.
f
For more information about how to use the USB-Blaster, MasterBlaster, ByteBlaster II,
ByteBlasterMV, or EthernetBlaster cable, refer to the following user guides:
■
USB-Blaster USB Port Download Cable User Guide
■
MasterBlaster Serial/USB Communications Cable User Guide
■
ByteBlaster II Parallel Port Download Cable User Guide
■
ByteBlasterMV Parallel Port Download Cable User Guide
■
EthernetBlaster Download Cable User Guide
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
JTAG Configuration
11–37
JTAG Configuration
The JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently test
components on PCBs with tight lead spacing. The BST architecture can test pin
connections without using physical test probes and capture functional data while a
device is operating normally. You can also use the JTAG circuitry to shift
configuration data into the device. The Quartus II software automatically generates
SOFs that can be used for JTAG configuration with a download cable in the Quartus II
software programmer.
f
For more information about JTAG boundary-scan testing and commands available
using Stratix III devices, refer to the following documents:
■
IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Device chapter of the
Stratix III Device Handbook
■
AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
Stratix III devices are designed such that JTAG instructions have precedence over any
device configuration modes. Therefore, JTAG configuration can take place without
waiting for other configuration modes to complete. For example, if you attempt JTAG
configuration of Stratix III devices during PS configuration, PS configuration is
terminated and JTAG configuration begins.
1
You cannot use the Stratix III decompression or design security features if you are
configuring your Stratix III device when using JTAG-based configuration.
1
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK,
and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor,
while the TDI, TMS, and TRST pins have weak internal pull-up resistors (typically
25 kΩ). JTAG output pin TDO and all JTAG input pins are powered by the
2.5 V/3.0 V/3.3 V VCCPD power supply of I/O bank 1A. All the JTAG pins support
only LVTTL I/O standard.
All user I/O pins are tri-stated during JTAG configuration. Table 11–11 explains each
JTAG pin's function.
f
© March 2011
The TDO output is powered by the VCCPD power supply of I/O bank 1A. For
recommendations on how to connect a JTAG chain with multiple voltages across the
devices in the chain, refer to the IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III
Devices chapter of the Stratix III Device Handbook.
Altera Corporation
Stratix III Device Handbook, Volume 1
11–38
Chapter 11: Configuring Stratix III Devices
JTAG Configuration
Table 11–11. Dedicated JTAG Pins
Pin Name
Pin Type
Description
Test data input
Serial input pin for instructions as well as test and programming data. Data is shifted in
the rising edge of TCK. If the JTAG interface is not required on the board, you can
disable the JTAG circuitry by connecting this pin to VCC PD.
Test data output
Serial data output pin for instructions as well as test and programming data. Data is
shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted
out of the device. If the JTAG interface is not required on the board, you can disable the
JTAG circuitry by leaving this pin unconnected.
TMS
Test mode select
Input pin that provides the control signal to determine the transitions of the TAP
controller state machine. Transitions within the state machine occur on the rising edge
of TCK. Therefore, you must set up TMS before the rising edge of TCK. TMS is
evaluated on the rising edge of TCK. If the JTAG interface is not required on the board,
you can disable the JTAG circuitry by connecting this pin to VCCPD.
TCK
Test clock input
The clock input to the BST circuitry. Some operations occur at the rising edge while
others occur at the falling edge. If the JTAG interface is not required on the board, you
can disable the JTAG circuitry by connecting this pin to GND.
TRST
Test reset input
(optional)
Active-low input to asynchronously reset the boundary-scan circuit. The TRST pin is
optional according to IEEE Std. 1149.1. If the JTAG interface is not required on the
board, you can disable the JTAG circuitry by connecting this pin to GND.
TDI
TDO
During JTAG configuration, you can download data to the device on the PCB through
the USB-Blaster, MasterBlaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster
download cables. Configuring devices through a cable is similar to programming
devices in-system, except you should connect the TRST pin to VCCPD. This ensures that
the TAP controller is not reset.
1
The JRunner™ software driver is developed to configure Altera FPGA devices in
JTAG mode through the ByteBlaster II or ByteBlasterMV download cables for
embedded configurations. For more information, refer to AN 414: The JRunner
Software Driver.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
JTAG Configuration
11–39
Figure 11–19 shows JTAG configuration of a single Stratix III device.
Figure 11–19. JTAG Configuration of a Single Device Using a Download Cable
VCCPD (1)
(5)
VCCPGM (1)
VCCPGM (1)
VCCPD (1)
10 kΩ
Stratix III Device
10 kΩ
nCE (4)
GND N.C.
(2)
(2)
(2)
nCE0
nSTATUS
CONF_DONE
nCONFIG
MSEL[2..0]
DCLK
(5)
TCK
TDO
TMS
TDI
Download Cable
10-Pin Male Header
(JTAG Mode)
(Top View)
VCCPD
TRST
Pin 1
VCCPD
GND
VIO (3)
1 kΩ
GND
GND
Notes to Figure 11–19:
(1) You should connect the pull-up resistor to the same supply voltage as the USB-Blaster, MasterBlaster (VIO pin), ByteBlaster II, ByteBlasterMV,
or EthernetBlaster cables. The voltage supply can be connected to the VCCPD of the device.
(2) You should connect the nCONFIG and MSEL[2..0] pins to support a non-JTAG configuration scheme. If you only use the JTAG configuration,
connect nCONFIG to VCC PGM , and MSEL[2..0] to ground. Pull DCLK either high or low, whichever is convenient on your board.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device's VC CPD . Refer to the MasterBlaster
Serial/USB Communications Cable Data Sheet for this value. In the USB-Blaster, ByteBlaster II, ByteBlasterMV, and EthernetBlaster, this pin is a
no connect.
(4) You must connect nCE to GND or drive it low for successful JTAG configuration.
(5) Pull-up resistor values can vary from 1 kΩ to 10 kΩ.
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon completion. At
the end of configuration, the software checks the state of CONF_DONE through the
JTAG port. When Quartus II generates a JAM file (.jam) for a multi-device chain, it
contains instructions so that all the devices in the chain will be initialized at the same
time. If CONF_DONE is not high, the Quartus II software indicates that configuration
has failed. If CONF_DONE is high, the software indicates that configuration was
successful. After the configuration bitstream is transmitted serially through the JTAG
TDI port, the TCK port is clocked an additional 1,094 cycles to perform device
initialization.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–40
Chapter 11: Configuring Stratix III Devices
JTAG Configuration
Stratix III devices have dedicated JTAG pins that always function as JTAG pins. Not
only can you perform JTAG testing on Stratix III devices before and after, but also
during configuration. While other device families do not support JTAG testing during
configuration, Stratix III devices support the bypass, id code, and sample instructions
during configuration without interrupting configuration. All other JTAG instructions
may only be issued by first interrupting configuration and reprogramming I/O pins
using the CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured by using the JTAG
port and when issued, interrupts configuration. This instruction allows you to
perform board-level testing prior to configuring the Stratix III device or waiting for a
configuration device to complete configuration. When configuration has been
interrupted and JTAG testing is complete, you must reconfigure the part by using
JTAG (PULSE_CONFIG instruction) or by pulsing nCONFIG low.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on
Stratix III devices do not affect JTAG boundary-scan or programming operations.
Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration of Stratix III devices, consider the
dedicated configuration pins. Table 11–12 lists how these pins should be connected
during JTAG configuration.
Table 11–12. Dedicated Configuration Pin Connections During JTAG Configuration
Signal
Description
nCE
On all Stratix III devices in the chain, nCE should be driven low by connecting it to ground, pulling it low by
using a resistor, or driving it by some control circuitry. For devices that are also in multi-device FPP, AS, or
PS configuration chains, the nCE pins should be connected to GND during JTAG configuration or JTAG
configured in the same order as the configuration chain.
nCEO
On all Stratix III devices in the chain, you can leave nCEO floating or connected to the nCE of the next
device.
MSEL
These pins must not be left floating. These pins support whichever non-JTAG configuration is used in
production. If you only use JTAG configuration, tie these pins to ground.
nCONFIG
Driven high by connecting to VC CPGM , pull up by using a resistor, or driven high by some control circuitry.
nSTATUS
Pull to VCC PGM by using a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain, each
nSTATUS pin should be pulled up to VCC PGM individually.
Pull to VCC PGM by using a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain, each
CONF_DONE CONF_DONE pin should be pulled up to VCC PGM individually. CONF_DONE going high at the end of JTAG
configuration indicates successful configuration.
DCLK
Should not be left floating. Drive low or high, whichever is more convenient on your board.
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an
on-board buffer.
JTAG-chain device programming is ideal when the system contains multiple devices,
or when testing your system using JTAG BST circuitry. Figure 11–20 shows
multi-device JTAG configuration.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
JTAG Configuration
11–41
Figure 11–20. JTAG Configuration of Multiple Devices Using a Download Cable
Stratix III Device
Download Cable
10-Pin Male Header
(JTAG Mode)
VCCPGM (1)
(2)
Pin 1
(5)
VCCPD
VCCPGM (1)
10 kΩ
VCCPD (1)
nSTATUS
nCONFIG
(2)
(5)
(2)
VCCPD
(2)
VIO
VCCPGM (1)
10 kΩ
10 kΩ
nSTATUS
nCONFIG
VCCPGM (1)
10 kΩ
10 kΩ
(2)
nSTATUS
nCONFIG
CONF_DONE
CONF_DONE
DCLK
(2)
DCLK
(2)
DCLK
MSEL[2..0]
(2)
MSEL[2..0]
(2)
MSEL[2..0]
nCE (4)
TRST
TDI
TMS
(3)
VCCPGM (1)
VCCPGM (1)
10 kΩ
CONF_DONE
VCCPD (1)
Stratix II or Stratix II GX
Stratix
III Device
Device
Stratix III Device
VCCPD
TDO
TCK
nCE (4)
TRST
TDI
TMS
VCCPD
TDO
TCK
nCE (4)
TRST
TDI
TMS
TDO
TCK
1 kΩ
Notes to Figure 11–20:
(1) Connect the pull-up resistor to the same supply voltage as the USB-Blaster, MasterBlaster (VIO pin), ByteBlaster II, ByteBlasterMV, or
EthernetBlaster cables. The voltage supply can be connected to the VCCPD of the device.
(2) Connect the nCONFIG, MSEL[2..0] pins to support a non-JTAG configuration scheme. If you only use JTAG configuration, connect nCONFIG
to VC CPGM , and MSEL[2..0] to ground. Pull DCLK either high or low, whichever is convenient on your board.
(3) Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. V IO should match the device's VC CP D . Refer to the MasterBlaster
Serial/USB Communications Cable Data Sheet for this value. In the USB-Blaster, ByteBlaster II, ByteBlasterMV, and EthernetBlaster, this pin is a
no connect.
(4) You must connect nCE to GND or drive it low for successful JTAG configuration.
(5) Pull-up resistor values can vary from 1 kΩ to 10 kΩ.
You must connect the nCE pin to GND or drive it low during JTAG configuration. In
multi-device FPP, AS, and PS configuration chains, the first device's nCE pin is
connected to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device's nCE input comes from the previous device, while its nCEO pin
is left floating. In addition, the CONF_DONE and nSTATUS signals are all shared in
multi-device FPP, AS, or PS configuration chains so the devices can enter user mode at
the same time after configuration is complete. When the CONF_DONE and nSTATUS
signals are shared among all the devices, you must configure every device when JTAG
configuration is performed.
If you only use JTAG configuration, Altera recommends that you connect the circuitry
as shown in Figure 11–20, where each of the CONF_DONE and nSTATUS signals are
isolated, so that each device can enter user mode individually.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the second device's nCE pin, which prompts the
second device to begin configuration. Therefore, if these devices are also in a JTAG
chain, make sure the nCE pins are connected to GND during JTAG configuration or
that the devices are JTAG configured in the same order as the configuration chain. As
long as the devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO of the previous device will drive the nCE of the next
device low when it has successfully been JTAG configured.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–42
Chapter 11: Configuring Stratix III Devices
JTAG Configuration
You can place other Altera devices that have JTAG support in the same JTAG chain for
device programming and configuration.
1
f
JTAG configuration support has been enhanced and allows more than 17 Stratix III
devices to be cascaded in a JTAG chain.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera Device Chains chapter in the
Configuration Handbook.
You can configure Stratix III devices using multiple configuration schemes on the
same board. Combining JTAG configuration with passive serial (PS) or active serial
(AS) configuration on your board is useful in the prototyping environment because it
allows multiple methods to configure your FPGA.
f
For more information about combining JTAG configuration with other configuration
schemes, refer to the Combining Different Configuration Schemes chapter in the
Configuration Handbook.
Figure 11–21 shows JTAG configuration of a Stratix III device with a microprocessor.
Figure 11–21. JTAG Configuration of a Single Device Using a Microprocessor
VCCPGM (1)
VCCPGM (1)
Memory
ADDR
Stratix III Device
10 kΩ
DATA
VCCPD
Microprocessor
10 kΩ
TRST
TDI (4)
TCK (4)
TMS (4)
TDO (4)
nSTATUS
CONF_DONE
DCLK
nCONFIG
MSEL[2..0]
nCEO
(3) nCE
(2)
(2)
(2)
N.C.
GND
Notes to Figure 11–21:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all devices in the chain. VCCPGM
should be high enough to meet the VIH specification of the I/O on the device.
(2) Connect the nCONFIG and MSEL[2..0] pins to support a non-JTAG configuration scheme. If you use only the
JTAG configuration, connect nCONFIG to VCC PGM , and MSEL[2..0] to ground. Pull DCLK either high or low,
whichever is convenient on your board.
(3) You must connect nCE to GND or drive it low for successful JTAG configuration.
(4) Microprocessor should use the same I/O standard as VC CPD to drive the JTAG pins.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
11–43
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or configuration
of programmable devices and testing of electronic systems, using the IEEE 1149.1
JTAG interface. Jam STAPL is a freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP
state machine.
f
For more information about JTAG and Jam STAPL in embedded environments, refer
to AN 425: Using Command-Line Jam STAPL Solution for Device Programming. To
download the jam player, visit the Altera web site at www.altera.com.
Device Configuration Pins
The following tables describe the connections and functionality of all the
configuration-related pins on the Stratix III devices. Table 11–13 summarizes the
Stratix III configuration pins and their power supply.
Table 11–13. Stratix III Configuration Pin Summary (Note 1) (Part 1 of 2)
Description
Input/Output
Dedicated
Powered By
Configuration Mode
TDI
Input
Yes
VCC PD (2)
JTAG
TMS
Input
Yes
VCC PD (2)
JTAG
TCK
Input
Yes
VCC PD (2)
JTAG
TRST
Input
Yes
VCC PD (2)
JTAG
TDO
Output
Yes
VCC PD (2)
JTAG
CRC_ERROR
Output
—
Pull-up
Optional, all modes
DATA0
Input
—
VC CPGM /VCC IO (3)
All modes except JTAG
DATA[7..1]
Input
—
VC CP GM/VCC IO (3)
FPP
INIT_DONE
Output
—
Pull-up
Optional, all modes
CLKUSR
Input
—
VC CP GM/VCC IO (3)
Optional
nSTATUS
bi-directional
Yes
Pull-up
All modes
Input
Yes
VC CP GM
All modes
bi-directional
Yes
Pull-up
All modes
nCONFIG
Input
Yes
VC CP GM
All modes
PORSEL
Input
Yes
VC CP GM
All modes
ASDO
Output
Yes
VC CP GM
AS
nCSO
Output
Yes
VC CP GM
AS
nCE
CONF_DONE
DCLK
—
nIO_PULLUP
nCEO
© March 2011
Altera Corporation
Input
Yes
VC CP GM
PS, FPP
Output
—
VC CP GM
AS
Input
Yes
VC CP GM
All modes
Output
Yes
VC CP GM
All modes
Stratix III Device Handbook, Volume 1
11–44
Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
Table 11–13. Stratix III Configuration Pin Summary (Note 1) (Part 2 of 2)
Description
Input/Output
Dedicated
Powered By
Configuration Mode
Input
Yes
VC CP GM
All modes
MSEL[2..0]
Notes to Table 11–13:
(1) The total number of pins is 30. The total number of dedicated pins is 19.
(2) The JTAG output pin TDO and all JTAG input pins are powered by the 2.5 V/3.0 V/3.3-V VCCPD power supply of I/O bank 1A.
(3) These dual purpose pins are powered by VCCPGM during configuration, then are powered by V CCIO while in user mode.This applies for all
configuration modes.
Table 11–14 describes the dedicated configuration pins, which are required to be
connected properly on your board for successful configuration. Some of these pins
may not be required for your configuration schemes.
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 1 of 5)
Pin Name
User Mode
Configuration
Scheme
Pin Type
Description
Dedicated power pin. Use this pin to power all dedicated
configuration inputs, dedicated configuration outputs,
dedicated configuration bi-direction pins, and some of
the dual functional pins that are used for configuration.
VCCPGM
N/A
All
Power
You must connect this pin to 1.8-V, 2.5-V, 3.0-V, or
3.3-V. VC CP GM must ramp-up from 0-V to 3.3-V within 100
ms. If VC CP GM is not ramped up within this specified time,
your Stratix III device will not configure successfully. If
your system does not allow for a VCCPGM ramp-up
time of 100 ms or less, you must hold nCONFIG low
until all power supplies are stable.
Dedicated power pin. Use this pin to power the I/O
pre-drivers, the JTAG input and output pins, and the
design security circuitry.
VCCPD
N/A
All
Power
You must connect this pin to 2.5-V, 3.0-V, or 3.3-V
depending on the I/O standards selected. For 3.3-V I/O
standards, VCCPD=3.3-V, for 3.0-V I/O standards, VCC PD
= 3.0 V, for 2.5-V or below I/O standards, VC CP D = 2.5 V.
VC CP D must ramp-up from 0-V to 2.5-V / 3.0-V/3.3-V
within 100 ms. If VCC PD is not ramped up within this
specified time, your Stratix III device will not configure
successfully. If your system does not allow for a VC CPD
ramp-up time of 100 ms or less, you must hold
nCONFIG low until all power supplies are stable.
PORSEL
N/A
Stratix III Device Handbook, Volume 1
All
Input
Dedicated input which selects either a POR time of 12
ms or 100 ms. A logic high (1.8 V, 2.5 V, 3.0 V, 3.3 V)
selects a POR time of approximately 12 ms and a logic
low selects a POR time of approximately 100 ms.
The PORSEL input buffer is powered by VCCPGM and
has an internal 5-kΩ pull-down resistor that is always
active. You should tie the PORSEL pin directly to
VCCPGM or GND.
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
11–45
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 2 of 5)
Pin Name
User Mode
nIO_PULLUP
N/A
Configuration
Scheme
All
Pin Type
Description
Input
Dedicated input that chooses whether the internal
pull-up resistor on the user I/O pins and dual-purpose
I/O pins (nCSO, nASDO, DATA[7..0], nWS, nRS,
RDYnBSY, nCS, CLKUSR, INIT_DONE) are on or off
before and during configuration. A logic high (1.8 V, 2.5
V, 3.0 V, 3.3 V) turns off the weak internal pull-up
resistors, while a logic low turns them on.
The nIO-PULLUP input buffer is powered by VCCPGM
and has an internal 5-kΩ pull-down resistor that is
always active. You can tie the nIO-PULLUP directly to
VCCPGM or use a 1-kΩ pull-up resistor or tie it directly
to GND.
3-bit configuration input that sets the Stratix III device
configuration scheme. Refer to Table 11–1 for the
appropriate connections.
MSEL[2..0]
N/A
All
Input
You must hard-wire these pins to VCCPGM or GND.
The MSEL[2..0] pins have internal 5-kΩ pull-down
resistors that are always active.
nCONFIG
N/A
All
Input
Configuration control input. Pulling this pin low during
user-mode will cause the device to lose its configuration
data, enter a reset state, and tri-state all I/O pins.
Returning this pin to a logic high level will initiate a
reconfiguration.
Configuration is possible only if this pin is high, except
in JTAG programming mode when nCONFIG is
ignored.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–46
Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 3 of 5)
Pin Name
User Mode
Configuration
Scheme
Pin Type
Description
The device drives nSTATUS low immediately after
power-up and releases it after the POR time.
During user mode and regular configuration, this pin is
pulled high by an external 10-kΩ resistor.
This pin, when driven low by Stratix III, indicates that
the device is being initialized and has encountered an
error during configuration.
Status output. If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input. If an external source drives the nSTATUS
pin low during configuration or initialization, the target
device enters an error state.
nSTATUS
N/A
All
Bi-directional Driving nSTATUS low after configuration and
open-drain initialization does not affect the configured device. If you
use a configuration device, driving nSTATUS low will
cause the configuration device to attempt to configure
the device, but since the device ignores transitions on
nSTATUS in user-mode, the device does not
reconfigure. To initiate a reconfiguration, nCONFIG
must be pulled low.
If you have enabled the Auto-restart configuration after
error option, the nSTATUS pin transitions from high to
low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS
pin with a minimum pulse width of 10 μs to a maximum
pulse width of 500 μs, as defined in the tSTATUS
specification.
If VCC PGM and VC CIO are not fully powered up, the following
could occur:
nSTATUS
(continued)
—
Stratix III Device Handbook, Volume 1
—
—
■
VCC PGM and VC CIO are powered high enough for the
nSTATUS buffer to function properly, and
nSTATUS is driven low. When VC CPGM and VC CIO are
ramped up, POR trips and nSTATUS is released after
POR expires.
■
VCC PGM and VC CIO are not powered high enough for the
nSTATUS buffer to function properly. In this
situation, nSTATUS might appear logic high,
triggering a configuration attempt that would fail
because POR did not yet trip. When VCC PD and VC CIO are
powered up, nSTATUS is pulled low because POR
did not yet trip. When POR trips after VCC PGM and VC CIO
are powered up, nSTATUS is released and pulled
high. At that point, reconfiguration is triggered and
the device is configured.
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
11–47
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 4 of 5)
Pin Name
User Mode
Configuration
Scheme
Pin Type
Description
Status output. The target device drives the CONF_DONE
pin low before and during configuration. After all
configuration data is received without error and the
initialization cycle starts, the target device releases
CONF_DONE.
CONF_DONE
N/A
All
Status input. After all data is received and CONF_DONE
Bi-directional
goes high, the target device initializes and enters user
open-drain
mode. The CONF_DONE pin must have an external
10-kΩ pull-up resistor in order for the device to
initialize.
Driving CONF_DONE low after configuration and
initialization does not affect the configured device. Do
not connect bus holds or ADC to CONF_DONE pin.
nCE
N/A
All
Input
Active-low chip enable. The nCE pin activates the device
with a low signal to allow configuration. The nCE pin
must be held low during configuration, initialization, and
user mode. In single device configuration, it should be
tied low. In multi-device configuration, nCE of the first
device is tied low while its nCEO pin is connected to
nCE of the next device in the chain.
The nCE pin must also be held low for successful JTAG
programming of the device.
nCEO
N/A
All
Output
Output that drives low when device configuration is
complete. In single device configuration, this pin is left
floating. In multi-device configuration, this pin feeds the
next device's nCE pin. The nCEO of the last device in
the chain is left floating.
The nCEO pin is powered by VCC PGM .
ASDO (1)
N/A
AS
Output
Control signal from the Stratix III device to the serial
configuration device in AS mode used to read out
configuration data.
In AS mode, ASDO has an internal pull-up resistor that
is always active.
nCSO (1)
N/A
AS
Output
Output control signal from the Stratix III device to the
serial configuration device in AS mode that enables the
configuration device.
In AS mode, nCSO has an internal pull-up resistor that
is always active.
© March 2011
Altera Corporation
Stratix III Device Handbook, Volume 1
11–48
Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 5 of 5)
Pin Name
User Mode
Configuration
Scheme
Pin Type
Description
DCLK has an internal pull-up resistor (typically 25 kΩ)
that is always active.
DCLK (1)
DATA0 (1)
N/A
N/A in AS
mode. I/O in
PS or FPP
mode
Synchronous
configuration
schemes (PS,
FPP, AS)
Input (PS,
FPP)
Output (AS)
In AS mode, DCLK is an output from the Stratix III
device that provides timing for the configuration
interface. After AS configuration, this pin is driven to an
inactive state. In schemes that use a configuration
device, DCLK will be driven low after configuration is
done. In schemes that use a control host, DCLK should
be driven either high or low, whichever is more
convenient. Toggling this pin after configuration does
not affect the configured device.
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on
the DATA0 pin.
PS, FPP, AS
Input
In AS mode, DATA0 has an internal pull-up resistor that
is always active.
After PS or FPP configuration, DATA0 is available as a
user I/O pin and the state of this pin depends on the
Dual-Purpose Pin settings.
Data inputs. Byte-wide configuration data is presented
to the target device on DATA[7..0].
DATA[7..1]
I/O
Parallel
configuration
schemes (FPP)
Inputs
In serial configuration schemes, they function as user
I/O pins during configuration, which means they are
tri-stated.
After configuration, DATA[7..1] are available as user
I/O pins and the state of these pin depends on the
Dual-Purpose Pin settings.
Note to Table 11–14:
(1) To tri-state AS configuration pins in AS configuration scheme, turn on Enable input tri-state on active configuration pins in user mode option
from the Device and Pin Options dialog box. This tri-states DCLK, nCSO, Data0, and ASDO pins. Dual-purpose Pins Setting for Data0 is
ignored. To set Data0 to a different setting, for example to use Data0 pin as a regular I/O in user mode, turn off Enable input tri-state on
active configuration pins in user mode option and set your desired setting from the Dual-purpose Pins Setting menu.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
11–49
Table 11–15 describes the optional configuration pins. If these optional configuration
pins are not enabled in the Quartus II software, they are available as general-purpose
user I/O pins. Therefore, during configuration, these pins function as user I/O pins
and are tri-stated with weak pull-up resistors.
Table 11–15. Optional Configuration Pins
Pin Name
User Mode
N/A if option is on. I/O
if option is off.
CLKUSR
INIT_DONE
DEV_OE
DEV_CLRn
© March 2011
N/A if option is on. I/O
if option is off.
N/A if option is on. I/O
if option is off.
N/A if option is on. I/O
if option is off.
Altera Corporation
Pin Type
Input
Description
Optional user-supplied clock input synchronizes the
initialization of one or more devices. Enable this pin by
turning on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software.
Output open-drain
Use the Status pin to indicate when the device has
initialized and is in user mode. When nCONFIG is low and
during the beginning of configuration, the INIT_DONE
pin is tri-stated and pulled high due to an external 10-kΩ
pull-up resistor. After the option bit to enable
INIT_DONE is programmed into the device (during the
first frame of configuration data), the INIT_DONE pin will
go low. When initialization is complete, the INIT_DONE
pin is released and pulled high and the device enters user
mode. Thus, the monitoring circuitry must be able to
detect a low-to-high transition. This pin is enabled by
turning on the Enable INIT_DONE output option in the
Quartus II software.
Input
Optional pin that allows you to override all tri-states on the
device. When this pin is driven low, all I/O pins are
tri-stated, when this pin is driven high, all I/O pins behave
as programmed. Enable this pin by turning on the Enable
device-wide output enable (DEV_OE) option in the
Quartus II software.
Input
Optional pin that allows you to override all clears on all
device registers. When this pin is driven low, all registers
are cleared. When this pin is driven high, all registers
behave as programmed. This pin is enabled by turning on
the Enable device-wide reset (DEV_CLRn) option in the
Quartus II software.
Stratix III Device Handbook, Volume 1
11–50
Chapter 11: Configuring Stratix III Devices
Device Configuration Pins
Table 11–16 describes the dedicated JTAG pins. JTAG pins must be kept stable before
and during configuration to prevent accidental loading of JTAG instructions. The TDI,
TMS, and TRST have weak internal pull-up resistors while TCK has a weak internal
pull-down resistor (typically 25 kΩ). If you plan to use the SignalTap ® embedded logic
array analyzer, you must connect the JTAG pins of the Stratix III device to a JTAG
header on your board.
Table 11–16. Dedicated JTAG Pins
Pin Name
TDI
User Mode
N/A
Pin Type
Input
Description
Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of TCK. The TDI pin is powered by the
2.5-V/3.0-V/3.3-V VC CP D supply.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by connecting this pin to VCCPD.
TDO
N/A
Output
Serial data output pin for instructions as well as test and programming data. Data is
shifted out on the falling edge of TCK. The pin is tri-stated if data is not being
shifted out of the device. The TDO pin is powered by VCCP D For recommendations on
connecting a JTAG chain with multiple voltages across the devices in the chain,
refer to the chapter IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Devices
chapter in volume 1 of the Stratix III Device Handbook.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by leaving this pin unconnected.
TMS
N/A
Input
Input pin that provides the control signal to determine the transitions of the TAP
controller state machine. Transitions within the state machine occur on the rising
edge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMS is
evaluated on the rising edge of TCK. The TMS pin is powered by the
2.5-V/3.0-V/3.3-V VCCPD.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by connecting this pin to VC CP D.
The clock input to the BST circuitry. Some operations occur at the rising edge, while
others occur at the falling edge. The TCK pin is powered by the 2.5-V/3.0-V/3.3-V
VC CPD supply.
TCK
N/A
Input
It is expected that the clock input waveform have a nominal 50% duty cycle.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by connecting TCK to GND.
Active-low input to asynchronously reset the boundary-scan circuit. The TRST pin
is optional according to IEEE Std. 1149.1. The TRST pin is powered by the
2.5-V/3.0-V/3.3-V VC CP D supply.
TRST
N/A
Input
You should hold TMS at 1 or you should keep TCK static while TRST is changed
from 0 to 1.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by connecting the TRST pin to GND.
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
Chapter 11: Configuring Stratix III Devices
Chapter Revision History
11–51
Chapter Revision History
Table 11–17 lists the revision history for this chapter.
Table 11–17. Chapter Revision History (Part 1 of 2)
Date
Version
March 2011
Changes Made
■
Updated the “FPP Configuration Using a MAX II Device as an External Host”, “Fast
Active Serial Configuration (Serial Configuration Devices)”, and “PS Configuration
Using a MAX II Device as an External Host”
■
Updated Table 11–14.
■
Updated Table 11–14.
■
Updated “FPP Configuration Using a MAX II Device as an External Host” on
page 11–8.
2.0
July 2010
1.9
Updated for the Quartus II software version 9.1 SP2 release:
March 2010
1.8
May 2009
1.7
February 2009
October 2008
© March 2011
1.6
1.5
Altera Corporation
■
Added Figure 11–11.
■
Updated Figure 11–6, Figure 11–7, Figure 11–16, Figure 11–19, and Figure 11–20.
■
Updated “Estimating Active Serial Configuration Time” section.
■
Added Table 11–8.
■
Updated Table 11–8, Table 11–13, and Table 11–14.
■
Removed “Conclusion” section.
■
Updated Table 11–1, Table 11–2, Table 11–5, Table 11–6, Table 11–9, and
Table 11–13.
■
Updated Figure 11–6, Figure 11–16, Figure 11–17, Figure 11–18, Figure 11–19,
and Figure 11–20.
■
Updated “PS Configuration Using a Microprocessor”, “PS Configuration Using a
Download Cable”, and “JTAG Configuration” sections.
■
Removed Figure 11-12 Fast AS Configuration Timing.
■
Removed Table 11-8 Fast AS Timing Parameters for Stratix III devices.
■
Updated Figure 11–6, Figure 11–7, Figure 11–12, and Figure 11–16.
■
Removed “Referenced Documents” section.
■
Updated “FPP Configuration Using a MAX II Device as an External Host”, “Fast
Active Serial Configuration (Serial Configuration Devices)”, “JTAG Configuration”,
“Power-On Reset Circuit”, “PS Configuration Using a MAX II Device as an External
Host”, and “PS Configuration Using a Download Cable” sections.
■
Updated Table 11–13 and Table 11–14.
■
Updated New Document Format.
■
Updated (Note 3) to Figure 11–17.
■
Updated (Note 3) to Figure 11–18.
■
Updated (Note 3) to Figure 11–19.
■
Updated (Note 3) to Figure 11–20.
Stratix III Device Handbook, Volume 1
11–52
Chapter 11: Configuring Stratix III Devices
Chapter Revision History
Table 11–17. Chapter Revision History (Part 2 of 2)
Date
May 2008
November 2007
October 2007
Version
Changes Made
■
Updated “Power-On Reset Circuit” section.
■
Updated “Fast Active Serial Configuration (Serial Configuration Devices)” section.
■
Updated Table 11–4, Table 11–11, Table 11–12, Table 11–13, Table 11–14, and
Table 11–16.
■
Updated Figure 11–3, Figure 11–4, Figure 11–5, Figure 11–6, Figure 11–7, Figure
11–8, Figure 11–9, Figure 11–10, Figure 11–11, Figure 11–13, Figure 11–14, Figure
11–15, Figure 11–17, Figure 11–18, Figure 11–19, Figure 11–20, and Figure 11–21.
■
Updated Table 11–2.
■
Updated Figure 11–8, Figure 11–14, Figure 11–15, Figure 11–17, and
Figure 11–18.
■
Updated Table 11–13, Table 11–14.
■
Updated Figure 11–6, Figure 11–7, Figure 11–9, Figure 11–10, Figure 11–11, and
Figure 11–13.
■
Removed text regarding enhanced configuration device support. Removed
Figure 11–19.
■
Added live links for references.
■
Added section “Referenced Documents”
1.4
1.3
1.2
May 2007
1.1
Removed Bank Column from Table 11–13.
November 2006
1.0
Initial Release
Stratix III Device Handbook, Volume 1
© March 2011
Altera Corporation
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