Datasheet EV10AS150B High Linearity ADC 10-bit 2.6 Gsps with 1:4 DMUX

EV10AS150B

High Linearity ADC 10-bit 2.6 Gsps with 1:4 DMUX

5 GHz Full Power Bandwidth

Datasheet

Features

•

ADC 10-bit Resolution

•

Up to 2.6 Gsps Sampling Rate

•

Selectable 1:4 or 1:2 Demultiplexed Digital LVDS Outputs

•

True Single Core Architecture (No Calibration Required)

•

External Interleaving Possible Via 3-Wire Serial Interface

– Gain Adjust

– Offset Adjust

– Sampling Delay Adjust

•

Full Scale Analog Input Voltage Span 500 mVpp

•

100

Ω Differential Analog Input and Clock Input

•

Differential Digital Outputs, LVDS Logic Compatibility

•

Low Latency Pipeline Delay

•

Test Mode for Output Data Registering (BIST)

•

Power Management (Nap, Sleep Mode)

•

EBGA317 (Enhanced Ball Grid Array) Package

Performance

•

Single Tone Performance in 1 st

Nyquist (–1 dBFS)

– ENOB = 8.0 bit, SFDR = –57 dBFS at 2.6 Gsps, Fin = 495 MHz


•

Single Tone Performance in 2 nd

Nyquist (–3 dBFS):


•

5 GHz Full Power Input Bandwidth (–3 dB)

•

±0.5 dB Band Flatness from 10 MHz to 2.0 GHz

•

Input VSWR = 1.25:1 from DC to 3 GHz

•

Bit Error Rate: 10

–12

at 2.6 Gsps

Screening

•

Temperature Range

– Commercial “C” Grade: Tamb > 0

° C ; T

J

< 90

° C

– Industrial “V” Grade: Tamb > –40

° C ; T

J

< 110

° C

Applications

•

Direct Broadband RF Down Conversion

•

Wide Band Communications Receiver

•

High Speed Instrumentation

•

High Speed Data Acquisition Systems

e2v semiconductors SAS 2012

Visit our website: www.e2v.com

for the latest version of the datasheet

1076D–BDC–10/12

EV10AS150B

1.

Block Diagram

The EV10AS150B combines a 10-bit 2.6 Gsps fully bipolar analog-to-digital converter chip, driving a fully bipolar DMUX chip with selectable Demultiplexing ratio (1:2) or (1:4). The 5 GHz full power input bandwidth of the ADC allows the direct digitization of up to 1 GHz broadband signals in the high IF region, in either L_Band or S_Band.

The 1:4 demultiplexed digital outputs are LVDS logic compatible, which allows easy interface with standard FPGAs or DSPs. The EV10AS150B operates at up to 2.6 Gsps in DMUX 1:4 and up to 2.0 Gsps in

1:2 DMUX ratio (The speed limitation with 1:2 DMUX ratio is mainly dictated by external data flow exchange capability at 2 × 1 Gsps with available FPGAs).

The EV10AS150B ADC+DMUX combo device is packaged in a 25 × 35 mm Enhanced Ball Grid Array

EBGA317. This Package is based on multiple layers which allows the design of low impedance continuous ground and power supplies planes, and the design of 50

Ω controlled impedance lines (100Ω differential impedance). This package has the same Thermal Coefficient of Expansion (TCE) as FR4 application boards, thus featuring excellent long term reliability when submitted to repeated thermal cycles.

Figure 1-1.

Functional Block Diagram

DRR (ADC Reset)

CLK

CLKN

3 WSI RESET

3 WSI

SLDN

SDATA

SCLK

3-wire Serial

Interface

(3WSI)

8-bit

DAC

Sampling delay

Gain

8-bit

DAC

Offset

8-bit

DAC

VIN

VINN

100

Ω

T/H

100

Ω

Timing

Circuitry

& SDA

Tunable

Delay line

CLKDACTRL

ASYNCRST

(Dmux Reset)

Tunable

Delay line

Demultiplexer

1:2 or 1:4

2

2

20

2

20

20

2

20

2

Port A

AOR/AORN

DRA/DRAN

Port B

BOR/BORN

DRB/DRBN

Port C

COR/CORN

DRC/DRCN

Port D

DOR/DORN

DRD/DRDN

DR/DRN

BIST (Pattern Generator)

SLEEP (DMUX)

STAGG (Latency)

RS (Ratio Sel)

DRTYPE (Dual Data Rate)

2

1076D–BDC–10/12 e2v semiconductors SAS 2012

EV10AS150B

2.

Specifications

This section describes the device specifications in terms of:

• Absolute max ratings

• Recommended conditions of use

• Electrical operating characteristics

• Timings

2.1

Absolute Maximum Ratings

Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability.

Maximum ratings on I/Os are defined with device powered ON.

All integrated circuits have to be handled with appropriate care to avoid damages due to ESD. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure.

Table 2-1.

Absolute Maximum Ratings

Parameter

Analog 4.9V Power Supply voltage


Digital 3.3V Power Supply Voltage

Output 2.5V Power Supply voltage

Minimum Analog input peak voltage

(1)

(with differential input)

Maximum Analog input peak voltage

(1)


Maximum difference between V

IN

and V

INN

(1)


Symbol

V

CCA5

V

CCA3

V

CCD

V

PLUSD

V

IN

or V

INN

V

IN

or V

INN

|V

IN

– V

INN

|

Minimum Analog input peak voltage

(2)

(with single ended input)

Maximum Analog input peak voltage

(2)


V

IN

with V

INN

= 50

Ω to GND or

V

INN

with V

IN

= 50

Ω to GND

V

IN

with V

INN

= 50

Ω to GND or

V

INN

with V

IN

= 50

Ω to GND

Maximum amplitude on V

IN

or V

INN

(2)


Minimum Clock input peak voltage

(with differential clock)

Maximum Clock input peak voltage


Maximum difference between V

CLK

and V

CLKN


3WSI input voltage

|V

IN

| or |V

INN

|

V

CLK or V

CLKN

V

CLK

or V

CLKN

|V

CLK

– V

CLKN

|

SDATA, SLDN, SCLK, RESET

Value

GND to 6.0

GND to 3.6

GND to 3.6

GND to 3.0

2.0

4.0

2.0

(4 Vpp = +13 dBm in 100

Ω)

2.0

4.0

(2 Vpp = +10 dBm in 50

Ω)

1.5

4.0

1.5

(3 Vpp)

–0.3 to V

CCA3

+ 0.3

Unit

V

V

V

V

V

V

V

V

V

V

V

V

V

V

1076D–BDC–10/12

3


EV10AS150B

Table 2-1.

Absolute Maximum Ratings (Continued)

Parameter

ADC Reset Voltage

DMUX function input voltage

DMUX Asynchronous Reset

DMUX Control Voltage

Maximum input voltage on DIODE

Maximum input current on DIODE

Max Junction Temperature

Storage temperature

ESD protection (HBM)

Symbol

DRR

RS, DRTYPE, SLEEP, STAGG, BIST

ASYNCRST

CLKDACTRL

DIODE ADC

DIODE ADC

T

J

Tstg

Value

–0.3 to V

CCA3

+ 0.3

–0.3 to V

CCD

+ 0.3

–0.3 to V

CCD

+ 0.3

–0.3 to V

CCD

+ 0.3

700

1

135

–55 to 150

≥ 500 on ADC inputs

500 on DMUX outputs

Notes:

1. See Section 2.1.1

.

2. See Section 2.1.2

.

2.1.1

Analog Input Max Ratings in differential configuration

Internal DC Common mode bias for differential analog inputs is: +3V (90.9% of V

CCA3

).

Input impedance on V

IN

and V

INN

is: 55

Ω // 550Ω = 50Ω.

Max rating is ±1V = 2 Vpp on each single ended input, corresponding to 4 Vpp in differential.

Unit

V

V

V

V mV mA

° C

° C

V

• Vinput max = 3V + 1V = 4V

• Vinput min = 3V – 1V = 2V

• With V

IN

= +4V and V

INN

= +2V => V

IN

– V

INN

= +2V

• With V

INN

= +4V and V

IN

= +2V => V

IN

– V

INN

= –2V

Figure 2-1.

Analog Input Max Ratings in Differential Configuration

Differential analog input signals:

Max rating differential inputs = ± 2 Vpeak = 4 Vpeak to peak

Maximum voltage on VIN or on VINN : +4 Volt:

=> ESD protections connected between VIN and VINN to +3.25V

4V max

VIN

VINN

DC blocking

50

Ω Line

VIN

DC blocking

50

Ω Line

2V min

VINN

Max (VIN - VINN) = 4 Volt peak-peak

EV10AS150B

V

CCA3

= +3.25V

+0.7V max

+ 10 mA max

55

Ω

ESD

V

CCA5

= +4.9V

V

CCA3

= +3.25V

+3V DC common mode

+0.7V max

+ 10 mA max

55

Ω

± 2Vpeak max diff

ESD

VINN

ESD

550

Ω

550

Ω

ESD

GND

4


EV10AS150B

2.1.2

Analog Input Max Ratings in Single Ended Configuration

Internal DC common mode bias for differential analog inputs is +3V (90.9% of V

CCA3

).

Input impedance on V

IN

(and V

INN

) is: 55

Ω // 550Ω = 50Ω

Max rating is ±1V on one single ended signal, corresponding to 2 Vpp on 50

Ω

Limiting parameter for maximum rating is not V

IN

– V

INN

differential input voltage but V

IN

peak voltage value which shall not exceed +4V to avoid turning on the ESD protection tied to V

CCA3

= +3.25V.

Vinput max = 3V (CM) + 1V (ESD) = 4V (If +4 Vp is applied, the ESD protections becomes forward biased: (+4V – 3.25V = +0.75V).

Vinput min = 3V – 1V = 2V

The ESD diode can sustain up to 10 mA forward biasing without damage, but incoming signal will be clipped at +4V = +3V (internal DC common mode) + 1V.

Figure 2-2.

Analog Input Max Ratings in Single Ended Configuration

Single-ended analog input signal:

Max rating differential inputs = ±1Vpeak = 2 Vpeak to peak

Maximum voltage on VIN: +4 Volt

Minimum voltage on VIN: +2 Volt

=> ESD protections connected between VIN and VINN to +3.25V:

+0.7 Volt max, + 10 mA max

VIN

4V max

VIN

DC blocking

50

Ω Line

EV10AS150B

V

CCA3

= +3.25V

+0.7V max

+ 10 mA max

55

Ω

ESD

V

CCA5

= +4.9V

+3V DC

± 2Vpeak max diff

V common mode

CCA3

55

Ω

= +3.25V

+0.7V max

+ 10 mA max

ESD

VINN

2V min

ESD

550

Ω 550

Ω

ESD

50

Ω

DC blocking

VINN

50

Ω Line

GND

GND = 0V

1076D–BDC–10/12

5


EV10AS150B

2.2

Recommended Conditions of Use

Table 2-2.

Recommended Conditions of Use

Symbol Parameter

Power supplies



Digital 3.3V Power Supply voltage

Output 2.5V Power Supply voltage

Analog Input

Recommended Configuration

Clock Input

Recommended Configuration

V

CCA3

V

CCA5

V

CCD

V

PLUSD

Clock input power level

External clock Duty cycle

Control functions input level

ADC 3WSI Inputs

ADC Reset

P

CLK

P

CLKN

DCYC

DMUX Control Inputs

Operating Temperature


DRR

SLEEP, STAGG, ASYNCRST,

BIST, RS, DRTYPE,

CLKDACTRL

T

J

Comments

No specific power supply sequencing required during power

ON / OFF

100

Ω differential clock

Recommended

3.25

4.75V to 4.9V

3.3

2.5

Differential Analog input

Differential Clock input

+1 dBm / 50

Ω

(1Vpp in 100

Ω)

50

0 to V

CCA3

0 to V

CCA3

0 to V

CCD

Best performances at highest temperatures

Unit

dBm

%

V

V

V

V

V

V

V

Table 2-3.

3WSI Register

Recommended Configuration for Optimum Dynamic Performances

Recommended value

State register SDA OFF

comment

For optimum SNR in 2 nd

Nyquist zone if not used in interleaving mode

Clock duty Cycle adjust register D4….D0

35/65%

Clock adjust register D4 … D0 +30 ps

Gain adjust D7...D0

Minimum gain

For optimum SFDR and THD

For optimum SFDR and THD

For optimum SNR and SFDR

SNR can be increased by around 1 dB if V

CCA5

is decreased from 4.9V to 4.75V.

SFDR in the 2 nd

Nyquist is optimum near V

CCA

= 4.9V. Decreasing V

CCA the 2 nd

Nyquist by around 4 dB.

at 4.75V will degrade SFDR in

6


EV10AS150B

2.3

Electrical Characteristics for Supplies, Inputs and Outputs

Unless otherwise specified:

Values are given over temperature and power supplies range.

Table 2-4.

Electrical Characteristics for Supplies, Inputs and Outputs

Test Level Symbol Parameter

Power requirements

Power Supply voltages

Analog 4.9V

Analog 3.25V

Digital 3.3V

Output 2.5V

Power Supply current in 1:2 DMUX

Analog V

CCA5

= 4.9V

Analog V

CCA3

= 3.25V

Digital V

CCD

= 3.3V

Output V

PLUSD

= 2.5V

Power Supply current in 1:4 DMUX

Analog V

CCA5

= 4.9V

Analog V

CCA3

= 3.25V

Digital V

CCD

= 3.3V

Output V

PLUSD

= 2.5V

Power Supply current in NAP and SLEEP mode

Analog V

CCA5

= 4.9V

Analog V

CCA3

= 3.25V

Digital V

CCD

= 3.3V

Output V

PLUSD

= 2.5V

Power dissipation

- 1:2 DMUX

- 1:4 DMUX

- NAP & SLEEP mode (1:4 or 1:2)

Analog inputs

Common mode compatibility for analog inputs

(1)

Analog inputs common voltage (internal)

Full-Scale input Voltage Range

Differential mode

Full-Scale input Voltage Range

Single ended mode with other input connected to ground through 50

Ω resistors

Analog Input power Level

(in 100

Ω differential termination)

Analog Input power Level

(in 50

Ω single ended termination)

Analog input capacitance (die)

Input leakage current

1

1

1

1

1

4

1

1

1

4

4

4

V

CCA5

V

CCA3

V

CCD

V

PLUSD

I

VCCA5

I

VCCA3

I

VCCD

I

VPLUSD

I

VCCA5

I

VCCA3

I

VCCD

I

VPLUSD

I

VCCA5

I

VCCA3

I

VCCD

I

VPLUSD

P

D

V

CM

V

IN

V

INN

V

IN

or V

INN

P

IN, INN

P

IN or P

INN

C

IN

I

IN

Min

4.75

3.15

3.15

2.4

–250

Typ

4.9

3.25

3.3

2.5

150

850

350

470

150

850

400

490

110

560

130

400

5.8

6.0

3.8

–5

0.5

–2

0.3

10

Max

5.05

3.35

3.45

2.6

190

990

430

620

190

990

470

650

150

800

150

550

7.4

7.6

5.4

AC or DC (AC recommended)

3.0

–125

–125

125

125

250

Unit

W

W

W mA mA mA mA mA mA mA mA mA mA mA mA

V

V

V

V

V mV mV dBm

Vpp dBm pF

µA

1076D–BDC–10/12

7


EV10AS150B

Table 2-4.

Parameter

Input resistance

- Single-ended

- Differential

Clock inputs

Electrical Characteristics for Supplies, Inputs and Outputs (Continued)

Test Level Symbol Min

4 R

IN

R

IN, INN

47

94

Logic common mode compatibility for clock inputs

ADC intrinsic clock jitter

(2)

4

4

Typ

50

100

Max

53

106

Low phase noise sinewave at 2.6 GHz (> 155 dBc/Hz) or low jitter LVDS/LVPECL (<100 fs rms)

120

Clock inputs internal DC common mode voltage 4 V

CM

3.0

90.9%

Clock input voltage on each single ended input (2.6 GHz sinewave)

Clock input voltage into 100

Ω differential clock input

(2.6 GHz sinewave)

Clock input power level (2.6 GHz low phase noise sinewave input) in 50

Ω

Sinewave or Square wave

Clock signal (minimum) slew-rate

Square Wave differential Clock input voltage on 100

Ω input

(LVDS & LVPECL compatible)

Clock input capacitance (die)

Clock input Resistance

- Single-ended

- Differential

Digital Data Outputs

Logic compatibility

50

Ω transmission lines, 100Ω (2 × 50Ω) differential termination

- Logic low

- Logic high

- Differential output

- Common mode

Control Function Inputs

ASYNCRST (DEMUX Reset) input voltages and currents

- Logic Low

- Logic High (reset mode)

4

4

4

4

4

4

4

1

1

V

CLK or V

CLKN

|V

CLK

–V

CLKN

|

P

CLK, CLKN

SR

CLK, CLKN

VSQ

CLK-CLKN

C

CLK

R

CLK

R

CLK, CLKN

VOL

VOH

VODIFF

VOCM

V

IL

I

IL

V

IH

I

IH

±0.158

0.632

–3

5

0.25

47

94

1.25

250

1.125

0

–300

1.8

±0.25

1

+1

8

0.8

0.3

50

100

LVDS

1.075

1.375

350

1.25

±0.5

2

+7

2

53

106

1.25

450

1.375

1.4

V

CCD

50

DRR (ADC reset)

(3)

Logic low

Logic high

Threshold

4

V

IL

V

IH

V

TH

0

1.5

1.4

1.1

V

CCA3

Unit

fs rms

V

% of

V

CCA3

V

Vpp dBm

GV/s

Vpp pF

V

µA

V

µA

V

V

V

Ω

Ω

Ω

Ω

V

V mV

V

8


EV10AS150B

Table 2-4.

Electrical Characteristics for Supplies, Inputs and Outputs (Continued)

Test Level Symbol Min Parameter

RS, BIST, STAGG, SLEEP, DRTYPE (Control Input Voltages)

- Logic low

(4)

Resistor to ground

Voltage level

Input low current

- Logic high

(4)

Resistor to ground

Voltage level

Input high current


Logic low

Logic high

CLKDACTRL input voltage

1

4

4

R

IL

V

IL

I

IL

R

IH

V

IH

I

IH

V

IL

V

IH

0

–500

10k

2.0

0

2.3

1/3 × V

CCD

Typ Max

10

0.5

Infinite

10

1.0

V

CCA3

2/3 × V

CCD

Unit

Ω

V

µA

Ω

V

µA

V

V

V

Notes: 1. The DC analog common mode voltage is provided by ADC.

2. Measured with SDA OFF(ADC Jitter = 120 fs rms). ADC Jitter with SDA = ON is 150 fs rms, and 170 fs rms with SDA = ON and fully tuned.

3. DRR logic programmable with 3WSI interface. Default value is DRR active low.

4. See Section 4.4 on page 43

for control signal settings.

2.4

Converter Characteristics


Recommended conditions of use (refer to Table 2-2 and Table 2-3 on page 6

). Values are specified for

Tj

≥ 65°C and over specified power supplies range.

Typical values are given at ambient (Tj ~65°C) with typical power supplies.

These conditions apply for all tables from Table 2-5 to

Table 2-7 .

Table 2-5.

DC Converter Characteristics

Test Level Parameter

DC Accuracy

Resolution

DNLrms

(1)

Differential non-linearity

(1)

Differential non-linearity

(1) )

Integral non-linearity

(1)

Integral non-linearity

(1)

Gain center value

(2)

Gain error drift

Input offset voltage

(3)

1

4

4

4

1

4

4

1

4

Symbol

N

DNLrms

DNL+

DNL-

INL-

INL+

G

G(T)

OFFSET

Min

–1.0

0.95

Typ

–3.0

2.3

1

50

10

0.22

0.75

0.6

Max

1.05

Unit

bit

LSB

LSB

LSB

LSB

LSB ppm/

° C mV –20 20

Notes: 1. Histogram testing at Fs = 2.6 Gsps Fin = 100 MHz satured.

DNLrms is the deviation from ideal ADC rms quantification noise. For reference, a DNL of 0.22 LSB rms has the same order of magnitude as the 10 Bit rms quantification noise : 1 LSB/ SQRT(12) = 1 LSB /

3.46 = 0.288 LSB rms.

1076D–BDC–10/12

9


EV10AS150B

2. ADC gain with programmed default value.

This ADC Gain can be fine tuned to “1” by monitoring of the gain adjust function through the 3WSI serial interface.

3. ADC offset with programmed default values.

The ADC Offset can be compensated through the 3WSI up to ± 20 mV by an 8 Bit embedded control

DAC: Resolution: 40 mV/256 = 156 µV (See 3WSI table in Section 4.5.3 ”3WSI Register Description” on page 51

).

Table 2-6.

Dynamic Converter Characteristics

Test

Level Parameter

AC Characteristics

Full Power Input Bandwidth (–3 dB)

Gain Flatness (10 MHz-1.7 GHz)

• Systematic roll-off

• AC gain variation

Gain Flatness (1.7 GHz-2.9 GHz)



Gain Flatness (2.9 GHz-4.4 GHz)



Input Voltage Standing Wave Ratio

(DC

–

3 GHz)

(3 GHz – 5 GHz)

4

4

4

Symbol

FPBW

GF

VSWR

Min Typ

5

–0.5

±0.1

–

0.5

±0.2

–

1.0

±0.3

Max

1.25:1

1.50:1

Unit

GHz dB

Table 2-7.

Dynamic Converter Characteristics

Parameter

Effective Number of Bits

Fs = 2.6 Gsps Fin = 495 MHz





Test

Level

AC Performance with differential analog input

Ain = –1 dBFS, +1 dBm differential clock (1 Vpp in 100

Ω), 50% external duty cycle, binary output mode

Signal to Noise and Distortion Ratio






4

4

1

1

4

SINAD

44.0

44.0

50.0

49.5

48.0

48.0

49.0

4

4

1

1

4

Symbol

ENOB

Min

7.0

7.0

Typ

8.0

7.9

7.7

7.7

7.8

Max Unit

dBFS

Bits

10


EV10AS150B

Table 2-7.

Dynamic Converter Characteristics (Continued)

Parameter

Signal to Noise Ratio






Total Harmonic Distortion (10 harmonics)






Test

Level

1

1

4

4

4

1

1

4

4

4

Symbol

SNR

|THD|

Min

45.0

45.0

45.0

45.0

Typ

52.0

52.0

51.0

49.0

50.0

54.0

54.0

51.0

53.0

56.0

Spurious Free Dynamic Range






Two-Tone 3 rd order Intermodulation distortion

IMD3 (

–

): (2f1-f2, 2f2-f1) at

–

7 dBFS each tone, Fs = 2.6 Gsps

Fin1 = 790 MHz, Fin2 = 800 MHz

Fin1 = 1550 MHz, Fin2 = 1560 MHz

Fin1 = 2640 MHz, Fin2 = 2650 MHz

1

1

4

4

4

1

1

4

4

4

8.1

8.1

8.0

7.9

7.9

57.0

57.0

54.5

57.0

60.0

59

59

59

Signal independent Spurious level

(Fclk/4 with 1:4 DMUX Ratio)

(

–

1 dBFS Analog Input)

Differential driven analog input (100

Ω)

(ADC full scale input power:

–

5 dBm)

(0.5Vpp in 100

Ω Differential analog input)

4 Fclk/4

–

–

78

83

Ain =

–

3 dBFS, + 1 dBm differential clock (1 Vpp in 100








1

1

4

4

4

SINAD

45.0

45.0

50.5

51.0

50.0

49.0

49.0







4

|SFDR|

IMD3(

–

)

ENOB

49.0

49.0

7.2

7.2

Max Unit

dBFS dBFS dBFS dBc dBFS dBm dBFS

Bits

1076D–BDC–10/12

11


EV10AS150B

Table 2-7.


Parameter







Test

Level

1

1

4

4

4

Symbol

SNR

Min

46.0

46.0

Typ

52.0

52.0

52.0

50.5

50.5













1

1

4

4

4







1

1

4

4

4

|SFDR|

50.0

50.0

60.0

61.0

60.0

59.0

59.0

Ain = –13 dBFS, +1 dBm differential clock (1 Vpp in 100








4

4

1

1

4

SINAD

47.0

47.0

51.5

51.5

51.5

51.0

50.5

4

4

1

1

4

|THD|

ENOB

49.0

49.0

7.5

7.5

56.0

55.0

54.5

54.0

55.0

8.2

8.2

8.2

8.2

8.1

Max Unit

dBFS dBFS dBFS dBFS

Bits

12


EV10AS150B

6.5

6.0

5.5

5.0

7.5

7.0

Table 2-7.


Test

Level Symbol Parameter



















1

1

4

4

4

1

1

4

4

4

1

1

4

4

4

SNR

|THD|

|SFDR|

Min

50.5

50.5

48.0

48.0

50.0

50.0

Typ

57.0

57.0

57.0

56.5

57.0

53.0

53.0

53.0

53.0

52.0

58.0

58.0

58.0

57.5

58.0

Max Unit

dBFS dBFS dBFS

Note: Dynamic performances near full scale may vary by up to typically #0.6 bit ENOB (compared to performances specified in

Table 2-7 ) around Fclk 0.85 Gsps, 1.6 Gsps, 1.8 Gsps, 2.1 Gsps & 2.35 Gsps as

illustrated in Figure 2-3 . For best performances, use the device in the recommended conditions settings

described in Table 2-2 and Table 2-3

.

Figure 2-3.

ENOB performance versus Fclock

ENOB versus Fclk & Gain - Fin=2595 MHz @-1dBFs

Recommended conditions of use and typical supplies - Tj = 65°C

Min Gain

Typ gain

Max Gain

8.0

Fclock (Gsps)

1076D–BDC–10/12

13


EV10AS150B

2.4.1

2.4.2

When a single tone sinewave at level of around -6 dBFs is applied, a SNR reduction may be observed by typically #3-5 dB resulting in ENOB decrease (#-0.8 bit). (No impact on THD/SFDR). In time domain the

"glitches" that may be observed in this condition are 32 LSB maximum. Their potential occurrence is reduced with minimum gain and minimum VCCA5 and higher temperature. Low Fin (1st Nyquist) and/or low Fclk Frequencies are also more favourable cases.

ADC Converter Characteristics with Single Ended Analog Input

For optimum dynamic performances, it is strongly recommended to use a differential Analog input.

In single ended input at low levels, dynamic performances are similar to those specified in

Table 2-7

.

However, for high input levels, THD & SFDR are reduced by around 1dB compared to

Table 2-7

.

Sensitivity of Dynamic Performances to Power Supplies

The three figures below illustrate the impact of VCCA3 and VCCA5 power supplies on dynamic performances near full scale depending on Nyquist zone (1st or 2nd).

Measurements conditions are the recommended conditions of use defined in

Table 2-2

&

Table 2-3

at

ambient temperature (Tj ~ 65°C).

Figure 2-4.

ENOB versus VCCA5 & VCCA3

ENOB @2.6Gsps versus Vcca5 & Vcca3

Recommended conditions of use - Tj = 70°C

7.95

7.90

7.85

7.80

7.75

7.70

7.65

4.70

4.75

4.80

4.85

4.90

Vcca5 (V)

4.95

5.00

5.05

5.10

Vcca3 typ, Fin=2.595 GHz

@-1dBFs

Vcca3 min, Fin=2.595 GHz

@-1dBFs

Vcca3 max, Fin=2.595 GHz

@-1dBFs


@-1dBFs


@-1dBFs


@-1dBFs

14


EV10AS150B

Figure 2-5.

SNR versus VCCA5 & VCCA3

SNR @2.6Gsps versus Vcca5 & Vcca3


52.5

52.0

51.5

51.0

50.5

50.0

49.5

49.0

4.70

4.75

4.80

4.85

4.90

Vcca5 (V)

4.95

5.00

5.05

5.10


@-1dBFs


@-1dBFs


@-1dBFs


@-1dBFs


@-1dBFs


@-1dBFs

Figure 2-6.

THD versus VCCA5 & VCCA3

THD @2.6Gsps versus Vcca5 & Vcca3


-56

-55

-54

-53

-52

4.70

4.75

4.80

4.85

4.90

4.95

Vcca5 (V)

5.00

5.05

5.10


@-1dBFs


@-1dBFs


@-1dBFs


@-1dBFs


@-1dBFs


@-1dBFs

1076D–BDC–10/12

15


EV10AS150B

2.4.3

Sensitivity of dynamic performances to temperature

The three following figures illustrate the impact of junction temperature on dynamic performances in 1st

& 2nd Nyquist zone and versus Analog input level.

Measurements conditions are the recommended conditions of use defined in

Table 2-2

&

Table 2-3

.

Figure 2-7.

ENOB versus junction temperature in 1st & 2nd Nyquist

ENOB @2.6Gsps Fin = 1.295 GHz

ENOB @2.6Gsps Fin = 2.595 GHz

9.0

9.0

8.5

8.5

8.0

@-1dBFs

@-3dBFs

@-7dBFs

@-13dBFs

8.0

7.5

7.5

7.0

7.0

6.5

-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130

Tj (°C)

6.5

-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130

Tj (°C)

Figure 2-8.

SNR versus junction temperature in 1st & 2nd Nyquist

SNR @2.6Gsps Fin = 1.295 GHz

54.0

53.0

52.0

51.0

50.0

49.0

48.0

47.0

46.0

-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130

Tj (°C)

@-1dBFs

@-3dBFs

@-7dBFs

@-13dBFs

SNR @2.6Gsps Fin = 2.595 GHz

54.0

53.0

52.0

51.0

50.0

49.0

48.0

47.0

46.0

-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130

Tj (°C)

Figure 2-9.

SFDR versus junction temperature in 1st & 2nd Nyquist

SFDR @2.6Gsps Fin = 1.295 GHz

-69.0

-69.0

SFDR @2.6Gsps Fin = 2.595 GHz

-64.0

-59.0

-54.0

-64.0

@-1dBFs

@-3dBFs

@-7dBFs

@-13dBFs

-59.0

-54.0

-49.0

-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130

Tj (°C)

-49.0

-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130

Tj (°C)

16


EV10AS150B

2.4.4

Figure 2-10. THD versus junction temperature in 1st & 2nd Nyquist

THD @2.6Gsps Fin = 1.295 GHz

-68.0

-68.0

THD @2.6Gsps Fin = 2.595 GHz

-63.0

-58.0

@-1dBFs

@-3dBFs

@-7dBFs

@-13dBFs

-63.0

-58.0

-53.0

-53.0

-48.0

-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130

Tj (°C)

-48.0

-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130

Tj (°C)

Examples of FFT Spectrum

Following spectrums (32 Kpts FFT) are given for the following conditions:


Recommended conditions of use (refer to

Table 2-2

and

Table 2-3 on page 6

).

Typical supplies

Ambient temperature with heatspreader (Tj ~65 °C)

Figure 2-11. FFT 2.6 Gsps Fin = 1295 MHz @–1 dBFS

2.6Gsps Fin = 1.295 GHz -1dBFs

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0 100 200 300 400 500 600

F (MHz)

700 800 900 1000 1100 1200 1300

1076D–BDC–10/12

17


EV10AS150B

Figure 2-12. FFT 2.6 Gsps Fin = 1295 MHz @-3 dBFS

2.6 Gsps Fin = 1.295 GHz -3dBFs

-40

-50

-60

-70

-80

-90

-100

0

0

-10

-20

-30

100 200 300 400 500 600

F (MHz)

700 800 900 1000 1100 1200 1300

Figure 2-13. FFT 2.6 Gsps Fin = 1295 MHz @-7 dBFS


-30

-40

-50

-60

-70

-80

-90

-100

0

0

-10

-20

100 200 300 400 500 600

F (MHz)

700 800 900 1000 1100 1200 1300

18


EV10AS150B

Figure 2-14. FFT 2.6 Gsps Fin = 1295 MHz @–13 dBFS

2.6Gsps Fin = 1.295GHz -13dBFs

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0 100 200 300 400 500 600

F (MHz)

700 800 900 1000 1100 1200 1300

Figure 2-15. FFT 2.6 Gsps Fin = 2595 MHz @–1 dBFS (Carrier at end of the 2nd Nyquist Zone is

folded back to baseband)


0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0 100 200 300 400 500 600

F (MHz)

700 800 900 1000 1100 1200 1300

1076D–BDC–10/12

19


EV10AS150B




0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0 100 200 300 400 500 600

F (MHz)

700 800 900 1000 1100 1200 1300



2.6Gsps Fin = 2.595GHz -7dBFs

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0 100 200 300 400 500 600

F (MHz)

700 800 900 1000 1100 1200 1300

20


EV10AS150B




0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0 100 200 300 400 500 600

F (MHz)

700 800 900 1000 1100 1200 1300

2.5

Transient and Switching Characteristics


Recommended conditions of use (refer to Table 2-2 and Table 2-3 on page 6

). Values are specified for

Tj

≥ 65°C and over specified power supplies range.

Typical values are given at ambient (Tj ~65°C) with typical power supplies.

These conditions apply for all tables from Table 2-8 to

Table 2-9 .

Table 2-8.

Transient Characteristics

Parameter Test Level Symbol Min Typ Max Unit

TRANSIENT PERFORMANCE

Bit Error Rate

(1)

ADC settling time (± 2%)

Overvoltage recovery time

ADC step response

Rise/Fall Time (10–90%)

4

4

4

4

BER

TS

ORT

10

–12

70

350

400

85

Error/sample ps ps ps

Note: 1. Measured with SDA OFF

ADC Bit Error Rate is related to internal regeneration latches indecision (for analog inputs very close to latches threshold), which may produce large amplitude output errors. The probability of error is measured at 2.6 Gsps maximum operating frequency.

1076D–BDC–10/12

21


EV10AS150B

Table 2-9.

Switching Characteristics

Parameter

Switching Performance and Characteristics

Maximum Clock Frequency

DRTYPE = DR/2, 1:2 mode

DRTYPE = DR, 1:2 mode

DRTYPE = DR/2 1:4 mode

DRTYPE = DR 1:4 mode

Minimum clock frequency

Minimum Clock pulse width (High)

Minimum Clock pulse width (Low)

External clock Duty cycle

(1)

Aperture Delay

(2)

Aperture Jitter added by the ADC

(2)

Output Rise/Fall time for Data (20% – 80%)

(3)

)

Output Rise/Fall time for Output Clock (20% – 80%)

(3)

Digital Data Output propagation delay

Data Ready Clock Output propagation delay

Differential propagation delay (Output Data vs. Data clock)

Tskew (40 digital output data)

Output Data Pipeline delay (Latency)

Synchronized 1:2 mode on Port A

Synchronized 1:2 mode on Port B

Synchronized 1:4 mode on Port A

Synchronized 1:4 mode on Port B

Synchronized 1:4 mode on Port C

Synchronized 1:4 mode on Port D

Test Level

4

4

4

4

4

4

4

4

4

4

4

4

1

1

4

4

Symbol

Fs MAX

Fs MIN

TC1

TC2

DCYC

TA

Jitter

TR/TF

TR/TF

TOD

TDR

TOD – TDR

Tskew

Min

2.0

2.0

2.6

2.6

0.192

0.192

45

300

0

Typ

50

350

120

120/120

120/120

2.5

2.35

150

± 15

5.5

4.5

Max

500

1.0

1.0

55

400

180/180

180/180

200

± 35

Unit

Gsps

4 PD 7.5

6.5

5.5

4.5

Clock

Cycles

Staggered 1:2 mode or 1:4 mode

ASYNCRST minimum pulse width

DRR minimum pulse width

5

5

RSTPW

DRRPW

4.5

3

3.5

ns ns

Notes: 1. ADC performance are given for optimum value of 50% external clock duty cycle.

2. ADC Aperture delay and Aperture jitter measured with SDA = OFF. (Default setting at Reset).

3. Rise time and fall time are defined for 100

Ω differentially terminated output load with 2nH and 2 pF termination parasitics.

2.6

Timing Diagram

2.6.1

Aperture Delay

The analog input is sampled on the rising edge of the differential clock input (CLK, CLKN) after TA (aperture delay) of +350 ps typical. Aperture delay (TA) is measured at package input balls with the assumption that the external trace length of analog input and clock input are well matched (6.6 ps/mm of mismatch with

ε r

= 4).

Msps ns ns

% ps fs rms ps ps ns ns ps ps

22


EV10AS150B

2.6.2

2.6.3

Latency (Simultaneous Mode and Staggered Mode)

In simultaneous output mode with 1:4 DMUX Ratio, the digitized digital output data N, N+1,N+2, N+3 respectively on port A, B, C and D are aligned (on the latest data available N+3 on port D). The data N on port A is available after 7.5 Clock cycles pipeline delay, plus an additional propagation delay TOD

(due to Output Buffers + Package propagation delay). Due to data alignment, the pipeline delay is decreased of one clock cycle for each port from port A to D leading to:

• 7.5 clock cycles for port A

• 6.5 clock cycles for port B

• 5.5 clock cycles for port C

• 4.5 clock cycles for port D

In simultaneous output mode with 1:2 DMUX ratio, the latency becomes respectively 5.5 and 4.5 Clock cycles on port A and port B, with same TOD propagation delay.

In staggered output mode, the latency of the 4 Digital output ports A,B,C,D is the same, since data are presented on output port as soon as available.

In staggered mode for 1:4 DMUX ratio and 1:2 DMUX ratio latency is only 4.5 Clock cycles for port A, B,

C and D (see Timing Diagram).

The output propagation delays TOD1, TOD2, TOD3, and TOD4 of the 4 outputs ports in staggered mode can be considered as identical to TOD.

Data Ready Positioning Versus Output Data (DR/2 Mode and DR Mode)

The Data Ready output clock signal (DR, DRN) is synchronized with ADC (CLK, CLKN) differential clock falling edges to be synchronous with Digital output data (since digital data are output on falling edge of sampling Clock after a latency of 7.5 Clock cycles).

In 1:4 DMUX Ratio, the (DR, DRN) signal is shifted by 2 clock cycles in order to be located at center of data pulse.

In 1:2 DMUX Ratio, the (DR, DRN) signal is shifted by 1 clock cycle to be located at center of data pulse.

Furthermore, the output propagation delay (TDR) of the Data Ready signal and the output propagation delay of the digital data (TOD) are matching very closely, and track each other over full operating temperature range.

Therefore the Data signals and Data clock signals are synchronized at Package output, with the differential Data Ready output clock pulse rising edge being centered within Data pulse, in either dual Data rate mode (DR/2) or DR mode.

In dual data rate (DR/2 mode), the Data clock switches at the same rate as the digital data, and therefore both the rising and falling edges of (DR, DRN) data clock are located at the center of the data pulse over temperature (with max TOD-TDR = 200 ps).

In DR mode, the Data clock switches at twice the rate of the digital data, with the differential Data Ready pulse rising edge being centered within Data pulse and differential falling edges being synchronous with

Data transitions.

1076D–BDC–10/12

23


EV10AS150B

2.6.4

2.6.5

Differential Timing Values TOD-TDR Versus Absolute Timing Values TOD and TDR

The absolute values for TOD and TDR are given for information only, and are corresponding to the digital output data propagation delay and to the Data Ready output propagation delay, related to ADC output buffers throughput delay and package propagation times.

TOD and TDR are measured at Package I/Os level, (Input/Outputs Balls), taking out the board extra propagation delays of the 50

Ω/100Ω controlled impedance lines.

Assuming the application board trace lengths are matched for digital data and data ready lines (within skew limit), one has only to consider the time difference between differential digital data outputs and differential Data clock signals TOD-TDR in simultaneous mode.

In staggered mode, the differential delays are (TOD1-TDR1), (TOD2-TDR2), (TOD3-TDR3), (TOD4-

TDR4). See

Figure 2-20 on page 27 .

Therefore the absolute delay values TOD and TDR are not actually of interest: only the time difference

TOD-TDR has to be actually considered.

The measurement of the relative time difference is easy with matches probes, whereas absolute timings are very difficult to measure.

If the propagation time delays (trace lengths for digital data outputs and Data Ready outputs are well matched, together with ideal TOD = TDR, we shall measure ideally TOD-TDR = 0 at application board outputs (FPGA or DSP incoming signals).

Alignment Between Data Ready and Data Including Skew Management

Real TOD-TDR excluding skew between different data is 150 ps typical, and 200 ps max.

In simultaneous mode, one common Data Ready pulse (DR, DRN) is output for all 4 differential Output

Ports A,B,C,D. Therefore the skews of the 4 differential data ports have to be as low as possible: the skews of the 4 differential output ports due to ADC Package and internal ADC Buffers is less than ±

35 ps max (measured at Package output Balls).

The external skews due to track length differences of the external 100

Ω controlled impedance lines), shall be kept as low as possible.

For example, (considering 3.3 ps/mm propagation time in vacuum), the signal propagation time in a different medium of dielectric constant

ε r

= 4 (at 10 GHz), is yielding to SQRT(

ε r

) × 3.3 ps/mm =

6.6 ps/mm: a 3 mm skew in length between the 40 differential data will result in a 3 mm × 6.6 ps/mm =

~ 20 ps skew, to be added to the ±35 ps skew due to the ADC (Package outputs).

The total skew (ADC + board) will be in this case 70 ps + 20 ps = 90 ps = ± 45 ps in actual skew at FPGA incomings.

Since TOD-TDR is 150 ps typical, and 200 ps max, TOD-TDR shall be added to the total data skew,

(ADC and board), leading to:

(TOD-TDR) + Tskew(total) = (200 ps) + (± 45 ps) = 245 ps maximum uncertainty on positioning of differential Data Ready signal rising edge (DR, DRN), pulse within Data pulse.

In staggered mode, the 4 (four) out-of-range bit function for the 4 (four) Ports A,B,C,D are respectively re-allocated to the Data Ready function, available for each output Port, since latency is different, namely:

Port A (AOR, AORN); Port B (BOR, BORN); Port C (COR, CORN); Port D (DOR, DORN) is respectively replaced by: (DRA, DRAN), (DRB, DRBN), (DRC, DRCN), (DRD, DRDN).

The output propagation delays of the 4 Data Ready pulses (TDR1, TDR2, TDR3, TDR4) are identical to the TDR output propagation delay in simultaneous mode, and are matching the Digital Data propagation delays of the 4 Output Ports over temperature.

24


EV10AS150B

2.6.6

The relative differential timing values (TOD1-TDR1), (TOD2-TDR2), (TOD3-TDR3), (TOD4-TDR4) are identical to the TOD - TDR differential timing of the simultaneous mode. Skew for port A, B, C, D are considered for 10 bit data in staggered instead of 44 bit of data in simultaneous. Skew between 10 data is slightly better in staggered mode. To simplify calculation skew values of previous section shall be applied.

Minimum Available Time Width Between Data and Data Ready (TD1, TD2)

At 2.6 GHz sampling rate, the time difference between zero crossing point of change of differential data and differential Data Ready output clock rising edge (centered within data pulse) is defined by TD1. The time difference between differential data clock rising edge and next point of change of the differential data output is defined by TD2.

The order of magnitude of time difference TD1-TD2 is identical to TOD-TDR:

TOD-TDR is frequency independent, whereas TD1 and TD2 are sampling frequency dependent:

For example at 1:4 DMUX ratio, the data pulse width at maximum operating frequency of 2.6 GHz is

4 × 384.6 ps = 1.538 ns. Assuming TOD = TDR, the rising edge of differential data clock is ideally located at center of data pulse, with TD1 = TD2 = 770 ps. With a maximum difference of TOD-TDR of

200 ps over temperature, and a total of ±45 ps output Data skew (ADC + Board) and 120 ps for rise and fall times, this is yielding to a minimum available time width for TD1 or TD2 pulses of: 770 ps –200 ps –

45 ps –120 ps = 425 ps (with 50/50 duty cycle).


1076D–BDC–10/12

25

EV10AS150B

2.6.7

Timing Diagram in Simultaneous and Staggered Mode

Figure 2-19. Timing Diagram Simultaneous mode, 1:4 DMUX Ratio

ADC

VIN

ADC CLK

(internal)

N

TA = +350 ps

ADC Pipeline Delay: 4 clock cycles

ADC+1:4 DMUX Pipeline Delay: 7.5 clock cycles on Port A

4 clock cycles: ADC Pipeline Delay

Digital Outputs

( internal )

ADC Data Clock

( internal Fclock/2)

N-4

N

N+1 N+2

N+3 N+4 N+5 N+6

DMUX Even Latches

DMUX Odd Latches

-2

3.5 clock cycles

N

2

1:4 DMUX Pipeline Delay on Port A

4

6

-1

1 3

5

7

Port Select A

Port Select B

Port Select C

Port Select D

N - 1

N - 2

N - 3

N - 4

N

N + 4

N + 1

N + 2

N + 3

N + 5

N + 6

N + 7

DMUX

(internal)

(A0, A0N)...(A9, A9N)

Digital outputs : Port A

(B0, B0N)...(B9, B9N)

Digital outputs : Port B

(C0, C0N)...(C9, C9N)

Digital outputs : Port C

N - 4

N - 3

N

N + 1

N + 2

N+4

N + 5

N + 6

N - 2

(D0, D0N)...(D9, D9N)

Digital outputs : Port D

Clock/4 synchronised on falling edges of Clock

Clock/8 synchronized with output Data on falling edges of Clock

Clock/8 shifted

+ 2 clock cycles

2 Tclock

ADC : 4 cycles

Digital Outputs

Port A, Port B, Port C, Port D

N - 1

2 Tclock

DMUX : 3.5 cycles

N + 3

7.5 clock cycles (ADC+DMUX)

N -8

N -7

N -6

N -5

TOD

N -4

N -3

N -2

N -1

N + 7

Tskew

TD1 TD2

Tskew

Port A : N,

Port B : N+1

Port C : N+2

Port D :

N+3

TDR

(DR, DRN) Data Ready

(in DR/2 mode)

26


EV10AS150B

Figure 2-20. Timing Diagram Staggered mode, 1:4 DMUX Ratio

TA = +350ps

N

N+1

N+2 N+3

A B C D

Pipeline Delay Port A, B ,C ,D : 4.5 clock cycles

VIN

ADC CLK

ADC Pipeline Delay: 4 clock cycles

ADC

(internal)

ADC Digital

Outputs

ADC Data Clock

(Fclock / 2)

N-4

N

N+1 N+2 N+3

N+4 N+5 N+6

DMUX Even Latches

-2

N

2

4 6

DMUX Odd Latches

-1

1 3

5

7

ADC Fclock / 4

DMUX

(internal)

(A0, A0N)...(A9, A9N)

Port Select A

Port Select B

Port Select C

(B0, B0N)...(B9, B9N)

Port Select D

Latches Port A

Latches Port B

(C0, C0N)...(C9, C9N)

Latches : Port C

N - 1

N

N + 4

N - 4

N - 2

N - 3

N + 1

N + 2

N + 5

N + 6

N - 4

N + 3

Port A B C D DMUX Latency : 0.5 clock

N

N+4

N + 7

N - 3

N - 2

N + 1

N + 2

N + 5

N + 6

(D0, D0N)...(D9, D9N)

Port A (N) : 4.5 Clock Cycles

(DRA, DRAN) in DR/2 mode

Latches : Port D

4.5 ADC+DMUX

Data for N

N - 1

TOD1

TDR1

N + 3

N

N + 7

Tskew

TD

1 TD2

N+4

Tskew

Port B (N+1) : 4.5 Clock Cycles

(DRB, DRBN) in DR/2 mode

N+1

4.5 ADC+DMUX

Data for N+1

TOD2

N+1

N+5

TDR2

Port C (N+2 ) : 4.5 Clock Cycles

(DRC, DRCN) in DR/2 mode

N+2

4.5 ADC+DMUX

Data for N+2

TOD3

TDR3

N+2

Port D (N+3 ): 4.5 Clock Cycles

(DRD, DRDN) in DR/2 mode

4.5 ADC+DMUX

TOD4

N+3

Data for N+3

N+3

Digital Outputs & Data Ready Signals for Port A, Port B, Port C, Port D:

Digital Data: after TOD1, TOD2, TOD3, TOD4 ; Data Ready Signals: after TDR1, TDR2, TDR3, TDR4

N+6

Tskew

TD1 TD2

N+7

1076D–BDC–10/12

27


EV10AS150B

2.7

Digital Output Data Coding

Table 2-10.

Digital Output Data Coding Table

Differential analog input

> 250.25 mV

250.25 mV

249.75 mV

125.25 mV

124.75 mV

0.25 mV

–0.25 mV

–124.75 mV

–124.25 mV

–249.75 mV

–250.25 mV

< –250.25 mV

Voltage level

>Top end of full scale + ½ LSB

Top end of full scale + ½ LSB

Top end of full scale – ½ LSB

3

/

4 full scale + ½ LSB

3

/

4 full scale – ½ LSB

Mid scale + ½ LSB

Mid scale – ½ LSB

1

/

4 full scale + ½ LSB

1

/

4 full scale – ½ LSB

Bottom end of full scale + ½ LSB

Bottom end of full scale – ½ LSB

< Bottom end of full scale – ½ LSB

Natural Binary

(2)

MSB……….LSB OR

0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 1 0

0 0 1 1 1 1 1 1 1 1 0

0 1 0 0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1 1 1 0

1 0 0 0 0 0 0 0 0 0 0

1 0 1 1 1 1 1 1 1 1 0

1 1 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 0 0

1 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1 1 1 1

Digital output

Binary 2’s Complement

(2)

MSB……....LSB OR

1 0 0 0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 1 0

1 0 1 1 1 1 1 1 1 1 0

1 1 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0

0 0 1 1 1 1 1 1 1 1 0

0 1 0 0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1 1 0 0

0 1 1 1 1 1 1 1 1 1 0

0 1 1 1 1 1 1 1 1 1 1

Gray Coding

(2)

MSB……..LSB OR

0 1 1 1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1 1 1 0

0 1 1 1 1 1 1 1 1 0 0

0 1 0 1 1 1 1 1 1 1 0

0 0 0 1 1 1 1 1 1 1 0

0 0 1 1 1 1 1 1 1 1 0

1 0 1 1 1 1 1 1 1 1 0

1 0 0 1 1 1 1 1 1 1 0

1 1 0 1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1 1 0 0

1 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1 1 1 1

A9 = B9 = C9 = D9 = MSB

A0 = B0 = C0 = D0 = LSB

Note: 1. Be aware that code 0x000 is obtained for positive full scale analog input and code 0x3FF for negative full scale.

2. Refer to Table 4-9 on page 51

for selection between natural binary, binary two’s complement or Gray coding.

2.8

Explanation of Test Levels

Table 2-11.

Test Levels

1

2

100% production tested at +25

° C

(1)

(for C temperature range

(2)

)

100% production tested at +25

° C

(1)

, and sample tested at specified temperatures for V temperature

ranges

(2)

.

3

4

5

Sample tested only at specified temperature

Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature)

Parameter is a typical value only guaranteed by design only

Only MIN and MAX values are guaranteed (typical values are issuing from characterization results).

Notes: 1. Unless otherwise specified.

2. Refer to

Section 7. ”Ordering Information” on page 72

.

28


EV10AS150B

2.9

Definition of Terms

Table 2-12.

Definition of Terms

(Fs max)

(Fs min)

Maximum Sampling

Frequency

Minimum Sampling frequency

Performances are guaranteed up to Fs max

Performances are guaranteed for clock frequency higher than Fs min

(BER)

(FPBW)

(SSBW)

(SINAD)

(SNR)

(THD)

(SFDR)

Bit Error Rate

Full power input bandwidth

Small Signal Input bandwidth

Signal to noise and distortion ratio

Signal to noise ratio

Total harmonic distortion

Spurious free dynamic range

Probability to exceed a specified error threshold for a sample at maximum specified sampling rate. An error code is a code that differs by more than ± 32 LSB from the correct code.

Analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at Full Scale

–1 dB (–1 dBFS).

Analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at Full Scale

–10 dB (–10 dBFS).

Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale (–1 dBFS), to the RMS sum of all other spectral components, including the harmonics except DC.

Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all other spectral components excluding the ten first harmonics.

Ratio expressed in dB of the RMS sum of the first ten harmonic components, to the RMS input signal amplitude. It may be reported in dBFS (i.e, related to converter Full Scale), or in dBc (i.e, related to input signal level).

Ratio expressed in dB of the RMS signal amplitude to the RMS value of the highest spectral component

(peak spurious spectral component). The peak spurious component may or may not be a harmonic. It may be reported in dBFS (i.e., related to converter Full Scale), or in dBc (i.e, related to input signal level).

(ENOB)

(DNL)

(INL)

(TA)

(JITTER)

(TS)

(ORT)

(TOD)

(TDR)

(TD1)

Effective Number Of Bits

Differential non linearity

Integral non linearity

Aperture delay

Aperture uncertainty

Settling time

Overvoltage recovery time

Digital data Output delay

Data ready output delay

Time delay from Data transition to Data Ready

ENOB =

Where A is the actual input amplitude and FS is the full scale range of the ADC under test

6.02

The Differential Non Linearity for an output code i is the difference between the measured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no missing output codes and that the transfer function is monotonic.

The Integral Non Linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition.

INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.

Delay between the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point), and the time at which (V

IN,

V

INN

) is sampled.

Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the signal at the sampling point.

Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step function is applied to the differential analog input.

Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input is reduced to midscale.

Delay from the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load.

Delay from the falling edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load.

Time delay between Data transition to output clock (Data Ready). If output clock is in the middle of the Data,

TD1 = Tdata/2

1076D–BDC–10/12

29


EV10AS150B

Table 2-12.

Definition of Terms (Continued)

(TD2)

TD1-TD2

(TC)

(TPD)

(TR)

(TF)

(PSRR)

(IMD)

Time delay from Data

Ready to Data

Encoding clock period

Pipeline Delay

Rise time

Fall time

Power supply rejection ratio

Intermodulation

Distortion

Time delay between output clock (Data Ready) to Data transition. If output clock is in the middle of the Data,

TD2 = Tdata/2.

The difference TD1-TD2 gives an information if the output clock is centered on the output data. If output clock is in the middle of the data TD1 = TD2 = Tdata/2.

TC1 = Minimum clock pulse width (high) TC = TC1 + TC2

TC2 = Minimum clock pulse width (low)

Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD).

Time delay for the output DATA signals to rise from 20% to 80% of delta between low level and high level.

Time delay for the output DATA signals to fall from 20% to 80% of delta between low level and high level.

Ratio of input offset variation to a change in power supply voltage.

(NPR)

(VSWR)

Noise Power Ratio

Voltage Standing Wave

Ratio

The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the worst third order intermodulation products.

The NPR is measured to characterize the ADC performance in response to broad bandwidth signals. When applying a notch-filtered broadband white-noise signal as the input to the ADC under test, the Noise Power

Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test.

The VSWR corresponds to the ADC input insertion loss due to input power reflection. For example a VSWR of 1.2 corresponds to a 20 dB return loss (that is, 99% power transmitted and 1% reflected).

30


3.

Pin Description

3.1

Pinout View

Figure 3-1.

EBGA 317 Pinout Table (View from Bottom of the Package)

EV10AS150B

Dam and Fill

(not an exposed pad)

Dam and Fill

(not an exposed pad)

Note: Area in dashed line corresponds to dam & fill (not an exposed pad) e2v semiconductors SAS 2012

1076D–BDC–10/12

31

EV10AS150B

3.2

Pin Description Table

Table 3-1.

Pin Description Table

Signal Name

POWER SUPPLIES

Pin Number

V

CCA5

V

CCA3

V

PLUSD

V

CCD

A24, A26, A27,

B24, B26, B27,

C24, C26, C27,

D24, D26, D27,

E24, E26, F25, L25,

L26, M27, R21,

T21, U21

A25, B22, B25,

C20, C22, C25,

D20, D22, D25,

E20; E22, E25,

F20, F22, F24, K25,

K26, L27, M25,

M26, N26, N27,

R20, T20

C4, C5, C6, C7, C9,

C11, C13, C14,

C15, C16, C19, D5,

D6, D7, D9, D11,

D13, D19, E3, E19,

F19, J3, J4, L3, L4,

N3, N4, R3, R4,

R19, T6, T7, T9,

T11, T13, T14, T15,

T19, U4, U5, U6,

U7, U9, U11, U13,

U14, U15

C3, C8, C10, C12,

D3, D4, D8, D10,

D12, D16, E4, E17,

G3, G4, K3, K4,

R16, T3, T4, T5,

T8, T10, T12, T16,

T17, U3, U8, U10,

U12

Description

Analog 4.9V

Power Supply (ADC)

Analog 3.25V

Power Supply (ADC)

Output 2.5V

Power Supply (ADC and

DMUX)

Digital 3.3V Power Supply

(DMUX)

SUB D14, D15, R17

Substrate connect to Board

Ground Plane (DGND)

DGND

A19, A20, B19,

B20, C17, C18,

D17, D18, E18, F3,

F4, F18, H3, H4,

M3, M4, P3, P4,

R18, T18, U16,

U17, U19, U20

Digital Ground, connect to

Board Ground Plane

Dir.

Equivalent Simplified Schematics

32


Table 3-1.

Signal Name

AGND

Pin Description Table (Continued)

Description Pin Number

B21, B23, C21,

C23, D21, D23,

E21, E23, F21, F23,

F26, F27, G25,

G26, G27, H25,

H26, J25, J26, K27,

N25, P25, R22,

R23, R24, R25,

R26, R27, T22, t23,

T24, T25, T26, T27,

U22, U23, U24,

U25, U26, U27,

V21, V23, V24,

V26, V27, W22,

W25, W26, W27

Analog Ground, connect to

Board Ground Plane

NO CONNECT

DNC B18

Do Not connect (Leave this pin floating)

NC

W1, W18, W17,

W19, V19, W20,

V20, A1, V18, P26,

V22, V25

Pins can be left no connect or grounded.

ANALOG INPUTS

Dir.


V

IN

V

INN

H27

J27

ADC In-Phase Analog input

ADC Inverted-Phase

Analog input

(On chip 2 × 50

Ω terminated, 3V biased)

I

VCCA5

VCCA3

VIN

VINN

ESD

ESD

55 55

40p

ESD

ESD

550 550

AGND

EV10AS150B

6 mA

80

6 mA

1076D–BDC–10/12

33


EV10AS150B

Table 3-1.

Signal Name

CLOCK INPUTS


Pin Number Description

CLK

CLKN

W24

W23

Dir.


ADC Clock Differential

Inputs

(On chip 50

Ω terminated,

3V biased)

I

VCCAS

VCCA3

CLK

CLKN

ESD

ESD

55 55

60p

ESD ESD

550 550

AGND

RESET INPUT

DRR

ASYNCRST

P27

B17

VCCA3

2k 2k 15k

ESD

10k

ADC Data Ready reset

(active High or Low depending on bit D8 of state register at address

0110)

I

DRR

ESD

AGND

10k

10k

VCCD (3.3V ± 5%)

ESD

12K

DMUX Asynchronous

Reset

• Leave floating or connect to V

CCD

for RESET mode

• Connect to Ground for normal mode

I

ASYNCRST

ESD

12K 500

500

12K 4K 4K

DGND (0V)

SUBST (0V)

3K 3K

87

μΑ

34


EV10AS150B

Table 3-1.


Signal Name

DIGITAL OUTPUTS


A0…A9

A0N…A9N

AOR/DRAN

AORN/DRA

B0…B9

B0N…B9N

BOR/DRBN

BORN/DRB

B16, B15, B14,

B13, B12, B11,

B10, B9, B8, B7

A16, A15, A14,

A13, A12, A11,

A10, A9, A8, A7

B6

A6

B5, B4, B3, B2, C2,

D2, E2, F2, G2, H2

A5, A4, A3, A2, B1,

C1, D1, E1, F1, G1

J2

H1

In-Phase Digital Outputs

Port A

LVDS compatible

A0 = LSB, A9 = MSB

Inverted-Phase Digital

Outputs Port A

LVDS compatible

A0N = LSB, A9N = MSB

Port A Out of Range in simultaneous mode or

Port A Data Ready Output

Clock in staggered mode


Port B

LVDS compatible

B0 = LSB, B9 = MSB


Outputs Port B

LVDS compatible

B0N = LSB, B9N = MSB

Port B Out of Range in simultaneous mode or

Port B Output Clock in staggered mode

Dir.


O

O

O

O

O

O

590

100

590

820

μΑ

VPLUSD (2.5V ± 5%)

490 490

1.8K

1.8K

DGND (0V)

55

ESD ESD

ESD ESD

SUBST (0V) out outn

1076D–BDC–10/12

35


EV10AS150B

Table 3-1.

Signal Name

C0…C9

C0N…C9N

COR/DRCN

CORN/DRC

D0…D9

D0N…D9N

DOR/DRDN

DORN/DRD

DR

DRN


Pin Number

M2, N2, P2, R2, T2,

U2, V1, V2, V3, V4

L1, M1, N1, P1, R1,

T1, U1, W2, W3,

W4

V5

W5

V6, V7, V8, V9,

V10, V11, V12,

V13, V14, V15

W6, W7, W8, W9,

W10, W11, W12,

W13, W14, W15

V16

W16

J1

K2

Description


Port C

LVDS compatible

C0 = LSB, C9 = MSB


Outputs Port C

LVDS compatible

C0N = LSB, C9N = MSB

Port C Out of Range in simultaneous mode

Or

Port C Data Ready Output



Port D

LVDS compatible

D0 = LSB, D9 = MSB


Outputs Port D

LVDS compatible

D0N = LSB, D9N = MSB

Port D Out of Range in simultaneous mode or

Port D Data Ready Output


Differential Data Ready

Output Clock

LVDS compatible

CONTROL INPUT FUNCTIONS

RESET

SDATA

SLDN

E27

A23

A21

Reset for fast programming of 3WSI to default values.

Data input of 3WSI

(3 Wires Serial Interface)

Load Enable input of 3WSI

Dir.

O

O

O

O

O

O

O

I

I

I


590

VCCA3

100

590

820

μΑ

VPLUSD (2.5V ± 5%)

490

1.8K

1.8K

DGND (0V)

10k

8k

490

ESD

8k

55

ESD ESD

ESD ESD

SUBST (0V)

19.6k

out outn

SCLK A22 Clock input of 3WSI I

SCLK

SDATA

Reset

SLDN

ESD

AGND

14k

20k

20k

36


EV10AS150B

Table 3-1.

Signal Name



SLEEP A18

Dir.


8K

VCCD (3.3V ± 5%)

1.2K

1.2K

ESD

DMUX SLEEP mode

Enable

Leave floating or connect to V

CCD

for normal mode

Connect to Ground for

SLEEP mode

I

10

Ω = 0

10 K

Ω = 1

RS

DRTYPE

BIST

SLEEP

STAGG

ESD

16K

10K

14K 10K

DGND (0V)

STAGG

DRTYPE

RS

BIST

A17

K1

L2

V17

SUBST (0V)

DMUX Staggered mode

Enable


CCD

for normal mode


STAGG mode

DMUX Output Clock mode selection


DR/2 type


CCD

for DR type

DMUX Ratio mode selection

Connect to Ground for 1:2 ratio


CCD

for 1:4 ratio

DMUX BIST mode


CCD

for normal mode


BIST mode

I

I

I

I

10

Ω = 0

10 K

Ω = 1

RS

DRTYPE

BIST

SLEEP

STAGG

ESD

ESD

SUBST (0V)

8K

VCCD (3.3V ± 5%)

1.2K

1.2K

16K

DGND (0V)

10K

14K 10K

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37


EV10AS150B

Table 3-1.

Signal Name



CLKDACTRL U18

DMUX clock Delay control

(from 1/3 × V

CCD

to 2/3 ×

V

CCD

)

I

Dir.


VCCD (3.3V ± 5%)

ESD

10.0 K 2.3 K 2.3 K

4K 4K

CLKDACTRL

3K 3K

ESD

200 µA

10.0 K

3K 3K

DGND (0V)

SUBST (0V)

CONTROL OUTPUT FUNCTIONS

DIOD E

DIODE ADC W21

ADC Die Junction

Temperature monitoring

I/O

2 protection diodes

1 mA

AGND

Protection

Diodes

38


EV10AS150B

4.

Theory of Operation

4.1

Overview

The EV10AS150B is a 10-bit 2.6 Gsps ADC combined with a 1:4 demultiplexer (DMUX) allowing to lower the output Data stream (10-bit data and one out-of-range bit) by a selectable factor of 2 or 4. (Please note that for maximal operating speed, the DMUX has to be used in 1:4 mode).

The ADC works in fully differential mode from analog input up to digital outputs. The ADC differential

Analog Inputs and Clock Inputs are on chip 100

Ω terminated.

The ADC analog input can be driven in either single ended or differential configuration without significant impact on dynamic performances (SFDR), but slight degradation on THD since the weighting of second and third harmonics are similar in single-ended.

The output Data clock and Digital output data are LVDS logic compatible, and should be 100

Ω differentially terminated (2nH // 2 pF maximum output loading parasitics).

The main functions of the EV10AS150B ADC are digitally controlled via on-chip DACs controlled by 3wire serial interface (3WSI):

• Sampling Delay Adjust, with a tuning range of ~ 120 ps, with a coarse and a fine tuning available (8bit resolution on the fine tuning of ~30 ps).

• Offset Control, ± 20 mV, 8-bit resolution.

• Gain Control, ±0.5 dB, 8-bit resolution

• Delay adjustment between the logical clock and the T/H clock, 0 to 30 ps (5-bit resolution).

• Internal clock duty cycle adjust from 60% to 70% at 2.6 Gsps (5-bit resolution).

• Selectable binary or the Gray coding mode.

• Selectable inversion of MSB for binary two's complement.

• Reset to program quickly all registers to default values.

• NAP (ADC part) mode to save power when device is not used.

The Sampling Delay Adjust function (controlled through the 3WSI) may be used to fine-tune the ADC aperture delay from 0 to 120 ps. The SDA function is very useful when interleaving multiple ADCs.

The output demultiplexing ratio 1:4 or 1:2 can be selected by the means of RS digital control input.

The data outputs are available at the output of the EV10AS150B with two different latency modes:

• Staggered (Low latency): data output on ports A, B, C and D are shifted from one clock cycle between two successive ports.

• Simultaneous: data output on all ports A, B, C and D are aligned.

A Built-In Test (BIST) is provided for quick debug or acquisition setup: activation of checker board like pattern generator.

The ADC junction temperature monitoring is made possible through the DIODE ADC input by sensing the voltage drop across a diode implemented on the ADC close to chip hot point.

The EV10AS150B is delivered in an Enhanced Ball Grid Array (EBGA), suitable for applications subjected to large thermal variations (thanks to its TCE which is similar to FR4 material TCE).

1076D–BDC–10/12

39


EV10AS150B

4.2

Functional Pin Table

Table 4-1.

Name

V

CCA5

V

CCA3

V

CCD

V

PLUSD

AGND

DGND

CLK, CLKN

V

IN

,

V

INN

DRR

ASYNCRST

DR/DRN

A0… A9

A0N…A9N

Functional Pin Table

Function

Analog 4.9V Power Supply

Analog 3.25V Power supply

Digital 3.3V Power supply

Output 2.5V Power Supply

Analog Ground

Digital Ground

ADC clock input signal

ADC Analog Input signal

ADC Data Ready reset

DMUX Asynchronous Reset

Data Ready output clock

Digital Output Data Port A

AOR/DRAN,

AORN/DRA

Out-of-range bit Port A or Data Ready output clock in staggered mode Port A

B0… B9

B0N…B9N

Digital Output data Port B

BOR/DRBN,

BORN/DRB

Out-of-range bit Port B or Data Ready output clock in staggered mode Port B

C0… C9

C0N…C9N

Digital Output data Port C

COR/DRCN,

CORN/DRC

Out-of-range bit Port C or Data Ready output clock in staggered mode Port C

D0… D9

D0N…D9N

Digital Output data Port D

DOR/DRDN,

DORN/DRD

RS

CLKDACTRL

DIODE ADC

Out-of-range bit Port D or Data Ready output clock in staggered mode Port D

DMUX Ratio Selection signal (1:2 or 1:4)

Control signal input for fine tuning of internal ADC Data Clock Delay line.

Diode for die Junction Temperature monitoring (ADC)

Name

BIST

SLEEP

DRTYPE

STAGG

SCLK

SDATA

SLDN

RESET

2

VIN, VINN

CLK, CLKN

DRR

ASYNCRST

SDATA

SLDN

SCLK

RESET

2

CLKDACTRL

VCCA3

3.25V

VCCA5

4.9V

VCCD

3.3V

VPLUSD

2.5V

EV10AS150B

20

20

2

20

2

20

2

2

2

[A0…A9]

[A0N…A9N]

AOR/DRAN,

AORN/DRA

[B0…B9]

[B0N…B9N]

BOR/DRBN,

BORN/DRB

[C0…C9]

[C0N…C9N]

COR/DRCN,

CORN/DRC

[D0…D9]

[D0N…D9N]

DOR/DRDN,

DORN/DRD

DR, DRN

SLEEP

STAGG

RS

BIST

DRTYPE

DIODE ADC

AGND

Function

DGND

Built In output checker board

Pattern generation

DMUX Sleep mode input pin selection signal

Data Ready Output Clock Type selection

(Dual Data Rate DR/2 or DR)

Staggered mode selection for Data outputs (low latency)

3 Wire Serial Interface (3WSI)

Clock input

3 Wire Serial Interface (3WSI) serial Input Data

3 Wire Serial Interface (3WSI) Load

Enable signal (Active low)

3WSI Reset input (force registers default settings).

40


EV10AS150B

4.3

RESETs and ADC Synchronization

There are three reset signals available on the device to start the device properly:

• DRR (Data Ready Reset) is used to reset and synchronize the Data Ready Output Clock of the ADC.

DRR ensures that the first edge of the ADC output Data clock after DRR reset pulse is always a rising edge. This ensures that the first Data for N sampled after ADC reset corresponds to the first acquisition in the DMUX.

• ASYNCRST is an asynchronous reset used to synchronize the DMUX so that the data are outputted on the right order (Port A, then Port B, then Port C and then Port D). It is also necessary to have a deterministic sequence in BIST mode.

• RESET is a signal used to reset (load default settings) the 3 Wire Serial Interface (3WSI), see

Section

4.5.2

.

DRR, RESET and ASYNCRST are mandatory for proper device initialization.

Please refer to the paragraph 5.5 for more information on how to implement these reset functions.

DRR is active high or low depending on bit D8 of state register at address 0110 while ASYNCRST is active high.

It is mandatory to apply ASYNCRST while DRR is active.

2 sequences are recommended depending on the applications.

• Sequence 1: to be used in the case where multiple ADCs synchronization is not needed

1.

Perform a RESET on ADC (DRR active low or high depending on 3WSI settings). Maintain DRR active up to step 4.

2.

While DRR is active, perform an asynchronous reset of the DEMUX (ASYNCRST high).

3.

Release ASYNCRST (ASYNCRST low) (minimum pulse width is 3ns)

4.

Release DRR (minimum DRR pulse width is 3.5ns)

5.

3WSI interface can then be programmed if needed.

During this sequence 1, the clock can be running or not running. But pipeline delay up to ADC outputs will not be deterministic.

• Sequence 2: to be used in the case where multiple ADCs synchronization is needed

1.

Apply a running clock in order to initialize ADC clock path

2.

Stop ADC clock at low level

3.

Perform a RESET on ADC (DRR active low or high depending on 3WSI settings).

4.

Maintain DRR active up to step 7.

5.

While DRR is active, perform an asynchronous reset of the DEMUX (ASYNCRST high).

6.

Release ASYNCRST (ASYNCRST low) (minimum pulse width is 3ns)

7.

Release DRR (minimum DRR pulse width is 3.5ns)

8.

Restart ADC clock

9.

3WSI interface can then be programmed if needed.

With this sequence 2, all ADCs will start on the first rising edge of the clock and they will be synchronized.

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EV10AS150B

Figure 4-1.

Asynchronous Reset Timing Diagram, 1:2 Mode, Simultaneous Mode (Principle of

Operation)

TA = 350 ps

N VIN

CLK

3.5 ns min

DRR

ASYNCRST

3 ns min

A9…A0

B9…B0

DR

(DR mode)

DR

(DR/2 mode)

TOD + 5.5 cycles

N - 2 N N + 2 N + 4

N - 1 N + 1 N + 3 N + 5

Figure 4-2.

Asynchronous Reset Timing Diagram, 1:4 mode, simultaneous mode (Principle of operation)

TA = 350 ps

VIN

CLK

N

3.5 ns min

DRR

3 ns min

ASYNCRST

A9…A0

B9…B0

C9…C0

D9…D0

DR

(DR mode)

DR

(DR/2 mode)

TOD + 7.5 cycles

N - 4

N - 3

N - 2

N - 1

N

N + 1

N + 2

N + 3

42


EV10AS150B

4.4

Control Signal Settings (DMUX)

The SLEEP, RS, STAGG, BIST and DRTYPE control signals use the same input buffer.

SLEEP, STAGG, BIST are activated on Logic Low (10

Ω Grounded), and deactivated on Logic High (10

K

Ω to Ground, or tied to V

CCD

= 3.3V, or left floating).

This is illustrated in Figure hereafter:

Figure 4-3.

Control Signal Settings (SLEEP, RS, STAGG, BIST and DRTYPE)

10

Ω

Control

Signal Pin

10 K

Ω

Control

Signal Pin

Not

Connected

Control

Signal Pin

GND

Low Level (‘0’)

GND

High Level (‘1’)

Table 4-2.

Function

BIST

DMUX Mode Settings - Summary

Logic Level

Electrical Level

Static drive Dynamic drive

(1)

0

1

10

Ω to ground

10 K

Ω to ground

N/C

V(BIST) = V

IL

V(BIST)

≥ V

IH

Description

BIST: Checker board on output data

Normal conversion

0 10

Ω to ground

SLEEP

STAGG

1

0

10 K

Ω to ground

N/C

10

Ω to ground

10 K

Ω to ground

1

RS

0

1

N/C

10

Ω to ground

10 K

Ω to ground

N/C

DRTYPE

0

1

10

Ω to ground

10 K

Ω to ground

Note: 1. Refer to

Table 2-4 on page 7

for logical levels.

V(SLEEP) = V

V(SLEEP)

≥ V

V(STAGG) = V

V(STAGG)

≥ V

V(RS) = V

V(RS)

≥ V

IL

IH

IL

IH

IL

IH

V(DRTYPE) = V

IL

V(DRTYPE)

≥ V

IH

Power reduction mode (the outputs are fixed at an arbitrary LVDS level)

Normal conversion

Staggered mode

Simultaneous mode

1:2 ratio

1:4 ratio

DR/2 mode

DR mode

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43


EV10AS150B

4.4.1

4.4.2

DMUX Ratio

The demultiplexer ratio is programmable thanks to the RS Ratio selection signal.

Table 4-3.

DMUX Ratio Selection Settings

RS

0

1

DMUX Ratio

1:2

1:4

Figure 4-4.

DMUX in 1:2 Ratio

Input Words:

1, 2, 3, 4, 5, 6, 7, 8…

1:2

Output Words:

Port A 1 3 5 7 …

Port B 2 4 6 8 …

Port C Not Used

Port D Not Used

Figure 4-5.

DMUX in 1:4 Ratio

Input Words:

1, 2, 3, 4, 5, 6, 7, 8, 9…

Output Words:

1:4

Port A 1 5 9 …

Port B 2 6 10 …

Port C 3 7 11 …

Port D 4 8 12 …

DMUX Data Ready Output Clock Selection (DRTYPE)

DMUX Data Ready Output Clock is used to latch EV10AS150B output data.

Two modes for the output Data clock rate can be selected (via DRTYPE):

• DR mode: The output data clock frequency is 1/4 th

the ADC Clock frequency (assuming 1:4 DMUX

Ratio), and switches at twice the output data rate. Therefore only the rising edge is considered as active for output data registering (Rising edge of differential output Data clock (DR, DRN) is located at center of the digital data pulse).

• DR/2 mode: The output data clock frequency is 1/8 th

the ADC Clock frequency (assuming 1:4 DMUX

Ratio), the output clock switches at same rate as the digital data. Therefore, both output Data clock rising and falling edges are active for output data registering (Rising and Falling edge of differential output Data clock (DR, DRN) are located at center of the digital data pulse).

This is illustrated in the following figures:

Figure 4-6.

DR Mode

DR

Data Out

Figure 4-7.

DR/2 Mode

DR

Data Out

44


EV10AS150B

4.4.3

Table 4-4.

DMUX Output Clock Type Selection Settings

DRTYPE

1

0

When DRTYPE is left floating, the default mode is DR.

DMUX Output Clock Type

DR

DR/2

DMUX Output Data Mode (STAGG)

Two output modes are provided:

• Staggered: the output data come out of the DMUX the one after the other;

• Simultaneous: the output data come out of the DMUX at the same time.

In staggered mode, the output clock for each port is provided by the DRA, DRAN, DRB, DRBN, DRC,

DRCN and DRD, DRDN signals which corresponds respectively to the AORN, AOR, BORN, BOR,

CORN, COR, DORN and DOR.

The Simultaneous mode is the default mode (STAGG left floating or at logic “1”).

The Staggered mode is activated by the means of the STAGG input (active low).

Figure 4-8.

Simultaneous Mode in 1:4 Ratio (STAGG = 1)

DR

in DR mode

DR in DR/2 mode

Data Out Port A

N

Data Out Port B

Data Out Port C

N + 1

N + 2

Data Out Port D

N + 3

N + 4

N + 5

N + 6

N + 7

Figure 4-9.

Simultaneous Mode in 1:2 Ratio (STAGG = 1)

DR in DR mode

DR in DR/2 mode

Data Out Port A

N

Data Out Port B

N + 1

N + 4

N + 5

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EV10AS150B

Figure 4-10. Staggered Mode in 1:2 Ratio (STAGG = 0)

Data Out Port A

N

DRA in DR mode

DRA in DR/2 mode

Data Out Port B

DRB in DR mode

DRB in DR/2 mode

DR in DR mode

DR

in DR/2 mode

N - 1 N + 1

N + 2

N + 3

Figure 4-11. Staggered Mode in 1:4 Ratio (STAGG = 0)

N

Data Out Port A

DRA in DR mode

DRA in DR/2 mode

Data Out Port B

DRB in DR mode

DRB in DR/2 mode

N + 1

N - 2 N + 2

Data Out Port C

DRC

In DR mode

DRC in DR/2 mode

N - 1

Data Out Port D

DRD in DR mode

DRD in DR/2 mode

DR in DR mode

DR in DR/2 mode

N + 4

N + 3

N + 5

N + 6

46


EV10AS150B

4.4.4

4.4.5

4.4.6

Out-of-range Bit and Data Ready Output Clocks

In simultaneous output mode:

The (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) and

(DOR/DRDN, DORN/DRD) signals are used to add the out-of-range bit to the ADC output data.

On each port (A, B, C, D) the out-of-range bit (*OR/*ORN) indicates (logic “1”) when the analog input overrides the ADC 0.5 Vpp Full Scale voltage span, in case of underflow or overflow.

When the analog input exceeds the positive full scale, the 10 bit digital outputs data remain at high logical state, with (*OR,*ORN) at logical one. When the analog input falls below the negative full scale, the

10 bit digital outputs data remain at logical low state, with (*OR,*ORN) at logical one again.

In Staggered output mode:

The (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) and

(DOR/DRDN, DORN/DRD) signals will output the Data Ready Output Clock signal (one for each port), centered on the corresponding Data.

In this case, the overflow can be computed with all 10 digital output data detection at logic “1”, (binary mode), and underflow can be computed with all 10 digital output data detection at logic “0” (binary mode).

In 1:2 DMUX Ratio, DR/DRN and DRB/DRBN are identical.

In 1:4 DMUX Ratio, DR/DRN and DRD/DRDN are identical.

DMUX Power Reduction Mode (SLEEP)

The power reduction (SLEEP) mode allows the user to reduce the power consumption of the device

(DMUX part in Sleep mode). In this mode, the DMUX part consumption is reduced by 0.9W.

The Power reduction mode is active when SLEEP is low.

The device is in normal mode when SLEEP is high.

When the device is not used, minimal Power consumption is obtained with NAP (ADC part) and SLEEP

(DMUX part) modes used simultaneously.

DMUX Clock input Delay Cell (CLKDACTRL)

A tunable delay cell (CLKDACTRL) is in serial on the 11 Bit DMUX Data path to fine tune the data vs.

clock alignment at the interface between the ADC and the DMUX.

The delay is controlled via the CLKDACTRL pin. This delay can be tuned around default center value. It ranges from –100 ps to 100 ps for CLKDACTRL varying from V

CCD

/ 3 to 2 × V

CCD

/ 3.

This function results in a delayed internal clock signal.

This pin must always be biased and it is recommended to set CLKDACTRL at V

CCD

/3.

With the recommended value, it is normally not necessary to tune the CLKDACTRL voltage over the full specified clock rate, temperature range and power supply voltage range.

Figure 4-12. DMUX Clock Input Cell Block Diagram

CLK/CLKN

CLKDACTRL

2

Delay

(-100 to 100 ps)

2

Internal clock signal

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EV10AS150B

4.4.7

DMUX Built-In Test

The Built-In Self Test allows to test rapidly the DMUX block of the device.

It is activating via the BIST bit (active low) a checker board like pattern generator.

When this signal is left floating, the BIST is inactive.

When in BIST mode, a clock must be applied to the device, which can be set to 1:2 or 1:4 mode. The output clock mode DRTYPE can be either DR or DR/2.

In the BIST mode, all the bits are either all at low or high level (even and odd bits are in phase opposition) and transition every new cycle.

In order to have a deterministic output sequence, it is necessary to perform an asynchronous reset.

The output sequence is then:

Table 4-5.

BIST Output Sequence in 1:4 Mode

BIST sequence Binary (D9 …. D0)

DATA N on Port A

DATA N+1 on Port B

DATA N+2 on Port C

DATA N+3 on Port D

DATA N+4 on Port A

DATA N+5 on Port B

DATA N+6 on Port C

DATA N+7 on Port D

DATA N+8 on Port A

...

10 1010 1010

01 0101 0101

10 1010 1010

01 0101 0101

01 0101 0101

10 1010 1010

01 0101 0101

10 1010 1010

10 1010 1010

...

Table 4-6.

BIST Output Sequence in 1:2 Mode

BIST sequence Binary (D9 …. D0)

DATA N on Port A

DATA N+1 on Port B

DATA N+2 on Port A

DATA N+3 on Port B

DATA N+4 on Port A

...

10 1010 1010

01 0101 0101

01 0101 0101

10 1010 1010

10 1010 1010

...

Hexa (D9…D0)

0x2AA

0x155

0x2AA

0x155

0x155

0x2AA

0x155

0x2AA

0x2AA

...

Hexa (D9…D0)

0x2AA

0x155

0x155

0x2AA

0x2AA

...

Out-of-range Bit

0

1

1

0

0

1

0

...

1

0

Out-of-range Bit

0

1

0

...

1

0

48


EV10AS150B

4.5

ADC 3 Wire Serial Interface (ADC Controls)

4.5.1

3WSI Address and Data Format

The 3WSI is a synchronous write only serial interface made of 3 wires.

This 3 wire bus is activated with the SLDN control pin going low (please refer to “write timing” in next section).

The length of the word is 14 bits: 10 for the data and 4 for the address.

Bit d[9] of Data is MSB and bit a[3] of address is MSB.

The maximum serial logic clock frequency is 100MHz.

4.5.2

3WSI Timing

The 3WSI is a synchronous write only serial interface made of 3 wires:

• SCLK: serial clock input

• SLDN: serial load enable input

• SDATA: serial data input.

Please refer to Table 2-4 on page 7 for logical levels of SLCK, SLDN, SDATA and RESET.

The 3WSI gives a “write-only” access to up to 16 different internal registers of up to 10 bits each.

The input format is fixed with always 4 bits of register address followed by always 10 bits of data.

Address and data are entered MSB first.

The write procedure is fully synchronous with the clock rising edge of SCLK and described in the write chronogram

Figure 4-13 on page 50 .

For proper initialization of 3WSI default settings, an asynchronous reset pulse on pin RESET is required.

The RESET pin combined with the SLDN pin must be used as a reset to program the chip to the “reset setting”.

• RESET high: no effect

• RESET low and SLDN low: programming of registers to default values

SLDN and SDATA are sampled on each rising edge of SCLK clock (clock cycle).

SLDN must be set at “1” when no write procedure is done.

A minimum of one clock rising edge (clock cycle) with SLDN at “1” is required for a correct start of the write procedure.

A write starts on the first clock cycle with SLDN at “0”. SLDN must stay at “0” during the complete write procedure.

In the first 4 clock cycles with SLDN at “0”, 4 bits of register address from MSB (a[3]) to LSB (a[0]) are entered.

In the next 10 clock cycles with SLDN at “0”, 10 bits of data from MSB (d[9]) to LSB (d[0]) are entered.

An additional clock cycle with SLDN at “0” is required for parallel transfer of the serial data d[9:0] in the register addressed with address a[3:0].

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EV10AS150B

This gives 15 clock cycles with SLDN at “0” for a normal write procedure.

A minimum of one clock cycle with SLDN returned at “1” is requested to end the write procedure, before the interface is ready for a new write procedure.

Any clock cycle with SLDN at “1” before the write procedure is completed, interrupts this procedure and no data transfer to internal registers is done.

Additional clock cycles with SLDN at “0” after the parallel data transfer to the register (done at 15 th

consecutive clock cycle with SLDN at “0”) do not affect the write procedure and are ignored.

It is possible to have only one clock cycle with SLDN at “1” between two successive write procedures.

10 bits of data must always be entered even if the internal addressed register has less than 10 bits.

Unused bits (usually MSB’s) are ignored. Bit signification and bit position for the internal registers are

detailed in the Section 4.5.3

.

Figure 4-13. 3WSI Timing Diagram

RESET

SLCK

SLDN

SDATA

Internal

Register

Value

Previous setting Default setting a[3] a[2] a[1] a[0]

11 12

13

14 15 d[2] d[1] d[0]

Table 4-7.

Name

Tsclk

Timings Related to Serial 3 Wire Serial Interface

Parameter

Period of SCLK

Min

10

Twsclk High or low time of SCLK

Tssldn Setup time of SLDN before rising edge of SCLK

Thsldn Hold time of SLDN after rising edge of SCLK

Tssdata Setup time of SDATA before rising edge of SCLK

Thsdata Hold time of SDATA after rising edge of SCLK

Twlreset Minimum low pulse width of RESET

Tdreset

Minimum delay between an edge of RESET and the rising edge of SCLK

2

4

5

4

2

5

10

New Setting

Typ Max

ns ns ns ns

Unit

ns ns ns ns

Note

50


EV10AS150B

4.5.3

3WSI Register Description

Note: Addresses and/or data bits not described herein are not accessible via Graphical User Interface

(GUI).

Table 4-8.

3WSI Settings

Address

0000

0001

0010

0011

0100

Description

Clock Duty Cycle

adjust

(1)

Clock Adjust

(2)

Sampling Delay

Adjust Coarse

(3)

Sampling Delay

Adjust Fine

(3)

Gain Adjust

Offset Adjust

register D4:D0 parameter value

Register D4:D0 parameter value

Register D9:D8 parameter value register D7:D0 parameter value register D7:D0 parameter value register D7:D0 parameter value register D9:D0

Default Value

10000

35/65%

10000

15 ps

10

60 ps

00000000

0 ps

10000000

0 dB

10000000

0mV

0000000000

Recommended

Value

10000

35/65%

11111

+30 ps

Max Value

11111

30/70%

11111

+30 ps

11

90 ps

11111111

Min Value

00000

40/60%

00000

0 ps

00

0 ps

00000000

SDA OFF

(See state register description below)

30 ps

11111111

+0.5 dB

11111111

0 ps

00000000

–0.5 dB

00000000

+20mV –20mV

See description hereafter 0110 State Register

Notes: 1. It is recommended to adjust clock duty cycle at 35/65%

2. It is recommended to adjust clock adjust to +30 ps

3. SDA Coarse & SDA fine: Total possible = total Coarse + total Fine = 90 + 30 ps = 120 ps

Step

0.3%

1 ps

30 ps

120 fs

0.004 dB

156 µV

Table 4-9.

State Register Description

Setting for Address :0110

Mode SDA OFF

Mode SDA ON

Mode binary output

Mode gray output

Two’s complement OFF

Two’s Complement ON

Data Ready Reset (DRR) inactive High

Data Ready Reset (DRR) inactive Low

NAP Mode OFF

NAP mode ON

X

X

X

X

D9

X

X

X

X

0

1

X

0

X

X

D8

X

X

X

1

X

X

X

X

X

X

D7

X

X

X

X

X

X

1

X

X

0

D6

X

X

X

X

X

X

0

X

1

0

D5

X

X

0

X

X

X

X

X

X

X

D4

X

X

X

X

X

X

X

X

X

X

D3

0

1

X

X

X

X

X

X

X

X

D2

X

X

X

X

X

X

X

X

X

X

D1

X

X

X

X

X

X

Comments:

1.

SDA Mode: to take into account the value of the Sampling Delay Adjust register, bit D3 of the state register should be asserted to 1. For applications requiring extremely low clock jitter and no interleaving of several ADCs, it is recommended to assert bits D3 of state register to 0.

2.

NAP mode of the ADC part reduces its power dissipation (in standby mode, both terminations of the differential data output buffers of the ADC are driven at same value).

X

X

X

X

D0

X

X

X

X

X

X

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EV10AS150B

4.5.4

4.5.5

4.5.6

NAP Mode

The NAP mode is controlled via the 3WSI serial interface, reducing the ADC power dissipation by 0.9W.

When the device is not used, minimal Power consumption for the combined ADC and 1:4 DMUX chips is obtained by turning on the NAP mode (on ADC part) and the SLEEP mode (DMUX) simultaneously.

Binary or Gray Output Mode

It is possible for the user to choose between the binary or Gray output data format. Gray coding may be used in order to reduce the effect of BER when occurring, by storing Gray output codes.

Digital Data format selection is made using the 3WSI (default selection is binary), programming the state register at address “0110”.

Binary two’s complement is also available asserting bit D6 at 1 of state register at address “0110”.(only taken in account if bit D5 is asserted at 0, i.e. in binary output mode).

Sampling Delay Adjust Function (SDA) – ADC Interleaving

This function is of most importance for applications based on time interleaving of multiple ADCs, in order to increase the actual sampling rate. In interleaved system the channels relative phasing has to be matched finely to avoid intermodulation spurs. The SDA function is monitored through the 3 Wire Serial

Interface (3WSI), for remote fine alignment of ADC Aperture delays.

The SDA fine tuning has to be done after proper alignment of ADC Gains and Offsets, also monitored by the 3WSI.

A control voltage is applied on the tunable delay line, through embedded control DACs: 2 Bit DAC

(coarse tuning) and 8 Bit DAC (fine tuning). The coarse 2 Bit DAC allows for coarse alignment of the

ADCs aperture delays, with a step (resolution) of 30 ps. The 8 Bit control DACs allows for fine phase alignment of ADCs, with a resolution of 30 ps/256 = 117 fs. This is more than enough for very fine phase alignment of multiple ADCs. Once tuned, the ADCs track each other versus temperature.

It is reminded that the ADC intrinsic jitter is 120 fs rms, (with SDA = OFF).

The sampling delay adjust enables a tuning of the aperture delay of each channel over a range of 120 ps with a first coarse tuning over a range of 90 ps and then a fine tuning on 8 bit over a range of 30 ps for better accuracy of the settings.

It is pointed out that the ADC intrinsic jitter is 120 fs rms if SDA is turned OFF, and becomes 150 fs rms if SDA is turned ON, and 170 fs rms if SDA is fully tuned. This is related to extra delay cells in the sampling clock path, which are bypassed if SDA is OFF. If the SDA is turned on, an amount of + 60 ps extra time delay adds onto the sampling clock path.

For reference, the measured SNR at Fin = 2500 MHz (–1 dBFS) is 50 dB with SDA = OFF, 49.2 dB with

SDA turned on, and 48.5 dB with SDA turned ON and fully tuned.

For optimum dynamic performance (low jitter), it is recommended to disable SDA (Mode SDA OFF).

52


EV10AS150B

Figure 4-14. Programming the SDA Tunable Delay Line Through the 3WSI

SDA Coarse tuning on 2 Bit: 30 ps step

SDA Fine tuning on 8 Bit : 117 fs resolution

4.5.7

SDA = OFF

(ADC Jitter

= 120 fs rms

60 ps

00

SDA = ON

(ADC Jitter

= 150 fs rms

30 ps

01

30 ps

10

SDA = ON

30 ps 30 ps

11

SDA = ON fully tuned

(coarse)

SDA = ON fully tuned

(coarse + fine)

ADC Jitter =170 fs

ADC Gain Control

The 3-Wire bus interface also allows for adjusting the gain by enabling a fine tuning by ±0.5 dB and an

8-bit resolution.

4.5.8

Offset Control

The 3WSI allows to control the offset of the ADC with a tuning range of ± 20mV, and an 8 bit resolution.

An accurate tuning of aperture delay, gain and offset allows to interleave two ADCs with minimum number of external analog components, thus providing an equivalent 5.2 Gsps ADC. Due to matching difficulties of the roll off of the input frequency response beyond 4 GHz, it is not recommended to use the

ADC in interleaved mode for coding of broadband signal beyond 4 GHz.

4.6

Die Junction Temperature Monitoring

A die junction temperature measurement setting is available, for maximum junction temperature monitoring (hot point measurement).

The measurement setup is described in the Figure hereafter:

Note: If not used, DIODE pin can be left floating.

Figure 4-15. ADC Diode for Die Junction Temperature Monitoring Setup

DIOD E

D+

1 nF

Temperature sensor

D-

AGND

Diode pin is provided so that the diode can be probed using standard temperature sensors.

For information, the forward voltage drop (V

DIODE

) across diode component, versus junction temperature,

(including chip parasitic resistance), is given below (I

DIODE

= 1 mA).

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53


EV10AS150B

Figure 4-16. Junction Temperature Versus Diode Voltage for I = 1 mA

Junction Temperature Versus Diode voltage for I = 1mA

890

880

870

860

850

840

830

820

810

800

790

780

770

760

750

740

730

720

710

700

980

970

960

950

940

930

920

910

900

-30 -20 -10 0

y = -1,195x + 911,855

10 20 30 40 50 60 70 80 90

Junction temperature (°C)

100 110 120 130 140

5.

Applications Information

5.1

Bypassing, Decoupling and Grounding

5.1.1

Decoupling capacitor

Globally, the ADC is decoupled following a four row decoupling capacitors strategy, providing adequate decoupling over frequency taking into account the external decoupling: at Evaluation Board and Package surrounding level, and the internal ADC decoupling (transparent for the end-user): at internal

Package decoupling and on chip decoupling level.

ADC external decoupling: typical values

1.

At Evaluation Board incoming level: (1 st

level): the capacitor should be chosen depending on

DC/DC regulator characteristics.

2.

Close to Package surrounding: 2 nd

level: 144 nF per analog supply (V

CCA5

& V

CCA3

), 192 nF for

V

CCD

and 288 nF for V

PLUSD

.

It is recommended to decouple all power supplies to ground as close as possible to the device balls.

ADC internal decoupling: typical values

3.

Inside Package: (3 rd

level): 100 pF per power supply plane to ground plane.

4.

On chip decoupling level: (4th level): nearly 300 pF per power supplies.

54


EV10AS150B

Figure 5-1.

EV10AS150B Decoupling Schema

Level 1: Power management

Capacitor: should be chosen depending on DC/DC regulator characteristics

EV10AS150B

Level 3: Package

Capacitor, ~100 pF

Level 4: On Chip

Capacitor, ~300 pF

5.1.2

Level 2: PCB board

Capacitor, 47 nF // 1nF

Power Supplies Decoupling Schema

Figure 5-2.

Power Supplies Decoupling Schema

EV10AS150B

V

CCA3

V

PLUSD

X3(min)

47 nF

1 nF

AGND

DGND

GND

V

CCA5

V

CCD

X3(min)

47 nF

1 nF

AGND

DGND

GND

GND = common ground plane

1 nF

1 nF

47 nF

X6(min)

GND

47 nF

X4(min)

GND

1076D–BDC–10/12

55


EV10AS150B

5.1.3

5.1.4

V

CCA5

V

CCA5

V

CCA5

V

CCA3

V

CCA3

V

CCA3

V

PLUSD

V

PLUSD

V

PLUSD

V

PLUSD

V

PLUSD

V

PLUSD

V

CCD

V

CCD

V

CCD

V

CCD

Decoupling Capacitors Package Implementation

The table below indicates the pins to pins connected together with a pair of decoupling capacitance

(47 nF // 1 nF).

Table 5-1.

Supply

Decoupling Capacitors Implementation

Total decoupling per supply

144 nF

List of pins to be connected together with 47 nf // 1 nF

A27, A26, A24, B27, B26, B24, C27, C26, C24, D27, D26, D24,

E26, E24, F25

L26, L25, M27

144 nF

288 nF

192 nF

R21, T21, U21

A25, B25, B22, C25, C22, C20, D25, D22, D20, E25, E22, E20, F24,

F22, F20

R20, T20

K26, K25,L27, M26, M25, N26, N27

C19, C16, C15, C14, C13, D19, D13, E19, F19

T15, T14, T13, U15, U14, U13

C11, C9, C7, C6, C5, D11, D9, D7, D6, D5

T11, T9, T7, T6, U11, U9, U7, U6, U5

C4, E3, J4, J3

L4, L3, N4, N3, R4, R3, U4

C12, C10, C8, D16, D12, D10, D8, E17

D4, D3, E4, G4, G3

K4, K3, T4, T3, U3

R16, T17, T16, T12, T10, T8, T5, U12, U10, U8

Decoupling Capacitors PCB Implementation

Figure 5-3.

Decoupling Capacitors PCB Implementation

Package

Evaluation board

(Component side)

Balls

Component and back side traces

1 nF capacitors

Evaluation board

(back side)

Vias

47 nF capacitors

56


EV10AS150B

5.1.5

Power Plane (Analog and Digital)

For performance reasons it is always recommend to use separate supplies for digital and analog circuitry.

The digital supply should only be used for parts placed over the digital ground plane, i.e. all pure digital parts. The analog supply is used for all analog and mixed-signal parts.

Analog supplies

Î V

CCA3

and V

CCA5

Digital supplies

Î V

PLUSD

and V

CCD

V

PLUSD

supply must be isolated from analog supplies

Note: V

PLUSD

supply is dedicated to digital output buffer only

It is important that a digital power plane does not overlap an analog power plane as can be seen on Figure 5-4

a). If this constraint is not respected, this will induce capacitance between the overlapping areas, which is likely to cause RF emissions to pass from one plane to another.

Figure 5-4.

Overlapping of Analog and Digital Power supplies planes

Analog

Digital

Analog VCCA3

Analog VCCA5

Digital VPLUSD

Digital VCCD

Ground

a) Bad

Analog VCCA3

Digital VPLUSD

Ground

Analog VCCA5

Digital VCCD

c) Optimum

Ground b) Correct

Since DGND and AGND are separated on package and chip, a continuous low impedance ground plane can be used for both Digital and Analog ground.

Moreover, power supply pins should be decoupled directly to the ground plane. The ceramic capacitor should be located as close as possible to the IC power pins.

The sampling clock generation circuitry should be considered like analog circuitry and also be grounded and heavily-decoupled to the common digital and analog ground plane. It also should be isolated from noisy digital circuits.

So, the ground plane not only acts a low impedance return path for decoupling high frequency currents but also minimizes RF emissions. Because of the shielding action of the ground plane, the circuit’s susceptibility to external RF is also reduced.

The optimum partitioning for Analog and Digital Power and Ground planes is illustrated in Figure 5-5 on page 59 .

The isolation between FPGA Ground plane and ADC ground plane is recommended but not mandatory, depending on switching noise level which may be injected by FPGA.

1076D–BDC–10/12

57


EV10AS150B

In case of separate ground between ADC and FGPA, they should be DC connected together by a 0 ohm resistor, making use of the parasitic (high resonant) inductance of the resistor element to reject the HF spikes.

This recommendation for optimum isolation must be followed carefully for optimum rejection of Fclk/4 clock spur in 1:4 DMUX mode.

Information regarding partitioning of package level:

DGND is only allocated to Output Buffers of ADC and digital section + Digital output buffers of 1:4

DMUX. AGND ground plane is allocated to ADC only, and needs to be isolated from 1:4 DMUX output buffers switching into 40 differential 100

Ω terminations. Switching Noise is mainly generated by back reflection effects due to L,C parasitics of 100

Ω terminations. This leads to switching noise into V

PLUSD and DGND which gives energy to Fclk/4 clock related spur if fed back to the ADC Ground.

58


EV10AS150B

Figure 5-5.

Analog and Digital Partitioning of Power and Ground Planes for Optimum Isolation

Ground planes

Optional but not mandatory

R=0 Ohm

High resonant

MCM

ADC +

DMUX

Common Digital and

Analog ground plane

Output buffers

FPGA or µC

FPGA Digital

Ground

Power supplies planes

ADC

AGND

DMUX

DGND

MCM package internal ground planes partitioning:

AGND vs DGND

V

CCA5

(5.2V)

V

CCA3

(3.3V)

Analog Power

Supplies

Regulator 1 and 2

MCM

ADC +

DMUX

Output buffers

V

PLUSD

(2.5V)

V

CCD

(3.3V)

Digital Power

Supplies

Regulator 3

FPGA or µC

FPGA Digital

Power

Regulator 4

1076D–BDC–10/12

59


EV10AS150B

5.2

Analog Input Implementation

5.2.1

ADC Analog Input Terminations

The DC analog common mode voltage is provided by ADC and the analog input signal must be used in

AC coupling mode (with a DC blocking capacitor).

The front-end input preamplifier in on chip terminated (100

Ω differential, 50Ω single-ended with accurate thin film TaN resistors with temperature coefficient close to 0

° C), driven by 50Ω controlled impedance lines (100

Ω differential) with the multilayer EBGA317 Package.

This allows flat input Voltage Standing Wave Ratio (VSWR) over frequency, (< 1.25:1 measured for packaged ADC, from DC up to 3 GHz (less than 1.3% of incoming power reflected from the ADC input, <

0.05 dB transmission loss), and < 1.5:1 from 3 GHz to 5 GHz Full power input bandwidth of the ADC

(less than 4% of power reflected from ADC input, < 0.17 dB transmission loss).

The low input VSWR together with the 5 GHz (–3 dB) full power input Bandwidth of the ADC, allows operation up to the 3 rd

Nyquist region (including L_Band and S_Band) with negligible carrier level fluctuations related to packaged ADC input impedance deviation from ideal Z = 50

Ω (including package parasitics).

The on-chip terminations (in-phase V

I N

and inverted phase V

I N N

) are actually based on a resistive voltage splitter of 55

Ω + 550Ω biased under +3.3V to ground, providing proper 50Ω termination

(550 // 55 = 50), together with 3V internal DC common mode biasing. Since the internal analog input DC common mode is +3V, the differential Analog inputs must be driven through high resonant (> 5 GHz) DC blocking capacitors.

Driving the EV10AS150B in single-ended for ADC Full Scale voltage span:

If single-ended driven, the applied in-phase (V

IN

) input voltage amplitude for ADC full-scale voltage span is 0.5V peak-to-peak, (i.e. –2 dBm Full Scale input power into 50

Ω on-chip termination.)

For proper symmetric input impedance matching, the inverted phase input (V

INN

) must be externally terminated by 50

Ω to Ground through a DC blocking chip capacitor. The inverted phase (V

INN on-chip 50

Ω terminated and biased the same way as the in-phase analogue input.

) is internally

Driving the EV10AS150B in differential for ADC Full Scale voltage span:

If entered in differential, each analog input (in-phase V

IN

and inverted phase V

INN

) shall be entered with

±0.125V peak = 0.25V peak-to-peak amplitude, to comply with 0.5V ADC Full Scale voltage span.

Since the 0.5Vpp Full Scale input voltage span is applied onto 100

Ω termination instead of 50Ω, the ADC

Full Scale differential input power into 100

Ω loading is –5 dBm instead of –2 dBm into 50Ω if singleended driven.

Low cost low profile sub-miniature unbalanced to balanced transformers (baluns) are commercially available, designed specifically for driving differential inputs and/or output locations for fast sampling ADCs in the GHz range. These baluns are providing 50

Ω impedance on unbalanced input, and 100Ω impedance on the balanced differential output port, making it easy to use on surface mount application boards to drive AC coupled differential Analog inputs and clock inputs.

For optimum SFDR performance, the maximum phase balance shall not exceed 12 degree and less than 1.5 dB for amplitude balance, over the entire band of operation. For example, for operation over the

2 nd

Nyquist region at 2.6 Gsps, baluns featuring less than 6 degree Phase Balance and 1 dB amplitude

Balance within a band of operation of 1.6 GHz to 3 GHz are available (for roughly 1 dB insertion loss).

Baluns covering a larger band of operation (e.g. 400 MHz to 3000 MHz) with 12 degrees max Phase unbalance and 1.5 dB Amplitude Balance are also convenient.

60


EV10AS150B

Since the ADC tolerates up to 12 degrees of phase unbalance without impacting the dynamic performance (SFDR), it is not mandatory to use cascaded (double) transformer to improve phase balance characteristics. Double transformer implementations may degrade the inherent band flatness of the device with additional insertion loss.

Figure 5-6.

ADC Full Scale Single Ended vs. Differential Analog Input

Vin = 500 mVpp

ADC Full Scale

Single ended

+ 250 mVp

-

Vin = 500 mVpp

ADC Full Scale

Differential

VIN

+125 mV

VINN

VINN (DC = +3V)

+ 500 mVpp

+ 250 mV - 250 mV

5.2.2

Full Scale input power:

0.5 Vpp into 50

Ω = -2 dBm

Full Scale input power:

0.5 Vpp into 100

Ω = -5 dBm

Differential Versus Single-ended Input Dynamic Performance (SNR, SFDR, THD)

The EV10AS150B implements a front-end Track and Hold preamplifier which has been designed in order to be entered either in differential or single-ended, up to maximum operating sampling rate without significant loss in dynamic performance in either 1 st

and 2 nd

Nyquist for large signals close to ADC Full

Scale:

Same SNR values are measured in single-ended and differential, 1 st

and 2 nd

Nyquist (delta SNR <

0.2 dB).

Regarding linearity performance (Total Harmonic Distortion (THD) and Spurious Free Dynamic Range

(SFDR)):

• If differential driven, it is the odd Harmonics (mainly H3) which mainly dictates the ADC large signal linearity performance (SFDR and THD), whereas the even harmonics (H2, H4, …) only little contributes to THD.

• In single-ended driven, the even harmonics (H2, H4, …) will become significant with the same weighting as the odd Harmonics (H3,H5,…). The 2 nd

Harmonic will rise to the same level as 3 rd

Harmonic, mainly in the 2 nd

Nyquist.

The EV10AS150B front-end preamplifier has been boosted to maintain the 2 nd

Harmonic (H2) level below –60 dBFS in single-ended over 1 st

and 2 nd

Nyquist, even for large signals close to ADC Full

Scale. Since the 2 nd

harmonic weighting is not higher than the 3 rd

Harmonic level (H3), the SFDR performance will not be impacted.

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61


EV10AS150B

5.2.3

However, the THD will be somewhat impacted, since the harmonics are RSS summed since even and odd harmonics have now similar weightings in single-ended:

The THD is slightly impacted by –1 dB in the 1 st

Nyquist, and –2 dB in the 2 nd

Nyquist (Fin < 3000

MHz).

In the 3 rd

Nyquist for large signals close to ADC Full Scale, (e.g. Fin = 4000 MHz, –1 dBFS), the 2 nd

Harmonic impact on THD in single-ended will become much more important (H2 = + 6 dB versus differential mode):

Therefore in the 3 rd

Nyquist, it is highly recommended to drive the inputs in differential for optimum

Spurious Free Dynamic Range (SFDR) and optimum total harmonic distortion performance (THD).

Note: For THD computation, the 10 1 st

low rank harmonics are taken into account.

Differential versus Single-ended Input: Rejection for Fclk/4 Spurs

If the 1:4 DMUX Ratio is selected, the rejection of the Fclk/4 clock related spur becomes an issue since the clock spur is located at the middle of the Nyquist zone.

With 1:2 DMUX Ratio, the clock related spur is located at Fclk/2, and does not affect the center of the band of operation.

The rejection of Fclk/4 becomes 6 dB more efficient if the ADC is differentially driven. (A delta of –6 dB is measured in differential vs. single-ended for the Fclk/4 level).

On EV10AS150B evaluation board, the measured Fclk/4 level is:

• –72 dBFS in single-ended, corresponding to –74 dBm with –2 dBm Full Scale input power (0.5Vpp in

50

Ω).

• –78 dBFS in differential, corresponding to –82 dBm with –5 dBm Full Scale input power (0.5Vpp in

100

Ω).

The ADC has been carefully implemented at chip layout level and packaging level to ensure maximum electric isolation between the noisy Digital output buffers Section and Analog sections of the ADC. (Analog sections include the logic section and the timing circuitry of the ADC).

At application board level:

The absolute value for Fclk/4 in either single-ended or differential mode can be even further improved by improving the electric isolation of the +2.5V power supply: The +2.5V Power plane dedicated to the 40

Digital Output Buffers drives most of the Fclk/4 switching noise energy, and has to be isolated from the other remaining power supplies.

Refer to Figure 5-5 on page 59 for board layout recommendation for optimum isolation.

5.3

Clock Input Implementation

The EV10AS150B differential clock input buffer is based on fast regeneration amplifiers, in order to feature a square wave like sampling clock for the Track and Hold, featuring very fast internal slew-rates to ensure low internal sampling jitter.

The EV10AS150B differential clock input buffer is on-chip 100

Ω terminated (50Ω on each single-ended clock input).

The clock input buffer is biased in the same way as the differential analog input preamplifier:

The differential on-chip clock inputs terminations are based on resistive 55

Ω + 550Ω voltage splitter biased under +3.3V to Ground, providing 5

Ω impedance (550Ω // 55Ω = 50Ω) together with 3V internal

DC common mode biasing for both inputs.

62


EV10AS150B

5.3.1

Driving the EV10AS150B with a Sinewave Clock Input

The SNR rolloff in the high input frequency region (2 nd

and 3 rd

Nyquist) is dictated by sampling jitter:

The ADC sampling jitter is 120 fs rms, to be RSS summed with external sampling clock jitter:

To achieve optimum SNR in the 2 nd

& 3 rd

Nyquist (e.g; SNR > 48 dB at Fin = 3000 MHz, the external clock sinewave requirements are mainly two-fold:

The external sinewave clock signal phase noise and clock signal slew-rate.

The Single Side Band (SSB) phase noise floor of the reference sinewave clock signal shall not exceed

155 dBc/Hz (at 1 MHz from carrier).

The slew-rate of the 2.6 GHz clock input shall not be lower than 5 GV/s at 2.6 GHz frequency.

Accordingly, at 2.6 GHz sampling clock frequency, a sinewave clock input can be directly entered provided the sinewave amplitude is 0.632 Vpp minimum into the 100

Ω differential output to ensure 5 GV/s minimum slew-rate, and 155 dBc/Hz phase noise floor.

Sinewave Clock slew-rate effect on SNR:

Due to very fast internal slew-rates of regeneration stages, a sinewave clock can be entered without impacting the SNR so far the sinewave slew-rate is higher than 5 GV/s minimum (8 GV/s recommended).

These fast slewing front-end clock buffer regeneration stages provides lowest internal rms time domain jitter, as illustrated by the following relationship:

Rms(time jitter) = Rms(voltage noise) / Rms(slew-rate)

Assuming the ADC clock input is driven by a transformer (single-ended unbalanced 50

Ω to balanced

100

Ω differential), the minimum clock input power shall not be lower than –3 dBm into 50Ω input impedance = 0.45 Vpp at transformer input yielding 0.45 Vpp.SQRT(2) = 0.632 Vpp across 100

Ω differential outputs applied to the ADC.

A minimum swing of 0.632 Vpp at 2.6 GHz corresponds to a minimum slew-rate of nearly 5.2 GV/s.

Therefore, the 2.6 GHz external sinewave clock signal voltage amplitude applied across the 100

Ω termination shall not be lower than 0.632 Vpeak to peak for optimum SNR performance in the 1 st

and 2 nd

Nyquist.

For sinewave clock frequencies lower than 2.6 GHz, the sinewave amplitude shall be increased accordingly, to preserve the minimum slew-rate of 5 GV/s, without exceeding 2 Vpp maximum operating amplitude applied to the differential clock input. For example, with a 1.3 GHz sinewave clock, to keep the same slew-rate of 5 GV/s, the minimum voltage amplitude to be applied to the ADC clock input shall not be lower than 2 × 0.632 Vpp = 1.264 Vpp across the 100

Ω differential clock inputs, corresponding to + 3 dBm into 50

Ω transformer input (which is twice the clock input power of a 2.6 GHz sinewave input).

Typical recommended clock input power for a 2.6 GHz sinewave clock for optimum SNR over full temperature range shall be +1 dBm into 50

Ω transformer input impedance, which corresponds to 0.710

Vpp.SQRT(2) = 1 Vpp across 100

Ω across differential outputs applied to the ADC clock inputs. This corresponds to a slew-rate of 8.16 GV/s at 2.6 GHz.

Therefore, typical recommended slew-rates to ensure flat SNR over operating temperature range shall be in the range of 8 GV/s.

Maximum operating clock input power shall not exceed + 7 dBm, which corresponds to 2 Vpp on differential 100

Ω clock input. This corresponds to slew-rates of 15.7 GV/s.

1076D–BDC–10/12

63


EV10AS150B

Maximum ratings for differential clock input is 3 Vpp which corresponds nearly to +11 dBm maximum clock input power.

Sinewave Clock Phase noise vs. time domain jitter effect on SNR rolloff at high input frequencies:

The SNR due to ADC intrinsic clock jitter contribution only (i.e. 120 fs rms), excluding external clock source jitter (jitter free external clock source), is 50 dB at Fin = 2500 MHz, –1 dBFS.

Taking into account the external clock source time domain jitter contribution on SNR performance, the

ADC intrinsic clock jitter of 120 fs rms has to be RSS summed to the external rms clock jitter, yielding to total sampling clock Jitter:

For example with a 100 fs rms external clock source jitter, the total sampling clock jitter will be

SQRT(120

2

+ 100

2

) = 156 fs rms.

With a 120 fs rms clock source jitter, the total jitter will be 170 fs rms:

For the EV10AS150B, the measured SNR at Fin = 2500 MHz for –1 dBFS analog input amplitude is

50 dB with a jitter free external clock source, (taking only into account the ADC intrinsic jitter of 120 fs rms). With 120 fs rms external clock source time domain jitter RSS summed with the 120 fs rms intrinsic

ADC clock jitter, (leading to 170 fs rms total jitter), the measured SNR becomes 48.5 dB.

Relationship between sinewave clock source phase noise and time domain jitter:

The 100 fs rms external time domain jitter corresponds approximately to an external sinewave clock source with (white) phase noise floor spectral density of 155 dBc / Hz, integrated from 1 MHz up to

5.5 GHz:

The 5.5 GHz upper limit of integration corresponds to the ADC clock input bandwidth. The 1 MHz lower limit of integration corresponds to the flat section of white phase noise, excluding 1/f and close in phase noise contribution for 1 st

order calculations.

The integration bandwidth for the phase noise floor is taken from 1 MHz up to 5.5 GHz ADC clock input bandwidth, leading to:

Integrated SSB phase noise floor spectral density: 155 dBc/Hz, 1 MHz to 5.5 GHz:

–155 dB + 10.log(5.5.10

9

–1.10

6

) = –155 + 97.4 dB = –57.6 dB.

This corresponds to the Single Side Band (SSB) phase noise power spectral density 10.log(Rad

2

/Hz) expressed in dBc/Hz, integrated over nearly 5.5 GHz. The total integrated Double Side Band phase noise power expressed in radian (rms) is:

SQRT (2.10

–57.6 / 10

) = 1,86.10

–03

radians (rms).

In time domain, the rms jitter is obtained by dividing the total phase noise power (radians rms) by the carrier frequency.

For example, with a 2.6 GHz sinewave clock carrier, the time domain jitter will be 1,86.10

–03

radians

(rms) / 2.

π.2,6 GHz = ~ 114 fs rms

Therefore for a given constant phase noise floor, the external clock source time domain jitter will be slightly better when increasing clock frequency (due to faster signal slew-rate).

64


EV10AS150B

The 1/f phase noise contribution from 10 KHz to 1 MHz can be neglected so far the mean noise level in this region is below 130 dBc / Hz:

Integrated SSB mean phase noise spectral density: 130 dBc/Hz, 10 KHz to 1 MHz:

–130 dB + 10.log(10

6

–10

4

) = –130 + 60 dB = –70 dB

Integrated double SSB phase noise power in radians (rms):

SQRT(2.10

–70 / 10

) = 0,447.10

–03

radians (rms)

To be compared with 1,86.10

–03

radians (rms) 155 dBc/Hz phase noise integrated over 5.5 GHz. The total RSS summed phase noise from 10KHz to 5.5 GHz is:

SQRT ((1,86.10

–03

radians)2 + (0,447.10

–03

radians)

2

) = 1,91.10

–03

radians

Therefore the close-in phase contribution remains negligible. The close-in phase noise (1/f2 and 1/f3) contributions can also be neglected since this type of phase noise is related only to long term jitter drift effects which are not of concern here regarding the registration length of the Digital Data.

For example, considering the registration length time window for a 32K FFT at 2.6 Gsps:

32768x385 ps = 12.616 µs, corresponding to 79.3 KHz.

As a result, the close-in phase noise below 70 KHz has not to be taken into account for the integration.

As a conclusion, considering a phase noise floor between 1 MHz and 5.5 GHz, any clock source phase noise floor better than 155 dBc/Hz will improve somewhat the SNR:

For example, a 160 dBc/Hz phase noise clock source will feature only 67 fs rms time domain jitter for a

2.6 GHz carrier, and a 165 dBc/Hz clock source will feature only 38 fs rms.

In these cases, the external clock source contribution to total jitter will be negligible, compared to the 120 fs rms intrinsic jitter of the ADC, and SNR performance in the 2 nd

and 3 rd

Nyquist will be improved.

Better SNR performance over frequency will then necessarily go through the improvement of intrinsic

ADC jitter (< 50 fs rms for instance).

On the other hand, using a lower performance phase noise floor sinewave source will cause extra rolloff of the SNR in 2 nd

Nyquist region.

Example: 150 dBc/Hz phase noise will feature a time domain jitter of 188 fs rms time domain jitter for a

2.6 GHz carrier, and a 145 dBc/Hz phase noise will feature 375 fs rms time domain jitter at 2.6 GHz.

Therefore the impact on SNR (and therefore ENOB performance) for very high analog input frequencies is no more negligible against ADC intrinsic jitter, and the SNR performance will be impacted in these cases.

As a conclusion, the recommended phase noise floor shall be at least 155 dBc / Hz for optimum SNR performance over multiple Nyquist zones. Any improvement in phase noise floor will help to save a few dBs especially in the 2 nd

and 3 rd

Nyquist zones.

Note: If a fixed clock source can be used, (i.e.: non swept clock), the sinewave clock source can be band-pass filtered to further improve the phase noise floor.

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65


EV10AS150B

5.3.2

Driving the EV10AS150B with a Square Wave Differential Cock Input

If the clock input signal is a square wave, the incoming signal slew-rate becomes independent to signal amplitude and frequency:

So far the slew-rate of the square clock signals is constant and controlled (> 5 GV/s), the SNR performance of the ADC will be independent to clock signal frequency and amplitude.

Consequently with square wave clock signals, much lower signal amplitudes and frequencies can be entered to the ADC as with sinewaves. With square waves, the SNR performance will be mainly dependant on time domain jitter, which shall remain below 100 fs rms, to ensure optimum SNR performance especially in the 2 nd

and 3 rd

Nyquist as detailed in the previous sections.

With a square wave clock input, a minimum amplitude of ±125 mV peak = 250 mVpp can be entered without impact on linearity (SFDR and THD) and SNR. LVDS logic compatible and LVPECL logic compatible clock inputs can therefore be used to drive the EV10AS150B ADC clock input, so far the time domain jitter of the square wave is < 100 fs rms, and slew-rate is > 5GV/s. So it is not actually the rise/fall time of the square wave clock signals which are of interest, but the actual Slew-rate of the clock edges.

For LVPECL square wave clock input featuring a typical rise time (20% to 80%) of 75 ps for 800 mV voltage swing, the corresponding signal slew-rate is roughly 500 mV/75 ps = 6.6 GV/s, which is convenient.

In addition to that, the time domain jitter shall be < 100 fs rms. (e.g.: 70 fs rms).

LVDS and/or LVPECL compatible low jitter regeneration signals Buffers are commercially available, featuring less than 100 fs rms time domain jitter.

Of course, the sinewave to square wave regeneration buffers shall be driven by a low phase noise sinewave reference clock source (> 155 dBc/Hz), as stated in the previous sections:

The additional jitter due to the square wave regeneration circuitry has then to be RSS summed to the driving sinewave signal time domain jitter (e.g.: 100 fs rms time domain jitter which are achieved by a

155 dBc/Hz sinewave clock source will have to be RSS summed with a 70 fs rms square wave jitter, yielding to SQRT(100

2

+ 70

2

) = 122 fs rms total external jitter (sinewave & square wave)).

In these conditions, the SNR performance of the ADC will be nearly 49 dB at Fin = 3000 MHz, (–1 dBFS at 2.6 Gsps). It is reminded that an SNR of 50 dB at (3000 MHz, –1 dBFS) is achieved if the external clock source jitter contribution can be neglected, only taking into account the 120 fs rms intrinsic sampling clock jitter of the ADC, assuming ideal (jitter-free) external clock sources with ultra fast slew-rates

(> 10 GV/s).

Note 1: ADC Minimum sampling clock frequency:

The square wave clock input frequency shall not be lower than 500 MHz minimum, to avoid SNR and

THD rolloff due to front-end Track and Hold droop rate. Recommended minimum value for clock frequency over temperature is 1 GHz to avoid any roll-off in dynamic performance.

Note 2: ADC SNR performance at low analog input frequencies:

The sampling clock jitter effect on SNR is negligible at low input frequencies (oversampling conditions).

The SNR performance for low input frequencies is mainly dictated by the ADC front-end Track and Hold input referred thermal noise integrated over the 5 GHz Analog input Bandwidth (times

π/2 assuming 1 st order rolloff).

The measured SNR in oversampling conditions is 54 dB.

The ADC deviation from ideal quantification noise (Differential Non Linearity: DNL) on SNR performance is negligible compared to input referred thermal noise:

The measured Differential Non Linearity (DNL) is < 0.5 LSB peak (= 0.2

LSB

rms) at 2.6 Gsps 1 st

and 2 nd

Nyquist, which is the same order of magnitude as quantification noise Q/SQRT(12).

66


EV10AS150B

Note 3: Effect of 3WSI SDA (Sampling Delay Adjust) tunable delay line on ADC intrinsic jitter

The previous assumptions are made with ADC intrinsic clock jitter = 120 fs rms, which is assuming the sampling clock adjust is de-activated (SDA OFF), which is the case by default setting at ADC Reset.

If multiple ADCs need to be interleaved, the respective Aperture delays of the ADCs need to be carefully aligned, and fine tuned with the “SDA” function monitored by the 3 Wire Serial Interface (3WSI), by activating the SDA function (SDA ON).

Turning “ON” the SDA will activate an internal tunable delay line in serial with the sampling clock path,

(which is bypassed if SDA is turned OFF). By turning ON the SDA, the ADC intrinsic jitter becomes 150 fs rms (with minimum delay), since some additional extra delay cells will contribute to jitter, which will slightly impact the SNR performance by 1 dB at Fin = 2500 MHz. (50 dB with SDA turned OFF, and 49 dB if SDA is turned ON). If SDA is turned ON and fully tuned (maximum delay), the ADC intrinsic jitter becomes 170 fs rms.

Refer to chapter 4.6.6. for more information about Sampling Delay Adjust function.

5.4

LVDS Output Implementation

Output Data, Output Clock (Data Ready) and out-of-range bit are LVDS signals that needs to be 100

Ω differentially terminated.

Output data:

• In-phase (Ai) and inverted phase (AiN) digital outputs on DEMUX Port A (with i = 0…9)

• In-phase (Bi) and inverted phase (BiN) digital outputs on DEMUX Port B (with i = 0…9)

• In-phase (Ci) and inverted phase (CiN) digital outputs on DEMUX Port C (with i = 0…9)

• In-phase (Di) and inverted phase (DiN) digital outputs on DEMUX Port D (with i = 0…9)

A0, B0, C0, D0 are the LSB, A9, B9, C9, D9 are the MSB

Output Clock (Data Ready)

• In-phase DR and inverted phase DRN.

• In-phase DRA and inverted phase DRAN on DEMUX Port A used in staggered mode.

• In-phase DRB and inverted phase DRBN on DEMUX Port B used in staggered mode.

• In-phase DRC and inverted phase DRCN on DEMUX Port C used in staggered mode.

• In-phase DRD and inverted phase DRDN on DEMUX Port D used in staggered mode.

Out of Range

• In-phase AOR and inverted phase AORN on DEMUX Port A used in simultaneous mode.

• In-phase BOR and inverted phase BORN on DEMUX Port B used in simultaneous mode.

• In-phase COR and inverted phase CORN on DEMUX Port C used in simultaneous mode.

• In-phase DOR and inverted phase DORN on DEMUX Port D used in simultaneous mode.

Each of these outputs should be terminated by 100

Ω differential resistor placed as close as possible to the differential receiver (inside receiver is even better).

In 1:2 DMUX Ratio the unused Output Data and out-of-range bit (Port C and D) could be leave floating without 100

Ω differential resistor.

1076D–BDC–10/12

67


EV10AS150B

Figure 5-7.

Differential Digital Outputs Terminations (100

Ω LVDS)

EV10AS150B

Output Data

Z0 = 50

Ω

Data Out

Differential Output buffers

Data OutN

Z0 = 50

Ω

100

Ω Termination

To Load

5.5

DRR and ASYNCRST Implementation

FPGA outputs can be directly connected to ADC DRR and ASYNCRST inputs.

Figure 5-8.

DRR and ASYNCRST Signals Implementation

FPGA

EV10AS150B

DRR

D0

D1

Note: Take care of signal integrity to avoid parasitic transitions.

ASYNCRST

68


EV10AS150B

6.

Package Description

6.1

Package Outline

Figure 6-1.

EBGA 317 Package Outline

8

A1 Corner

Ni Plated

A4

DETAIL A

SIDE VIEW

DETAIL A

D

TOP VIEW

A

E

B e

A2

A1

DETAIL B

E1

27

26 24

25

22

23

20

21

18

19 17

16 14

15

12

13

10

11 9

8

7

6

5

4

3

2

1

A

C

E

G

B

D

F

J

H

K

L

N

R

M

P

U

W

T

V

REF.

DIMENSIONAL REFERENCES

MIN.

NOM.

A

A1

A2

A4

D

D1

E

E1 b

1.25

0.50

0.75

0.10

34.80

24.80

0.60

1.45

0.60

0.85

35.00

33.02 (BSC.)

25.00

22.86 (BSC.)

MD

ME

N bbb

0.75

27

19

317 ddd e

Q

0.25

1.27 TYP.

MAX.

1.65

0.70

0.95

35.20

25.20

0.90

0.25

0.20

D1

BOTTOM VIEW

Q

A

DETAIL B e bbb C

Q b (Nx PLACES)

4

0.30

M

0.15

M

C

C

A B

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. "e" REPRESENTS THE BASIC SOLDER BALL GRID PITCH.

3. "MD" AND "ME" REPRESENTS THE BASIC SOLDER BALL MATRIX SIZE IN

"D" AND "E" DIRECTION RESPECTIVELY, AND SYMBOL "N" IS THE

MAXIMUM ALLOWABLE NUMBER OF BALLS AFTER DEPOPULATING.

4. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER

5.

PARALLEL TO PRIMARY DATUM C .

DIMENSION "ddd" IS MEASURED PARALLEL TO PRIMARY DATUM C .

6. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE

SPHERICAL CROWNS OF THE SOLDER BALLS.

7. PACKAGE SURFACE SHALL BE Ni PLATED.

8. BLACK SPOT FOR PIN 1 IDENTIFICATION.

9. ENCAPSULANT SIZE MAY VARY WITH DIE SIZE.

10. "A4" IS MEASURED AT THE EDGE OF ENCAPSULANT TO THE INNER EDGE

OF BALL PAD.

11. DIMENSIONING AND TOLERANCING PER ASME Y14.5 1994

12. THE OUTLINE DIMENSION IS REFERENCE TO JEDEC MS034.

13. FOR QUALIFICATION PURPOSE ONLY.

C

SEATING PLANE 6 ddd C

5

1076D–BDC–10/12

69


EV10AS150B

6.2

Land Pattern Recommendation

Figure 6-2.

EBGA 317 Land Pattern Recommendation

TOP VIEW

A

B

D e

BOTTOM VIEW

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12 10 8

11 9 7

6

5

4

3

2

1

N

P

R

T

U

W

V

A

B

C

D

E

G

F

H

J

K

L

M

E

C

Note: Not solder PADS

LAND PATTERN

RECOMMENDATIONS

E

A B C D E e b

25.00

35.00

0.85

22.86

33.02

1.27

0.60

b

D e

All dimensions are in millimeters

70


EV10AS150B

6.3

Thermal Characteristics

As there is no JEDEC standard definition for the thermal resistance applied to a multi-die device, only the thermal resistance for each die (ADC block powered ON only or DMUX block powered ON only) is provided.

All results were computed with ANSYS thermal simulation tool and with the following assumptions:

• Half geometry simulation

• ADC heating zone = 1.9 × 1.9 mm

2

• MUX heating 4.0 × 4.0 mm

2

• No air, pure conduction, no radiation

• ADC block ~ 4.0W

• DMUX block ~ 2.2W

6.3.1

Table 6-1.

Thermal Resistor

ADC block ON only

DMUX block ON only

Rth junction to bottom of balls

7

° C/W

3.9

° C/W

Note: 1. Assumed board size = 53 × 43 mm².

Rth junction to

Top of Case

4.1

° C/W

1.5

° C/W

Rth junction to

Board

(1)

8

° C/W

4.9

° C/W

Rth junction to ambient

17.1

° C/W

13.9

° C/W

Thermal Management Recommendations

In still air and 25

° C ambient temperature conditions, the maximum temperature of 106° C + 25° C

= 131

° C is reached for the ADC block. It is consequently necessary to manage heat from the

EV10AS150 very carefully to avoid permanent damages of the device due to over temperature operation.

In no air cooling conditions, an external heatsink must be placed on top of package. An electrical isolation may be necessary as the TOP of the package is at ground potential.

It is advised to use an external heatsink with intrinsic thermal resistance better than 4

° C/Watt when using air at room temperature 20–25

° C. At 60° C, the external heatsink should have an intrinsic thermal resistance better than 3

° C/Watt.

Figure 6-3.

EV10AS150B-EB Evaluation Board Heat Sink Outlines

35 x 35 x 18 heat sink

Thermal conductive foil both sides

Note: ADC performance is improved at higher temperature.

1076D–BDC–10/12

71


EV10AS150B

6.4

Moisture Characteristics

This device is sensitive to the moisture (MSL3 according to JEDEC standard). Its shelf life in sealed bag is 12 months at < 40

° C and < 90% relative humidity (RH).

Once the bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temp. 260

° C for ROHS versions and 220° C for non ROHS versions) must be:

• Mounted within 168 hours at factory conditions of

≤ 30° C/60% RH, or

• Stored at

≤ 20% RH

Before mounting, devices will require baking if the humidity indicator is > 20% when read at 23

° C ± 5° C.

If baking is required, devices may be baked for:

• 192 hours at 40

° C + 5° C/–0° C and < 5% RH for low-temperature device containers, or

• 24 hours at 125

° C ± 5° C for high-temperature device containers

7.

Ordering Information

Table 7-1.

Ordering Information

Part Number

EVX10AS150BTP

Package

EBGA317

EVX10AS150BTPY EBGA317 RoHS

EV10AS150BCTP EBGA317

EV10AS150BVTP

EV10AS150BCTPY

EV10AS150BVTPY

EV10AS150BTP-EB

EBGA317

EBGA317

RoHS

EBGA317

RoHS

EBGA317

Temperature

Ambient

Ambient

Commercial grade

0

° C < T amb

; T

J

< 90

° C

Industrial grade

–40

° C < T amb

; T

J

< 110

° C

Commercial grade

0

° C < T amb

; T

J

< 90

° C

Industrial grade

–40

° C < T amb

; T

J

< 110

° C

Ambient

Screening

Prototype

Prototype

Standard

Standard

Standard

Standard

Prototype

Comments

Production version

Production version

Production version

Production version

Evaluation Board with soldered

EVX10AS150BTP prototype in

EBGA317 package

72


EV10AS150B

Table of Contents

Features ..................................................................................................... 1

Performance .............................................................................................. 1

Screening .................................................................................................. 1

Applications .............................................................................................. 1

1 Block Diagram .......................................................................................... 2

2 Specifications .......................................................................................... 3

2.1 Absolute Maximum Ratings ..................................................................................... 3

2.2 Recommended Conditions of Use ........................................................................... 6

2.3 Electrical Characteristics for Supplies, Inputs and Outputs ..................................... 7

2.4 Converter Characteristics ........................................................................................ 9

2.5 Transient and Switching Characteristics ............................................................... 21

2.6 Timing Diagram ..................................................................................................... 22

2.7 Digital Output Data Coding .................................................................................... 28

2.8 Explanation of Test Levels .................................................................................... 28

2.9 Definition of Terms ................................................................................................ 29

3 Pin Description ...................................................................................... 31

3.1 Pinout View ........................................................................................................... 31

3.2 Pin Description Table ............................................................................................ 32

4 Theory of Operation .............................................................................. 39

4.1 Overview ............................................................................................................... 39

4.2 Functional Pin Table .............................................................................................. 40

4.3 RESETs and ADC Synchronization ...................................................................... 41

4.4 Control Signal Settings (DMUX) ............................................................................ 43

4.5 ADC 3 Wire Serial Interface (ADC Controls) ......................................................... 49

4.6 Die Junction Temperature Monitoring ................................................................... 53

5 Applications Information ...................................................................... 54

5.1 Bypassing, Decoupling and Grounding ................................................................. 54

5.2 Analog Input Implementation ................................................................................. 60

5.3 Clock Input Implementation ................................................................................... 62

5.4 LVDS Output Implementation ................................................................................ 67

5.5 DRR and ASYNCRST Implementation ................................................................. 68

1076D–BDC–10/12

i


EV10AS150B

6 Package Description ............................................................................. 69

6.1 Package Outline .................................................................................................... 69

6.2 Land Pattern Recommendation ............................................................................. 70

6.3 Thermal Characteristics ........................................................................................ 71

6.4 Moisture Characteristics ........................................................................................ 72

7 Ordering Information ............................................................................. 72

ii


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1076D–BDC–10/12

EV10AS150B

iv


Datasheet EV10AS150B High Linearity ADC 10-bit 2.6 Gsps with 1:4 DMUX

Datasheet

Features

Performance

Screening

Applications

Visit our website: www.e2v.com

for the latest version of the datasheet

1.

Block Diagram

Figure 1-1.

2

2.

Specifications

2.1

Absolute Maximum Ratings

Table 2-1.

3

Table 2-1.

2.1.1

Analog Input Max Ratings in differential configuration

Figure 2-1.

4

2.1.2

Analog Input Max Ratings in Single Ended Configuration

Figure 2-2.

5

2.2

Recommended Conditions of Use

Table 2-2.

Table 2-3.

6

2.3

Electrical Characteristics for Supplies, Inputs and Outputs

Table 2-4.

7

Table 2-4.

8

Table 2-4.

2.4

Converter Characteristics

Table 2-5.

9

Table 2-6.

Table 2-7.

10

Table 2-7.

11

Table 2-7.

12

Table 2-7.

Figure 2-3.

ENOB versus Fclk & Gain - Fin=2595 MHz @-1dBFs

Recommended conditions of use and typical supplies - Tj = 65°C

13

2.4.1

2.4.2

ADC Converter Characteristics with Single Ended Analog Input

Sensitivity of Dynamic Performances to Power Supplies

Figure 2-4.

14

Figure 2-5.

Figure 2-6.

15

2.4.3

Sensitivity of dynamic performances to temperature

Figure 2-7.

Figure 2-8.

Figure 2-9.

16

2.4.4

Figure 2-10. THD versus junction temperature in 1st & 2nd Nyquist

Examples of FFT Spectrum

Figure 2-11. FFT 2.6 Gsps Fin = 1295 MHz @–1 dBFS

17

Figure 2-12. FFT 2.6 Gsps Fin = 1295 MHz @-3 dBFS

Figure 2-13. FFT 2.6 Gsps Fin = 1295 MHz @-7 dBFS

18

Figure 2-14. FFT 2.6 Gsps Fin = 1295 MHz @–13 dBFS

Figure 2-15. FFT 2.6 Gsps Fin = 2595 MHz @–1 dBFS (Carrier at end of the 2nd Nyquist Zone is