VDO | TR 7327 B | Specifications | VDO TR 7327 B Specifications

INTEGRATED CIRCUITS
DATA SHEET
SAA7327
Digital servo processor and
Compact Disc decoder with
integrated DAC for video
CD (CD7 II)
Product specification
Supersedes data of 1999 Jun 17
File under Integrated Circuits, IC01
2000 Jun 26
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.14
7.14.1
7.14.2
7.14.3
7.14.4
7.14.5
7.14.6
7.14.7
7.14.8
7.14.9
7.14.10
7.14.11
7.15
7.15.1
7.15.2
7.15.3
7.15.4
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
QUICK REFERENCE DATA
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.4
7.4.1
7.4.2
7.5
7.5.1
7.5.2
Decoder part
Principal operational modes of the decoder
Decoding speed and crystal frequency
Lock-to-disc mode
Standby modes
Crystal oscillator
Data slicer and clock regenerator
Demodulator
Frame sync protection
EFM demodulation
Subcode data processing
Q-channel processing
EIAJ 3 and 4-wire subcode (CD graphics)
interfaces
V4 subcode interface
FIFO and error corrector
Flags output (CFLG)
Audio functions
De-emphasis and phase linearity
Digital oversampling filter
Concealment
Mute, full-scale, attenuation and fade
Peak detector
DAC interface
Internal bitstream Digital-to-Analog Converter
(DAC)
External DAC interface
EBU interface
Format
KILL circuit
Audio features off
The VIA interface
Spindle motor control
Motor output modes
Spindle motor operating modes
Loop characteristics
FIFO overflow
7.5.3
7.6
7.6.1
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.8
7.8.1
7.8.2
7.9
7.9.1
7.10
7.11
7.12
7.13
7.13.1
7.13.2
7.13.3
7.13.4
2000 Jun 26
7.15.6
7.15.7
Servo part
Diode signal processing
Signal conditioning
Focus servo system
Radial servo system
Off-track counting
Defect detection
Off-track detection
High-level features
Driver interface
Laser interface
Radial shock detector
Microcontroller interface
Microcontroller interface (4-wire bus mode)
Microcontroller interface (I2C-bus mode)
Decoder registers and shadow registers
Summary of functions controlled by decoder
registers 0 to F
Summary of functions controlled by shadow
registers
Summary of servo commands
Summary of servo command parameters
8
LIMITING VALUES
9
CHARACTERISTICS
10
OPERATING CHARACTERISTICS
(SUBCODE INTERFACE TIMING)
11
OPERATING CHARACTERISTICS (I2S-BUS
TIMING)
12
OPERATING CHARACTERISTICS
(MICROCONTROLLER INTERFACE TIMING)
13
APPLICATION INFORMATION
14
PACKAGE OUTLINE
15
SOLDERING
15.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
7.15.5
15.2
15.3
15.4
15.5
2
SAA7327
16
DATA SHEET STATUS
17
DEFINITIONS
18
DISCLAIMERS
19
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
1
SAA7327
FEATURES
• Integrated bitstream DAC with differential outputs,
operating at 96fs with 3rd order noise shaper; typical
performance of −95 dB signal-to-noise ratio (EIAJ
A-weighted)
• Separate serial input and output interfaces allow data
‘loopback’ mode for use of onboard DAC as stand-alone
DAC for digital audio signals
• Up to 2 times speed mode
• Electronic damping of fast radial actuator during long
jump
• Lock-to-disc mode
• Microcontroller loading LOW
• Full error correction strategy, t = 2 and e = 4
• High-level servo control option
• Full subcode (CD graphics) interface
• High-level mechanism monitor
• All standard decoder functions implemented digitally on
chip
• Communication may be via TDA1301/SAA7345
compatible bus or I2C-bus
• FIFO overflow concealment for rotational shock
resistance
• Digital audio interface (EBU), audio and data
• On-chip clock multiplier allows the use of 8.4672,
16.9344 or 33.8688 MHz crystals or ceramic
resonators.
• 2 and 4 times oversampling integrated digital filter,
including fs mode
2
• Audio data peak level detection
The SAA7327 (CD7 II) is a single chip combining the
functions of a CD decoder, digital servo and bitstream
DAC, especially designed for Video CD applications.
The decoder/servo part is based on the SAA737x (CD7)
and is software compatible with this design. Extra
functions are controlled by use of ‘shadow’ registers
(see Section 7.15.3).
• Kill interface for external DAC deactivation during digital
silence
• All SAA737x (CD7) digital servo and high-level functions
• Low focus noise
• Improved playability performance
• Automatic closed-loop gain control available for focus
and radial loops
Supply of this Compact Disc IC does not convey an
implied license under any patent right to use this IC in any
Compact Disc application.
• Pulsed sledge support
3
GENERAL DESCRIPTION
ORDERING INFORMATION
TYPE
NUMBER
SAA7327H
2000 Jun 26
PACKAGE
NAME
QFP64
DESCRIPTION
plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14 × 14 × 2.7 mm
3
VERSION
SOT393-1
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
4
SAA7327
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDD
supply voltage
IDD
supply current
fxtal
CONDITIONS
MIN.
TYP.
MAX.
UNIT
3.0
3.3
3.6
V
−
20
−
mA
crystal frequency
8
8.4672 35
MHz
Tamb
ambient temperature
−10
−
+70
°C
Tstg
storage temperature
−55
−
+125
°C
S/NDAC
onboard DAC signal-to-noise ratio
−90
−95
−
dB
n = 1 mode; note 1
1 kHz; 1fs;
EIAJ A-weighted;
see Figs 38 and 39
Note
1. n = overspeed factor.
2000 Jun 26
4
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
5
SAA7327
BLOCK DIAGRAM
D1 D2
8
R1
R2
VDDA2
VSSA2
handbook, full pagewidth
D3
9
10
VSSA1
D4
11
4
VDDA1
14
VSSD2
VDDD1(P)
VDDD2(C)
VSSD3
VSSD1
5
17
33
50
58
52
57
12
PREPROCESSING
ADC
13
CONTROL
FUNCTION
54
OUTPUT
STAGES
VRIN
7
Vref
GENERATOR
55
56
RA
FO
SL
CONTROL
PART
SCL
SDA
RAB
SILD
HFIN
HFREF
ISLICE
Iref
64
40
39
41
MICROCONTROLLER
INTERFACE
59
42
MOTOR
CONTROL
2
3
MOTO1
MOTO2
SAA7327
DIGITAL
PLL
1
60
LDON
ERROR
CORRECTOR
FRONT-END
FLAGS
6
53
CFLG
EFM
DEMODULATOR
TEST1
TEST2
TEST3
AUDIO
PROCESSOR
25
31
TEST
44
EBU
INTERFACE
SRAM
SELPLL
CRIN
CROUT
CL16
CL11/4
SBSY
SFSY
SUB
RCK
30
24
16
15
51
SERIAL DATA
INTERFACE
TIMING
26
29
28
27
RAM
ADDRESSER
RESET
37
SERIAL DATA
(LOOPBACK)
INTERFACE
48
SCLK
WCLK
DATA
35
36
SCLI
WCLI
SDI
47
SUBCODE
PROCESSOR
46
20
PEAK
DETECT
45
21
43
DECODER
MICROCONTROLLER
INTERFACE
BITSTREAM
DAC
19
22
VERSATILE PINS
INTERFACE
KILL
23
38
63
34
61
62
32
MGS234
V1
V2/V3
V4
V5
Fig.1 Block diagram.
2000 Jun 26
EF
49
18
STATUS
DOBM
5
KILL
Vneg
Vpos
LN
LP
RN
RP
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
6
PINNING
SYMBOL
PIN
DESCRIPTION
HFREF
1
comparator common mode input
HFIN
2
comparator signal input
ISLICE
3
current feedback output from data slicer
VSSA1
4(1)
analog ground 1
VDDA1
5(1)
analog supply voltage 1
6
reference current output
Iref
VRIN
7
reference voltage for servo ADCs
D1
8
unipolar current input 1 (central diode signal input)
D2
9
unipolar current input 2 (central diode signal input)
D3
10
unipolar current input 3 (central diode signal input)
D4
11
unipolar current input 4 (central diode signal input)
R1
12
unipolar current input 1 (satellite diode signal input)
R2
13
unipolar current input 2 (satellite diode signal input)
VSSA2
14(1)
analog ground 2
CROUT
15
crystal/resonator output
CRIN
16
crystal/resonator input
VDDA2
17(1)
analog supply voltage 2
LN
18
DAC left channel differential negative output
LP
19
DAC left channel differential positive output
Vneg
20
DAC negative reference input
Vpos
21
DAC positive reference input
RN
22
DAC right channel differential negative output
RP
23
DAC right channel differential positive output
SELPLL
24
selects whether internal clock multiplier PLL is used
TEST1
25
test control input 1 (this pin should be tied LOW)
CL16
26
16.9344 MHz system clock output
DATA
27
serial d4(1) data output (3-state)
WCLK
28
word clock output (3-state)
SCLK
29
serial bit clock output (3-state)
EF
30
C2 error flag output (3-state)
TEST2
31
test control input 2 (this pin should be tied LOW)
KILL
32
kill output (programmable; open-drain)
VSSD1
33(1)
V2/V3
34
versatile I/O: versatile input 2 or versatile output 3 (open-drain)
WCLI
35
word clock input (for data loopback to DAC)
digital ground 1
SDI
36
serial data input (for data loopback to DAC)
SCLI
37
serial bit clock input (for data loopback to DAC)
RESET
38
power-on reset input (active LOW)
SDA
39
microcontroller interface data I/O line (I2C-bus; open-drain output)
SCL
40
microcontroller interface clock line input (I2C-bus)
2000 Jun 26
6
SAA7327
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SYMBOL
PIN
SAA7327
DESCRIPTION
RAB
41
microcontroller interface R/W and load control line input (4-wire bus mode)
SILD
42
microcontroller interface R/W and load control line input (4-wire bus mode)
STATUS
43
servo interrupt request line/decoder status register output (open-drain)
TEST3
44
test control input 3 (this pin should be tied LOW)
RCK
45
subcode clock input
SUB
46
P-to-W subcode bits output (3-state)
SFSY
47
subcode frame sync output (3-state)
SBSY
48
subcode block sync output (3-state)
CL11/4
49
VSSD2
50(1)
DOBM
51
VDDD1(P)
52(1)
11.2896 or 4.2336 MHz (for microcontroller) clock output
digital ground 2
bi-phase mark output (externally buffered; 3-state)
digital supply voltage 1 for periphery
CFLG
53
correction flag output (open-drain)
RA
54
radial actuator output
FO
55
focus actuator output
SL
56
sledge control output
VDDD2(C)
57(1)
digital supply voltage 2 for core
VSSD3
58(1)
digital ground 3
MOTO1
59
motor output 1; versatile (3-state)
MOTO2
60
motor output 2; versatile (3-state)
V4
61
versatile output 4
V5
62
versatile output 5
V1
63
versatile input 1
LDON
64
laser drive on output (open-drain)
Note
1. All supply pins must be connected to the same external power supply voltage.
2000 Jun 26
7
Philips Semiconductors
Product specification
49 CL11/4
50 VSSD2
SAA7327
51 DOBM
52 VDDD1(P)
53 CFLG
54 RA
55 FO
56 SL
58 VSSD3
59 MOTO1
60 MOTO2
61 V4
62 V5
63 V1
64 LDON
handbook, full pagewidth
57 VDDD2(C)
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
HFREF 1
48 SBSY
HFIN 2
47 SFSY
ISLICE 3
46 SUB
VSSA1 4
45 RCK
VDDA1 5
44 TEST3
Iref 6
43 STATUS
VRIN 7
42 SILD
D1 8
41 RAB
SAA7327H
D2 9
40 SCL
D3 10
39 SDA
D4 11
38 RESET
R1 12
37 SCLI
R2 13
36 SDI
VSSA2 14
35 WCLI
CROUT 15
34 V2/V3
33 VSSD1
KILL 32
TEST2 31
EF 30
SCLK 29
WCLK 28
DATA 27
CL16 26
TEST1 25
SELPLL 24
RP 23
RN 22
Vpos 21
Vneg 20
LP 19
LN 18
VDDA2 17
CRIN 16
MGS249
Fig.2 Pin configuration.
7
FUNCTIONAL DESCRIPTION
7.1
7.1.1
Depending on the crystal frequency used and the internal
clock settings (selectable via decoder register B), the
playback speeds shown in Table 1 are possible, where ‘n’
is the overspeed factor (1 or 2).
Decoder part
PRINCIPAL OPERATIONAL MODES OF THE DECODER
The decoding part supports a full audio specification and
can operate at two different disc speeds, from
single-speed (n = 1) to 2 times speed (n = 2). The factor
‘n’ is called the overspeed factor. A simplified data flow
through the decoder part is illustrated in Fig.7.
An internal clock multiplier is present, controlled by
SELPLL, and should only be used if a 8.4672 or
16.9344 MHz crystal, ceramic resonator or external clock
is present.
7.1.3
7.1.2
DECODING SPEED AND CRYSTAL FREQUENCY
For Electronic Shock Absorption (ESA) applications, the
SAA7327 can be put into lock-to-disc mode. This allows
Constant Angular Velocity (CAV) disc playback with
The SAA7327 is a two speed decoding device, with an
internal Phase-Locked Loop (PLL) clock multiplier.
2000 Jun 26
LOCK-TO-DISC MODE
8
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
• Standby 1: ‘CD-STOP’ mode; most I/O functions are
switched off
varying input data rates from the inside-to-outside of the
disc.
• Standby 2: ‘CD-PAUSE’ mode; audio output features
are switched off, but the motor loop, the motor output
and the subcode interfaces remain active; this is also
called a ‘Hot Pause’.
In the lock-to-disc mode, the FIFO is blocked and the
decoder will adjust its output data rate to the disc speed.
Hence, the frequency of the I2S-bus (WCLK and SCLK)
clocks are dependent on the disc speed. In the lock-to-disc
mode there is a limit on the maximum variation in disc
speed that the SAA7327 will follow. Disc speeds must
always be within 25% to 100% range of their nominal
value. The lock-to-disc mode is enabled/disabled by
decoder register E.
7.1.4
SAA7327
In the standby modes the various pins will have the
following values:
• MOTO1 and MOTO2: put in high-impedance, PWM
mode (standby 1 and reset: operating in standby 2); put
in high-impedance, PDM mode (standby 1 and reset:
operating in standby 2)
STANDBY MODES
• SCL and SDA: no interaction; normal operation
continues
The SAA7327 may be placed in two standby modes
selected by decoder register B (it should be noted that the
device core is still active):
• SCLK, WCLK, DATA, EF and DOBM: 3-state in both
standby modes; normal operation continues after reset
• CRIN, CROUT, CL16 and CL11/4: no interaction;
normal operation continues
• V1, V2/V3, V4, V5 and CFLG: no interaction; normal
operation continues.
Table 1
Playback speeds
CRYSTAL FREQUENCY (MHz)
REGISTER B
33.8688
16.9344
8.4672
CL11
FREQUENCY
(MHz)(1)
SELPLL
00XX
0
n=1
−
−
11.2896
00XX
1
−
−
n=1
11.2896
01XX
0
−
n=1
−
5.6448
01XX
1
−
n=1
−
11.2896
10XX
0
n=2
−
−
11.2896
10XX
1
−
−
n=2
11.2896
11XX
0
−
n = 2(2)
−
5.6448
11XX
1
−
n=2
−
11.2896
Notes
1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. CL11 is
available on the CL11/4 output, enabled by programming shadow register 3 (see Section 7.15.3).
2. Data capture performance is not optimized for this option.
2000 Jun 26
9
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.2
Crystal oscillator
7.3
The crystal oscillator is a conventional 2-pin design
operating between 8 and 35 MHz. This oscillator is
capable of operating with ceramic resonators and with
both fundamental and third overtone crystals. External
components should be used to suppress the fundamental
output of the third overtone crystals as shown in
Figs 3 and 4. Typical oscillation frequencies required are
8.4672, 16.9344 or 33.8688 MHz depending on the
internal clock settings used and whether or not the clock
multiplier is enabled.
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two registers
(8 and 9) for selecting bandwidth and equalization.
The PLL response is shown in Fig.5.
SAA7327
OSCILLATOR
33 pF
For certain applications an off-track input is necessary.
This is internally connected from the servo part (its polarity
can be changed by the foc_parm1 parameter), but may be
input via the V1 pin if selected by register C. If this flag is
HIGH, the SAA7327 will assume that its servo part is
following on the wrong track, and will flag all incoming
HF data as incorrect.
CRIN
8.4672 MHz
Data slicer and clock regenerator
The SAA7327 has an integrated slice level comparator
which can be clocked by the crystal frequency clock, or
4 times the crystal frequency clock (if SELPLL is set HIGH
while using a 16.9344 MHz crystal and register 4 is set to
0XXX), or 8 times the crystal frequency clock (if SELPLL is
set HIGH while using an 8.4672 MHz crystal, and
register 4 is set to 0XXX). The slice level is controlled by
an internal current source applied to an external capacitor
under the control of the Digital Phase-Locked
Loop (DPLL).
handbook, halfpage
CROUT
SAA7327
33 pF
MGS246
Fig.3 8.4672 MHz fundamental configuration.
handbook, halfpage
PLL
loop
response
handbook, halfpage
SAA7327
OSCILLATOR
CROUT
3. PLL, LPF
f
CRIN
33.8688 MHz
2. PLL bandwidth
1. PLL integrator
3.3 µH
10 pF
10 pF
MGS178
1 nF
1, 2 and 3 are programmable via decoder register 8.
MGS247
Fig.5 Digital PLL loop response.
Fig.4 33.8688 MHz overtone configuration.
2000 Jun 26
10
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
crystal
clock
100 nF
HFREF
VSSA
D
47 pF
1 nF
Q
HF input
2.2 kΩ
HFIN
DPLL
22 kΩ
100 µA
VSS
100 nF
ISLICE
MGS179
VDD
100 µA
VSSA
Fig.6 Data slicer showing typical application components (for n = 1).
7.4
7.4.1
Demodulator
The PLL lock signal can be accessed via the SDA or
STATUS pins selected by decoder registers 2 and 7.
FRAME SYNC PROTECTION
• A sync coincidence is detected; sync pattern occurs
588 ±1 EFM clocks after the previous sync pattern
Also incorporated in the demodulator is a Run Length
2 (RL2) correction circuit. Every symbol detected as RL2
will be pushed back to RL3. To do this, the phase error of
both edges of the RL2 symbol are compared and the
correction is executed at the side with the highest error
probability.
• A new sync pattern is detected within ±6 EFM clocks of
its expected position.
7.4.2
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.
The master counter is only reset if:
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if during 61
consecutive frames no sync coincidence is found.
2000 Jun 26
EFM DEMODULATION
11
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RCK
0: reg D = XX01
CD GRAPHICS
INTERFACE
SBSY
SFSY
SUB
MICROCONTROLLER
INTERFACE
V4 SUBCODE
INTERFACE
SDA
reg F
SUBCODE
PROCESSOR
output from
data slicer
DIGITAL PLL
AND
DEMODULATOR
EBU
INTERFACE
1: decoder reg A = XX0X
0: decoder reg A ≠ XX1X
decoder reg A
DOBM
1: shadow reg 7 = XX1X
0: shadow reg 7 = XX0X
SCLK
WCLK
DATA
EF
1
1
1: decoder reg 3 = XX10
(1fs mode)
0: decoder reg 3 ≠ XX10
0
0
12
1: no pre-emphasis detected
OR reg D = 01XX
(de-emphasis signal at V5)
0: pre-emphasis detected
AND reg D ≠ 01XX
FIFO
ONBOARD
DAC
1
0
1
ERROR
CORRECTOR
FADE/MUTE/
INTERPOLATE
DIGITAL
FILTER
0
PHASE
COMPENSATION
1
0
Vneg
1
0
LN
LP
RN
RP
1
0
I2S/EIAJ BUS
INTERFACE
1
1: shadow reg 7 = XXX1
0: shadow reg 7 = XXX0
0
decoder reg 3
KILL
decoder reg C
DE-EMPHASIS
FILTER
decoder
reg 3
KILL
V3
1: decoder reg 3 ≠ 101X
0: decoder reg 3 = 101X
(CD-ROM modes)
1: shadow reg 7 = XX1X
0: shadow reg 7 = XX0X
I2S/EIAJ
LOOPBACK
INTERFACE
WCLI
SCLI
SDI
MGS180
Product specification
SAA7327
Fig.7 Simplified data flow of decoder functions.
Philips Semiconductors
V4
0
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
ok, full pagewidth
2000 Jun 26
1
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.5
7.5.1
Subcode data processing
The subcode interface output formats are illustrated in
Fig.8, where the RCK signal is supplied by another device
such as a CD graphics decoder.
Q-CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a
Cyclic Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the SDA or STATUS pins, selected via decoder
register 2. Good Q-channel data may be read from SDA.
7.5.2
7.5.3
INTERFACES
Data from all the subcode channels (P-to-W) may be read
via the subcode interface, which conforms to EIAJ
CP-2401. The interface is enabled and configured as
either a 3 or 4-wire interface via decoder register F.
SF0
SF1
V4 SUBCODE INTERFACE
Data of subcode channels, Q-to-W, may be read via pin V4
if selected via decoder register D. The format is similar to
RS232 and is illustrated in Fig.9. The subcode sync word
is formed by a pause of (200/n) µs minimum. Each
subcode byte starts with a logic 1 followed by 7 bits
(Q-to-W). The gap between bytes is variable between
(11.3/n) µs and (90/n) µs.
EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)
handbook, full pagewidth
SAA7327
The subcode data is also available in the EBU output
(DOBM) in a similar format.
SF2
SF3
SF97
P-W
P-W
P-W
SF0
SF1
SF0
SF1
SBSY
SFSY
RCK
SUB
EIAJ 4-wire subcode interface
SF0
SF1
SF2
SF3
SF97
P-W
P-W
P-W
SFSY
RCK
SUB
EIAJ 3-wire subcode interface
SFSY
RCK
P
Q
R
S
T
U
V
W
SUB
MBG410
Fig.8 EIAJ subcode (CD graphics) interface format.
2000 Jun 26
13
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
200/n µs
min
W96
11.3/n µs min
90/n µs max
11.3/n
µs
1
Q
SAA7327
R
S
T
U
V
W
1
Q
MBG401
n = disc speed.
Fig.9 Subcode format and timing on pin V4.
7.6
FIFO and error corrector
7.6.1
The SAA7327 has a ±8 frame FIFO. The error corrector is
a t = 2, e = 4 type, with error corrections on both C1
(32 symbol) and C2 (28 symbol) frames. Four symbols are
used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
up to four errors on the C2 level.
The flags output pin CFLG shows the status of the error
corrector and interpolator and is updated every frame
(7.35 × n kHz). In the SAA7327 chip a 1-bit flag is present
on the CFLG pin as illustrated in Fig.10. This signal shows
the status of the error corrector and interpolator.
The first flag bit, F1, is the absolute time sync signal, the
FIFO-passed subcode sync and relates the position of the
subcode sync to the audio data (DAC output). This flag
may also be used in a super FIFO or in the synchronization
of different players. The output flags can be made
available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by decoder register A.
The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read after (de-interleaving) by C2,
to help in the generation of C2 output flags.
The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM). The EF output will flag bytes
in error in both audio and CD-ROM modes.
handbook, full pagewidth
33.9/n µs
F8
FLAGS OUTPUT (CFLG)
11.3/n
µs
F1
33.9/n µs
F2
F3
F4
F5
F6
F7
F8
F1
MBG425
n = disc speed.
Fig.10 Flag output timing diagram.
2000 Jun 26
14
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
Table 2
SAA7327
Output flags
F1
F2
F3
F4
F5
F6
F7
F8
DESCRIPTION
0
X
X
X
X
X
X
X
no absolute time sync
1
X
X
X
X
X
X
X
absolute time sync
X
0
0
X
X
X
X
X
C1 frame contained no errors
X
0
1
X
X
X
X
X
C1 frame contained 1 error
X
1
0
X
X
X
X
X
C1 frame contained 2 errors
X
1
1
X
X
X
X
X
C1 frame uncorrectable
X
X
X
0
0
X
X
0
C2 frame contained no errors
X
X
X
0
0
X
X
1
C2 frame contained 1 error
X
X
X
0
1
X
X
0
C2 frame contained 2 errors
X
X
X
0
1
X
X
1
C2 frame contained 3 errors
X
X
X
1
0
X
X
0
C2 frame contained 4 errors
X
X
X
1
1
X
X
1
C2 frame uncorrectable
X
X
X
X
X
0
0
X
no interpolations
X
X
X
X
X
0
1
X
at least one 1-sample interpolation
X
X
X
X
X
1
0
X
at least one hold and no interpolations
X
X
X
X
X
1
1
X
at least one hold and one 1-sample interpolation
7.7
7.7.1
Audio functions
Table 3
DE-EMPHASIS AND PHASE LINEARITY
When pre-emphasis is detected in the Q-channel
subcode, the digital filter automatically includes a
de-emphasis filter section. When de-emphasis is not
required, a phase compensation filter section controls the
phase of the digital oversampling filter to ≤ ±1° within the
band 0 to 16 kHz. With de-emphasis the filter is not phase
linear.
PASS BAND
STOP BAND
ATTENUATION
0 to 9 kHz
−
≤0.001 dB
19 to 20 kHz
−
≤0.03 dB
−
24 kHz
≥25 dB
−
24 to 27 kHz
≥38 dB
−
27 to 35 kHz
≥40 dB
If the de-emphasis signal is set to be available at V5,
selected via decoder register D, then the de-emphasis
filter is bypassed.
7.7.2
DIGITAL OVERSAMPLING FILTER
7.7.3
For optimizing performance with an external DAC, the
SAA7327 contains a 2 to 4 times oversampling IIR filter.
The filter specification of the 4 times oversampling filter is
given in Table 3.
−
35 to 64 kHz
≥50 dB
−
64 to 68 kHz
≥31 dB
−
68 kHz
≥35 dB
−
69 to 88 kHz
≥40 dB
CONCEALMENT
A 1-sample linear interpolator becomes active if a single
sample is flagged as erroneous but cannot be corrected.
The erroneous sample is replaced by a level midway
between the preceding and following samples. Left and
right channels have independent interpolators. If more
than one consecutive non-correctable sample is found, the
last good sample is held. A 1-sample linear interpolation is
then performed before the next good sample (see Fig.11).
These attenuations do not include the sample-and-hold at
the external DAC output or the DAC post filter. When using
the oversampling filter, the output level is scaled −0.5 dB
down, to avoid overflow on full-scale sine wave inputs
(0 to 20 kHz).
2000 Jun 26
Filter specification
In CD-ROM modes (i.e. the external DAC interface is
selected to be in a CD-ROM format) concealment is not
executed.
15
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.7.4
7.7.5
MUTE, FULL-SCALE, ATTENUATION AND FADE
A digital level controller is present on the SAA7327 which
performs the functions of soft mute, full-scale, attenuation
and fade; these are selected via decoder register 0:
SAA7327
PEAK DETECTOR
The peak detector measures the highest audio level
(absolute value) on positive peaks for left and right
channels. The 8 most significant bits are output in the
Q-channel data in place of the CRC bits. Bits 81 to 88
contain the left peak value (bit 88 = MSB) and
bits 89 to 96 contain the right peak value (bit 96 = MSB).
The values are reset after reading Q-channel data via
SDA.
• Mute: signal reduced to 0 in a maximum of 128 steps;
(3/n) ms
• Attenuate: signal scaled by −12 dB
• Full-scale: ramp signal back to 0 dB level; from mute
takes (3/n) ms
• Fade: activates a 128 stage counter which allows the
signal to be scaled up/down by 0.07 dB steps
– 128 = full-scale
– 120 = −0.5 dB (i.e. full-scale if oversampling filter
used)
– 32 = −12 dB
– 0 = mute.
Interpolation
OK
Error
Hold
OK
Error
Interpolation
Error
Error
OK
OK
MGA372
Fig.11 Concealment mechanism.
2000 Jun 26
16
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.8
7.8.1.2
DAC interface
7.8.1
INTERNAL BITSTREAM DIGITAL-TO-ANALOG
CONVERTER (DAC)
Loopback external data into onboard DAC
The onboard DAC can also be set to accept digital audio
inputs from an external source, e.g. audio from a VCD
decoder IC. This is known as loopback mode and is
enabled by setting shadow register 7 to XX01. This
enables the serial data output pins SCLK, WCLK, DATA
and EF so that data can be routed to the external VCD
decoder (or external DAC).
The onboard bitstream DAC operates at a clock frequency
of 96fs and is designed for operation with an audio input at
1fs. Optimum performance is dependent on the application
circuit used and careful consideration should be given to
the recommended application circuits shown in
Figs 38 and 39. The onboard DAC is controlled from
shadow register 7 (see Section 7.15.3 for definition of
shadow registers). This shadow register controls routing of
data into the onboard DAC and also controls the DAC
output pins, which can be held at zero when the onboard
DAC is not required; see Table 4.
The digital audio data output from the VCD decoder can
then also be input to the onboard DAC on the SAA7327 by
utilising the serial data input interface (SCLI, SDI and
WCLI).
In this mode, a wide range of data formats to the external
VCD IC can be programmed as shown in Table 4.
However, the serial inputs on the SAA7327 will always
expect the input digital audio data from the VCD IC to be
16-bit 1fs and the same data format, either I2S-bus or
EIAJ, as the serial output format (set by decoder
register 3). In fact, the onboard DAC will also accept 18-bit
I2S-bus data; in this case the 16 MSBs only will be read
and the 2 LSBs discarded.
Audio data from the decoder part of SAA7327 can be
routed as described in Sections 7.8.1.1 and 7.8.1.2.
7.8.1.1
SAA7327
Use onboard DAC
Setting shadow register 7 to XX11 will route audio data
from the CD7 II decoder into the internal DAC and enables
the DAC output pins (LN, LP, RN, RP). To enable the
on-board DAC, the DAC interface format (set by register 3)
must be set to 16-bit 1fs mode, either I2S or EIAJ format.
CD-ROM mode can also be used if interpolation is not
required. The serial data output pins for interfacing with an
external DAC (SCLK, WCLK, DATA and EF) are set to
high-impedance.
Table 4
Shadow register
SHADEN
SHADOW
ADDRESS
1
0111 (7H)
2000 Jun 26
REGISTER
DATA
control of
onboard DAC
XXX0
hold onboard DAC outputs at
zero
reset
XXX1
enable onboard DAC outputs
−
XX0X
use external DAC or route audio
data into onboard DAC
(loopback mode)
XX1X
route audio data into onboard
DAC (non-loopback mode)
17
FUNCTION
RESET
reset
−
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.8.2
All formats are MSB first and fs is (44.1 × n) kHz.
The polarity of the WCLK and the data can be inverted;
selectable by decoder register 7. It should be noted that
EF is only a defined output in CD-ROM and 1fs modes.
EXTERNAL DAC INTERFACE
Audio data from the CD7 II decoder can be sent direct to
an external DAC, identical to the SAA737x series. This is
similar to the ‘loopback’ mode, but in this case the internal
DAC outputs can be held at zero i.e. shadow register 7 is
set to XX00. The SAA7327 is compatible with a wide range
of external DACs. Eleven formats are supported and are
given in Table 4. Figures 12 and 13 show the Philips
I2S-bus and the EIAJ data formats respectively. When the
decoder is operated in lock-to-disc mode, the SCLK
frequency is dependent on the disc speed factor ‘d’.
Table 5
SAA7327
When using an external DAC (or when using the onboard
DAC in non-loopback mode), the serial data inputs to the
onboard DAC (SCLI, SDI and WCLI) should be left
unconnected.
DAC interface formats
REGISTER 3
SAMPLE
FREQUENCY
NUMBER OF
BITS
SCLK (MHz)
1010
fs
16
2.1168 × n
CD-ROM (I2S-bus)
1011
fs
16
2.1168 × n
CD-ROM (EIAJ)
FORMAT
INTERPOLATION
no
no
1110
fs
16/18(1)
2.1168 × n
Philips
0010
fs
16
2.1168 × n
EIAJ 16 bits
yes
0110
fs
18
2.1168 × n
EIAJ 18 bits
yes
0000
4fs
16
8.4672 × n
EIAJ 16 bits
yes
0100
4fs
18
8.4672 × n
EIAJ 18 bits
yes
1100
4fs
18
8.4672 × n
Philips I2S-bus 18 bits
yes
0011
2fs
16
4.2336 × n
EIAJ 16 bits
yes
0111
2fs
18
4.2336 × n
EIAJ 18 bits
yes
1111
2fs
18
4.2336 × n
Philips I2S-bus 18 bits
yes
I2S-bus
16/18
bits(1)
yes
Note
1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated
then the first 18 bits contain data.
2000 Jun 26
18
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1
15 14
0
1
0
15 14
LEFT CHANNEL DATA (WCLK NORMAL POLARITY)
WCLK
EF
LSB error flag
(CD-ROM
AND Ifs MODES ONLY)
MSB error flag
LSB error flag
MSB error flag
MBG424
Fig.12 Philips I2S-bus data format (16-bit word length shown).
Philips Semiconductors
DATA
19
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
2000 Jun 26
SCLK
SCLK
DATA
0
17
0
17
LEFT CHANNEL DATA
WCLK
LSB error flag
MSB error flag
MBG423
Fig.13 EIAJ data format (18-bit word length shown).
Product specification
MSB error flag
SAA7327
EF
(CD-ROM
AND Ifs MODES ONLY)
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.9
EBU interface
7.9.1
SAA7327
FORMAT
The digital audio output consists of 32-bit words
(‘subframes’) transmitted in bi-phase mark code (two
transitions for a logic 1 and one transition for a logic 0).
Words are transmitted in blocks of 384. The formats are
given in Table 6.
The bi-phase mark digital output signal at pin DOBM is in
accordance with the format defined by the IEC 958
specification. Three different modes can be selected via
decoder register A:
• DOBM pin held LOW
• Data taken before concealment, mute and fade (must
always be used for CD-ROM modes)
• Data taken after concealment, mute and fade.
Table 6
Format
FUNCTION
BITS
Sync
0 to 3
Auxiliary
4 to 7
Error flags
4
Audio sample
8 to 27
DESCRIPTION
−
not used; normally zero
CFLG error and interpolation flags when selected by register A
first 4 bits not used (always zero) twos complement LSB = bit 12,
MSB = bit 27
Validity flag
28
valid = logic 0
User data
29
used for subcode data (Q-to-W)
Channel status
30
control bits and category code
Parity bit
31
even parity for bits 4 to 30
Table 7
Description of Table 6
FUNCTION
DESCRIPTION
Sync
The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.
Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample
(no block start) and sync W: word contains right sample.
Audio sample
Left and right samples are transmitted alternately.
Validity flag
Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This
flag remains the same even if data is taken after concealment.
User data
Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is
asynchronous with the block rate.
Channel status
The channel status bit is the same for left and right words. Therefore a block of 384 words contains
192 channel status bits. The category code is always CD. The bit assignment is given in Table 8.
Table 8
Bit assignment
FUNCTION
Control
BITS
DESCRIPTION
0 to 3
copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when
copy permitted; bit 3 is logic 1 when recording has pre-emphasis
Reserved mode
4 to 7
always zero
Category code
8 to 15
CD: bit 8 = logic 1, all other bits = logic 0
Clock accuracy
28 to 29
set by register A; 10 = level I; 00 = level II; 01 = level III
Remaining
2000 Jun 26
6 to 27 and 30 to 191 always zero
20
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.10
KILL circuit
It should be noted that the EBU output should be set LOW
prior to switching the audio features off and after switching
audio features back on a full-scale command should be
given.
The KILL circuit detects digital silence by testing for an
all-zero or all-ones data word in the left or right channel
prior to the digital filter. The output is switched active LOW
when silence has been detected for at least 270 ms, or if
mute is active, or in CD-ROM modes. Two modes are
available which can be selected by decoder register C:
7.12
The VIA interface
The SAA73727 has four pins that can be reconfigured for
different applications. One of these pins, V2/V3, can be
programmed as an input (V2) or as an output (V3). Control
of the V2/V3 pin is via shadow register 3; see Table 9:
• Pin KILL: KILL active LOW indicates silence detected on
both left and right channels
• Pin KILL: KILL active LOW indicates silence detected on
left channel. V3 active LOW indicates silence detected
on right channel.
Selection of the V2/V3 pin does not affect the function
programmed by decoder register C i.e. the V2/V3 pin can
be changed from V2 to V3 function either before or after
setting the desired function via decoder register 1100.
Selection of, for instance, a V3 function while the V2/V3
pin is set to V2 will not affect the V2 functionality.
It should be noted that when mute is active or in CD-ROM
modes the output(s) are switched LOW.
7.11
SAA7327
Audio features off
The functions of these versatile pins is identical to the
SAA737x series. The functions of these versatile pins is
programmed by decoder registers C and D, as shown in
Table 10.
The audio features can be turned off (selected by decoder
register E) which affects the following functions:
• Digital filter, fade, peak detector, KILL circuit (but
outputs KILL, V3 still active) are disabled
• V5 (if selected to be the de-emphasis flag output) and
the EBU outputs become undefined.
Table 9
V2/V3 configuration
SHADEN
ADDRESS
REGISTER
DATA
FUNCTION
1
0011 (3H)
control of
V2/V3 pin
0XXX
V2/V3 pin configured as V2 input
1XXX
V2/V3 pin configured as V3 output (open-drain)
RESET
reset
−
Table 10 Pin applications
PIN NAME
PIN
NUMBER
TYPE
V1
63
input
1100
−
XXX1
XXX0
V2
36
input
−
−
V3
36
output
V4
61
output
V5
62
output
1100
−
−
1101
−
−
−
1101
−
−
XX0X
X01X
X11X
0000
XX01
XX10
XX11
01XX
10XX
11XX
2000 Jun 26
REGISTER REGISTER
ADDRESS
DATA
21
FUNCTION
external off-track signal input
internal off-track signal used input may be read
via decoder status bit; selected via register 2
input may be read via decoder status bit;
selected via register 2
KILL output for right channel
output = 0
output = 1
4-line motor drive (using V4 and V5)
Q to W subcode output
output = 0
output = 1
de-emphasis output (active HIGH)
output = 0
output = 1
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.13
7.13.1
7.13.1.1
Spindle motor control
SAA7327
Pulse density output mode
In the pulse density mode the motor output pin (MOTO1)
is the pulse density modulated motor output signal. A 50%
duty factor corresponds with the motor not actuated,
higher duty factors mean acceleration, lower mean
braking. In this mode, the MOTO2 signal is the inverse of
the MOTO1 signal. Both signals change state only on the
edges of a (1 × n) MHz internal clock signal. Possible
application diagrams are illustrated in Fig.14.
MOTOR OUTPUT MODES
The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal
±8 frame FIFO and disc speed information are used to
calculate the motor control output signals. Several output
modes, selected by decoder register 6, are supported:
• Pulse density, 2-line (true complement output),
(1 × n) MHz sample frequency
• PWM output, 2-line, (22.05 × n) kHz modulation
frequency
7.13.1.2
PWM output mode (2-line)
In the PWM mode the motor acceleration signal is put in
pulse-width modulation form on the MOTO1 output.
The motor braking signal is pulse-width modulated on the
MOTO2 output. The timing is illustrated in Fig.15. A typical
application diagram is illustrated in Fig.16.
• PWM output, 4-line, (22.05 × n) kHz modulation
frequency
• CDV motor mode.
22 kΩ
22 kΩ
MOTO1
+
–
10 nF
VDD
MOTO2
+
–
M
VSS
10 nF
VSS
22 kΩ
22 kΩ
MOTO1
+
–
10 nF
22 kΩ
M
VSS
22 kΩ
VSS
VSS
22 kΩ
VDD
MGA363 - 1
Fig.14 Motor pulse density application diagrams.
t rep = 45 µs
t dead
240 ns
MOTO1
MOTO2
Accelerate
Brake
Fig.15 2-line PWM mode timing.
2000 Jun 26
22
MGA366
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
+
M
10 Ω
100 nF
MOTO1
MOTO2
VSS
MGA365 - 2
Fig.16 Motor 2-line PWM mode application diagram.
7.13.1.3
PWM output mode (4-line)
Using two extra outputs from the versatile pins interface, it is possible to use the SAA7327 with a 4-input motor bridge.
The timing is illustrated in Fig.17. A typical application diagram is illustrated in Fig.18.
t rep = 45 µs
t dead
240 ns
MOTO1
MOTO2
V4
V5
t ovl = 240 ns
Accelerate
Fig.17 4-line PWM mode timing.
2000 Jun 26
MGA367 - 1
Brake
23
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
+
V4
V5
M
10 Ω
100 nF
MOTO1
MOTO2
VSS
MGA364 - 2
Fig.18 Motor 4-line PWM mode application diagram.
7.13.1.4
CDV/CAV output mode
7.13.2.1
In the CDV motor mode, the FIFO position will be put in
pulse-width modulated form on the MOTO1 pin [carrier
frequency (300 × d) Hz], where ‘d’ is the disc speed factor.
The PLL frequency signal will be put in pulse-density
modulated form (carrier frequency 4.23 × n MHz) on the
MOTO2 pin. The integrated motor servo is disabled in this
mode.
In start mode 1, start mode 2, stop mode 1 and stop
mode 2, a fixed positive or negative voltage is applied to
the motor. This voltage can be programmed as a
percentage of the maximum possible voltage, via
register 6, to limit current drain during start and stop.
The following power limits are possible; 100% (no power
limit), 75%, 50%, or 37% of maximum.
The PWM signal on MOTO1 corresponds to a total
memory space of 20 frames, therefore the nominal FIFO
position (half full) will result in a PWM output of 60%.
7.13.3
• Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32
SPINDLE MOTOR OPERATING MODES
• Crossover frequency f4: 0.5 × n Hz, 0.7 × n Hz,
1.4 × n Hz and 2.8 × n Hz
The operation modes of the motor servo is controlled by
decoder register 1 (see Table 11).
• Crossover frequency f3: 0.85 × n Hz, 1.71 × n Hz and
3.42 × n Hz.
In the SAA7327 decoder there is an anti-windup mode for
the motor servo, selected via decoder register 1. When the
anti-wind-up mode is activated the motor servo integrator
will hold if the motor output saturates.
2000 Jun 26
LOOP CHARACTERISTICS
The gain and crossover frequencies of the motor control
loop can be programmed via decoder registers 4 and 5.
The following parameter values are possible:
In the lock to-disc (CAV) mode the CDV motor mode is the
only mode that can be used to control the motor.
7.13.2
Power limit
It should be noted that the crossover frequencies f3 and f4
are scaled with the overspeed factor ‘n’ whereas the gains
are not.
24
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.13.4
SAA7327
FIFO OVERFLOW
If FIFO overflow occurs during Play mode (e.g.: as a result of motor rotational shock), the FIFO will be automatically reset
to 50% and the audio interpolator tries to conceal as much as possible to minimize the effect of data loss.
Table 11 Operating modes
MODE
DESCRIPTION
Start mode 1
The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved
and the PLL is reset. No disc speed information is available for the microcontroller.
Start mode 2
The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the
disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status
signals selectable via register 2 are valid.
Jump mode
Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is
possible to read the subcode. It should be noted that in the CD-ROM modes the data, on EBU and
the I2S-bus is not muted.
Jump mode 1
Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a large
change in disc speed.
Play mode
FIFO released after resetting to 50%. Audio mute released.
Stop mode 1
Disc is braked by applying a negative voltage to the motor. No decisions are involved.
Stop mode 2
The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc
reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its nominal
speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode.
Off mode
Motor not steered.
MGA362 - 2
G
f4
BW
f3
Fig.19 Motor servo mode diagram.
2000 Jun 26
25
f
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.14
7.14.1
Servo part
SAA7327
The ADCs are designed to convert unipolar currents into a
digital code. The dynamic range of the input currents is
adjustable within a given range, which is dependent on the
value of the external reference current (Iref) resistor and
the values programmed in shadow registers A and C.
The magnitude of the signal currents for the central
aperture diodes D1 to D4 and the radial diodes R1 and R2
are programmed separately to sixteen separate current
ranges.
DIODE SIGNAL PROCESSING
The photo detector in conventional two-stage three-beam
Compact Disc systems normally contains six discrete
diodes. Four of these diodes (three for single foucault
systems) carry the Central Aperture signal (CA) while the
other two diodes (satellite diodes) carry the radial tracking
information. The CA signal is processed into an HF signal
(for the decoder function) and LF signal (information for
the focus servo loop) before it is supplied to the SAA7327.
The maximum input currents with an external 30 kΩ
reference current resistor are given in Table 12.
The analog signals from the central and satellite diodes
are converted into a digital representation using
Analog-to-Digital Converters (ADCs).
Table 12 Shadow register settings to control diode input current ranges
SHADEN BIT
1
2000 Jun 26
SHADOW
REGISTER
A signal
magnitude
control for
diodes
D1 to D4
ADDRESS
DATA
FUNCTION
INITIAL
1010
0000
(0.042).Iref = 1.006 µA (nominal)
−
0001
(0.083).Iref = 2.013 µA (nominal)
−
0010
(0.125).Iref = 3.019 µA (nominal)
−
0011
(0.167).Iref = 4.025 µA (nominal)
−
0100
(0.208).Iref = 5.031 µA (nominal)
−
0101
(0.25).Iref = 6.034 µA (nominal)
−
0110
(0.292).Iref = 7.044 µA (nominal)
−
0111
(0.333).Iref = 8.05 µA (nominal)
−
1000
(0.375).Iref = 9.056 µA (nominal)
−
1001
(0.417).Iref = 10.063 µA (nominal)
−
1010
(0.458).Iref = 11.069 µA (nominal)
−
1011
(0.5).Iref = 12.075 µA (nominal)
−
1100
(0.542).Iref = 13.081 µA (nominal)
−
1101
(0.583).Iref = 14.088 µA (nominal)
−
1110
(0.625).Iref = 15.094 µA (nominal)
−
1111
(0.667).Iref = 16.1 µA (nominal)
26
reset
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SHADEN BIT
1
7.14.2
SHADOW
REGISTER
C signal
magnitude
control for
diodes
R1 and R2
ADDRESS
DATA
1100
0000
(0.042).Iref = 1.006 µA (nominal)
−
0001
(0.083).Iref = 2.013 µA (nominal)
−
0010
(0.125).Iref = 3.019 µA (nominal)
−
0011
(0.167).Iref = 4.025 µA (nominal)
−
0100
(0.208).Iref = 5.031 µA (nominal)
−
0101
(0.25).Iref = 6.034 µA (nominal)
−
0110
(0.292).Iref = 7.044 µA (nominal)
−
0111
(0.333).Iref = 8.05 µA (nominal)
−
1000
(0.375).Iref = 9.056 µA (nominal)
−
1001
(0.417).Iref = 10.063 µA (nominal)
−
1010
(0.458).Iref = 11.069 µA (nominal)
−
1011
(0.5).Iref = 12.075 µA (nominal)
−
1100
(0.542).Iref = 13.081 µA (nominal)
−
1101
(0.583).Iref = 14.088 µA (nominal)
−
1110
(0.625).Iref = 15.094 µA (nominal)
1111
(0.667).Iref = 16.1 µA (nominal)
SIGNAL CONDITIONING
FUNCTION
INITIAL
−
reset
The radial or tracking error signal is generated by the
satellite detector signals R1 and R2. The radial error
signal can be formulated as follows:
The digital codes retrieved from the ADCs are applied to
logic circuitry to obtain the various control signals. The
signals from the central aperture diodes are processed to
obtain a normalised focus error signal.
REs = (R1 − R2) × re_gain + (R1 + R2) × re_offset
where the index ‘s’ indicates the automatic scaling
operation which is performed on the radial error signal.
This scaling is necessary to avoid non-optimum dynamic
range usage in the digital representation and reduces the
radial bandwidth spread. Furthermore, the radial error
signal will be made free from offset during start-up of the
disc.
D1 – D2 D3 – D4
FE n = --------------------- – --------------------D1 + D2 D3 + D4
where the detector set-up is assumed as shown in Fig.20.
In the event of single Foucault focusing method, the signal
conditioning can be switched under software control such
that the signal processing is as follows:
The four signals from the central aperture detectors,
together with the satellite detector signals generate a
Track Position signal (TPI) which can be formulated as
follows:
D1 – D2
FE n = 2 × --------------------D1 + D2
The error signal, FEn, is further processed by a
proportional integral and differential (PID) filter section.
TPI = sign [(D1 + D2 + D3 + D4) − (R1 + R2) × sum_gain]
where the weighting factor sum_gain is generated
internally by the SAA7327 during initialization.
A Focus OK (FOK) flag is generated by means of the
central aperture signal and an adjustable reference level.
This signal is used to provide extra protection for the
Track-Loss (TL) generation, the focus start-up procedure
and the dropout detection.
2000 Jun 26
SAA7327
27
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
handbook, full pagewidth
SATELLITE
DIODE R1
SATELLITE
DIODE R1
D1
D2
D1
D2
D4
D3
SATELLITE
DIODE R1
D1
D2
D3
D3
D4
SATELLITE
DIODE R2
SATELLITE
DIODE R2
SATELLITE
DIODE R2
single Foucault
astigmatic focus
double Foucault
MBG422
Fig.20 Detector arrangement.
7.14.3
7.14.3.1
7.14.3.2
FOCUS SERVO SYSTEM
Focus start-up
The focus control loop contains a digital PID controller
which has 5 parameters which are available to the user.
These coefficients influence the integrating (foc_int),
proportional (foc_lead_length, part of foc_parm3) and
differentiating (foc_pole_lead, part of foc_parm1) action of
the PID and a digital low-pass filter (foc_pole_noise, part
of foc_parm2) following the PID. The fifth coefficient
foc_gain influences the loop gain.
Five initially loaded coefficients influence the start-up
behaviour of the focus controller. The automatically
generated triangular voltage can be influenced by
3 parameters; for height (ramp_height) and DC offset
(ramp_offset) of the triangle and its steepness
(ramp_incr).
For protection against false focus point detections two
parameters are available which are an absolute level on
the CA-signal (CA_start) and a level on the FEn signal
(FE_start). When this CA level is reached the FOK signal
becomes true.
7.14.3.3
Dropout detection
This detector can be influenced by one parameter
(CA_drop). The FOK signal will become false and the
integrator of the PID will hold if the CA signal drops below
this programmable absolute CA level. When the
FOK signal becomes false it is assumed, initially, to be
caused by a black dot.
If the FOK signal is true and the level on the FEn signal is
reached, the focus PID is enabled to switch on when the
next zero crossing is detected in the FEn signal.
2000 Jun 26
Focus position control loop
28
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
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7.14.3.4
Focus loss detection and fast restart
7.14.4.3
Whenever FOK is false for longer than approximately
3 ms, it is assumed that the focus point is lost. A fast
restart procedure is initiated which is capable of restarting
the focus loop within 200 to 300 ms depending on the
programmed coefficients of the microcontroller.
7.14.3.5
Focus loop gain switching
Both modes of S-curve extension make use of a
track-count mechanism. In this mode, track counting
results in an ‘automatic return-to-zero track’, to avoid
major music rhythm disturbances in the audio output for
improved shock resistance. The sledge is continuously
controlled, or provided with step pulses to reduce power
consumption using the filtered value of the radial PID
output. Alternatively, the microcontroller can read the
average voltage on the radial actuator and provide the
sledge with step pulses to reduce power consumption.
Filter coefficients of the continuous sledge control can be
preset by the user.
Focus automatic gain control loop
The loop gain of the focus control loop can be corrected
automatically to eliminate tolerances in the focus loop.
This gain control injects a signal into the loop which is used
to correct the loop gain. Since this decreases the optimum
performance, the gain control should only be activated for
a short time (for example, when starting a new disc).
7.14.4
7.14.4.1
7.14.4.4
Access
The access procedure is divided into two different modes
(see Table 13), depending on the requested jump size.
RADIAL SERVO SYSTEM
Table 13 Access modes
Level initialization
ACCESS
TYPE
During start-up an automatic adjustment procedure is
activated to set the values of the radial error gain (re_gain),
offset (re_offset) and satellite sum gain (sum_gain) for
TPI level generation. The initialization procedure runs in a
radial open loop situation and is ≤300 ms. This start-up
time period may coincide with the last part of the motor
start-up time period:
Sledge jump
ACCESS
SPEED
decreasing
velocity
brake_distance - 32768 maximum
power to
sledge(1)
Note
1. Microcontroller presettable.
• Offset adjustment: the additional offset in RE due to the
limited accuracy of the start-up procedure is less than
±50 nm
The access procedure makes use of a track counting
mechanism, a velocity signal based on a fixed number of
tracks passed within a fixed time interval, a velocity set
point calculated from the number of tracks to go and a user
programmable parameter indicating the maximum sledge
performance.
• TPI level generation: the accuracy of the initialization
procedure is such that the duty factor range of TPI
becomes 0.4 < duty factor < 0.6 (default duty
factor = TPI HIGH/TPI period).
If the number of tracks remaining is greater than the
brake_distance then the sledge jump mode should be
activated or, the actuator jump should be performed.
The requested jump size together with the required sledge
breaking distance at maximum access speed defines the
brake_distance value.
Sledge control
The microcontroller can move the sledge in both directions
via the steer sledge command.
2000 Jun 26
JUMP SIZE(1)
Actuator jump 1 - brake_distance
• Automatic gain adjustment: as a result of this
initialization the amplitude of the RE signal is adjusted to
within ±10% around the nominal RE amplitude
7.14.4.2
Tracking control
The actuator is controlled using a PID loop filter with user
defined coefficients and gain. For stable operation
between the tracks, the S-curve is extended over 0.75 of
the track. On request from the microcontroller, S-curve
extension over 2.25 tracks is used, automatically changing
to access control when exceeding those 2.25 tracks.
The gain of the focus control loop (foc_gain) can be
multiplied by a factor of 2 or divided by a factor of 2 during
normal operation. The integrator value of the PID is
corrected accordingly. The differentiating (foc_pole_lead)
action of the PID can be switched at the same time as the
gain switching is performed.
7.14.3.6
SAA7327
29
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
These signals are, however, afflicted with some
uncertainties caused by:
During the actuator jump mode, velocity control with a
PI controller is used for the actuator. The sledge is then
continuously controlled using the filtered value of the radial
PID output. All filter parameters (for actuator and sledge)
are user programmable.
• Disc defects such as scratches and fingerprints
• The HF information on the disc, which is considered as
noise by the detector signals.
In the sledge jump mode maximum power (user
programmable) is applied to the sledge in the correct
direction while the actuator becomes idle (the contents of
the actuator integrator leaks to zero just after the sledge
jump mode is initiated). The actuator can be electronically
damped during sledge jump. The gain of the damping loop
is controlled via the hold_mult parameter.
In order to determine the spot position with sufficient
accuracy, extra conditions are necessary to generate a
Track Loss signal (TL) and an off-track counter value.
These extra conditions influence the maximum speed and
this implies that, internally, one of the following three
counting states is selected:
Fast track jumping circuitry can be enabled/disabled via
the xtra_preset parameter.
1. Protected state: used in normal play situations. A good
protection against false detection caused by disc
defects is important in this state.
7.14.4.5
2. Slow counting state: used in low velocity track jump
situations. In this state a fast response is important
rather than the protection against disc defects (if the
phase relationship between TL and RP of 1⁄2π radians
is affected too much, the direction cannot then be
determined accurately).
Radial automatic gain control loop
The loop gain of the radial control loop can be corrected
automatically to eliminate tolerances in the radial loop.
This gain control injects a signal into the loop which is used
to correct the loop gain. Since this decreases the optimum
performance, the gain control should only be activated for
a short time (for example, when starting a new disc).
3. Fast counting state: used in high velocity track jump
situations. Highest obtainable velocity is the most
important feature in this state.
This gain control differs from the level initialization.
The level initialization should be performed first.
The disadvantage of using the level initialization without
the gain control is that only tolerances from the front-end
are reduced.
7.14.5
7.14.6
DEFECT DETECTION
A defect detection circuit is incorporated into the
SAA7327. If a defect is detected, the radial and focus error
signals may be zeroed, resulting in better playability.
The defect detector can be switched off, applied only to
focus control or applied to both focus and radial controls
under software control (part of foc_parm1).
OFF-TRACK COUNTING
The Track Position signal (TPI) is a flag which is used to
indicate whether the radial spot is positioned on the track,
with a margin of ±1⁄4 of the track-pitch. In combination with
the radial polarity flag (RP) the relative spot position over
the tracks can be determined.
The defect detector (see Fig.21) has programmable set
points selectable by the parameter defect_parm.
handbook, full pagewidth
sat1
+
−
DECIMATION
FILTER
FAST
FILTER
SLOW
FILTER
DEFECT
GENERATION
defect
output
MBG421
sat2
Fig.21 Block diagram of defect detector.
2000 Jun 26
PROGRAMMABLE
HOLD-OFF
30
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.14.7
7.14.8.3
OFF-TRACK DETECTION
During active radial tracking, off-track detection has been
realised by continuously monitoring the off-track counter
value. The off-track flag becomes valid whenever the
off-track counter value is not equal to zero. Depending on
the type of extended S-curve, the off-track counter is reset
after 0.75 extend or at the original track in the 2.25 track
extend mode.
7.14.8
7.14.8.1
SAA7327
Automatic error handling
Three Watchdogs are present:
• Focus: detects focus dropout of longer than 3 ms, sets
focus lost interrupt, switches off radial and sledge
servos, disables drive to disc motor
• Radial play: started when radial servo is on-track mode
and a first subcode frame is found; detects when
maximum time between two subcode frames exceeds
time set by playwatchtime parameter; then sets radial
error interrupt, switches radial and sledge servos off,
puts disc motor in jump mode
HIGH-LEVEL FEATURES
Interrupt mechanism and STATUS pin
• Radial jump: active when radial servo is in long jump or
short jump modes; detects when the off-track counter
value decreases by less than 4 tracks between two
readings (time interval set by jumpwatchtime
parameter); then sets radial jump error, switches radial
and sledge servos off to cancel jump.
The STATUS pin is an output which is active LOW, its
output is selected by decoder register 7 to be either the
decoder status bit (active LOW) selected by decoder
register 2 (only available in 4-wire bus mode) or the
interrupt signal generated by the servo part.
8 signals from the interrupt status register are selectable
from the servo part via the interrupt_mask parameter.
The interrupt is reset by sending the read high-level status
command. The 8 signals are as follows:
The focus Watchdog is always active, the radial
Watchdogs are selectable via the radcontrol parameter.
• Focus lost: dropout of longer than 3 ms
7.14.8.4
• Subcode ready
Two automatic sequencers are implemented (and must be
initialized after power-on):
• Subcode absolute seconds changed
Automatic sequencers and timer interrupts
• Autostart sequencer: controls the start-up of focus,
radial and motor
• Subcode discontinuity detected: new subcode time
before previous subcode time, or more than 10 frames
later than previous subcode time
• Autostop sequencer: brakes the disc and shuts down
servos.
• Radial error: during radial on-track, no new subcode
frame occurs within time defined by playwatchtime
parameter; during radial jump, less than 4 tracks have
been crossed during time defined by jumpwatchtime
parameter
When the automatic sequencers are not used it is possible
to generate timer interrupts, defined by the
time_parameter coefficient.
• Autosequencer state change
7.14.8.5
• Autosequencer error
The read high-level status command can be used to obtain
the interrupt, decoder, autosequencer status registers and
the motor start time. Use of the read high-level status
command clears the interrupt status register, and
re-enables the subcode read via a servo command.
• Subcode interface blocked: the internal decoder
interface is being used.
It should be noted that if the STATUS pin output is selected
via decoder register 2 and either the microcontroller writes
a different value to decoder register 2 or the decoder
interface is enabled then the STATUS output will change.
7.14.8.2
7.14.9
DRIVER INTERFACE
The control signals (pins RA, FO and SL) for the
mechanism actuators are pulse density modulated.
The modulating frequency can be set to either
1.0584 MHz (DSD mode) or 2.1168 MHz; controlled via
the xtra_preset parameter. An analog representation of
the output signals can be achieved by connecting a
1st-order low-pass filter to the outputs.
Decoder interface
The decoder interface allows decoder registers 0 to F to
be programmed and subcode Q-channel data to be read
via servo commands. The interface is enabled/disabled by
the preset latch command (and the xtra_preset
parameter).
2000 Jun 26
High-level status
31
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Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.15
During reset (i.e. RESET pin is held LOW)
the RA, FO and SL pins are high-impedance.
• 4-wire bus mode: protocol compatible with SAA7345
(CD6) and TDA1301 (DSIC2) where:
The LDON pin (open-drain output) is used to switch the
laser off and on. When the laser is on, the output is
high-impedance. The action of the LDON pin is controlled
by the xtra_preset parameter; the pin is automatically
driven if the focus control loop is active.
– SCL = serial clock
– SDA = serial data
– RAB = R/W control and data strobe (active HIGH) for
writing to decoder registers 0 to F, reading status bit
selected via decoder register 2 and reading
Q-channel subcode
7.14.11 RADIAL SHOCK DETECTOR
The shock detector (see Fig.22) can be switched on during
normal track following, and detects within an adjustable
frequency whether disturbances in the radial spot position
relative to the track exceed an adjustable level (controlled
by shock_level).
– SILD = R/W control and data strobe (active LOW) for
servo commands.
• I2C-bus mode: I2C-bus protocol where SAA7327
behaves as slave device, activated by setting
RAB = HIGH and SILD = LOW where:
Every time the radial tracking error exceeds this level the
radial control bandwidth is switched to twice its original
bandwidth and the loop gain is increased by a factor of 4.
– I2C-bus slave address (write mode) = 30H
– I2C-bus slave address (read mode) = 31H
The shock detection level is adjustable in 16 steps from
0% to 100% of the traverse radial amplitude which is sent
to an amplitude detection unit via an adjustable band-pass
filter (controlled by sledge_parm1); lower corner frequency
can be set at either 0 or 20 Hz, and upper corner
frequency at 750 or 1850 Hz. The shock detector is
switched off automatically during jump mode.
RE
HIGH-PASS FILTER
(0 or 20 Hz)
Microcontroller interface
Communication on the microcontroller interface can be
set-up in two different modes:
7.14.10 LASER INTERFACE
handbook, full pagewidth
SAA7327
– Maximum data transfer rate = 400 kbits/s.
It should be noted that only servo commands can be used
therefore, writing to decoder registers 0 to F, reading
decoder status and reading Q-channel subcode data must
be performed by servo commands.
LOW-PASS FILTER
(750 or 1850 Hz)
AMPLITUDE
DETECTION
SHOCK
OUTPUT
MGC914
Fig.22 Block diagram of radial shock detector.
2000 Jun 26
32
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.15.1
7.15.1.1
7.15.1.4
MICROCONTROLLER INTERFACE (4-WIRE BUS MODE)
Writing data to registers 0 to F
It should be noted that SILD must be held HIGH; after
subcode read starts, the microcontroller may take as long
as it wants to terminate the read operation; when enough
subcode has been read (1 to 96 bits), terminate reading by
pulling RAB LOW.
It should be noted that SILD must be held HIGH; A3 to A0
identifies the register number and D3 to D0 is the data.
The data is latched into the register on the LOW-to-HIGH
transition of RAB.
Alternatively, the Q-channel subcode can be read using a
servo command as follows:
Writing repeated data to registers 0 to F
• Use the read high-level status command to monitor the
subcode ready signal
The same data can be repeated several times (e.g. for a
fade function) by applying extra RAB pulses as shown in
Fig.24. It should be noted that SCL must stay HIGH
between RAB pulses.
7.15.1.3
Reading Q-channel subcode
To read the Q-channel subcode direct in the 4-wire bus
mode, the SUBQREADY-I signal should be selected as
status signal. The subcode read protocol is illustrated in
Fig.26.
The sixteen 4-bit programmable configuration registers,
0 to F (see Table 14), can be written to via the
microcontroller interface using the protocol shown in
Fig.23.
7.15.1.2
SAA7327
• Send the read subcode command, and read the
required number of bytes (up to 12)
• Send the read high-level status command; to re-enable
the decoder interface.
Reading decoder status information on SDA
There are several internal status signals, selected via
register 2, which can be made available on the SDA line:
7.15.1.5
SUBQREADY-I: LOW if new subcode word is ready in
Q-channel register
Behaviour of the SUBQREADY-I signal
When the CRC of the Q-channel word is good, and no
subcode is being read, the SUBQREADY-I status signal
will react as shown in Fig.27. When the CRC is good and
the subcode is being read, the timing in Fig.28 applies.
MOTSTART1: HIGH if motor is turning at 75% or more
of nominal speed
If t1 (SUBQREADY-I status LOW to end of subcode read)
is below 2.6/n ms, then t2 = 13.1/n ms (i.e.: the
microcontroller can read all subcode frames if it completes
the read operation within 2.6/n ms after the subcode is
ready). If these criteria are not met, it is only possible to
guarantee that t3 will be below 26.2/n ms (approximately).
MOTSTART2: HIGH if motor is turning at 50% or more
of nominal speed
MOTSTOP: HIGH if motor is turning at 12% or less of
nominal speed; can be set to indicate 6% or less
(instead of 12% or less) via register E
PLL lock: HIGH if sync coincidence signals are found
If subcode frames with failed CRCs are present, the
t2 and t3 times will be increased by 13.1/n ms for each
defective subcode frame.
V1: follows input on pin V1
V2: follows input on pin V2
MOTOR-OV: HIGH if the motor servo output stage
saturates
It should be noted that in the lock-to-disc mode ‘n’ is
replaced by ‘d’, which is the disc speed factor.
FIFO-OV: HIGH if FIFO overflows
7.15.1.6
SHOCK: MOTSTART2 + PLL Lock + MOTOR-OV +
FIFO-OV + servo interrupt signal + OTD (HIGH if shock
detected)
A write data command is used to transfer data (a number
of bytes) from the microcontroller, using the protocol
shown in Fig.29. The first of these bytes is the command
byte and the following are data bytes; the number
(between 1 and 7) depends on the command byte.
LA-SHOCK: latched SHOCK signal.
The status read protocol is shown in Fig.25. It should be
noted that SILD must be held HIGH.
2000 Jun 26
Write servo commands
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Philips Semiconductors
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Digital servo processor and Compact Disc
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It should be noted that RAB must be held LOW;
the command or data is interpreted by the SAA7327 after
the HIGH-to-LOW transition of SILD; there must be a
minimum time of 70 µs between SILD pulses.
• Send START condition
7.15.1.7
• Write data byte 2
• Send address 30H (write)
• Write command byte
• Write data byte 1
Writing repeated data in servo commands
• Write data byte 3
The same data byte can be repeated by applying extra
SILD pulses as illustrated in Fig.30. SCL must be HIGH
between the SILD pulses.
7.15.1.8
• Send STOP condition.
It should be noted that more than one command can be
sent in one write sequence.
Read servo commands
The sequence for a read data command (that reads 2 data
bytes) is as follows:
A read data command is used to transfer data (status
information) to the microcontroller, using the protocol
shown in Fig.31. The first byte written determines the type
of command. After this byte a variable number of bytes can
be read. It should be noted that RAB must be held LOW;
after the end of the command byte (LOW-to-HIGH
transition on SILD) there must be a delay of 70 µs before
reading data is started (i.e. the next HIGH-to-LOW
transition on SILD); there must be a minimum time of 70 µs
between SILD pulses.
7.15.2
SAA7327
• Send START condition
• Send address 30H (write)
• Write command byte
• Send STOP condition
• Send START condition
• Send address 31H (read)
• Read data byte 1
• Read data byte 2
MICROCONTROLLER INTERFACE (I2C-BUS MODE)
• Send STOP condition.
Bytes are transferred over the interface in groups (i.e.
servo commands) of which there are two types: write data
commands and read data commands.
It should be noted that the timing constraints specified for
the read and write servo commands must still be adhered
to.
The sequence for a write data command (that requires
3 data bytes) is as follows:
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller)
SDA
(SAA7327)
A3
A2
A1
A0
D3
D2
D1
D0
high-impedance
MGS236
Fig.23 Microcontroller write protocol for registers 0 to F.
2000 Jun 26
34
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller)
A3
SDA
(SAA7327)
A2
A1
A0
D3
D2
D1
D0
high-impedance
MGS237
Fig.24 Microcontroller write protocol for registers 0 to F (repeat mode).
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller)
high-impedance
SDA
(SAA7327)
STATUS
MGS238
Fig.25 Microcontroller read protocol for decoder status on SDA.
2000 Jun 26
35
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
RAB
(microcontroller)
SCL
(microcontroller)
CRC
OK
SDA
(SAA7327)
Q1
Q2
Q3
Qn – 2 Qn – 1 Qn
MGS239
STATUS
Fig.26 Microcontroller protocol for reading Q-channel subcode.
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(SAA7327)
high-impedance
CRC OK
10.8/n ms
CRC OK
15.4/n ms
2.3/n
ms
READ start allowed
Fig.27 SUBQREADY-I status timing when no subcode is read.
2000 Jun 26
36
MGS240
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
t2
t1
t3
RAB
(microcontroller)
SCL
(microcontroller)
SDA
(SAA7327)
Q1
Q2
Q3
Qn
MGS241
Fig.28 SUBQREADY-I status timing when subcode is read.
SILD
handbook, full pagewidth
(microcontroller)
SCL
(microcontroller)
SDA
(microcontroller)
D7
D6
D5
D4
D3
D2
D1
D0
command or data byte
SDA
(SAA7327)
high-impedance
microcontroller write (one byte: command or data)
SILD
(microcontroller)
SDA
(microcontroller)
COMMAND
DATA1
DATA2
DATA3
MGS242
microcontroller write (full command)
Fig.29 Microcontroller protocol for write servo commands.
2000 Jun 26
37
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
handbook, full pagewidth
SILD
(microcontroller)
SDA
(microcontroller)
COMMAND
DATA1
MBG413
microcontroller write (full command)
Fig.30 Microcontroller protocol for repeated data in write servo commands.
SILD
(microcontroller)
handbook, full pagewidth
SCL
(microcontroller)
SDA (SAA7327)
D7
D6
D5
D4
D3
D2
D1
D0
data byte
microcontroller read (one data byte)
SILD
(microcontroller)
DATA1
SDA (SAA7327)
SDA
(microcontroller)
DATA2
DATA3
COMMAND
MGS243
microcontroller read (full command)
Fig.31 Microcontroller protocol for read servo commands.
2000 Jun 26
38
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.15.3
When SHADEN is set to logic 0 (decoder register F set to
XXX0) all subsequent addresses are decoded by the main
decoder registers again.
DECODER REGISTERS AND SHADOW REGISTERS
To maintain compatibility with the SAA737x series,
decoder registers 0 to F are identical to the SAA7370.
However, to control the extra functionality of SAA7327, a
new set of registers called shadow registers have been
implemented.
Access to decoder register F is always enabled so that
SHADEN can be set or reset as required.
The SHADEN bit and subsequent shadow registers are
programmed identically to the main decoder registers, i.e.
they can be directly programmed when using SAA7327 in
4-wire mode or programmed via the servo interface when
using 3-wire or I2C-bus modes.
These are accessed by using the LSB of decoder
register F. This bit is called SHADEN (shadow registers
enable) on SAA7327. When this bit is set to logic 1 (i.e.
decoder register F set to XXX1), any subsequent
addresses will be decoded by the shadow registers.
In fact, only four addresses are implemented as shadow
registers; 3, 7, A and C. Any other addresses sent while
SHADEN = 1 are invalid and have no effect.
7.15.4
SAA7327
The main decoder registers are shown in Table 14. The
functions implemented using shadow registers are shown
in Table 16.
SUMMARY OF FUNCTIONS CONTROLLED BY DECODER REGISTERS 0 TO F
Table 14 Registers 0 to F
REGISTER
0
(fade and
attenuation)
1
(motor mode)
2000 Jun 26
DATA
0000
0000
mute
0010
attenuate
−
0001
full-scale
−
0100
step down
−
0101
step up
−
X000
motor off mode
X001
motor stop mode 1
−
X010
motor stop mode 2
−
X011
motor start mode 1
−
X100
motor start mode 2
−
X101
motor jump mode
−
X111
motor play mode
−
0001
FUNCTION
INITIAL(1)
ADDRESS
reset
reset
X110
motor jump mode 1
−
1XXX
anti-windup active
−
0XXX
anti-windup off
39
reset
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
INITIAL(1)
REGISTER
ADDRESS
DATA
2
(status control
to servo part not the
STATUS pin)
0010
0000
status = SUBQREADY-I
0001
status = MOTSTART1
−
0010
status = MOTSTART2
−
0011
status = MOTSTOP
−
0100
status = PLL Lock
−
0101
status = V1
−
0110
status = V2
−
0111
status = MOTOR-OV
−
1000
status = FIFO overflow
−
1001
status = shock detect
−
1010
status = latched shock detect
−
3
(DAC output)
4
(motor gain)
5
(motor
bandwidth)
2000 Jun 26
0011
0100
0101
FUNCTION
SAA7327
reset
1011
status = latched shock detect reset
−
1010
I2S-bus; CD-ROM mode
−
1011
EIAJ; CD-ROM mode
−
1100
I2S-bus;
1111
I2S-bus; 18-bit; 2fs mode
−
1110
I2S-bus;
−
18-bit; 4fs mode
16-bit; fs mode
reset
0000
EIAJ; 16-bit; 4fs
−
0011
EIAJ; 16-bit; 2fs
−
0010
EIAJ; 16-bit; fs
−
0100
EIAJ; 18-bit; 4fs
−
0111
EIAJ; 18-bit; 2fs
−
0110
EIAJ; 18-bit; fs
−
X000
motor gain G = 3.2
reset
X001
motor gain G = 4.0
−
X010
motor gain G = 6.4
−
X011
motor gain G = 8.0
−
X100
motor gain G = 12.8
−
X101
motor gain G = 16.0
−
X110
motor gain G = 25.6
−
−
X111
motor gain G = 32.0
0XXX
disable comparator clock divider
1XXX
enable comparator clock divider; only if SELLPLL
set HIGH
XX00
motor f4 = 0.5 × n Hz
reset
XX01
motor f4 = 0.7 × n Hz
−
XX10
motor f4 = 1.4 × n Hz
−
XX11
motor f4 = 2.8 × n Hz
−
00XX
motor f3 = 0.85 × n Hz
reset
01XX
motor f3 = 1.71 × n Hz
−
10XX
motor f3 = 3.42 × n Hz
−
40
reset
−
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
REGISTER
6
(motor output
configuration)
7
(DAC output
and status
control)
ADDRESS
DATA
0110
XX00
0111
A
(EBU output)
B
(speed control)
2000 Jun 26
1001
1010
1011
INITIAL(1)
motor power maximum 37%
reset
XX01
motor power maximum 50%
−
XX10
motor power maximum 75%
−
XX11
motor power maximum 100%
−
00XX
MOTO1, MOTO2 pins 3-state
reset
01XX
motor PWM mode
−
10XX
motor PDM mode
−
11XX
motor CDV mode
−
XX00
interrupt signal from servo at STATUS pin
XX10
status bit from decoder status register at STATUS
pin
X0XX
DAC data normal value
X1XX
DAC data inverted value
0XXX
left channel first at DAC (WCLK normal)
1XXX
right channel first at DAC (WCLK inverted)
−
see Table 15
−
8
(PLL loop filter
bandwidth)
9
(PLL
equalization)
FUNCTION
SAA7327
reset
−
reset
−
reset
0011
PLL loop filter equalization
reset
0001
PLL 30 ns over-equalization
−
0010
PLL 15 ns over-equalization
−
0100
PLL 15 ns under-equalization
−
0101
PLL 30 ns under-equalization
−
XX0X
EBU data before concealment
XX1X
EBU data after concealment and fade
reset
X0X0
level II clock accuracy (<1000 ppm)
reset
X0X1
level I clock accuracy (<50 ppm)
−
X1X0
level III clock accuracy (>1000 ppm)
−
X1X1
EBU off - output low
−
0XXX
flags in EBU off
reset
1XXX
flags in EBU on
−
X0XX
33.8688 MHz crystal present, or 8.4672 MHz (or
16.9344 MHz) crystal with SELPLL set HIGH
−
reset
−
X1XX
16.9344 MHz crystal present
0XXX
single-speed mode
reset
1XXX
double-speed mode
−
XX00
standby 1: ‘CD-STOP’ mode
reset
XX10
standby 2: ‘CD-PAUSE’ mode
−
XX11
operating mode
−
41
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
REGISTER
C
(versatile pins
interface)
D
(versatile pins
interface)
E
F
(subcode
interface and
shadow
register
enable)
DATA
1100
XXX1
external off-track signal input at V1
XXX0
internal off-track signal used (V1 may be read via
status)
XX0X
kill-L at KILL output, kill-R at V3 output
001X
V3 = 0; single KILL output
reset
011X
V3 = 1; single KILL output
−
0000
4-line motor (using V4 and V5)
−
XX01
Q to W subcode at V4
−
XX10
V4 = 0
−
XX11
V4 = 1
reset
01XX
de-emphasis signal at V5, no internal
de-emphasis filter
−
10XX
V5 = 0
−
reset
1110
1111
−
reset
−
11XX
V5 = 1
00XX
audio features disabled
−
01XX
audio features enabled
reset
XX0X
lock-to-disc mode disabled
reset
XX1X
lock-to-disc mode enabled
−
XXX0
motor brakes to 12%
XXX1
motor brakes to 6%
X0XX
subcode interface off
reset
X1XX
subcode interface on
−
0XXX
4-wire subcode
reset
1XXX
3-wire subcode
−
XXX0
SHADEN = 0; shadow registers not enabled;
addresses will be decoded by main decoder
registers
reset
XXX1
SHADEN = 1; shadow registers enabled; all
subsequent addresses will be decoded by
shadow registers, not decoder registers
−
Note
1. The initial column shows the power-on reset state.
2000 Jun 26
INITIAL(1)
ADDRESS
1101
FUNCTION
SAA7327
42
reset
−
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
Table 15 Loop filter bandwidth
FUNCTION
REGISTER
ADDRESS
8
(PLL loop filter
bandwidth)
1000
DATA
LOOP
BANDWIDTH
(Hz)
INTERNAL
BANDWIDTH
(Hz)
LOW-PASS
BANDWIDTH
(Hz)
INITIAL(1)
0000
1640 × n
525 × n
8400 × n
−
0001
3279 × n
263 × n
16800 × n
−
0010
6560 × n
131 × n
33600 × n
−
0100
1640 × n
1050 × n
8400 × n
−
0101
3279 × n
525 × n
16800 × n
−
0110
6560 × n
263 × n
33600 × n
−
1000
1640 × n
2101 × n
8400 × n
−
1001
3279 × n
1050 × n
16800 × n
reset
1010
6560 × n
525 × n
33600 × n
−
1100
1640 × n
4200 × n
8400 × n
−
1101
3279 × n
2101 × n
16800 × n
−
1110
6560 × n
1050 × n
33600 × n
−
Note
1. The initial column shows the power-on reset state.
7.15.5
SUMMARY OF FUNCTIONS CONTROLLED BY SHADOW REGISTERS
Table 16 Shadow register settings
SHADEN BIT
1
2000 Jun 26
SHADOW
REGISTER
3
control of
versatile and
clock pins
ADDRESS
DATA
0011
XXX0
select CL4 on CL11/4 output
reset
XXX1
select CL11 on CL11/4 output
−
XX0X
enable CL11/4 output pin
reset
XX1X
set CL11/4 output pin to
high-impedance
−
X0XX
enable CL16 output pin
reset
X1XX
set CL16 output pin to
high-impedance
−
0XXX
V2/V3 pin configured as V2 input
1XXX
V2/V3 pin configured as V3 output
(open-drain)
43
FUNCTION
INITIAL
reset
−
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SHADEN BIT
1
SHADOW
REGISTER
7
control of
onboard DAC
ADDRESS
DATA
0111
XXX0
hold onboard DAC outputs at zero
XXX1
enable onboard DAC outputs
XX0X
use external DAC or route audio
data into onboard DAC (loopback
mode)
XX1X
route audio data into onboard DAC
(non-loopback mode)
X1XX
use internal reference for servo
reference voltage
reset
X0XX
use external reference for servo
reference voltage
−
0000
(0.042).Iref = 1.006 µA (nominal)
−
0001
(0.083).Iref = 2.013 µA (nominal)
−
0010
(0.125).Iref = 3.019 µA (nominal)
−
0011
(0.167).Iref = 4.025 µA (nominal)
−
0100
(0.208).Iref = 5.031 µA (nominal)
−
0101
(0.25).Iref = 6.034 µA (nominal)
−
0110
(0.292).Iref = 7.044 µA (nominal)
−
0111
(0.333).Iref = 8.05 µA (nominal)
−
1000
(0.375).Iref = 9.056 µA (nominal)
−
1001
(0.417).Iref = 10.063 µA (nominal)
−
1010
(0.458).Iref = 11.069 µA (nominal)
−
1011
(0.5).Iref = 12.075 µA (nominal)
−
1100
(0.542).Iref = 13.081 µA (nominal)
−
1101
(0.583).Iref = 14.088 µA (nominal)
−
1110
(0.625).Iref = 15.094 µA (nominal)
1111
(0.667).Iref = 16.1 µA (nominal)
7
servo
reference
pin 7, VRIN
1
2000 Jun 26
A
signal
magnitude
control for
diodes
D1 to D4
SAA7327
1010
44
FUNCTION
INITIAL
reset
−
reset
−
−
reset
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SHADEN BIT
1
2000 Jun 26
SHADOW
REGISTER
C
signal
magnitude
control for
diodes
R1 and R2
SAA7327
ADDRESS
DATA
1100
0000
(0.042).Iref = 1.006 µA (nominal)
−
0001
(0.083).Iref = 2.013 µA (nominal)
−
0010
(0.125).Iref = 3.019 µA (nominal)
−
0011
(0.167).Iref = 4.025 µA (nominal)
−
0100
(0.208).Iref = 5.031 µA (nominal)
−
0101
(0.25).Iref = 6.034 µA (nominal)
−
0110
(0.292).Iref = 7.044 µA (nominal)
−
0111
(0.333).Iref = 8.05 µA (nominal)
−
1000
(0.375).Iref = 9.056 µA (nominal)
−
1001
(0.417).Iref = 10.063 µA (nominal)
−
1010
(0.458).Iref = 11.069 µA (nominal)
−
1011
(0.5).Iref = 12.075 µA (nominal)
−
1100
(0.542).Iref = 13.081 µA (nominal)
−
1101
(0.583).Iref = 14.088 µA (nominal)
−
1110
(0.625).Iref = 15.094 µA (nominal)
1111
(0.667).Iref = 16.1 µA (nominal)
45
FUNCTION
INITIAL
−
reset
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.15.6
SAA7327
SUMMARY OF SERVO COMMANDS
A list of the servo commands is given in Table 17. These are fully compatible with SAA7370.
Table 17 SAA7327 servo commands
COMMANDS
CODE
BYTES
PARAMETERS
Write_focus_coefs1
17H
7
<foc_parm3> <foc_int> <ramp_incr> <ramp_height>
<ramp_offset> <FE_start> <foc_gain>
Write_focus_coefs2
27H
7
<defect_parm> <rad_parm_jump> <vel_parm2>
<vel_parm1> <foc_parm1> <foc_parm2> <CA_drop>
Write_focus_command
33H
3
<foc_mask> <foc_stat> <shock_level>
Focus_gain_up
42H
2
<foc_gain> <foc_parm1>
Focus_gain_down
62H
2
<foc_gain> <foc_parm1>
Write_radial coefs
57H
7
<rad_length_lead> <rad_int> <rad_parm_play>
<rad_pole_noise> <rad_gain> <sledge_parm2>
<sledge_parm_1>
Preset_Latch
81H
1
<chip_init>
Radial_off
C1H
1
1CH
Radial_init
C1H
1
3CH
Short_jump
C3H
3
<tracks_hi> <tracks_lo> <rad_stat>
Long_jump
C5H
5
<brake_dist> <sledge_U_max> <tracks_hi> <tracks_lo>
<rad_stat>
Steer_sledge
B1H
1
<sledge_level>
Preset_init
93H
3
<re_offset> <re_gain> <sum_gain>
Write_decoder_reg(1)
D1H
1
<decoder_reg_data>
Write_parameter
A2H
2
<param_ram_addr> <param_data>
Read_Q_subcode(1)(2)
0H
up to 12
<Q_sub1 to 10> <peak_l> <peak_r>
Read_status
70H
up to 5
<foc_stat> <rad_stat> <rad_int_lpf> <tracks_hi>
<tracks_lo>
Read_hilevel_status(3)
E0H
up to 4
<intreq> <dec_stat> <seq_stat> <motor_start_time>
Read_aux_status
F0H
up to 3
<re_offset> <re_gain> <sum_gain>
Write commands
Read commands
Notes
1. These commands only available when internal decoder interface is enabled.
2. <peak_l> and <peak_r> bytes are clocked out LSB first.
3. Decoder status flag information in <dec_stat> is only valid when the internal decoder interface is enabled.
2000 Jun 26
46
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
7.15.7
SAA7327
SUMMARY OF SERVO COMMAND PARAMETERS
Table 18 Servo command parameters
PARAMETER
foc_parm_1
RAM
ADDRESS
AFFECTS
POR VALUE
−
focus PID
−
DETERMINES
end of focus lead
defect detector enabling
foc_parm_2
−
focus PID
−
foc_parm_3
−
focus PID
−
focus low-pass
focus error normalising
focus lead length
minimum light level
foc_int
14H
focus PID
−
foc_gain
15H
focus PID
70H
CA_drop
12H
focus PID
−
sensitivity of dropout detector
ramp_offset
16H
focus ramp
−
asymmetry of focus ramp
ramp_height
18H
focus ramp
−
peak-to-peak value of ramp voltage
−
focus ramp
−
slope of ramp voltage
FE_start
19H
focus ramp
−
minimum value of focus error
rad_parm_play
28H
radial PID
−
end of radial lead
rad_pole_noise
29H
radial PID
−
radial low-pass
rad_length_lead
1CH
radial PID
−
length of radial lead
rad_int
1EH
radial PID
−
radial integrator crossover frequency
rad_gain
2AH
radial PID
70H
rad_parm_jump
27H
radial jump
−
filter during jump
vel_parm1
1FH
radial jump
−
PI controller crossover frequencies
vel_parm2
32H
radial jump
−
jump pre-defined profile
speed_threshold
48H
radial jump
−
maximum speed in fastrad mode
hold_mult
49H
radial jump
00H
ramp_incr
focus integrator crossover frequency
focus PID loop gain
radial loop gain
electronic damping
sledge bandwidth during jump
brake_dist_max
21H
radial jump
−
sledge_long_brake
maximum sledge distance allowed in fast
actuator steered mode
58H
radial jump
FFH
sledge_Umax
−
sledge
−
voltage on sledge during long jump
brake distance of sledge
sledge_level
−
sledge
−
voltage on sledge when steered
sledge_parm_1
36H
sledge
−
sledge integrator crossover frequency
sledge_parm_2
17H
sledge
−
sledge low-pass frequencies
sledge gain
sledge operation mode
sledge_pulse1
46H
pulsed sledge
−
pulse width
sledge_pulse2
64H
pulsed sledge
−
pulse height
−
defect detector
−
defect detector setting
−
shock detector
−
shock detector operation
54H
Watchdog
−
radial on-track Watchdog time
defect_parm
shock_level
playwatchtime
2000 Jun 26
47
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
RAM
ADDRESS
AFFECTS
POR VALUE
jumpwatchtime
57H
Watchdog
−
radial jump Watchdog time-out
radcontrol
59H
Watchdog
−
enable/disable automatic radial off feature
−
set-up
−
enable/disable decoder interface
4AH
set-up
38H
PARAMETER
chip_init
xtra_preset
DETERMINES
laser on/off
RA, FO and SL PDM modulating frequency
fast jumping circuit on/off
decoder
interface
−
decoder part commands
53H
STATUS pin
−
enabled interrupts
42H
autosequencer
−
autosequencer control
focus_start_time
5EH
autosequencer
−
focus start time
motor_start_time1
5FH
autosequencer
−
motor start 1 time
motor_start_time2
60H
autosequencer
−
motor start 2 time
radial_init_time
61H
autosequencer
−
radial initialization time
brake_time
62H
autosequencer
−
brake time
RadCmdByte
63H
autosequencer
−
radial command byte
osc_inc
68H
focus/radial
AGC
−
AGC control
cd6cmd
4DH
interrupt_mask
seq_control
frequency of injected signal
phase_shift
67H
focus/radial
AGC
−
phase shift of injected signal
level1
69H
focus/radial
AGC
−
amplitude of signal injected
level2
6AH
focus/radial
AGC
−
amplitude of signal injected
agc_gain
6CH
focus/radial
AGC
−
focus/radial gain
2000 Jun 26
48
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
VDD
supply voltage
VI(max)
maximum input voltage
CONDITIONS
MIN.
−0.5
note 1
MAX.
UNIT
+3.6
V
any input
−0.5
VDD + 0.5
V
pins SDA, SCL, RAB and SILD
−0.5
+5.5
V
VO
output voltage (any output)
−0.5
+3.6
V
VDDdiff
difference between VDDA, VDDD and Vpos
−
± 0.25
V
IO
output current (continuous)
−
± 20
mA
II(d)
DC input diode current (continuous)
−
± 20
mA
Ves
electrostatic handling
note 2
−2000
+2000
V
note 3
−200
+200
V
Tamb
ambient temperature
−10
+70
°C
Tstg
storage temperature
−55
+125
°C
Notes
1. All VDD (and Vpos) connections and VSS (and Vneg) connections must be made externally to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
9 CHARACTERISTICS
VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
IDD
supply current
3.0
3.3
3.6
V
VDD = 3.3 V; n = 1
mode
−
20
−
mA
VDD = 3.3 V; n = 2
mode
−
25
−
mA
Bitstream DAC output (VDDD = 3.3 V, Vpos = 3.3 V; VSS = 0 V, Vneg = 0 V; Tamb = 25 °C)
DIFFERENTIAL OUTPUTS: PINS LN, LP, RN AND RP
S/N
signal-to-noise ratio
(THD + N)/S total harmonic distortion
plus noise-to-signal ratio
EIAJ A-weighted;
note 1
90
95
−
dB
at 0 dB; note 1
−
−83
−80
dB
Servo and decoder analog functions (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 °C)
REFERENCE GENERATOR: PIN IREF
VIref
reference voltage level
Iref
input reference current
RIref
external resistor
2000 Jun 26
±2%
49
1.14
1.2
1.26
V
−
40
−
µA
−
30
−
kΩ
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SYMBOL
PARAMETER
CONDITIONS
SAA7327
MIN.
TYP.
MAX.
UNIT
Decoder analog front-end (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 °C)
COMPARATOR INPUTS: PINS HFIN AND HFREF
8
−
70
MHz
switching voltage
threshold
−
0.5VDD
−
V
input voltage level (HFIN)
−
1.0
−
V
fclk
clock frequency
Vth(sw)
Vi(HFIN)
note 2
Servo analog part (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 °C; RIref = 30 kΩ)
PINS D1 TO D4; R1 AND R2
ID(max)
maximum input current
for central diode input
signal
note 3
1.006
−
16.1
µA
IR(max)
maximum input current
for satellite diode input
signal
note 3
1.006
−
16.1
µA
VRIN
internally generated
reference voltage
note 4
0.64
−
0.9
V
externally generated
reference voltage applied
to VRIN (pin 7)
note 4
0.5
−
0.5VDD + 0.1
V
at 0 dB; note 5
−
−50
−45
dB
−
55
−
dB
(THD + N)/S total harmonic distortion
plus noise-to-signal ratio
S/N
signal-to-noise ratio
PSRR
power supply ripple
rejection at VDDA2
note 6
−
45
−
dB
Gtol
gain tolerance
note 7
−20
0
+20
%
∆Gv
variation of gain between
channels
−
−
2
%
αcs
channel separation
−
60
−
dB
Digital inputs
PINS RESET AND V1 (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS)
Vthr(sw)
switching voltage
threshold rising
−
−
0.8VDDD
V
Vthf(sw)
switching voltage
threshold falling
0.2VDDD
−
−
V
Vhys
hysteresis voltage
0.4
−
−
V
Ri(pu)
input pull-up resistance
Ci
input capacitance
tresL
reset pulse width
(active LOW)
2000 Jun 26
Vi = 0 V
RESET only
50
−
160
−
kΩ
−
−
10
pF
1
−
−
µs
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SYMBOL
PARAMETER
CONDITIONS
SAA7327
MIN.
TYP.
MAX.
UNIT
PIN SELPLL (CMOS INPUT WITH PULL-UP RESISTOR)
VIL
LOW-level input voltage
−0.3
−
+0.3VDDD
V
VIH
HIGH-level input voltage
0.7VDDD
−
VDDD + 0.3
V
Ri(pu)
input pull-up resistance
−
160
−
kΩ
Ci
input capacitance
−
−
10
pF
Vi = 0 V
PINS TEST1, TEST2 AND TEST3 (CMOS INPUTS WITH PULL-DOWN RESISTORS)
VIL
LOW-level input voltage
−0.3
−
+0.3VDDD
V
VIH
HIGH-level input voltage
0.7VDDD
−
VDDD + 0.3
V
Ri(pu)
input pull-down
resistance
−
160
−
kΩ
Ci
input capacitance
−
−
10
pF
−0.3
−
+0.3VDDD
V
Vi = VDDD
INPUT: RCK, WCLI, SDI AND SCLI (CMOS INPUTS)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
ILI
input leakage current
Ci
input capacitance
Vi = 0 to VDDD
0.7VDDD
−
VDDD + 0.3
V
−10
−
+10
µA
−
−
10
pF
PINS SCL, SILD AND RAB (5 V TOLERANT CMOS INPUTS)
VIL
LOW-level input voltage
−0.3
−
+0.2VDDD
V
VIH
HIGH-level input voltage
0.8VDDD
−
5.5
V
ILI
input leakage current
−10
−
+10
µA
Ci
input capacitance
−
−
10
pF
0
−
0.4
V
Vi = 0 to VDDD
Digital outputs
PINS V4 AND V5
VOL
LOW-level output voltage
IOL = 4 mA
VOH
HIGH-level output voltage IOH = −4 mA
VDDD − 0.4 −
VDDD
V
CL
load capacitance
−
−
100
pF
to(r)
output rise time
CL = 20 pF;
0.4 to (VDDD − 0.4 V
−
−
10
ns
to(f)
output fall time
CL = 20 pF;
(VDDD − 0.4) to 0.4 V
−
−
10
ns
0
−
0.4
V
−
−
2
mA
Open-drain outputs
PINS CFLG, STATUS, KILL AND LDON (OPEN-DRAIN OUTPUT)
VOL
LOW-level output voltage
IOL
LOW-level output current
CL
load capacitance
to(f)
output fall time
2000 Jun 26
IOL = 1 mA
CL = 50 pF;
(VDDD − 0.4) to 0.4 V
51
−
−
50
pF
−
−
30
ns
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SYMBOL
PARAMETER
CONDITIONS
SAA7327
MIN.
TYP.
MAX.
UNIT
3-state outputs
PINS EF, SCLK, WCLK, DATA, CL16, RA, FO, SL, SBSY, SFSY, SUB AND CL11/4
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.4
V
VOH
HIGH-level output voltage IOH = −1 mA
VDDD − 0.4 −
VDDD
V
CL
load capacitance
−
−
35
pF
to(r)
output rise time
CL = 20 pF;
0.4 to (VDDD − 0.4) V
−
−
15
ns
to(f)
output fall time
CL = 20 pF;
(VDDD − 0.4) to 0.4 V
−
−
15
ns
IZO
output 3-state leakage
current
Vi = 0 to VDD
−10
−
+10
µA
Vo = 1.5 V
45
50
55
%
IOL = 4 mA
0
−
(WHEN CL11/4 CONFIGURED AS CL11 OUTPUT)
tOH
output HIGH time
(relative to clock period)
PINS MOTO1, MOTO2 AND DOBM
VOL
LOW-level output voltage
0.4
V
VOH
HIGH-level output voltage IOH = −4 mA
VDDD − 0.4 −
VDD
V
CL
load capacitance
−
−
100
pF
to(r)
output rise time
CL = 20 pF;
0.4 to (VDDD − 0.4) V
−
−
10
ns
to(f)
output fall time
CL = 20 pF;
(VDDD − 0.4) to 0.4 V
−
−
10
ns
IZO
output 3-state leakage
current
Vi = 0 to VDD
−10
−
+10
µA
Digital input/output
PIN SDA (5 V TOLERANT CMOS INPUT/OPEN-DRAIN I2C-BUS OUTPUT)
VIL
LOW-level input voltage
−0.3
−
+0.2VDDD
V
VIH
HIGH-level input voltage
0.8VDDD
−
5.5
V
IZO
3-state leakage current
−10
−
+10
µA
−
−
10
pF
0
−
0.4
V
−
−
6
mA
−
−
50
pF
−
−
15
ns
Ci
input capacitance
VOL
LOW-level output voltage
IOL
LOW-level output current
CL
load capacitance
to(f)
output fall time
Vi = 0 to VDDD
IOL = 2 mA
CL = 20 pF;
0.85VDDD to 0.4
PIN V2/V3 (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS/OPEN-DRAIN OUTPUT)
Vthr(sw)
switching voltage
threshold rising
−
−
0.8VDDD
V
Vthf(sw)
switching voltage
threshold falling
0.2VDDD
−
−
V
Vhys
hysteresis voltage
1.35
1.65
−
V
2000 Jun 26
52
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SYMBOL
PARAMETER
Ri(pu)
input pull-up resistance
Ci
input capacitance
VOL
LOW-level output voltage
IOL
LOW-level output current
CL
load capacitance
to(f)
output fall time
CONDITIONS
Vi = 0 V
IOL = 1 mA
CL = 20 pF;
(VDDD − 0.4) to 0.4 V
SAA7327
MIN.
TYP.
MAX.
UNIT
−
120
−
kΩ
−
−
10
pF
0
−
0.4
V
−
−
1
mA
−
−
25
pF
−
−
15
ns
−0.3
−
0.2VDD
V
Crystal oscillator
INPUT: PIN CRIN (EXTERNAL CLOCK)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.8VDD
−
VDD + 0.3
V
ILI
input leakage current
−10
−
+10
µA
Ci
input capacitance
−
−
10
pF
8
8.4672
35
MHz
OUTPUT: PIN CROUT; SEE FIGS 3 AND 4
±100 ppm
fxtal
crystal frequency
gm
mutual conductance at
start-up
17
−
−
mA/V
Cfb
feedback capacitance
−
−
2
pF
Co
output capacitance
−
−
7
pF
Notes
1. Assumes use of external components as shown in the application diagram (Figs 38 or 39).
2. Highest clock frequency at which data slicer produces 1010 output in analog self-test mode.
3. The maximum input current depends on the value of the external resistor connected to Iref and the settings of shadow
registers A and C:
a) With RIref = 30 kΩ, minimum Imax = (0.025). Iref → (0.025) × (40 µA) = 1 µA.
b) With RIref = 30 kΩ, maximum Imax = (0.4). Iref → (0.4) × (40 µA) = 16 µA.
4. VRIN can be set to an internal source or an externally applied reference voltage using shadow register 7.
5. Measuring bandwidth: 200 Hz to 20 kHz, fi(ADC) = 1 kHz.
6. fripple = 1 kHz, Vripple = 0.5 V (p-p).
7. Gain of the ADC is defined as GADC = fsys/Imax (counts/µA); thus digital output = Ii × GADC where:
a) Digital output = the number of pulses at the digital output in counts/s and Ii = the DC input current in µA.
b) The maximum input current depends on RIref and on shadow registers A and C.
c) The gain tolerance is the deviation from the calculated gain.
2000 Jun 26
53
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)
VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Subcode interface timing (single-speed × n); see Fig.32; note 1
INPUT: PIN RCK
tCLKH
input clock HIGH time
2/n
4/n
6/n
µs
tCLKL
input clock LOW time
2/n
4/n
6/n
µs
tr
input clock rise time
−
−
80/n
ns
tf
input clock fall time
−
−
80/n
ns
td(SFSY-RCK)
delay time SFSY to RCK
10/n
−
20/n
µs
OUTPUTS: PINS SBSY, SFSY AND SUB (CL = 20 pF)
Tcy(block)
block cycle time
12.0/n
13.3/n
14.7/n
ms
tW(SBSY)
SBSY pulse width
−
−
300/n
µs
Tcy(frame)
frame cycle time
122/n
136/n
150/n
µs
tW(SFSY)
SFSY pulse width (3-wire mode only)
−
−
366/n
µs
tSFSYH
SFSY HIGH time
−
−
66/n
µs
tSFSYL
SFSY LOW time
−
−
84/n
µs
td(SFSY-SUB)
delay time SFSY to SUB (P data) valid
−
−
1/n
µs
td(RCK-SUB)
delay time RCK falling to SUB
−
−
0
µs
th(RCK-SUB)
hold time RCK to SUB
−
−
0.7/n
µs
Note
1. The subcode timing is directly related to the overspeed factor ‘n’ in normal operating mode. ‘n’ is replaced by the disc
speed factor ‘d’, in lock-to-disc mode.
2000 Jun 26
54
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
tW(SBSY)
handbook, full pagewidth
SAA7327
Tcy(block)
SBSY
tSFSYH
SFSY
(4-wire mode)
tW(SFSY)
Tcy(frame)
SFSY
(3-wire mode)
tSFSYL
SFSY
0.8 V
td(SFSY−RCK)
tf
tr
VDD – 0.8 V
RCK
0.8 V
td(SFSY−SUB)
th(RCK−SUB)
td(RCK−SUB)
VDD – 0.8 V
SUB
0.8 V
MGL718
Fig.32 Subcode interface timing diagram.
2000 Jun 26
55
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
11 OPERATING CHARACTERISTICS (I2S-BUS TIMING)
VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2S-bus timing (single-speed × n); see Fig.33; note 1
CLOCK OUTPUT: PIN SCLK (CL = 20 pF)
Tcy
tCH
tCL
output clock period
clock HIGH time
clock LOW time
sample rate = fs
−
472.4/n
−
ns
sample rate = 2fs
−
236.2/n
−
ns
sample rate = 4fs
−
118.1/n
−
ns
sample rate = fs
166/n
−
−
ns
sample rate = 2fs
83/n
−
−
ns
sample rate = 4fs
42/n
−
−
ns
sample rate = fs
166/n
−
−
ns
sample rate = 2fs
83/n
−
−
ns
sample rate = 4fs
42/n
−
−
ns
sample rate = fs
95/n
−
−
ns
sample rate = 2fs
48/n
−
−
ns
sample rate = 4fs
24/n
−
−
ns
sample rate = fs
95/n
−
−
ns
sample rate = 2fs
48/n
−
−
ns
sample rate = 4fs
24/n
−
−
ns
OUTPUTS: PINS WCLK, DATA AND EF (CL = 20 pF)
tsu
th
set-up time
hold time
Note
1. The I2S-bus timing is directly related to the overspeed factor ‘n’ in the normal operating mode. In the lock-to-disc
mode ‘n’ is replaced by the disc speed factor ‘d’.
clock period Tcy
t CH
t CL
V DD – 0.8 V
SCLK
0.8 V
t su
th
V
WCLK
DATA
EF
DD
– 0.8 V
0.8 V
MBG407
Fig.33 I2S-bus timing diagram.
2000 Jun 26
56
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)
VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.
NORMAL MODE
SYMBOL
PARAMETER
LOCK-TO-DISC MODE
CONDITIONS
UNIT
MIN.
MAX.
MIN.
MAX.
Microcontroller interface timing (4-wire bus mode; writing to decoder registers 0 to F; reading Q-channel
subcode and decoder status); see Figs 34 and 35; note 1
INPUTS SCL AND RAB
480/n + 20
−
2400/n + 20 −
ns
input HIGH time
480/n + 20
−
2400/n + 20 −
ns
rise time
−
480/n
−
480/n
ns
fall time
−
480/n
−
480/n
ns
ns
tCL
input LOW time
tCH
tr
tf
READ MODE (CL = 20 pF)
tdRD
delay time RAB to SDA
valid
−
50
−
50
tPD
propagation delay SCL
to SDA
720/n − 20
960/n + 20
720/n + 20
4800/n + 20 ns
tdRZ
delay time RAB to SDA
high-impedance
−
50
−
50
ns
ns
WRITE MODE (CL = 20 pF)
tsuD
set-up time SDA to SCL note 2
20 − 720/n
−
20 − 720/n
−
thD
hold time SCL to SDA
−
960/n + 20
−
4800/n + 20 ns
tsuCR
set-up time SCL to RAB
240/n + 20
−
1200/n + 20 −
ns
tdWZ
delay time SDA
high-impedance to RAB
0
−
0
−
ns
Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 36 and 37; notes 3 and 4
INPUTS SCL AND SILD
tL
input LOW time
710
−
710
−
ns
tH
input HIGH time
710
−
710
−
ns
tr
rise time
−
240
−
240
ns
tf
fall time
−
240
−
240
ns
READ MODE (CL = 20 pF)
tdLD
delay time SILD to SDA
valid
−
25
−
25
ns
tPD
propagation delay SCL
to SDA
−
950
−
950
ns
tdLZ
delay time SILD to SDA
high-impedance
−
50
−
50
ns
tsCLR
set-up time SCL to
SILD
480
−
480
−
ns
thCLR
hold time SILD to SCL
830
−
830
−
ns
2000 Jun 26
57
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
NORMAL MODE
SYMBOL
PARAMETER
LOCK-TO-DISC MODE
CONDITIONS
UNIT
MIN.
MAX.
MIN.
MAX.
WRITE MODE (CL = 20 pF)
0
−
0
−
ns
hold time SCL to SDA
950
−
950
−
ns
set-up time SCL to
SILD
480
−
480
−
ns
thCL
hold time SILD to SCL
120
−
120
−
ns
tdPLP
delay between two
SILD pulses
70
−
70
−
µs
tdWZ
delay time SDA
high-impedance to
SILD
0
−
0
−
ns
tsD
set-up time SDA to SCL
thD
tsCL
Notes
1. The 4-wire bus mode microcontroller interface timing for writing to decoder registers 0 to F, and reading Q-channel
subcode and decoder status, is a function of the overspeed factor ‘n’. In the lock-to-disc mode the maximum data
rate is lower.
2. Negative set-up time means that the data may change after clock transition.
3. If a 16.9344 MHz crystal is used and SELPLL = 0 then the timings are divided-by-2 until the microcontroller has
written X1XX to register B.
tr
tf
VDD − 0.8 V
RAB
tr
SCL
tf
0.8 V
t CH
VDD − 0.8 V
t dRD
0.8 V
t dRZ
t CL
t PD
VDD − 0.8 V
SDA (SAA7327)
high-impedance
0.8 V
MGS244
Fig.34 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information).
2000 Jun 26
58
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
tr
handbook, full pagewidth
SAA7327
t CH
tf
V DD – 0.8 V
t suCR
RAB
0.8 V
t CH
tf
t CL
tr
VDD – 0.8 V
SCL
0.8 V
t CL
t dWZ
t hD
t suD
V DD – 0.8 V
SDA
(microcontroller)
high-impedance
0.8 V
MBG405
Fig.35 4-wire bus microcontroller timing; write mode (decoder registers 0 to F).
handbook, full pagewidth
VDD − 0.8 V
SILD
0.8 V
t hCLR
t sCLR
VDD − 0.8 V
SCL
0.8 V
t dLD
t dLZ
t PD
VDD − 0.8 V
SDA
(SAA7327)
0.8 V
MGS245
Fig.36 4-wire bus microcontroller timing; read mode (servo commands).
2000 Jun 26
59
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
handbook, full pagewidth
SAA7327
VDD - 0.8 V
SILD
0.8 V
tsCL
tL
tH
tdPLP
VDD – 0.8 V
SCL
0.8 V
thCL
tL
tsD
tdWZ
thD
VDD – 0.8 V
SDA
(microcontroller)
0.8 V
MBG416
Fig.37 4-wire bus microcontroller timing; write mode (servo commands).
2000 Jun 26
60
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VDDD
2.2 Ω
MOTOR
INTERFACE
1
4
2
220 pF
O3
O4
10 kΩ
O1
10 kΩ
220 pF
D3
220 pF
D4
220 pF
O5
O6
D2
R1
220 pF
R2
220 pF
VSSA2
CROUT
CRIN
(1)
33 pF
100 nF
220
pF
CL11/4
VSSD2
DOBM
VDDD1(P)
CFLG
RA
FO
VDDD2(C)
VSSD3
MOTO1
MOTO2
V4
V1
46
4
45
5
44
6
43
7
42
8
41
SAA7327
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
LN
18
19
20
1.5
nF
2.2 Ω
11
kΩ
21
22
220
nF
23
24
25
26
27
22
kΩ
22
kΩ
11
kΩ
220
pF
28
29
30
31
32
1.5
nF
47
µF
VDDD
1/2 VDDD(2)
220
pF
49
3
VDDA
22
kΩ
220
pF
SUB
to CD graphics/subcode interface
RCK
VDDD
TEST3
4.7
kΩ
STATUS
4.7
kΩ
SILD
RAB
to microcontroller
interface
SCL
SDA
RESET
SCLI
to ESA
serial data
loopback
SDI
WCLI
V2/V3
VSSD1
100 nF
11 kΩ
11
kΩ
to external
DAC
10 kΩ
right output
Fig.38 Typical application diagram for current mechanisms.
Product specification
33 µF
MGS248
left output
SFSY
1/2 VDDD(2)
22
kΩ
33 µF
10 kΩ
SBSY
SAA7327
(1) For crystal oscillator see Figs 3 and 4.
(2) 1.5 nF capacitors connected between
pins LN and LP, and RN and RP must be
placed as near to the pins as possible. This also
applies to the 220 nF and 47 µF capacitors
connected between pins Vneg and Vpos.
(3) For single-speed applications, use 47 pF
capacitors, for double-speed use 22 pF
capacitors.
(4) The connections to TDA1300 are shown for
single Foucault mechanisms.
50
47
(2)
33 µF
51
48
17
33 pF
52
2
VDDA2
61
5
D1
O2
53
KILL
3
Iref
VRIN
54
55
EF
6
30 kΩ
100 nF
56
TEST2
(4)
57
SCLK
(TDA1300)
VDDA1
58
WCLK
100 nF
59
DATA
33 µF
2.2 Ω
60
CL16
MECHANISM
AND
HF
AMPLIFIER
61
TEST1
VSSA1
VDDA
62
SELPLL
100 nF
ISLICE
63
RP
22 kΩ
64
1
RN
9
HFIN
Vpos
HFREF
47 pF (3)
1 kΩ
Vneg
1 nF
LP
22 nF
RFE
V5
LDON
SL
100
nF
LDON
7
to DOBM
transformer
Philips Semiconductors
100 nF
to power
amplifiers
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
2.2 Ω
13 APPLICATION INFORMATION
book, full pagewidth
2000 Jun 26
VDDD VDDD
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2.2 Ω
VDDD
2.2 Ω
100 nF
MOTOR
INTERFACE
220 pF
D2
D2
220 pF
D3
D3
220 pF
D4
D4
220 pF
R1
62
S1
220 pF
R2
S2
220 pF
VSSA2
CROUT
OEIC
LP FILTER
(4)
(5)
V
I
CRIN
(5)
(1)
VSSD2
DOBM
VDDD1(P)
CFLG
RA
FO
SL
VDDD2(C)
VSSD3
MOTO1
MOTO2
V1
CL11/4
49
4
45
5
44
6
43
7
42
8
41
SAA7327
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
LN
18
19
20
1.5
nF
11
kΩ
21
22
220
nF
2.2 Ω
23
24
25
26
27
22
kΩ
22
kΩ
11
kΩ
220
pF
30
31
32
SFSY
SUB
to CD graphics/subcode interface
RCK
VDDD
TEST3
4.7
kΩ
STATUS
4.7
kΩ
SILD
RAB
to microcontroller
interface
SCL
SDA
RESET
SCLI
to ESA
serial data
loopback
SDI
WCLI
V2/V3
VSSD1
100 nF
22
kΩ
220
pF
11 kΩ
11
kΩ
10 kΩ
right output
Fig.39 Typical application diagram for voltage mechanisms.
to external
DAC
MGS235
Product specification
33 µF
SAA7327
left output
29
SBSY
1/2 VDDD(2)
22
kΩ
33 µF
10 kΩ
28
1.5
nF
47
µF
VDDD
1/2 VDDD(2)
220
pF
50
46
VDDA
220
pF
51
47
100 nF
33 µF
52
3
(2)
(1) For crystal oscillator see Figs 3 and 4.
(2) 1.5 nF capacitors connected between pins
LN and LP, and RN and RP must be placed as near
to the pins as possible. This also applies to the
220 nF and 47 µF capacitors connected between
pins Vneg and Vpos. Power supplies and VDDD
reference inputs (1⁄2VDDD) for DAC operational
amplifiers must be low noise.
(3) For single-speed applications, use 47 pF capacitors,
for double-speed use 22 pF capacitors.
(4) For connections between OEIC and TZA1024, refer
to TZA1024 device specification.
(5) Resistor values for V to I conversion depend on
OEIC and current range set on CD7 II.
53
48
VDDA2
33 pF
54
2
17
33 pF
55
KILL
D1
56
TEST2
D1
57
EF
VRIN
58
SCLK
Iref
30 kΩ
59
WCLK
VDDA1
60
DATA
100 nF
61
CL16
33 µF
2.2 Ω
62
TEST1
VSSA1
VDDA
VCOM
ISLICE
63
SELPLL
22 kΩ
100 nF
VCC
HFIN
64
1
RP
47 pF (3 )
3 nF
RN
HFREF
1 kΩ
Vpos
100 nF
CMFB
Vneg
8
ΣD1-D4 (4)
V4
10 kΩ
RFFB
9
5 TZA1024
RFEQO
10
(4)
V5
PWRON
LP
DIN
100
nF
LDON
7
to DOBM
transformer
Philips Semiconductors
to power
amplifiers
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
dbook, full pagewidth
2000 Jun 26
VDDD VDDD
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
14 PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
Lp
bp
pin 1 index
L
17
64
detail X
16
1
w M
bp
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
3.00
0.25
0.10
2.75
2.55
0.25
0.45
0.30
0.23
0.13
14.1
13.9
14.1
13.9
0.8
HD
HE
L
17.45 17.45
1.60
16.95 16.95
Lp
v
w
y
1.03
0.73
0.16
0.16
0.10
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT393-1
134E07
MS-022
2000 Jun 26
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
63
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
If wave soldering is used the following conditions must be
observed for optimal results:
15 SOLDERING
15.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
15.2
SAA7327
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.3
15.4
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2000 Jun 26
Manual soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
64
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
15.5
SAA7327
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Jun 26
65
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
SAA7327
16 DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
17 DEFINITIONS
18 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 Jun 26
66
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC for video CD (CD7 II)
NOTES
2000 Jun 26
67
SAA7327
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For all other countries apply to: Philips Semiconductors,
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The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 70
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/02/pp68
Date of release: 2000
Jun 26
Document order number:
9397 750 06994
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