AK4186EN

[AK4186]

Low Power Touch Screen Controller with I

2

AK4186

C Interface

GENERAL DESCRIPTION

The AK4186 is a 4-wire/ 5-wire resistive touch screen controller that incorporates 12bit SAR A/D converter. The AK4186 can detect the pressed screen location with two A/D conversions and it can also measure touch pressure. The AK4186 has both an automatic continuous measurement and a measurement data calculation function. The functions that normally require external processing, such as calculating the average screen input value, are processed by the AK4186. In addition, a new sequential mode achieves short coordinate measurement time while greatly reducing the microprocessor overhead. The AK4186 operates off of supply voltage down to 1.6V in order to connect a low voltage microprocessor. The AK4186 is the best fit for cellular phone, DSC, DVC, smart phone and other portable devices.

FEATURES

!

4-wire or 5-wire Touch Screen Interface

!

I

2

C Serial Interface

!

12bit SAR A/D Converter with S/H circuit

!

Sampling Rate: 22.2kHz

!

Pen Pressure Measurement (4-wire)

!

Continuous Read Function

!

Integrated Internal Osc (Sequence Mode)

!

Integrated Median Averaging Filter

!

Low Voltage Operation: VDD = 1.6V ~ 3.6V

!

PENIRQN Buffer Output

!

Low Power Consumption: 60µA at 1.8V

!

Auto Power Down

!

Package: 12pin CSP (1.7mm x 1.3mm, pitch 0.4mm)

16pin QFN (3mm x 3mm, pitch 0.5mm)

VDD

XP/BR

YP/TR

XN/TL

YN/BL

IN/

WIPER

4/5wire

Touch

Screen

Drivers

Interface MUX

AIN+

VREF+

SAR

AIN-

ADC

VREF-

I

2

C

Serial I/F

&

Control

Logic

TEST

CAD0

SCL

SDA

PENIRQN

Internal

Osc

VSS

Figure 1. Block Diagram

I

2

C-bus is a trademark of NXP B.V.

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Ordering Guide

AK4186ECB

−40 ∼ +85°C

12pin CSP (1.66mm x 1.26mm, 0.4mm pitch)

AK4186EN

−40 ∼ +85°C

16pin QFN (3mm x 3mm, 0.5mm pitch)

Evaluation

AKD4186EN AK4186EN Evaluation Board

Pin Layout

AK4186ECB

3

AK4186ECB

2

Top View

1

A B C D

Black Type

[AK4186]

1 IN/WIPER PENIRQN SDA SCL

A B C D

TOP View

AK4186EN

NC 13

VSS

14

TEST

15

NC

16

AK4186EN

Top View

6

5

8

7

NC

VDD

IN/WIPER

NC

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[AK4186]

PIN/FUNCTION

Pin No.

ECB EN

Pin Name

I/O

I C Serial Clock Input

Function

B1 3 PENIRQN O Pen Interrupt Output (CMOS output)

The PENIRQN pin is “L” when touch-screen press is detected. This pin is always “L” irrespective of touch-screen press when pen interrupt is not enabled.

B2 4 I

2

C Slave Address bit 0

- 5 NC Connection.

No internal bonding. This pin must be connected to VSS.

A2

-

7

WIPER

VDD

8 NC

I Auxiliary Analog Input (4-wire, PANEL bit = “0”)

I Top Touch Panel Input (5-wire, PANEL bit = “1”)

- Power Supply and External Reference Input: 1.6V ~ 3.6V

Connection.

No internal bonding. This pin must be connected to VSS.

I/O Touch Panel X+ Input (4-wire, PANEL bit = “0”)

BR

-

TR

TL

BL

13 NC

I/O Touch Panel Bottom Right Input (5-wire, PANEL bit = “1”)

I/O Touch Panel Y+ Input (4-wire, PANEL bit = “0”)

I/O Touch Panel Top Right Input (5-wire, PANEL bit = “1”)

I/O Touch Panel X- Input (4-wire, PANEL bit = “0”)

I/O Touch Panel Top Left Input (5-wire, PANEL bit = “1”)

I/O Touch Panel Y- Input (4-wire, PANEL bit = “0”)

I/O Touch Panel Bottom Left Input (5-wire, PANEL bit = “1”)

No internal bonding. This pin must be connected to VSS.

- 16 NC

This pin must be connected to VSS.

Connection.

No internal bonding. This pin must be connected to VSS.

Note 1. All digital input pins (CAD0, SCL, SDA) must not be left floating.

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[AK4186]

Handling of Unused Pin

The unused I/O pin must be processed appropriately as below.

Analog IN/WIPER

Setting

This pin must be open.

ABSOLUTE MAXIMUM RATINGS

(VSS = 0V (

Note 2

))

Power Supply

Input Current, Any Pins except for supply

VDD

IIN

-0.3

-

Touch Panel Drive Current IOUTDRV -

Input Voltage ( Note 3

−0.3

Ambient Temperature (power applied)

Storage Temperature

Ta

Tstg

-40

-65

4.6

±10

50

85

150

Note 2. All voltages with respect to ground.

Note 3. XP/BR, XN/TL, YP/TR, YN/TL, IN/WIPER, CAD0, SCL and SDA pins. Max is smaller value between

(VDD+0.3)V and 4.6V.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMEND OPERATING CONDITIONS

(VSS = 0V (

Note 2

))

V mA mA

V

°C

°C

VDD 1.6 1.8 3.6 V

Note 2. All voltages with respect to ground.

WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

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[AK4186]

ANALOG CHARACTERISTICS

(Ta = -40

°C to 85°C, VDD = 1.8V, I 2

C bus SCL=400kHz)

A/D Converter

No Missing Codes

Integral Nonlinearity (INL) Error

Differential Nonlinearity (DNL) Error

Offset Error

Gain Error

AK4186ECB

AK4186ECB

11

-

-2

-

-

12

-

±1

-

-

-

±2

+3

±6

±4

Bits

LSB

LSB

LSB

LSB

Throughput Rate

Touch Panel Drivers Switch On-Resistance

XP, YP

XN, YN

PENIRQ Pull Up Resistor R

IRQ

Auxiliary IN Input

Input Voltage Range

-

-

-

-

6

6

22.2

-

- kHz

- 50 - kΩ

0 - VDD V

Power Supply Current

Normal Mode (Single mode, PD0 bit = “0”)

( Note 4

)

VDD=1.8V - 60 - μA

VDD=3.6V

Normal Mode (Sequence mode, 10kHz equal rate) (

Note 5 ) -

Full Power Down (SDA = SCL = “H”) -

Note 4. Continuous ADC data read (fs = 22.2kHz). Expect for Power Consumption of Touch Panel driver.

Note 5. COUNT bit = “1”, INTERVAL2-0 bits = 000. Write command cycle = 1kHz. Expect for Power Consumption of Touch Panel driver.

DC CHARACTERISTTICS (Logic I/O)

(Ta=-40

°C to 85°C, VDD =1.6V to 3.6V)

Parameter Symbol

“H” level input voltage

“L” level input voltage

Input Leakage Current

“H” level output voltage (PENIRQN pin @ Iout = -250

μA)

“L” level output voltage (PENIRQN pin @ Iout = 250

μA)

(SDA pin @ Iout = 3mA)

Tri-state Leakage Current (

Note 6 )

All pins expect for XP, YP, XN, YN pins

XP, YP, XN, YN pins

VIH 0.8xVDD

VIL -

IILK -10

VOH VDD-0.3

IOLK

-10

-10

-

-

-

-

-

0.2xVDD

10

-

10

10

V

V

μA

V

VOL - - 0.3 V

μA

μA

Note 6. Expect for TEST pin. TEST pin has internal pull-down device, nominally 100kΩ.

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[AK4186]

SWITCHING CHARACTERISTICS

(Ta=-40

°C to 85°C, VDD=1.6V to 3.6V)

Internal OSCILATOR

Clock Frequency

Touch Panel (A/D Converter)

SCL clock frequency

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first Clock pulse)

Clock Low Time f

OSC fSCL tBUF tHD:STA tLOW

-

1.3

0.6

1.3

-

-

-

-

400

-

-

-

Clock High Time

Setup Time for Repeated Start Condition tHIGH tSU:STA

0.6

0.6

-

-

SDA Hold Time from SCL Falling ( Note 7 ) tHD:DAT

-

-

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

Pulse Width of Spike Noise Suppressed By Input Filter

Capacitive load on bus tSU:DAT tR tF tSU:STO tSP

Cb

0.1

-

-

0.6

0

-

-

-

-

-

-

-

-

0.3

0.3

-

50

400

Note 7: Data must be held for sufficient time to bridge the 300ns transition time of SCL.

SDA

VIH

VIL tBUF tLOW tR tHIGH tF tSP

SCL

VIH

VIL tHD:STA

Stop Start tHD:DAT tSU:DAT tSU:STA

Start

Figure 2. Timing Diagram tSU:STO

Stop

μs

μs

μs

μs ns pF kHz

μs

μs

μs

μs

μs

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[AK4186]

OPERATION OVERVIEW

Function Overview

The AK4186 consists of the following blocks:

● 1.6V Successive Approximation Resister (SAR) A/D converter

● 4-wire or 5-wire resistive touch screen controller interface

● Single or Continuous A/D conversion

● Internal Clock for SAR A/D Converter

● I C

TM

I/F

A/D Converter for Touch Screen

The AK4186 integrates a 12bit successive approximation resistor (SAR) A/D converter for position measurement, temperature, and auxiliary input. The architecture is based on capacitive redistribution algorithm, and an internal capacitor array functions as the sample/hold (S/H) circuit.

The SAR A/D converter output is a straight binary format as shown below:

Input Voltage Output Code

(

ΔVREF-1.5LSB)~ ΔVREF

(

ΔVREF-2.5LSB) ~ (ΔVREF-1.5LSB)

FFFH

FFEH

--------- ---------

0.5LSB ~ 1.5LSB 001H

0 ~ 0.5LSB 000H

ΔVREF: (VREF+) – (VREF-)

The f

OSC

Table 1. Output Code

clock of an internal oscillator is used for A/D conversion. The full scale (

ΔVREF) of the A/D converter depends on the input mode. Position and pen pressure are measured in differential mode, and then IN is measured in single-ended mode. The AK4186 is controlled by 8bit serial command. A/D conversion result is 12bit data output on the SDA pin.

Analog Inputs

The analog input channel is automatically selected in sequential measurement mode. When position detection (X-axis and Y-axis) and pen pressure are selected as analog inputs in differential mode, the full scale (

ΔVREF) is the voltage difference between the non-inverting terminal and the inverting terminal of the measured axis (e.g. X-axis measurement: (XP) – (XN)). Analog input to A/D converters (

ΔAIN) is the voltage difference between the noninverting terminal of the non-measured axis and the inverting terminal of the measured axis. At single-ended mode, the full scale of A/D converter (

ΔVREF) is the voltage difference between the VDD and the VSS. The analog input of A/D converter (

ΔAIN) is the voltage difference between the selected channel (IN) and the VSS.

If the source of analog input is high impedance, longer tracking time is required. Then A/D conversion should be started.

Channel Selection

Status of Driver Switch

X-Driver Y-Driver

ADC input (

ΔAIN)

AIN+ AIN-

Reference Voltage (

ΔVREF)

VREF+ VREF-

Ref. Mode

AIN Measure OFF OFF IN GND VREF GND SER

Z1 Measure (Pressure)

Z2 Measure (Pressure)

XN-ON

XN-ON

YP-ON

YP-ON

XP

YN

XN

XN

Table 2. Measurement Mode (4-wire)

YP

YP

XN

XN

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[AK4186]

Channel Selection

X-axis Measure

Y-axis Measure

Status of Driver Switch

TL-Driver BR-Driver

ON

OFF

OFF

ON

ADC input (

ΔAIN)

Reference Voltage (

ΔVREF)

AIN+ AIN- VREF+ VREF-

WIPER

WIPER

TL

BR

BR

TL

TL

BR

Ref. Mode

DFR

DFR

Table 3. Measurement Mode (5-wire)

Position Detection of Touch Screen

1. The Position Detection for 4-wire Touch Screen

The position on the touch screen is detected by taking the voltage of one axis when the voltage is supplied between the two terminals of another axis. At least two A/D conversions are needed to get the two-dimensions (X/Y-axis) position.

VDD VDD

X-Plate

X-Plate

XP-Driver SW ON YP-Driver SW ON

XP XP

Y-Plate

Y-Plate

AIN+ AIN+

ADC

VREF+

VREF AIN-

YP

ADC

VREF+

VREF- AIN-

YP

XN

XN

XN-Driver SW ON

YN YN

Touch Screen

YN-Driver SW ON a) X-Position Measurement Differential Mode b) Y-Position Measurement Differential Mode

The X-plate and Y-plate are connected on the dotted line when the panel is touched.

X+

X-Plate (Top side)

X-

Y-Plate (Bottom side)

Y- Y+ c) 4-wire Touch Screen Construction

Figure 3. Axis Measurements for 4-wire Touch Screen

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[AK4186]

2. The Position Detection for 5-wire Touch Screen

A 5-wire touch panel consists of one transparent resistive layer and a top metal contact area separated by insulating spacers. The top layer acts only as a voltage measuring probe, the position detection uses the bottom resistive layer that had metal contacts at the 4 corners. When the top layer is pressed by a pen or stylus, the top layer contacts with the bottom layer. Then the X and Y coordinates is detected. The 5-wire touch screen works properly even with damages or scratches on the top layer, therefore the 5-wire touch panel has higher durability than the 4-wire touch panel. Connect the metal contact of the top layer to the WIPER pin to measure the Y-axis of current position at AIN+. The top right and top left contacts at the 4 corners are connected to VDD and the bottom right and bottom left contacts connected to VSS.

Then the AK4186 initiates A/D conversion of AIN+ input voltage, and Y-axis position is determined.

Terminal TL TR BL BR

X-axis VSS VDD VSS VDD

Y-axis VDD VDD VSS VSS

SW

Switch VDD VSS Switch

VDD/VSS ON/OFF ON/OFF VDD/VSS

Table 4. Driver SW configuration

VDD

VDD

TR SW ON

BR SW ON

BR

TR

WIPER

VDD

TR SW ON

VDD

TL SW ON

TL

TR

VREF+

ADC

VREF

AIN+

AIN-

TL

VREF+ AIN+

VREF-

ADC

AIN-

WIPER

BL

TL SW ON

BL SW ON

BR

BL

BL SW ON

BR SW ON a) X-Position Measurement Differential Mode b) Y-Position Measurement Differential Mode

The Top layer and Bottom layer are connected on the dotted line when the panel is touched.

TL

Detection side

(Top layer)

WIPER

TR

ADC

BL

BR

5-wire Touch Screen Construction

Drive side

(Bottom Layer)

Figure 4. Axis Measurements for 5-wire Touch Screen

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[AK4186]

Pen Pressure Measurement (Only 4-wire Touch Screen)

The touch screen pen pressure can be derived from the measurement of the contact resistor between two plates. The contact resistance depends on the size of the depressed area and the pressure. The area of the spot is proportional to the contact resistance.

This resistance (Rtouch) can be calculated using two different methods. The first method is that when the total resistance of the X-plate sheet is already known. The resistance, Rtouch, is calculated from the results of three conversions, X-position, Z1-position, and Z2-position, and then using following formula:

R

TOUCH

=

R

X plate

X

Position

4096

⎜⎜

Z

2

Z

1

1

⎟⎟

The second method is that when both the resistances of the X-plate and Y-plate are known. The resistance, Rtouch, is calculated from the results of three conversions, X-position, Y-position, and Z1-position, and then using the following formula:

R

TOUCH

=

R

X plate

X

4096

Position

⎜⎜

4096

Z

1

1

⎟⎟

R

Y plate

1 -

Y

Position

4096

VDD

VDD

ON ON

YP YP

XP touch XP

ADC

VREF+

VREF-

ON

AIN+

AIN-

XN

YN

ADC

VREF+

VREF-

ON

AIN+

AIN-

XN

YN a) Z1-Position Measurement Differential Mode b) Z2-Position Measurement Differential Mode

Figure 5. Pen Pressure Measurements touch

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[AK4186]

Digital I/F

The AK4186 is controlled by a microprocessor via I

2

C bus and supports standard mode (100kHz) and fast mode

(400kHz). Note that the AK4186 operates in those two modes and does not support a High speed mode I

2

(3.4MHz). The AK4186 can operate as a slave device on the I

2

C bus network. The AK4186 operates off of supply voltage down to 1.6V in order to connect a low voltage microprocessor.

C-bus system

VDD=1.6V ~ 3.6V

4/5-wire touch panel

AK4186

CAD0

“L” or “H”

Rp

SCL

SDA

PENIRQN

Rp

Micro-

Processor

I

2

C bus

Controller

Figure 6. Digital I/F

Operations

Figure 7

shows the data transfer sequence for the I

2

C-bus mode. All commands are preceded by START condition. A

HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (

Figure 11 ). After the

START condition, a slave address is sent. This address is 6 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as “100100”. The next bit is CAD0 (device address bit). This bit identify the specific device on the bus. The hard-wired input pin (CAD0 pin) set this device

address bit ( Figure 8 ). If the slave address matches that of the AK4186, the AK4186 generates an acknowledge and the

operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH)

during the acknowledge clock pulse ( Figure 12 ). R/W bit value of “1” indicates that the read operation is to be executed.

“0” indicates that the write operation is to be executed.

The second byte consists of the control register address of the AK4186. The format is MSB first, and those most

significant two bits are fixed to zeros ( Figure 9 ). The data after the second byte contains control data. The format is

MSB first, 8bits ( Figure 10 ). The AK4186 generates an acknowledge after each byte is received. A data transfer is

always terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (

Figure 11 ).

The AK4186 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4186 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.

The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is LOW ( Figure 13

) except for the START and STOP conditions.

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[AK4186]

SDA

S

T

A

R

T

R/W = “0”

Sub

Address(n)

Data (n) Data (n+1) Data (n+x)

S

T

O

P

P

Figure 7. Data Transfer Sequence at the I

2

C-Bus Mode

1 0 0 1 0 0 R/W

(This CAD0 should match with CAD0 pin.)

Figure 8. The First Byte

0 0 A5 A4 A3 A2 A1 A0

Figure 9. The Second Byte

SDA

D7 D6 D5 D4 D3 D2 D1 D0

Figure 10. Byte Structure after the second byte

SCL

S start condition

Figure 11. START and STOP Conditions

P stop condition

DATA

OUTPUT BY

TRANSMITTER not acknowledge

DATA

OUTPUT BY

RECEIVER

SCL FROM

MASTER

S

START

CONDITION

1

2

Figure 12. Acknowledge on the I

2

C-Bus

8 acknowledge

9 clock pulse for acknowledgement

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[AK4186]

SDA

SCL data line stable; data valid change of data allowed

Operations

Set the R/W bit = “1” for the READ operation of the AK4186.

(1) Register READ Operation

After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to generating stop condition, the address counter will “roll over” to 00H and the data of 00H will be read out. The register read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit “1”. The AK4186 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but generates stop condition instead, the AK4186 ceases transmission. A/D conversion data in sequence mode can be read when the data is available.

S

T

A

R

T

R/W= “0”

S

T

A

R

T

R/W= “1”

S

T

O

P

SDA

Sub

Address(n)

Data (n) Data (n+1) Data (n+x) P

Figure 14. Register Address Read

(2) A/D Measurement Operation

When the master send a READ command after sending a control register address for a measurement channel by a

WRITE operation, the AK4186 starts A/D conversion in single mode. The master issues the slave address with the R/W bit “1”. The AK4186 then generates an acknowledge, and outputs ADC data. The ADC data is 2 bytes format (MSB

first), and upper 12-bit are valid and lower 4-bit are filled with “0”. ( Figure 17

,

Figure 18

) The master receives the first byte, and generates an acknowledge. Then the master receives the second byte and does not generate an acknowledge, the AK4186 ceases transmission. (

Figure 15 ) If the master generates an acknowledge, the AK4186 newly repeats A/D

conversion to set the channel every read cycle, and the master can receive update ADC data on each read operation. The

AK4186 repeats A/D conversion and continuously outputs ADC data until the master does not generate an acknowledge but generates a stop condition instead. (

Figure 16 ) This continuous read mode enables the higher sampling rate and

lower processor load than a single ADC data read.

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[AK4186]

SDA

S

T

A

R

T

SDA

S

T

A

R

T

R/W= “0”

Sub

Address(n)

S

T

A

R

T

R/W= “1”

ADC Data

(High Byte)

ADC Data

(Low Byte)

S

T

O

P

P

ADC Data

(High Byte)

ADC Data

(Low Byte)

R/W= “0”

Figure 15. Single ADC Data Read

S

T

A

R

T

R/W= “1”

Sub

Address(n)

ADC Data

(High Byte)

ADC Data

(Low Byte)

ADC Data

(High Byte)

ADC Data

(Low Byte)

S

T

O

P

P

Figure 16. Continuous ADC Data Read

D11 D10 D9 D8 D7 D6 D5 D4

Figure 17. ADC Data (High Byte)

D3 D2 D1 D0 0 0 0 0

Figure 18. ADC Data (Low Byte)

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[AK4186]

Register Map

Addr Register D7 D6 D5 D4 D3 D2 D1 D0

00H Reset

PANEL

0

0 SLEEP1 SLEEP0 0 0 0 PD0

03H

-0FH

Reserved 0 0 0 0 0 0 0 0

11H Sequence Data 1H

13H Sequence Data 2H

15H Sequence Data 3H

17H Sequence Data 4H

CHST3 CHST2 CHST1 CHST0 SEQST3 SEQST2 SEQST1 SEQST0

D1T11 D1T10 D1T9 D1T8 D1T7 D1T6 D1T5 D1T4

D1T3 D1T2 D1T1 D1T0 0 0 0 0

D2T11 D2T10 D2T9 D2T8 D2T7 D2T6 D2T5 D2T4

D2T3 D2T2 D2T1 D2T0 0

D3T11 D3T10

0 0 0

D3T9 D3T8 D3T7 D3T6 D3T5 D3T4

D3T3 D3T2 D3T1 D3T0 0

D4T11 D4T10

0 0 0

D4T9 D4T8 D4T7 D4T6 D4T5 D4T4

D4T3 D4T2 D4T1 D4T0 0 0 0 0

19H

-1FH

Reserved 0 0 0 0 0 0 0 0

XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4

XS3 XS2 XS1 XS0 0 0 0 0

YS11 YS10 YS9 YS8 YS7 YS6 YS5 YS4

YS3 YS2 YS1 YS0 0 0 0 0

Z1S11 Z1S10 Z1S9 Z1S8 Z1S7 Z1S6 Z1S5 Z1S4

Z1S3 Z1S2 Z1S1 Z1S0 0 0 0 0

Z2S11 Z2S10 Z2S9 Z2S8 Z2S7 Z2S6 Z2S5 Z2S4

Z2S3 Z2S2 Z2S1 Z2S0 0 0 0 0

INS11 INS10 INS9 INS8 INS7 INS6 INS5 INS4

INS3 INS2 INS1 INS0 0 0 0 0

Table 5. AK4186 Register Map

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[AK4186]

System Reset

Upon power-up, the AK4186 must be reset by writing the reset command. (Refer to the “

Power-up Sequence

” for

details) This ensures that all internal register reset to their initial values (00H) and set the channel to X-axis (auto driver

= OFF). The System reset can also stop a sequential measurement forcibly, but all data will be cleared.

S

T

A

R

T

R/W= “0”

S

T

O

P

SDA

Sub

Address

Reset

Command

P

Figure 19. Data Transfer Sequence at the System Reset

1 0 0 1 0 0 R/W

(Those CAD1/0 should match with CAD1/0 pins.)

Figure 20. The First Byte

0 0 0 0 0 0 0 0

Figure 21. The Second Byte

0 0 0 0 0 0 0 1

Figure 22. Byte Structure at Reset Command

Setup Function of Touch Panel

1. Setup Command Configuration

01H Setup

PANEL SLEEP0

Table 6. Setup Command Register Format

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[AK4186]

Bits Name Description

D7 PANEL Selection

0: 4-wire (default)

1: 5-wire

D6 Reserved

D5-D4 SLEEP1-0

Must write “0”

Sleep Command bits (refer to “

■ Sleep Mode ”)

00: Normal Mode (default)

01: Sleep Mode 1 (PENIRQN disabled and output “H”. Touch Panel is open.)

10: Sleep Mode 2 (PENIRQN disabled and open. Touch Panel is open.)

11: Reserved

D3

D2

D1

D0

Reserved

Reserved

Reserved

PD0

Must write “0”

Must write “0”

Must write “0”

Power-down Mode (refer to “

■ Power-down Control ”)

0: Auto Power-down Mode (default)

1: Driver ON Mode

Table 7. Setup Command description

SLEEP1-0, PD0 bits can be written during a sequential measurement but PANEL bit will not be changed.

2. Sequence Command Configuration

Addr Register D2 D1 D0

02H Sequence

0 SEQM2 SEQM1 SEQM0 COUNT INTERVAL2 INTERAVAL1

Table 8. Sequence Command Register Format

The AK4186 starts A/D conversion in sequence mode by setting the COUNT, SEQM2-0, INTERVAL2-0 bits of the register address to 02H. The AK4186 makes six or ten measurements by setting the COUNT bit. The results are used to calculate the average value, discarding the minimum and maximum values, and the result sets the data register of sequence mode. If the address 02H is set again during a sequential measurement, this setting is ignored and the AK4186 continues the measurement. The master executes the register read operation to read the measurement data of sequence mode after confirming the PENIRQN pin turns to “H” (Data Available).

Bits Name Description

D7 Reserved

D6-D4 SEQM2-0

Must write “0”

000: X → Y → Z1 → Z2 Scan (only 4-wire Touch Screen) (default)

001: X → Y Scan

010: X Scan

011: Y Scan

100: Z1 → Z2 Scan (only 4-wire Touch Screen)

101: Reserved

110: A-IN (only 4-wire Touch Screen)

111: Reserved

D3 COUNT A/D Conversion count

0: 6 times A/D Conversion (default)

1: 10 times A/D Conversion

D2-D0 INTERVAL2-0 Sampling interval times.

000: 0μs (default) 001: 5μs

010: 10μs 011: 20μs

100: 50μs 101: 100μs

110: 200μs 111: 500μs

Table 9. Sequence Command description

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[AK4186]

Data Register

1. Sequence Mode Data Register

The AK4186 starts A/D conversion in sequence mode by setting the COUNT, SEQM2-0, INTERVAL2-0 bits of the register address 02H.

The AK4186 makes six or ten measurements by setting the COUNT bit. The results are used to calculate the average value, discarding the minimum and maximum values, and the result sets the data register of sequence mode. The AK4186 registers data from address 11H in order of setting the SEQM2-0 bits. The master can read the ADC data by the register read operation after confirming the PENIRQN pin turns to “H” or a register status

SEQST3-0 = 02H (Data Available). The data register is Read Clear so that data will be deleted once it is read. Do not read data during a sequential measurement.

Addr Register D7 D6 D5 D4 D3 D2 D1 D0

11H Sequence Data 1H

13H Sequence Data 2H

15H Sequence Data 3H

17H Sequence Data 4H

CHST3 CHST2 CHST1 CHST0 SEQST3 SEQST2 SEQST1 SEQST0

D1T11 D1T10 D1T9 D1T8 D1T7 D1T6 D1T5 D1T4

D1T3 D1T2 D1T1 D1T0 0

D2T11 D2T10

0 0 0

D2T9 D2T8 D2T7 D2T6 D2T5 D2T4

D2T3 D2T2 D2T1 D2T0 0

D3T11 D3T10

0 0 0

D3T9 D3T8 D3T7 D3T6 D3T5 D3T4

D3T3 D3T2 D3T1 D3T0 0

D4T11 D4T10

0 0 0

D4T9 D4T8 D4T7 D4T6 D4T5 D4T4

D4T3 D4T2 D4T1 D4T0 0

Table 10. Data Register for Sequence Mode (Read Only)

0 0 0

BIT Name Description

D7-D4 CHST3-0 Last Measurement Channel for Single Mode

0011: AIN

0100: X-axis

0101: Y-axis

0110: Z1

0111: Z2 others: Reserved

D3-D0 SEQST3-0 Status Bits for Sequence Mode

0000: Not Busy

0001: Sequence Busy

0010: Data Available others: Reserved

Table 11. Status Register description (Read Only)

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[AK4186]

2. Single Mode Data Register

The AK4186 starts A/D conversion in single mode by receiving a single measurement command, and then outputs MSB first 12bit A/D data.

Addr Register D7 D6 D5 D4 D3 D2 D1 D0

XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4

XS3 XS2 XS1 XS0 0 0 0 0

YS11 YS10 YS9 YS8 YS7 YS6 YS5 YS4

YS3 YS2 YS1 YS0 0 0 0 0

Z1S11 Z1S10 Z1S9 Z1S8 Z1S7 Z1S6 Z1S5 Z1S4

Z1S3 Z1S2 Z1S1 Z1S0 0 0 0 0

Z2S11 Z2S10 Z2S9 Z2S8 Z2S7 Z2S6 Z2S5 Z2S4

Z2S3 Z2S2 Z2S1 Z2S0 0 0 0 0

INS11 INS10 INS9 INS8 INS7 INS6 INS5 INS4

INS3 INS2 INS1 INS0 0 0 0 0

Table 12. Data Register for Single Mode (Read Only)

Power-down Control

Power-down and pen interrupt function are controlled by PD0 bit. In order to achieve minimum current, it is recommended to set PD0 bit = “0” for automatic power down of the touch screen driver after A/D conversion. It is possible to reduce the variation in data by setting PD0 bit = “1” during measurements. A/D converter keeps power up state after every measurement completed.

When the register data of address 01H is written, PD0 bit is updated at the rising edge of the 27th SCL. The last PD0 bit is valid until this timing.

The A/D converter and internal oscillator are automatically powered up at the start of the conversion, and automatically powered down at the end of the conversion, regardless of the PD0 bit setting.

PD0 PENIRQN

0 Enable

Function

Auto Power-down Mode

In power-down state, the touch screen driver switches are powered down. (Only YN or BL driver switch is turned ON and forced to VSS.) PEN interrupt function is enabled except when in the sampling time and converting time.

ON

If X-axis or Y-axis is selected as analog input, touch screen driver switches are always powered up. This is effective when more settling time is required to suppress the electrical bouncing of touch plate. PEN interrupt function is disabled and

PENIRQN is forced to “L” state.

Table 13. Power-down Control

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[AK4186]

Sleep Mode

The AK4186 supports sleep mode that puts touch panel to open state and disables pen interrupt function, effective for reducing power consumption caused by unnecessary pen touch.

Sleep mode is controlled by SLEEP1-0 bits. The AK4186 changes to sleep mode on the rising edge of 27th SCL after the micro-controller writes “01” or “10” to SLEEP1-0 bits of AK4186’s register. All touch screen driver switches and

A/D converter are powered down in this sleep mode, and it reduces power consumption to the minimum value. The

PENIRQN output is shown below. (

Table 14 )

The AK4186 returns to normal operation out of sleep mode when the micro-controller writes “00” to SLEEP1-0 bits.

The timing of going back to normal operation mode is the rising edge of the 27th SCL. The initial state after system reset is in normal operation mode.

SLEEP1-0 PENIRQN

00 Normal Normal Operation

11 N/A

Open

Open

N/A

Table 14. Sleep Mode

A/D conversion is available during sleep mode by issuing an ADC executing command (sequential). The AK4186 returns to sleep mode after completing an A/D conversion.

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[AK4186]

CONTROL SEQUENCE

Power-up Sequence

To fix the I

2

C interface statement, send a dummy command when first power up. After the dummy command, send a reset command to initialize internal registers.

1 0 0 1 0 0 R/W

Figure 23. Slave Address Construction (CAD0 is set by a pin)

1 1 1 1 1 1 1 1

Figure 24. Dummy Address Construction

SDA

S

T

A

R

T

1 1 1 1 1 1 1 1

R/W= “0”

Figure 25. Dummy Command Construction

Dummy

Address

Dummy

Command

S

T

O

P

P

S

T

A

R

T

R/W= “0”

Sub

Address

4186 AC 4186 AC

Reset

Command

4186 AC

S

T

O

P

P

Dummy Command

Figure 26. Power-up Sequence

Reset Command

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[AK4186]

Touch Screen Controller Control Sequence (Single Mode)

(1) Setup Sequence

In case of the single measurement mode, this touch panel configuration register sets the measurement mode of the

AK4186. Touch screen driver switches are turned ON at Driver ON mode (PD0 bit = “1”) on the rising edge of the 27th

SCL. It is possible to have longer tracking time even if the source of analog input impedance is high, because the actual sampling is executed at the read operation. If a current measurement is made by the same setting of PD0 bit as the last time, the setup sequence is unnecessary.

0

17 18

19 20

21 22 23 24 25 26 27

SCL

Data Byte

SDA

START

Touch Screen

Driver SW

PD0=1

Slave Address Byte

1 0 0 1 0 0

CAD0

R/ W

0 0

AK4186

ACK

Sub Address Byte

Register Addr = 01H 0 PANEL

AK4186

ACK

0

AK4186

ACK

STOP

PD0=0 “Off”

Figure 27. Setup operation and Driver SW timing

(2) Single Measurement Sequence

When the master send a READ command after sending a control register address for a measurement channel by a

WRITE operation, the AK4186 starts A/D conversion in single mode. This A/D conversion is synchronized with the internal clock. The internal oscillator of the AK4186 is automatically powered up on the falling edge of 25th SCL after writing the register address, and the AK4186 samples the analog input and completes A/D conversion after the rising edge of 26th SCL. The master receives the first byte of serial data (D11-D4, MSB first), and generates an acknowledge.

Then the master receives the second byte of serial data (D3-D0, followed by four 0 bits). When the master continuously reads ADC data, the master repeats read operation after generating an acknowledge. If the master does not generate an acknowledge but generates stop condition instead, the AK4186 ceases continuous operation.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCL

SDA

1 0 0 1 0 0

R/ W

CAD

0

0 0

START

AK4186

ACK

Slave Address Byte

Register Addr = 20H~28H

Sub Address Byte

AK4186

ACK

START

1 0 0

R/ W

1 0 0

CAD

0

1 0

D11 D10 D9 D8 D7 D6 D5 D4

0 D3 D2 D1 D0 0 0 0

0

1

AK4186

ACK

Master

ACK

Master

ACK

Slave Address Byte Data Byte (MSB) Data Byte (LSB)

STOP

OSCLK

Sampling

AD conv.

Sampling

AD conv.

Touch Screen

Driver SW

PD0=“1”

PD0=“0”

PENIRQN

PD0=“0”

“H”

ENABLE “L”

Figure 28. Single Measurement operation and Driver SW timing

ENABLE

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[AK4186]

Touch Screen Controller Control Sequence (Sequence Mode)

The AK4186 starts A/D conversion in sequence mode by setting the COUNT, SEQM2-0, INTERVAL2-0 bits of the register address 02H. PENIRQN is forced to “L” state, and internal oscillator is automatically powered up. The AK4186 makes six or ten measurements by setting the COUNT bit. The results are used to calculate the average value, discarding the minimum and maximum values, and the result sets the data register of sequence mode. When the sequence is finished, the AK4186 sets the PENIRQN pin to “H” and notifies that sequence is ended. After 20μs (typ.) is passed from the rising edge of the PENIRQN pin, the internal oscillator is powered down and PEN interrupt function is enabled.

The master executes the register read operation to read the measurement data of sequence mode after confirming Data availability. The master can confirm Data availability by PENIRQN↑ or SEQST3-0 = 03H.

This sequence data can be read in register read operation one by one (Address 11H). Prior to issuing the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit “1”. The AK4186 then generates an acknowledge, 1 byte of ADC data, and increments the internal address counter by 1. If the master does not generate an acknowledge but generates stop condition instead, the AK4186 ceases transmission. The A/D data is cleared after reading all the A/D data.

Pen

Touch

Sequence Start

Set PENIRQN Low

Start Clock

Driver Set

Wait Timer

ADC

No

Count End?

Yes

Sequence

End?

Yes

Set PENIRQN High

No

Stop Clock & PenTouch Enable

Done

Figure 29. Internal Clock Mode Control Flowchart

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[AK4186]

PENIRQN

SCL

SDA Sub Address (02H) Data (10H) P

W=0

OSCLK

Internal Sequence

(SEQM2-0 bits=“001”, X-Y Scan)

PEN Touch

Wait

Tracking, Conversion

(X-axis 1st)

20 / fosc

Tracking, Conversion

(X-axis nth)

20 / fosc Wait

Tracking, Conversion

(Y-axis 1st)

20 / fosc

Figure 30. Sequence Mode Control Sequence (X-Y Scan: SEQM bits = “001”)

(Sequence Mode Start → Internal Sequence Processing → Data Available)

Tracking, Conversion

(Y-axis nth)

20 / fosc

DAV

PENIRQN

Enable

PENIRQN

SCL

SDA

DAV

Sub Address (11H) S Slave Address R ADC Data (11H) ADC Data (12H) ADC Data (13H) ADC Data (14H)

W=0

AK4186

ACK

AK4186

ACK

R=1

AK4186

ACK

MASTER

ACK

MASTER

ACK

MASTER

ACK

Figure 31. Sequence Mode Control Sequence (X-Y Scan: SEQM bits = “001”)

(Data Available → A/D Data Read)

MASTER

NACK

P

D11

(MSB)

D10 D9 D8 D7 D6 D5 D4

Figure 32. ADC Data (High Byte)

D3 D2 D1

D0

(LSB)

0 0 0 0

Figure 33. ADC Data (Low Byte)

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[AK4186]

Pen Interrupt

The AK4186 has pen interrupt function to detect pen touches. Pen interrupt function is enabled at power-down state and

PD0 bit = “0” (

Figure 34 ). The YN pin (4-wire) or BL pin (5-wire) is connected to VSS at the PEN interrupt enabled

state. The XP pin (4-wire) or WIPER pin (5-wire) is pulled up via an internal resistor (R

IRQ

: typ.50kΩ). PENIRQN is connected to the XP pin (4-wire) or WIPER pin (5-wire) inside. If touch plate is pressed by a pen, the current flows via

<VDD> - <Ri> - <X+> - <Y-> (4-wire). If 5-wire, via <VDD> - <Ri> - <WIPER> - <BL>. The resistance of the plate is generally 1kΩ or less, PENIRQN is forced to “L” level. If the pen is released, PENIRQN returns “H” level because two plates are disconnected, and the current does not flow via two plates.

During an A/D conversion or Sequence measurement or when PD0 bit is set to “1”, the PENIRQN is “L” for all the time in this period regardless of the touched/non-touched state.

While in single measurement mode, the pen interrupt function is disabled from the rising edge of 26th SCL to the end of the measurement. (

Figure 28 )

It is recommended that the micro controller mask the pseudo-interrupts while the control command is issued or A/D data is output.

VDD

R

IRQ

=

50k

Ω

PENIRQN

VDD VDD

EN2

Driver OFF

XP/WIPER

EN1

YN/BL

Driver ON

Figure 34. PENIRQN Functional Block Diagram (WIPER does not have a driver.)

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[AK4186]

SYSTEM DESIGN

Figure 35 ,

Figure 36

,

Figure 37 ,

Figure 38

shows the system connection diagram for the AK4186. The evaluation board

[AKD4186] demonstrates the optimum layout, power supply arrangements and measurement results.

AK4186ECB <4-wire Touch Screen Input>

4-wire

Touch Screen

Analog Ground Digital Ground

0.001µ *

0.001µ *

0.001µ *

0.001µ *

Analog Supply

1.6

∼3.6V

10µ

+

0.1µ

XP

VDD

IN

YP XN

Top View

CAD0

PENIRQN

TEST

SDA

YN

VSS

SCL

Auxiliary

Analog Input

“L” or “H”

Rp

Rp

µP

Figure 35. Typical Connection Diagram (4-wire, AK4186ECB)

Notes:

- VSS of the AK4186 should be distributed separately from the ground of external controllers.

- All digital input pins (SCL, SDA, CAD0 pins) must not be left floating.

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AK4186EN <4-wire Touch Screen Input>

Digital Ground Analog Ground

4-wire

Touch Screen

[AK4186]

13

14

15

NC NC

VSS

AK4186EN

VDD

Top View

T EST IN

8

7

6

16 N C NC 5

0.1µ

0.001µ *

0.001µ *

0.001µ *

0.001µ *

10µ

+

Analog Supply

1.6

∼3.6V

Auxiliary

Analog Input

µP

Rp Rp

“L” or “H”

Figure 36. Typical Connection Diagram (4-wire, AK4186EN)

Notes:

- VSS of the AK4186 should be distributed separately from the ground of external controllers.

- All digital input pins (SCL, SDA, CAD0 pins) must not be left floating.

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AK4186ECB <5-wire Touch Screen Input>

5-wire

Touch Screen

Analog Ground Digital Ground

[AK4186]

0.001µ *

0.001µ *

0.001µ *

0.001µ *

Analog Supply

1.6

∼3.6V

10µ

+

0.1µ

BR TR TL

Top View

VDD

WIPER

CAD0

PENIRQN

TEST

SDA

BL

VSS

SCL

0.001µ*

Rp

“L” or “H”

Rp

µP

Figure 37. Typical Connection Diagram (5-wire, AK4186ECB)

Notes:

- VSS of the AK4186 should be distributed separately from the ground of external controllers.

- All digital input pins (SCL, SDA, CAD0 pins) must not be left floating.

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AK4186EN <5-wire Touch Screen Input>

Digital Ground Analog Ground

5-wire

Touch Screen

0.001µ *

0.001µ *

0.001µ *

0.001µ *

+

10µ

Analog Supply

1.6

∼3.6V

13

NC NC

VSS

AK4186EN

VDD

14

15

T EST

Top View

WI PER

8

7

6

16

N C NC

5

0.1µ

0.001µ *

[AK4186]

Rp Rp

µP

“L” or “H”

Figure 38. Typical Connection Diagram (5-wire, AK4186EN)

Notes:

- VSS of the AK4186 should be distributed separately from the ground of external controllers.

- All digital input pins (SCL, SDA, CAD0 pins) must not be left floating.

1. Grounding and Power Supply Decoupling

The AK4186 requires careful attention to power supply and grounding arrangements. VDD is usually supplied from the system’s analog supply. VSS of the AK4186 must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board.

Decoupling capacitors should be as near to the AK4186 as possible, with the small value ceramic capacitor being the nearest.

2. Analog Inputs

When an EMI source is close to the touch panel analog signal line, EMI noise affects analog characteristics performance. Connect noise canceling capacitors (*) as close as possible to each pin (XP, XN, YP, YN pins) of the

AK4186 to avoid this noise. ( Figure 35

,

Figure 36 ,

Figure 37

,

Figure 38 )

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12pin CSP (Unit: mm)

PACKAGE (AK4186ECB)

S

Top View

1.66

± 0.05

XXXX

B

(0.23)

Bottom View

A

0.40

D C B

φ 0.27 ± 0.05

A

φ 0.05

M

S

AB

1

3

2

[AK4186]

0.08

S

Material & Lead finish

Package molding compound: Epoxy resin, Halogen (bromine and chlorine) free

Solder ball material: SnAgCu

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16pin QFN (Unit: mm)

PACKAGE (AK4186EN)

Top View

9

Bottom View

1.80

12

[AK4186]

8

13

A

B

1.50

3.00±0.07

0.22±0.05

4

Exposed

Pad

16

1

0.05 M S A B

C0.30

S

Part A

0.50

0.17~0.27

[Part A Detail]

0.05

S

Note: The thermal die pad must be open or connected to the ground.

Package & Lead frame material

Package molding compound: Epoxy Resin, Halogen (bromine and chlorine) free

Lead frame material: Cu Alloy

Lead frame surface treatment: Palladium Plate

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[AK4186]

MARKING (AK4186ECB)

XXXX

A1

Date Code: XXXX(4 digits)

Pin #A1 indication

MARKING (AK4186EN)

4186

XXXXX

Date Code: XXXXX (5 digits)

Pin #1 indication

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[AK4186]

REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page/Line Contents

09/03/30 00 Edition

Correction

18

/2

/6

Sequence Mode Data Register

“register address 03H” →“register address 02H”

SEQST7-0 = 03H → SEQST3-0 = 02H

Setup

Figure 27 was changed.

Addition

Spec

Change

CHARACTERISTICS

Gain Error (AK4186EN): -6 → -4.5 (min)

+2 → +3.5 (max)

Error

Correction

3 PIN/FUNCTION

Pin No. D3, 12: BL

“Touch Panel Bottom Right Input”

→ “Touch Panel Bottom Left Input”

IMPORTANT NOTICE

" These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

Microdevices Corporation (AKM) or authorized distributors as to current status of the products.

" Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein.

" Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.

" AKM products are neither intended nor authorized for use as critical components

Note1) other hazard related device or system

Note2)

in any safety, life support, or

, and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property.

" It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

MS1068-E-04

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