View detail for ATF15XX-DK2 CPLD Development/Programmer Kit

View detail for ATF15XX-DK2 CPLD Development/Programmer Kit

CPLD Development/Programmer Kit

..............................................................................................

User Guide

-2

xxxxA–XXXXX–xx/xx

CPLD Development/Programmer Kit User Guide

Table of Contents

Section 1

Introduction ........................................................................................... 1-1

1.1

CPLD Development/Programmer Kit ........................................................1-1

1.3

Kit Features...............................................................................................1-2

1.3.1

CPLD Development/Programmer Board ............................................1-2

1.3.2

Logic Doubling CPLDs .......................................................................1-2

1.3.3

CPLD ISP Download Cable ................................................................1-2

1.3.4

PLD Software CD-ROM......................................................................1-2

1.3.5

Atmel CD-ROM Data Books ...............................................................1-3

1.4

Device Support .........................................................................................1-3

1.5

System Requirements...............................................................................1-3

1.7

Technical Support .....................................................................................1-4

1.8.1

ProChip Designer ...............................................................................1-5

1.8.2

Atmel-WinCUPL .................................................................................1-5

1.8.3

ATMISP ..............................................................................................1-5

1.8.4

POF2JED ...........................................................................................1-5

Section 2

Hardware Description ........................................................................... 2-1

2.1

Atmel CPLD Development/Programmer Board.........................................2-1

2.1.1

8-segment Display LEDs ....................................................................2-2

2.1.2

Push-button Switches.........................................................................2-6

2.1.3

Clock Select Jumper...........................................................................2-6

2.1.4

VCC Select Jumper ............................................................................2-7

2.1.5

JTAG Port Header ..............................................................................2-7

2.1.6

Power Connectors ..............................................................................2-8

2.2.1

Expansion Terminal Holes..................................................................2-9

2.3

Atmel CPLD ISP Cable .............................................................................2-9

Section 3

CPLD Design Flow Tutorial .................................................................. 3-1

3.1

Overview ...................................................................................................3-1

3.2

Create a Project Using the “New Project Wizard” .....................................3-1

3.3

Add a Design File......................................................................................3-6

Section 4

Schematic Diagrams............................................................................. 4-1

CPLD Development/Programmer Kit User Guide i

3300A–PLD–08/02

Table of Contents ii

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

Section 1

Introduction

1.1

CPLD

Development/

Programmer Kit

The Atmel CPLD Development/Programmer Kit (P/N: ATF15xx-DK2) is a complete development system and an In-System Programming (ISP) programmer for the

ATF15xx family of industry-standard pin-compatible Complex Programmable Logic

Devices (CPLDs) with Logic Doubling

™ features. This kit provides designers a very quick and easy way to develop, prototype and evaluate new designs with an ATF15xx

CPLD. With the availability of the different Socket Adapter Boards to support all the package types offered in the ATF15xx family of ISP CPLDs, this CPLD Development/Programmer Board can be used as an ISP programmer to program the ATF15xx

ISP CPLDs in all the available package types through the industry-standard JTAG interface (IEEE 1149.1a-1993).

Figure 1-1.

Contents of the ATF15xx-DK2

CPLD Development/Programmer Kit User Guide 1-1

Rev. 3300A–PLD–08/02

Introduction

1.2

Kit Contents

n CPLD Development/Programmer Board n 84-lead PLCC Socket Adapter Board (P/N: ATF15xx-SAJ84)

(1) n Atmel CPLD ISP Download Cable n Atmel PLD Software CD-ROM (includes ProChip Designer

, Atmel-WinCUPL

™ other EPLD software) and n Atmel CD-ROM Data Books n One ATF1508AS 5V 84-lead PLCC Sample Device n One ATF1508ASVL 3.3V, low-power, 84-lead PLCC Sample Device n Atmel CPLD Development/Programmer Kit User Guide

Note: 1. Only the 84-lead PLCC Socket Adapter Board is included in this kit. Other Socket

Adapter Boards are sold separately. Please refer to Section 1.6 for ordering informa-

tion of the Socket Adapter Boards.

1.3

Kit Features

1.3.1

1.3.2

1.3.3

1.3.4

CPLD Development/

Programmer Board

Logic Doubling

CPLDs

CPLD ISP Download

Cable

PLD Software

CD-ROM

n 10-lead JTAG-ISP Port n Regulated Power Supply Circuitry for 9V DC Power Source n 5V or 3.3V V

CC

Operation n 84-lead PLCC Socket Adapter Board n Socket Adapter Board Headers n Expansion Terminal Holes for all Input and I/O pins of the ATF15xx Device n 2 MHz Crystal Oscillator n Eight 8-segment LED Displays n Global Clear and Output Enable Push Button Switches n ATF1508AS-15JC84, 5V 128-Macrocell ISP CPLD with Logic Doubling Architecture n ATF1508ASVL-20JC84, 3.3V Low-power 128-Macrocell ISP CPLD with Logic

Doubling Architecture n 5V/3.3V ISP Download Cable for PC Parallel Printer (LPT) Port n Free Atmel-WinCUPL ™

Design Software n 30-day Trial Version of Atmel ProChip Designer

Software n Full Licensed Version of Atmel ProChip Designer Software (permanent license required) n Atmel CPLD ISP Software (ATMISP) n POF2JED Conversion Utility n Logic Doubling Support and Documentation

1-2

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

Introduction

1.3.5

Atmel CD-ROM

Data Books

n Data Sheets n Application Notes n Manuals and User Guides

1.4

Device Support

The Atmel CPLD Development/Programmer Board supports the following devices in all speed grades and packages:

ATF1502AS/ASL

ATF1502ASV

ATF1502SE/SEL

ATF1502AE/AEL

ATF1504AS/ASL

ATF1504ASV/ASVL

ATF1504SE/SEL

ATF1504AE/AEL

ATF1508AS/ASL

ATF1508ASV/ASVL

ATF1508SE/SEL

ATF1508AE/AEL

ATF1516SE/SEL (Future)

ATF1516AE/AEL (Future)

ATF1532AE/AEL (Future)

1.5

System

Requirements

The minimum hardware and software requirements to program an ATF15xx ISP CPLD on the CPLD Development/Programmer Board through the Atmel CPLD ISP Software

(ATMISP) V4.0 or later are: n Pentium ® or Pentium-compatible microprocessor based computer n Windows

®

98, Windows NT

®

4.0, Windows ME, or Windows 2000 n 16-MByte RAM n 10-MByte free hard disk space n Windows-supported mouse n Available parallel printer (LPT) port n 9V DC power supply with 500 mA of supply current n SVGA monitor (800 x 600 resolution)

CPLD Development/Programmer Kit User Guide 1-3

3300A–PLD–08/02

Introduction

1.6

Ordering

Information

1.7

Technical

Support

Part Number

ATF15xx-DK2

ATF15xx-SAA44

ATF15xx-SAJ44

ATF15xx-SAC49

ATF15xx-SAJ68

ATF15xx-SAJ84

ATF15xx-SAA100

ATF15xx-SAQ100

ATF15xx-SACT100

ATF15xx-SAA144

ATF15xx-SAQ160

ATF15xx-SAC169

ATF15xx-SAQ208

ATF15xx-SACT256

Description

Atmel CPLD Development/Programmer Kit

44-lead TQFP Socket Adapter Board

44-lead PLCC Socket Adapter Board

49-lead BGA Socket Adapter Board

68-lead PLCC Socket Adapter Board

84-lead PLCC Socket Adapter Board

100-lead TQFP Socket Adapter Board

100-lead PQFP Socket Adapter Board

100-lead BGA Socket Adapter Board

144-lead TQFP Socket Adapter Board

160-lead PQFP Socket Adapter Board

169-lead BGA Socket Adapter Board

208-lead PQFP Socket Adapter Board

256-lead BGA Socket Adapter Board

For technical support on any Atmel PLD related issues, please contact the Atmel PLD

Applications Group at:

Hotline: 1-408-436-4333

Email: [email protected]

URL: www.atmel.com/atmel

1-4

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

Introduction

1.8

1.8.1

References

ProChip Designer

To help PLD designers use the different Atmel PLD software, documentation such as

Help Files, Tutorials, Application Notes/Briefs, and User Guides are available.

ProChip Designer

Help Files

Tutorials

Known Problems &

Solutions

From the ProChip Designer main window, click on HELP and then select PROCHIP DESIGNER HELP.

From the ProChip Designer main window, click on HELP and then select TUTORIALS.

From the ProChip Designer main window, click on HELP and then select REVIEW KPS.

1.8.2

Atmel-WinCUPL

Help Files

CUPL Programmers

Reference Guide

Tutorial

Known Problems &

Solutions

From the Atmel-WinCUPL main window, click on HELP and then select CONTENTS.

From the Atmel-WinCUPL main window, click on HELP and then select CUPL PROGRAMMERS REFERENCE.

From the Atmel-WinCUPL main window, click on HELP, select ATMEL

INFO and then select TUTORIAL1.PDF.

From the Atmel-WinCUPL main window, click on HELP, select ATMEL

INFO and then select CUPL_BUG.PDF.

1.8.3

ATMISP

Help Files

Tutorial

Known Problems &

Solutions

From the ATMISP main window, click on HELP and then select ISP

HELP.

From the ATMISP main window, click on HELP, and then select

ATMISP TUTORIAL.

Using Windows Explorer, go to the directory where ATMISP is installed and open the README.TXT file through any ASCII text editor.

1.8.4

POF2JED

ATF15xx Conversion

Application Brief

From the POF2JED main window, click on HELP and then select

CONVERSION OPTIONS.

CPLD Development/Programmer Kit User Guide 1-5

3300A–PLD–08/02

Introduction

1-6

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

Section 2

Hardware Description

2.1

Atmel CPLD

Development/

Programmer

Board

The Atmel CPLD Development/Programmer Board, along with the Socket Adapter

Board as shown in Figure 2-1, contains many features that designers will find very use-

ful when developing, prototyping, or evaluating their ATF15xx CPLD design. Features such as push-button switches, 8-segment display LEDs, 2 MHz crystal oscillator,

5V/3.3V V

CC selector, JTAG-ISP port, and expansion terminal holes make this a very versatile starter/development kit and an ISP programmer for the ATF15xx family of

JTAG-ISP CPLDs.

Figure 2-1.

CPLD Development/Programmer Board with 84-lead PLCC Socket Adapter Board

Power Supply

Header

Power Supply

Jack

8-segment

Display LEDs

2 MHz Crystal

Oscillator

Clock Select

Jumper

Power Switch

Power LED

84-pin PLCC

Socket

Expansion

Terminal Holes

JTAG Port

Header

V

CC

Select

Jumper

GCLR

Push-button

Switch

GOE

Push-button

Switch

CPLD Development/Programmer Kit User Guide 2-1

Rev. 3300A–PLD–08/02

Hardware Description

2.1.1

8-segment Display

LEDs

The Atmel CPLD Development/Programmer Board contains eight 8-segment LEDs to allow the designer to observe the outputs of the ATF15xx. These eight LEDs are labeled

DSP1 to DSP8 on the board. These eight display LEDs are common anode LEDs with the common anode lines connected to V

CC and the individual cathode lines connected to the I/O pins of the ATF15xx CPLD on the CPLD Development/Programmer Board. To turn on a particular segment of an LED, the corresponding ATF15xx I/O pin connected to this LED segment must be in a logical-0 state. Hence, the outputs of the ATF15xx need to be configured as active-low outputs in the design file.

Figure 2-2.

8-segment Display LED

A

F B

G

E

D

C

Dot

Each segment of the display LED is hard-wired to one specific I/O pin of the ATF15xx.

For the higher pin count devices (100-lead and larger), all eight segments of the eight

LEDs are connected to the I/O pins of the ATF15xx. However, for the lower pin count devices (84-lead and smaller), only a subset of the LED segments are connected to the

ATF15xx's I/O pins. Table 2-1 to Table 2-8 below show the connections of the LEDs to

the ATF15xx in all the different package types.

Table 2-1.

Connections of LEDs to ATF15xx 44-lead PLCC

DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

2/A

2/B

2/C

2/D

2/E

2/F

2/G

2/DOT

1/A

1/B

1/C

1/D

1/E

1/F

1/G

1/DOT

4/A

4/B

4/C

4/D

4/E

4/F

4/G

4/DOT

3/A

3/B

3/C

3/D

3/E

3/F

3/G

3/DOT

37

39

41

NC

36

33

34

40

27

29

31

NC

28

26

24

25

5/G

5/DOT

6/A

6/B

6/C

6/D

6/E

6/F

6/G

6/DOT

DSP/Sgt

5/A

5/B

5/C

5/D

5/E

5/F

14

17

19

20

12

NC

18

16

21

NC

PLD Pin #

6

4

11

9

5

8

7/G

7/DOT

8/A

8/B

8/C

8/D

8/E

8/F

8/G

8/DOT

DSP/Sgt

7/A

7/B

7/C

7/D

7/E

7/F

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

PLD Pin #

NC

NC

NC

NC

NC

NC

2-2

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

Table 2-2.

Connections of LEDs to ATF15xx 44-lead TQFP

DSP/Sgt

1/A

PLD Pin #

NC

DSP/Sgt PLD Pin #

3/A 21

2/C

2/D

2/E

2/F

2/G

2/DOT

1/B

1/C

1/D

1/E

1/F

1/G

1/DOT

2/A

2/B

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

4/C

4/D

4/E

4/F

4/G

4/DOT

3/B

3/C

3/D

3/E

3/F

3/G

3/DOT

4/A

4/B

28

34

31

33

35

NC

22

23

25

19

18

20

NC

30

27

DSP/Sgt

5/A

5/B

5/C

5/D

5/E

5/F

5/G

5/DOT

6/A

6/B

6/C

6/D

6/E

6/F

6/G

6/DOT

8

11

13

14

15

NC

PLD Pin #

44

42

43

2

5

3

6

NC

12

10

Table 2-3.

Connections of LEDs to ATF15xx 68-lead PLCC

DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #

NC

NC

NC

37

33

36

NC

NC

NC

NC

NC

39

41

40

42

NC

1/F

1/G

1/DOT

2/A

2/B

2/C

1/A

1/B

1/C

1/D

1/E

2/D

2/E

2/F

2/G

2/DOT

3/F

3/G

3/DOT

4/A

4/B

4/C

3/A

3/B

3/C

3/D

3/E

4/D

4/E

4/F

4/G

4/DOT

51

52

NC

56

54

55

47

45

44

46

49

61

59

60

64

NC

DSP/Sgt

5/A

5/B

5/C

5/D

5/E

5/F

5/G

5/DOT

6/A

6/B

6/C

6/D

6/E

6/F

6/G

6/DOT

8

10

NC

17

14

15

PLD Pin #

5

4

7

9

13

18

22

20

23

NC

CPLD Development/Programmer Kit User Guide

Hardware Description

DSP/Sgt

7/A

7/B

7/C

7/D

7/E

7/F

7/G

7/DOT

8/A

8/B

8/C

8/D

8/E

8/F

8/G

8/DOT

PLD Pin #

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

DSP/Sgt

7/A

7/B

7/C

7/D

7/E

7/F

7/G

7/DOT

8/A

8/B

8/C

8/D

8/E

8/F

8/G

8/DOT

28

30

NC

NC

NC

NC

PLD Pin #

25

24

27

29

32

NC

NC

NC

NC

NC

2-3

3300A–PLD–08/02

Hardware Description

Table 2-4.

Connections of LEDs to ATF15xx 84-lead PLCC

DSP/Sgt

1/A

PLD Pin #

49

DSP/Sgt PLD Pin #

3/A 67

2/C

2/D

2/E

2/F

2/G

2/DOT

1/B

1/C

1/D

1/E

1/F

1/G

1/DOT

2/A

2/B

56

58

61

60

63

NC

52

51

54

46

48

50

NC

57

55

4/C

4/D

4/E

4/F

4/G

4/DOT

3/B

3/C

3/D

3/E

3/F

3/G

3/DOT

4/A

4/B

75

77

80

79

81

NC

70

69

73

64

65

68

NC

76

74

DSP/Sgt

5/A

5/B

5/C

5/D

5/E

5/F

5/G

5/DOT

6/A

6/B

6/C

6/D

6/E

6/F

6/G

6/DOT

PLD Pin #

6

4

5

8

10

9

11

45

16

12

15

17

20

18

21

44

Table 2-5.

Connections of LEDs to ATF15xx 100-lead TQFP

DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #

45

42

49

54

41

40

47

52

48

46

44

56

58

57

60

55

1/F

1/G

1/DOT

2/A

2/B

2/C

1/A

1/B

1/C

1/D

1/E

2/D

2/E

2/F

2/G

2/DOT

3/F

3/G

3/DOT

4/A

4/B

4/C

3/A

3/B

3/C

3/D

3/E

4/D

4/E

4/F

4/G

4/DOT

69

71

61

80

76

78

67

64

63

65

68

84

81

83

85

75

DSP/Sgt

5/A

5/B

5/C

5/D

5/E

5/F

5/G

5/DOT

6/A

6/B

6/C

6/D

6/E

6/F

6/G

6/DOT

PLD Pin #

96

93

94

97

99

12

9

8

98

100

92

10

13

14

16

6

2-4

3300A–PLD–08/02

DSP/Sgt

7/A

7/B

7/C

7/D

7/E

7/F

7/G

7/DOT

8/A

8/B

8/C

8/D

8/E

8/F

8/G

8/DOT

PLD Pin #

25

22

24

27

29

28

30

41

34

31

33

35

37

36

39

40

DSP/Sgt

7/A

7/B

7/C

7/D

7/E

7/F

7/G

7/DOT

8/A

8/B

8/C

8/D

8/E

8/F

8/G

8/DOT

23

29

22

32

30

31

PLD Pin #

20

17

19

21

25

33

36

35

37

28

CPLD Development/Programmer Kit User Guide

Table 2-6.

Connections of LEDs to ATF15xx 100-lead PQFP

DSP/Sgt

1/A

PLD Pin #

48

DSP/Sgt PLD Pin #

3/A 69

2/C

2/D

2/E

2/F

2/G

2/DOT

1/B

1/C

1/D

1/E

1/F

1/G

1/DOT

2/A

2/B

42

58

60

59

62

52

44

46

43

50

49

47

51

56

54

4/C

4/D

4/E

4/F

4/G

4/DOT

3/B

3/C

3/D

3/E

3/F

3/G

3/DOT

4/A

4/B

81

86

83

85

87

77

70

71

73

66

65

67

63

82

78

DSP/Sgt

5/A

5/B

5/C

5/D

5/E

5/F

5/G

5/DOT

6/A

6/B

6/C

6/D

6/E

6/F

6/G

6/DOT

PLD Pin #

98

95

96

99

94

14

11

3

100

4

10

12

15

16

18

8

Table 2-7.

Connections of LEDs to ATF15xx 144-lead TQFP

DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #

81

83

77

88

86

87

79

78

74

80

82

91

93

92

94

84

1/F

1/G

1/DOT

2/A

2/B

2/C

1/A

1/B

1/C

1/D

1/E

2/D

2/E

2/F

2/G

2/DOT

3/F

3/G

3/DOT

4/A

4/B

4/C

3/A

3/B

3/C

3/D

3/E

4/D

4/E

4/F

4/G

4/DOT

102

107

97

118

119

117

100

98

99

101

106

114

112

116

113

111

DSP/Sgt

5/A

5/B

5/C

5/D

5/E

5/F

5/G

5/DOT

6/A

6/B

6/C

6/D

6/E

6/F

6/G

6/DOT

PLD Pin #

134

137

136

133

138

132

131

139

9

7

6

8

10

11

15

5

CPLD Development/Programmer Kit User Guide

Hardware Description

DSP/Sgt

7/A

7/B

7/C

7/D

7/E

7/F

7/G

7/DOT

8/A

8/B

8/C

8/D

8/E

8/F

8/G

8/DOT

PLD Pin #

22

19

21

23

27

25

39

24

37

38

35

33

31

34

32

30

DSP/Sgt

7/A

7/B

7/C

7/D

7/E

7/F

7/G

7/DOT

8/A

8/B

8/C

8/D

8/E

8/F

8/G

8/DOT

27

29

21

41

31

32

PLD Pin #

25

22

23

26

28

38

37

40

39

30

2-5

3300A–PLD–08/02

Hardware Description

Table 2-8.

Connections of LEDs to ATF15xx 160-lead PQFP

DSP/Sgt

1/A

PLD Pin #

91

DSP/Sgt PLD Pin #

3/A 102

2/C

2/D

2/E

2/F

2/G

2/DOT

1/B

1/C

1/D

1/E

1/F

1/G

1/DOT

2/A

2/B

2.1.2

2.1.3

68

92

94

93

96

70

73

78

72

89

90

80

88

69

71

4/C

4/D

4/E

4/F

4/G

4/DOT

3/B

3/C

3/D

3/E

3/F

3/G

3/DOT

4/A

4/B

109

123

111

121

122

107

100

98

101

103

105

106

97

110

108

DSP/Sgt

5/A

5/B

5/C

5/D

5/E

5/F

5/G

5/DOT

6/A

6/B

6/C

6/D

6/E

6/F

6/G

6/DOT

PLD Pin #

11

159

160

10

12

13

14

158

20

18

16

19

21

23

24

15

DSP/Sgt

7/A

7/B

7/C

7/D

7/E

7/F

7/G

7/DOT

8/A

8/B

8/C

8/D

8/E

8/F

8/G

8/DOT

Push-button

Switches

Two push-button switches are provided to allow the user to control the logic states of the

OE1 and GCLR inputs of the ATF15xx. These two switches are labeled GOE and GCLR on the board. The GCLR push-button switch is a momentary Single-Pole Single-Throw

(SPST) normally open switch while the GOE push-button switch is a snap-acting momentary SPST normally open switch. As shown in the CPLD Development/Program-

mer Board schematic in Figure 4-1, these two switches are normally open and the

GCLR and GOE signals are pulled-up to V

CC when they are not depressed. When the switches are depressed, the GCLR and GOE signals are connected to GND.

The output of the GCLR switch is connected to the GCLR dedicated input pin of the

ATF15xx, and it is intended to be used as an active-low reset signal to reset the registers in the ATF15xx. The output of the GOE switch is connected to the OE1 dedicated input pin of the ATF15xx. It is intended to be used as an active-high or active-low output enable signal to control the enabling/disabling of the tri-state output buffers in the

ATF15xx. However, these two switches can also be used to generate general logic input signals to the GCLR and OE1 input pins of the ATF15xx.

Clock Select Jumper

The Clock Select Jumper, labeled JPCLK, on the CPLD Development/Programmer

Board is a two-position jumper that allows the user to select which GCLK dedicated input pin (either GCLK1 or GCLK2) of the ATF15xx should be connected to the output of the 2 MHz crystal oscillator. In addition, the jumper can be removed to allow an external clock source to be connected to GCLK1 and/or GCLK2 of the ATF15xx.

Table 2-9 shows the pin numbers for the GCLR, OE1, GCLK1 and GCLK2 dedicated

input pins of the ATF15xx in all the available package types.

PLD Pin #

29

27

28

52

50

53

51

25

43

49

30

31

32

41

33

48

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CPLD Development/Programmer Kit User Guide

Hardware Description

Table 2-9.

Pin Numbers of GCLR, OE1, GCLK1 and GCLK2

Signal

GCLR

OE1

GCLK1

GCLK2

2.1.4

2.1.5

44-lead

TQFP

39

38

37

40

44-lead

PLCC

1

44

43

2

V

CC

Select Jumper

JTAG Port Header

68-lead

PLCC

1

68

67

2

84-lead

PLCC

1

84

83

2

100-lead

PQFP

91

90

89

92

100-lead

TQFP

89

88

87

90

144-lead

TQFP

127

126

125

128

160-lead

PQFP

141

140

139

142

The V

CC

Select Jumper, labeled VCC Select, on the CPLD Development/Programmer

Board is a two-position jumper that allows the users to select the V

CC voltage level

(either 3.3V or 5.0V) used by various components on the CPLD Development/Programmer Board. This voltage generated by the on-board voltage regulation circuitry is applied to the V

CC input pins (both VccINT and VccIO) of the ATF15xx, the common anode lines of the eight 8-segment LEDs, the V

CC the two push-button switches, and the V

CC input of the 2 MHz crystal oscillator, pin (Pin 4) of the 10-pin JTAG port header labeled JTAG.

Therefore, when a 3.3V device (ATF15xxASV/ASVL/AE/AEL) is used on this board, the

V

CC

Select Jumper must be in the 3.3V position. On the other hand, when a 5V device

(ATF15xxAS/ASL/SE/SEL) is used on this board, the V

CC

Select Jumper must be in the

5.0V position. This is also true when the ATF15xx is being programmed through ISP on this board.

The JTAG Port Header, labeled JTAG, on the CPLD Development/Programmer Board is used to connect the ATF15xx's JTAG port pins (TCK, TDI, TMS and TDO) through the

ISP download cable to the parallel printer (LPT) port of a PC for ISP programming of the

ATF15xx. Table 2-10 shows the pin numbers for the four JTAG port pins of the ATF15xx

in all the available package types.

Table 2-10.

Pin Numbers of JTAG Port Signals

Signal

TDI

TDO

TMS

TCK

44-lead

TQFP

1

32

7

26

44-lead

PLCC

7

38

13

32

68-lead

PLCC

12

57

19

50

84-lead

PLCC

14

71

23

62

100-lead

PQFP

6

75

17

64

100-lead

TQFP

4

73

15

62

144-lead

TQFP

4

104

20

89

160-lead

PQFP

9

112

22

99

The ISP algorithm is controlled by the ATMISP software, which runs on the PC. The four JTAG signals are generated by the LPT port and they are buffered by the ISP download cable before going into the ATF15xx on the CPLD Development/Programmer

Board. The pinout for the 10-pin JTAG Port Header on the CPLD Development/Pro-

grammer Board is shown in Figure 2-3 and the dimensions of this 10-pin male JTAG header are shown in Figure 2-4.

CPLD Development/Programmer Kit User Guide 2-7

3300A–PLD–08/02

Hardware Description

Figure 2-3.

Pinout Diagram of 10-pin JTAG Port Header (Top-view)

TCK

TDO

TMS

NC

TDI

5

7

9

1

3

2

4

6

8

10

GND

VCC

NC

NC

GND

Figure 2-4.

10-pin Male Header Dimensions

Top View

0.100

0.100

Side View

0.025 Sq.

0.235

All dimensions are in inches

2.1.6

Power Connectors

The pinout of this 10-pin JTAG Port Header is compatible with the Altera

® and ByteBlasterMV

ByteBlaster

™ cables. In addition, the ATMISP software allows users to choose either the Atmel CPLD ISP Cable or the ByteBlaster/ByteBlasterMV cable to implement

ISP.

The Atmel CPLD Development/Programmer Board contains two different types of power connectors, and either one can be used to connect to a 9V DC power source to power the board. The first power connector, labeled JPower, is a barrel power jack with a

2.1 mm diameter post and it mates to a 2.1 mm (inner diameter) x 5.5 mm (outer diameter) female plug. The second power connector, labeled JP Power, is a 4-pin male 0.1" header with 0.025" square posts. The availability of these two types of power connectors allows the users to choose the type of power supply equipment to use for the CPLD

Development/Programmer Board.

2-8

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

Hardware Description

2.2

2.2.1

Socket Adapter

Board

Expansion Terminal

Holes

Atmel CPLD Development/Programmer Socket Adapter Boards are circuit boards that interface with the Atmel CPLD Development/Programmer Board. They are used in conjunction with the CPLD Development/Programmer Board to evaluate/program Atmel ISP

CPLDs in different package types. Currently, there are nine Socket Adapter Boards available covering all the package types offered in the ATF15xx family of CPLDs. They include 44-lead PLCC, 44-lead TQFP, 68-lead PLCC, 84-lead PLCC, 100-lead TQFP,

100-lead PQFP, 144-lead TQFP and 160-lead PQFP. New Socket Adapter Boards will become available when new packages are offered.

Each socket adapter board contains a socket for the Atmel ATF15xx device on the top side and male headers on the bottom side. The headers on the bottom side mate with the female headers, labeled JPLEFT and JPRIGHT, on the CPLD Development/Programmer Board. The eight 8-segment LEDs, push-button switches, JTAG port signals, crystal oscillator, V

CC

, and GND on the CPLD Development/Programmer Board are connected to the ATF15xx device on the Socket Adapter Board through these two rows of connectors.

Rows of expansion terminal holes suitable for 0.1" headers with 0.025" square posts are available on each of the Socket Adapter Boards to allow users to interface the ATF15xx to an external circuit board. All input and I/O pins except the four JTAG port pins of the

ATF15xx are routed to these expansion terminal holes, and the corresponding pin numbers are marked next to the terminal holes. Please refer to the Socket Adapter Board

schematics in Section 4 for the pinouts of the expansion terminal holes.

On the bottom side of the Socket Adapter Boards, traces connecting the pairs of expansion terminal holes can be cut to isolate the LEDs, push-button switches and crystal oscillator from the ATF15xx on the Socket Adapter Board. This allows the users to gain complete control and access to all input and I/O pins of the ATF15xx.

2.3

Atmel CPLD ISP

Cable

The Atmel CPLD ISP Cable connects the parallel printer (LPT) port of the user’s PC to the 10-pin JTAG header on the Atmel CPLD Development/Programmer Board or a cus-

tom circuit board. This is shown in Figure 2-5. This ISP cable acts as a buffer to buffer

the JTAG signals between the PC's LPT port and the ATF15xx on the circuit board. The

circuit schematic of the Atmel CPLD ISP Cable is shown in Figure 4-10 and Figure 4-11.

The Power-On LED on the back of the 25-pin male connector housing indicates that the cable is connected properly. Make sure this LED is turned on before using the Atmel

CPLD ISP Software (ATMISP).

This ISP cable consists of a 25-pin (DB25) male connector, which is connected to the

LPT port of a PC. The 10-pin female plug connects to the 10-pin male JTAG header on the ISP circuit board. The red color stripe on the ribbon cable indicates the orientation of

Pin 1 of the female plug. The 10-pin male JTAG header on the CPLD Development/Programmer Board is polarized to prevent users from inserting the female plug in the wrong orientation.

If the user is attempting to program low voltage (3.3V) devices, the user needs to use

Rev. 4 or later of the Atmel CPLD ISP Cable. This and later revisions will support both the 3.3V and 5V ATF15xx ISP CPLDs. Earlier revisions of the cable only supported 5V devices.

When programming 3.3V devices, the V

CC

3.3V. Similarly, the V

CC supplied to the ISP cable should also be supplied to the ISP cable should be 5.0V when programming

5V devices.

CPLD Development/Programmer Kit User Guide 2-9

3300A–PLD–08/02

Hardware Description

Figure 2-5.

Atmel ISP Cable Connection to ISP Hardware Board/Circuit Board

Figure 2-6 shows the pinout for the 10-pin Female header on the Atmel-ISP Cable. The

pinout on the 10-pin male header on the PC board (if used for ISP) must match this pinout.

Figure 2-6.

Atmel ISP Download Cable 10-pin Female Header Pinout

Note:

The user’s circuit board must supply VCC and GND to the Atmel CPLD ISP

Cable through the 10-pin male header (See Figure 2-3).

2-10

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

Section 3

CPLD Design Flow Tutorial

3.1

Overview

This tutorial will guide the user through a complete design cycle for the Atmel ATF15xx

CPLD with Logic Doubling architecture. It will go through each phase of the design cycle step-by-step from design entry, logic synthesis, device fitting, in-system programming, and finally verifying the design on the Atmel CPLD Development/Programming Board.

Note:

To complete this tutorial, ProChip Designer V4.0 or later and Atmel-ISP Software (ATMISP) V4.0 or later are required.

3.2

Create a Project

Using the “New

Project Wizard”

Before starting the design process, a Project File must be created within ProChip

Designer. ProChip Designer's New Project Wizard provides a very easy way to create a new Project File.

1.

Click on the START .... PROGRAMS .... PROCHIP Icon to launch ProChip

Designer. Or double-click on the PROCHIP icon on the desktop.

(1) Click to launch

ProChip Designer

CPLD Development/Programmer Kit User Guide 3-1

Rev. 3300A–PLD–08/02

CPLD Design Flow Tutorial

2.

Click on PROJECT .... NEW or double-click on the NEW PROJECT shortcut button to launch the New Project Wizard.

(2)

Click to create

New Project

3.

Click on the NEXT button to start the project file creation process.

3-2

3300A–PLD–08/02

(3) Click Next to Start

4.

Click on the BROWSE button to open the browser window.

5.

Use C:\PROCHIP\DESIGNS\CUPL as the directory of the project.

6.

Enter DEV_KIT.APJ as the project filename. The extension of a project file must be .APJ.

Note:

The name and directory of the design project is specified in this window. All design, simulation and other project files must be placed in this project directory.

(4) Click on

Browse

(5) Select the

Project Directory

(6) Enter the

Project Filename

CPLD Development/Programmer Kit User Guide

CPLD Design Flow Tutorial

7.

Choose [ATF1508AS-10JC84] as the target device type for the project. Also review the

Filters

that allow for selection of a specific

Speed Grade

or

Package

Type

.

(7) Select the

Device Type

8.

Select CUPL – ALTIUM as the software tool for this design flow.

(8)Select the

Design Flow

With ProChip Designer V4.0 and later, the five possible design flows and their corresponding design entry types supported are listed in the table below:

Design Flow

CUPL – Altium

Verilog – Exemplar

™(1)

Design Entry Type

CUPL design entry through Altium Protel

99SE

Verilog

® design entry through Exemplar Leonardo Spectrum

VHDL – Altium

VHDL – Exemplar

(1)

VHDL design entry through the Altium PeakFPGA

VHDL design entry through Exemplar Leonardo Spectrum

Schematic – Altium Schematic design entry through Altium Protel 99SE

Note: 1. Design flow require Mentor Graphics

®

Leonardo Spectrum software with Atmel CPLD support.

CPLD Development/Programmer Kit User Guide 3-3

3300A–PLD–08/02

CPLD Design Flow Tutorial

9.

Select DONE WITH PARTS so that there will be only one device in this project.

On the other hand, users can select ADD MORE PARTS to include more parts to the current Project Directory.

(9) Select Done with Parts

10. Click the FINISH button to finish the New Project Wizard and the project creation process.

This closes the

New Project Wizard

and opens the

ProChip Designer

window. The

Sources

in the project are shown in the Left window.

(10) Click Finish to End

New Project Wizard

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CPLD Development/Programmer Kit User Guide

CPLD Design Flow Tutorial

11. Click on the Device Icon [ATF1508AS-10JC84] to view the window.

Design Flow

Project Sources Window Information Dialog Box

Message Window

Project File Window

(11) Click on the Device Icon

Design Flow Window

CPLD Development/Programmer Kit User Guide 3-5

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CPLD Design Flow Tutorial

3.3

Add a Design

File

Once the Project File is created, the next step is to add the design source file(s) into the user’s project. For this tutorial, a single CUPL design file will be added into the project.

1.

Click on the ADD/EDIT button from

Source Manager

to open the

Source Manager Window

. The user can view the

Source Manager

Help File by clicking on the Help button within the

Source Manager Window

to view the description for the different processes.

2.

In the

Source Manager Window

file to the project.

, click on the ADD button to add a CUPL design

3.

In the

File Manager Window

, select LOGIC_D8.PLD from the

C:\PROCHIP\DESIGNS\CUPL

directory as the source design file for this project.

3-6

3300A–PLD–08/02

(1)

Click Add/Edit to Open Source

Manager Window

(3)

Select CUPL

Source File

(2) Click ADD to add Design File

This "LOGIC_D8.PLD" is a CUPL design that uses the eight 8-segment LED displays and the 2 MHz oscillator on the Atmel CPLD Development/Programmer Board to generate a scrolling message that displays the words "logic doubling" on the LEDs. The GOE push-button switch is used to control the direction that the message scrolls in (left or right). The GCLR push-button switch is used to reset the counter registers. When the

GCLR push-button switch is depressed, the message will stop scrolling. This CUPL design can be compiled using either the ProChip Designer or the Atmel-WinCUPL software.

The first section of the LOGIC_D8.PLD as shown below pre-defines which segments of the LED should be asserted in order to display the desired letter or number. For example, to display the upper case letter "C", segments A, D, E, and F need to be set to low

(active low) and the remaining segments need to be set to high.

$define Font0 'b'1000000 /* = ( _f_e_d_c_b_a );

$define Font1 'b'1111001 /* = ( _c_b );

:

$define FontA 'b'0001000 /* = (_g_f_e _c_b_a );

0 */

1 */

A */

CPLD Development/Programmer Kit User Guide

CPLD Design Flow Tutorial

The next section of this CPLD design as shown below illustrates how to declare and assign pin numbers in the CUPL language to the input and output signals. The input and output pin assignments are assigned according to the connections between the CPLD

and the eight 8-segment LED's as shown in the connection tables (Table 2-1 to Table 2-

8) in Section 2.

/* Inputs */ pin 1 = GCLR; /* Global Clear input */ pin 83 = MCLK; /* Global Clock input */ pin 84 = GOE; /* GOE1 button used as direction control */

/* Outputs */

/* DSP1 */ pin 49 = LED1A; /* LED1 segment A */ pin 46 = LED1B; /* LED1 segment B */ pin 48 = LED1C; /* LED1 segment C */ pin 50 = LED1D; /* LED1 segment D */ pin 52 = LED1E; /* LED1 segment E */ pin 51 = LED1F; /* LED1 segment F */ pin 54 = LED1G; /* LED1 segment G */

Next, the buried signals for the counter and state machine are declared as PINNODE's as shown below. The feedback and/or the foldback paths available in each macrocell implement these buried signals. For the listing of the pinnode numbers, please refer to the "ATF15xx Device Help" section of the ProChip Designer Help File.

pinnode [618,634,650,687]= [CA20..CA17]; pinnode = [CA16..CA0]; pinnode = [SM7..SM0];

After assigning the input, output and buried signals, the related signals (i.e. the LED segments and buried counter) are grouped together as shown below to make the design source code more readable and manageable. In CUPL, the "Field" declaration can be used to group a specific set of signals.

Field DSP1 = [LED1G,LED1F,LED1E,LED1D,LED1C,LED1B,LED1A];

Field DSP2 = [LED2G,LED2F,LED2E,LED2D,LED2C,LED2B,LED2A];

:

Field CNT_A = [CA20..CA0];

Field SM = [SM7..SM0];

Next, a 21-bit buried up-counter implemented using D-type Flip-flops is shown below and it is used to divide the 2.0 MHz clock into a 0.954 Hz (2 MHz

÷ 2

21

= 0.954 Hz) signal that can be used to display the text messages. The last bit of this counter is used as the clock for the state machine that controls the display sequence of the messages on the LEDs.

CA0.d = !CA0;

CA1.d = CA0 $ CA1;

:

CA7.d = (CA6 & CA5 & CA4 & CA3 & CA2 & CA1 & CA0) $ CA7;

:

CNT_A.ck = MCLK;

CNT_A.ar = !GCLR;

CPLD Development/Programmer Kit User Guide 3-7

3300A–PLD–08/02

CPLD Design Flow Tutorial

The next section of this PLD design is a state machine with 15 states to control the display sequence of the text messages on the LEDs. The GOE push-button switch on the

CPLD Development/Programmer Board controls the flow of this state machine. When this switch is in the "up" position, the state machine will go from RESET to State-0 to

State-1 to State-2 and so on until it reaches State-14 and then it will go back to State-0.

On the other hand, if the GOE switch is in the "down" position, the state machine will go in the opposite direction (i.e. State-14 to State13 .. etc).

SM.ck = COUNTER_1; sequence SM

{ present RESET

next S0; present S0 if SM_DIR next S1; if !SM_DIR next S14;

: present S14

} if SM_DIR next S0; if !SM_DIR next S13;

Finally, the last section of the PLD design will assign the appropriate letters or numbers to the eight 8-segment LEDs to be displayed during the different states of the state machine. The user can easily change the letters/numbers to be displayed by changing this section of the code to the appropriate pre-defined letters/numbers.

LED1 = FontBK & SM:[RESET]

# FontBK & SM:[S0]

# FontLl & SM:[S1]

# FontLo & SM:[S2]

# FontLg & SM:[S3]

# FontLi & SM:[S4]

# FontLc & SM:[S5]

# FontBK & SM:[S6]

# FontLd & SM:[S7]

# FontLo & SM:[S8]

# FontLu & SM:[S9]

# FontLb & SM:[S10]

# FontLl & SM:[S11]

# FontLi & SM:[S12]

# FontLn & SM:[S13]

# FontLg & SM:[S14];

3-8

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

3.4

Compile the

CUPL Design

CPLD Design Flow Tutorial

In this part of the tutorial, the CUPL design will be compiled through the Logic Synthesis process into a set of optimized/minimized logic equations.

1.

Click on the CUPL – Design Ex. button in the Design Flow Window to open the

Logic Synthesis Window.

(1) Open Logic

Synthesis

2.

Make sure all of the options in the

Optimization

section are unchecked.

3.

Make sure the

Minimization

setting is set to Quick.

4.

Click on the Compile button to start the CUPL compile process.

(2) Make sure these

Options are

Not Checked

(3) Set to

Quick

(4) Start the

Compile

Process

The user can click on the Set Defaults button and it will automatically specify the Synthesis tool in the Tool Text box.

If the user clicks on the CUPL Tab, it shows the various Synthesis options. Please refer to the HELP file for further description.

CPLD Development/Programmer Kit User Guide 3-9

3300A–PLD–08/02

CPLD Design Flow Tutorial

3.5

Fit the

Synthesized

Design File

In Section 3.4, the Logic Synthesis portion of the CPLD Design Flow was completed. On

successful compilation, the CUPL compiler tool produces a PLA output file (with extension .pla). A PLA file contains the netlist of the optimized and minimized logic equations.

It is now necessary to map this netlist into a specific Atmel PLD architecture using the

Atmel Fitter.

1.

The user can now proceed to the Device Fitter portion of the Design Flow by clicking on the Atmel Fitter button.

(1) Open the Atmel

Fitter Window

The user can either use the Default options or specify Fitter properties. ProChip

Designer will automatically select the PLA file associated to the current design project and the tool type. In this example, since the target device is an ATF1508AS, the fit1508.exe device fitter will be selected.

The fitter creates the important JEDEC and FIT REPORT output files. They contain the data for programming the Device (using In-System Programming or on a third party device programmer) and the pin assignments required for board layout respectively.

Please review the Global Device Parameters and Pin/Node Options as well. The Help

Files also show the Device Pin_Node lists for each of the ATMEL CPLDs.

2.

Make sure the JTAG box is checked. This enables the JTAG port for ISP programming.

3.

Make sure the

PIN FIT CONTROL

setting is set to Keep. This will ensure that the pin assignments in the PLD file will be kept during the Place-and-Route process.

4.

When all the fitter options are set, click on the Run Fitter button to fit the design.

(2)Check the

JTAG box

(3) Set the Pin Fit

Control setting to KEEP

3-10

3300A–PLD–08/02

(4) Start the

Fitting Process

CPLD Development/Programmer Kit User Guide

CPLD Design Flow Tutorial

The Fitter Report (.FIT) File generated for this design is shown below.

Logic Array Block

Cascades

A: LC1 - LC16

B: LC17 - LC32

C: LC33 - LC48

D: LC49 - LC64

E: LC65 - LC80

F: LC81 - LC96

G: LC97 - LC112

H: LC113- LC128

Logic Cells

16/16(100%)

16/16(100%)

16/16(100%)

16/16(100%)

16/16(100%)

16/16(100%)

16/16(100%)

16/16(100%)

I/O Pins

8/16(50%)

8/16(50%)

8/16(50%)

6/16(37%)

6/16(37%)

8/16(50%)

8/16(50%)

8/16(50%)

Foldbacks

5/16(31%)

3/16(18%)

2/16(12%)

2/16(12%)

6/16(37%)

2/16(12%)

3/16(18%)

2/16(12%)

TotalPT

46/80(57%)

51/80(63%)

48/80(60%)

40/80(50%)

55/80(68%)

47/80(58%)

43/80(53%)

42/80(52%)

FanIN

(19)

(38)

(38)

(38)

(32)

(38)

(25)

(34)

0

0

0

0

0

0

0

0

Total dedicated input used: 3/4

Total I/O pins used

(75%)

60/64 (93%)

Total Logic cells used

Total Flip-Flop used

128/128 (100%)

31/128 (24%)

Total Foldback logic used 25/128 (19%)

Total Nodes+FB/MCells 153/128 (119%)

Total cascade used 0

Total input pins

Total output pins

7

56

Total Pts 372

:

The ATF15xx Family devices Logic Doubling features provide extra I/O connectivity and logic reusability. Some of the Logic Doubling features available in the ATF15xx family of

CPLDs are: n Bury either Register or Combinatorial signal while using the other for output n Dual independent feedback allows multiple latch functions per macrocell n 5 product terms per macrocell, expandable to 40 per macrocell with cascade logic, plus 15 more with foldback logic n D/T/Latch configurable flip-flops plus transparent latches n Global and/or per macrocell Output Enable n Single level Switch Matrix n Up to 40 inputs per Logic Block

In the LOGIC_D8.PLD example given in this tutorial, Logic Blocks B, C D, and F have

37 or more signal inputs (Fan-In's) as shown in the Universal-Interconnect-Multiplexer assignments section of the .FIT file. The availability of wide Fan-In's to the Logic Blocks is one of the many Logic Doubling features. This feature improves the possibility of routing all the necessary signals from the Global Bus to the Logic Blocks.

In addition, macrocells 37 and 59 of the ATF1508 are able to implement both combinatorial outputs (LED1G and LED8D) and buried registered signals (CA0 and RST) within the same macrocells. This is shown in the Resource Usage section of the .FIT file.

For more examples of design techniques that utilize the Logic Doubling features of the

ATF15xx Family, refer to Atmel's Logic Doubling White Paper and Reference Designs available on the Atmel website. These examples show how to apply Logic Doubling techniques to new product designs, to obtain the benefits of more features in a smaller and possibly less expensive chip, or spare logic resources for future revisions and reduce the risk of PCB re-spin.

CPLD Development/Programmer Kit User Guide 3-11

3300A–PLD–08/02

CPLD Design Flow Tutorial

3.6

Program and

Verify Design

In this step of the tutorial, the user will program an ATF1508AS 84-pin PLCC device on the Atmel CPLD Development/Programmer Board through ISP and then verify the design by observing the text messages displayed on the eight 8-segment LED displays of the CPLD Development/Programmer Board.

The user will need to follow the steps below to setup the ATMISP software in order to program the ATF1508AS 84-pin PLCC on the CPLD Development/Programmer Board.

1.

To create a new chain file, the ATMISP Software first needs to be launched either through the PROGRAM CHIP button in the ProChip Designer window, the

ATMISP desktop icon or the

Start ... Programs .. Atmel ISP

menu.

(1)

Launch

ATMISP

If ATMISP is launched through ProChip Designer, steps 2 to 6 below can be skipped since ProChip Designer will automatically setup the appropriate chain file for the ISP operation.

2.

To create a new chain file, select the New command under the File menu or click on the New Shortcut Button.

3-12

3300A–PLD–08/02

(2) Create New

Chain File

3.

The first piece of information that the software asks for when creating a new chain is the number of devices in the JTAG chain. Therefore, enter 1 and then click OK since a 1-device JTAG chain will be programmed.

(3) Enter the number of devices

4.

Next the user will need to specify the properties of each JTAG device in the

Device Properties window. First, select the target device type of the first device in the JTAG chain. For this tutorial, please select ATF1508AS as the target device type.

5.

In the JTAG Instruction field, the user can specify the appropriate JTAG instruction to be executed on this device in the chain. Please select Program/Verify to program and verify the ATF1508AS.

CPLD Development/Programmer Kit User Guide

CPLD Design Flow Tutorial

6.

The next step is to specify the JEDEC file to be programmed into the target device in the JEDEC File field. Click on the Browse button, change the directory to [..\PROCHIP\DESIGNS\CUPL"] and then select LOGIC_D8.JED as the target JEDEC file. Click OK to close the JTAG Device Properties window when all properties are specified.

(5) Specify

JTAG

Instruction

(4) Specify

Target

Device Type

(6) Select

JEDEC

File

The next few steps require the user to setup the Atmel CPLD Development/Programmer

Board to program the ATF1508AS through ISP.

7.

Connect the 25-DB side of the Atmel-ISP Cable to the PC's parallel port and the

10-pin header side of the Atmel-ISP Cable to the Atmel CPLD Development

Board as shown Figure 2-5.

8.

Connect a 9V AC/DC power adapter to the power connector (JPower) of the

Atmel CPLD Development/Programmer Board.

9.

Set the 5V/3.3V jumper to 5V. This will set the system board V

CC to 5V.

10. Set the JPCLK jumper to GCLK1 so that the output of the crystal oscillator will be connected to Pin 83 of the ATF1508AS.

11. Connect the 84-pin PLCC Socket Adapter Board onto the main Development/Programmer Board.

Note: If a device in a different package type is to be programmed, then the appropriate Socket

Adapter Board must be used.

12. Switch the Power Switch to the ON position.

13. Select the appropriate LPT port in the

Port Setting

field. LPT 1 is the default port.

14. Select the ISP download cable type in the

Cable Types

field. The default cable type is the Atmel ISP Cable but it can be changed to the Altera ByteBlaster cable if the ByteBlaster cable is being used.

Now both the user’s software and hardware are setup for ISP programming, and the user can execute the PROGRAM/VERIFY instruction to program the ATF1508AS on the Atmel CPLD Development/Programmer Board.

CPLD Development/Programmer Kit User Guide 3-13

3300A–PLD–08/02

CPLD Design Flow Tutorial

15. Click on the Run button in the ATMISP main window to execute the JTAG instruction to program the ATF1508AS on the CPLD Development/Programmer

Board.

(13) Select

LPT Port

Number

(14) Select

Cable

Type

(15) Click on the

RUN Button

After successfully programming the ATF1508AS with the LOGIC_D8.JED file, the eight

8-segment LED's will display the words "Logic Doubling".

If these two text messages are correctly displayed on the CPLD Development/Programmer Board, then the user has successfully completed this tutorial.

3-14

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

Section 4

Schematic Diagrams

CPLD Development/Programmer Kit User Guide 4-1

Rev. 3300A–PLD–08/02

Schematic Diagrams

Figure 4-1.

Schematic Diagram of the Atmel CPLD Development/Programmer Board

3

4

1

2

4-2

3300A–PLD–08/02

3

2

1

1

5

3

1

5

3

1

6

4

2

6

4

2

D4B

D4C

D 4 E

D4F

D5A

D5B

D5C

D5D

D5F

D5G

D6A

D6B

D6D

D 6 E

D7B

D7C

D 7 E

D7F

D8A

D8B

D8C

D8D

D8F

D8G

D1B

D1C

D 1 E

D1F

D2A

D2B

D2C

D2D

D2F

D2G

D3A

D3B

D3D

D 3 E a b c d e f g a b c d e f g c d e f g a b a b c d e f g e f g a b c d a b c d e f g a b c d e f g f g d e a b c

1

2

3

CPLD Development/Programmer Kit User Guide

VCC

GOE

D5B

D5A

D5F

D5G

D6B

D6A

D6F

D6G

GND

VCC

GCLK1

D4G

D4F

D4A

D4B

D3G

D3F

D3A

D3B

TCK

GND

JPRIGHT

15

17

19

21

23

25

27

5

7

1

3

9

11

13

29

31

33

35

37

39

HEADER 20X2

16

18

20

22

24

26

28

10

12

14

6

8

2

4

30

32

34

36

38

40

28

30

32

34

18

20

22

24

26

10

12

14

16

2

4

6

8

36

38

40

HEADER 20X2

JPLEFT

27

29

31

33

17

19

21

23

25

9

11

13

15

1

3

5

7

35

37

39

GND

GCLR

D5C

D5D

D5E

TDI

D6C

D6D

D6E

TMS

VCC

GND

GCLK2

D4D

D4E

D4C

TDO

D3E

D3D

D3C

VCC

TDI

D5D

D5F

GND

D5E

D5G

TMS

D6C

VCC

D6B

D6D

P8

P9

P11

P12

P14

P16

P17

9

10

7

8

11

12

13

14

15

16

17

TDI

I/O

I/O

GND

I/O

I/O

TMS

I/O

VCC

I/O

I/O

ATMEL PLCC44

I/O

TDO

I/O

I/O

VCC

I/O

I/O

TCK

I/O

GND

I/O

U1

35

34

33

32

31

30

29

39

38

37

36

PLCC44

P39

P37

P36

P34

P33

P31

P29

D4F

TDO

D4E

D4A

VCC

D4C

D4B

TCK

D3G

GND

D3F

VCC c1

0.1uF

c2

0.1uF

c3

0.1uF

c4

0.1uF

VCC

GOE

D5B

D5A

D5F

D5G

D6B

D6A

D6F

D6G

GND

VCC

GCLK1

D4G

D4F

D4A

D4B

D3G

D3F

D3A

D3B

TCK

GND

JPLEFT

23

25

27

29

15

17

19

21

31

33

35

5

7

1

3

9

11

13

37

39

HEADER 20X2

24

26

28

30

16

18

20

22

32

34

36

10

12

14

6

8

2

4

38

40

JPRIGHT

23

25

27

29

15

17

19

21

31

33

35

5

7

1

3

9

11

13

37

39

HEADER 20X2

24

26

28

30

16

18

20

22

32

34

36

10

12

14

6

8

2

4

38

40

VCC

VCC

GND

GCLR

D5C

D5D

D5E

TDI

D6C

D6D

D6E

TMS

GND

GCLK2

D4D

D4E

D4C

TDO

D3E

D3D

D3C

TDI

D5D

D5F

GND

D5E

D5G

TMS

D6C

VCC

D6B

D6D

P2

P3

P5

P6

P8

P10

P11

3

4

1

2

5

6

9

10

7

8

11

TDI

I/O

I/O

GND

I/O

I/O

TMS

I/O

VCC

I/O

I/O

ATMEL TQFP44

I/O

TDO

I/O

I/O

VCC

I/O

I/O

TCK

I/O

GND

I/O

U1

33

32

31

30

29

28

27

26

25

24

23

TQFP44

P33

P31

P30

P28

P27

P25

P23

D4F

TDO

D4E

D4A

VCC

D4C

D4B

TCK

D3G

GND

D3F

VCC c1

0.1uF

c2

0.1uF

c3

0.1uF

c4

0.1uF

VCC

GOE

D5B

D5A

D5F

D5G

D6B

D6A

D6F

D6G

D7B

D7A

D7F

D7G

GND

VCC

GCLK1

D4G

D4F

D4A

D4B

D3G

D3F

D3A

D3B

TCK

D2G

D2F

D2A

D2B

GND

JPRIGHT

11

13

15

17

19

21

1

7

9

3

5

23

25

27

29

31

33

35

37

39

HEADER 20X2

12

14

16

18

20

22

2

8

10

4

6

24

26

28

30

32

34

36

38

40

JPLEFT

33

35

37

39

19

21

23

25

27

29

31

1

3

5

7

9

11

13

15

17

HEADER 20X2

34

36

38

40

20

22

24

26

28

30

32

2

4

6

8

10

12

14

16

18

VCC

VCC

GND

GCLR

D5C

D5D

D5E

TDI

D6C

D6D

D6E

TMS

D7C

D7D

D7E

GND

GCLK2

D4D

D4E

D4C

TDO

D3E

D3D

D3C

D2E

D2D

D2C

D5G

VCC

TDI

D5E

D6B

D6C

GND

D6A

D6D

TMS

D6F

VCC

D6E

D6G

D7B

D7A

GND

P10

P13

P14

P15

P17

P18

P20

P22

P23

P24

P25

I/O

VCC

TDI

I/O

I/O

I/O

GND

I/O

I/O

TMS

I/O

VCC

I/O

I/O

I/O

I/O

GND

14

15

16

17

18

19

20

10

11

12

13

21

22

23

24

25

26

ATMEL PLCC68

U1

56

55

54

53

52

51

50

49

48

47

46

45

44

60

59

58

57

I/O

I/O

GND

TDO

I/O

I/O

I/O

VCC

I/O

I/O

TCK

I/O

GND

I/O

I/O

I/O

I/O

P60

P59

P56

P55

P54

P52

P51

P49

P47

P46

P45

P44

D4F

D4E

GND

TDO

D4A

D4C

D4B

VCC

D3G

D3F

TCK

D3E

GND

D3A

D3D

D3B

D3C

VCC c1

0.1uF

c2

0.1uF

c3

0.1uF

c4

0.1uF

PIN12

VCC

TDI

PIN15

PIN16

PIN17

PIN18

GND

PIN20

PIN21

PIN22

TMS

PIN24

PIN25

VCC

PIN27

PIN28

PIN29

PIN30

PIN31

GND

12

13

14

15

16

17

18

19

20

21

22

23

24

29

30

31

32

25

26

27

28

I/O

VCC_IO

I/O / TDI

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O / TMS

I/O

I/O

VCC_IO

I/O

I/O

I/O

I/O

I/O

GND

ATMEL

ATF1508AS-15JC84

U1

I/O

I/O

GND

I/O / TDO

I/O

I/O

I/O

I/O

VCC_IO

I/O

I/O

I/O

I/O / TCK

I/O

I/O

GND

I/O

I/O

I/O

I/O

I/O

69

68

67

66

65

64

74

73

72

71

70

63

62

61

60

59

58

57

56

55

54

MARK

SMALLATMEL

PIN74

PIN73

GND

TDO

PIN70

PIN69

PIN68

PIN67

VCC

PIN65

PIN64

PIN63

TCK

PIN61

PIN60

GND

PIN58

PIN57

PIN56

PIN55

PIN54

VCC c1

0.1uF

c2

0.1uF

c3

0.1uF

c4

0.1uF

PIN83

PIN81

PIN79

PIN76

PIN74

PIN73

PIN69

PIN67

PIN64

PIN63

PIN60

PIN57

PIN55

PIN54

PIN51

PIN49

PIN46

PIN21

PIN22

PIN25

PIN28

PIN30

PIN31

PIN34

PIN36

PIN39

PIN84

PIN4

PIN6

PIN9

PIN11

PIN44

PIN12

PIN16

PIN18

JL1

JL3

JL5

JL7

JL9

JL11

JL12

JL14

JL16

JL18

JL19

JL21

JL23

JL25

JL27

JL29

JL31

JL33

JR1

JR3

JR5

JR7

JR9

JR11

JR12

JR14

JR15

JR18

JR20

JR23

JR25

JR27

JR29

JR31

JR33

VCC

GOE

D5B

D5A

D5F

D5G

DOT6

D6B

D6A

D6F

D6G

D7B

D7A

D7F

D7G

D8B

D8A

D8F

D8G

GND

D2F

D2A

D2B

D1G

D1F

D1A

D1B

GND

VCC

GCLK1

D4G

D4F

D4A

D4B

D3G

D3F

D3A

D3B

TCK

D2G

JPRIGHT

19

21

23

25

11

13

15

17

1

3

5

7

9

27

29

31

33

35

37

39

HEADER 20X2

20

22

24

26

12

14

16

18

2

4

6

8

10

28

30

32

34

36

38

40

JPLEFT

15

17

19

21

23

25

1

7

9

3

5

11

13

27

29

31

33

35

37

39

HEADER 20X2

16

18

20

22

24

26

2

4

6

8

10

12

14

28

30

32

34

36

38

40

GND

GCLR

DOT5

D5C

D5D

D5E

TDI

D6C

D6D

D6E

TMS

DOT7

D7C

D7D

D7E

DOT8

D8C

D8D

D8E

VCC

D2E

D2D

D2C

D1E

D1D

D1C

VCC

GND

GCLK2

D4D

D4E

D4C

TDO

D3E

D3D

D3C

JR2

JR4

JR6

JR8

JR10

JR13

JR16

JR17

JR19

JR21

JR22

JR24

JR26

JR28

JR30

JR32

JR34

PIN2

PIN77

PIN80

PIN75

PIN70

PIN68

PIN65

PIN61

PIN58

PIN56

PIN52

PIN50

PIN48

JL2

JL4

JL6

JL8

JL10

JL13

JL15

JL17

JL20

JL22

JL24

JL26

JL28

JL30

JL32

JL34

PIN1

PIN45

PIN5

PIN8

PIN10

PIN15

PIN17

PIN20

PIN41

PIN24

PIN27

PIN29

PIN40

PIN33

PIN35

PIN37

P1

P2

P3

P4

P14

P15

P16

P18

P19

P7

P8

P9

P10

P11

P12

P21

P22

P23

P24

P25

P26

P27

P29

P30

D5E

D5G

VCC

TDI

DOT6

D6G

D7B

VCC

D7C

D7A

D7D

DOT7

D7F

D6C

D6B

D6D

GND

D6A

D6E

D6F

TMS

D7E

GND

DOT8

24

25

26

27

28

29

30

20

21

22

23

16

17

18

19

12

13

14

15

8

9

10

11

3

4

1

2

5

6

7

I/O

I/O

GND

I/O

I/O

I/O

TMS

I/O

I/On

I/On

I/O

I/O

VCCIO

TDI

I/On

I/O

I/On

I/O

I/O

VCCIO

I/O

I/O

I/O

I/On

I/O

I/On

I/O

GND

I/On

I/On

ATMEL PQFP100

U1

75

74

73

72

71

70

69

68

67

66

80

79

78

77

76

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

I/On

I/On

I/O

I/O

GND

TDO

I/On

I/O

I/On

I/O

I/O

I/O

VCCIO

I/O

I/O

I/On

I/O

I/On

I/O

VCCIO

I/On

I/On

I/O

I/O

TCK

I/O

I/O

GND

I/O

I/O

P80

P79

P78

P77

P67

P66

P65

P63

P62

P74

P73

P72

P71

P70

P69

P60

P59

P58

P57

P56

P55

P54

P52

P51

D4B

DOT4

GND

TDO

D3G

D3F

D3E

D3A

VCC

D3D

D3B

D3C

TCK

DOT3

D2G

GND

D2E

D2F

D2D

D2A

D2B

VCC

DOT2

DOT1

VCC

D6A

D6F

D6G

D7B

D7A

D7F

D7G

D8B

D8A

D8F

D8G

GND

VCC

GOE

D5B

D5A

D5F

D5G

DOT6

D6B

D3G

D3F

D3A

D3B

TCK

D2G

D2F

D2A

D2B

D1G

VCC

GCLK1

D4G

D4F

D4A

D4B

D1F

D1A

D1B

GND

JPRIGHT

17

19

21

23

25

27

29

31

33

35

37

9

11

13

15

5

7

1

3

39

HEADER 20X2

18

20

22

24

26

28

30

32

34

36

38

10

12

14

16

6

8

2

4

40

JPLEFT

23

25

27

29

15

17

19

21

31

33

35

37

39

5

7

1

3

9

11

13

HEADER 20X2

24

26

28

30

16

18

20

22

32

34

36

38

40

10

12

14

6

8

2

4

D6D

D6E

TMS

DOT7

D7C

D7D

D7E

DOT8

D8C

D8D

D8E

VCC

GND

GCLR

DOT5

D5C

D5D

D5E

TDI

D6C

D3D

D3C

DOT3

D2E

D2D

D2C

DOT2

D1E

D1D

D1C

DOT1

VCC

GND

GCLK2

D4D

D4E

D4C

DOT4

TDO

D3E c1

0.1uF

c2

0.1uF

c3

0.1uF

c4

0.1uF

D6G

D7B

D7A

D7F

D7G

D8B

D8A

D8F

D8G

GND

VCC

GOE

D5B

D5A

D5F

D5G

DOT6

D6B

D6A

D6F

D2G

D2F

D2A

D2B

D1G

D1F

D1A

D1B

GND

VCC

GCLK1

D4G

D4F

D4A

D4B

D3G

D3F

D3A

D3B

TCK

JPLEFT

29

31

33

35

37

39

19

21

23

25

27

9

11

13

15

17

5

7

1

3

HEADER 20X2

30

32

34

36

38

40

20

22

24

26

28

10

12

14

16

18

6

8

2

4

JPRIGHT

25

27

29

31

33

35

37

39

15

17

19

21

23

5

7

9

1

3

11

13

HEADER 20X2

26

28

30

32

34

36

38

40

16

18

20

22

24

6

8

10

12

14

2

4

DOT3

D2E

D2D

D2C

DOT2

D1E

D1D

D1C

DOT1

VCC

GND

GCLK2

D4D

D4E

D4C

DOT4

TDO

D3E

D3D

D3C

GND

GCLR

DOT5

D5C

D5D

D5E

TDI

D6C

D6D

D6E

TMS

DOT7

D7C

D7D

D7E

DOT8

D8C

D8D

D8E

VCC

VCC

TDI

DOT6

D6C

D6B

D6D

GND

D6A

D6E

D6F

TMS

D6G

D7B

VCC

D7C

D7A

D7D

DOT7

D7F

D7E

P1

P2

P12

P13

P14

P16

P17

P5

P6

P7

P8

P9

P10

P19

P20

P21

P22

P23

P24

P25

19

20

21

22

23

24

25

14

15

16

17

18

9

10

11

12

13

7

8

3

4

5

6

1

2

GND

I/O

I/O

I/O

TMS

I/O

I/O

VCCIO

I/O

I/O

I/On

I/On

VCCIO

TDI

I/On

I/O

I/On

I/O

I/O

I/O

I/O

I/On

I/O

I/On

I/O

VCC c1

0.1uF

c2

0.1uF

c3

0.1uF

c4

0.1uF

ATMEL TQFP100

U1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

I/O

GND

TDO

I/On

I/O

I/On

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

TCK

I/O

I/O

GND

I/O

I/O

I/O

I/On

I/O

I/On

I/O

VCCIO

TQFP100

P75

P65

P64

P63

P61

P60

P72

P71

P70

P69

P68

P67

P58

P57

P56

P55

P54

P53

P52

DOT4

GND

TDO

D3G

DOT3

D2G

GND

D2E

D2F

D2D

DOT2

D2A

D3F

D3E

D3A

VCC

D3D

D3B

D3C

TCK

D1B

VCC

Figure 4-8.

Schematic Diagram of 144-pin TQFP Socket Adapter Board

D8E

D8D

D8G

D8F

D8A

VCC

VCC

GND

GND

VCC

GND

GND

P 3 7

P 3 8

P 3 9

P 4 0

P 4 1

P 4 2

P 4 4

P 4 5

P 6 0

P 6 1

P 6 2

P 6 3

P 6 5

P 6 7

P 6 8

P 6 9

P 7 0

P 7 1

P 7 2

P 5 3

P 5 4

P 5 5

P 5 6

37

38

39

40

41

42

43

44

45

66

67

68

69

62

63

64

65

70

71

72

58

59

60

61

54

55

56

57

50

51

52

53

46

47

48

49

I/O

I/O

I/O

I/O

I/O

I/O

I/On

I/O

I/O

I/O

GND

I/O

I/On

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/On

I/On

I/On

I/On

VCCIO

VCCINT

GND

I/O

I/O

I/O

I/O

GND

VCCINT

GND

I/O

I/O

P77 P78 P81 P82 P93 P94 P97 P98 P101 P102

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

P128

P127

P126

P125

P119

P118

P117

P116

P114

P113

P112

P111

P110

P109

P143

P142

P141

P140

P139

P138

P137

P136

P134

P133

P132

P131

VCCIO

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O

VCCINT

GND

GCLK2

GCLR

GOE

GCLK

GND

VCINT

I/On

I/On

I/On

I/O

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

I/O

I/O

I/O

VCC

D4B

D4A

D4C

D4F

VCC

D4D

D4G

D4E

DOT4

DOT5

D5E

D5B

D5C

GND

D5A

D5D

D5F

D5G

VCC

GND

GCLK2

GCLR

GOE

GCLK1

GND

VCC

Schematic Diagrams

CPLD Development/Programmer Kit User Guide

D1B D1A D2B D2A D4B D4A

DOT5 GCLR

4-9

3300A–PLD–08/02

Schematic Diagrams

Figure 4-9.

Schematic Diagram of 160-pin PQFP Socket Adapter Board

D5A D5D

P11 P10

D8F

GND

D8A

DOT8

D8B

D7E

D7G

D7D

D7F

VCC

GND

VCC

GND

D2C

D2A

DOT2

D2B

D1G

D1E

D1F

VCC

D1D

P48

P49

P50

P51

P52

P53

P54

P56

P57

P58

P59

P41

P43

P62

P63

P64

P65

P67

P68

P69

P70

P71

P72

P73

P78

P80

49

50

51

52

53

54

55

56

57

58

59

60

41

42

43

44

45

46

47

48

61

62

63

68

69

70

71

72

73

64

65

66

67

74

75

76

77

78

79

80

I/O

GND

I/O

NC

NC

NC

NC

I/O

I/O

I/O

I/O

I/O

VCCINT

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

I/O

GND

I/O

NC

NC

NC

NC

I/O

VCCIO

I/O

P90 P91 P102 P103 P106 P107

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O

VCCINT

GCLK2

GCLR

I/O

I/O

I/O

NC

NC

NC

NC

OE1

GCLK1

GND

I/O/GCLK3

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

I/O

I/O

NC

NC

NC

NC

I/O

I/O

I/O

152

151

150

149

148

147

146

145

144

143

142

141

160

159

158

157

156

155

154

153

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

P 1 6 0

P 1 5 9

P 1 5 8

P123

P122

P121

P 1 5 3

P 1 5 2

P 1 5 1

P 1 5 0

P 1 4 9

P 1 4 7

P 1 4 6

P 1 4 5

P 1 4 4

P 1 4 2

P 1 4 1

P 1 4 0

P 1 3 9

P 1 3 7

P 1 3 6

P 1 3 5

P 1 3 4

P 1 3 2

P 1 3 1

P 1 3 0

P 1 2 9

P 1 2 8

D5C

D5B

DOT5

GND

VCC

GCLK2

GCLR

GOE

GCLK1

GND

VCC

D4D

D4G

D4F

D4F D4G

4-10

3300A–PLD–08/02

CPLD Development/Programmer Kit User Guide

Buffer/Line Driver

STROBE

AUTO

D0

INIT

SEL_IN

D7

VCC

D1

1N4148

R26

4.7k

R25

4.7k

R24

4.7k

R23

4.7k

R22

4.7k

R21

4.7k

TDO

8

11

13

2

4

6

15

17

1

19

U1

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1G

2G

74VHC244

20-SOIC

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

VCC

GND

18

16

14

12

9

7

5

3

20

10

GND

VCC

GND

C1

0.1uF

R16 100

R17 100

R18 100

R19 100

R20 100

TCK

TDO

TMS

TDI

10 Pin Header to ISP Board

JP1

1

3

5

7

9

2

4

6

8

10

HEADER 5X2

GND

VCC

GND

R1

330ohm

L1

LED

INI

AF

TCK

AF

TDI

INI

TMS nACK

BUSY

P1

DB25

5

18

6

19

7

20

8

21

9

22

10

23

11

24

12

25

13

1

14

2

15

3

16

4

17

Parallel Port Section

R2 100

R3

R4

100

100

R5

100

R6 100

STROBE

AUTO

D0

ERROR

INIT

SEL_IN

R7 100

R8

R9

100

100

R10 4.7K

R11 4.7K

D7 nACK

VCC

BUSY

GND

VCC

Voltage Detection

D2

R12 10K

1.5V - 1.6V

Vref

1N4148

D3 1N4148

D4 1N4148

4

LM393

8-SOP

GND

ERROR

3V = 0

5V = 1

1.36V at VCC = 3.3

2.06V at VCC = 5.0

R13 4.7K

U2A

8

VCC

R14 3.3K

4

LM393

8-SOP

U2B

8

VCC

R15 30K

GND

Atmel Headquarters

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

TEL (41) 26-426-5555

FAX (41) 26-426-5500

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Operations

Memory

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 2-40-18-18-18

FAX (33) 2-40-18-19-60

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

TEL (33) 4-42-53-60-00

FAX (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

TEL (44) 1355-803-000

FAX (44) 1355-242-743

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex, France

TEL (33) 4-76-58-30-00

FAX (33) 4-76-58-34-80

e-mail

[email protected]

Web Site

http://www.atmel.com

© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.

ATMEL

® is the registered trademark of Atmel; Logic Doubling

, ProChip Designer

™ and Atmel-WinCUPL

™ are the trademarks of Atmel.

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® is the registered trademark of Altera Corporation; ByteBlaster

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® and ByteBlasterMV

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® and Windows NT

® are the registered trademarks of Microsoft Corporation. Verilog

® is a registered trademark of

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Exemplar

™ and Leonardo Spectrum

® is a registered trademark of Mentor Graphics Corporation; are trademarks of Mentor Graphics Corporation. Altium

®

, PeakFPGA

™ and Protel

™ are trademarks and registered trademarks of Altium Limited. Other terms and product names may be the trademarks of others.

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3300A–PLD–08/02 /1M

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