User manual | External Memory Interfaces in Stratix IV Devices

7. External Memory Interfaces in
Stratix IV Devices
February 2011
SIV51007-3.2
SIV51007-3.2
This chapter describes external memory interfaces available with the Stratix ® IV
device family and that family’s silicon capability to support external memory
interfaces. To support the level of system bandwidth achievable with Altera ®
Stratix IV FPGAs, the devices provide an efficient architecture to quickly and easily fit
wide external memory interfaces within their small modular I/O bank structure. The
I/Os are designed to provide high-performance support for existing and emerging
external double data rate (DDR) memory standards, such as DDR3, DDR2, DDR
SDRAM, QDR II+, QDR II SRAM, and RLDRAM II.
Stratix IV I/O elements provide easy-to-use built-in functionality required for a rapid
and robust implementation with features such as dynamic calibrated on-chip
termination (OCT), trace mismatch compensation, read- and write-leveling circuit for
DDR3 SDRAM interfaces, half data rate (HDR) blocks, and 4- to 36-bit programmable
DQ group widths.
The high-performance memory interface solution is backed-up by a self-calibrating
megafunction (ALTMEMPHY), optimized to take advantage of the Stratix IV I/O
structure and the TimeQuest Timing Analyzer, which completes the picture by
providing the total solution for the highest reliable frequency of operation across
process, voltage, and temperature (PVT) variations.
This chapter contains the following sections:
■
“Memory Interfaces Pin Support” on page 7–3
■
“Stratix IV External Memory Interface Features” on page 7–29
f For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to the External Memory Interface Handbook.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Stratix IV Device Handbook Volume 1
February 2011
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7–2
Chapter 7: External Memory Interfaces in Stratix IV Devices
Figure 7–1 shows an overview of the memory interface data path that uses all the
Stratix IV I/O element (IOE) features.
Figure 7–1. External Memory Interface Data Path Overview (Note 1), (2)
Memory
Stratix IV FPGA
Postamble Enable
Postamble Clock
4n
DPRAM
(2)
DLL
DQS Logic
Block
Postamble
Control
Circuit
DQS Enable
Circuit
2n
2n
Alignment &
Synchronization
Registers
Half Data Rate
Input Registers
DQS (Read) (3)
DDR Input
Registers
n
DQ (Read) (3)
Resynchronization Clock
n
2n
4n
Half-Rate
Resynchronization
Clock
Clock Management & Reset
DQ Write Clock
Half-Rate Clock
4
2n
Alignment
Registers
Half Data Rate
Output Registers
2
2
Half Data Rate
Output Registers
Alignment
Registers
DQ (Write) (3)
DDR Output
and Output
Enable
Registers
DQS (Write) (3)
DDR Output
and Output
Enable
Registers
Alignment Clock
DQS Write Clock
Notes to Figure 7–1:
(1) You can bypass each register block.
(2) The blocks used for each memory interface may differ slightly. The shaded blocks are part of the Stratix IV IOE.
(3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
and write operations.
Memory interfaces use Stratix IV device features such as delay-locked loops (DLLs),
dynamic OCT control, read- and write-leveling circuitry, and I/O features such as
OCT, programmable input delay chains, programmable output delay, slew rate
adjustment, and programmable drive strength.
f For more information about I/O features, refer to the I/O Features in Stratix IV Devices
chapter.
The ALTMEMPHY megafunction instantiates a phase-locked loop (PLL) and PLL
reconfiguration logic to adjust the phase shift based on VT variation.
f For more information about the Stratix IV PLL, refer to the Clock Networks and PLLs in
Stratix IV Devices chapter. For more information about the ALTMEMPHY
megafunction, refer to the External Memory PHY Interface (ALTMEMPHY) (nonAFI)
Megafunction User Guide.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–3
Memory Interfaces Pin Support
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ and
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data
mask (DM, BWSn, or NWSn) pins to enable write masking and QVLD pins to indicate
that the read data is ready to be captured. This section describes how Stratix IV
devices support all these different pins.
1
If you have more than one clock pair, you must place them in the same DQ group. For
example, if you have two clock pairs, you must place both of them in the same ×4
DQS group.
f For more information about pin connections, refer to the Stratix IV GX and Stratix IV E
Device Family Pin Connection Guidelines.
f For more information about pin planning and pin connections between a Stratix IV
device and an external memory device, refer to the External Memory Interface
Handbook.
DDR3, DDR2, DDR SDRAM, and RLDRAM II devices use the CK and CK# signals to
capture the address and command signals. Generate these signals to mimic the
write-data strobe using Stratix IV DDR I/O registers (DDIOs) to ensure that the
timing relationships between the CK/CK# and DQS signals (tDQSS, tDSS, and tDSH in
DDR3, DDR2, and DDR SDRAM devices or tCKDK in RLDRAM II devices) are met.
QDR II+ and QDR II SRAM devices use the same clock (K/K#) to capture write data,
address, and command signals.
Memory clock pins in Stratix IV devices are generated using a DDIO register going to
differential output pins (refer to Figure 7–2), marked in the pin table with DIFFOUT,
DIFFIO_TX, or DIFFIO_RX prefixes.
f For more information about which pins to use for memory clock pins, refer to the
External Memory Interface Handbook.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–4
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–2. Memory Clock Generation
FPGA LEs
I/O Elements
VCC
D
Q
1
D
Q
mem_clk (2)
0
mem_clk_n (2)
System Clock (3)
Notes to Figure 7–2:
(1) For pin location requirements,refer to the External Memory Interface Handbook.
(2) The mem_clk[0] and mem_clk_n[0] pins for DDR3, DDR2, and DDR SDRAM interfaces use the I/O input buffer for feedback required by
the ALTMEMPHY megafunction for tracking; therefore, use bidirectional I/O buffers for these pins. For memory interfaces using a differential DQS
input, the input feedback buffer is configured as differential input. For memory interfaces using a single-ended DQS input, the input buffer is
configured as a single-ended input. Using a single-ended input feedback buffer requires that I/O standard’s VREF voltage is provided to that I/O
bank’s VREF pins.
(3) To minimize jitter, regional clock networks are required for memory output clock generation.
Stratix IV devices offer differential input buffers for differential read-data strobe and
clock operations. In addition, Stratix IV devices also provide an independent DQS
logic block for each CQn pin for complementary read-data strobe and clock
operations. In the Stratix IV pin tables, the differential DQS pin pairs are denoted as
DQS and DQSn pins, while the complementary CQ signals are denoted as CQ and
CQn pins. DQSn and CQn pins are marked separately in the pin table. Each CQn pin
connects to a DQS logic block and the shifted CQn signals go to the negative-edge
input registers in the DQ IOE registers.
1
Use differential DQS signaling for DDR2 SDRAM interfaces running at or above
333 MHz.
DQ pins can be bidirectional signals, as in DDR3, DDR2, and DDR SDRAM, and
RLDRAM II common I/O (CIO) interfaces, or unidirectional signals, as in QDR II+,
QDR II SRAM, and RLDRAM II separate I/O (SIO) devices. Connect the
unidirectional read-data signals to Stratix IV DQ pins and the unidirectional
write-data signals to a different DQS/DQ group than the read DQS/DQ group.
Furthermore, the write clocks must be assigned to the DQS/DQSn pins associated to
this write DQS/DQ group. Do not use the CQ/CQn pin-pair for write clocks.
1
Using a DQS/DQ group for the write-data signals minimizes output skew, allows
access to the write-leveling circuitry (for DDR3 SDRAM interfaces), and allows
vertical migration. These pins also have access to deskewing circuitry (using
programmable delay chains) that can compensate for delay mismatch between signals
on the bus.
The DQS and DQ pin locations are fixed in the pin table. Memory interface circuitry is
available in every Stratix IV I/O bank that does not support transceivers. All the
memory interface pins support the I/O standards required to support DDR3, DDR2,
DDR SDRAM, QDR II+, QDR II SRAM, and RLDRAM II devices.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–5
The Stratix IV device family supports DQS and DQ signals with DQ bus modes of ×4,
×8/×9, ×16/×18, or ×32/×36, although not all devices support DQS bus mode
×32/×36. When any of these pins are not used for memory interfacing, you can use
them as user I/Os. In addition, you can use any DQSn or CQn pins not used for
clocking as DQ (data) pins. Table 7–1 lists pin support per DQS/DQ bus mode,
including the DQS/CQ and DQSn/CQn pin pair.
Table 7–1. Stratix IV DQS/DQ Bus Mode Pins
Maximum
Number of
Data Pins
per Group
(2)
DQSn Support
CQn Support
Parity or DM
(Optional)
QVLD
(Optional) (1)
Typical
Number of
Data Pins
per Group
×4
Yes
No
No (6)
No
4
5
×8/×9 (3)
Yes
Yes
Yes
Yes
8 or 9
11
×16/×18 (4)
Yes
Yes
Yes
Yes
16 or 18
23
×32/×36 (5)
Yes
Yes
Yes
Yes
32 or 36
47
×32/×36 (7)
Yes
Yes
No (8)
Yes
32 or 36
39
Mode
Notes to Table 7–1:
(1) The QVLD pin is not used in the ALTMEMPHY megafunction.
(2) This represents the maximum number of DQ pins (including parity, data mask, and QVLD pins) connected to the DQS bus network with
single-ended DQS signaling. When you use differential or complementary DQS signaling, the maximum number of data per group decreases
by one. This number may vary per DQS/DQ group in a particular device. Check the pin table for the exact number per group. For DDR3, DDR2,
and DDR interfaces, the number of pins is further reduced for an interface larger than ×8 due to the need of one DQS pin for each ×8/×9 group
that is used to form the x16/×18 and ×32/×36 groups.
(3) Two ×4 DQS/DQ groups are stitched to make a ×8/×9 group so there are a total of 12 pins in this group.
(4) Four ×4 DQS/DQ groups are stitched to make a ×16/×18 group.
(5) Eight ×4 DQS/DQ groups are stitched to make a ×32/×36 group.
(6) The DM pin can be supported if differential DQS is not used and the group does not have additional signals.
(7) These ×32/×36 DQS/DQ groups are available in EP4SGX290, EP4SGX360, and EP4SGX530 devices in 1152- and 1517-pin FineLine BGA
packages. There are 40 pins in each of these DQS/DQ groups.
(8) There are 40 pins in each of these DQS/DQ groups. The BWSn pins cannot be placed within the same DQS/DQ group as the write data pins
because of insufficient pins available.
Table 7–2 lists the number of DQS/DQ groups available per side in each Stratix IV
device. For a more detailed listing of the number of DQS/DQ groups available per
bank in each Stratix IV device, see Figure 7–3 through Figure 7–19. These figures
represent the die-top view of the Stratix IV device.
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 1 of 3) (Note 1)
Device
Package
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
780-pin
FineLine BGA
EP4SGX290
EP4SGX360
780-pin
FineLine BGA
EP4SE230
EP4SE360
780-pin
FineLine BGA
February 2011
Altera Corporation
Side
×4 (2)
×8/×9
×16/×18
×32/×36 (3)
Left
14
6
2
0
Top/Bottom
17
8
2
0
Right
0
0
0
0
Left/Right
0
0
0
0
Top/Bottom
18
8
2
0
Left/Right
14
6
2
0
Top/Bottom
17
8
2
0
Refer to:
Figure 7–3
Figure 7–5
Figure 7–4
Stratix IV Device Handbook Volume 1
7–6
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 2 of 3) (Note 1)
Device
Package
Side
×4 (2)
×8/×9
×16/×18
×32/×36 (3)
EP4SGX110
1152-pin
FineLine BGA
(with 16
transceivers)
EP4SGX70
EP4SGX110
1152-pin
FineLine BGA
(with 24
transceivers)
EP4SGX180
EP4SGX230
1152-pin
FineLine BGA
EP4SGX290
EP4SGX360
EP4SGX530
1152-pin
FineLine BGA
EP4SE360
EP4SE530
EP4SE820
Right/Left
7
3
1
0
Top/Bottom
17
8
2
0
Right/Left
14
6
2
0
Top/Bottom
17
8
2
0
Right/Left
13
6
2
0
Top/Bottom
26
12
4
0
Right/Left
13
6
2
0
Top/Bottom
26
12
4
2 (4)
1152-pin
FineLine BGA
All sides
26
12
4
0
Figure 7–10
EP4SGX180
EP4SGX230
1517-pin
FineLine BGA
All sides
26
12
4
0
Figure 7–11
EP4SGX290
EP4SGX360
EP4SGX530
1517-pin
FineLine BGA
Right/Left
26
12
4
0
Top/Bottom
26
12
4
2 (4)
EP4SE530
EP4SE820
1517-pin
FineLine BGA
Right/Left
34
16
6
0
Top/Bottom
38
18
8
4
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G5
Left
12
3
1
0
1517-pin
FineLine BGA
Top/Bottom
26
12
4
0
Right
11
4
1
0
EP4SGX290
EP4SGX360
EP4SGX530
1760-pin
FineLine BGA
Right/Left
26
12
4
0
Top/Bottom
38
18
8
4
EP4SE530
1760-pin
FineLine BGA
Right/Left
34
16
6
0
Top/Bottom
38
18
8
4
EP4SE820
1760-pin
FineLine BGA
Right/Left
40
18
6
0
Top/Bottom
44
22
10
4
EP4SGX290
EP4SGX360
EP4SGX530
1932-pin
FineLine BGA
Right/Left
29
13
4
0
Top/Bottom
38
18
8
4
Stratix IV Device Handbook Volume 1
February 2011
Refer to:
Figure 7–6
Figure 7–7
Figure 7–8
Figure 7–9
Figure 7–12
Figure 7–13
Figure 7–14
Figure 7–15
Figure 7–16
Figure 7–17
Figure 7–18
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–7
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 3 of 3) (Note 1)
Device
Package
EP4S100G3
EP4S100G4
EP4S100G5
1932-pin
FineLine BGA
Side
×4 (2)
×8/×9
×16/×18
×32/×36 (3)
Left
8
2
0
0
Top/Bottom
38
18
8
4
Right
7
1
0
0
Refer to:
Figure 7–19
Notes to Table 7–2:
(1) These numbers are preliminary until the devices are available.
(2) Some of the ×4 groups may use RUP and RDN pins. You cannot use these groups if you use the Stratix IV calibrated OCT feature.
(3) To interface with a ×36 QDR II+/QDR II SRAM device in a Stratix IV FPGA that does not support the ×32/×36 DQS/DQ group, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(4) These ×32/×36 DQS/DQ groups have 40 pins instead of 48 pins per group. BWSn pins cannot be placed within the same DQS/DQ group as the
write data pins because of insufficient pins available.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–8
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–3. Number of DQS/DQ Groups per Bank in EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the
780-Pin FineLine BGA Package (Note 1), (2), (3), (4). (5)
DLL0
I/O Bank 8A
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 1C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
EP4SGX70, EP4SGX110, EP4SGX180, and
EP4SGX230 Devices in the
780-Pin FineLine BGA
I/O Bank 2C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 2A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
DLL1
I/O Bank 3A
I/O Bank 3C
I/O Bank 4C
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–3:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM
device, refer to “Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–9
Figure 7–4. Number of DQS/DQ Groups per Bank in EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA
Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 1C
I/O Bank 6C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
EP4SE230 and EP4SE360 Devices in the
780-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 2A
I/O Bank 5A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
DLL1
I/O Bank 3A
I/O Bank 3C
I/O Bank 4C
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–4:
(1) These numbers are preliminary until the devices are available.
(2) EP4SE230 and EP4SE360 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–10
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–5. Number of DQS/DQ Groups per Bank in EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA
Package (Note 1), (2)
DLL0
I/O Bank 8A
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
EP4SGX290 and EP4SGX360 Devices
in the 780-Pin FineLine BGA
DLL1
I/O Bank 3A
I/O Bank 3C
I/O Bank 4C
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–5:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX290 and EP4SGX360 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–11
Figure 7–6. Number of DQS/DQ Groups per Bank in EP4SGX110 Devices with 16 Transceivers in the 1152-Pin FineLine
BGA Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
EP4SGX110 Devices
in the 1152-Pin FineLine BGA
(with 16 Transceivers)
I/O Bank 1C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
DLL1
I/O Bank 6C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 3A
I/O Bank 3C
I/O Bank 4C
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–6:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX110 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining ×16/×18 DQS/DQ
Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–12
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–7. Number of DQS/DQ Groups per Bank in EP4SGX70 and EP4SGX110 Devices with 24 Transceivers in the
1152-Pin FineLine BGA Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A (3)
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A (3)
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 1A (3)
DLL3
I/O Bank 6A (3)
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 1C (4)
26 User I/Os (5)
x4=3
x8/x9=1
x16/x18=0
I/O Bank 6C
26 User I/Os (5)
x4=3
x8/x9=1
x16/x18=0
EP4SGX70 and EP4SGX110 Devices
in the 1152-Pin FineLine BGA
(with 24 Transceivers)
I/O Bank 6A (3)
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 1C (4)
26 User I/Os (5)
x4=3
x8/x9=1
x16/x18=0
I/O Bank 6C
26 User I/Os (5)
x4=3
x8/x9=1
x16/x18=0
I/O Bank 3A (3)
DLL1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 3C
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
I/O Bank 4C
I/O Bank 4A (3)
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–7:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX70 and EP4SGX110 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–13
Figure 7–8. Number of DQS/DQ Groups per Bank in EP4SGX180 and EP4SGX230 Devices in the 1152-Pin FineLine BGA
Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
EP4SGX180 and EP4SGX230 Devices
in the 1152-Pin FineLine BGA
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–8:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX180 and EP4SGX230 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–14
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–9. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1152-Pin
FineLine BGA Package (Note 1), (3), (4), (5)
DLL0
I/O Bank 8A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1152-Pin FineLine BGA
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL1
I/O Bank 3A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
DLL2
Notes to Figure 7–9:
(1) These numbers are preliminary until the devices are available.
(2) These ×32/×36 DQS/DQ groups have 40 pins instead of 48 pins per group.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–15
Figure 7–10. Number of DQS/DQ Groups per Bank in EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin
FineLine BGA Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
EP4SE360, EP4SE530
and EP4SE820 Devices
in the 1152-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 2A
I/O Bank 5A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
DLL1
I/O Bank 3A
I/O Bank 3B
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–10:
(1) These numbers are preliminary until the devices are available.
(2) EP4SE360, EP4SE530, and EP4SE820 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to
“Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–16
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–11. Number of DQS/DQ Groups per Bank in EP4SGX180 and EP4SGX230 Devices in the 1517-Pin FineLine BGA
Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
EP4SGX180 and EP4SGX230 Devices
in the 1517-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 2A
I/O Bank 5A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
DLL1
I/O Bank 3A
I/O Bank 3B
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–11:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX180 and EP4SGX230 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–17
Figure 7–12. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1517-Pin
FineLine BGA Package (Note 1), (3), (4), (5)
DLL0
I/O Bank 8A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1517-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 2A
I/O Bank 5A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
DLL1
I/O Bank 3A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
I/O Bank 3B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4C
I/O Bank 4B
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
DLL2
Notes to Figure 7–12:
(1) These numbers are preliminary until the devices are available.
(2) These ×32/×36 DQS/DQ groups have 40 pins instead of 48 pins per group.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–18
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–13. Number of DQS/DQ Groups per Bank in EP4SE530 and EP4SE820 Devices in the 1517-pin FineLine BGA
Package (Note 1), (2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 1A
DLL3
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 6B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 1C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
EP4SE530 and EP4SE820 Devices
in the 1517-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2B
I/O Bank 5B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 2A
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–13:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–19
Figure 7–14. Number of DQS/DQ Groups per Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the
1517-Pin FineLine BGA Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 8B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 7B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
43 User I/Os
x4=5
x8/x9=1
x16/x18=0
44 User I/Os
x4=5
x8/x9=1
x16/x18=0
I/O Bank 1C
20 User I/Os
x4=0
x8/x9=0
x16/x18=0
I/O Bank 6C
21 User I/Os
x4=0
x8/x9=0
x16/x18=0
EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices
in the 1517-Pin FineLine BGA
I/O Bank 2C
21 User I/Os
x4=1
x8/x9=0
x16/x18=0
I/O Bank 5C
21 User I/Os
x4=0
x8/x9=0
x16/x18=0
I/O Bank 2A
I/O Bank 5A
46 User I/Os
x4=6
x8/x9=2
x16/x18=1
46 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–14:
(1) These numbers are preliminary until the devices are available.
(2) EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 devices do not support × 32/× 36 mode. To interface with a × 36 QDR II+/QDR II SRAM
device, refer to “Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a × 4 DQS/DQ group with any of its pin members
used for configuration purposes. Make sure that the DQS/DQ groups that you have chosen are not used for configuration as you may lose up to
four × 4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–20
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–15. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin
FineLine BGA Package (Note 1), (2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL3
I/O Bank 1A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x6/x18=1
x32/x36=0
I/O Bank 1C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1760-Pin FineLine BGA
I/O Bank 2C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 3B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 4C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 4B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–15:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–21
Figure 7–16. Number of DQS/DQ Groups per Bank in EP4SE530 Devices in the 1760-Pin FineLine BGA Package (Note 1),
(2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL3
I/O Bank 1A
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 6B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 1C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
EP4SE530 Devices
in the 1760-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2B
I/O Bank 5B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 2A
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–16:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–22
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–17. Number of DQS/DQ Groups per Bank in EP4SE820 Devices in the 1760-pin FineLine BGA Package (Note 1),
(2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
48 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 7C
48 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL3
I/O Bank 1A
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6B
36 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1B
36 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1C
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
EP4SE820 Devices
in the 1760-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2B
I/O Bank 5B
36 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
36 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2A
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
48 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–17:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–23
Figure 7–18. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin
FineLine BGA Package (Note 1), (2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 1A
DLL3
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1932-Pin FineLine BGA
I/O Bank 2B
I/O Bank 5B
20 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
20 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 2A
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–18:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–24
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–19. Number of DQS/DQ Groups per Bank in EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin
FineLine BGA Package (Note 1), (2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL3
I/O Bank 6A
I/O Bank 1A
38 User I/Os
x4=3
x8/x9=0
x16/x18=0
x32/x36=0
40 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 6C
20 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 1C
19 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 2C
I/O Bank 5C
19 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
17 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
EP4S100G3, EP4S100G4, and EP4S100G5 Devices
in the 1932-Pin FineLine BGA
I/O Bank 2B
I/O Bank 5B
13 User I/Os
x4=1
x8/x9=0
x16/x18=0
x32/x36=0
12 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 2A
I/O Bank 5A
39 User I/Os
x4=4
x8/x9=1
x16/x18=0
x32/x36=0
40 User I/Os
x4=4
x8/x9=1
x16/x18=0
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–19:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
The DQS and DQSn pins are listed in the Stratix IV pin tables as DQSXY and DQSnXY,
respectively, where X indicates the DQS/DQ grouping number and Y indicates
whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the
device. The DQS/DQ pin numbering is based on ×4 mode.
The corresponding DQ pins are marked as DQXY, where X indicates which DQS group
the pins belong to and Y indicates whether the group is located on the top (T), bottom
(B), left (L), or right (R) side of the device. For example, DQS1L indicates a DQS pin
located on the left side of the device. The DQ pins belonging to that group are shown
as DQ1L in the pin table. For more information, refer to Figure 7–20.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
1
7–25
The parity, DM, BWSn, NWSn, ECC, and QVLD pins are shown as DQ pins in the pin
table.
The numbering scheme starts from the top-left corner of the device going
counter-clockwise in a die-top view. Figure 7–20 shows how the DQS/DQ groups are
numbered in a die-top view of the device. The top and bottom sides of the device can
contain up to 38 ×4 DQS/DQ groups. The left and right sides of the device can contain
up to 34 ×4 DQS/DQ groups.
Figure 7–20. DQS Pins in Stratix IV I/O Banks
DQS20T
DQS38T
DQS19T
DQS1T
DLL0
DLL3
PLL_T1
PLL_T2
PLL_R1
PLL_L1
8A
8B
8C
7C
7B
7A
DQS1L
DQS34R
1A
6A
1B
6B
1C
6C
DQS17L
DQS18R
PLL_R2
PLL_L2
Stratix IV Device
PLL_R3
PLL_L3
DQS18L
DQS17R
2C
5C
2B
5B
2A
5A
DQS34L
DQS1R
3A
3B
3C
4C
4B
4A
PLL_R4
PLL_L4
PLL_B1
PLL_B2
DLL2
DLL1
DQS1B
February 2011
Altera Corporation
DQS19B
DQS20B
DQS38B
Stratix IV Device Handbook Volume 1
7–26
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Using the RUP and RDN Pins in a DQS/DQ Group Used for Memory Interfaces
You can use the DQS/DQSn pins in some of the ×4 groups as R UP and R DN pins (listed
in the pin table). You cannot use a ×4 DQS/DQ group for memory interfaces if any of
its pin members are used as RUP and RDN pins for OCT calibration. You may be able to
use the ×8/×9 group that includes this ×4 DQS/DQ group, if either of the following
applies:
■
You are not using DM pins with your differential DQS pins
■
You are not using complementary or differential DQS pins
You can use the ×8/×9 group because a DQS/DQ ×8/×9 group actually comprises 12
pins, as the groups are formed by stitching two DQS/DQ groups in ×4 mode with six
pins each (refer to Table 7–1 on page 7–5). A typical ×8 memory interface consists of
one DQS, one DM, and eight DQ pins that add up to 10 pins. If you choose your pin
assignment carefully, you can use the two extra pins for RUP and RDN . In a DDR3
SDRAM interface, you must use differential DQS, which means that you only have
one extra pin. In this case, pick different pin locations for the RUP and R DN pins (for
example, in the bank that contains the address and command pins).
You cannot use the RUP and RDN pins shared with DQS/DQ group pins when using
×9 QDR II+/QDR II SRAM devices, as the R UP and R DN pins are dual purpose with
the CQn pins. In this case, pick different pin locations for R UP and RDN pins to avoid
conflict with memory interface pin placement. In this case, you have the choice of
placing the RUP and RDN pins in the data-write group or in the same bank as the
address and command pins.
There is no restriction on using ×16/×18 or ×32/×36 DQS/DQ groups that include the
×4 groups whose pins are being used as RUP and RDN pins, because there are enough
extra pins that can be used as DQS pins.
1
For ×8, ×16/×18, or ×32/×36 DQS/DQ groups whose members are used for R UP and
RDN , you must assign DQS and DQ pins manually. The Quartus ® II software might
not be able to place DQS and DQ pins without manual pin assignments, resulting in a
“no-fit”.
Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface
This implementation combines ×16/×18 DQS/DQ groups to interface with a ×36
QDR II+/QDR II SRAM device. The ×36 read data bus uses two ×16/×18 groups
while the ×36 write data uses another two ×16/×18 or four ×8/×9 groups. The
CQ/CQn signal traces are split on the board trace to connect to two pairs of CQ/CQn
pins in the FPGA. This is the only connection on the board that you need to change for
this implementation. Other QDR II+/QDR II SRAM interface rules for Stratix IV
devices also apply for this implementation.
1
The ALTMEMPHY megafunction and UniPHY-based external memory interface IPs
do not use the QVLD signal, so you can leave the QVLD signal unconnected as in any
QDR II+/QDR II SRAM interface.
f For more information about the ALTMEMPHY megafunction or UniPHY-based IPs,
refer to the External Memory Interface Handbook.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–27
Rules to Combine Groups
In 780-, 1152-, and some 1517-pin package devices, there is at most one ×16/×18 group
per I/O sub-bank. You can combine two ×16/×18 groups from a single side of the
device for a ×36 interface.
For devices that do not have four ×16/×18 groups in a single side of the device to
form two ×36 groups for read and write data, you can form one ×36 group on one side
of the device and another ×36 group on the other side of the device.
For vertical migration with the ×36 emulation implementation, check if migration is
possible by enabling device migration in the Quartus II project. The Quartus II
software supports the use of four ×8/×9 DQ groups for write data pins and migration
of these groups across device density. Table 7–3 lists the possible combinations to use
two ×16/×18 DQS/DQ groups to form a ×32/×36 group on Stratix IV devices lacking
a native ×32/×36 DQS/DQ group.
Table 7–3. Possible Group Combinations in Stratix IV Devices (Part 1 of 2)
Package
780-Pin
FineLine BGA
1152-Pin
FineLine BGA
February 2011
Altera Corporation
Device Density
■
EP4SGX70
■
EP4SGX110
■
EP4SGX180
■
EP4SGX230
■
EP4SGX290
■
EP4SGX360
■
EP4SE230
■
EP4SE360
■
EP4SGX70
■
EP4SGX110
■
EP4SGX180
■
EP4SGX230
■
EP4SGX290 (2)
■
EP4SGX360 (2)
■
EP4SGX530 (2)
■
EP4SE360
■
EP4SE530
■
EP4SE820
I/O Sub-Bank Combinations
3A and 4A, 7A and 8A (bottom and top I/O banks) (1)
1A and 2A, 5A and 6A (left and right I/O banks)
3A and 4A, 7A and 8A (bottom and top I/O banks) (1)
3A and 4A, 7A and 8A (bottom and top I/O banks) (1)
1A and 1C, 6A and 6C (left and right I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
Stratix IV Device Handbook Volume 1
7–28
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Table 7–3. Possible Group Combinations in Stratix IV Devices (Part 2 of 2)
Package
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
1932-Pin
FineLine BGA
Device Density
■
EP4SGX180
■
EP4SGX230
■
EP4SGX290 (2)
■
EP4SGX360 (2)
■
EP4SGX530 (2)
■
EP4SE530 (2)
■
EP4SE820 (2)
■
EP4S40G2
■
EP4S40G5
■
EP4S100G2
■
EP4S100G5
■
EP4SGX290
■
EP4SGX360
■
EP4SGX530
■
EP4SE530 (2)
■
EP4SE820 (2)
■
EP4SGX290 (2)
■
EP4SGX360 (2)
■
EP4SGX530 (2)
I/O Sub-Bank Combinations
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1B, 2A and 2B or 1B and 1C, 2B and 2C (left I/O
banks) (3)
5A and 5B, 6A and 6B or 5B and 5C, 6B and 6C (right I/O
banks) (3)
3A and 3B, 4A and 4B (bottom I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1B, 2A and 2B or 1B and 1C, 2B and 2C (left I/O
banks) (3)
5A and 5B, 6A and 6B or 5B and 5C, 6B and 6C (right I/O
banks) (3)
1A and 1C, 2A and 2C (left I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
Notes to Table 7–3:
(1) Each side of the device in these packages has four remaining ×8/×9 groups. You can combine them for the write
side (only) if you want to keep the ×36 QDR II+/QDR II SRAM interface on one side of the device. You must change
the Memory Interface Data Group default assignment from the default 18 to 9 in this case.
(2) This device supports ×36 DQS/DQ groups on the top and bottom I/O banks natively.
(3) Although it is possible to combine the ×16/×18 DQS/DQ groups from I/O banks 1A and 1C, 2A and 2C, 5A and 5C,
and 6A and 6C, Altera does not recommend this due to the size of the package. Similarly, crossing a bank number
(for example, combining groups from I/O banks 6C and 5C) is not supported in this package.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–29
Stratix IV External Memory Interface Features
Stratix IV devices are rich with features that allow robust high-performance external
memory interfacing. The ALTMEMPHY megafunction allows you to use these
external memory interface features and helps set up the physical interface (PHY) best
suited for your system. This section describes each Stratix IV device feature that is
used in external memory interfaces from the DQS phase-shift circuitry, DQS logic
block, leveling multiplexers, and dynamic OCT control block.
1
The ALTMEMPHY megafunction and the Altera memory controller MegaCore®
functions can run at half the frequency of the I/O interface of the memory devices to
allow better timing management in high-speed memory interfaces. Stratix IV devices
have built-in registers in the IOE to convert data from full-rate (the I/O frequency) to
half-rate (the controller frequency) and vice versa. You can bypass these registers if
your memory controller is not running at half the rate of the I/O frequency. When
using the Altera memory controller MegaCore functions, the ALTMEMPHY
megafunction is instantiated for you.
f For more information about the ALTMEMPHY megafunction, refer to the External
Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide.
DQS Phase-Shift Circuitry
Stratix IV phase-shift circuitry provides phase shift to the DQS/CQ and CQn pins on
read transactions when the DQS/CQ and CQn pins are acting as input clocks or
strobes to the FPGA. The DQS phase-shift circuitry consists of DLLs that are shared
between multiple DQS pins and the phase-offset module to further fine-tune the DQS
phase shift for different sides of the device.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–30
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–21 shows how the DQS phase-shift circuitry is connected to the DQS/CQ
and CQn pins in the device where memory interfaces are supported on all sides of the
Stratix IV device.
Figure 7–21. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry (Note 1), (2)
DQS/CQ
Pin
CQn
Pin
DLL
Reference
Clock
DQS/CQ
Pin
CQn
Pin
DLL
Reference
Clock
DQS Logic
Blocks
DQS
Phase-Shift
Circuitry
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
DQS
Phase-Shift
Circuitry
DQS Logic
Blocks
DQS/CQ
Pin
CQn
Pin
DQS/CQ
Pin
CQn
Pin
Δt
to
IOE
Δt
to
IOE
Δt
to
IOE
Δt
to
IOE
DQS
Phase-Shift
Circuitry
to IOE
to IOE
to IOE
to IOE
Δt
Δt
Δt
Δt
to
IOE
Δt
CQn
Pin
to
IOE
Δt
DQS/CQ
Pin
to
IOE
Δt
CQn
Pin
to
IOE
Δt
DQS/CQ
Pin
DQS
Phase-Shift
Circuitry
DLL
Reference
Clock
DLL
Reference
Clock
CQn
Pin
DQS/CQ
Pin
CQn
Pin
DQS/CQ
Pin
Notes to Figure 7–21:
(1) For possible reference input clock pins for each DLL, refer to “DLL” on page 7–31.
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
DQS phase-shift circuitry is connected to the DQS logic blocks that control each
DQS/CQ or CQn pin. The DQS logic blocks allow the DQS delay settings to be
updated concurrently at every DQS/CQ or CQn pin.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–31
DLL
DQS phase-shift circuitry uses a DLL to dynamically control the clock delay needed
by the DQS/CQ and CQn pin. The DLL, in turn, uses a frequency reference to
dynamically generate control signals for the delay chains in each of the DQS/CQ and
CQn pins, allowing it to compensate for PVT variations. The DQS delay settings are
Gray-coded to reduce jitter when the DLL updates the settings. The phase-shift
circuitry needs 1,280 clock cycles to lock and calculate the correct input clock period
when the DLL is in low jitter mode. Otherwise, only 256 clock cycles are needed. Do
not send data during these clock cycles because there is no guarantee that it will be
captured properly. As the settings from the DLL may not be stable until this lock
period has elapsed, be aware that anything using these settings (including the
leveling delay system) may be unstable during this period.
1
You can still use the DQS phase-shift circuitry for any memory interfaces that are less
than 100 MHz. However, the DQS signal may not shift over 2.5 ns. Even if the DQS
signal is not shifted exactly to the middle of the DQ valid window, the I/O element
should still be able to capture the data in low-frequency applications in which a large
amount of timing margin is available.
There are a maximum of four DLLs in a Stratix IV device, located in each corner of the
device. These four DLLs support a maximum of four unique frequencies, with each
DLL running at one frequency. Each DLL can have two outputs with different phase
offsets, which allows one Stratix IV device to have eight different DLL phase shift
settings.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–32
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–22 shows the DLL and I/O bank locations in Stratix IV devices from a
die-top view if all sides of the device support external memory interfaces.
Figure 7–22. Stratix IV DLL and I/O Bank Locations (Die-Top View)
PLL_L1
8A
8B
8C
PLL_T1
PLL_T2
7C
7B
PLL_R1
7A
6
6
DLL0
DLL3
6
6
1A
6A
1B
6B
1C
6C
PLL_R2
PLL_L2
Stratix IV FPGA
PLL_L3
PLL_R3
2C
5C
2B
5B
5A
2A
6
6
DLL1
6
DLL2
6
PLL_L4
3A
3B
3C
PLL_B1
PLL_B2
4C
4B
4A
PLL_R4
The DLL can access the two adjacent sides from its location within the device. For
example, DLL0 on the top left of the device can access the top side (I/O banks 7A, 7B,
7C, 8A, 8B, and 8C) and the left side of the device (I/O banks 1A, 1B, 1C, 2A, 2B, and
2C). This means that each I/O bank is accessible by two DLLs, giving more flexibility
to create multiple frequencies and multiple-type interfaces. You can have two
different interfaces with the same frequency on the two sides adjacent to a DLL, where
the DLL controls the DQS delay settings for both interfaces.
Each bank can use settings from either or both DLLs the bank is adjacent to. For
example, DQS1L can get its phase-shift settings from DLL0, while DQS2L can get its
phase-shift settings from DLL1. Table 7–4 lists the DLL location and supported I/O
banks for Stratix IV devices.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
1
7–33
You can only have one memory interface in each I/O sub-bank (such as I/O
sub-banks 1A, 1B, and 1C) when you use leveling delay chains. This is because there
is only one leveling delay chain per I/O sub-bank.
Table 7–4. DLL Location and Supported I/O Banks
DLL
Location
Accessible I/O Banks (1)
DLL0
Top-left corner
1A, 1B, 1C, 2A, 2B, 2C, 7A, 7B, 7C, 8A, 8B, 8C
DLL1
Bottom-left corner
1A, 1B, 1C, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C
DLL2
Bottom-right corner
3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C
DLL3
Top-right corner
5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C
Note to Table 7–4:
(1) The DLL can access these I/O banks if they are available for memory interfacing.
The reference clock for each DLL may come from PLL output clocks or any of the two
dedicated clock input pins located in either side of the DLL. Table 7–5 through
Table 7–17 lists the available DLL reference clock input resources for the Stratix IV
device family.
1
When you have a dedicated PLL that only generates the DLL input reference clock, set
the PLL mode to No Compensation to achieve better performance or the Quartus II
software changes it automatically. Because the PLL does not use any other outputs, it
does not need to compensate for any clock paths.
Table 7–5. DLL Reference Clock Input for EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin
FineLine BGA Package
DLL
DLL0
DLL1
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
PLL_T1
PLL_L2
—
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
PLL_B1
—
—
CLK7P
CLK3P
—
PLL_B1
—
—
—
PLL_T1
—
—
CLK4P
DLL2
CLK5P
CLK6P
CLK7P
CLK12P
DLL3
CLK13P
CLK14P
CLK15P
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–34
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–6. DLL Reference Clock Input for EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
PLL_L2
—
PLL_B1
PLL_R2
—
PLL_T1
PLL_R2
—
Table 7–7. DLL Reference Clock Input for EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA Package
DLL
CLKIN (Top/Bottom)
CLKIN
(Left/Right)
PLL (Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
—
PLL_T1
—
—
—
PLL_B1
—
—
—
PLL_B2
—
—
—
PLL_T2
—
—
CLK12P
DLL0
CLK13P
CLK14P
CLK15P
CLK4P
DLL1
CLK5P
CLK6P
CLK7P
CLK4P
DLL2
CLK5P
CLK6P
CLK7P
CLK12P
DLL3
CLK13P
CLK14P
CLK15P
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–35
Table 7–8. DLL Reference Clock Input for EP4SGX70 and EP4SGX110 Devices in the 1152-Pin FineLine BGA Package
(with 24 Transceivers)
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
CLK12P
CLK13P
CLK14P
CLK15P
CLK0P
CLK1P
CLK2P
CLK3P
PLL_T1
PLL_L2
—
DLL1
CLK4P
CLK5P
CLK6P
CLK7P
CLK0P
CLK1P
CLK2P
CLK3P
PLL_B1
PLL_L2
—
DLL2
CLK4P
CLK5P
CLK6P
CLK7P
CLK8P
CLK9P
CLK10P
CLK11P
PLL_B1
PLL_R2
—
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK8P
CLK9P
CLK10P
CLK11P
PLL_T1
PLL_R2
—
DLL
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–36
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–9. DLL Reference Clock Input for EP4SGX110 Devices in the 1152-Pin FineLine BGA Package (with 16
Transceivers)
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
—
—
PLL_B1
—
—
PLL_T1
PLL_R2
—
CLK12P
DLL0
CLK13P
CLK0P
CLK14P
CLK1P
CLK15P
CLK4P
DLL1
CLK5P
CLK0P
CLK6P
CLK1P
CLK7P
CLK4P
DLL2
CLK5P
CLK10P
CLK6P
CLK11P
CLK7P
CLK12P
DLL3
CLK13P
CLK10P
CLK14P
CLK11P
CLK15P
Table 7–10. DLL Reference Clock Input for EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1152-Pin FineLine BGA Package
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
—
—
PLL_B2
—
—
PLL_T2
PLL_R2
—
CLK12P
DLL0
CLK13P
CLK0P
CLK14P
CLK1P
CLK15P
CLK4P
DLL1
CLK5P
CLK0P
CLK6P
CLK1P
CLK7P
CLK4P
DLL2
CLK5P
CLK10P
CLK6P
CLK11P
CLK7P
CLK12P
DLL3
CLK13P
CLK10P
CLK14P
CLK11P
CLK15P
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–37
Table 7–11. DLL Reference Clock Input for EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin FineLine BGA
Packages
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
PLL_L3
—
PLL_B2
PLL_R3
—
PLL_T2
PLL_R2
—
Table 7–12. DLL Reference Clock Input for EP4SE530 and EP4SE820 Devices in the 1517- and 1760-Pin FineLine BGA
Packages
DLL
DLL0
DLL1
DLL2
DLL3
February 2011
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
Altera Corporation
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
PLL_L1
PLL_B1
PLL_L3
PLL_L4
PLL_B2
PLL_R3
PLL_R4
PLL_T2
PLL_R2
PLL_R1
Stratix IV Device Handbook Volume 1
7–38
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–13. DLL Reference Clock Input for EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1517-Pin FineLine BGA Package
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
Stratix IV Device Handbook Volume 1
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
PLL_L3
—
PLL_B2
PLL_R3
—
PLL_T2
PLL_R2
—
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–39
Table 7–14. DLL Reference Clock Input for EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin
FineLine BGA Package
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
CLK12P
CLK13P
CLK14P
CLK15P
CLK1P
CLK3P
PLL_T1
PLL_L2
—
DLL1
CLK4P
CLK5P
CLK6P
CLK7P
CLK1P
CLK3P
PLL_B1
PLL_L3
—
DLL2
CLK4P
CLK5P
CLK6P
CLK7P
CLK8P
CLK10P
PLL_B2
PLL_R3
—
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK8P
CLK10P
PLL_T2
PLL_R2
—
DLL
Table 7–15. DLL Reference Clock Input for EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin FineLine
BGA Package
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
CLK12P
CLK13P
CLK14P
CLK15P
CLK0P
CLK1P
CLK2P
CLK3P
PLL_T1
PLL_L2
—
DLL1
CLK4P
CLK5P
CLK6P
CLK7P
CLK0P
CLK1P
CLK2P
CLK3P
PLL_B1
PLL_L3
—
DLL2
CLK4P
CLK5P
CLK6P
CLK7P
CLK8P
CLK9P
CLK10P
CLK11P
PLL_B2
PLL_R3
—
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK8P
CLK9P
CLK10P
CLK11P
PLL_T2
PLL_R2
—
DLL
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–40
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–16. DLL Reference Clock Input for EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine
BGA Package
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
PLL_L1
PLL_B1
PLL_L3
PLL_L4
PLL_B2
PLL_R3
PLL_R4
PLL_T2
PLL_R2
PLL_R1
Table 7–17. DLL Reference Clock Input for EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin FineLine
BGA Package
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
CLK12P
CLK13P
CLK14P
CLK15P
—
PLL_T1
PLL_L2
PLL_L1
DLL1
CLK4P
CLK5P
CLK6P
CLK7P
—
PLL_B1
PLL_L3
PLL_L4
DLL2
CLK4P
CLK5P
CLK6P
CLK7P
CLK9P
CLK11P
PLL_B2
PLL_R3
PLL_R4
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK9P
CLK11P
PLL_T2
PLL_R2
PLL_R1
DLL
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–41
Figure 7–23 shows a simple block diagram of the DLL. The input reference clock goes
into the DLL to a chain of up to 16 delay elements. The phase comparator compares
the signal coming out of the end of the delay chain block to the input reference clock.
The phase comparator then issues the upndn signal to the Gray-code counter. This
signal increments or decrements a six-bit delay setting (DQS delay settings) that
increases or decreases the delay through the delay element chain to bring the input
reference clock and the signals coming out of the delay element chain in phase.
Figure 7–23. Simplified Diagram of the DQS Phase-Shift Circuitry (Note 1)
addnsub
Phase offset settings
from the logic array
( offset [5:0] )
6
offsetdelayctrlin [5:0]
DLL
aload
Input Reference
Clock (2)
offsetdelayctrlout [5:0]
Phase
Comparator
upndninclkena
6
Phase
Offset
Control
B
offsetdelayctrlout [5:0]
offsetdelayctrlin [5:0]
6
delayctrlout [5:0]
6
6
Phase offset
settings to DQS pins
on top or bottom edge (3)
( offsetctrlout [5:0] )
addnsub
Phase offset settings
from the logic array ( offset [5:0] )
Up/Down
Counter
Delay Chains
6
(dll_offset_ctrl_a)
upndnin
clk
Phase
Offset
Control
A
6
(dll_offset_ctrl_b)
Phase offset
settings to DQS pin
on left or right edge (3)
( offsetctrlout [5:0] )
DQS Delay
Settings (4)
dqsupdate
Notes to Figure 7–23:
(1) All features of the DQS phase-shift circuitry are accessible from the ALTMEMPHY megafunction in the Quartus II software.
(2) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer
to Table 7–5 on page 7–33 through Table 7–17 on page 7–40.
(3) Phase offset settings can only go to the DQS logic blocks.
(4) DQS delay settings can go to the logic array, DQS logic block, and leveling circuitry.
1
In the Quartus II assignment, phase offset control block ‘A’ is designated as
DLLOFFSETCTRL_<coordinate x>_<coordinate y>_N1 and phase offset control block
‘B’ is designated as DLLOFFSETCTRL_<coordinate x>_<coordinate y>_N2.
You can reset the DLL from either the logic array or a user I/O pin. Each time the DLL
is reset, you must wait for 1,280 clock cycles for the DLL to lock before you can
capture the data properly.
Depending on the DLL frequency mode, the DLL can shift the incoming DQS signals
by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°, 120°, 135°, 144°, 180°, or 240°. The
shifted DQS signal is then used as the clock for the DQ IOE input registers.
All DQS/CQ and CQn pins, referenced to the same DLL, can have their input signal
phase shifted by a different degree amount but all must be referenced at one
particular frequency. For example, you can have a 90° phase shift on DQS1T and a 60°
phase shift on DQS2T, referenced from a 200-MHz clock. Not all phase-shift
combinations are supported. The phase shifts on the DQS pins referenced by the same
DLL must all be a multiple of 22.5° (up to 90°), 30° (up to 120°), 36° (up to 144°), 45°
(up to 180°), or 60° (up to 240°).
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–42
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
There are eight different frequency modes for the Stratix IV DLL, as listed in
Table 7–18. Each frequency mode provides different phase shift selections. In
frequency mode 0, 1, 2, and 3, the 6-bit DQS delay settings vary with PVT to
implement the phase-shift delay. In frequency modes 4, 5, 6, and 7, only 5 bits of the
DQS delay settings vary with PVT to implement the phase-shift delay; the most
significant bit of the DQS delay setting is set to 0.
Table 7–18. Stratix IV DLL Frequency Modes
Frequency Mode
Available Phase Shift
Number of Delay Chains
0
22.5, 45, 67.5, 90
16
1
30, 60, 90, 120
12
2
36, 72, 108, 144
10
3
45, 90, 135, 180
8
4
30, 60, 90, 120
12
5
36, 72, 108, 144
10
6
45, 90, 135, 180
8
7
60, 120, 180, 240
6
f For the frequency range of each mode, refer to the DC and Switching Characteristics for
Stratix IV Devices chapter.
For 0° shift, the DQS/CQ signal bypasses both the DLL and DQS logic blocks. The
Quartus II software automatically sets the DQ input delay chains so that the skew
between the DQ and DQS/CQ pin at the DQ IOE registers is negligible when 0° shift
is implemented. You can feed the DQS delay settings to the DQS logic block and logic
array.
The shifted DQS/CQ signal goes to the DQS bus to clock the IOE input registers of the
DQ pins. The signal can also go into the logic array for resynchronization if you are
not using IOE resynchronization registers. The shifted CQn signal can only go to the
negative-edge input register in the DQ IOE and is only used for QDR II+ and QDR II
SRAM interfaces.
Phase Offset Control
Each DLL has two phase-offset modules and can provide two separate DQS delay
settings with independent offsets, one for the top and bottom I/O bank and one for
the left and right I/O bank, so you can fine-tune the DQS phase-shift settings between
two different sides of the device. Even though you have independent phase offset
control, the frequency of the interface using the same DLL must be the same. Use the
phase offset control module for making small shifts to the input signal and use the
DQS phase-shift circuitry for larger signal shifts. For example, if the DLL only offers a
multiple of 30° phase shift, but your interface needs a 67.5° phase shift on the DQS
signal, you can use two delay chains in the DQS logic blocks to give you 60° phase
shift and use the phase offset control feature to implement the extra 7.5° phase shift.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–43
You can use either a static phase offset or a dynamic phase offset to implement the
additional phase shift. The available additional phase shift is implemented in 2’s:
complement in Gray-code between settings –64 to +63 for frequency mode 0, 1, 2, and
3, and between settings –32 to +31 for frequency modes 4, 5, 6, and 7. An additional bit
indicates whether the setting has a positive or negative value. The settings are linear,
each phase offset setting adds a delay amount specified in the DC and Switching
Characteristics for Stratix IV Devices chapter. The DQS phase shift is the sum of the DLL
delay settings and the user-selected phase offset settings whose top setting is 64 for
frequency modes 0, 1, 2, and 3; and 32 for frequency modes 4, 5, 6, and 7, so the actual
physical offset setting range is 64 or 32 subtracted by the DQS delay settings from the
DLL.
1
When using this feature, you need to monitor the DQS delay settings to know how
many offsets you can add and subtract in the system. Note that the DQS delay settings
output by the DLL are also Gray coded.
For example, if the DLL determines that DQS delay settings of 28 is needed to achieve
a 30° phase shift in DLL frequency mode 1, you can subtract up to 28 phase offset
settings and you can add up to 35 phase offset settings to achieve the optimal delay
that you need. However, if the same DQS delay settings of 28 is needed to achieve 30°
phase shift in DLL frequency mode 4, you can still subtract up to 28 phase offset
settings, but you can only add up to 3 phase offset settings before the DQS delay
settings reach their maximum settings because DLL frequency mode 4 only uses 5-bit
DLL delay settings.
f For more information about the value for each step, refer to the DC and Switching
Characteristics for Stratix IV Devices chapter.
When using static phase offset, you can specify the phase offset amount in the
ALTMEMPHY megafunction as a positive number for addition or a negative number
for subtraction. You can also have a dynamic phase offset that is always added to,
subtracted from, or both added to and subtracted from the DLL phase shift. When
you always add or subtract, you can dynamically input the phase offset amount into
the dll_offset[5..0] port. When you want to both add and subtract dynamically,
you control the addnsub signal in addition to the dll_offset[5..0] signals.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–44
Stratix IV Device Handbook Volume 1
DQS Logic Block
Each DQS/CQ and CQn pin is connected to a separate DQS logic block, which consists of the DQS delay chains, update enable
circuitry, and DQS postamble circuitry, as shown in Figure 7–24.
Figure 7–24. Stratix IV DQS Logic Block
DQS Delay Chain
DQS Enable
dqsenable (2)
1xx
000 dqsbusout
001
010
011
Bypass
dqsin
DQS bus
6
6
DQS Enable Control
0
1
0
1
6
D
Input Reference
Clock (1)
Q
dqsupdateen
Update
Enable
Circuitry
phasectrlin
6
<dqs_ctrl_latches_enable>
6
delayctrlin
Resynchronization
Clock
clk
4
phaseinvertctrl
0111
0110
0101
0100
0011
0010
0001
0000
Postamble
Enable
0
1
<level_dqs_enable>
postamble control clock
0
0 dqsenableout
0 1
1
1
dqsenablein
enaphasetransferreg
<delay_dqs_enable_by_half_cycle>
February 2011
Notes to Figure 7–24:
(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer to Table 7–5 on page 7–33 through Table 7–17 on page 7–40.
(2) The dqsenable signal can also come from the Stratix IV FPGA fabric.
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
6
offsetctrlin [5:0]
6
Phase offset
1
D Q
settings from the
0
DQS phase-shift
circuitry
<dqs_offsetctrl_enable>
6
DQS delay
settings from the delayctrlin [5:0]
DQS phase-shift
circuitry
dqsbusout
phasectrlin[2:0]
dqsin
DQS/CQ or
CQn Pin
6
PRE
Q D
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–45
DQS Delay Chain
DQS delay chains consist of a set of variable delay elements to allow the input
DQS/CQ and CQn signals to be shifted by the amount specified by the DQS
phase-shift circuitry or the logic array. There are four delay elements in the DQS delay
chain; the first delay chain closest to the DQS/CQ pin can be shifted either by the
DQS delay settings or by the sum of the DQS delay setting and the phase-offset
setting. The number of delay chains required is transparent because the
ALTMEMPHY megafunction automatically sets it when you choose the operating
frequency. The DQS delay settings can come from the DQS phase-shift circuitry on
either end of the I/O banks or from the logic array.
The delay elements in the DQS logic block have the same characteristics as the delay
elements in the DLL. When the DLL is not used to control the DQS delay chains, you
can input your own Gray-coded 6-bit or 5-bit settings using the
dqs_delayctrlin[5..0] signals available in the ALTMEMPHY megafunction. These
settings control 1, 2, 3, or all 4 delay elements in the DQS delay chains. The
ALTMEMPHY megafunction can also dynamically choose the number of DQS delay
chains needed for the system. The amount of delay is equal to the sum of the delay
element’s intrinsic delay and the product of the number of delay steps and the value
of the delay steps.
You can also bypass the DQS delay chain to achieve a 0° phase shift.
Update Enable Circuitry
Both the DQS delay settings and the phase-offset settings pass through a register
before going into the DQS delay chains. The registers are controlled by the update
enable circuitry to allow enough time for any changes in the DQS delay setting bits to
arrive at all the delay elements. This allows them to be adjusted at the same time. The
update enable circuitry enables the registers to allow enough time for the DQS delay
settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic
blocks before the next change. It uses the input reference clock or a user clock from the
core to generate the update enable output. The ALTMEMPHY megafunction uses this
circuit by default. Figure 7–25 shows an example waveform of the update enable
circuitry output.
Figure 7–25. DQS Update Enable Waveform
DLL Counter Update
(Every 8 cycles)
DLL Counter Update
(Every 8 cycles)
System Clock
DQS Delay Settings
(Updated every 8 cycles)
6 bit
Update Enable
Circuitry Output
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–46
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe such as in DDR3,
DDR2, and DDR SDRAM, the DQS signal is low before going to or coming from a
high-impedance state. The state in which DQS is low, just after a high-impedance
state, is called the preamble; the state in which DQS is low, just before it returns to a
high-impedance state, is called the postamble. There are preamble and postamble
specifications for both read and write operations in DDR3, DDR2, and DDR SDRAM.
The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS
line during the end of a read operation that occurs while DQS is in a postamble state.
Stratix IV devices have dedicated postamble registers that you can control to ground
the shifted DQS signal used to clock the DQ input registers at the end of a read
operation. This ensures that any glitches on the DQS input signals during the end of a
read operation that occurs while DQS is in a postamble state do not affect the DQ IOE
registers.
In addition to the dedicated postamble register, Stratix IV devices also have an HDR
block inside the postamble enable circuitry. Use these registers if the controller is
running at half the frequency of the I/Os.
Using the HDR block as the first stage capture register in the postamble enable
circuitry block is optional. The HDR block is clocked by the half-rate
resynchronization clock, which is the output of the I/O clock divider circuit (shown in
Figure 7–31 on page 7–50). There is an AND gate after the postamble register outputs
that is used to avoid postamble glitches from a previous read burst on a
non-consecutive read burst. This scheme allows a half-a-clock cycle latency for
dqsenable assertion and zero latency for dqsenable de-assertion, as shown in
Figure 7–26.
Figure 7–26. Avoiding Glitch on a Non-Consecutive Read Burst Waveform
Postamble glitch
Postamble
Preamble
DQS
Postamble Enable
dqsenable
Delayed by
1/2T logic
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–47
Leveling Circuitry
DDR3 SDRAM unbuffered modules use a fly-by clock distribution topology for better
signal integrity. This means that the CK/CK# signals arrive at each DDR3 SDRAM
device in the module at different times. The difference in arrival time between the first
DDR3 SDRAM device and the last device on the module can be as long as 1.6 ns.
Figure 7–27 shows the clock topology in DDR3 SDRAM unbuffered modules.
Figure 7–27. DDR3 SDRAM Unbuffered Module Clock Topology
DQS/DQ
DQS/DQ
DQS/DQ
DQS/DQ CK/CK# DQS/DQ
DQS/DQ
DQS/DQ
DQS/DQ
Stratix IV Device
Because the data and read strobe signals are still point-to-point, take special care to
ensure that the timing relationship between the CK/CK# and DQS signals (tDQSS,
tDSS, and tDSH) during a write is met at every device on the modules. Furthermore,
read data coming back into the FPGA from the memory is also staggered in a similar
way.
Stratix IV FPGAs have leveling circuitry to address these two situations. There is one
leveling circuitry per I/O sub-bank (for example, I/O sub-bank 1A, 1B, and 1C each
has one leveling circuitry). These delay chains are PVT-compensated by the same DQS
delay settings as the DLL and DQS delay chains.
For frequencies equal to and above 400 MHz, the DLL uses eight delay chains, such
that each delay chain generates a 45° delay. The generated clock phases are
distributed to every DQS logic block that is available in the I/O sub-bank. The delay
chain taps then feeds a multiplexer controlled by the ALTMEMPHY megafunction to
select which clock phases are to be used for that ×4 or × 8 DQS group. Each group can
use a different tap output from the read-leveling and write-leveling delay chains to
compensate for the different CK/CK# delay going into each device on the module.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–48
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–28 and Figure 7–29 show the Stratix IV write- and read-leveling circuitry.
Figure 7–28. Stratix IV Write-Leveling Delay Chains and Multiplexers (Note 1)
Write clk
(-900)
Write-Leveled DQS Clock
Write-Leveled DQ Clock
Note to Figure 7–28:
(1) There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can only have
one memory interface in each I/O sub-bank when you use the leveling delay chain.
Figure 7–29. Stratix IV Read-Leveling Delay Chains and Multiplexers (Note 1)
I/O Clock Divider (2)
use_masterin
slaveout
masterin
DQS
delayctrlin
1
0
Half-Rate
Resynchronization Clock
DFF
1
0
clkout
Half-Rate Source
Synchronous Clock
phaseselect
phasectrlin
6
4
phaseinvertctrl
Resynchronization Clock
(resync_clk_2x)
0111
0110
0101
0100
0011
0010
0001
0000
0
1
Read-Leveled Resynchronization Clock
Notes to Figure 7–29:
(1) There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can only have one memory interface in each
I/O sub-bank when you use the leveling delay chain.
(2) Each divider feeds up to six pins (from a × 4 DQS group) in the device. To feed wider DQS groups, you must chain multiple clock dividers together
by feeding the slaveout output of one divider to the masterin input of the neighboring pins’ divider.
The –90° write clock of the ALTMEMPHY megafunction feeds the write-leveling
circuitry to produce the clock to generate the DQS and DQ signals. During
initialization, the ALTMEMPHY megafunction picks the correct write-leveled clock
for the DQS and DQ clocks for each DQS/DQ group after sweeping all the available
clocks in the write calibration process. The DQ clock output is –90° phase-shifted
compared to the DQS clock output.
Similarly, the resynchronization clock feeds the read-leveling circuitry to produce the
optimal resynchronization and postamble clock for each DQS/DQ group in the
calibration process. The resynchronization and postamble clocks can use different
clock outputs from the leveling circuitry. The output from the read-leveling circuitry
can also generate the half-rate resynchronization clock that goes to the FPGA fabric.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
1
7–49
The ALTMEMPHY megafunction dynamically calibrates the alignment for read- and
write-leveling during the initialization process.
f For more information about the ALTMEMPHY megafunction, refer to the External
Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide.
Dynamic On-Chip Termination Control
Figure 7–30 shows the dynamic OCT control block. The block includes all the registers
needed to dynamically turn on OCT RT during a read and turn OCT RT off during a
write.
f For more information about dynamic on-chip termination control, refer to the I/O
Features in Stratix IV Devices chapter.
Figure 7–30. Stratix IV Dynamic OCT Control Block
OCT Control
OCT Enable
2
DFF
OCT HalfRate Clock
HDR
Block
DFF
Resynchronization
Registers
Write
Clock (1)
OCT Control Path
Note to Figure 7–30:
(1) The write clock comes from either the PLL or the write-leveling delay chain.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–50
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
I/O Element Registers
The IOE registers are expanded to allow source-synchronous systems to have faster
register-to-register transfers and resynchronization. Both top and bottom and left and
right IOEs have the same capability. Left and right IOEs have extra features to support
LVDS data transfer.
Figure 7–31 shows the registers available in the Stratix IV input path. The input path
consists of the DDR input registers, resynchronization registers, and HDR block. You
can bypass each block of the input path.
Figure 7–31. Stratix IV IOE Input Registers (Note 1)
DQ
Double Data Rate Input Registers
D
Q
DFF
Input Reg AI
D
DQS/CQ (3), (9)
Differential
Input
Buffer
DQSn (9)
CQn (4)
Q
neg_reg_out
DFF
Input Reg BI
0
1
D
Q
Half Data Rate Registers
DFF
Input Reg C I
directin
Alignment & Synchronization Registers
D
Q
D
0
1
Q
datain [0]
D
Q
dataout
D
DFF
DFF
0
D
0
1
1
Q
To Core
dataout [0]
(7)
DFF
Q
DFF
DFF
D
enaphasetransferreg
enainputcycledelay
<bypass_output_register>(10)
D
Q
1
D
DFF
Q
0
1
DFF
dataout
D
DFF
Resynchronization Clock
(resync_clk_2x) (5)
DFF
1
Q
DFF
D
Q
DFF
I/O Clock
Divider (6)
DFF
Q
(2)
dataoutbypass
(8)
Q
0
D
0
Q
D
DFF
datain [1]
D
Q
To Core
dataout[2]
(7)
D
To Core
dataout [1]
(7)
To Core
dataout [3]
(7)
Q
DFF
Half-Rate Resynchronization Clock (resync_clk_1x)
to core (7)
Notes to Figure 7–31:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
You can bypass each register block in this path.
This is the 0-phase resynchronization clock (from the read-leveling delay chain).
The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
This input clock comes from the CQn logic block.
This resynchronization clock comes from a PLL through the clock network (resync_ck_2x).
The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL and read-leveled resync clock, the I/O clock divider can also
be fed by the DQS bus or CQn bus.
The half-rate data and clock signals feed into a dual-port RAM in the FPGA core.
You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data
rate register to feed dataout.
The DQS and DQSn signals must be inverted for DDR, DDR2, and DDR3 interfaces. When using Altera’s memory interface IPs, the DQS and DQSn
signals are automatically inverted.
The bypass_output_register option allows you to select either the output from the second mux or the output of the fourth alignment/
synchronization register to feed dataout.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–51
There are three registers in the DDR input registers block. Two registers capture data
on the positive and negative edges of the clock, while the third register aligns the
captured data. You can choose to use the same clock for the positive edge and
negative edge registers, or two complementary clocks (DQS/CQ for the positive-edge
register and DQSn/CQn for the negative-edge register). The third register that aligns
the captured data uses the same clock as the positive edge registers.
The resynchronization registers consist of up to three levels of registers to
resynchronize the data to the system clock domain. These registers are clocked by the
resynchronization clock that is either generated by the PLL or the read-leveling delay
chain. The outputs of the resynchronization registers can go straight to the core or to
the HDR blocks, which are clocked by the divided-down resynchronization clock.
For more information about the read-leveling delay chain, refer to “Leveling
Circuitry” on page 7–47.
Figure 7–32 shows the registers available in the Stratix IV output and output-enable
paths. The path is divided into the HDR block, resynchronization registers, and
output and output-enable registers. The device can bypass each block of the output
and output-enable path.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–52
Stratix IV Device Handbook Volume 1
Figure 7–32. Stratix IV IOE Output and Output-Enable Path Registers (Note 1)
Half Data Rate to Single Data Rate Output-Enable Registers
From Core (2)
Alignment Registers (4)
D
Q
Double Data Rate Output-Enable Registers
DFF
DFF
From Core (2)
0
1
D
Q
D
DFF
D
Q
D
D
D
Q
Q
Q
DFF
Q
OE Reg A OE
DFF
OR2
1
DFF
DFF
0
DFF
D
Half Data Rate to Single Data Rate Output Registers
Q
Alignment Registers (4)
OE Reg B OE
From Core
(wdata2) (2)
D
Q
Double Data Rate Output Registers
DFF
DFF
0
D
Q
D
Q
D
1
From Core
(wdata0) (2)
D
DFF
D
Q
D
Q
Q
Q
TRI
DFF
Output Reg Ao
DFF
DFF
D
Output Reg Bo
0
1
D
Q
DFF
D
Q
Q
DFF
Q
DFF
From Core
(wdata1) (2)
D
Q
D
D
Q
Q
DFF
DFF
DFF
Half-Rate Clock (3)
February 2011
Alignment
Clock (3)
Write
Clock (5)
Notes to Figure 7–32:
Altera Corporation
(1)
(2)
(3)
(4)
(5)
You can bypass each register block of the output and output-enable paths.
Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode.
The half-rate clock comes from the PLL, while the alignment clock comes from the write-leveling delay chains.
These registers are only used in DDR3 SDRAM interfaces for write-leveling purposes.
The write clock can come from either the PLL or from the write-leveling delay chain. The DQ write clock and DQS write clock have a 90° offset between them.
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
D
DQ or DQS
DFF
DFF
From Core
(wdata3) (2)
1
0
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–53
The output path is designed to route combinatorial or registered SDR outputs and
full-rate or half-rate DDR outputs from the FPGA core. Half-rate data is converted to
full-rate using the HDR block, clocked by the half-rate clock from the PLL. The
resynchronization registers are also clocked by the same 0° system clock, except in the
DDR3 SDRAM interface. In DDR3 SDRAM interfaces, the leveling registers are
clocked by the write-leveling clock.
For more information about the write-leveling delay chain, refer to “Leveling
Circuitry” on page 7–47.
The output-enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications and you can use half-rate or
full-rate operation in DDR applications. Also, the ouput-enable path’s
resynchronization registers have a structure similar to the output path registers,
ensuring that the output-enable path goes through the same delay and latency as the
output path.
Delay Chain
Stratix IV devices have run-time adjustable delay chains in the I/O blocks and the
DQS logic blocks. You can control the delay chain setting through the I/O or the DQS
configuration block output. Figure 7–33 shows the delay chain ports.
Figure 7–33. Delay Chain
delayctrlin [3..0]
<use finedelayctrlin>
finedelayctrlin
datain
Δt
0
dataout
Δt
1
Every I/O block contains the following:
February 2011
■
Two delay chains in a series between the output registers and the output buffer
■
One delay chain between the input buffer and the input register
■
Two delay chains between the output enable and the output buffer
■
Two delay chains between the OCT RT enable control register and the output
buffer
Altera Corporation
Stratix IV Device Handbook Volume 1
7–54
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–34 shows the delay chains in an I/O block.
Figure 7–34. Delay Chains in an I/O Block
rtena
oe
octdelaysetting1 (only)
D5 OCT
Delay
Chain
D5 OutputEnable Delay
Chain
octdelaysetting2 (only)
D6 OCT
Delay
Chain
D6 OutputEnable Delay
Chain
(outputdelaysetting1 +
outputfinedelaysetting1)
(outputdelaysetting2 +
outputfinedelaysetting2)
D5 Delay
Delay
Chain
D6 Delay
Delay
Chain
0
1
(outputdelaysetting2 + outputfinedelaysetting2) or
(outputonlydelaysetting2 + outputonlyfinedelaysetting2)
D1 Delay
Delay Chain
(padtoinputregisterdelaysetting +
padtoinputregisterfinedelaysetting)
Each DQS logic block contains a delay chain after the dqsbusout output and another
delay chain before the dqsenable input. Figure 7–35 shows the delay chains in the
DQS input path.
Figure 7–35. Delay Chains in the DQS Input Path
(dqsbusoutdelaysetting +
dqsbusoutfinedelaysetting)
DQS
DQS
Delay
Chain
DQS
Enable
D4 Delay
Chain
dqsin
dqsbusout
dqsenable
(dqsenabledelaysetting +
dqsenablefinedelaysetting)
T11 Delay
Chain
DQS
Enable
Control
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–55
I/O Configuration Block and DQS Configuration Block
The I/O configuration block and the DQS configuration block are shift registers that
you can use to dynamically change the settings of various device configuration bits.
The shift registers power-up low. Every I/O pin contains one I/O configuration
register, while every DQS pin contains one DQS configuration block in addition to the
I/O configuration register. Figure 7–36 shows the I/O configuration block and the
DQS configuration block circuitry.
Figure 7–36. I/O Configuration Block and DQS Configuration Block
bit 0
bit 1
MSB
bit 2
datain
update
ena
clk
Table 7–19 lists the I/O configuration block bit sequence.
Table 7–19. I/O Configuration Block Bit Sequence
Bit
Bit Name
0..3
outputdelaysetting1[0..3]
4..6
outputdelaysetting2[0..2]
7..10
padtoinputregisterdelaysetting[0..3]
Table 7–20 lists the DQS configuration block bit sequence.
Table 7–20. DQS Configuration Block Bit Sequence (Part 1 of 2)
February 2011
Altera Corporation
Bit
Bit Name
0..3
dqsbusoutdelaysetting[0..3]
4..6
dqsinputphasesetting[0..2]
7..10
dqsenablectrlphasesetting[0..3]
11..14
dqsoutputphasesetting[0..3]
15..18
dqoutputphasesetting[0..3]
19..22
resyncinputphasesetting[0..3]
23
dividerphasesetting
24
enaoctcycledelaysetting
25
enainputcycledelaysetting
26
enaoutputcycledelaysetting
27..29
dqsenabledelaysetting[0..2]
30..33
octdelaysetting1[0..3]
Stratix IV Device Handbook Volume 1
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Document Revision History
Table 7–20. DQS Configuration Block Bit Sequence (Part 2 of 2)
Bit
Bit Name
34..36
octdelaysetting2[0..2]
37
enadataoutbypass
38
enadqsenablephasetransferreg
39
enaoctphasetransferreg
40
enaoutputphasetransferreg
41
enainputphasetransferreg
42
resyncinputphaseinvert
43
dqsenablectrlphaseinvert
44
dqoutputphaseinvert
45
dqsoutputphaseinvert
Document Revision History
Table 7–21 lists the revision history for this chapter.
Table 7–21. Document Revision History (Part 1 of 2)
Date
February 2011
March 2010
Version
3.2
3.1
Stratix IV Device Handbook Volume 1
Changes
■
Updated Table 7–5, Table 7–6, Table 7–11, Table 7–19, and Table 7–20.
■
Added Table 7–12.
■
Updated Figure 7–36.
■
Removed Table 7-1 and Table 7-6.
■
Applied new template.
■
Minor text edits.
■
Updated Figure 7–8, Figure 7–11, Figure 7–23, Figure 7–24, Figure 7–29, Figure 7–31,
and Figure 7–36.
■
Added Figure 7–9 and Figure 7–12.
■
Added Table 7–7.
■
Updated Table 7–1, Table 7–2, Table 7–3, Table 7–4, Table 7–6, Table 7–8 and Table 7–19.
■
Added note to the “Memory Interfaces Pin Support” section.
■
Changed “DLL1 through DLL4” to “DLL0 through DLL3” throughout.
■
Added frequency mode 7 throughout.
■
Minor text edits.
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Document Revision History
7–57
Table 7–21. Document Revision History (Part 2 of 2)
Date
Version
November 2009
June 2009
2.3
April 2009
2.2
March 2009
2.1
November 2008
May 2008
February 2011
3.0
2.0
1.0
Altera Corporation
Changes
■
Updated the “Memory Interfaces Pin Support” and “Combining ×16/×18 DQS/DQ Groups
for a ×36 QDR II+/QDR II SRAM Interface” sections.
■
Updated Table 7–1, Table 7–2, Table 7–7, and Table 7–12.
■
Updated Figure 7–3, Figure 7–4, Figure 7–5, Figure 7–6, Figure 7–7, Figure 7–8,
Figure 7–9, Figure 7–10, Figure 7–11, Figure 7–13, Figure 7–14, Figure 7–15, and
Figure 7–16.
■
Added Figure 7–12 and Figure 7–17.
■
Added Table 7–14, Table 7–17, Table 7–19, and Table 7–20.
■
Added “Delay Chain” and “I/O Configuration Block and DQS Configuration Block”
sections.
■
Removed Figure 7-8 and Figure 7-12.
■
Removed Table 7-1, Table 7-2, and Table 7-24.
■
Minor text edits.
■
Updated “Overview” and “Leveling Circuitry”.
■
Updated Figure 7–26 and Figure 7–27.
■
Updated Table 7–3.
■
Added introductory sentences to improve search ability.
■
Removed the Conclusion section.
■
Updated Table 7–5, Table 7–6, Table 7–15, and Table 7–17
■
Removed Figure 7-12, Figure 7-13, and Figure 7-20
■
Updated Table 7–1, Table 7–5, Table 7–8, Table 7–12, Table 7–13, Table 7–14,
Table 7–15, and Table 7–17.
■
Replaced Table 7–6.
■
Added Table 7–11 and Table 7–16.
■
Updated Figure 7–3, Figure 7–6, Figure 7–8, Figure 7–9, and Figure 7–11.
■
Added Figure 7–7, Figure 7–11, Figure 7–12, Figure 7–13, and Figure 7–20.
■
Updated “Combining ×16/×18 DQS/DQ Groups for ×36 QDR II+/QDR II SRAM Interface”.
■
Updated “Rules to Combine Groups”.
■
Removed “Referenced Documents” section.
■
Updated Table 7–1, Table 7–2, Table 7–3, Table 7–4, Table 7–5, and Table 7–6.
■
Added Table 7–7.
■
Updated Figure 7–1 and Figure 7–19.
■
Updated “Combining ×16/×18 DQS/DQ groups for ×36 QDR II+/QDR II SRAM Interface”
on page 7–26.
■
Updated “Rules to Combine Groups” on page 7–27.
■
Updated “DQS Phase-Shift Circuitry” on page 7–29.
■
Updated Table 7–9, Table 7–10, Table 7–11, Table 7–13, Table 7–13, Table 7–14,
Table 7–15, Table 7–15, Table 7–16, and Table 7–18.
■
Updated Figure 7–30 and Figure 7–31.
■
Made minor editorial changes.
Initial release.
Stratix IV Device Handbook Volume 1
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Document Revision History
February 2011
Altera Corporation

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