HSMS-282x Data Sheet Surface Mount RF Schottky Barrier Diodes Description/Applications

HSMS-282x Data Sheet Surface Mount RF Schottky  Barrier Diodes Description/Applications

HSMS-282x

Surface Mount RF Schottky Barrier Diodes

Data Sheet

Description/Applications

These Schottky diodes are specifically designed for both analog and digital applications. This series offers a wide range of specifica tions and package con figura tions to give the designer wide flexi bility. Typical applications of these Schottky diodes are mixing, detecting, switching, sampling, clamping, and wave shaping. The HSMS‑282x series of diodes is the best all‑around choice for most applications, featuring low series resistance, low forward voltage at all current levels and good RF characteristics.

Note that Avago’s manufacturing techniques assure that dice found in pairs and quads are taken from adjacent sites on the wafer, assuring the highest degree of match.

Package Lead Code Identification,

SOT-23/SOT-143 (Top View)

SINGLE

3

SERIES

3

COMMON

ANODE

3

COMMON

CATHODE

3

Features

Low Turn‑On Voltage (As Low as 0.34 V at 1 mA)

Low FIT (Failure in Time) Rate*

Six‑sigma Quality Level

Single, Dual and Quad Versions

• Unique Configurations in Surface Mount SOT‑363 Package

– increase flexibility

– save board space

– reduce cost

HSMS‑282K Grounded Center Leads Provide up to 10 dB Higher Isolation

Matched Diodes for Consistent Performance

• Better Thermal Conductivity for Higher Power Dissipation

Lead‑free Option Available

* For more information see the Surface Mount Schottky Reliability

Data Sheet.

Package Lead Code Identification, SOT-363

(Top View)

HIGH ISOLATION

UNCONNECTED PAIR

6 5 4

UNCONNECTED

TRIO

6 5 4

1

#0

2

UNCONNECTED

PAIR

3 4

1

#2

2

3

RING

QUAD

4

1

#3

2

3

BRIDGE

QUAD

4

1

#4

2

CROSS-OVER

QUAD

3 4

1 2

K

3

COMMON

CATHODE QUAD

6 5 4

1 2

L

3

6

COMMON

ANODE QUAD

5 4

1

#5

2 1

#7

2 1

#8

2

Package Lead Code Identification, SOT-323

(Top View)

SINGLE

SERIES

1

#9

2

1

6

2

M

3

BRIDGE

QUAD

5 4

1

6

2

N

3

RING

QUAD

4

1 2

P

3 1 2

R

3

B

COMMON

ANODE

C

COMMON

CATHODE

E

F

Pin Connections and Package Marking

1

2

3

6

5

4

Notes:

1. Package marking provides orientation and identification.

2. See “Electrical Specifications” for appropriate package marking.

Absolute Maximum Ratings

[1]

T

C

= 25°C

Symbol Parameter Unit SOT-23/SOT-143 SOT-323/SOT-363

I f

P

IV

Forward Current (1 µs Pulse)

Peak Inverse Voltage

Amp

V

1

15

1

15

T j

Junction Temperature °C 150 150

T stg

Storage Temperature °C ‑65 to 150 ‑65 to 150

θ jc

Thermal Resistance

[2]

°C/W 500 150

Notes:

1. Operation in excess of any one of these conditions may result in permanent damage to the device.

2. T

C

= +25°C, where T

C

is defined to be the temperature at the package pins where contact is made to the circuit board.

Electrical Specifications T

C

= 25°C, Single Diode

[3]

Minimum

Breakdown

Voltage

V

BR

(V)

15

Maximum

Forward

Voltage

V

F

(mV)

340

Maximum

Forward

Voltage

V

I

F

F

(V) @

(mA)

0.5 10

Maximum

Reverse

I

Leakage

R

(nA) @

V

R

(V)

100 1

C3

C4

CK

C8

C9

C0

C2

C3

C4

C5

C7

Package

Marking

Code

C0

C2

2828

2829

282B

282C

282E

282F

282K

Part

Number

HSMS

[4]

2820

2822

2823

2824

2825

2827

282L

282M

282N

282P

CL

HH

NN

CP

282R OO

Test Conditions

N

P

L

M

R

E

F

K

B

C

8

9

5

7

3

4

0

2

Lead

Code Configuration

Single

Series

Common Anode

Common Cathode

Unconnected Pair

Ring Quad [4]

Bridge Quad [4]

Cross‑over Quad

Single

Series

Common Anode

Common Cathode

High Isolation

Unconnected Pair

Unconnected Trio

Common Cathode Quad

Common Anode Quad

Bridge Quad

Ring Quad

I

R

= 100 mA I

F

= 1 mA [1]

Maximum

Capacitance

C

T

(pF)

1.0

V

R

= 0V [2] f = 1 MHz

Notes:

1.

∆V

F

for diodes in pairs and quads in 15 mV maximum at 1 mA.

2. ∆C

TO

for diodes in pairs and quads is 0.2 pF maximum.

3. Effective Carrier Lifetime (

τ) for all these diodes is 100 ps maximum measured with Krakauer method at 5 mA.

4. See section titled “Quad Capacitance.”

5. R

D

= R

S

+ 5.2Ω at 25°C and I f

= 5 mA.

2

Typical

Dynamic

Resistance

R

D

(

)

[5]

12

I

F

= 5 mA

Quad Capacitance

Capacitance of Schottky diode quads is measured using an HP4271 LCR meter. This instrument effectively isolates individual diode branches from the others, allowing ac‑ curate capacitance measurement of each branch or each diode. The conditions are: 20 mV R.M.S. voltage at 1 MHz.

Avago defines this measurement as “CM”, and it is equiv‑ alent to the capaci tance of the diode by itself. The equiv‑ alent diagonal and adja cent capaci‑tances can then be calculated by the formulas given below.

In a quad, the diagonal capaci tance is the capacitance be‑ tween points A and B as shown in the figure below. The diagonal capacitance is calculated using the following formula

C

DIAGONAL

C

1

1

x C

+ C

2

2

C

C

3

x C

3

+ C

4

4

The equivalent adjacent capacitance is the capacitance

C

ADJACENT

DIAGONAL

= _______ + _______

C

1

+ C

2

2

1 1 1

C

2

C

3

x C

C

4

C j

= C + ____________ b

+ I

1 1 1

–– + –– + ––

C

2

C

3

C

4

This information does not apply to cross‑over quad di‑ odes.

j

I b

+ I s

-5

nT

C

C

1

C

2

C

3

C

4

A

B

Linear Equivalent Circuit Model Diode Chip

R

S

R j

C j

R

S

= series resistance (see Table of SPICE parameters)

C j

= junction capacitance (see Table of SPICE parameters)

R j

=

8.33 X 10

-5

nT

I b

+ I s where

I

I

T b

= externally applied bias current in amps s

= saturation current (see table of SPICE parameters)

= temperature, K n = ideality factor (see table of SPICE parameters)

Note:

To effectively model the packaged HSMS-282x product, please refer to Application Note AN1124.

ESD WARNING: Handling Precautions Should Be Taken To Avoid Static Discharge.

SPICE Parameters

Parameter

B

V

C

J0

E

G

I

BV

I

S

N

P

T

M

R

S

P

B

Units

V pF eV

A

A

Ω

V

HSMS-282x

15

0.7

0.69

1E‑4

2.2E‑8

1.08

6.0

0.65

2

0.5

3

Typical Performance, T

C

= 25°C (unless otherwise noted), Single Diode

100

100,000

10

T

A

T

A

T

A

T

A

= +125C

= +75C

= +25C

= –25C

10,000

1000

1

100

0.1

0.01

0 0.10

0.20

0.30

0.40

V

F

– FORWARD VOLTAGE (V)

Figure 1. Forward Current vs. Forward Voltage at

Temperatures.

0.50

10

1

0 5

T

A

= +125C

T

T

A

A

= +75C

= +25C

10

V

R

– REVERSE VOLTAGE (V)

Figure 2. Reverse Current vs. Reverse Voltage at

Temperatures.

15

1000 30

10

I

F

(Left Scale)

30

10

100

1

0.8

0.6

0.4

0.2

0

0 2 4 6

V

R

– REVERSE VOLTAGE (V)

Figure 3. Total Capacitance vs. Reverse Voltage.

8

100

I

F

(Left Scale)

1.0

10

10

1

V

F

(Right Scale)

1

1

0.1

1 10 100

I

F

– FORWARD CURRENT (mA)

Figure 4. Dynamic Resistance vs. Forward Current.

0.3

0.2

0.4

0.6

0.8

1.0

V

F

- FORWARD VOLTAGE (V)

1.2

1.4

0.3

Figure 5. Typical V

Mixer Bias Levels.

f

Match, Series Pairs and Quads at

V

F

(Right Scale)

1

0.10

0.15

0.20

V

F

- FORWARD VOLTAGE (V)

0.1

0.25

Figure 6. Typical V

Levels. f

Match, Series Pairs at Detector Bias

1

DC bias = 3 A

0.1

-25C

+25C

+75C

0.01

RF in

18 nH HSMS-282B

Vo

3.3 nH

100 pF

100 K

0.001

-40 -30 -20 -10

P in

– INPUT POWER (dBm)

Figure 7. Typical Output Voltage vs. Input Power,

Small Signal Detector Operating at 850 MHz.

0

10

1

0.1

0.01

0.001

+25C RF in

HSMS-282B

Vo

0.0001

68

100 pF

4.7 K

1E-005

-20 -10 0 10 20

P in

– INPUT POWER (dBm)

Figure 8. Typical Output Voltage vs. Input Power,

Large Signal Detector Operating at 915 MHz.

30

10

9

8

7

6

0 2 4 6 8 10

LOCAL OSCILLATOR POWER (dBm)

12

Figure 9. Typical Conversion Loss vs. L.O. Drive, 2.0 GHz

(Ref AN997).

4

Applications Information

Product Selection

Avago’s family of surface mount Schottky diodes provide unique solutions to many design problems. Each is opti‑ mized for certain applications.

The first step in choosing the right product is to select the diode type. All of the products in the HSMS‑282x fami‑ ly use the same diode chip–they differ only in package configuration. The same is true of the HSMS‑280x, ‑281x,

285x, ‑286x and ‑270x families. Each family has a different set of characteristics, which can be compared most easily by consulting the SPICE parameters given on each data sheet.

The HSMS‑282x family has been optimized for use in RF applications, such as

DC biased small signal detectors to 1.5 GHz.

Biased or unbiased large signal detectors (AGC or power monitors) to 4 GHz.

Mixers and frequency multipliers to 6 GHz.

The other feature of the HSMS‑282x family is its unit‑to‑unit and lot‑to‑lot consistency. The silicon chip used in this se‑ ries has been designed to use the fewest possible process‑ ing steps to minimize variations in diode characteristics.

Statistical data on the consistency of this product, in terms of SPICE parameters, is available from Avago.

For those applications requiring very high breakdown voltage, use the HSMS‑280x family of diodes. Turn to the

HSMS‑281x when you need very low flicker noise. The

HSMS‑285x is a family of zero bias detector diodes for small signal applications. For high frequency detector or mixer applications, use the HSMS‑286x family. The HSMS‑270x is a series of specialty diodes for ultra high speed clipping and clamping in digital circuits.

Schottky Barrier Diode Characteristics

Stripped of its package, a Schottky barrier diode chip con‑ sists of a metal‑semiconductor barrier formed by deposi‑ tion of a metal layer on a semiconductor. The most com‑ mon of several different types, the passivated diode, is shown in Figure 10, along with its equivalent circuit.

R

S

is the parasitic series resistance of the diode, the sum of the bondwire and leadframe resistance, the resistance of the bulk layer of silicon, etc. RF energy coupled into R is lost as heat—it does not contribute to the rectified out‑

S put of the diode. C

J

is parasitic junction capaci tance of the diode, controlled by the thick‑ness of the epitaxial layer and the diameter of the Schottky contact. R flowing through it.

j

is the junc‑ tion resistance of the diode, a function of the total current

8.33 X 10

-5

nT

S b

≈ ––––– at 25 °C

I

S

+ I b where ––––– n = ideality factor (see table of SPICE parameters)

I

S

I

T = temperature in °K

R b v

= saturation current (see table of SPICE parameters)

= externally applied bias current in amps

= sum of junction and series resistance, the slope of the V‑I curve

I

S

is a function of diode barrier height, and can range from picoamps for high barrier diodes to as much as 5 µA for very low barrier diodes.

-5

The Height of the Schottky Barrier

b

– R s

The current‑voltage character istic of a Schottky barrier diode at room temperature is described by the following equation:

S

+ I b

V

I = I

S

(e

–––––

– 1)

On a semi‑log plot (as shown in the Avago catalog) the current graph will be a straight line with inverse slope 2.3

X 0.026 = 0.060 volts per cycle (until the effect of R by the saturation current, I height of the diode.

S

S

is seen in a curve that droops at high current). All Schottky diode curves have the same slope, but not necessarily the same value of current for a given voltage. This is deter mined

, and is related to the barrier

Through the choice of p‑type or n‑type silicon, and the selection of metal, one can tailor the characteristics of a

Schottky diode. Barrier height will be altered, and at the same time C

J

and R

S

will be changed. In general, very low barrier height diodes (with high values of I zero bias applica tions) are realized on p‑type silicon. Such diodes suffer from higher values of R

S

S

, suitable for

than do the n‑type.

METAL

V

– R s

PASSIVATION PASSIVATION

N-TYPE OR P-TYPE EPI LAYER

SCHOTTKY JUNCTION

N-TYPE OR P-TYPE SILICON SUBSTRATE

CROSS-SECTION OF SCHOTTKY

BARRIER DIODE CHIP

Figure 10. Schottky Diode Chip.

C j

R

S

R j

EQUIVALENT

CIRCUIT

5

Thus, p‑type diodes are generally reserved for detector applications (where very high values of R

V

swamp out high R

S

) and n‑type diodes such as the HSMS‑282x are used for mixer applications (where high L.O. drive levels keep R

V

low). DC biased detectors and self‑biased detec‑ tors used in gain or power control circuits.

Detector Applications

Detector circuits can be divided into two types, large signal

(P in

> ‑20 dBm) and small signal (P in

< ‑20 dBm). In general, the former use resistive impedance matching at the input to improve flatness over frequency—this is possible since the input signal levels are high enough to produce ade‑ quate output voltages without the need for a high Q reac‑ tive input matching network. These circuits are self‑biased

(no external DC bias) and are used for gain and power control of amplifiers.

Small signal detectors are used as very low cost receivers, and require a reactive input impedance matching net‑ work to achieve adequate sensitivity and output voltage.

Those operating with zero bias utilize the HSMS‑ 285x family of detector diodes. However, superior performance over temperature can be achieved with the use of 3 to 30

µA of DC bias. Such circuits will use the HSMS‑282x family of diodes if the operating frequency is 1.5 GHz or lower.

Typical performance of single diode detectors (using

HSMS‑2820 or HSMS‑282B) can be seen in the transfer curves given in Figures 7 and 8. Such detectors can be re‑ alized either as series or shunt circuits, as shown in Figure

11.

DC Bias

• The two diodes are in parallel in the RF circuit, lowering the input impedance and making the design of the RF matching network easier.

• The two diodes are in series in the output (video) circuit, doubling the output voltage.

• Some cancellation of even‑order harmonics takes place at the input.

DC Bias

Zero Biased Diodes

Figure 12. Voltage Doubler.

DC Biased Diodes

The most compact and lowest cost form of the doubler is achieved when the HSMS‑2822 or HSMS‑282C series pair is used.

Both the detection sensitivity and the DC forward voltage of a biased Schottky detector are temperature sensitive.

Where both must be compensated over a wide range of temperatures, the differential detector

[2]

is often used.

Such a circuit requires that the detector diode and the reference diode exhibit identical characteristics at all DC bias levels and at all temperatures. This is accomplished through the use of two diodes in one package, for exam‑ ple the HSMS‑2825 in Figure 13. In the Avago assembly facility, the two dice in a surface mount package are taken from adjacent sites on the wafer (as illustrated in Figure

14). This assures that the characteristics of the two diodes are more highly matched than would be possible through individual testing and hand matching.

Shunt inductor provides video signal return

Shunt diode provides video signal return

DC Bias

RF in

RF impedance matching network

R

M

R

L differential amplifier

Video out

+3V

Zero Biased Diodes DC Biased Diodes

Figure 11. Single Diode Detectors.

The series and shunt circuits can be combined into a volt‑ age doubler

[1]

, as shown in Figure 12. The doubler offers three advantages over the single diode circuit.

Figure 13. Differential Detector.

R

L

Notes:

1. Avago Application Note 956‑4, “Schottky Diode Voltage Doubler.”

2. Raymond W. Waugh, “Designing Large‑Signal Detectors for Handsets and Base Stations,” Wireless Systems Design, Vol. 2, No. 7, July 1997, pp 42 – 48.

6

bias differential amplifier matching network

HSMS-282P

Figure 14. Fabrication of Avago Diode Pairs.

In high power applications, coupling of RF energy from the detector diode to the reference diode can introduce error in the differential detector. The HSMS‑282K diode pair, in the six lead SOT‑363 package, has a copper bar between the diodes that adds 10 dB of additional isola‑ tion between them. As this part is manufactured in the

SOT‑363 package it also provides the benefit of being 40% smaller than larger SOT‑143 devices. The HSMS‑282K is il‑ lustrated in Figure 15—note that the ground connections must be made as close to the package as possible to min‑ imize stray inductance to ground.

detector diode

PA V bias

Figure 17. Voltage Doubler Differential Detector.

However, care must be taken to assure that the two refer‑ ence diodes closely match the two detector diodes. One possible configuration is given in Figure  16, using two

HSMS‑2825. Board space can be saved through the use of the HSMS‑282P open bridge quad, as shown in Figure 17.

While the differential detector works well over tempera‑ ture, another design approach

[3]

works well for large signal detectors. See Figure 18 for the schematic and a physical layout of the circuit. In this design, the two 4.7 KΩ resis‑ tors and diode D2 act as a variable power divider, assuring constant output voltage over temperature and improving output linearity.

RF in

D1

68

4.7 K

33 pF

V o

4.7 K

D2

68 33 pF

HSMS-282K reference diode to differential amplifier

Figure 15. High Power Differential Detector.

The concept of the voltage doubler can be applied to the differential detector, permitting twice the output voltage for a given input power (as well as improving input im‑ pedance and suppressing second harmonics).

bias matching network differential amplifier

HSMS-2825

HSMS-2825

HSMS-2825 or

HSMS-282K

RF in

HSMS-282K

4.7 K

V o

Figure 18. Temperature Compensated Detector.

In certain applications, such as a dual‑band cellphone handset operating at both 900 and 1800  MHz, the sec‑ ond harmonics generated in the power control output detector when the handset is working at 900 MHz can cause problems. A filter at the output can reduce unwant‑ ed emissions at 1800 MHz in this case, but a lower cost solution is available

[4]

. Illustrated schematically in Figure

19, this circuit uses diode D2 and its associated passive components to cancel all even order harmonics at the de‑ tector’s RF input. Diodes D3 and D4 provide temperature compensation as described above. All four diodes are con‑ tained in a single HSMS‑ 282R package, as illustrated in the layout shown in Figure 20.

Figure 16. Voltage Doubler Differential Detector.

Note 3. Hans Eriksson and Raymond W. Waugh, “A Temperature Compensated Linear Diode Detector,” to be published.

7

RF in

68

D1

D2

R3

C2

R4

V–

D4

C1

R1 V+

R2

D3

C1 = C2 ª 100 pF

R1 = R2 = R3 = R4 = 4.7 K

D1 & D2 & D3 & D4 = HSMS-282R

Figure 19. Schematic of Suppressed Harmonic Detector.

Both of these networks require a crossover or a three di‑ mensional circuit. A planar mixer can be made using the

SOT‑143 crossover quad, HSMS‑2829, as shown in Figure

22. In this product, a special lead frame permits the cross‑ over to be placed inside the plastic package itself, elimi‑ nating the need for via holes (or other measures) in the RF portion of the circuit itself.

HSMS-2829

LO in

RF in

HSMS-282R

4.7 K

4.7 K

V+

V–

IF out

100 pF

100 pF

Figure 22. Planar Double Balanced Mixer.

RF in

68

Figure 20. Layout of Suppressed Harmonic Detector.

Note that the forgoing discussion refers to the output volt‑ age being extracted at point V+ with respect to ground. If a differential output is taken at V+ with respect to V‑, the circuit acts as a voltage doubler.

Mixer applications

The HSMS‑282x family, with its wide variety of packaging, can be used to make excellent mixers at frequencies up to 6 GHz.

The HSMS‑2827 ring quad of matched diodes (in the

SOT‑143 package) has been designed for double balanced mixers. The smaller (SOT‑363) HSMS‑282R ring quad can similarly be used, if the quad is closed with external con‑ nections as shown in Figure 21.

A review of Figure 21 may lead to the question as to why the HSMS‑282R ring quad is open on the ends. Distortion in double balanced mixers can be reduced if LO drive is increased, up to the point where the Schottky diodes are driven into saturation. Above this point, increased LO drive will not result in improvements in distortion. The use of expensive high barrier diodes (such as those fabricated on GaAs) can take advantage of higher LO drive power, but a lower cost solution is to use a eight (or twelve) diode ring quad. The open design of the HSMS‑282R permits this to easily be done, as shown in Figure 23.

LO in

HSMS-282R

Figure 23. Low Distortion Double Balanced Mixer.

RF in

IF out

LO in

HSMS-282R

Figure 21. Double Balanced Mixer.

RF in

IF out

This same technique can be used in the single‑balanced mixer. Figure 24 shows such a mixer, with two diodes in each spot normally occupied by one. This mixer, with a sufficiently high LO drive level, will display low distortion.

RF in

HSMS-282R

180 hybrid

Low pass filter

IF out

LO in

Figure 24. Low Distortion Balanced Mixer.

Note 4. Alan Rixon and Raymond W. Waugh, “A Suppressed Harmonic Power Detector for Dual Band ‘Phones,” to be published.

8

Sampling Applications

The six lead HSMS‑282P can be used in a sampling circuit, as shown in Figure 25. As was the case with the six lead

HSMS‑282R in the mixer, the open bridge quad is closed with traces on the circuit board. The quad was not closed internally so that it could be used in other applications, such as illustrated in Figure 17.

sample point

HSMS-282P

Equation (1) would be straightforward to solve but for the fact that diode forward voltage is a function of tempera‑ ture as well as forward current. The equation for V f

is:

I f

11600 (V f

= I

S

e nT

– I f

R s

)

– 1 where n = ideality factor

T = temperature in °K

R s

= diode series resistance and I

S

(diode saturation current) is given by

sampling pulse sampling circuit

I s

= I

0

(

T

298

)

2 1 1 n – 4060

(

T – 298

)

e

Figure 25. Sampling Circuit.

Thermal Considerations

The obvious advantage of the SOT‑323 and SOT‑363 over the SOT‑23 and SOT‑142 is combination of smaller size and extra leads. However, the copper leadframe in the

SOT‑3x3 has a thermal conductivity four times higher than the Alloy 42 leadframe of the SOT‑23 and SOT‑143, which enables the smaller packages to dissipate more power.

The maximum junction temperature for these three fami‑ lies of Schottky diodes is 150°C under all operating condi‑ tions. The following equation applies to the thermal anal‑ ysis of diodes:

Tj = (V f

I f

+ P

RF

)

θ jc

+ T a

(1) where

T

T

θ j a

= junction temperature

= diode case temperature

V

P f jc

= thermal resistance

RF

I f

= DC power dissipated

= RF power dissipated

Note that sistances,

θ jc

, the thermal resistance from diode junction to the foot of the leads, is the sum of two component re‑

θ jc

= θ pkg

+ θ chip

(2)

Equation (4) is substituted into equation (3), and equa‑ tions (1) and (3) are solved simultaneously to obtain the value of junction temperature for given values of diode case temperature, DC power dissipation and RF power dissipation.

Package thermal resistance for the SOT‑3x3 package is ap‑ proximately 100°C/W, and the chip thermal resistance for the HSMS‑282x family of diodes is approximately 40°C/W.

The designer will have to add in the thermal resistance from diode case to ambient—a poor choice of circuit board material or heat sink design can make this number very high.

Note 5. Avago Application Note 1050, “Low Cost, Surface Mount Power Limiters.”

9

Diode Burnout

Any Schottky junction, be it an RF diode or the gate of a

MESFET, is relatively delicate and can be burned out with excessive RF power. Many crystal video receivers used in RFID (tag) applications find themselves in poorly con‑ trolled environments where high power sources may be present. Examples are the areas around airport and

FAA radars, nearby ham radio operators, the vicinity of a broadcast band transmitter, etc. In such environments, the Schottky diodes of the receiver can be protected by a device known as a limiter diode.

[5]

Formerly available only in radar warning receivers and other high cost electronic warfare applications, these diodes have been adapted to commercial and consumer circuits.

Avago offers a com plete line of surface mountable PIN limiter diodes. Most notably, our HSMP‑4820 (SOT‑23) can act as a very fast (nanosecond) power‑sensitive switch when placed between the antenna and the Schottky di‑ ode, shorting out the RF circuit temporarily and reflecting the excessive RF energy back out the antenna.

Assembly Instructions

SOT-3x3 PCB Footprint

Recommended PCB pad layouts for the miniature SOT‑

3x3 (SC‑70) packages are shown in Figures 26 and 27 (di‑ mensions are in inches). These layouts provide ample al‑ lowance for package placement by automated assembly equipment without adding parasitics that could impair the performance.

0.039

0.026

0.022

0.079

Dimensions in inches

Figure 26. Recommended PCB Pad Layout for Avago’s SC70 3L/SOT-323 Products.

0.026

0.079

0.039

0.018

Dimensions in inches

Figure 27. Recommended PCB Pad Layout for Avago's SC70 6L/SOT-363 Products.

10

SMT Assembly

Reliable assembly of surface mount components is a com‑ plex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the

SOT packages, will reach solder reflow temperatures faster than those with a greater mass.

Avago’s diodes have been qualified to the time‑tempera‑ ture profile shown in Figure 28. This profile is representa‑ tive of an IR reflow type of surface mount assembly pro‑ cess.

After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones.

The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to pro‑ duce a reflow of the solder.

The rates of change of temperature for the ramp‑up and cool‑down zones are chosen to be low enough to not cause deformation of the board or damage to compo‑ nents due to thermal shock. The maximum temperature in the reflow zone (T

MAX

) should not exceed 260°C.

These parameters are typical for a surface mount assem‑ bly process for Avago diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder.

tp

Tp

Ramp-up

Critical Zone

T

L

to Tp

T

L

Ts max

Ts min t

L ts

Preheat

Ramp-down

25 t 25

°

C to Peak

Time

Figure 28. Surface Mount Assembly Profile.

Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C)

Reflow Parameter

Average ramp-up rate (Liquidus Temperature (T

S(max)

to Peak)

Preheat Temperature Min (T

S(min)

)

Temperature Max (T

S(max)

)

Time (min to max) (t

S

)

Ts(max) to TL Ramp-up Rate

Lead-Free Assembly

3°C/ second max

150°C

200°C

60-180 seconds

3°C/second max

Time maintained above: Temperature (T

L

)

Time (t

L

)

217°C

60-150 seconds

Peak Temperature (T

P

)

Time within 5 °C of actual

Peak temperature (t

P

)

Ramp-down Rate

260 +0/-5°C

20-40 seconds

Time 25 °C to Peak Temperature

6°C/second max

8 minutes max

Note 1: All temperatures refer to topside of the package, measured on the package body surface

11

Package Dimensions

Outline 23 (SOT-23)

e2 e1

E e

XXX

D

B

A1

Notes:

XXX-package marking

Drawings are not to scale

E1

A

L

D

E1 e e1 e2

L

E

SYMBOL

A

A1

B

C

C

DIMENSIONS (mm)

2.73

1.15

0.89

1.78

0.45

2.10

0.45

MIN.

0.79

0.000

0.30

0.08

3.13

1.50

1.02

2.04

0.60

2.70

0.69

MAX.

1.20

0.100

0.54

0.20

Outline 143 (SOT-143)

e2 e1

B1

E

XXX

E1

A1 e

D

Notes:

XXX-package marking

Drawings are not to scale

B

A

L

C

SYMBOL

A

A1

B

B1

C

D

E1 e e1 e2

E

L

DIMENSIONS (mm)

MIN.

0.79

0.013

0.36

0.76

0.086

2.80

1.20

0.89

1.78

0.45

2.10

0.45

MAX.

1.097

0.10

0.54

0.92

0.152

3.06

1.40

1.02

2.04

0.60

2.65

0.69

Outline SOT-323 (SC-70 3 Lead)

e1

E e

XXX

D

B

A1

Notes:

XXX-package marking

Drawings are not to scale

E1

A e1

E

L

D

E1 e

SYMBOL

A

A1

B

C

L

C

DIMENSIONS (mm)

MIN.

0.80

0.00

0.15

0.08

1.80

1.10

0.65 typical

1.30 typical

2.25

1.40

1.80

0.26

2.40

0.46

MAX.

1.00

0.10

0.40

0.25

Outline SOT-363 (SC-70 6 Lead)

HE e

D

E e b

A2

A1

L c

SYMBOL

E

D

HE

A

DIMENSIONS (mm)

MIN.

1.15

1.80

1.80

0.80

0.80

0.00

0.650 BCS

1.00

0.10

0.15

0.08

0.10

0.30

0.25

0.46

MAX.

1.35

2.25

2.40

1.10

A1

A2

A b L c

12

Device Orientation

REEL

USER

FEED

DIRECTION

COVER TAPE

For Outline SOT-143

TOP VIEW

4 mm

8 mm

ABC ABC ABC

Note: "AB" represents package marking code.

"C" re presents date code.

ABC

CARRIER

TAPE

END VIEW

For Outlines SOT-23, -323

TOP VIEW

4 mm

END VIEW

8 mm

ABC ABC ABC ABC

Note: "AB" represents package marking code.

"C" represents date code.

For Outline SOT-363

TOP VIEW

4 mm

END VIEW

8 mm

ABC ABC ABC ABC

Note: "AB" represents package marking code.

"C" represents date code.

13

Tape Dimensions and Product Orientation

For Outline SOT-23

P

D

P

2

P

0

E t1

D

1

9° MAX

Ko

8° MAX

13.5° MAX

A

0

CAVITY

PERFORATION

CARRIER TAPE

DISTANCE

BETWEEN

CENTERLINE

DESCRIPTION

LENGTH

WIDTH

DEPTH

PITCH

BOTTOM HOLE DIAMETER

DIAMETER

PITCH

POSITION

WIDTH

THICKNESS

CAVITY TO PERFORATION

(WIDTH DIRECTION)

CAVITY TO PERFORATION

(LENGTH DIRECTION)

For Outline SOT-143

P

P

0

P

2

B

0

SYMBOL

K

P

A

B

D

1

0

0

0

D

P

E

0

W t1

F

P

2

SIZE (mm)

3.15 ± 0.10

2.77 ± 0.10

1.22 ± 0.10

4.00 ± 0.10

1.00 + 0.05

1.50 + 0.10

4.00 ± 0.10

1.75 ± 0.10

8.00 + 0.30 – 0.10

0.229 ± 0.013

3.50 ± 0.05

SIZE (INCHES)

0.124 ± 0.004

0.109 ± 0.004

0.048 ± 0.004

0.157 ± 0.004

0.039 ± 0.002

0.059 + 0.004

0.157 ± 0.004

0.069 ± 0.004

0.315 + 0.012 – 0.004

0.009 ± 0.0005

0.138 ± 0.002

2.00 ± 0.05

0.079 ± 0.002

D

E

F

W

D

1 t

1

9° M A X

A

0

CAVITY

PERFORATION

CARRIER TAPE

DISTANCE

DESCRIPTION

LENGTH

WIDTH

DEPTH

PITCH

BOTTOM HOLE DIAMETER

DIAMETER

PITCH

POSITION

WIDTH

THICKNESS

CAVITY TO PERFORATION

(WIDTH DIRECTION)

CAVITY TO PERFORATION

(LENGTH DIRECTION)

K

0

9 ° MAX

SYMBOL

D

P0

E

A0

B0

K0

P

D1

W t1

F

P2

B

0

SIZE (mm)

3.19 ± 0.10

2.80 ± 0.10

1.31 ± 0.10

4.00 ± 0.10

1.00 + 0.25

1.50 + 0.10

4.00 ± 0.10

1.75 ± 0.10

8.00 + 0.30 – 0.10

0.254 ± 0.013

3.50 ± 0.05

SIZE (INCHES)

0.126 ± 0.004

0.110 ± 0.004

0.052 ± 0.004

0.157 ± 0.004

0.039 + 0.010

0.059 + 0.004

0.157 ± 0.004

0.069 ± 0.004

0.315+ 0.012 – 0.004

0.0100 ± 0.0005

0.138 ± 0.002

2.00 ± 0.05

0.079 ± 0.002

F

W

14

Tape Dimensions and Product Orientation

For Outlines SOT-323, -363

P

P

0

D

P

2

E

F

W

C t

1

(CARRIER TAPE THICKNESS)

An

A

0

CAVITY

PERFORATION

CARRIER TAPE

COVER TAPE

DISTANCE

ANGLE

DESCRIPTION

LENGTH

WIDTH

DEPTH

PITCH

BOTTOM HOLE DIAMETER

DIAMETER

PITCH

POSITION

WIDTH

THICKNESS

WIDTH

TAPE THICKNESS

CAVITY TO PERFORATION

(WIDTH DIRECTION)

CAVITY TO PERFORATION

(LENGTH DIRECTION)

FOR SOT-323 (SC70-3 LEAD)

FOR SOT-363 (SC70-6 LEAD)

SYMBOL

A

0

B

0

K

0

P

D

1

D

P

E

0

C

T t

F t

W

1

P

2

An 8 °C MAX

10 °C MAX

SIZE (mm)

2.40 ± 0.10

2.40 ± 0.10

1.20 ± 0.10

4.00 ± 0.10

1.00 + 0.25

1.55 ± 0.05

4.00 ± 0.10

1.75 ± 0.10

8.00 ± 0.30

0.254 ± 0.02

5.4 ± 0.10

0.062 ± 0.001

3.50 ± 0.05

2.00 ± 0.05

SIZE (INCHES)

0.094 ± 0.004

0.094 ± 0.004

0.047 ± 0.004

0.157 ± 0.004

0.039 + 0.010

0.061 ± 0.002

0.157 ± 0.004

0.069 ± 0.004

0.315 ± 0.012

0.0100 ± 0.0008

0.205 ± 0.004

0.0025 ± 0.00004

0.138 ± 0.002

0.079 ± 0.002

K

0

D

1

B

0

An

T t

(COVER TAPE THICKNESS)

Part Number Ordering Information

Part Number

HSMS‑282x‑TR2G

HSMS‑282x‑TR1G

HSMS‑282x‑BLK G

No. of Devices Container

10000 13" Reel

3000

100

7" Reel antistatic bag x = 0, 2, 3, 4, 5, 7, 8, 9, B, C, E, F, K, L, M, N, P or R

For product information and a complete list of distributors, please go to our web site:

www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.

Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved. Obsoletes 5989-4030EN

AV02-1320EN - November 26, 2014

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