Features •

Features •

Features

High Performance, Low Power AVR

®

32 32-Bit Microcontroller

– 210 DMIPS throughput at 150 MHz

– 16 KB instruction cache and 16 KB data caches

– Memory Management Unit enabling use of operating systems

– Single-cycle RISC instruction set including SIMD and DSP instructions

– Java Hardware Acceleration

Pixel Co-Processor

– Pixel Co-Processor for video acceleration through color-space conversion

(YUV<->RGB), image scaling and filtering, quarter pixel motion compensation

Multi-hierarchy bus system

– High-performance data transfers on separate buses for increased performance

Data Memories

– 32KBytes SRAM

External Memory Interface

– SDRAM, DataFlash

, SRAM, Multi Media Card (MMC), Secure Digital (SD),

– Compact Flash, Smart Media, NAND Flash

Direct Memory Access Controller

– External Memory access without CPU intervention

Interrupt Controller

– Individually maskable Interrupts

– Each interrupt request has a programmable priority and autovector address

System Functions

– Power and Clock Manager

– Crystal Oscillator with Phase-Lock-Loop (PLL)

– Watchdog Timer

– Real-time Clock

6 Multifunction timer/counters

– Three external clock inputs, I/O pins, PWM, capture and various counting capabilities

4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– 115.2 kbps IrDA Modulation and Demodulation

– Hardware and software handshaking

3 Synchronous Serial Protocol controllers

– Supports I2S, SPI and generic frame-based protocols

Two-Wire Interface

– Sequential Read/Write Operations, Philips’ I2C© compatible

Image Sensor Interface

– 12-bit Data Interface for CMOS cameras

Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device

– On-chip Transceivers with physical interface

16-bit stereo audio bitstream DAC

– Sample rates up to 50 kHz

On-Chip Debug System

– Nexus Class 3

– Full speed, non-intrusive data and program trace

– Runtime control and JTAG interface

Package/Pins

– AT32AP7001: 208-pin QFP/ 90 GPIO pins

Power supplies

– 1.65V to1.95V VDDCORE

– 3.0V to 3.6V VDDIO

AVR

®

32 32-bit

Microcontroller

AT32AP7001

Preliminary

32015D-AVR32-10/07

AT32AP7001

1.

Part Description

The AT32AP7001 is a complete System-on-chip application processor with an AVR32 RISC processor achieving 210 DMIPS running at 150 MHz. AVR32 is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high application performance.

AT32AP7001 implements a Memory Management Unit (MMU) and a flexible interrupt controller supporting modern operating systems and real-time operating systems. The processor also includes a rich set of DSP and SIMD instructions, specially designed for multimedia and telecom applications.

AT32AP7001 incorporates SRAM memories on-chip for fast and secure access. For applications requiring additional memory, external 16-bit SRAM is accessible. Additionally, an SDRAM controller provides off-chip volatile memory access as well as controllers for all industry standard off-chip non-volatile memories, like Compact Flash, Multi Media Card (MMC), Secure Digital

(SD)-card, SmartCard, NAND Flash and Atmel DataFlash™.

The Direct Memory Access controller for all the serial peripherals enables data transfer between memories without processor intervention. This reduces the processor overhead when transferring continuous and large data streams between modules in the MCU.

The Timer/Counters includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.

A pixel co-processor provides color space conversions for images and video, in addition to a wide variety of hardware filter support

Synchronous Serial Controllers provide easy access to serial communication protocols, audio standards like I2S and frame-based protocols.

The Java hardware acceleration implementation in AVR32 allows for a very high-speed Java byte-code execution. AVR32 implements Java instructions in hardware, reusing the existing

RISC data path, which allows for a near-zero hardware overhead and cost with a very high performance.

The Image Sensor Interface supports cameras with up to 12-bit data buses.

PS2 connectivity is provided for standard input devices like mice and keyboards.

AT32AP7001 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control.

The C-compiler is closely linked to the architecture and is able to utilize code optimization features, both for size and speed.

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32015D–AVR32–10/07

AT32AP7001

2.

Signals Description

AVDDPLL

AVDDUSB

AVDDOSC

VDDCORE

VDDIO

AGNDPLL

AGNDUSB

AGNDOSC

GND

Table 2-1.

Signal Name

The following table gives details on the signal name classified by peripheral. The pinout multiplexing of these signals is given in the Peripheral Muxing table in the Peripherals chapter.

Signal Description List

Function Type

Active

Level Comments

Power

PLL Power Supply

USB Power Supply

Oscillator Power Supply

Core Power Supply

I/O Power Supply

PLL Ground

USB Ground

Oscillator Ground

Ground

Crystal 0, 1, 32 Input

Power

Power

Power

Power

Power

Ground

Ground

Ground

Ground

Clocks, Oscillators, and PLL’s

Analog XIN0, XIN1, XIN32

XOUT0, XOUT1,

XOUT32

PLL0, PLL1

Crystal 0, 1, 32 Output

PLL 0,1 Filter Pin

Analog

1.65 to 1.95 V

1.65 to 1.95 V

1.65 to 1.95 V

1.65 to 1.95 V

3.0 to 3.6V

TCK

TDI

TDO

TMS

TRST_N

MCKO

MDO0 - MDO5

MSEO0 - MSEO1

EVTI_N

Test Clock

Test Data In

Test Data Out

Test Mode Select

Test Reset

Trace Data Output Clock

Trace Data Output

Trace Frame Control

Event In

Analog

JTAG

Input

Input

Output

Input

Input

Auxiliary Port - AUX

Output

Output

Output

Input

Low

Low

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32015D–AVR32–10/07

AT32AP7001

Table 2-1.

Signal Description List

Signal Name

EVTO_N

Function

Event Out

Type

Output

GCLK0 - GCLK4

OSCEN_N

RESET_N

WAKE_N

Generic Clock Pins

Oscillator Enable

Reset Pin

Wake Pin

Power Manager - PM

Output

Input

Input

Input

External Interrupt Controller - EIC

EXTINT0 - EXTINT3 External Interrupt Pins

NMI_N Non-Maskable Interrupt Pin

Input

Input

Active

Level

Low

Comments

Low

Low

Low

Low

SCLK

SDI

SDO

SYNC

DATA0 - DATA1

DATAN0 - DATAN1

PX0 - PX53

ADDR0 - ADDR25

CAS

CFCE1

CFCE2

CFRNW

DATA0 - DATA31

NANDOE

NANDWE

NCS0 - NCS5

AC97 Clock Signal

AC97 Receive Signal

AC97 Transmit Signal

AC97 Controller - AC97C

Input

Output

Output

AC97 Frame Synchronization Signal Input

Audio Bitstream DAC - ABDAC

D/A Data Out

D/A Inverted Data Out

Output

Output

I/O Controlled by EBI

Address Bus

Column Signal

Compact Flash 1 Chip Enable

Compact Flash 2 Chip Enable

Compact Flash Read Not Write

Data Bus

External Bus Interface - EBI

I/O

Output

Output

Output

Output

Output

I/O

NAND Flash Output Enable

NAND Flash Write Enable

Chip Select

Output

Output

Output

Low

Low

Low

Low

Low

Low

4

32015D–AVR32–10/07

AT32AP7001

Signal Name

NRD

NWAIT

NWE0

NWE1

NWE3

RAS

SDA10

SDCK

SDCKE

SDWE

Table 2-1.

CLK

CMD0 - CMD1

DATA0 - DATA7

PA0 - PA31

PB0 - PB30

PD0 - PD17

PE0 - PE26

Signal Description List

DATA0 - DATA11

HSYNC

PCLK

VSYNC

CLOCK0 - CLOCK1

DATA0 - DATA1

Function

Read Signal

External Wait Signal

Write Enable 0

Write Enable 1

Write Enable 3

Row Signal

SDRAM Address 10 Line

SDRAM Clock

SDRAM Clock Enable

SDRAM Write Enable

Output

Output

Output

Output

Output

Image Sensor Interface - ISI

Image Sensor Data

Horizontal Synchronization

Image Sensor Data Clock

Vertical Synchronization

Input

Input

Input

Input

Type

Output

Input

Output

Output

Output

Low

Multimedia Card Clock

MultiMedia Card Interface - MCI

Output

Multimedia Card Command

Multimedia Card Data

I/O

I/O

Parallel Input/Output - PIOA, PIOB, PIOC, PIOD, PIOE

Parallel I/O Controller PIOA I/O

Parallel I/O Controller PIOB

Parallel I/O Controller PIOD

Parallel I/O Controller PIOE

I/O

I/O

I/O

PS2 Interface - PSIF

PS2 Clock

PS2 Data

Input

I/O

Serial Peripheral Interface - SPI0, SPI1

Active

Level

Low

Comments

Low

Low

Low

Low

Low

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32015D–AVR32–10/07

AT32AP7001

Table 2-1.

Signal Name

MISO

MOSI

NPCS0 - NPCS3

SCK

Signal Description List

Function

Master In Slave Out

Type

I/O

Active

Level

Master Out Slave In

SPI Peripheral Chip Select

Clock

I/O

I/O Low

Output

Synchronous Serial Controller - SSC0, SSC1, SSC2

Comments

A0

A1

A2

B0

B1

B2

CLK0

CLK1

CLK2

RX_CLOCK

RX_DATA

RX_FRAME_SYNC

TX_CLOCK

SSC Receive Clock

SSC Receive Data

SSC Receive Frame Sync

SSC Transmit Clock

I/O

Input

I/O

I/O

TX_DATA

TX_FRAME_SYNC

DMARQ0 - DMARQ3

SSC Transmit Data

SSC Transmit Frame Sync

DMA Requests

Output

I/O

DMA Controller - DMACA

Input

Channel 0 Line A

Channel 1 Line A

Channel 2 Line A

Timer/Counter - TIMER0, TIMER1

I/O

I/O

I/O

Channel 0 Line B

Channel 1 Line B

Channel 2 Line B

Channel 0 External Clock Input

I/O

I/O

I/O

Input

SCL

SDA

CLK

Channel 1 External Clock Input

Channel 2 External Clock Input

Serial Clock

Input

Input

Two-wire Interface - TWI

I/O

Serial Data I/O

Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3

Clock I/O

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32015D–AVR32–10/07

AT32AP7001

Table 2-1.

Signal Description List

Signal Name

CTS

RTS

RXD

TXD

PWM0 - PWM3

HSDM

FSDM

HSDP

FSDP

Function

Clear To Send

Request To Send

Receive Data

Transmit Data

Type

Input

Output

Input

Output

Pulse Width Modulator - PWM

PWM Output Pins Output

USB Interface - USBA

High Speed USB Interface Data -

Full Speed USB Interface Data -

Analog

Analog

High Speed USB Interface Data +

Full Speed USB Interface Data +

Analog

Analog

Active

Level Comments

VBG USB bandgap Analog

Connected to a 6810 Ohm ± 0.5% resistor to gound and a 10 pF capacitor to ground.

7

32015D–AVR32–10/07

AT32AP7001

3.

Power Considerations

3.1

Power Supplies

The AT32AP7001 has several types of power supply pins:

VDDCORE pins: Power the core, memories, and peripherals. Voltage is 1.8V nominal.

VDDIO pins: Power I/O lines. Voltage is 3.3V nominal.

VDDPLL pin: Powers the PLL. Voltage is 1.8V nominal.

VDDUSB pin: Powers the USB. Voltage is 1.8V nominal.

VDDOSC pin: Powers the oscillators. Voltage is 1.8V nominal.

The ground pins GND are common to VDDCORE and VDDIO. The ground pin for VDDPLL is

GNDPLL, and the GND pin for VDDOSC is GNDOSC.

See ”Electrical Characteristics” on page 789 for power consumption on the various supply pins.

3.2

Power Supply Connections

Special considerations should be made when connecting the power and ground pins on a PCB.

Figure 3-1 shows how this should be done.

Figure 3-1.

Connecting analog power supplies

C54

0.10u

AVDDUSB

AVDDPLL

AVDDOSC

AGNDUSB

AGNDPLL

AGNDOSC

C56

0.10u

C55

0.10u

3.3uH

VDDCORE

VCC_1V8

8

32015D–AVR32–10/07

AT32AP7001

4.

Package and Pinout

4.1

AVR32AP7001

Figure 4-1.

208 QFP Pinout.

157

156 105

104

208

1

PE18

PX47

PX48

PX49

PX50

PX51

VDDIO

PX32

PX33

PX00

PX01

PX02

PX03

PX04

PX05

VDDCORE

GND

TDO

TCK

Table 4-1.

1

2

GND

PE17

QFP-208 Package Pinout

53

54

GND

PA23

15

16

17

18

11

12

13

14

19

20

21

7

8

9

10

5

6

3

4

67

68

69

70

63

64

65

66

71

72

73

59

60

61

62

55

56

57

58

PA24

XIN1

XOUT1

AVDDUSB

AGNDUSB

VDDIO

FSDM

FSDP

GND

GND

HSDM

HSDP

VDDCORE

GND

GND

VBG

VDDIO

PA25

PA26

52

PX36

PX37

PX38

PX18

PX19

PX20

PX21

PX22

GND

PX13

PX14

PX15

PX16

PX17

PX34

PX35

PX23

PX24

PX25

PX26

VDDIO

117

118

119

120

113

114

115

116

121

122

123

124

125

109

110

111

112

105

106

107

108

53

GND

PB10

PB11

PB12

PB13

PB14

PB15

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

VDDCORE

GND

GND

PA06

PA07

VDDIO

169

170

171

172

165

166

167

168

173

174

175

176

177

161

162

163

164

157

158

159

160

32015D–AVR32–10/07

9

PA10

PA11

PA12

PA13

PA14

PA15

PA16

PA17

PA18

PA19

PA20

PA21

PA22

VDDIO

PA04

PA05

PB24

PB25

PA08

VDDIO

GND

PA09

TDI

TRST_N

EVTI_N

RESET_N

PA00

PA01

PA02

PA03

Table 4-1.

22 TMS

QFP-208 Package Pinout (Continued)

74 PA27

47

48

49

50

51

52

43

44

45

46

39

40

41

42

35

36

37

38

31

32

33

34

27

28

29

30

23

24

25

26

99

100

101

102

103

104

95

96

97

98

91

92

93

94

87

88

89

90

83

84

85

86

79

80

81

82

75

76

77

78

PE21

PE20

PE19

PX06

PX07

PX08

PX09

PX10

PX11

PB29

PB30

PX12

PC00

VDDIO

PX53

PX52

PX41

GND

PE25

PE24

PE23

PE22

PA28

PA29

PA30

PA31

WAKE_N

PB26

PB27

PB28

PB05

PB06

PB07

PB08

PB09

PC16

PC17

VDDIO

PX44

PX45

PX46

PB00

PB01

PB02

PB03

PB04

PX27

PX28

PX29

PX30

PX31

VDDCORE

GND

GND

PE26

PX39

VDDCORE

GND

PX40

PX42

PX43

153

154

155

156

149

150

151

152

145

146

147

148

141

142

143

144

137

138

139

140

133

134

135

136

126

127

128

129

130

131

132

AT32AP7001

PE03

PE04

PE05

PE06

PE07

PE08

PE09

PE10

PE11

PE12

PE13

PE14

PE15

PE16

No Connect

GND

VDDIO

OSCEN_N

XIN32

XOUT32

AGNDOSC

AVDDOSC

PLL1

XIN0

XOUT0

AGNDPLL

AVDDPLL

PLL0

PE00

PE01

PE02

205

206

207

208

201

202

203

204

197

198

199

200

193

194

195

196

189

190

191

192

185

186

187

188

178

179

180

181

182

183

184

10

32015D–AVR32–10/07

AT32AP7001

5.

Blockdiagram

Figure 5-1.

Blockdiagram

PA

PB

PC

PD

PE

D+

D-

TRST_N

TCK

TDO

TDI

TMS

JTAG

INTERFACE

EVTI_N

MCKO

MDO[5..0]

MSEO[1..0]

EVTO_N

DATA[11..0]

HSYNC

VSYNC

PCLK

USB

INTERFACE

DMA

IMAGE

SENSOR

INTERFACE

INTRAM0

INTRAM1

DATA0

DATA1

DATA0N

DATA1N

CLK

CMD

DATA[7..0]

SCLK

SDI

SSYNC

SDO

NEXUS

CLASS 3

OCD

AP CPU

MEMORY MANAGEMENT UNIT

INSTR

CACHE

DATA

CACHE

PIXEL COPROCESSOR

S

M

M

M M

M

HIGH SPEED

BUS MATRIX

S

S

S M M S S M

PB HSB

HSB-PB

BRIDGE

B

CONFIGURATION REGISTERS BUS

HSB

HSB-PB

BRIDGE A

PB

HSB-HSB BRIDGE

PERIPHERAL

DMA

CONTROLLER

DMA CONTROLLER

AUDIO BITSTREAM

DAC

MULTIMEDIA CARD

INTERFACE

AC97 CONTROLLER

USART0

USART1

USART2

USART3

NWAIT

NCS[5,4,2]

CFRNW,

CFCE1,

CFCE2,

ADDR[23..25]

DATA[31..16]

RXD

TXD

CLK

RTS, CTS

SERIAL

PERIPHERAL

INTERFACE 0/1

SCK

MISO, MOSI

NPCS0

NPCS[3..1]

SYNCHRONOUS

SERIAL

CONTROLLER 0/1/2

TX_CLOCK, TX_FRAME_SYNC

TX_DATA

RX_CLOCK, RX_FRAME_SYNC

RX_DATA

RAS,

CAS,

SDWE,

NANDOE,

NANDWE,

SDCK,

SDCKE,

NWE3,

NWE1,

NWE0,

NRD,

NCS[3,1,0],

ADDR[22..0]

DATA[15..0]

POWER

MANAGER

TWO-WIRE

INTERFACE

SCL

SDA

XIN32

XOUT32

32 KHz

OSC

XIN0

XOUT0

XIN1

XOUT1

PLL0

OSC0

OSC1

PLL0

PLL1

PLL1

OSCEN_N

RESET_N

GCLK[3..0]

CLOCK

GENERATOR

CLOCK

CONTROLLER

SLEEP

CONTROLLER

RESET

CONTROLLER

PS2 INTERFACE

REAL TIME

COUNTER

WATCHDOG

TIMER

CLOCK[1..0]

DATA[1..0]

A[2..0]

B[2..0]

CLK[2..0]

TIMER/COUNTER 0/1

INTERRUPT

CONTROLLER

EXTINT[7..0]

KPS[7..0]

NMI_N

EXTERNAL

INTERRUPT

CONTROLLER

PULSE WIDTH

MODULATION

CONTROLLER

PWM0

PWM1

PWM2

PWM3

PA

PB

PC

PD

PE

11

32015D–AVR32–10/07

AT32AP7001

5.0.1

AVR32AP CPU

32-bit load/store AVR32B RISC architecture.

– Up to 15 general-purpose 32-bit registers.

– 32-bit Stack Pointer, Program Counter and Link Register reside in register file.

– Fully orthogonal instruction set.

– Privileged and unprivileged modes enabling efficient and secure Operating Systems.

– Innovative instruction set together with variable instruction length ensuring industry leading code density.

– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.

– SIMD extention for media applications.

7 stage pipeline allows one instruction per clock cycle for most instructions.

– Java Hardware Acceleration.

– Byte, half-word, word and double word memory access.

– Unaligned memory access.

– Shadowed interrupt context for INT3 and multiple interrupt priority levels.

– Dynamic branch prediction and return address stack for fast change-of-flow.

– Coprocessor interface.

Full MMU allows for operating systems with memory protection.

16Kbyte Instruction and 16Kbyte data caches.

– Virtually indexed, physically tagged.

– 4-way associative.

– Write-through or write-back.

Nexus Class 3 On-Chip Debug system.

– Low-cost NanoTrace supported.

5.0.2

Pixel Coprocessor (PICO)

Coprocessor coupled to the AVR32 CPU Core through the TCB Bus.

– Coprocessor number one on the TCB bus.

Three parallel Vector Multiplication Units (VMU) where each unit can:

– Multiply three pixel components with three coefficients.

– Add the products from the multiplications together.

– Accumulate the result or add an offset to the sum of the products.

Can be used for accelerating:

– Image Color Space Conversion.

• Configurable Conversion Coefficients.

• Supports packed and planar input and output formats.

• Supports subsampled input color spaces (i.e 4:2:2, 4:2:0).

– Image filtering/scaling.

• Configurable Filter Coefficients.

• Throughput of one sample per cycle for a 9-tap FIR filter.

• Can use the built-in accumulator to extend the FIR filter to more than 9-taps.

• Can be used for bilinear/bicubic interpolations.

– MPEG-4/H.264 Quarter Pixel Motion Compensation.

Flexible input Pixel Selector.

– Can operate on numerous different image storage formats.

Flexible Output Pixel Inserter.

– Scales and saturates the results back to 8-bit pixel values.

– Supports packed and planar output formats.

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32015D–AVR32–10/07

AT32AP7001

Configurable coefficients with flexible fixed-point representation.

5.0.3

Debug and Test system

IEEE1149.1 compliant JTAG and boundary scan

Direct memory access and programming capabilities through JTAG interface

Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 3

Auxiliary port for high-speed trace information

Hardware support for 6 Program and 2 data breakpoints

Unlimited number of software breakpoints supported

Advanced Program, Data, Ownership, and Watchpoint trace supported

5.0.4

DMA Controller

2 HSB Master Interfaces

3 Channels

Software and Hardware Handshaking Interfaces

– 11 Hardware Handshaking Interfaces

Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer

Single-block DMA Transfer

Multi-block DMA Transfer

– Linked Lists

– Auto-Reloading

– Contiguous Blocks

DMA Controller is Always the Flow Controller

Additional Features

– Scatter and Gather Operations

– Channel Locking

Bus Locking

FIFO Mode

– Pseudo Fly-by Operation

5.0.5

Peripheral DMA Controller

Transfers from/to peripheral to/from any memory space without intervention of the processor.

Next Pointer Support, forbids strong real-time constraints on buffer management.

Eighteen channels

– Two for each USART

– Two for each Serial Synchronous Controller

– Two for each Serial Peripheral Interface

5.0.6

Bus system

HSB bus matrix with 10 Masters and 8 Slaves handled

– Handles Requests from the CPU Icache, CPU Dcache, HSB bridge, HISI, USB 2.0 Controller,

DMA Controller 0, DMA Controller 1, and to internal SRAM 0, internal SRAM 1, PB A, PB B,

EBI and, USB.

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32015D–AVR32–10/07

AT32AP7001

– Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master)

– Burst Breaking with Slot Cycle Limit

– One Address Decoder Provided per Master

2 Peripheral buses allowing each bus to run on different bus speeds.

– PB A intended to run on low clock speeds, with peripherals connected to the PDC.

– PB B intended to run on higher clock speeds, with peripherals connected to the DMACA.

HSB-HSB Bridge providing a low-speed HSB bus running at the same speed as PBA

– Allows PDC transfers between a low-speed PB bus and a bus matrix of higher clock speeds

An overview of the bus system is given in Figure 4-1 on page 13 . All modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the

Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the HSB bus, and which DMA controller is connected to which peripheral.

32015D–AVR32–10/07

14

AT32AP7001

6.

I/O Line Considerations

6.1

JTAG pins

6.2

WAKE_N pin

6.3

RESET_N pin

The WAKE_N pin is a schmitt trigger input integrating a permanent pull-up resistor to VDDIO.

The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product.

6.4

EVTI_N pin

The TMS, TDI and TCK pins have pull-up resistors. TDO is an output, driven at up to VDDIO, and have no pull-up resistor. The TRST_N pin is used to initialize the embedded JTAG TAP

Controller when asserted at a low level. It is a schmitt input and integrates permanent pull-up resistor to VDDIO, so that it can be left unconnected for normal operations.

The EVTI_N pin is a schmitt input and integrates a non-programmable pull-up resistor to VDDIO.

6.5

TWI pins

When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the pins have the same characteristics as PIO pins.

6.6

PIO pins

All the I/O lines integrate a programmable pull-up resistor

.

Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, I/O lines default as inputs with pull-up resistors enabled, except when indicated otherwise in the column

“Reset State” of the PIO Controller multiplexing tables.

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7.

AVR32 AP CPU

Rev.: 1.0.0.0

This chapter gives an overview of the AVR32 AP CPU. AVR32 AP is an implementation of the

AVR32 architecture. A summary of the programming model, instruction set, caches and MMU is presented. For further details, see the AVR32 Architecture Manual and the AVR32 AP Technical

Reference Manual.

7.1

AVR32 Architecture

AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for costsensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.

Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and half-word data types without penalty in code size and performance.

Memory load and store operations are provided for byte, half-word, word and double word data with automatic sign- or zero extension of half-word and byte data.

In order to reduce code size to a minimum, some instructions have multiple addressing modes.

As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution.

The register file is organized as sixteen 32-bit registers and includes the Program Counter, the

Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions.

7.2

The AVR32 AP CPU

AVR32 AP targets high-performance applications, and provides an advanced OCD system, effi-

cient data and instruction caches, and a full MMU. Figure 7-1 on page 17 displays the contents

of AVR32 AP.

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Figure 7-1.

Overview of the AVR32 AP CPU

OCD system

JTAG control

Reset control

Tightly Coupled Bus BTB RAM interface

AVR32 CPU pipeline with Java accelerator

MMU

Cache RAM interface

Dcache controller

HSB master

Icache controller

Cache RAM interface

HSB master

7.2.1

Pipeline Overview

AVR32 AP is a pipelined processor with seven pipeline stages. The pipeline has three subpipes, namely the Multiply pipe, the Execute pipe and the Data pipe. These pipelines may execute different instructions in parallel. Instructions are issued in order, but may complete out of order

(OOO) since the subpipes may be stalled individually, and certain operations may use a subpipe for several clock cycles.

Figure 7-2 on page 18

shows an overview of the AVR32 AP pipeline stages.

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Figure 7-2.

The AVR32 AP Pipeline

IF1 IF2

Prefetch unit

ID IS

Decode unit

M1 M2 Multiply pipe

A1

DA

A2

D

WB ALU pipe

Load-store pipe

7.2.2

7.2.3

7.2.4

.The follwing abbreviations are used in the figure:

• IF1, IF2 - Instruction Fetch stage 1 and 2

• ID - Instruction Decode

• IS - Instruction Issue

• A1, A2 - ALU stage 1 and 2

• M1, M2 - Multiply stage 1 and 2

• DA - Data Address calculation stage

• D - Data cache access

• WB - Writeback

AVR32B Microarchitecture Compliance

AVR32 AP implements an AVR32B microarchitecture. The AVR32B microarchitecture is targeted at applications where interrupt latency is important. The AVR32B therefore implements dedicated registers to hold the status register and return address for interrupts, exceptions and supervisor calls. This information does not need to be written to the stack, and latency is therefore reduced. Additionally, AVR32B allows hardware shadowing of the registers in the register file.

The scall, rete and rets instructions use the dedicated return status registers and return address registers in their operation. No stack accesses are performed by these instructions.

Java Support

AVR32 AP provides Java hardware acceleration in the form of a Java Virtual Machine hardware implementation. Refer to the AVR32 Java Technical Reference Manual for details.

Memory management

AVR32 AP implements a full MMU as specified by the AVR32 architecture. The page sizes provided are 1K, 4K, 64K and 1M. A 32-entry fully-associative common TLB is implemented, as well as a 4-entry micro-ITLB and 8-entry micro-DTLB. Instruction and data accesses perform lookups in the micro-TLBs. If the access misses in the micro-TLBs, an access in the common TLB is performed. If this access misses, a page miss exception is issued.

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7.2.5

7.2.6

Caches and write buffer

AVR32 AP implements 16K data and 16K instruction caches. The caches are 4-way set associative. Each cache has a 32-bit System Bus master interface connecting it to the bus. The instruction cache has a 32-bit interface to the fetch pipeline stage, and the data cache has a 64bit interface to the load-store pipeline. The caches use a least recently used allocate-on-readmiss replacement policy. The caches are virtually tagged, physically indexed, avoiding the need to flush them on task switch.

The caches provide locking on a per-line basis, allowing code and data to be permanently locked in the caches for timing-critical code. The data cache also allows prefetching of data using the pref instruction.

Accesses to the instruction and data caches are tagged as cacheable or uncacheable on a perpage basis by the MMU. Data cache writes are tagged as write-through or writeback on a perpage basis by the MMU.

The data cache has a 32-byte combining write buffer, to avoid stalling the CPU when writing to external memory. Writes are tagged as bufferable or unbufferable on a per-page basis by the

MMU. Bufferable writes to sequential addresses are placed in the buffer, allowing for example a sequence of byte writes from the CPU to be combined into word transfers on the bus. A sync instruction is provided to explicitly flush the write buffer.

Unaligned reference handling

AVR32 AP has hardware support for performing unaligned memory accesses. This will reduce the memory footprint needed by some applications, as well as speed up other applications operating on unaligned data.

AVR32 AP is able to perform certain word-sized load and store instructions of any alignment, and word-aligned st.d and ld.d. Any other unaligned memory access will cause an MMU address exception. All coprocessor memory access instructions require word-aligned pointers. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two wordsized accesses.

The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Accessing an unaligned address may require several clock cycles, refer to the AVR32 AP Technical Reference Manual for details.

Table 7-1.

Instruction

ld.w

Instructions with unaligned reference support

Supported alignment

Any st.w

lddsp lddpc stdsp

Any

Any

Any

Any ld.d

st.d

Word

Word

All coprocessor memory access instruction Word

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7.2.7

7.2.8

Unimplemented instructions

The following instructions are unimplemented in AVR32 AP, and will cause an Unimplemented

Instruction Exception if executed:

• mems

• memc

• memt

Exceptions and Interrupts

AVR32 AP incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a well-defined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class. Each priority class has dedicated registers to keep the return address and status register thereby removing the need to perform time-consuming memory operations to save this information.

There are four levels of external interrupt requests, all executing in their own context. The INT3 context provides dedicated shadow registers ensuring low latency for these interrupts. An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU.

The addresses and priority of simultaneous events are shown in

Table 7-2 on page 21

.

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Table 7-2.

Priority and handler addresses for events

Priority Handler Address Name

21

22

23

24

17

18

19

20

25

26

27

28

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

EVBA+0x24

EVBA+0x28

EVBA+0x2C

EVBA+0x30

EVBA+0x100

EVBA+0x34

EVBA+0x38

EVBA+0x60

EVBA+0x70

EVBA+0x3C

EVBA+0x40

EVBA+0x44

0xA000_0000

Provided by OCD system

EVBA+0x00

EVBA+0x04

EVBA+0x08

EVBA+0x0C

EVBA+0x10

Autovectored

Autovectored

Autovectored

Autovectored

EVBA+0x14

EVBA+0x50

EVBA+0x18

EVBA+0x1C

EVBA+0x20

Reset

OCD Stop CPU

Unrecoverable exception

TLB multiple hit

Bus error data fetch

Bus error instruction fetch

NMI

Interrupt 3 request

Interrupt 2 request

Interrupt 1 request

Interrupt 0 request

Instruction Address

ITLB Miss

ITLB Protection

Breakpoint

Illegal Opcode

Unimplemented instruction

Privilege violation

Floating-point

Coprocessor absent

Supervisor call

Data Address (Read)

Data Address (Write)

DTLB Miss (Read)

DTLB Miss (Write)

DTLB Protection (Read)

DTLB Protection (Write)

DTLB Modified

DTLB

DTLB

DTLB

DTLB

DTLB

DTLB

OCD system

Instruction

Instruction

Instruction

FP Hardware

Instruction

Instruction

DTLB

Event source

External input

OCD system

Internal

Internal signal

Data bus

Data bus

External input

External input

External input

External input

External input

ITLB

ITLB

ITLB

Stored Return Address

Undefined

First non-completed instruction

PC of offending instruction

PC of offending instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

First non-completed instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

First non-completed instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC(Supervisor Call) +2

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

PC of offending instruction

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7.3

Programming Model

7.3.1

Register file configuration

The AVR32B architecture specifies that the exception contexts may have a different number of shadowed registers in different implementations.

Figure 7-3 on page 22

shows the model used in AVR32 AP.

Figure 7-3.

The AVR32 AP Register File

Application

Supervisor INT0 INT1

Bit 31 Bit 0

PC

LR

SP_APP

R12

R11

R10

R9

R8

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

INT2

Bit 31

Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

R7

R6

INT3

Bit 31 Bit 0

PC

LR_INT3

SP_SYS

R12_INT3

R11_INT3

R10_INT3

R9_INT3

R8_INT3

R7

R6

Exception

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

NMI

Bit 31 Bit 0

PC

LR

SP_SYS

R12

R11

R10

R9

R8

R3

R2

R1

R0

SR

R3

R2

R1

R0

SR

RSR_SUP

RAR_SUP

R3

R2

R1

R0

SR

RSR_INT0

RAR_INT0

R3

R2

R1

R0

SR

RSR_INT1

RAR_INT1

R3

R2

R1

R0

SR

RSR_INT2

RAR_INT2

R3

R2

R1

R0

SR

RSR_INT3

RAR_INT3

R3

R2

R1

R0

SR

RSR_EX

RAR_EX

R3

R2

R1

R0

SR

RSR_NMI

RAR_NMI

7.3.2

Status register configuration

The Status Register (SR) is splitted into two halfwords, one upper and one lower, see

Figure 7-4 on page 22 and

Figure 7-5 on page 23 . The lower word contains the C, Z, N, V and Q condition

code flags and the R, T and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.

Figure 7-4.

The Status Register High Halfword

Bit 31

-

0

LC

-

1

0

H

0

J

0

DM D

0 0

M2 M1

0 0 0

M0 EM I3M I1M

1 1 0 0 0 0

Bit 16

I0M GM

1

Bit name

Initial value

Global Interrupt Mask

Interrupt Level 0 Mask

Interrupt Level 1 Mask

Interrupt Level 2 Mask

Interrupt Level 3 Mask

Exception Mask

Mode Bit 0

Mode Bit 1

Mode Bit 2

Reserved

Debug State

Debug State Mask

Java State

Java Handle

Reserved

Reserved

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Figure 7-5.

The Status Register Low Halfword

Bit 15

R T -

Bit 0

L Q V N Z C

Bit name

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Initial value

Carry

Zero

Sign

Overflow

Saturation

Lock

Reserved

Scratch

Register Remap Enable

7.3.3

7.3.3.1

Processor States

Normal RISC State

The AVR32 processor supports several different execution contexts as shown in

Table 7-3 on page 23 .

Table 7-3.

Overview of execution modes, their priorities and privilege levels.

Priority Mode Security Description

5

6

N/A

N/A

3

4

1

2

Non Maskable Interrupt

Exception

Interrupt 3

Interrupt 2

Interrupt 1

Interrupt 0

Supervisor

Application

Privileged

Privileged

Privileged

Privileged

Privileged

Privileged

Privileged

Unprivileged

Non Maskable high priority interrupt mode

Execute exceptions

General purpose interrupt mode

General purpose interrupt mode

General purpose interrupt mode

General purpose interrupt mode

Runs supervisor calls

Normal program execution mode

7.3.3.2

Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead.

When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode.

Debug State

The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available.

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All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register.

Debug state can be entered as described in the AVR32 AP Technical Reference Manual.

Debug state is exited by the retd instruction.

Java State

AVR32 AP implements a Java Extension Module (JEM). The processor can be set in a Java

State where normal RISC operations are suspended. Refer to the AVR32 Java Technical Refer-

ence Manual for details.

32015D–AVR32–10/07

24

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8.

Pixel Coprocessor (PICO)

Rev.: 1.0.0.0

8.1

Features

Coprocessor coupled to the AVR32 CPU Core through the TCB Bus.

Three parallel Vector Multiplication Units (VMU) where each unit can:

– Multiply three pixel components with three coefficients.

– Add the products from the multiplications together.

– Accumulate the result or add an offset to the sum of the products.

Can be used for accelerating:

– Image Color Space Conversion.

• Configurable Conversion Coefficients.

• Supports packed and planar input and output formats.

• Supports subsampled input color spaces (i.e 4:2:2, 4:2:0).

– Image filtering/scaling.

• Configurable Filter Coefficients.

• Throughput of one sample per cycle for a 9-tap FIR filter.

• Can use the built-in accumulator to extend the FIR filter to more than 9-taps.

• Can be used for bilinear/bicubic interpolations.

– MPEG-4/H.264 Quarter Pixel Motion Compensation.

Flexible input Pixel Selector.

– Can operate on numerous different image storage formats.

Flexible Output Pixel Inserter.

– Scales and saturates the results back to 8-bit pixel values.

– Supports packed and planar output formats.

Configurable coefficients with flexible fixed-point representation.

8.2

Description

The Pixel Coprocessor (PICO) is a coprocessor coupled to the AVR32 CPU through the TCB

(Tightly Coupled Bus) interface. The PICO consists of three Vector Multiplication Units (VMU0,

VMU1, VMU2), an Input Pixel Selector and an Output Pixel Inserter. Each VMU can perform a vector multiplication of a 1x3 12-bit coefficient vector with a 3x1 8-bit pixel vector. In addition a

12-bit offset can be added to the result of this vector multiplication.

The PICO can be used for transforming the pixel components in a given color space (i.e. RGB,

YCrCb, YUV) to any other color space as long as the transformation is linear. The flexibility of the Input Pixel Selector and Output Pixel Insertion logic makes it easy to efficiently support different pixel storage formats with regards to issues such as byte ordering of the color components, if the color components constituting an image are packed/interleaved or stored as separate images or if any of the color components are subsampled.

The three Vector Multiplication Units can also be connected together to form one large vector multiplier which can perform a vector multiplication of a 1x9 12-bit coefficient vector with a 9x1 8bit pixel vector. This can be used to implement FIR filters, bilinear interpolations filters for smoothing/scaling images etc. By allowing the outputs from the Vector Multiplication units to accumulate it is also possible to extend the order of the filter to more than 9-taps.

The results from the VMUs are scaled and saturated back to unsigned 8-bit pixel values in the

Output Pixel Inserter.

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8.3

Block Diagram

The PICO is divided into three pipeline stages with a throughput of one operation per cpu clock cycle.

Figure 8-1.

Pixel Coprocessor Block Diagram

INPIX0 INPIX1 INPIX2

Pipeline Stage 1

Input Pixel Selector

COEFF0_0

COEFF0_1

COEFF0_2

VMU0_IN0 VMU0_IN1 VMU0_IN2 VMU1_IN0 VMU1_IN1 VMU1_IN2

VMU0

COEFF1_0

COEFF1_1

COEFF1_2

VMU1

COEFF2_0

COEFF2_1

COEFF2_2

VMU2_IN0 VMU2_IN1 VMU2_IN2

VMU2

OFFSET0

VMU0_OUT

OFFSET1

VMU1_OUT

OFFSET2

VMU2_OUT

Pipeline Stage 2

ADD

Output Pixel Inserter

OUTPIX0 OUTPIX1 OUTPIX2

Pipeline Stage 3

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8.4

Vector Multiplication Unit (VMU)

Each VMU consists of three multipliers used for multiplying unsigned 8-bit pixel components with signed 12-bit coefficients.The result from each multiplication is a 20-bit signed number that is input to a 22-bit vector adder along with an offset as shown in

Figure 8-2 on page 27

. The operation is equal to the offsetted vector multiplication given in the following equation: vmu_out

= coeff0 coeff1 coeff2 vmu_in0 vmu_in1 vmu_in2

+ offset

Figure 8-2.

Inside VMUn (n

∈ {0,1,2}) coeffn_0 vmun_in0 coeffn_1 vmun_in1 coeffn_2 vmun_in2

Multiply Multiply Multiply offsetn

Vector Adder

VMUn vmun_out

8.5

Input Pixel Selector

The Input Pixel Selector uses the ISM (Input Selection Mode) field in the CONFIG register and the three input pixel source addresses given in the PICO operation instructions to decide which pixels to select for inputs to the VMUs.

8.5.1

Transformation Mode

When the Input Selection Mode is set to Transformation Mode the input pixel source addresses

INx, INy and INz directly maps to three pixels in the INPIXn registers. These three pixels are then input to each of the VMUs. The following expression then represents what is computed by the VMUs in Transformation Mode:

VMU0_OUT

VMU1_OUT

VMU2_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

COEFF1_0 COEFF1_1 COEFF1_2

COEFF2_0 COEFF2_1 COEFF2_2

INx

INy

INz

+

OFFSET0 or VMU0_OUT

OFFSET1 or VMU1_OUT

OFFSET2 or VMU2_OUT

8.5.2

Horizontal Filter Mode

In Horizontal Filter Mode the input pixel source addresses INx, INy and INz represents the base pixel address of a pixel triplet. The pixel triplet {IN(x), IN(x+1), IN(x+2)} is input to VMU0, the pixel triplet {IN(y), IN(y+1), IN(y+2)} is input to VMU1 and the pixel triplet {IN(z), IN(z+1), IN(z+2)}

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is input to VMU2.

Figure 8-3 on page 28 shows how the pixel triplet is found by taking the pixel

addressed by the base address and following the arrow to find the next two pixels which makes up the triplet.

Figure 8-3.

Horizontal Filter Mode Pixel Addressing

INPIX0

INPIX1

INPIX2

IN0

IN4

IN8

IN1

IN5

IN9

IN2

IN6

IN10

IN3

IN7

IN11

The following expression represents what is computed by the VMUs in Horizontal Filter Mode:

VMU0_OUT =

COEFF0_0 COEFF0_1 COEFF0_2

IN(x+0)

IN(x+1)

IN(x+2)

+

(

OFFSET0 or VMU0_OUT

)

VMU1_OUT

=

COEFF1_0 COEFF1_1 COEFF1_2

IN(y+0)

IN(y+1)

IN(y+2)

+

(

OFFSET1 or VMU1_OUT

)

VMU2_OUT

=

COEFF2_0 COEFF2_1 COEFF2_2

IN(z+0)

IN(z+1)

IN(z+2)

+

(

OFFSET2 or VMU2_OUT

)

8.5.3

Vertical Filter Mode

In Vertical Filter Mode the input pixel source addresses INx, INy and INz represent the base of a

pixel triplet found by following the vertical arrow shown in Figure 8-4 on page 28 . The pixel triplet

{IN(x), IN((x+4)%11), IN((x+8)%11)} is input to VMU0, the pixel triplet {IN(y), IN((y+4)%11),

IN((y+8)%11)} is input to VMU1 and the pixel triplet {IN(z), IN((z+4)%11), IN((z+8)%11)} is input to VMU2.

Figure 8-4.

Vertical Filter Mode Pixel Addressing

INPIX0

INPIX1

INPIX2

IN0

IN4

IN8

IN1

IN5

IN9

IN2

IN6

IN10

IN3

IN7

IN11

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The following expression represents what is computed by the VMUs in Vertical Filter Mode:

VMU0_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

IN((x+0)%11)

IN((x+4)%11)

IN((x+8)%11)

+

(

OFFSET0 or VMU0_OUT

)

VMU1_OUT

=

COEFF1_0 COEFF1_1 COEFF1_2

IN((y+0)%11)

IN((y+4)%11)

IN((y+8)%11)

+

(

OFFSET1 or VMU1_OUT

)

VMU2_OUT =

COEFF2_0 COEFF2_1 COEFF2_2

IN((z+0)%11)

IN((z+4)%11)

IN((z+8)%11)

+

(

OFFSET2 or VMU2_OUT

)

8.6

Output Pixel Inserter

The Output Pixel Inserter uses the OIM (Output Insertion Mode) field in the CONFIG register and the destination pixel address given in the PICO operation instructions to decide which three of the twelve possible OUTn pixels to write back the scaled and saturated results from the VMUs to. The 22-bit results from each VMU is first scaled by performing an arithmetical right shift by

COEFF_FRAC_BITS in order to remove the fractional part of the results and obtain the integer part. The integer part is then saturated to an unsigned 8-bit number in the range 0 to 255.

8.6.1

Planar Insertion Mode

In Planar Insertion Mode the destination pixel address OUTd specifies which pixel in each of the registers OUTPIX0, OUTPIX1 and OUTPIX2 will be updated. VMUn writes to OUTPIXn. This can be seen in

Figure 8-5 on page 29

and

Table 8-2 on page 47

. This mode is useful when

transforming from one color space to another where the resulting color components should be stored in separate images.

Figure 8-5.

Planar Pixel Insertion

= VMU0

= VMU1

= VMU2

OUTPIX0

OUTPIX1

OUTPIX2

OUT0

OUT4

OUT8 d = 0

OUT1

OUT5

OUT9 d = 1

OUT2

OUT6

OUT10 d = 2

OUT3

OUT7

OUT11 d = 3

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8.6.2

Packed Insertion Mode

In Packed Insertion Mode the three output registers OUTPIX0, OUTPIX1 and OUTPIX2 are divided into four pixel triplets as seen in

Figure 8-6 on page 30 and

Table 8-2 on page 47

. The destination pixel address is then the address of the pixel triplet. VMUn writes to pixel n of the pixel triplet.This mode is useful when transforming from one color space to another where the resulting color components should be packed together.

Figure 8-6.

Packed Pixel Insertion.

= VMU0

= VMU1

= VMU2

OUT0

OUTPIX0

OUT1 OUT2 d = 0

OUT3 OUT4 d = 1

OUTPIX1

OUT5 OUT6 OUT7 d = 2

OUT8

OUTPIX2

OUT9 OUT10 OUT11 d = 3

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8.7

User Interface

The PICO uses the TCB interface to communicate with the CPU and the user can read from or write to the PICO Register File by using the PICO load/store/move instructions which maps to generic coprocessor instructions.

8.7.1

Register File

The PICO register file can be accessed from the CPU by using the picomv.x, picold.x, picost.x,

picoldm and picostm instructions.

Table 8-1.

Cp Reg #

cr0 cr9 cr10 cr11 cr12 cr13 cr14 cr15 cr5 cr6 cr7 cr8 cr1 cr2 cr3 cr4

PICO Register File

Register

Input Pixel Register 2

Input Pixel Register 1

Input Pixel Register 0

Output Pixel Register 2

Output Pixel Register 1

Output Pixel Register 0

Coefficient Register A for VMU0

Coefficient Register B for VMU0

Coefficient Register A for VMU1

Coefficient Register B for VMU1

Coefficient Register A for VMU2

Coefficient Register B for VMU2

Output from VMU0

Output from VMU1

Output from VMU2

PICO Configuration Register

Name

INPIX2

INPIX1

INPIX0

OUTPIX2

OUTPIX1

OUTPIX0

COEFF0_A

COEFF0_B

COEFF1_A

COEFF1_B

COEFF2_A

COEFF2_B

VMU0_OUT

VMU1_OUT

VMU2_OUT

CONFIG

Access

Read/Write

Read/Write

Read/Write

Read Only

Read Only

Read Only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

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8.7.1.1

Input Pixel Register 0

Register Name: INPIX0

Access Type: Read/Write

31 30 29

23

15

7

22

14

6

21

13

5

• IN0: Input Pixel 0

Input Pixel number 0 to the Input Pixel Selector Unit.

• IN1: Input Pixel 1

Input Pixel number 1 to the Input Pixel Selector Unit.

• IN2: Input Pixel 2

Input Pixel number 2 to the Input Pixel Selector Unit.

• IN3: Input Pixel 3

Input Pixel number 3 to the Input Pixel Selector Unit.

28

20

12

4

IN0

27

19

IN1

11

IN2

3

IN3

10

2

26

18

9

1

25

17

8

0

24

16

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8.7.1.2

Input Pixel Register 1

Register Name: INPIX1

Access Type: Read/Write

31 30 29

23

15

7

22

14

6

21

13

5

• IN0: Input Pixel 4

Input Pixel number 4 to the Input Pixel Selector Unit.

• IN1: Input Pixel 5

Input Pixel number 5 to the Input Pixel Selector Unit.

• IN2: Input Pixel 6

Input Pixel number 6 to the Input Pixel Selector Unit.

• IN3: Input Pixel 7

Input Pixel number 7 to the Input Pixel Selector Unit.

28

20

12

4

IN4

27

19

IN5

11

IN6

3

IN7

10

2

26

18

9

1

25

17

8

0

24

16

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8.7.1.3

Input Pixel Register 2

Register Name: INPIX2

Access Type: Read/Write

31 30 29

23

15

7

22

14

6

21

13

5

• IN0: Input Pixel 8

Input Pixel number 8 to the Input Pixel Selector Unit.

• IN1: Input Pixel 9

Input Pixel number 9 to the Input Pixel Selector Unit.

• IN2: Input Pixel 10

Input Pixel number 10 to the Input Pixel Selector Unit.

• IN3: Input Pixel 11

Input Pixel number 11 to the Input Pixel Selector Unit.

28 27

IN8

20 19

IN9

12

IN10

11

4 3

IN11

10

2

26

18

9

1

25

17

8

0

24

16

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AT32AP7001

8.7.1.4

Output Pixel Register 0

Register Name: OUTPIX0

Access Type: Read

31 30 29 28 27

OUT0

23 22 21 20 19

OUT1

15 14 13 12

OUT2

7 6 5 4

• OUT0: Output Pixel 0

Output Pixel number 0 from the Output Pixel Inserter Unit.

• OUT1: Output Pixel 1

Output Pixel number 1 from the Output Pixel Inserter Unit.

• OUT2: Output Pixel 2

Output Pixel number 2 from the Output Pixel Inserter Unit.

• OUT3: Output Pixel 3

Output Pixel number 3 from the Output Pixel Inserter Unit.

OUT3

11

3

10

2

26

18

9

1

25

17

8

0

24

16

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AT32AP7001

8.7.1.5

Output Pixel Register 1

Register Name: OUTPIX1

Access Type: Read

31 30 29 28 27

OUT4

23 22 21 20 19

OUT5

15 14 13 12

OUT6

7 6 5 4

• OUT4: Output Pixel 4

Output Pixel number 4 from the Output Pixel Inserter Unit.

• OUT5: Output Pixel 5

Output Pixel number 5 from the Output Pixel Inserter Unit.

• OUT6: Output Pixel 6

Output Pixel number 6 from the Output Pixel Inserter Unit.

• OUT7: Output Pixel 7

Output Pixel number 7 from the Output Pixel Inserter Unit.

OUT7

11

3

10

2

26

18

9

1

25

17

8

0

24

16

36

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AT32AP7001

8.7.1.6

Output Pixel Register 2

Register Name: OUTPIX2

Access Type: Read

31 30 29 28 27

OUT8

23 22 21 20 19

OUT9

15 14 13 12 11

OUT10

7 6 5 4

OUT11

• OUT8: Output Pixel 8

Output Pixel number 8 from the Output Pixel Inserter Unit.

• OUT9: Output Pixel 9

Output Pixel number 9 from the Output Pixel Inserter Unit.

• OUT10: Output Pixel 10

Output Pixel number 10 from the Output Pixel Inserter Unit.

• OUT11: Output Pixel 11

Output Pixel number 11 from the Output Pixel Inserter Unit.

3

10

2

26

18

9

1

25

17

8

0

24

16

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8.7.1.7

Coefficient Register A for VMU0

Register Name: COEFF0_A

Access Type: Read/Write

31

-

30

-

29

-

23

15

-

7

22

14

-

6

21

13

-

5

28

-

27

20

COEFF0_0

19

12

-

11

4

COEFF0_1

3

26

COEFF0_0

25

18 17

10

COEFF0_1

9

2 1

24

16

8

0

• COEFF0_0: Coefficient 0 for VMU0

Coefficient 0 input to VMU0. A signed 12-bit fixed-point number where the number of fractional bits is given by the

COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

COEFF_FRAC_BITS

, where the COEFF0_0 value is interpreted as a 2’s complement integer. When reading this register, COEFF0_0 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register.

• COEFF0_1: Coefficient 1 for VMU0

Coefficient 1 input to VMU0. A signed 12-bit fixed-point number where the number of fractional bits is given by the

COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

COEFF_FRAC_BITS

, where the COEFF0_1 value is interpreted as a 2’s complement integer. When reading this register, COEFF0_1 is signextended to 16-bits in order to fill in the unused bits in the lower halfword of this register.

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8.7.1.8

Coefficient Register B for VMU0

Register Name: COEFF0_B

Access Type: Read/Write

31

-

30

-

29

-

23

15

-

7

22

14

-

6

21

13

-

5

28

-

27

20

COEFF0_2

19

12

-

11

4

OFFSET0

3

26

COEFF0_2

25

18 17

10

OFFSET0

9

2 1

24

16

8

0

• COEFF0_2: Coefficient 2 for VMU0

Coefficient 2 input to VMU0. A signed 12-bit fixed-point number where the number of fractional bits is given by the

COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

COEFF_FRAC_BITS

, where the COEFF0_2 value is interpreted as a 2’s complement integer. When reading this register, COEFF0_2 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register.

• OFFSET0: Offset for VMU0

Offset input to VMU0 in case of non-accumulating operations. A signed 12-bit fixed-point number where the number of fractional bits is given by the OFFSET_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

OFFSET_FRAC_BITS

, where the OFFSET0 value is interpreted as a 2’s complement integer. When reading this register, OFFSET0 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register.

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8.7.1.9

Coefficient Register A for VMU1

Register Name: COEFF1_A

Access Type: Read/Write

31

-

30

-

29

-

23

15

-

7

22

14

-

6

21

13

-

5

28

-

27

20

COEFF1_0

19

12

-

11

4

COEFF1_1

3

26

COEFF1_0

25

18 17

10

COEFF1_1

9

2 1

24

16

8

0

• COEFF1_0: Coefficient 0 for VMU1

Coefficient 0 input to VMU1. A signed 12-bit fixed-point number where the number of fractional bits is given by the

COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

COEFF_FRAC_BITS

, where the COEFF1_0 value is interpreted as a 2’s complement integer. When reading this register, COEFF1_0 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register.

• COEFF1_1: Coefficient 1 for VMU1

Coefficient 1 input to VMU0. A signed 12-bit fixed-point number where the number of fractional bits is given by the

COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

COEFF_FRAC_BITS

, where the COEFF1_1 value is interpreted as a 2’s complement integer. When reading this register, COEFF1_1 is signextended to 16-bits in order to fill in the unused bits in the lower halfword of this register.

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8.7.1.10

Coefficient Register B for VMU1

Register Name: COEFF1_B

Access Type: Read/Write

31

-

30

-

29

-

23

15

-

7

22

14

-

6

21

13

-

5

28

-

27

20

COEFF1_2

19

12

-

11

4

OFFSET1

3

26

COEFF1_2

25

18 17

10

OFFSET1

9

2 1

24

16

8

0

• COEFF1_2: Coefficient 2 for VMU1

Coefficient 2 input to VMU1. A signed 12-bit fixed-point number where the number of fractional bits is given by the

COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

COEFF_FRAC_BITS

, where the COEFF1_2 value is interpreted as a 2’s complement integer. When reading this register, COEFF1_2 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register.

• OFFSET1: Offset for VMU1

Offset input to VMU1 in case of non-accumulating operations. A signed 12-bit fixed-point number where the number of fractional bits is given by the OFFSET_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

OFFSET_FRAC_BITS

, where the OFFSET1 value is interpreted as a 2’s complement integer. When reading this register, OFFSET1 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register.

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AT32AP7001

8.7.1.11

Coefficient Register A for VMU2

Register Name: COEFF2_A

Access Type: Read/Write

31

-

30

-

29

-

23

15

-

7

22

14

-

6

21

13

-

5

28

-

27

20

COEFF2_0

19

12

-

11

4

COEFF2_1

3

26

COEFF2_0

25

18 17

10

COEFF2_1

9

2 1

24

16

8

0

• COEFF2_0: Coefficient 0 for VMU2

Coefficient 0 input to VMU2. A signed 12-bit fixed-point number where the number of fractional bits is given by the

COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

COEFF_FRAC_BITS

, where the COEFF2_0 value is interpreted as a 2’s complement integer. When reading this register, COEFF2_0 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register.

• COEFF2_1: Coefficient 1 for VMU2

Coefficient 1 input to VMU2. A signed 12-bit fixed-point number where the number of fractional bits is given by the

COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

COEFF_FRAC_BITS

, where the COEFF2_1 value is interpreted as a 2’s complement integer. When reading this register, COEFF2_1 is signextended to 16-bits in order to fill in the unused bits in the lower halfword of this register.

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AT32AP7001

8.7.1.12

Coefficient Register B for VMU2

Register Name: COEFF2_B

Access Type: Read/Write

31

-

30

-

29

-

23

15

-

7

22

14

-

6

21

13

-

5

28

-

27

20

COEFF2_2

19

12

-

11

4

OFFSET2

3

26

COEFF2_2

25

18 17

10

OFFSET2

9

2 1

24

16

8

0

• COEFF2_2: Coefficient 2 for VMU2

Coefficient 2 input to VMU2. A signed 12-bit fixed-point number where the number of fractional bits is given by the

COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

COEFF_FRAC_BITS

, where the COEFF2_2 value is interpreted as a 2’s complement integer. When reading this register, COEFF2_2 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register.

• OFFSET2: Offset for VMU2

Offset input to VMU2 in case of non-accumulating operations. A signed 12-bit fixed-point number where the number of fractional bits is given by the OFFSET_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to

OFFSET_FRAC_BITS

, where the OFFSET2 value is interpreted as a 2’s complement integer. When reading this register, OFFSET2 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register.

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AT32AP7001

8.7.1.13

VMU0 Output Register

Register Name: VMU0_OUT

Access Type: Read/Write

31

-

30

-

29

-

23

-

15

7

22

-

14

6

21

13

5

28

-

20

27

-

12

VMU0_OUT

11

26

-

19

VMU0_OUT

18

10

4

VMU0_OUT

3 2

25

-

17

9

1

24

-

16

8

0

• VMU0_OUT: Output from VMU0

This register is used for directly accessing the output from VMU0 or for setting the initial value of the accumulator for accumulating operations. The output from VMU0 is a signed 22-bit fixed-point number where the number of fractional bits are given by the COEFF_FRAC_BITS field in the CONFIG register. When reading this register the signed 22-bit value is signextended to 32-bits.

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AT32AP7001

8.7.1.14

VMU1 Output Register

Register Name: VMU1_OUT

Access Type: Read/Write

31

-

30

-

29

-

23

-

15

7

22

-

14

6

21

13

5

28

-

20

27

-

12

VMU1_OUT

11

26

-

19

VMU1_OUT

18

10

4

VMU1_OUT

3 2

25

-

17

9

1

24

-

16

8

0

• VMU1_OUT: Output from VMU1

This register is used for directly accessing the output from VMU1 or for setting the initial value of the accumulator for accumulating operations. The output from VMU1 is a signed 22-bit fixed-point number where the number of fractional bits are given by the COEFF_FRAC_BITS field in the CONFIG register. When reading this register the signed 22-bit value is signextended to 32-bits.

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AT32AP7001

8.7.1.15

VMU2 Output Register

Register Name: VMU2_OUT

Access Type: Read/Write

31

-

30

-

29

-

23

-

15

7

22

-

14

6

21

13

5

28

-

20

27

-

12

VMU2_OUT

11

26

-

19

VMU2_OUT

18

10

4

VMU2_OUT

3 2

25

-

17

9

1

24

-

16

8

0

• VMU2_OUT: Output from VMU2

This register is used for directly accessing the output from VMU2 or for setting the initial value of the accumulator for accumulating operations. The output from VMU2 is a signed 22-bit fixed-point number where the number of fractional bits are given by the COEFF_FRAC_BITS field in the CONFIG register. When reading this register the signed 22-bit value is signextended to 32-bits.

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AT32AP7001

8.7.1.16

PICO Configuration Register

Register Name: CONFIG

Access Type: Read/Write

31

-

30

-

29

-

23

-

15

-

7

22

-

14

-

6 5

OFFSET_FRAC_BITS

21

-

13

-

28

-

20

-

12

-

4

27

-

19

-

11

-

3

26

-

18

-

10

OIM

2 1

COEFF_FRAC_BITS

25

-

17

-

9

ISM

24

-

16

-

8

0

• OIM: Output Insertion Mode

The OIM bit specifies the semantics of the OUTd output pixel address parameter to the pico(s)v(mul/mac) instructions. The

OIM together with the output pixel address parameter specify which of the 12 output bytes (OUTn) of the OUTPIXn registers will be updated with the results from the VMUs.

Table 8-2 on page 47

describes the different Output Insertion Modes.

See

Section 8.6 ”Output Pixel Inserter” on page 29 for a description of the Output Pixel Inserter.

Table 8-2.

OIM Mode

Output Insertion Modes

Description

{OUTPIX0, OUTPIX1, OUTPIX2} is treated as one large register containing 4 sequential 24bit pixel triplets. The DST_ADR field specifies which of the sequential triplets will be updated.

0 Packed Insertion Mode

OUT(d*3 + 0)

Scaled and saturated output from VMU0

OUT(d*3 + 1)

Scaled and saturated output from VMU1

OUT(d*3 + 2)

Scaled and saturated output from VMU2

Each of the OUTPIXn registers will get one of the resulting pixels. The triplet address specifies what byte in each of the OUTPIXn registers the results will be written to.

1 Planar Insertion Mode

OUT(d + 0)

Scaled and saturated output from VMU0

OUT(d+ 4)

Scaled and saturated output from VMU1

OUT(d + 8)

Scaled and saturated output from VMU2

• ISM: Input Selection Mode

T h e I S M f i e l d s p e c i f i e s t h e s e m a n t i c s o f t h e i n p u t p i x e l a d d r e s s p a r a m e t e r s I N x , I N y a n d I N z t o t h e

pico(s)v(mul/mac) instructions. Together with the three input pixel addresses the ISM field specifies to the Input Pixel

Selector which of the input pixels (INn) that should be selected as inputs to the VMUs.

Table 8-3 on page 48

describes the

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AT32AP7001

different Input Selection Modes. See

Section 8.5 ”Input Pixel Selector” on page 27

for a description of the Input Pixel

Table 8-3.

ISM

Input Selection Modes

Mode

0

0

1

1

0

1

0

1

Transformation Mode

Horizontal Filter Mode

Vertical Filter Mode

Reserved

VMU0, VMU1 and VMU2 get the same pixel inputs. These three pixels can be freely selected from the INPIXn registers.

Pixel triplets are selected for input to each of the VMUs by addressing horizontal pixel triplets from the INPIXn registers.

Pixel triplets are selected for input to each of the VMUs by addressing vertical pixel triplets from the INPIXn registers.

N.A

Selector.

• OFFSET_FRAC_BITS: Offset Fractional Bits

Specifies the number of fractional bits in the fixed-point offsets input to each VMU. Must be in the range from 0 to

COEFF_FRAC_BITS. Other values gives undefined results.This value is used for scaling the OFFSETn values before being input to VMUn so that the offset will have the same fixed-point format as the outputs from the multiplication stages before performing the vector addition in the VMU.

• COEFF_FRAC_BITS: Coefficient Fractional Bits

Specifies the number of fractional bits in the fixed-point coefficients input to each VMU. Must be in the range from 0 to 11, since at least one bit of the coefficient must be used for the sign. Other values gives undefined results.

COEFF_FRAC_BITS is used in the Output Pixel Inserter to scale the fixed-point results from the VMUs back to unsigned 8bit integers.

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8.8

PICO Instructions

8.8.1

PICO Instructions Nomenclature

8.8.1.1

Registers and Operands

R{d, s, …} The uppercase ‘R’ denotes a 32-bit (word) register.

Rd

Rs

The lowercase ‘d’ denotes the destination register number.

The lowercase ‘s’ denotes the source register number.

Rb

Ri

Rp

IN{x, y, z}

The lowercase ‘b’ denotes the base register number for indexed addressing modes.

The lowercase ‘i’ denotes the index register number for indexed addressing modes.

The lowercase ‘p’ denotes the pointer register number.

The uppercase ‘IN’ denotes a pixel in the INPIXn registers.

INx

INy

INz

OUTd

OUTd

Pr

PrHi:PrLo

The lowercase ‘x’ denotes the first input pixel number for the PICO operation instructions.

The lowercase ‘y’ denotes the second input pixel number for the PICO operation instructions.

The lowercase ‘z’ denotes the third input pixel number for the PICO operation instructions.

The uppercase ‘OUT’ denotes a pixel in the OUTPIXn registers.

The lowercase ‘d’ denotes the destination pixel number for the PICO operation instructions.

PICO register. See

Section 8.7.1 ”Register File” on page 31

for a complete list of registers.

PICO register pair. Only register pairs corresponding to valid coprocessor double registers are valid.

E.g. INPIX1:INPIX2 (cr1:cr0). The low part must correspond to an even coprocessor register number

n and the high part must then correspond to coprocessor register n+1. See Table 8-1 on page 31

for a mapping between PICO register names and coprocessor register numbers.

PC

LR

SP

Program Counter, equal to R15

Link Register, equal to R14

Stack Pointer, equal to R13

PICORegList Register List used in the picoldm and picostm instructions. See instruction description for which register combinations are allowed in the register list.

disp Displacement sa

[i]

[i:j]

Shift amount

Denotes bit i in a immediate value. Example: imm6[4] denotes bit 4 in an 6-bit immediate value.

Denotes bit i to j in an immediate value.

Some instructions access or use doubleword operands. These operands must be placed in two consecutive register addresses where the first register must be an even register. The even register contains the least significant part and the odd register contains the most significant part. This ordering is reversed in comparison with how data is organized in memory (where the most significant part would receive the lowest address) and is intentional.

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The programmer is responsible for placing these operands in properly aligned register pairs. This is also specified in the "Operands" section in the detailed description of each instruction. Failure to do so will result in an undefined behavior.

8.8.1.2

Operations

ASR(x, n) SE(x, Bits(x) + n) >> n

SATSU(x, n) Signed to Unsigned Saturation ( x is treated as a signed value ):

If (x > (2 n

-1)) then (2 n-1

-1); elseif ( x < 0 ) then 0; else x;

SE(x, n) Sign Extend x to an n-bit value

8.8.1.3

.d

.w

Data Type Extensions

Double (64-bit) operation.

Word (32-bit) operation.

32015D–AVR32–10/07

50

AT32AP7001

8.8.2

PICO Instruction Summary

Table 8-4.

PICO instruction summary

Mnemonics Operands / Syntax Description

picosvmac picosvmul picovmac picovmul picold.d

picold.w

picoldm picomv.d

picomv.w

picost.d

picost.w

picostm

E

E

E

OUTd, INx, INy, INz

OUTd, INx, INy, INz

OUTd, INx, INy, INz

PICO single vector multiplication and accumulation.

PICO single vector multiplication

PICO vector multiplications and accumulations.

PICO vector multiplications.

E OUTd, INx, INy, INz

E PrHi:PrLo, Rp[disp]

E PrHi:PrLo, --Rp

E

PrHi:PrLo,

Rb[Ri<<sa]

E

E

Rd, PrHi:PrLo

PrHi:PrLo, Rd

Load PICO register pair

Load PICO register pair with pre-decrement

Load PICO register pair with indexed addressing

E Pr, Rp[disp]

E Pr, --Rp

Load PICO register

Load PICO register with pre-decrement

E Pr, Rb[Ri<<sa] Load PICO register with indexed addressing

E Rp{++}, PICORegList Load multiple PICO registers

Move from PICO register pair to CPU register pair

Move from CPU register pair to PICO register pair

E Rd, Pr

E Pr, Rd

E Rp[disp], PrHi:PrLo

E Rp++, PrHi:PrLo

E

Rb[Ri<<sa],

PrHi:PrLo

Move from PICO register to CPU register

Move from CPU register to PICO register

Store PICO register pair

Store PICO register pair with post-increment

Store PICO register pair with indexed addressing

E Rp[disp], Pr

E Rp++, Pr

Store PICO register

Store PICO register with post-increment

E Rb[Ri<<sa], Pr Store PICO register with indexed addressing

E {--}Rp, PICORegList Store multiple PICO registers

Operation

See PICO instruction set reference

See PICO instruction set reference

See PICO instruction set reference

See PICO instruction set reference

PrHi:PrLo

*(Rp+ZE(disp8<<2))

PrHi:PrLo

*(--Rp)

PrHi:PrLo

*(Rb+(Ri << sa2))

Pr

*(Rp+ZE(disp8<<2))

Pr

*(--Rp)

Pr

*(Rb+(Ri << sa2))

See PICO instruction set reference

Rd+1:Rd

PrHi:PrLo

PrHi:PrLo

Rd+1:Rd

Rd

Pr

Pr

Rd

*(Rp+ZE(disp8<<2))

PrHi:PrLo

*(Rp--)

PrHi:PrLo

*(Rb+(Ri << sa2))

PrHi:PrLo

*(Rp+ZE(disp8<<2))

Pr

*(Rp--)

Pr

*(Rb+(Ri << sa2))

Pr

See PICO instruction set reference

51

32015D–AVR32–10/07

AT32AP7001

PICOSVMAC – PICO Single Vector Multiplication and Accumulation

Description

Performs three vector multiplications where the input pixels taken from the INPIXn registers depends on the Input Selection

Mode and the input pixel addresses given in the instruction. The values in the VMUn_OUT registers are then accumulated with the new results from the vector multiplications. The results from each Vector Multiplication Unit (VMU) are then added together for one of the outputs to the Output Pixels Inserter to form the result of a single vector multiplication of two 9-element vectors. The results from the VMUs are then scaled and saturated to unsigned 8-bit values before being inserted into the OUTPIXn registers. Which pixels to update in the OUTPIXn registers depend upon the Output Insertion Mode and the output pixel address given in the instruction.

Operation:

I.

if ( Input Selection Mode == Horizontal Filter Mode ) then

VMU0_OUT =

COEFF0_0 COEFF0_1 COEFF0_2

IN(x+0)

IN(x+1)

IN(x+2)

+ VMU0_OUT

VMU1_OUT =

COEFF1_0 COEFF1_1 COEFF1_2

IN(y+0)

IN(y+1)

IN(y+2)

+ VMU1_OUT

VMU2_OUT =

COEFF2_0 COEFF2_1 COEFF2_2

IN(z+0)

IN(z+1)

IN(z+2)

+ VMU2_OUT else if ( Input Selection Mode == Vertical Filter Mode ) then

VMU0_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

IN((x+0)%11)

IN((x+4)%11)

IN((x+8)%11)

+

VMU0_OUT

VMU1_OUT

=

COEFF1_0 COEFF1_1 COEFF1_2

IN((y+0)%11)

IN((y+4)%11)

IN((y+8)%11)

+

VMU1_OUT

VMU2_OUT =

COEFF2_0 COEFF2_1 COEFF2_2

IN((z+0)%11)

IN((z+4)%11)

IN((z+8)%11)

+ VMU2_OUT else if ( Input Selection Mode == Transformation Mode ) then

VMU0_OUT

VMU1_OUT

VMU2_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

COEFF1_0 COEFF1_1 COEFF1_2

COEFF2_0 COEFF2_1 COEFF2_2

INx

INy

INz

+

VMU0_OUT

VMU1_OUT

VMU2_OUT if ( Output Insertion Mode == Packed Insertion Mode ) then

OUT(d*3 + 0)

SATSU(ASR(VMU0_OUT + VMU1_OUT + VMU2_OUT, COEFF_FRAC_BITS) , 8);

OUT(d*3 + 1)

SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d*3 + 2)

SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); else if ( Output Insertion Mode == Planar Insertion Mode ) then

OUT(d + 0)

SATSU(ASR(VMU0_OUT + VMU1_OUT+ VMU2_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 4)

SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 8)

SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);

52

32015D–AVR32–10/07

AT32AP7001

Syntax:

I.

picosvmac OUTd, INx, INy, INz

Operands:

I.

d

{0, 1, 2, 3} x, y, z

{0, 1, ..., 11}

Opcode:

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

OUT d[0]

27

0

11

26

0

10

INx

25

0

9

24

1

8

23

1

7

22

0

6

INy

21

1

5

20

0

4

19

0

3

18

1

2

INz

17

1

1

16

OUT d[1]

0

Example:

/*

Inner loop of a 16-tap symmetric FIR filter with coefficients {c0, c1, c2, c3, c4, c5, c6, c7, c7, ..., c0} set to filter the pixels pointed to by r12 storing the result to the memory pointed to by r11. The coefficients in the PICO are already set to the following values: COEFF0_0 = c0, COEFF0_1 = c1, COEFF0_2 = c2, COEFF1_0 = c3, COEFF1_1 = c4,

COEFF1_2 = c5, COEFF2_0 = c6, COEFF2_1 = c7, COEFF2_2 = 0, OFFSET0 = 0.5 (For rounding the result),

OFFSET1 = 0, OFFSET2 = 0.

*/

...

ld.w

ld.w

ld.w

ld.w

picomv.d

swap.b

swap.b

picosvmul

The Input Selection Mode is set to Horizontal Filter Mode while the Output Insertion Mode is set to Planar Insertion

Mode.

The input image pointer might be unaligned, hence the use of ld.w instead of picold.w.

r1, r12[0] r0, r12[4] r2, r12[8] r3, r12[12]

INPIX1:INPIX2, r0 r2 r3

OUT3, IN4, IN7, IN10

/* r1 = *((int *)src) */

/* r0 = *(((int *)src) + 1) */

/* r2 = *(((int *)src) + 2) */

/* r3 = *(((int *)src) + 3) */

/* INPIX1={src[0],src[1],src[2],src[3]}, INPIX2={src[4],src[5],src[6],src[7]}*/

/* r2 = {src[11],src[10],src[9],src[8]}*/

/* r3 = {src[15],src[14],src[13],src[12]}*/

/* VMU0_OUT = c0*src[0]+c1*src[1]+c2*src[2] + 0.5 picomv.d

picosvmac sub picomv.w

st.b

...

INPIX1:INPIX2, r2

OUT3, IN4, IN7, IN10 r12, -1 r4, OUTPIX0 r11++, r4

/*

/*

VMU2_OUT = c6*src[6]+c7*src[7] */

INPIX1={src[15],src[14],src[13],src[12]},

INPIX2 ={src[11],src[10],src[9],src[8]} */

VMU0_OUT += c0*src[15]+c1*src[14]+c2*src[13]

VMU2_OUT += c6*src[9]+c7*src[8]

OUT3 = satscaled(VMU0_OUT+VMU1_OUT+VMU2_OUT)*/

/* src++ */

/* r4 = { OUT0, OUT1, OUT2, OUT3 }

/* *dst = OUT3 */

53

32015D–AVR32–10/07

AT32AP7001

PICOSVMUL – PICO Single Vector Multiplication

Description

Performs three vector multiplications where the input pixels taken from the INPIXn registers depends on the Input Selection

Mode and the input pixel addresses given in the instruction. The results from each Vector Multiplication Unit (VMU) are then added together for one of the outputs to the Output Pixels Inserter to form the result of a single vector multiplication of two

9-element vectors. The results from the VMUs are then scaled and saturated to unsigned 8-bit values before being inserted into the OUTPIXn registers. Which pixels to update in the OUTPIXn registers depend upon the Output Insertion Mode and the output pixel address given in the instruction.

Operation:

I.

OFFSET_SCALE = COEFF_FRAC_BITS - OFFSET_FRAC_BITS if ( Input Selection Mode == Horizontal Filter Mode ) then

VMU0_OUT =

COEFF0_0 COEFF0_1 COEFF0_2

IN(x+0)

IN(x+1)

IN(x+2)

+ OFFSET0 << OFFSET_SCALE

VMU1_OUT =

COEFF1_0 COEFF1_1 COEFF1_2

IN(y+0)

IN(y+1)

IN(y+2)

+ OFFSET1 << OFFSET_SCALE

VMU2_OUT =

COEFF2_0 COEFF2_1 COEFF2_2

IN(z+0)

IN(z+1)

IN(z+2)

+ OFFSET2 << OFFSET_SCALE else if ( Input Selection Mode == Vertical Filter Mode ) then

VMU0_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

IN((x+0)%11)

IN((x+4)%11)

IN((x+8)%11)

+

OFFSET0 << OFFSET_SCALE

VMU1_OUT

=

COEFF1_0 COEFF1_1 COEFF1_2

IN((y+0)%11)

IN((y+4)%11)

IN((y+8)%11)

+

OFFSET1 << OFFSET_SCALE

VMU2_OUT =

COEFF2_0 COEFF2_1 COEFF2_2

IN((z+0)%11)

IN((z+4)%11)

IN((z+8)%11)

+ OFFSET2 << OFFSET_SCALE else if ( Input Selection Mode == Transformation Mode ) then

VMU0_OUT

VMU1_OUT

VMU2_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

COEFF1_0 COEFF1_1 COEFF1_2

COEFF2_0 COEFF2_1 COEFF2_2

INx

INy

INz

+

OFFSET0 << OFFSET_SCALE

OFFSET1 << OFFSET_SCALE

OFFSE20 << OFFSET_SCALE if ( Output Insertion Mode == Packed Insertion Mode ) then

OUT(d*3 + 0)

SATSU(ASR(VMU0_OUT + VMU1_OUT + VMU2_OUT, COEFF_FRAC_BITS), 8);

OUT(d*3 + 1)

SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d*3 + 2)

SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); else if ( Output Insertion Mode == Planar Insertion Mode ) then

OUT(d + 0)

SATSU(ASR(VMU0_OUT + VMU1_OUT+ VMU2_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 4)

SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 8)

SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);

54

32015D–AVR32–10/07

AT32AP7001

Syntax:

I.

picosvmul OUTd, INx, INy, INz

Operands:

I.

d

{0, 1, 2, 3} x, y, z

{0, 1, ... , 11}

Opcode:

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

OUT d[0]

27

0

11

26

0

10

INx

25

0

9

24

1

8

23

1

7

22

0

6

INy

21

1

5

20

0

4

19

0

3

18

1

2

INz

17

0

1

16

OUT d[1]

0

Example:

/*

Excerpt from inner loop of bilinear interpolation filter operating on image component stored in an array pointed to by r12. The width of the image is stored in r11 while the resulting filtered image is pointed to by r10. The coefficients of the filter: A, B, C, D are already set before this code is executed. COEFF0_0 = A, COEFF0_1 = B, COEFF0_2 = 0,

COEFF1_0 = C, COEFF1_1 = D, COEFF1_2 = 0, COEFF2_0 = 0, COEFF2_1 = 0, COEFF2_2 = 0, OFFSET0 = 0.5

(For rounding the result), OFFSET1 = 0, OFFSET2 = 0.

The Input Selection Mode is set to Horizontal Filter Mode while the Output Insertion Mode is set to Planar Insertion

Mode.

The input image pointer might be unaligned, hence the use of ld.w instead of picold.w, while the output image pointer is word aligned.

*/

...

ld.w

ld.w

sub ld.w

ld.w

picomv.d

Four output pixels are computed in this example which show an example of a bilinear interpolation filter found in the Motion Compensation used in the H.264 Video Standard.

r1, r12[0] r0, r12[r11] r12, -2 r3, r12[0] r2, r12[r11]

INPIX1:INPIX2, r0

OUT0, IN4, IN8, IN0

OUT1, IN5, IN9, IN0

/* r1 = *((int *)src) */

/* r0 = *((int *)(src + width)) */

/* src+=2 */

/* r3 = *((int *)src) */

/* r2 = *((int *)(src + width)) */

/* INPIX1 = r1, INPIX2 = r0 */

/* OUT0 = A*src[j][i+0] + B*src[j][i+1] C*src[j+1][i] + D*src[j+1][i+1] */

/* OUT1 = A*src[j][i+1] + B*src[j][i+2] C*src[j+1][i+1] + D*src[j+1][i+2] */ picosvmul picosvmul picomv.d

picosvmul picosvmul sub picost.w

...

INPIX1:INPIX2, r2

OUT2, IN4, IN8, IN0

OUT3, IN5, IN9, IN0 r12, -2 r10++, OUTPIX0

/* INPIX1 = r3, INPIX2 = r2 */

/* OUT2 = A*src[j][i+2] + B*src[j][i+3] C*src[j+1][i+2] + D*src[j+1][i+3] */

/* OUT3 = A*src[j][i+3] + B*src[j][i+4] C*src[j+1][i+3] + D*src[j+1][i+4] */

/* src+=2 */

/* *((int *)src) = { OUT0, OUT1, OUT2, OUT3 } */

55

32015D–AVR32–10/07

AT32AP7001

PICOVMAC – PICO Vector Multiplication and Accumulation

Description

Performs three vector multiplications where the input pixels taken from the INPIXn registers depends on the Input Selection

Mode and the input pixel addresses given in the instruction. The values in the VMUn_OUT registers are then accumulated with the new results from the vector multiplications. The results from the VMUs are then scaled and saturated to unsigned

8-bit values before being inserted into the OUTPIXn registers. Which pixels to update in the OUTPIXn registers depend upon the Output Insertion Mode and the output pixel address given in the instruction.

Operation:

I.

if ( Input Selection Mode == Horizontal Filter Mode ) then

VMU0_OUT =

COEFF0_0 COEFF0_1 COEFF0_2

IN(x+0)

IN(x+1)

IN(x+2)

+ VMU0_OUT

VMU1_OUT =

COEFF1_0 COEFF1_1 COEFF1_2

IN(y+0)

IN(y+1)

IN(y+2)

+ VMU1_OUT

VMU2_OUT =

COEFF2_0 COEFF2_1 COEFF2_2

IN(z+0)

IN(z+1)

IN(z+2)

+ VMU2_OUT else if ( Input Selection Mode == Vertical Filter Mode ) then

VMU0_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

IN((x+0)%11)

IN((x+4)%11)

IN((x+8)%11)

+

VMU0_OUT

VMU1_OUT

=

COEFF1_0 COEFF1_1 COEFF1_2

IN((y+0)%11)

IN((y+4)%11)

IN((y+8)%11)

+

VMU1_OUT

VMU2_OUT =

COEFF2_0 COEFF2_1 COEFF2_2

IN((z+0)%11)

IN((z+4)%11)

IN((z+8)%11)

+ VMU2_OUT else if ( Input Selection Mode == Transformation Mode ) then

VMU0_OUT

VMU1_OUT

VMU2_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

COEFF1_0 COEFF1_1 COEFF1_2

COEFF2_0 COEFF2_1 COEFF2_2

INx

INy

INz

+

VMU0_OUT

VMU1_OUT

VMU2_OUT if ( Output Insertion Mode == Packed Insertion Mode ) then

OUT(d*3 + 0)

SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8);

OUT(d*3 + 1)

SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d*3 + 2)

SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); else if ( Output Insertion Mode == Planar Insertion Mode ) then

OUT(d + 0)

SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 4)

SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 8)

SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);

56

32015D–AVR32–10/07

AT32AP7001

Syntax:

I.

picovmac OUTd, INx, INy, INz

Operands:

I.

d

{0, 1, 2, 3} x, y, z

{0, 1, ... , 11}

Opcode:

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

OUT d[0]

27

0

11

26

0

10

INx

25

0

9

24

1

8

23

1

7

22

0

6

INy

21

1

5

20

0

4

19

0

3

18

0

2

INz

17

1

1

16

OUT d[1]

0

Example:

/*

Inner loop of a 6-tap symmetric FIR filter with coefficients {c0, c1, c2, c2, c1, c0 } set to filter in the vertical direction of the image pointed to by r12 with the width of the image stored in r11 and the destination image stored in r10. The coefficients in the PICO are already set to the following values: COEFF0_0 = c0, COEFF0_1 = c1, COEFF0_2 = c2,

COEFF1_0 = c0, COEFF1_1 = c1, COEFF1_2 = c2, COEFF2_0 = c0, COEFF2_1 = c1, COEFF2_2 = c2,

OFFSET0 = OFFSET1 = OFFSET2 = 0.5 (For rounding the result).

The Input Selection Mode is set to Vertical Filter Mode while the Output Insertion Mode is set to Packed Insertion

Mode.

*/

...

picold.w

picold.w

picold.w

add picovmul

The input image is assumed to be word aligned.

INPIX0, r12[0]

INPIX1, r12[r11]

INPIX2, r12[r11 << 1] r9, r12, r11

OUT0, IN0, IN1, IN2

/* INPIX0 = {src[0][0], src[0][1], src[0][2], src[0][3] }*/

/* INPIX1 = {src[1][0], src[1][1], src[1][2], src[1][3] }*/

/* INPIX2 = {src[2][0], src[2][1], src[2][2], src[2][3] }*/

/* r9 = src + width */

/* VMU0_OUT = c0*src[0][0]+c1*src[1][0]+c2*src[2][0] + 0.5 picold.w

picold.w

picold.w

picovmac

INPIX2, r9[r11 << 1]

VMU2_OUT = c0*src[0][2]+c1*src[1][2]+c2*src[2][2] + 0.5*/

/* INPIX2 = {src[3][0], src[3][1], src[3][2], src[3][3] }*/

INPIX1, r12[r11 << 2] /* INPIX1 = {src[4][0], src[4][1], src[4][2], src[4][3] }*/

INPIX0, r9[r11 << 2]

OUT0, IN0, IN1, IN2

/* INPIX0 = {src[5][0], src[5][1], src[5][2], src[5][3] }*/

/* VMU0_OUT += c0*src[5][0]+c1*src[4][0]+c2*src[3][0]

VMU2_OUT += c0*src[5][2]+c1*src[4][2]+c2*src[3][2]

OUT0 = satscale(VMU0_OUT), OUT1 = satscale(VMU1_OUT),

OUT2 = satscale(VMU2_OUT) */

....

57

32015D–AVR32–10/07

AT32AP7001

PICOVMUL – PICO Vector Multiplication

Description

Performs three vector multiplications where the input pixels taken from the INPIXn registers depends on the Input Selection

Mode and the input pixel addresses given in the instruction. The results from the VMUs are then scaled and saturated to unsigned 8-bit values before being inserted into the OUTPIXn registers. Which pixels to update in the OUTPIXn registers depend upon the Output Insertion Mode and the output pixel address given in the instruction.

Operation:

I.

OFFSET_SCALE = COEFF_FRAC_BITS - OFFSET_FRAC_BITS if ( Input Selection Mode == Horizontal Filter Mode ) then

VMU0_OUT =

COEFF0_0 COEFF0_1 COEFF0_2

IN(x+0)

IN(x+1)

IN(x+2)

+ OFFSET0 << OFFSET_SCALE

VMU1_OUT =

COEFF1_0 COEFF1_1 COEFF1_2

IN(y+0)

IN(y+1)

IN(y+2)

+ OFFSET1 << OFFSET_SCALE

VMU2_OUT =

COEFF2_0 COEFF2_1 COEFF2_2

IN(z+0)

IN(z+1)

IN(z+2)

+ OFFSET2 << OFFSET_SCALE else if ( Input Selection Mode == Vertical Filter Mode ) then

VMU0_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

IN((x+0)%11)

IN((x+4)%11)

IN((x+8)%11)

+

OFFSET0 << OFFSET_SCALE

VMU1_OUT

=

COEFF1_0 COEFF1_1 COEFF1_2

IN((y+0)%11)

IN((y+4)%11)

IN((y+8)%11)

+

OFFSET1 << OFFSET_SCALE

VMU2_OUT =

COEFF2_0 COEFF2_1 COEFF2_2

IN((z+0)%11)

IN((z+4)%11)

IN((z+8)%11)

+ OFFSET2 << OFFSET_SCALE else if ( Input Selection Mode == Transformation Mode ) then

VMU0_OUT

VMU1_OUT

VMU2_OUT

=

COEFF0_0 COEFF0_1 COEFF0_2

COEFF1_0 COEFF1_1 COEFF1_2

COEFF2_0 COEFF2_1 COEFF2_2

INx

INy

INz

+

OFFSET0 << OFFSET_SCALE

OFFSET1 << OFFSET_SCALE

OFFSE20 << OFFSET_SCALE if ( Output Insertion Mode == Packed Insertion Mode ) then

OUT(d*3 + 0)

SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8);

OUT(d*3 + 1)

SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d*3 + 2)

SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8); else if ( Output Insertion Mode == Planar Insertion Mode ) then

OUT(d + 0)

SATSU(ASR(VMU0_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 4)

SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);

OUT(d + 8)

SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);

58

32015D–AVR32–10/07

AT32AP7001

Syntax:

I.

picovmul OUTd, INx, INy, INz

Operands:

I.

d

{0, 1, 2, 3} x, y, z

{0, 1, ... , 11}

Opcode:

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

OUT d[0]

27

0

11

26

0

10

INx

25

0

9

24

1

8

23

1

7

22

0

6

INy

21

1

5

20

0

4

19

0

3

18

0

2

INz

17

0

1

16

OUT d[1]

0

Example:

/*

Excerpt from inner loop of YCrCb 4:2:2 planar format to RGB packed format image color conversion. The coefficients of the transform is already set before this code is executed. In transforms like this, the inputs Y, Cr and

Cb are often offsetted with a given amount. This offset can be factored out and included in the offsets like this:

1.164*(Y - 16) = 1.164*Y - 18.625.

The pointer to the Y component is in r12, the pointer to the Cr component in r11 and the pointer to the Cb component in r10. The pointer to the RGB output image is in r9.

The Input Selection Mode is set to Transform Mode while the Output Insertion Mode is set to Packed Insertion

Mode.

...

picold.w

picold.w

picold.w

picovmul picovmul picovmul picovmul picostm

...

It is assumed that all the input and output pointers are word aligned.

Four RGB triplets are computed in this example. */

INPIX0, r12++

INPIX1, r11++

INPIX2, r10++

OUT0, IN0, IN4, IN8

OUT1, IN1, IN4, IN8

OUT2, IN2, IN5, IN9

OUT3, IN3, IN5, IN9

/* INPIX0= { Y[0], Y[1], Y[2], Y[3] }*/

/* INPIX1= { Cr[0], Cr[1], Cr[2], Cr[3] }*/

/* INPIX2= { Cb[0], Cb[1], Cb[2], Cb[3] }*/

/* OUT0 = r[0], OUT1 = g[0], OUT2 = b[0] */

/* OUT3 = r[1], OUT4 = g[1], OUT5 = b[1] */

/* OUT6 = r[2], OUT7 = g[2], OUT8 = b[2] */

/* OUT9 = r[3], OUT10 = g[3], OUT11 = b[3] */ r9, OUTPIX2, OUTPIX1, OUTPIX0/* RGB = {r[0],g[0],b[0],r[1],g[1],b[1],r[2],g[2],b[2],r[3],g[3],b[3]} */

59

32015D–AVR32–10/07

AT32AP7001

PICOLD.{D,W} – Load PICO Register(s)

Description

Reads the memory location specified into the given coprocessor register(s).

Operation:

I.

PrHi:PrLo

*(Rp + (ZE(disp8) << 2));

II.

III.

IV.

Rp

PrHi:PrLo

*(Rp);

*(Rb + (Ri << sa2));

Pr

Rp-8;

PrHi:PrLo

V.

VI.

Rp

*(Rp + (ZE(disp8) << 2));

Rp-4;

Pr

Pr

*(Rp);

*(Rb + (Ri << sa2));

Syntax:

I.

picold.d

II.

III.

picold.d

picold.d

IV.

V.

VI.

picold.w

picold.w

picold.w

PrHi:PrLo, Rp[disp]

PrHi:PrLo, --Rp

PrHi:PrLo, Rb[Ri<<sa]

Pr, Rp[disp]

Pr, --Rp

Pr, Rb[Ri<<sa]

Operands:

I-III.

PrHi:PrLo

{ INPIX1:INPIX2, COEFF0_B:COEFF0_A, COEFF1_B:COEFF1_A, COEFF2_B:COEFF2_A,

VMU1_OUT:VMU0_OUT, CONFIG:VMU2_OUT}

IV-VI.

Pr

{ INPIX0, INPIX1, INPIX2, COEFF0_A, COEFF0_B, COEFF1_A, COEFF1_B, COEFF2_A,

COEFF2_B, VMU0_OUT, VMU1_OUT, VMU2_OUT, CONFIG}

I-II, IV-V.p

{0, 1, …, 15}

I, IV.

disp

III, VI.

{b, i}

{0, 4, …, 1020}

{0, 1, …, 15}

III, VI.

sa

{0, 1, 2, 3}

Opcode

I.

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

1

27

1

11

26

0

10

PrLo[3:1]

25

0

9

24

1

8

0

23

1

7

22

0

6

21

1

5

20

0

4 disp8

19

3

18

Rp

17

2 1

16

0

II.

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

0

27

1

11

26

1

10

PrLo[3:1]

25

1

9

24

1

8

0

23

1

7

0 1

22

0

6

0

21

1

5

1

20

0

4 3

0

19 18 17

0

2

Rp

0

1

16

0

0

60

32015D–AVR32–10/07

AT32AP7001

III.

IV.

31

1

15

30

1

14

PICO CP#

29

1

13

31

1

15

30

1

14

PICO CP#

29

1

13

V.

VI.

31

1

15

30

1

14

PICO CP#

29

1

13

31

1

15

30

1

14

PICO CP#

29

1

13

28

0

12

1

28

0

12

0

28

0

12

1

28

0

12

0

27

1

11

27

1

11

26

1

10

PrLo[3:1]

25

1

9

24

1

8

0

26

0

10

Pr

25

0

9

24

1

8

27

1

11

26

1

10

Pr

25

1

9

24

1

8

27

1

11

26

1

10

Pr

25

1

9

24

1

8

23

1

7

23

1

7

0

23

1

7

0

22

0

6

1

21

1

5

Shamt

20

0

4

22

0

6

21

1

5

23

1

7

0 1

22

0

6

0

21

1

5

0

20

0

4

22

0

6

0

21

1

5

Shamt

20

0

4

20

0

4 disp8

19

3

19

3

18

Rp

17

2 1

Ri

16

0

18

Rp

17

2 1

16

0

3

0

19 18 17

0

2

Rp

0

1

16

0

0

19

3

18

Rp

17

2 1

Ri

16

0

Example:

picold.d

COEFF0_B:COEFF0_A, r12[4]

61

32015D–AVR32–10/07

AT32AP7001

PICOLDM – Load Multiple PICO Registers

Description

Reads the memory locations specified into the given PICO registers. The pointer register can optionally be updated after the operation.

Operation:

I. II. III. Loadaddress

Rp; if ( PICORegList contains CONFIG )

CONFIG

*(Loadaddress++); if ( PICORegList contains VMU2_OUT )

VMU2_OUT

*(Loadaddress++); if ( PICORegList contains VMU1_OUT )

VMU1_OUT

*(Loadaddress++); if ( PICORegList contains VMU0_OUT )

VMU0_OUT

*(Loadaddress++); if ( PICORegList contains COEFF2_B)

COEFF2_B

*(Loadaddress++); if ( PICORegList contains COEFF2_A)

COEFF2_A

*(Loadaddress++); if ( PICORegList contains COEFF1_B)

COEFF1_B

*(Loadaddress++); if ( PICORegList contains COEFF1_A)

COEFF1_A

*(Loadaddress++); if ( PICORegList contains COEFF0_B)

COEFF0_B

*(Loadaddress++); if ( PICORegList contains COEFF0_A)

COEFF0_A

*(Loadaddress++); if ( PICORegList contains OUTPIX0)

Loadaddress++; if ( PICORegList contains OUTPIX1)

Loadaddress++; if ( PICORegList contains OUTPIX2)

Loadaddress++; if ( PICORegList contains INPIX0)

INPIX0

*(Loadaddress++); if ( PICORegList contains INPIX1)

INPIX1

*(Loadaddress++); if ( PICORegList contains INPIX2)

INPIX2

*(Loadaddress++); if Opcode[++] == 1 then

Rp

Loadaddress;

Syntax:

I.

II.

III.

picoldm picoldm picoldm

Rp{++}, PICORegList

Rp{++}, PICORegList

Rp{++}, PICORegList

Operands:

I.

PICORegList

{ {INPIX1, INPIX2}, {OUTPIX2, INPIX0}, {OUTPIX0, OUTPIX1}, {COEFF0_B, COEFF0_A},

{COEFF1_B, COEFF1_A}, {COEFF2_B, COEFF2_A}, {VMU1_OUT, VMU0_OUT},

62

32015D–AVR32–10/07

AT32AP7001

II.

III.

I-III.

Opcode

I.

{CONFIG, VMU2_OUT} }

PICORegList

{ INPIX0, INPIX1, INPIX2, OUTPIX0, OUTPIX1, OUTPIX2, COEFF0_A, COEFF0_B }

PICORegList

{ COEFF1_A, COEFF1_B, COEFF2_A,COEFF2_B, VMU0_OUT,VMU1_OUT, p

{0, 1, …, 15}

VMU2_OUT, CONFIG, }

II.

31 30 29 28 27 26 25 24

1 1 1 0 1 1 0

15 14 13 12 11 10 9

1

8

PICO CP# W 0 1 0 0

23

1

7

CONFIG

VMU2_OUT

22

0

6

VMU1_OUT

VMU0_OUT

21

1

5

COEFF2_B

COEFF2_A

20

0

4

COEFF1_B

COEFF1_A

19

3

COEFF0_B

COEFF0_A

18 17

2

OUTPIX0

OUTPIX1

Rp

1

OUTPIX2

INPIX0

31 30 29 28 27 26 25 24

1 1 1 0 1 1 0

15 14 13 12 11 10 9

PICO CP# W 0 0 0

1

8

0

23

1

7

COEFF0_B

22

0

6

COEFF0_A

III.

21

1

5

OUTPIX0

20

0

4

OUTPIX1

19

3

OUTPIX2

18 17

2

INPIX0

Rp

1

INPIX1

16

0

INPIX1

INPIX2

16

0

INPIX2

31 30 29 28 27 26 25 24

1 1 1 0 1 1 0

15 14 13 12 11 10 9

PICO CP# W 0 0 0

1

8

1

23

1

7

CONFIG

22

0

6

VMU2_OUT

21

1

5

VMU1_OUT

20

0

4

VMU0_OUT

19

3

COEFF2_B

18 17

2

COEFF2_A

Rp

1

COEFF1_B

16

0

COEFF1_A

Example:

I.

picoldm

II.

III.

picoldm picoldm r7++, COEFF0_A, COEFF0_B, COEFF1_A, COEFF1_B, COEFF2_A, COEFF2_B r0, INPIX0, INPIX1, INPIX2 r12, VMU0_OUT, VMU1_OUT, VMU2_OUT

63

32015D–AVR32–10/07

AT32AP7001

PICOMV.{D,W} – Move between PICO Register(s) and Register File

Description

Move the specified PICO register(s) to register(s) in the Register File or move register(s) in the Register File to PICO register(s).

Operation:

I.

PrHi:PrLo

(Rs+1:Rs);

II.

III.

IV.

Pr

Rs;

(Rd+1:Rd)

PrHi:PrLo;

Rd

Pr;

Syntax:

I.

picomv.d

II.

III.

IV.

picomv.w

picomv.d

picomv.w

Operands:

I, II.

PrHi:PrLo

{ INPIX1:INPIX2, OUTPIX2:INPIX0, OUTPIX0:OUTPIX1, COEFF0_B:COEFF0_A,

COEFF1_B:COEFF1_A, COEFF2_B:COEFF2_A, VMU1_OUT:VMU0_OUT,

CONFIG:VMU2_OUT }

II, IV.

Pr

{ INPIX0, INPIX1, INPIX2, OUTPIX0, OUTPIX1, OUTPIX2, COEFF0_A, COEFF0_B, COEFF1_A,

I.

III.

II.

IV.

COEFF1_B, COEFF2_A, COEFF2_B, VMU0_OUT, VMU1_OUT, VMU2_OUT, CONFIG} s d

{0, 2, 4, …, 14} s

{0, 2, 4, …, 14} d

{0, 1, …, 15}

{0, 1, …, 15}

Opcode

I.

PrHi:PrLo, Rs

Pr, Rs

Rd, PrHi:PrLo

Rd, Pr

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

0

27

1

11

26

1

10

PrLo[3:1]

25

1

9

24

1

8

0

23

1

7

0

6

0

22

0

21

1

5

1

20

0

4

1

19

3

0

18

Rs

2

0

17

1

0

16

0

0

0

II.

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

0

27

1

11

26

1

10

Pr

25

1

9

24

1

8

23

1

7

0

6

0

22

0

21

1

5

1

20

0

4

0

19

3

0

18

Rs

17

2

0

1

0

16

0

0

64

32015D–AVR32–10/07

AT32AP7001

III.

IV.

31

1

15

30

1

14

PICO CP#

29

1

13

31

1

15

30

1

14

PICO CP#

29

1

13

28

0

12

0

28

0

12

0

27

1

11

27

1

11

26

1

10

PrLo[3:1]

25

1

9

24

1

8

0

26

1

10

Pr

25

1

9

24

1

8

23

1

7

0

23

1

7

0

22

0

6

0

21

1

5

0

22

0

6

0

21

1

5

0

20

0

4

1

20

0

4

0

19

3

0

3

0

19 18

Rd

2

0

17

1

0

16

0

0

0

18

Rd

17

2

0

1

0

16

0

0

Example:

picomv.d

picomv.w

r2, OUTPIX0:OUTPIX1

CONFIG, lr

65

32015D–AVR32–10/07

AT32AP7001

PICOST.{D,W} – Store PICO Register(s)

Description

Stores the PICO register value(s) to the memory location specified by the addressing mode.

Operation:

I.

*(Rp + (ZE(disp8) << 2))

PrHi:PrLo;

II.

III.

*(Rp)

PrHi:PrLo;

Rp

Rp+8;

*(Rb + (Ri << sa2))

IV.

V.

VI.

PrHi:PrLo;

*(Rp + (ZE(disp8) << 2))

Pr;

*(Rp)

Pr;

Rp

Rp-4;

*(Rb + (Ri << sa2))

Pr;

Syntax:

I.

picost.d

II.

III.

picost.d

picost.d

IV.

V.

VI.

picost.w

picost.w

picost.w

Rp[disp], PrHi:PrLo

Rp++, PrHi:PrLo

Rb[Ri<<sa], PrHi:PrLo

Rp[disp], Pr

Rp++, Pr

Rb[Ri<<sa], Pr

Operands:

I-III.

PrHi:PrLo

{ INPIX1:INPIX2, OUTPIX2:INPIX0, OUTPIX0:OUTPIX1, COEFF0_B:COEFF0_A,

COEFF1_B:COEFF1_A, COEFF2_B:COEFF2_A, VMU1_OUT:VMU0_OUT,

CONFIG:VMU2_OUT }

IV-VI.

Pr

{ INPIX0, INPIX1, INPIX2, OUTPIX0, OUTPIX1, OUTPIX2, COEFF0_A, COEFF0_B, COEFF1_A,

COEFF1_B, COEFF2_A, COEFF2_B, VMU0_OUT, VMU1_OUT, VMU2_OUT, CONFIG}

I-II, IV-V.p

{0, 1, …, 15}

I, IV.

disp

III, VI.

{b, i}

{0, 4, …, 1020}

{0, 1, …, 15}

III, VI.

sa

{0, 1, 2, 3}

Opcode

I.

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

1

27

1

11

26

0

10

PrLo[3:1]

25

1

9

24

1

8

0

23

1

7

22

0

6

21

1

5

20

0

4 disp8

19

3

18

Rp

17

2 1

II.

31

1

30

1

29

1

15 14

PICO CP#

13

28

0

12

0

27

1

11

26

1

10

PrLo[3:1]

25

1

9

24

1

8

0

23

1

7

0 1

22

0

6

1

21

1

5

1

20

0

4

16

0

3

0

19 18 17

0

2

Rp

0

1

16

0

0

66

32015D–AVR32–10/07

AT32AP7001

III.

IV.

31

1

15

30

1

14

PICO CP#

29

1

13

31

1

15

30

1

14

PICO CP#

29

1

13

V.

VI.

31

1

15

30

1

14

PICO CP#

29

1

13

31

1

15

30

1

14

PICO CP#

29

1

13

28

0

12

1

28

0

12

0

28

0

12

1

28

0

12

0

27

1

11

27

1

11

26

1

10

PrLo[3:1]

25

1

9

24

1

8

0

26

0

10

Pr

25

1

9

24

1

8

27

1

11

26

1

10

Pr

25

1

9

24

1

8

27

1

11

26

1

10

Pr

25

1

9

24

1

8

23

1

7

23

1

7

1

23

1

7

1

22

0

6

1

21

1

5

Shamt

20

0

4

22

0

6

21

1

5

23

1

7

0 1

22

0

6

1

21

1

5

0

20

0

4

22

0

6

0

21

1

5

Shamt

20

0

4

20

0

4 disp8

19

3

19

3

18

Rp

17

2 1

Ri

16

0

18

Rp

17

2 1

16

0

3

0

19 18 17

0

2

Rp

0

1

16

0

0

19

3

18

Rp

17

2 1

Ri

16

0

Example:

picost.w

r10++, OUTPIX0

67

32015D–AVR32–10/07

AT32AP7001

PICOSTM – Store Multiple PICO Registers

Description

Writes the PICO registers specified in the register list into the specified memory locations.

Operation:

I. II. III.

if Opcode[--] == 1 then

Rp

Storeaddress

Rp - 4*RegistersInList;

Rp; if ( PICORegList contains CONFIG )

*(Storeaddress++)

CONFIG; if ( PICORegList contains VMU2_OUT )

*(Storeaddress++)

VMU2_OUT; if ( PICORegList contains VMU1_OUT )

*(Storeaddress++)

VMU1_OUT; if ( PICORegList contains VMU0_OUT )

*(Storeaddress++)

VMU0_OUT; if ( PICORegList contains COEFF2_B)

*(Storeaddress++)

COEFF2_B; if ( PICORegList contains COEFF2_A)

*(Storeaddress++)

COEFF2_A; if ( PICORegList contains COEFF1_B)

*(Storeaddress++)

COEFF1_B; if ( PICORegList contains COEFF1_A)

*(Storeaddress++)

COEFF1_A; if ( PICORegList contains COEFF0_B)

*(Storeaddress++)

COEFF0_B; if ( PICORegList contains COEFF0_A)

*(Storeaddress++)

COEFF0_A; if ( PICORegList contains OUTPIX0)

*(Storeaddress++)

OUTPIX0; if ( PICORegList contains OUTPIX1)

*(Storeaddress++)

OUTPIX1; if ( PICORegList contains OUTPIX2)

*(Storeaddress++)

OUTPIX2; if ( PICORegList contains INPIX0)

*(Storeaddress++)

INPIX0 ; if ( PICORegList contains INPIX1)

*(Storeaddress++)

INPIX1 ; if ( PICORegList contains INPIX2)

*(Storeaddress++)

INPIX2 ;

Syntax:

I.

II.

III.

picostm picostm picostm

{--}Rp, PICORegList

{--}Rp, PICORegList

{--}Rp, PICORegList

Operands:

I.

PICORegList

{ {INPIX1, INPIX2}, {OUTPIX2, INPIX0}, {OUTPIX0, OUTPIX1}, {COEFF0_B, COEFF0_A},

{COEFF1_B, COEFF1_A}, {COEFF2_B, COEFF2_A}, {VMU1_OUT, VMU0_OUT},

68

32015D–AVR32–10/07

AT32AP7001

II.

III.

I-III.

Opcode

I.

{CONFIG, VMU2_OUT} }

PICORegList

{ INPIX0, INPIX1, INPIX2, OUTPIX0, OUTPIX1, OUTPIX2, COEFF0_A, COEFF0_B }

PICORegList

{ COEFF1_A, COEFF1_B, COEFF2_A,COEFF2_B, VMU0_OUT,VMU1_OUT, p

{0, 1, …, 15}

VMU2_OUT, CONFIG, }

II.

31 30 29 28 27 26 25 24

1 1 1 0 1 1 0

15 14 13 12 11 10 9

1

8

PICO CP# W 0 1 0 1

23

1

7

CONFIG

VMU2_OUT

22

0

6

VMU1_OUT

VMU0_OUT

21

1

5

COEFF2_B

COEFF2_A

20

0

4

COEFF1_B

COEFF1_A

19

3

COEFF0_B

COEFF0_A

18 17

2

OUTPIX0

OUTPIX1

Rp

1

OUTPIX2

INPIX0

31 30 29 28 27 26 25 24

1 1 1 0 1 1 0

15 14 13 12 11 10 9

PICO CP# W 0 0 1

1

8

0

23

1

7

COEFF0_B

22

0

6

COEFF0_A

III.

21

1

5

OUTPIX0

20

0

4

OUTPIX1

19

3

OUTPIX2

18 17

2

INPIX0

Rp

1

INPIX1

16

0

INPIX1

INPIX2

16

0

INPIX2

31 30 29 28 27 26 25 24

1 1 1 0 1 1 0

15 14 13 12 11 10 9

PICO CP# W 0 0 1

1

8

1

23

1

7

CONFIG

22

0

6

VMU2_OUT

21

1

5

VMU1_OUT

20

0

4

VMU0_OUT

19

3

COEFF2_B

18 17

2

COEFF2_A

Rp

1

COEFF1_B

16

0

COEFF1_A

Example:

I.

picostm

II.

III.

picostm picostm

--r7, COEFF0_A, COEFF0_B, COEFF1_A, COEFF1_B, COEFF2_A, COEFF2_B r2, OUTPIX0, OUTPIX1, OUTPIX2 r11, VMU0_OUT, VMU1_OUT, VMU2_OUT

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8.9

Data Hazards

Data hazards are caused by data dependencies between instructions which are in different stages of the pipeline and reads/writes registers which are common to several pipeline stages.

Because of the 3-stage pipeline employed in the PICO data hazards might exist between instructions. Data hazards are handled by hardware interlocks which can stall a new read command from or write command to the PICO register file.

Table 8-5.

Instruction

Data Hazards

Next

Instruction

picovmul picovmac picosvmul picosvmac picomv.x Pr,...

picold.x picoldm picomv.x Rd,...

picost.x

picostm

Condition

Write-After-Read (WAR) or Write-After-Write (WAW)

Hazard will occur if writing COEFFn_A/B, VMUn_OUT or CONFIG since these are accessed when the PICO command is in Pipeline Stage 2 and Pipeline Stage 3.

Writes to INPIXn registers produces no hazard since they are only accessed in Pipeline Stage 1.

Read-After-Write Hazard (RAW) will occur if reading the PICO register file while a command is in the pipeline.

Stall

Cycles

1

0

2

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9.

Memories

9.1

Embedded Memories

32 Kbyte SRAM

– Implemented as two 16Kbyte blocks

– Single cycle access at full bus speed

9.2

Physical Memory Map

The system bus is implemented as an HSB bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AT32AP7001 by default uses segment translation, as described in the AVR32 Architecture Manual. The 32 bit physical address space is mapped as follows:

Table 9-1.

Start Address

AT32AP7001 Physical Memory Map

Size Device

0x0000_0000

0x0400_0000

0x0800_0000

0x0C00_0000

0x1000_0000

0x2000_0000

0x2400_0000

0x2400_4000

0xFF20_0000

0xFF30_0000

0xFFE0_0000

0xFFF0_0000

64 Mbyte

64 Mbyte

64 Mbyte

64 Mbyte

256 Mbyte

64 Mbyte

16 Kbyte

16 Kbyte

1 KByte

1 MByte

1 MByte

1 MByte

EBI SRAM CS0

EBI SRAM CS4

EBI SRAM CS2

EBI SRAM CS3

EBI SRAM/SDRAM CS1

EBI SRAM CS5

Internal SRAM 0

Internal SRAM1

DMACA configuration

USBA Data

PBA

PBB

Accesses to unused areas returns an error result to the master requesting such an access.

The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, MCFG2 is associated with the HSB-HSB bridge.

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Table 9-2.

Master 0

Master 1

Master 2

Master 3

Master 4

Master 8

Master 9

HSB masters

CPU Dcache

CPU Icache

HSB-HSB Bridge

ISI DMA

USBA DMA

DMAC Master Interface 0

DMAC Master Interface 1

Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is associated with PBB.

HSB slaves

Table 9-3.

Slave 0

Slave 1

Slave 2

Slave 3

Slave 4

Slave 5

Slave 7

Internal SRAM 0

Internal SRAM1

PBA

PBB

EBI

USBA data

DMACA configuration

72

AT32AP7001

10. Peripherals

10.1

Peripheral address map

Table 10-1.

Peripheral Address Mapping

Address

0xFF200000

0xFF300000

0xFFE00000

0xFFE00400

0xFFE00800

0xFFE00C00

0xFFE01000

0xFFE01400

0xFFE01800

0xFFE01C00

0xFFE02000

0xFFE02400

0xFFE02800

0xFFE02C00

0xFFE03000

0xFFE03400

0xFFE03800

SSC1

SSC2

PIOA

PIOB

PIOC

PIOD

PIOE

DMACA

USBA

SPI0

SPI1

TWI

USART0

USART1

USART2

USART3

SSC0

Peripheral Name

DMA Controller Slave Interface- DMACA

USB Slave Interface - USBA

Serial Peripheral Interface - SPI0

Serial Peripheral Interface - SPI1

Two-wire Interface - TWI

Universal Synchronous Asynchronous Receiver

Transmitter - USART0

Universal Synchronous Asynchronous Receiver

Transmitter - USART1

Universal Synchronous Asynchronous Receiver

Transmitter - USART2

Universal Synchronous Asynchronous Receiver

Transmitter - USART3

Synchronous Serial Controller - SSC0

Synchronous Serial Controller - SSC1

Synchronous Serial Controller - SSC2

Parallel Input/Output 2 - PIOA

Parallel Input/Output 2 - PIOB

Parallel Input/Output 2 - PIOC

Parallel Input/Output 2 - PIOD

Parallel Input/Output 2 - PIOE

Bus

PB A

PB A

PB A

PB A

PB A

PB A

PB A

PB A

PB A

PB A

PB A

HSB

HSB

PB A

PB A

PB A

PB A

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Table 10-1.

Peripheral Address Mapping (Continued)

Address Peripheral Name

0xFFF00C00

0xFFF01000

0xFFF01400

0xFFF02000

0xFFF02400

0xFFF02800

0xFFF02C00

0xFFE03C00

0xFFF00000

0xFFF00080

0xFFF000B0

0xFFF00100

0xFFF00400

0xFFF00800

0xFFF03000

0xFFF03400

0xFFF03800

0xFFF03C00

INTC

HMATRIX

TC0

TC1

PWM

ABDAC

MCI

PSIF

PM

RTC

WDT

EIC

AC97C

ISI

USBA

SMC

SDRAMC

ECC

PS2 Interface - PSIF

Power Manager - PM

Real Time Counter- RTC

WatchDog Timer- WDT

External Interrupt Controller - EIC

Interrupt Controller - INTC

HSB Matrix - HMATRIX

Timer/Counter - TC0

Timer/Counter - TC1

Pulse Width Modulation Controller - PWM

Audio Bitstream DAC - ABDAC

MultiMedia Card Interface - MCI

AC97 Controller - AC97C

Image Sensor Interface - ISI

USB Configuration Interface - USBA

Static Memory Controller - SMC

SDRAM Controller - SDRAMC

Error Correcting Code Controller - ECC

AT32AP7001

Bus

PB B

PB B

PB B

PB B

PB B

PB B

PB B

PB A

PB B

PB B

PB B

PB B

PB B

PB B

PB B

PB B

PB B

PB B

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AT32AP7001

10.2

Interrupt Request Signal Map

The various modules may output interrupt request signals. These signals are routed to the Interrupt Controller (INTC). The Interrupt Controller supports up to 64 groups of interrupt requests.

Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individual submodules for a description of the semantic of the different interrupt requests.

The interrupt request signals in AT32AP7001 are connected to the INTC as follows:

15

16

17

18

19

11

12

13

14

7

8

9

10

5

6

3

4

Table 10-2.

Interrupt Request Signal Map

Group

0

Line

0

Signal

COUNT-COMPARE match

2

20

21

0

1

0

0

0

0

0

0

0

0

2

3

0

0

0

0

0

0

0

0

0

0

3

4

1

2

1

0

PIOA

PIOB

PIOC

PIOD

PIOE

PSIF

EIC0

EIC1

EIC2

EIC3

PM

RTC

TWI

USART0

USART1

USART2

USART3

SSC0

SSC1

SSC2

Performance Counter Overflow

DMACA BLOCK

DMACA DSTT

DMACA ERR

DMACA SRCT

DMACA TFR

SPI 0

SPI 1

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30

31

32

24

27

28

29

Table 10-2.

Interrupt Request Signal Map

Group Line Signal

22

23

0

0

1

2

2

0

0

1

0

0

0

0

0

TC00

TC01

TC02

TC10

TC11

TC12

PWM

ABDAC

MCI

AC97C

ISI

USBA

EBI

10.3

DMACA Handshake Interface Map

The following table details the hardware handshake map between the DMACA and the peripherals attached to it: :

Table 10-3.

Hardware Handshaking Connection

Request

MCI RX

MCI TX

ABDAC TX

AC97C CHANNEL A RX

AC97C CHANNEL A TX

AC97C CHANNEL B RX

AC97C CHANNEL B TX

EXTERNAL DMA REQUEST 0

EXTERNAL DMA REQUEST 1

EXTERNAL DMA REQUEST 2

EXTERNAL DMA REQUEST 3

Hardware Handshaking Interface

0

1

2

5

6

3

4

9

10

7

8

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10.4

Clock Connections

10.4.1

Timer/Counters

Each Timer/Counter channel can independently select an internal or external clock source for its counter:

Table 10-4.

Timer/Counter clock connections

Timer/Counter

0

Source

Internal

Name

TIMER_CLOCK1

1

External

Internal

External

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

XC1

XC2

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

XC1

XC2

Connection

clk_osc32 clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32

See Section 10.7

clk_osc32 clk_pbb / 4 clk_pbb / 8 clk_pbb / 16 clk_pbb / 32

See Section 10.7

10.4.2

USARTs

Each USART can be connected to an internally divided clock:

2

3

0

1

Table 10-5.

USART clock connections

USART Source

Internal

Name

CLK_DIV

Connection

clk_pba / 8

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AT32AP7001

10.4.3

SPIs

Each SPI can be connected to an internally divided clock:

Table 10-6.

SPI clock connections

SPI Source

0

1

Internal

Name

CLK_DIV

Connection

clk_pba / 32

10.4.4

USBA

OSC1 is connected to the USB HS Phy and must be 12 MHz when using the USBA.

10.5

External Interrupt Pin Mapping

External interrupt requests are connected to the following pins::

Table 10-7.

External Interrupt Pin Mapping

Source

NMI_N

EXTINT0

EXTINT1

EXTINT2

EXTINT3

Connection

PB24

PB25

PB26

PB27

PB28

10.6

Nexus OCD AUX port connections

If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 AP Techni-

cal Reference Manual.

Table 10-8.

Nexus OCD AUX port connections

Pin

EVTI_N

AXS=0

EVTI_N

MDO[5]

MDO[4]

MDO[3]

MDO[2]

MDO[1]

MDO[0]

EVTO_N

MCKO

MSEO[1]

MSEO[0]

PB09

PB08

PB07

PB06

PB05

PB04

PB03

PB02

PB01

PB00

AXS=1

EVTI_N

PC18

PC14

PC12

PC11

PC06

PC05

PB28

PC02

PC01

PC00

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AT32AP7001

10.7

Peripheral Multiplexing on IO lines

10.7.1

The AT32AP7001 features five PIO controllers, PIOA to PIOE, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines.

Each line can be assigned to one of two peripheral functions, A or B. The tables in the following pages define how the I/O lines of the peripherals A and B are multiplexed on the PIO

Controllers.

Note that some output only peripheral functions might be duplicated within the tables.

PIO Controller A Multiplexing

Table 10-9.

PIO Controller A Multiplexing

QFP208 I/O Line Peripheral A

49

50

51

54

45

46

47

48

55

72

73

74

75

41

42

43

44

35

38

39

40

31

32

175

176

27

28

29

30

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA08

PA09

PA10

PA11

PA12

PA13

PA14

PA15

PA00

PA01

PA02

PA03

PA04

PA05

PA06

PA07

SPI0 - MISO

SPI0 - MOSI

SPI0 - SCK

SPI0 - NPCS[0]

SPI0 - NPCS[1]

SPI0 - NPCS[2]

TWI - SDA

TWI - SCL

PSIF - CLOCK

PSIF - DATA

MCI - CLK

MCI - CMD

MCI - DATA[0]

MCI - DATA[1]

MCI - DATA[2]

MCI - DATA[3]

USART1 - CLK

USART1 - RXD

USART1 - TXD

USART1 - RTS

USART1 - CTS

SSC0 - RX_FRAME_SYNC

SSC0 - RX_CLOCK

SSC0 - TX_CLOCK

SSC0 - TX_FRAME_SYNC

SSC0 - TX_DATA

SSC0 - RX_DATA

SPI1 - NPCS[3]

PWM - PWM[0]

Peripheral B

TC0 - B1

TC0 - B2

TC0 - CLK2

TC0 - CLK1

SPI0 - NPCS[3]

PWM - PWM[2]

PWM - PWM[3]

TC1 - A0

TC1 - A1

TC1 - B0

TC1 - B1

TC1 - CLK0

TC1 - A2

SSC1 - RX_FRAME_SYNC

SSC1 - TX_FRAME_SYNC

SSC1 - TX_CLOCK

SSC1 - RX_CLOCK

SSC1 - TX_DATA

SSC1 - RX_DATA

USART0 - RTS

USART0 - CTS

USART0 - RXD

USART0 - TXD

USART0 - CLK

TC0 - CLK0

TC0 - A0

TC0 - A1

TC0 - A2

TC0 - B0

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10.7.2

Table 10-9.

PIO Controller A Multiplexing

76

77

78

PA29

PA30

PA31

PWM - PWM[1]

PM - GCLK[0]

PM - GCLK[1]

PIO Controller B Multiplexing

TC1 - B2

TC1 - CLK1

TC1 - CLK2

Table 10-10. PIO Controller B Multiplexing

QFP208 I/O Line Peripheral A

33

34

80

81

82

100

101

168

169

170

171

164

165

166

167

160

161

162

163

152

153

158

159

148

149

150

151

144

145

146

147

PB24

PB25

PB26

PB27

PB28

PB29

PB30

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

PB08

PB09

PB10

PB11

PB12

PB13

PB14

PB15

PB00

PB01

PB02

PB03

PB04

PB05

PB06

PB07

ISI - DATA[0]

ISI - DATA[1]

ISI - DATA[2]

ISI - DATA[3]

ISI - DATA[4]

ISI - DATA[5]

ISI - DATA[6]

ISI - DATA[7]

ISI - HSYNC

ISI - VSYNC

ISI - PCLK

PSIF - CLOCK[1]

PSIF - DATA[1]

SSC2 - TX_DATA

SSC2 - RX_DATA

SSC2 - TX_CLOCK

SSC2 - TX_FRAME_SYNC

SSC2 - RX_FRAME_SYNC

SSC2 - RX_CLOCK

PM - GCLK[2]

ABDAC - DATA[1]

ABDAC - DATA[0]

ABDAC - DATAN[1]

ABDAC - DATAN[0]

NMI_N

EXTINT0

EXTINT1

EXTINT2

EXTINT3

PM - GCLK[3]

PM - GCLK[4]

Peripheral B

SPI1 - MISO

SPI1 - MOSI

SPI1 - NPCS[0]

SPI1 - NPCS[1]

SPI1 - NPCS[2]

SPI1 - SCK

MCI - CMD[1]

MCI - DATA[4]

MCI - DATA[5]

MCI - DATA[6]

MCI - DATA[7]

ISI - DATA[8]

ISI - DATA[9]

ISI - DATA[10]

ISI - DATA[11]

USART3 - CTS

USART3 - RTS

USART3 - TXD

USART3 - RXD

USART3 - CLK

AC97C - SDO

AC97C - SYNC

AC97C - SCLK

AC97C - SDI

DMACA - DMARQ[0]

DMACA - DMARQ[1]

USART2 - RXD

USART2 - TXD

USART2 - CLK

USART2 - CTS

USART2 - RTS

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81

10.7.3

PIO Controller E Multiplexing

Table 10-11. PIO Controller E Multiplexing

QFP208 I/O Line Peripheral A

202

203

204

205

198

199

200

201

194

195

196

197

190

191

192

193

92

91

90

89

206

2

3

93

88

87

PE08

PE09

PE10

PE11

PE12

PE13

PE14

PE15

PE00

PE01

PE02

PE03

PE04

PE05

PE06

PE07

PE16

PE17

PE18

PE19

PE20

PE21

PE22

PE23

PE24

PE25

EBI - DATA[16]

EBI - DATA[17]

EBI - DATA[18]

EBI - DATA[19]

EBI - DATA[20]

EBI - DATA[21]

EBI - DATA[22]

EBI - DATA[23]

EBI - DATA[24]

EBI - DATA[25]

EBI - DATA[26]

EBI - DATA[27]

EBI - DATA[28]

EBI - DATA[29]

EBI - DATA[30]

EBI - DATA[31]

EBI - ADDR[23]

EBI - ADDR[24]

EBI - ADDR[25]

EBI - CFCE1

EBI - CFCE2

EBI - NCS[4]

EBI - NCS[5]

EBI - CFRNW

EBI - NWAIT

EBI - NCS[2]

Peripheral B

AT32AP7001

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10.7.4

10.7.4.1

IO Pins Without Multiplexing

Many of the external EBI pins are not controlled by the PIO modules, but directly driven by the

EBI. These pins have programmable pullup resistors. These resistors are controlled by Special

Function Register 4 (SFR4) in the HMATRIX. The pullup on the lines multiplexed with PIO is controlled by the appropriate PIO control register.

This SFR can also control CompactFlash, SmartMedia or NandFlash Support, see the EBI chapter for details

HMatrix SFR4 EBI Control Register

Name:

Access Type:

31

HMATRIX_SFR4

Read/Write

30

29

28

27

26

25

24

23

15

7

22

14

21

13

20

12

19

11

18

10

17

9

16

8

EBI_DBPUC

6

5

EBI_CS5A

4

EBI_CS4A

3

EBI_CS3A

2

1

EBI_CS1A

0

-

• CS1A: Chip Select 1 Assignment

0 = Chip Select 1 is assigned to the Static Memory Controller.

1 = Chip Select 1 is assigned to the SDRAM Controller.

• CS3A: Chip Select 3 Assignment

0 = Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.

1 = Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash/SmartMedia

Logic is activated.

• CS4A: Chip Select 4 Assignment

0 = Chip Select 4 is assigned to the Static Memory Controller and NCS4, NCS5 and NCS6 behave as defined by the SMC.

1 = Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.

• CS5A: Chip Select 5 Assignment

0 = Chip Select 5 is assigned to the Static Memory Controller and NCS4, NCS5 and NCS6 behave as defined by the SMC.

1 = Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.

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Accessing the address space reserved to NCS5 and NCS6 may lead to an unpredictable outcome.

• EBI_DBPUC: EBI Data Bus Pull-up Control

0: EBI D[15:0] are internally pulled up to the VDDIO power supply.

The pull-up resistors are enabled after reset.

1: EBI D[15:0] are not internally pulled up.

Table 10-12. IO Pins without multiplexing

I/O Line Function

PX24

PX25

PX26

PX27

PX28

PX29

PX30

PX31

PX16

PX17

PX18

PX19

PX20

PX21

PX22

PX23

PX08

PX09

PX10

PX11

PX12

PX13

PX14

PX15

PX00

PX01

PX02

PX03

PX04

PX05

PX06

PX07

EBI - ADDR[0]

EBI - ADDR[1]

EBI - ADDR[2]

EBI - ADDR[3]

EBI - ADDR[4]

EBI - ADDR[5]

EBI - ADDR[6]

EBI - ADDR[7]

EBI - ADDR[8]

EBI - ADDR[9]

EBI - ADDR[10]

EBI - ADDR[11]

EBI - ADDR[12]

EBI - ADDR[13]

EBI - ADDR[14]

EBI - ADDR[15]

EBI - DATA[0]

EBI - DATA[1]

EBI - DATA[2]

EBI - DATA[3]

EBI - DATA[4]

EBI - DATA[5]

EBI - DATA[6]

EBI - DATA[7]

EBI - DATA[8]

EBI - DATA[9]

EBI - DATA[10]

EBI - DATA[11]

EBI - DATA[12]

EBI - DATA[13]

EBI - DATA[14]

EBI - DATA[15]

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Table 10-12. IO Pins without multiplexing (Continued)

PX40

PX41

PX42

PX43

PX44

PX45

PX46

PX47

PX32

PX33

PX34

PX35

PX36

PX37

PX38

PX39

PX48

PX49

PX50

PX51

PX52

PX53

EBI - ADDR[16]

EBI - ADDR[17]

EBI - ADDR[18]

EBI - ADDR[19]

EBI - ADDR[20]

EBI - ADDR[21]

EBI - ADDR[22]

EBI - NCS[0]

EBI - NCS[1]

EBI - NCS[3]

EBI - NRD

EBI - NWE0

EBI - NWE1

EBI - NWE3

EBI - SDCK

EBI - SDCKE

EBI - RAS

EBI - CAS

EBI - SDWE

EBI - SDA10

EBI - NANDOE

EBI - NANDWE

AT32AP7001

85

AT32AP7001

10.8

Peripheral overview

10.8.1

10.8.2

10.8.3

External Bus Interface

Optimized for Application Memory Space support

Integrates Three External Memory Controllers:

– Static Memory Controller

– SDRAM Controller

– ECC Controller

Additional Logic for NAND Flash/SmartMedia

TM

and CompactFlash

TM

Support

– SmartMedia support: 8-bit as well as 16-bit devices are supported

– CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled.

Optimized External Bus:

– 16- or 32-bit Data Bus

– Up to 26-bit Address Bus, Up to 64-Mbytes Addressable

– Optimized pin multiplexing to reduce latencies on External Memories

Up to 6 Chip Selects, Configurable Assignment:

– Static Memory Controller on NCS0

– SDRAM Controller or Static Memory Controller on NCS1

– Static Memory Controller on NCS2

– Static Memory Controller on NCS3, Optional NAND Flash/SmartMedia

TM

Support

– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash

TM

Support

Static Memory Controller

6 Chip Selects Available

64-Mbyte Address Space per Chip Select

8-, 16- or 32-bit Data Bus

Word, Halfword, Byte Transfers

Byte Write or Byte Select Lines

Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

Programmable Data Float Time per Chip Select

Compliant with LCD Module

External Wait Request

Automatic Switch to Slow Clock Mode

Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

SDRAM Controller

Numerous Configurations Supported

– 2K, 4K, 8K Row Address Memory Parts

– SDRAM with Two or Four Internal Banks

– SDRAM with 16- or 32-bit Data Path

Programming Facilities

– Word, Half-word, Byte Access

– Automatic Page Break When Memory Boundary Has Been Reached

– Multibank Ping-pong Access

– Timing Parameters Specified by Software

– Automatic Refresh Operation, Refresh Rate is Programmable

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10.8.4

10.8.5

10.8.6

Energy-saving Capabilities

– Self-refresh, Power-down and Deep Power Modes Supported

– Supports Mobile SDRAM Devices

Error Detection

– Refresh Error Interrupt

SDRAM Power-up Initialization by Software

CAS Latency of 1, 2, 3 Supported

Auto Precharge Command Not Used

Error Corrected Code Controller

Hardware Error Corrected Code (ECC) Generation

– Detection and Correction by Software

Supports NAND Flash and SmartMedia

Devices with 8- or 16-bit Data Path.

Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes, Specified by Software

Serial Peripheral Interface

Supports communication with serial external devices

– Four chip selects with external decoder support allow communication with up to 15 peripherals

– Serial memories, such as DataFlash™ and 3-wire EEPROMs

– Serial peripherals, such as ADCs, DACs, CAN Controllers and Sensors

– External co-processors

Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select

– Programmable phase and polarity per chip select

– Programmable transfer delays between consecutive transfers and between clock and data per chip select

– Programmable delay between consecutive transfers

– Selectable mode fault detection

Very fast transfers supported

– Transfers with baud rates up to MCK

– The chip select line may be left active to speed up transfers on the same device

Two-wire Interface

Compatibility with standard two-wire serial memory

One, two or three bytes for slave address

Sequential read/write operations

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10.8.7

10.8.8

10.8.9

USART

Programmable Baud Rate Generator

5- to 9-bit full-duplex synchronous or asynchronous serial communications

– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode

– Parity generation and error detection

– Framing error detection, overrun error detection

– MSB- or LSB-first

– Optional break generation and detection

– By 8 or by-16 over-sampling receiver frequency

– Hardware handshaking RTS-CTS

– Receiver time-out and transmitter timeguard

– Optional Multi-drop Mode with address generation and detection

– Optional Manchester Encoding

RS485 with driver control signal

ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

IrDA modulation and demodulation

– Communication at up to 115.2 Kbps

Test Modes 46

– Remote Loopback, Local Loopback, Automatic Echo

Serial Synchronous Controller

Provides serial synchronous communication links used in audio and telecom applications (with

CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)

Contains an independent receiver and transmitter and a common clock divider

Offers a configurable frame sync and data length

Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal

Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal

AC97 Controller

Compatible with AC97 Component Specification V2.2

Capable to Interface with a Single Analog Front end

Three independent RX Channels and three independent TX Channels

– One RX and one TX channel dedicated to the AC97 Analog Front end control

– One RX and one TX channel for data transfers, connected to the DMACA

– One RX and one TX channel for data transfers, connected to the DMACA

Time Slot Assigner allowing to assign up to 12 time slots to a channel

Channels support mono or stereo up to 20 bit sample length - Variable sampling rate AC97 Codec

Interface (48KHz and below)

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10.8.10

Audio Bitstream DAC

Digital Stereo DAC

Oversampled D/A conversion architecture

– Oversampling ratio fixed 128x

– FIR equalization filter

– Digital interpolation filter: Comb4

10.8.11

Timer Counter

– 3rd Order Sigma-Delta D/A converters

Digital bitstream outputs

Parallel interface

Connected to DMA Controller for background transfer without CPU intervention

Three 16-bit Timer Counter Channels

Wide range of functions including:

– Frequency Measurement

– Event Counting

– Interval Measurement

– Pulse Generation

– Delay Timing

– Pulse Width Modulation

– Up/down Capabilities

Each channel is user-configurable and contains:

– Three external clock inputs

– Five internal clock inputs

– Two multi-purpose input/output signals

Two global registers that act on all three TC Channels

10.8.12

Pulse Width Modulation Controller

4 channels, one 16-bit counter per channel

Common clock generator, providing Thirteen Different Clocks

– A Modulo n counter providing eleven clocks

– Two independent Linear Dividers working on modulo n counter outputs

Independent channel programming

– Independent Enable Disable Commands

– Independent Clock

– Independent Period and Duty Cycle, with Double Bufferization

– Programmable selection of the output waveform polarity

– Programmable center or left aligned output waveform

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10.8.13

MultiMedia Card Interface

10.8.14

PS/2 Interface

2 double-channel MultiMedia Card Interface, allowing concurrent transfers with 2 cards

Compatibility with MultiMedia Card Specification Version 2.2

Compatibility with SD Memory Card Specification Version 1.0

Compatibility with SDIO Specification Version V1.0.

Cards clock rate up to Master Clock divided by 2

Embedded power management to slow down clock rate when not used

Each MCI has two slot, each supporting

– One slot for one MultiMediaCard bus (up to 30 cards) or

– One SD Memory Card

Support for stream, block and multi-block data read and write

10.8.15

USB Interface

Peripheral Bus slave

PS/2 Host

Receive and transmit capability

Parity generation and error detection

Overrun error detection

Supports Hi (480Mbps) and Full (12Mbps) speed communication

Compatible with the USB 2.0 specification

UTMI Compliant

7 Endpoints

Embedded Dual-port RAM for Endpoints

Suspend/Resume Logic (Command of UTMI)

Up to Three Memory Banks for Endpoints (Not for Control Endpoint)

4 KBytes of DPRAM

10.8.16

Image Sensor Interface

ITU-R BT. 601/656 8-bit mode external interface support

Support for ITU-R BT.656-4 SAV and EAV synchronization

Vertical and horizontal resolutions up to 2048 x 2048

Preview Path up to 640*480

Support for packed data formatting for YCbCr 4:2:2 formats

Preview scaler to generate smaller size image 50

Programmable frame capture rate

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11. Power Manager (PM)

Rev: 1.0.2.7

11.1

Features

Controls oscillators and PLLs

Generates clocks and resets for digital logic

Supports 2 high-speed crystal oscillators

Supports 2 PLLs

Supports 32KHz ultra-low power oscillator

On-the fly frequency change of CPU, HSB, and PB frequency

Sleep modes allow simple disabling of logic clocks, PLL’s and oscillators

Module-level clock gating through maskable peripheral clocks

Wake-up from interrupts or external pin

Generic clocks with wide frequency range provided

Automatic identification of reset sources

11.2

Description

The Power Manager (PM) controls the oscillators, PLL’s, and generates the clocks and resets in the device. The PM controls two fast crystal oscillators, as well as two PLL’s, which can multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power 32KHz oscillator is used to generate a slow clock for real-time counters.

The provided clocks are divided into synchronous and generic clocks. The synchronous clocks are used to clock the main digital logic in the device, namely the CPU, and the modules and peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous clocks, which can be tuned precisely within a wide frequency range, which makes them suitable for peripherals that require specific frequencies, such as timers and communication modules.

The PM also contains advanced power-saving features, allowing the user to optimize the power consumption for an application. The synchronous clocks are divided into four clock domains, for the CPU, and modules on the HSB, PBA, and PBB buses. The four clocks can run at different speeds, so the user can save power by running peripherals at a relatively low clock, while maintaining a high CPU performance. Additionally, the clocks can be independently changed on-the fly, without halting any peripherals. This enables the user to adjust the speed of the CPU and memories to the dynamic load of the application, without disturbing or re-configuring active peripherals.

Each module also has a separate clock, enabling the user to switch off the clock for inactive modules, to save further power. Additionally, clocks and oscillators can be automatically swithced off during idle periods by using the sleep instruction on the CPU. The system will return to normal on occurence of interrupts or an event on the WAKE_N pin.

The Power Manager also cointains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identifed by software.

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11.3

Block Diagram

Synchronous

Clock Generator

Synchronous clocks

Oscillator 0

PLL0

PLL1

Oscillator 1

Generic Clock

Generator

Generic clocks

OSCEN_N

WAKE_N

RESET_N

Power-On

Detector

Soft reset sources

OSC/PLL

Control signals

Oscillator and

PLL Control

Sleep Controller

Sleep instruction

32 KHz

Oscillator

Slow clock

Startup

Counter

Reset Controller resets

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11.4

Product Dependencies

11.4.1

I/O Lines

The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with PIO lines. The programmer must first program the PIO controller to assign these pins to their peripheral function. If the I/O pins of the PM are not used by the application, they can be used for other purposes by the PIO controller.

The PM also has a dedicated WAKE_N pin, as well as a number of pins for oscillators and

PLL’s, which do not require the PIO controller to be programmed.

11.4.2

Interrupt

The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using the PM interrupt requires the interrupt controller to be programmed first.

11.5

Functional Description

11.5.1

Oscillator 0 and 1 operation

The two main oscillators are designed to be used with an external high frequency crystal, as shown in

Figure 11-1 . See Electrical Characteristics for the allowed frequency range. The main

oscillators are enabled by default after reset, and are only switched off in sleep modes, as

described in Section 11.5.6 on page 99 . After a power-on reset, or when waking up from a sleep

mode that disabled the main oscillators, the oscillators need 128 slow clock cycles to stabilize on the correct frequency.

(1)

The PM masks the main oscillator outputs during this start-up period, to ensure that no unstable clocks propagate to the digital logic.

The oscillators can be bypassed by pulling the OSCEN_N pin high. This disables the oscillators, and an external clock must be applied on XIN. No start-up time applies to this clock.

Figure 11-1. Oscillator connections

C

2

XOUT

11.5.2

XIN

C

1

Typ. values: C

2

= C

2

= 22 pF

32 KHz oscillator operation

The 32 KHz oscillator operates similarly to Oscillator 0 and 1 described above, and is used to generate the slow clock in the device. A 32768 Hz crystal must be connected between XIN32 and XOUT32 as shown in

Figure 11-1 . The 32 KHz oscillator is is an ultra-low power design, and

remains enabled in all sleep modes except static mode, as described in Section 11.5.6 on page

1.When waking up from Stop mode using external interrupts, the startup time is 32768 slow clock cycles.

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11.5.3

PLL operation

99 . The oscillator has a rather long start-up time of 32768 clock cycles, and no clocks will be

generated in the device during this start-up time.

Note that in static sleep mode the startup counter will start at the negedge of reset and not at the posedge.

Pulling OSCEN_N high will also disable the 32 KHz oscillator, and a 32 KHz clock must be applied on the XIN32 pin. No start-up time applies to this clock.

The device contains two PLL’s, PLL0 and PLL1. These are disabled by default, but can be enabled to provide high frequency source clocks for synchronous or generic clocks. The PLL’s can take either Oscillator 0 or 1 as clock source. Each PLL has an input divider, which divides the source clock, creating the reference clock for the PLL. The PLL output is divided by a userdefined factor, and the PLL compares the resulting clock to the reference clock. The PLL will adjust its output frequency until the two compared clocks are equal, thus locking the output frequency to a multiple of the reference clock frequency.

When the PLL is switched on, or when changing the clock source or multiplication or division factor for the PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from receiving a too high frequency and thus become unstable.

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Figure 11-2. PLL with control logic and filters

Osc0 clock

Osc1 clock

0

1

PLLOSC

PLLDIV

Input

Divider

R

1

C

1

LFT

C

2

PLLMUL

Output

Divider

PLL

PLLEN

PLLOPT

Mask

Lock

Suppression

PLLCOUNT

PLL clock

LOCK

11.5.3.1

Enabling the PLL

PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source. The PLLDIV and PLLMUL bitfields must be written with the division and multiplication factor, respectively, creating the PLL frequency: f

PLL

= (PLLMUL+1) / (PLLDIV+1) • f

OSC

The LOCKn flag in ISR is set when PLLn becomes locked. The bit will stay high until cleared by writing 1 to ICR:LOCKn. The Power Manager interrupt can be triggered by writing IER:LOCKn to

1.

Note that the input frequency for the PLL must be within the range inidicated in the Electrical

Characteristics chapter. The input frequency for the PLL relates to the oscillator frequency and

PLLDIV setting as follows: f

PLLIN

= 2 • f

OSC

/ (PLLDIV+1)•

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11.5.3.2

11.5.3.3

11.5.4

Lock suppression

When using high division or multiplication factors, there is a possibility that the PLL can give false lock indications while sweeping to the correct frequency. To prevent false lock indications from setting the LOCKn flag, the lock indication can be suppressed for a number of slow clock cycles indicated in the PLLn:COUNT field. Typical start-up times can be found using the Atmel filter caluclator (see below).

Operating range selection

To use PLLn, a passive RC filter should be connected to the LFTn pin, as shown in Figure 11-2 .

Filter values depend on the PLL reference and output frequency range. Atmel provides a tool named “Atmel PLL LFT Filter Calculator AT91”. The PLL for AT32AP7001 can be selected in this tool by selecting “AT91RM9200 (58A07F)” and leave “Icp = ‘1’” (default).

Synchronous clocks

Oscillator 0 (default) or PLL0 provides the source for the main clocks, which is the common root for the synchronous clocks for the CPU, and HSB, PBA, and PBB modules. The main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tapping of this prescaler, or the undivided main clock, as long as f

CPU

≥ f

HSB

≥ f

PBA,

. The synchronous clock source can be changed on-the fly, responding to varying load in the application. The clock domains can be shut down in sleep mode, as described in

”Sleep modes” on page 99 . Additionally, the clocks for each module in the four domains can be individually

masked, to avoid power consumption in inactive modules.

Figure 11-3. Synchronous clock generation

Sleep instruction

Sleep

Controller

Osc0 clock

PLL0 clock

0

1

PLLSEL

Prescaler

0

1

Main clock

CPUSEL

CPUDIV

Mask

CPUMASK

CPU clocks

HSB clocks

PBAclocks

PBB clocks

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11.5.4.1

11.5.4.2

Selecting PLL or oscillator for the main clock

The common main clock can be connected to Oscillator 0 or PLL0. By default, the main clock will be connected to the Oscillator 0 output. The user can connect the main clock to the PLL0 output by writing the PLLSEL bit in the Main Clock Control Register (MCCTRL) to 1. This must only be done after PLL0 has been enabled, otherwise a deadlock will occur. Care should also be taken that the new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain.

Selecting synchronous clock division ratio

11.5.4.3

11.5.5

The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.

By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by writing CKSEL:CPUDIV to 1 and CPUSEL to the prescaling value, resulting in a CPU clock frequency: f

CPU

= f main

/ 2

(CPUSEL+1)

Similarly, the clock for HSB, PBA, and PBB can be divided by writing their respective bitfields.

To ensure correct operation, frequencies must be selected so that f

CPU

≥ f

HSB

≥ f

PBA,B

. Also, frequencies must never exceed the specified maximum frequency for each clock domain.

CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL bitfields. This way, it is possible to e.g. scale CPU and HSB speed according to the required performance, while keeping the PBA and PBB frequency constant.

Clock Ready flag

There is a slight delay from CKSEL is written and the new clock setting becomes effective. During this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER:CKRDY is written to

1, the Power Manager interrupt can be triggered when the new clock setting is effective. CKSEL must not be re-written while CKRDY is 0, or the system may become unstable or hang.

Peripheral clock masking

11.5.5.1

By default, the clock for all modules are enabled, regardless of which modules are actually being used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0.

When a module is not clocked, it will cease operation, and its registers cannot be read or written.

The module can be re-enabled later by writing the corresponding mask bit to 1.

A module may be connected to several clock domains, in which case it will have several mask bits.

Table 11-1

contains a list of implemented maskable clocks.

Cautionary note

Note that clocks should only be switched off if it is certain that the module will not be used.

Switching off the clock for the internal RAM will cause a problem if the stack is mapped there.

Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding PB bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.

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11.5.5.2

Mask Ready flag

Due to synchronization in the clock generator, there is a slight delay from a mask register is written until the new mask setting goes into effect. When clearing mask bits, this delay can usually be ignored. However, when setting mask bits, the registers in the corresponding module must not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR provides the required mask status information. When writing either mask register with any value, this bit is cleared. The bit is set when the clocks have been enabled and disabled according to the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the

MSKRDY bit in IER.

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Table 11-1.

Maskable module clocks in AT32AP7001.

Bit CPUMASK HSBMASK

12

13

14

15

10

11

8

9

16

31:17

6

7

4

5

2

3

0

1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

PICO

-

-

-

EBI

PBA

PBB

HRAMC

HSB-HSB Bridge

ISI

USB

-

-

-

-

DMA

-

-

-

PBAMASK

SPI0

SPI1

TWI

USART0

USART1

USART2

USART3

SSC0

SSC1

SSC2

PIOA

PIOB

PIOC

PIOD

PIOE

PSIF

PDC

-

PBBMASK

PM/EIC/RTC/WDT

INTC

HMATRIX

TC0

TC1

PWM

DAC

MCI

AC97C

ISI

USB

SMC

SDRAMC

ECC

-

-

11.5.6

11.5.6.1

Sleep modes

In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other clock domains to save power. This is activated by the sleep instruction, which takes the sleep mode index number as argument.

Entering and exiting sleep modes

The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains.

The modules will be halted regardless of the bit settings of the mask registers.

Oscillators and PLL’s can also be switched off to save power. These modules have a relatively long start-up time, and are only switched off when very low power consumption is required.

The CPU and affected modules are restarted when the sleep mode is exited. This occurs when an interrupt triggers, or the WAKE_N pin is asserted. Note that even though an interrupt is enabled in sleep mode, it may not trigger if the source module is not clocked.

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11.5.6.2

11.5.6.3

Supported sleep modes

The following sleep modes are supported. These are detailed in Table 11-2 .

•Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any interrupt, or WAKE_N pin.

•Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up sources are any interrupt from PB modules, or WAKE_N pin.

•Standby: All synchronous clocks are stopped, but oscillators and PLL’s are running, allowing quick wake-up to normal mode. Wake-up sources are RTC or external interrupt, or WAKE_N pin.

•Stop: As Standby, but Oscillator 0 and 1, and the PLL’s are stopped. 32 KHz oscillator and

RTC/WDT still operates. Wake-up sources are RTC or external interrupt, or WAKE_N pin.

•Static: All oscillators and clocks are stopped. Wake-up sources are external interrupt or

WAKE_N pin.•

Table 11-2.

Sleep modes

Index

0

1

2

3

5

Sleep Mode CPU

Idle

Frozen

Off

Off

Standby

Stop

Static

Off

Off

Off

Off

Off

Off

HSB

On

Off

Off

Off

Off

PBA,B +

GCLK

On

On

On

Off

Off

Osc0,1 +

PLL0,1

On

On

On

On

Off

Osc32 +

RTC/WDT

On

On

Precautions when entering sleep mode

Modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the module operation. This prevents erratic behavior when entering or exiting sleep mode. Please refer to the relevant module documentation for recommended actions.

Communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. This means that bus transactions are not allowed between clock domains affected by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus transaction.

The CPU and caches are automatically stopped in a safe state to ensure that all CPU bus operations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is necessary.

When entering a deeper sleep mode than Idle mode, all other HSB masters must be stopped before entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete, the CPU should perform a read operation from any register on the PB bus before executing the sleep instruction. This will stall the CPU while waiting for any pending PB operations to complete.

The Power manager will normally turn of all debug related clocks in the system in the static sleep mode, m aking it impossible for a debugger to comm unicate with the system . If a

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11.5.7

NEXUS_ACCESS or a MEMORY_ACCESS JTAG command is loaded into the instruction register before entering sleep mode some clocks are left running to enable debugging of the system.

This will increase the power consumption of the device. If the part entered static mode without a

NEXUS_ACCESS ot MEMORY_ACCESS instruction loaded into the JTAG instruction register an external reset is the only way for the debugger to get the part out of the sleep mode.

Generic clocks

When not debugging a program and using sleep modes the JTAG should always have the

IDCODE instruction loaded into the JTAG instruction register and the OCD system should be disabled. Otherwise some clocks may be left running, increasing the power consumption.

Timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly. The Power Manager contains an implementation defined number of generic clocks, that can provide a wide range of accurate clock frequencies.

Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the

Sleep Controller.

Sleep

Controller

Osc0 clock

Osc1 clock

PLL0 clock

PLL1 clock

0

1

PLLSEL

OSCSEL

Divider

DIV

0

1

DIVEN

Mask

Generic Clock

CEN

11.5.7.1

Figure 11-4. Generic clock generation

Enabling a generic clock

A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.

The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV, resulting in the output frequency: f

GCLK

= f

SRC

/

(2*(DIV+1))

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11.5.7.2

11.5.7.3

11.5.7.4

11.5.8

11.5.9

Disabling a generic clock

The generic clock can be disabled by writing CEN to 0 or entering a sleep mode that disables the PB clocks. In either case, the generic clock will be switched off on the first falling edge after the disabling event, to ensure that no glitches occur. If CEN is written to 0, the bit will still read as

1 until the next falling edge occurs, and the clock is actually switched off. When writing CEN to 0, the other bits in GCCTRL should not be changed until CEN reads as 0, to avoid glitches on the generic clock.

When the clock is disabled, both the prescaler and output are reset.

Changing clock frequency

When changing generic clock frequency by writing GCCTRL, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division setting. This prevents glitches during the transition.

Generic clock implementation

In AT32AP7001, there are 8 generic clocks. These are allocated to different functions as shown

in Table 11-3 .

Table 11-3.

Generic clock allocation

Clock number

0

Function

GCLK0 pin

3

4

1

2

5

6

GCLK1 pin

GCLK2 pin

GCLK3 pin

GCLK4 pin

Reserved for internal use

DAC

Divided PB clocks

The clock generator in the Power Manager provides divided PBA and PBB clocks for use by peripherals that require a prescaled PB clock. This is described in the documentation for the relevant modules.

The divided clocks are not directly maskable, but are stopped in sleep modes where the PB clocks are stopped.

Debug operation

During a debug session, the user may need to halt the system to inspect memory and CPU registers. The clocks normally keep running during this debug operation, but some peripherals may require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PB clocks. This is described in the documentation for the relevant modules. The divided PB clocks are always debug qualified clocks.

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Debug qualified PB clocks are stopped during debug operation. The debug system can optionally keep these clocks running during the debug operation. This is described in the documentation for the On-Chip Debug system.

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11.5.10

Reset Controller

The Reset Controller collects the various reset sources in the system and generates hard and soft resets for the digital logic.

The device contains a Power-On Detector, which keeps the system reset until power is stable.

This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device.

It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pullup, and does not need to be driven externally when negated.

Table 11-4

lists these and other reset sources supported by the Reset Controller.

RC_RCAUSE

RESET_N

Power-On

Detector

NTAE

DBR

Watchdog Reset

Reset

Controller

Soft Reset

Hard Reset

CPU, HSB,

PBA, PBB

OCD, RTC/WDT,

Clock Generator

Figure 11-5. Reset Controller block diagram

Reset sources are divided into hard and soft resets. Hard resets imply that the system could have become unstable, and virtually all logic will be reset. The clock generator, which also controls the oscillators, will also be reset. If the device is reset due to a power-on reset, or reset occurred when the device was in a sleep mode that disabled the oscillators, the normal oscillator startup time will apply.

A soft reset will reset most digital logic in the device, such as CPU, HSB, and PB modules, but not the OCD system, clock generator, Watchdog Timer and RTC, allowing some functions, including the oscillators, to remain active during the reset. The startup time from a soft reset is thus negligible. Note that all PB registers are reset, except those in the RTC/WDT. The

MCCTRL and CKSEL registers are reset, and the device will restart using Oscillator 0 as clock source for all synchronous clocks.

In addition to the listed reset types, the JTAG can keep parts of the device statically reset through the JTAG Reset Register. See JTAG documentation for details.

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The cause of the last reset can be read from the RC_RCAUSE register. This register contains one bit for each reset source, and can be identified during the boot sequence of an application to determine the proper action to be taken.

Table 11-4.

Reset types

Reset source

Power-on Reset

External

Description

Supply voltage below the power-on reset detector threshold voltage

RESET_N pin asserted

See On-Chip Debug documentation.

NanoTrace Access

Error

Watchdog Timer

OCD

See watchdog timer documentation.

See On-Chip Debug documentation

Type

Hard

Hard

Soft

Soft

Soft

32015D–AVR32–10/07

105

AT32AP7001

11.6

User Interface

0x20

0x24

0x40

0x44

0x48

0x4C

0x50

0x60

Offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x64

0x68

0x6C

0x70

0x74

0x78

0x7C

0x80 - 0xBC

0xC0

Register

Main Clock Control

Clock Select

CPU Clock Mask

HSB Clock Mask

PBA Clock Mask

PBB Clock Mask

PLL0 Control

PLL1 Control

Interrupt Enable

Interrupt Disable

Interrupt Mask

Interrupt Status

Interrupt Clear

Generic Clock Control 0

Generic Clock Control 1

Generic Clock Control 2

Generic Clock Control 3

Generic Clock Control 4

Generic Clock Control 5

Generic Clock Control 6

Generic Clock Control 7

Reserved

Reset Cause

11.6.1

Main Clock Control

Name: MCCTRL

Access Type:

Read/Write

31

-

23

-

32015D–AVR32–10/07

30

-

22

-

29

-

21

-

28

-

20

-

Register Name

MCCTRL

CKSEL

CPUMASK

HSBMASK

PBAMASK

PBBMASK

PLL0

PLL1

IER

IDR

IMR

ISR

ICR

GCCTRL0

GCCTRL1

GCCTRL2

GCCTRL3

GCCTRL4

GCCTRL5

GCCTRL6

GCCTRL7

RCAUSE

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Write-only

Write-only

Read-only

Read-only

Write-only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read

Reset

0x0

0x0

Impl. defined

Impl. defined

Impl. defined

Impl. defined

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

27

-

19

-

26

-

18

-

25

-

17

-

24

-

16

-

106

AT32AP7001

15

-

14

-

13

-

7

-

6

-

5

-

PLLSEL: PLL Select

0: Oscillator 0 is source for the main clock

11.6.2

1: PLL0 is source for the main clock

Clock Select

Name: CKSEL

Access Type:

Read/Write

4

-

12

-

3

-

11

-

2

-

10

-

9

-

1

PLLSEL

0

-

8

-

31

PBBDIV

23

PBADIV

15

HSBDIV

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

18

10

25

PBBSEL

17

PBASEL

9

HSBSEL

24

16

8

7

CPUDIV

6

-

5

-

4

-

3

-

2 1

CPUSEL

0

PBBDIV, PBBSEL: PBB Division and Clock Select

PBBDIV = 0: PBB clock equals main clock.

PBBDIV = 1: PBB clock equals main clock divided by 2

(PBBSEL+1)

.

PBADIV, PBASEL: PBA Division and Clock Select

PBADIV = 0: PBA clock equals main clock.

PBADIV = 1: PBA clock equals main clock divided by 2

(PBASEL+1)

.

HSBDIV, HSBSEL: HSB Division and Clock Select

HSBDIV = 0: HSB clock equals main clock.

HSBDIV = 1: HSB clock equals main clock divided by 2

(HSBSEL+1)

.

CPUDIV, CPUSEL: CPU Division and Clock Select

CPUDIV = 0: CPU clock equals main clock.

CPUDIV = 1: CPUclock equals main clock divided by 2

(CPUSEL+1)

.

Note that if xxxDIV is written to 0, xxxSEL should also be written to 0 to ensure correct operation.

Also note that writing this register clears ISR:CKRDY. The register must not be re-written until CKRDY goes high.

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11.6.3

Clock Mask

Name: CPU/HSB/PBA/PBBMASK

Access Type:

Read/Write

31

23

15

30

22

14

29

21

13

28

MASK[31:24]

27

20

MASK[23:16]

19

12

MASK[15:8]

11

26

18

10

25

17

9

24

16

8

7 6 5 4 3 2 1 0

MASK[7:0]

MASK: Clock Mask

If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is implementation dependent.

108

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11.6.4

PLL Control

Name: PLL0,1

Access Type:

Read/Write

31

PLLTEST

23

30

-

22

29

21

28

20

27

PLLCOUNT

26

19 18

25

17

24

16

PLLMUL

15 14 13 12 11 10 9 8

PLLDIV

7

-

6

-

5

-

4 3

PLLOPT

2 1

PLLOSC

0

PLLEN

PLLTEST: PLL Test

Reserved for internal use. Always write to 0.

PLLCOUNT: PLL Count

Specifies the number of slow clock cycles before ISR:LOCKn will be set after PLLn has been written, or after PLLn has been automatically re-enabled after exiting a sleep mode.

PLLMUL: PLL Multiply Factor

PLLDIV: PLL Division Factor

These bitfields determine the ratio of the PLL output frequency to the source oscillator frequency: f

PLL

= (PLLMUL+1)/(PLLDIV+1) f

OSC

PLLOPT: PLL Option

This field should be written to 100.

Other values are reserved.

PLLOSC: PLL Oscillator Select

0: Oscillator 0 is the source for the PLL.

1: Oscillator 1 is the source for the PLL.

PLLEN: PLL Enable

0: PLL is disabled.

1: PLL is enabled.

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11.6.5

Interrupt Enable/Disable/Mask/Status/Clear

Name: IER/IDR/IMR/ISR/ICR

Access Type:

IER/IDR/ICR: Write-only

IMR/ISR: Read-only

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

25

-

17

-

9

-

7

-

6

MSKRDY

5

CKRDY

4

VMRDY

3

VOK

2

WAKE

1

LOCK1

0

LOCK0

MSKRDY: Mask Ready

0: Either xxxMASK register has been written, and clocks are not yet enabled or disabled according to the new mask value.

1: Clocks are enabled and disabled as indicated in the xxxMASK registers.

Note: Writing ICR:MSKRDY to 1 has no effect.

CKRDY: Clock Ready

0: The CKSEL register has been written, and the new clock setting is not yet effective.

1: The synchronous clocks have frequencies as indicated in the CKSEL register.

Note: Writing ICR:CKRDY to 1 has no effect.

VMRDY, VOK

These bits are for internal use only. In ISR, the value of these bits is undefined. In IER, these bits should be written to 0.

WAKE: Wake Pin Asserted

0: The WAKE_N pin is not asserted, or has been asserted for less than one PB clock period.

1: The WAKE_N pin is asserted for longer than one PB clock period.

LOCK1: PLL1 locked

LOCK0: PLL0 locked

0: The PLL is unlocked, and cannot be used as clock source.

1: The PLL is locked, and can be used as clock source.

The effect of writing or reading the bits listed above depends on which register is being accessed:

IER (Write-only)

0: No effect

1: Enable Interrupt

IDR (Write-only)

0: No effect

1: Disable Interrupt

24

-

16

-

8

-

110

32015D–AVR32–10/07

IMR (Read-only)

0: Interrupt is disabled

1: Interrupt is enabled

ISR (Read-only)

0: An interrupt event has occurred

1: An interrupt even has not occurred

ICR (Write-only)

0: No effect

1: Clear interrupt event

AT32AP7001

32015D–AVR32–10/07

111

AT32AP7001

11.6.6

Generic Clock Control

Access Type:

Read/Write

31

-

23

-

15

30

-

22

-

14

29

-

21

-

13

28

-

20

-

12

DIV[7:0]

7

-

6

-

5

-

4

DIVEN

There is one GCCTRL register per generic clock in the design.

DIV: Division Factor

DIVEN: Divide Enable

0: The generic clock equals the undivided source clock.

1: The generic clock equals the source clock divided by 2*(DIV+1).

CEN: Clock Enable

0: Clock is stopped.

1: Clock is running.

PLLSEL: PLL Select

0: Oscillator is source for the generic clock.

1: PLL is source for the generic clock.

OSCSEL: Oscillator Select

0: Oscillator (or PLL) 0 is source for the generic clock.

1: Oscillator (or PLL) 1is source for the generic clock.

3

-

27

-

19

-

11

26

-

18

-

10

25

-

17

-

9

24

-

16

-

8

2

CEN

1

PLLSEL

0

OSCSEL

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AT32AP7001

11.6.7

Reset Cause

Name: RC_RCAUSE

Access Type:

Read-only

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

25

-

17

-

9

-

7

-

6

-

5

SERP

4

JTAG

3

WDT

2

EXT

1

-

SERP: Serious Problem Error

This bit is set if a reset occured due to a serious problem in the CPU, like Nanotrace access error, for instance.

JTAG: JTAG Reset

This bit is set if a reset occurred due to a JTAG reset.

WDT: Watchdog Timer

This bit is set if a reset occurred due to a timeout of the Watchdog Timer.

EXT: External Reset

This bit is set if a reset occurred due to assertion of the RESET_N pin.

POR: Power-On Detector

This bit is set if a reset was caused by the Power-On Detector.

0

POR

24

-

16

-

8

-

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12. Real Time Counter (RTC)

Rev: 1.0.1.1

12.1

Features

32-bit real-time counter with 16-bit prescaler

Clocked from 32 kHz oscillator

High resolution: Max count frequency 16KHz

Long delays

– Max timeout 272 years

Extremely low power consumption

Available in all sleep modes except Deepdown

Optional wrap at max value

Interrupt on wrap

12.2

Description

The Real Time Counter (RTC) enables periodic interrupts at long intervals, or accurate measurement of real-time sequences. The RTC is fed from a 16-bit prescaler, which is clocked from the 32 kHz oscillator. Any tapping of the prescaler can be selected as clock source for the RTC, enabling both high resolution and long timeouts. The prescaler cannot be written directly, but can be cleared by the user.

The RTC can generate an interrupt when the counter wraps around the top value of

0xFFFFFFFF. Optionally, the RTC can wrap at a lower value, producing accurate periodic interrupts.

12.3

Block Diagram

Figure 12-1. Real Time Counter module block diagram

RTC_TOP

32 KHz

16-bit Prescaler 32-bit counter TOPI

IRQ

RTC_VAL

12.4

Product Dependencies

12.4.1

I/O Lines

None.

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12.4.2

12.4.3

Power Management

The RTC is continously clocked, and remains operating in all sleep modes except Static.

Interrupt

The RTC interrupt line is connected to one of the internal sources of the interrupt controller.

Using the RTC interrupt requires the interrupt controller to be programmed first.

Debug Operation 12.4.4

The RTC prescaler and watchdog timer are frozen during debug operation, unless the OCD system keeps peripherals running in debug operation.

12.5

Functional Description

12.5.1

12.5.1.1

RTC operation

Source clock

12.5.1.2

12.5.1.3

The RTC is enabled by writing the EN bit in the CTRL register. This also enables the clock for the prescaler. The PSEL bitfield in the same register selects the prescaler tapping, selecting the source clock for the RTC: f

RTC

= 2

-(PSEL+1)

* 32KHz

Note that if the RTC is used in stop mode, PSEL must be 2 or higher to ensure no ticks are missed when entering or leaving sleep mode.

Counter operation

The RTC count value can be read from or written to the register VAL. The prescaler cannot be written directly, but can be reset by writing the strobe PCLR in CTRL.

RTC Interrupt

When enabled, the RTC will then up-count until it reaches 0xFFFFFFFF, and then wrap to 0x0.

Writing CTRL:TOPEN to one causes the RTC to wrap at the value written to TOP. The status bit

TOPI in ISR is set when this occurs.

Writing the TOPI bit in IER enables the RTC interrupt, while writing the corresponding bit in IDR disables the RTC interrupt. IMR can be read to see whether or not the interrupt is enabled. If enabled, an interrupt will be generated if the TOPI flag in ISR is set. The flag can be cleared by writing TOPI in ICR to one.

115

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12.6

User Interface

Offset

0x00

0x04

0x08

0x10

0x14

0x18

0x1C

0x20

Register

RTC Control

RTC Value

RTC Top

RTC Interrupt Enable

RTC Interrupt Disable

RTC Interrupt Mask

RTC Interrupt Status

RTC Interrupt Clear

AT32AP7001

Register Name

CTRL

VAL

TOP

IER

IDR

IMR

ISR

ICR

Access

Read/Write

Read/Write

Read/Write

Write-only

Write-only

Read-only

Read-only

Write-only

Reset

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

32015D–AVR32–10/07

116

AT32AP7001

12.6.1

RTC Control

Name: CTRL

Access Type:

Read/Write

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

26

-

18

-

7

-

6

-

5

-

4

-

3

-

2

TOPEN

PSEL: Prescale Select

Selects prescaler bit PSEL as source clock for the RTC.

TOPEN: Top Enable

0: RTC wraps at 0xFFFFFFFF

1: RTC wraps at RTC_TOP

PCLR: Prescaler Clear

Writing this strobe clears the prescaler. Note that this also resets the watchdog timer.

EN: Enable

0: RTC is disabled

1: RTC is enabled

10

PSEL[3:0]

9

1

PCLR

25

-

17

-

24

-

16

-

8

0

EN

117

32015D–AVR32–10/07

AT32AP7001

12.6.2

RTC Value

Name: VAL

Access Type:

Read/Write

31

23

15

30

22

14

29

21

13

28

VAL[31:24]

27

20

VAL[23:16]

19

12

VAL[15:8]

11

7 6 5 4 3

VAL[7:0]

VAL: RTC Value

This value is incremented on every rising edge of the source clock.

10

2

26

18

9

1

25

17

8

0

24

16

118

32015D–AVR32–10/07

AT32AP7001

12.6.3

RTC Top

Name: TOP

Access Type:

Read/Write

31

23

15

7

30

22

14

6

29

21

13

5

TOP: RTC Top Value

VAL wraps at this value if CTRL:TOPEN is 1.

28

TOP[31:24]

27

20

TOP[23:16]

19

12

TOP[15:8]

11

4 3

TOP[7:0]

10

2

26

18

9

1

25

17

8

0

24

16

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12.6.4

RTC Interrupt Enable/Disable/Mask/Status/Clear

Name: IER/IDR/IMR/ISR/ICR

Access Type:

IER/IDR/ICR: Write-only

IMR/ISR: Read-only

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

7

-

6

-

5

-

4

-

3

-

2

-

1

-

TOPI: Top Interrupt

VAL has wrapped at its TOP.

The effect of writing or reading this bit depends on which register is being accessed:

IER (Write-only)

0: No effect

1: Enable Interrupt

IDR (Write-only)

0: No effect

1: Disable Interrupt

IMR (Read-only)

0: Interrupt is disabled

1: Interrupt is enabled

ISR (Read-only)

0: An interrupt event has not occurred

1: An interrupt event has occurred. Note that this is only set when the RTC is configured to wrap at TOP.

ICR (Write-only)

0: No effect

1: Clear interrupt event

25

-

17

-

9

-

8

-

0

TOPI

24

-

16

-

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13. Watchdog Timer (WDT)

Rev: 1.0.1

13.1

Features

Watchdog timer with 16-bit prescaler

13.2

Description

13.3

Block Diagram

The Watchdog Timer (WDT) is fed from a 16-bit prescaler, which is clocked from the 32 kHz oscillator. Any tapping of the prescaler can be selected as clock source for the WDT.The watchdog timer must be periodically reset by software within the timeout period, ot herwise, the device is reset and starts executing from the boot vector. This allows the device to recover from a condition that has caused the system to be unstable.

Figure 13-1. Real Time Counter module block diagram

W D T _ C L R

3 2 K H z

1 6 -b it P re s c a le r

W a tc h d o g

D e te c to r

W D T _ C T R L

W a tc h d o g re s e t

13.4

Product Dependencies

13.4.1

13.4.2

13.4.3

I/O Lines

None

Power Management

The WDT is continously clocked, and remains operating in all sleep modes. However, if the

WDT is enabled and the user tries to enter a sleepmode where the 32 KHz oscillator is turned off the system will enter the STOP sleepmode instead. This is to ensure the WDT is still running.

Debug Operation

The watchdog timer is frozen during debug operation, unless the OCD system keeps peripherals running in debug operation.

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13.5

Functional Description

13.5.1

Watchdog Timer

The WDT is enabled by writing the EN bit in the CTRL register. This also enables the clock for the prescaler. The PSEL bitfield in the same register selects the watchdog timeout period:

T

WDT

= 2

(PSEL+1)

* 30.518

μ s

To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with the KEY field set to 0x55, then 0xAA without changing the other bitfields. Failure to do so will cause the write operation to be ignored, and CTRL does not change value.

The CLR register must be written with any value with regular intervals shorter than the watchdog timeout period. Otherwise, the device will receive a soft reset, and the code will start executing from the boot vector.

32015D–AVR32–10/07

122

AT32AP7001

13.6

User Interface

Offset

0x30

0x34

13.6.1

WDT Control

Name: CTRL

Access Type:

Read/Write

Register

WDT Control

WDT Clear

Register Name

CTRL

CLR

Access

Read/Write

Write-only

Reset

0x0

0x0

31

23

-

15

-

30

22

-

14

-

29

21

-

13

-

20

-

12

-

28

KEY[7:0]

27

19

-

11

26 25

18

-

10

PSEL[3:0]

9

17

-

24

16

-

8

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

EN

KEY

This bitfield must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This bitfield always reads as zero.

PSEL: Prescale Select

Prescaler bit PSEL is used as watchdog timeout period.

EN: WDT Enable

0: WDT is disabled.

1: WDT is enabled.

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13.6.2

WDT Clear

Name: CLR

Access Type:

Write-only

When the watchdog timer is enabled, this register must be periodically written, with any value, within the watchdog timeout period, to prevent a watchdog reset.

32015D–AVR32–10/07

124

AT32AP7001

14. Interrupt Controller (INTC)

Rev: 1.0.1.0

14.1

Description

The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for regular, maskable interrupts, and a Non-Maskable Interrupt (NMI).

14.2

Block Diagram

The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register

(IPR) and an Interrupt Request Register (IRR). The IPRs are used to assign a priority level and an autovector to each group, and the IRRs are used to identify the active interrupt request within each group. If a group has only one interrupt request line, an active interrupt group uniquely identifies the active interrupt request line, and the corresponding IRR is not needed. The INTC also provides one Interrupt Cause Register (ICR) per priority level. These registers identify the group that has a pending interrupt of the corresponding priority level. If several groups have an pending interrupt of the same level, the group with the highest number takes priority.

Figure 14-1 on page 125 gives an overview of the INTC. The grey boxes represent registers that

can be accessed via the Peripheral Bus (PB). The interrupt requests from the peripherals

(IREQn) and the NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of the figure.

Figure 14-1. Overview of the Interrupt Controller

Interrupt Controller

NMIREQ

CPU

Masks

SREG masks

I[3-0]M

GM

IREQ63

IREQ34

IREQ33

IREQ32

IREQ31

IREQ2

IREQ1

IREQ0

OR

GrpReqN

IRRn

OR

GrpReq1

Request masking

ValReq1

IPR1

INT_level, offset

IRR1

ValReqN

IPRn

INT_level, offset

ValReq0

OR

GrpReq0

IPR0 INT_level, offset

IRR0

IRR registers

IPR registers ICR registers

INTLEVEL

AUTOVECTOR

14.3

Operation

All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt

Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that is active. If several IREQs within the same group is active, the interrupt service routine must pri-

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14.3.1

14.3.2

14.3.3

oritize between them. All of the input lines in each group are logically-ORed together to form the

GrpReqN lines, indicating if there is a pending interrupt in the corresponding group.

The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to

INT3 by associating each group with the INTLEVEL field in the corresponding IPR register. The

GrpReq inputs are then masked by the I0M, I1M, I2M, I3M and GM mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted.

The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the pending interrupt of the highest priority. If a NMI interrupt is pending, it automatically gets highest priority of any pending interrupt. If several interrupt groups of the highest pending interrupt level have pending interrupts, the interrupt group with the highest number is selected.

Interrupt level (INTLEVEL) and handler autovector offset (AUTOVECTOR) of the selected interrupt are transmitted to the CPU for interrupt handling and context switching. The CPU doesn't need to know which interrupt is requesting handling, but only the level and the offset of the handler address. The IRR registers contain the interrupt request lines of the groups and can be read via PB for checking which interrupts of the group are actually active.

Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely interrupt level 3 mask (I3M) to interrupt level 0 mask (I0M), and Global interrupt mask (GM). An interrupt request is masked if either the Global interrupt mask or the corresponding interrupt level mask bit is set.

Non maskable interrupts

A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vector address defined by the AVR32 architecture, so AUTOVECTOR is undefined when

INTLEVEL indicates that an NMI is pending.

CPU response

When the CPU receives an interrupt request it checks if any other exceptions are pending. If no exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt handling, the corresponding interrupt mask bit is set automatically for this and lower levels in status register. E.g, if interrupt on level 3 is approved for handling the interrupt mask bits I3M, I2M,

I1M, and I0M are set in status register. If interrupt on level 1 is approved the masking bits I1M, and I0M are set in status register. The handler offset is calculated from AUTOVECTOR and

EVBA and a change-of-flow to this address is performed.

Setting of the interrupt mask bits prevents the interrupts from the same and lower levels to be passed trough the interrupt controller. Setting of the same level mask bit prevents also multiple request of the same interrupt to happen.

It is the responsibility of the handler software to clear the interrupt request that caused the interrupt before returning from the interrupt handler. If the conditions that caused the interrupt are not cleared, the interrupt request remains active.

Clearing an interrupt request

Clearing of the interrupt request is done by writing to registers in the corresponding peripheral module, which then clears the corresponding NMIREQ/IREQ signal.

The recommended way of clearing an interrupt request is a store operation to the controlling peripheral register, followed by a dummy load operation from the same register. This causes a

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pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared.

14.4

User Interface

This chapter lists the INTC registers are accessible through the PB bus. The registers are used to control the behaviour and read the status of the INTC.

14.4.1

Memory Map

The following table shows the address map of the INTC registers, relative to the base address of the INTC.

Table 14-1.

INTC address map

Offset

0

260

...

508

512

4

...

252

256

Register

Interrupt Priority Register 0

Interrupt Priority Register 1

...

Interrupt Priority Register 63

Interrupt Request Register 0

Interrupt Request Register 1

...

Name

IPR0

IPR1

...

IPR63

IRR0

IRR1

...

Interrupt Request Register 63 IRR63

Interrupt Cause Register 3 ICR3

516

520

524

Interrupt Cause Register 2

Interrupt Cause Register 1

Interrupt Cause Register 0

ICR2

ICR1

ICR0

Access

Read/Write

Read/Write

...

Read/Write

Read-only

Read-only

...

Read-only

Read-only

Read-only

Read-only

Read-only

N/A

N/A

N/A

N/A

N/A

Reset Value

0x0000_0000

0x0000_0000

...

0x0000_0000

N/A

N/A

...

14.4.2

Interrupt Request Map

The mapping of interrupt requests from peripherals to INTREQs is presented in the Peripherals

Section.

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14.4.3

Interrupt Request Registers

Register Name:

Access Type:

IRR0...IRR63

Read-only

31 30 29 28 27 26 25 24

IRR(32*x+31) IRR(32*x+30) IRR(32*x+29) IRR(32*x+28) IRR(32*x+27) IRR(32*x+26) IRR(32*x+25) IRR(32*x+24)

23 22 21 20 19 18 17 16

IRR(32*x+23) IRR(32*x+22) IRR(32*x+21) IRR(32*x+20) IRR(32*x+19) IRR(32*x+18) IRR(32*x+17) IRR(32*x+16)

15 14 13 12 11 10 9

IRR(32*x+15) IRR(32*x+14) IRR(32*x+13) IRR(32*x+12) IRR(32*x+11) IRR(32*x+10) IRR(32*x+9)

8

IRR(32*x+8)

7

IRR(32*x+7)

6

IRR(32*x+6)

5

IRR(32*x+5)

4

IRR(32*x+4)

3

IRR(32*x+3)

2

IRR(32*x+2)

1

IRR(32*x+1)

0

IRR(32*x+0)

• IRR: Interrupt Request line

0 = No interrupt request is pending on this input request input.

1 = An interrupt request is pending on this input request input.

The are 64 IRRs, one for each group. Each IRR has 32 bits, one for each possible interrupt request, for a total of 2048 possible input lines. The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The IRRs are sampled continuously, and are read-only.

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14.4.4

Interrupt Priority Registers

Register Name:

Access Type:

31

INTLEVEL[1:0]

30 29

-

23

-

15

-

7

22

-

14

-

6

21

-

13

5

IPR0...IPR63

Read/Write

28

-

20

-

12

27

-

19

-

4

11 10

AUTOVECTOR[13:8]

3

AUTOVECTOR[7:0]

2

26

-

18

-

• INTLEVEL: Interrupt level associated with this group

Indicates the EVBA-relative offset of the interrupt handler of the corresponding group:

25

-

17

-

9

1

24

-

16

-

8

0

0

0

1

1

INTLEVEL[1:0]

0

1

0

1

Priority

INT0

INT1

INT2

INT3

• AUTOVECTOR: Autovector address for this group

Handler offset is used to give the address of the interrupt handler. The least significant bit should be written to zero to give halfword alignment

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14.4.5

Interrupt Cause Registers

Register Name:

Access Type:

31

-

30

-

29

-

23

-

15

-

7

-

22

-

14

-

6

-

21

-

13

-

5

ICR0...ICR3

Read-only

28

-

20

-

12

-

4

11

-

3

27

-

19

-

10

-

2

26

-

18

-

9

-

1

25

-

17

-

8

-

0

24

-

16

-

CAUSE

• CAUSE: Interrupt group causing interrupt of priority n

ICRn identifies the group with the highest priority that has a pending interrupt of level n. If no interrupts of level n are pending, or the priority level is masked, the value of ICRn is UNDEFINED.

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15. External Interrupt Controller (EIC)

Rev: 1.0.0.1

15.1

Features

Dedicated interrupt requests for each interrupt

Individually maskable interrupts

Interrupt on rising or falling edge

Interrupt on high or low level

Maskable NMI interrupt

15.2

Description

15.3

Block Diagram

The External Interrupt Controller allows 4 pins to be configured as external interrupts. Each pin has its own interrupt request, and can be individually masked. Each pin can generate an interrupt on rising or falling edge, or high or low level.

The module also masks the NMI_N pin, which generates the NMI interrupt for the CPU.

Figure 15-1. External Interrupt Controller block diagram

EXTINTn

Sync

LEVEL

MODE

Edge/Level

Detector

ICR

INTn

IER

IDR

Mask

IRQn

ISR IMR

NMIC

Mask

NMI_IRQ

NMI_N

Sync

15.4

Product Dependencies

15.4.1

I/O Lines

The External Interrupt and NMI pins are multiplexed with PIO lines. To act as external interrupts, these pins must be configured as inputs pins by the PIO controller. It is also possible to trigger the interrupt by driving these pins from registers in the PIO controller, or another peripheral output connected to the same pin.

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15.4.2

Power Management

Edge triggered interrupts are available in all sleep modes except Deepdown. Level triggered interrupts and the NMI interrupt are available in all sleep modes.

Interrupt 15.4.3

The EIC interrupt lines are connected to internal sources of the interrupt controller. Using the

External Interrutps requires the interrupt controller to be programmed first.

Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed.

15.5

Functional Description

15.5.1

15.5.1.1

15.5.2

External Interrupts

Each external interrupt pin EXTINTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and

LEVEL registers. Each interrupt n has a bit INTn in each of these registers.

Similarly, each interrupt has a corresponding bit in each of the interrupt control and status registers. Writing 1 to the INTn strobe in IER enables the external interrupt on pin EXTINTn, while writing 1 to INTn in IDR disables the external interrupt. IMR can be read to check which interrupts are enabled. When the interrupt triggers, the corresponding bit in ISR will be set. For edge triggered interrupts, the flag remains set until the corresponding strobe bit in ICR is written to 1.

For level triggered interrupts, the flag remains set for as long as the interrupt condition is present on the pin.

Writing INTn in MODE to 0 enables edge triggered interrupts, while writing the bit to 1 enables level triggered interrupts.

If EXTINTn is configured as an edge triggered interrupt, writing INTn in EDGE to 0 will trigger the interrupt on falling edge, while writing the bit to 1 will trigger the interrupt on rising edge.

If EXTINTn is configured as a level triggered interrupt, writing INTn in LEVEL to 0 will trigger the interrupt on low level, while writing the bit to 1 will trigger the interrupt on high level.

Synchronization of external interrupts

The pin value of the EXTINTn pins is normally synchronized to the CPU clock, so spikes shorter than a CPU clock cycle are not guaranteed to produce an interrupt. In Stop mode, spikes shorter than a 32KHz clock cycle are not guaranteed to produce an interrupt. In Deepdown mode, only unsynchronized level interrupts remain active, and any short spike on this interrupt will wake up the device.

NMI Control

The Non-Maskable Interrupt of the CPU is connected to the NMI_N pin through masking logic in the External Interrupt Controller. This masking ensures that the NMI will not trigger before the

CPU has been set up to handle interrupts. Writing the EN bit in the NMIC register enables the

NMI interrupt, while writing EN to 0 disables the NMI interrupt. When enabled, the interrupt triggers whenever the NMI_N pin is negated.

The NMI_N pin is synchronized the same way as external level interrupts.

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15.6

User Interface

Offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x24

Register

EIC Interrupt Enable

EIC Interrupt Disable

EIC Interrupt Mask

EIC Interrupt Status

EIC Interrupt Clear

External Interrupt Mode

External Interrupt Edge

External Interrupt Level

External Interrupt NMI Control

Register Name

IER

IDR

IMR

ISR

ICR

MODE

EDGE

LEVEL

NMIC

Access

Write-only

Write-only

Read-only

Read-only

Write-only

Read/Write

Read/Write

Read/Write

Read/Write

Reset

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

32015D–AVR32–10/07

133

AT32AP7001

15.6.1

EIC Interrupt Enable/Disable/Mask/Status/Clear

Name: IER/IDR/IMR/ISR/ICR

Access Type:

IER/IDR/ICR: Write-only

IMR/ISR: Read-only

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

7

-

6

-

5

-

4

-

3

INT3

2

INT2

1

INT1

INTn: External Interrupt n

0: External Interrupt has not triggered

1: External Interrupt has triggered

The effect of writing or reading the bits listed above depends on which register is being accessed:

IER (Write-only)

0: No effect

1: Enable Interrupt

IDR (Write-only)

0: No effect

1: Disable Interrupt

IMR (Read-only)

0: Interrupt is disabled

1: Interrupt is enabled

ISR (Read-only)

0: An interrupt event has occurred

1: An interrupt even has not occurred

ICR (Write-only)

0: No effect

1: Clear interrupt event

25

-

17

-

9

-

8

-

0

INT0

24

-

16

-

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15.6.2

External Interrupt Mode/Edge/Level

Name: MODE/EDGE/LEVEL

Access Type:

Read/Write

31

-

23

-

15

-

7

-

6

-

INTn: External Interrupt n

30

-

22

-

14

-

The bit interpretation is register specific:

MODE

0: Interrupt is edge triggered

1: Interrupt is level triggered

EDGE

0: Interrupt triggers on falling edge

LEVEL

1: Interrupt triggers on rising edge

0: Interrupt triggers on low level

1: Interrupt triggers on high level

29

-

21

-

5

-

13

-

28

-

20

-

4

-

12

-

27

-

19

-

11

-

3

INT3

26

-

18

-

10

-

2

INT2

25

-

17

-

9

-

1

INT1

24

-

16

-

8

-

0

INT0

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15.6.3

NMI Control

Name: NMIC

Access Type:

Read/Write

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

7

-

6

-

5

-

4

-

3

-

EN: Enable

0: NMI disabled. Asserting the NMI pin does not generate an NMI request.

1: NMI enabled. Asserting the NMI pin generate an NMI request.

27

-

19

-

11

-

26

-

18

-

2

-

10

-

25

-

17

-

1

-

9

-

24

-

16

-

8

-

0

EN

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16. HSB Bus Matrix (HMATRIX)

Rev: 2.2.0.1

16.1

Features

User Interface on peripheral bus

Configurable Number of Masters (Up to sixteen)

Configurable Number of Slaves (Up to sixteen)

One Decoder for Each Master

Three Different Memory Mappings for Each Master (Internal and External boot, Remap)

One Remap Function for Each Master

Programmable Arbitration for Each Slave

– Round-Robin

– Fixed Priority

Programmable Default Master for Each Slave

– No Default Master

– Last Accessed Default Master

– Fixed Default Master

One Cycle Latency for the First Access of a Burst

Zero Cycle Latency for Default Master

One Special Function Register for Each Slave (Not dedicated)

16.2

Description

The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves.

The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16

Special Function Registers (SFR) that allow the Bus Matrix to support application specific features.

16.3

Memory Mapping

The Bus Matrix provides one decoder for every HSB Master Interface. The decoder offers each

HSB Master several memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different HSB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible.

The Bus Matrix user interface provides Master Remap Control Register (MRCR) that performs remap action for every master independently.

16.4

Special Bus Granting Mechanism

The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism reduces latency at first access of a burst or single transfer. This bus granting mechanism sets a different default master for every slave.

At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master.

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16.4.1

16.4.2

16.4.3

No Default Master

At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits low-power mode.

Last Access Master

At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request.

Fixed Default Master

At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master, the fixed master does not change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related SCFG).

To change from one kind of default master to another, the Bus Matrix user interface provides the

Slave Configuration Registers, one for each slave, that set a default master for each slave. The

Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The

2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description.

16.5

Arbitration

16.5.1

The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter per HSB slave is provided, thus arbitrating each slave differently.

The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types for each slave:

1.

Round-Robin Arbitration (default)

2.

Fixed Priority Arbitration

This choice is made via the field ARBT of the Slave Configuration Registers (SCFG).

Each algorithm may be complemented by selecting a default master configuration for each slave.

When a re-arbitration must be done, specific conditions apply. See

Section 16.5.1 ”Arbitration

Rules” on page 138

.

Arbitration Rules

Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles:

1.

Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it.

2.

Single Cycles: When a slave is currently doing a single access.

3.

End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is man-

aged differently for undefined length burst. See Section “16.5.1.1” on page 139.

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16.5.1.1

4.

Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken.

See Section “16.5.1.2” on page 139.

Undefined Length Burst Arbitration

In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected from among the following five possibilities:

1.

Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken.

2.

One beat bursts: Predicted end of burst is generated at each single transfer inside the

INCP transfer.

3.

Four beat bursts: Predicted end of burst is generated at the end of each four beat boundary inside INCR transfer.

4.

Eight beat bursts: Predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer.

5.

Sixteen beat bursts: Predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer.

This selection can be done through the field ULBT of the Master Configuration Registers

(MCFG).

Slot Cycle Limit Arbitration 16.5.1.2

16.5.2

16.5.2.1

The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave

Configuration Register (SCFG) and decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word transfer.

Round-Robin Arbitration

This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is first serviced, then the others are serviced in a round-robin manner.

There are three round-robin algorithms implemented:

• Round-Robin arbitration without default master

• Round-Robin arbitration with last default master

• Round-Robin arbitration with fixed default master

Round-Robin Arbitration without Default Master

This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending, the slave is disconnected from all masters.

This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts.

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16.5.2.2

16.5.2.3

16.5.3

Round-Robin Arbitration with Last Default Master

This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. Other non privileged masters still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses.

Round-Robin Arbitration with Fixed Default Master

This is another biased round-robin algorithm. It allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master. Every request attempted by this fixed default master will not cause any latency whereas other non privileged masters will still get one latency cycle. This technique can be used for masters that mainly perform single accesses.

Fixed Priority Arbitration

This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master requests are active at the same time, the master with the highest priority number is serviced first. If two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first.

For each slave, the priority of each master may be defined through the Priority Registers for

Slaves (PRAS and PRBS).

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16.6

User Interface

Table 16-1.

Register Mapping

Offset Register

0x0060

0x0064

0x0068

0x006C

0x0070

0x0074

0x0078

0x007C

0x0040

0x0044

0x0048

0x004C

0x0050

0x0054

0x0058

0x005C

0x0080

0x0084

0x0088

0x0020

0x0024

0x0028

0x002C

0x0030

0x0034

0x0038

0x003C

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

Master Configuration Register 0

Master Configuration Register 1

Master Configuration Register 2

Master Configuration Register 3

Master Configuration Register 4

Master Configuration Register 5

Master Configuration Register 6

Master Configuration Register 7

Master Configuration Register 8

Master Configuration Register 9

Master Configuration Register 10

Master Configuration Register 11

Master Configuration Register 12

Master Configuration Register 13

Master Configuration Register 14

Master Configuration Register 15

Slave Configuration Register 0

Slave Configuration Register 1

Slave Configuration Register 2

Slave Configuration Register 3

Slave Configuration Register 4

Slave Configuration Register 5

Slave Configuration Register 6

Slave Configuration Register 7

Slave Configuration Register 8

Slave Configuration Register 9

Slave Configuration Register 10

Slave Configuration Register 11

Slave Configuration Register 12

Slave Configuration Register 13

Slave Configuration Register 14

Slave Configuration Register 15

Priority Register A for Slave 0

Priority Register B for Slave 0

Priority Register A for Slave 1

32015D–AVR32–10/07

SCFG6

SCFG7

SCFG8

SCFG9

SCFG10

SCFG11

SCFG12

SCFG13

MCFG14

MCFG15

SCFG0

SCFG1

SCFG2

SCFG3

SCFG4

SCFG5

SCFG14

SCFG15

PRAS0

PRBS0

PRAS1

Name

MCFG0

MCFG1

MCFG2

MCFG3

MCFG4

MCFG5

MCFG6

MCFG7

MCFG8

MCFG9

MCFG10

MCFG11

MCFG12

MCFG13

AT32AP7001

0x00000002

0x00000002

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000010

0x00000000

0x00000000

0x00000000

Reset Value

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

0x00000002

141

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Table 16-1.

Register Mapping (Continued)

Offset Register

0x00AC

0x00B0

0x00B4

0x00B8

0x00BC

0x00C0

0x00C4

0x00C8

0x008C

0x0090

0x0094

0x0098

0x009C

0x00A0

0x00A4

0x00A8

Priority Register B for Slave 1

Priority Register A for Slave 2

Priority Register B for Slave 2

Priority Register A for Slave 3

Priority Register B for Slave 3

Priority Register A for Slave 4

Priority Register B for Slave 4

Priority Register A for Slave 5

Priority Register B for Slave 5

Priority Register A for Slave 6

Priority Register B for Slave 6

Priority Register A for Slave 7

Priority Register B for Slave 7

Priority Register A for Slave 8

Priority Register B for Slave 8

Priority Register A for Slave 9

0x00CC

0x00D0

0x00D4

0x00D8

0x00DC

0x00E0

0x00E4

0x00E8

Priority Register B for Slave 9

Priority Register A for Slave 10

Priority Register B for Slave 10

Priority Register A for Slave 11

Priority Register B for Slave 11

Priority Register A for Slave 12

Priority Register B for Slave 12

Priority Register A for Slave 13

0x00EC

0x00F0

0x00F4

0x00F8

Priority Register B for Slave 13

Priority Register A for Slave 14

Priority Register B for Slave 14

Priority Register A for Slave 15

0x00FC

0x0100

Priority Register B for Slave 15

Master Remap Control Register

0x0104 - 0x010C Reserved

0x0110 Special Function Register 0

0x0114

0x0118

0x011C

0x0120

Special Function Register 1

Special Function Register 2

Special Function Register 3

Special Function Register 4

32015D–AVR32–10/07

SFR0

SFR1

SFR2

SFR3

SFR4

PRBS12

PRAS13

PRBS13

PRAS14

PRBS14

PRAS15

PRBS15

MRCR

PRBS8

PRAS9

PRBS9

PRAS10

PRBS10

PRAS11

PRBS11

PRAS12

PRBS4

PRAS5

PRBS5

PRAS6

PRBS6

PRAS7

PRBS7

PRAS8

Name

PRBS1

PRAS2

PRBS2

PRAS3

PRBS3

PRAS4

AT32AP7001

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Reset Value

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

142

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Table 16-1.

Register Mapping (Continued)

Offset Register

0x0124

0x0128

0x012C

0x0130

0x0134

0x0138

0x013C

0x0140

Special Function Register 5

Special Function Register 6

Special Function Register 7

Special Function Register 8

Special Function Register 9

Special Function Register 10

Special Function Register 11

Special Function Register 12

0x0144

0x0148

Special Function Register 13

Special Function Register 14

0x014C Special Function Register 15

0x0150 - 0x01F8 Reserved

Name

SFR5

SFR6

SFR7

SFR8

SFR9

SFR10

SFR11

SFR12

SFR13

SFR14

SFR15

AT32AP7001

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Reset Value

143

32015D–AVR32–10/07

AT32AP7001

16.6.1

Bus Matrix Master Configuration Registers

Register Name:

Access Type:

31

MCFG0...MCFG15

Read/Write

30

29

28

23

15

7

22

14

6

21

13

5

20

12

4

11

3

27

19

10

2

26

18

9

1

ULBT

25

17

8

0

24

16

• ULBT: Undefined Length Burst Type

0: Infinite Length Burst

No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.

1: Single Access

The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst.

2: Four Beat Burst

The undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end.

3: Eight Beat Burst

The undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end.

4: Sixteen Beat Burst

The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end.

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16.6.2

Bus Matrix Slave Configuration Registers

Register Name:

Access Type:

31

SCFG0...SCFG15

Read/Write

30

29

28

23

22

21

27

20 19

FIXED_DEFMSTR

15

7

14

6

13

5

12

11

4

SLOT_CYCLE

3

10

2

26

18

9

1

25

24

ARBT

17 16

DEFMSTR_TYPE

8

0

• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst

When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.

This limit has been placed to avoid locking a very slow slave when very long bursts are used.

This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.

• DEFMSTR_TYPE: Default Master Type

0: No Default Master

At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.

This results in a one cycle latency for the first access of a burst transfer or for a single access.

1: Last Default Master

At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.

This results in not having one cycle latency when the last master tries to access the slave again.

2: Fixed Default Master

At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.

This results in not having one cycle latency when the fixed master tries to access the slave again.

• FIXED_DEFMSTR: Fixed Default Master

This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.

• ARBT: Arbitration Type

0: Round-Robin Arbitration

1: Fixed Priority Arbitration

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AT32AP7001

16.6.3

Bus Matrix Priority Registers A For Slaves

Register Name:

Access Type:

31

PRAS0...PRAS15

Read/Write

30

M7PR

29 28

23 22 21 20

M5PR

27

19

26

18

M6PR

M4PR

25

17

15 14 13 12 11 10 9

M3PR M2PR

7 6 5 4 3 2 1

M1PR M0PR

• MxPR: Master x Priority

Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.

24

16

8

0

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AT32AP7001

16.6.4

Bus Matrix Priority Registers B For Slaves

Register Name:

Access Type:

31

PRBS0...PRBS15

Read/Write

30

M15PR

29 28

23 22 21 20

M13PR

27

19

26

18

M14PR

M12PR

25

17

15 14 13 12 11 10 9

M11PR M10PR

7 6 5 4 3 2 1

M9PR M8PR

• MxPR: Master x Priority

Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.

24

16

8

0

147

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AT32AP7001

16.6.5

Bus Matrix Master Remap Control Register

Register Name:

Access Type:

Reset:

31

MRCR

Read/Write

0x0000_0000

30

29

28

23

15

RCB15

22

14

RCB14

21

13

RCB13

20

12

RCB12

7

RCB7

6

RCB6

5

RCB5

4

RCB4

• RCB: Remap Command Bit for Master x

0: Disable remapped address decoding for the selected Master

1: Enable remapped address decoding for the selected Master

3

RCB3

27

19

11

RCB11

26

18

10

RCB10

2

RCB2

25

17

9

RCB9

1

RCB1

24

16

8

RCB8

0

RCB0

148

32015D–AVR32–10/07

AT32AP7001

16.6.6

Bus Matrix Special Function Registers

Register Name:

Access Type:

Reset:

31

SFR0...SFR15

Read/Write

30 29 28 27

SFR

23 22 21 20 19

SFR

15 14 13 12 11

SFR

7 6 5 4 3

SFR

• SFR: Special Function Register Fields

The bitfields of these registers are described in the Peripherals chapter.

26

18

10

2

25

17

9

1

24

16

8

0

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AT32AP7001

17. External Bus Interface (EBI)

Rev: 1.0.1.2

17.1

Features

Optimized for Application Memory Space support

Integrates Three External Memory Controllers:

– Static Memory Controller

– SDRAM Controller

– ECC Controller

Additional Logic for NAND Flash/SmartMedia

TM

and CompactFlash

TM

Support

– NAND Flash support: 8-bit as well as 16-bit devices are supported

– CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled.

Optimized External Bus:

– 16- or 32-bit Data Bus

– Up to 26-bit Address Bus, Up to 64-Mbytes Addressable

– Optimized pin multiplexing to reduce latencies on External Memories

Up to 6 Chip Selects, Configurable Assignment:

– Static Memory Controller on NCS0

– SDRAM Controller or Static Memory Controller on NCS1

– Static Memory Controller on NCS2

– Static Memory Controller on NCS3, Optional NAND Flash Support

– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash

TM

Support

17.2

Description

The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an AVR32 device. The Static

Memory, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI.

These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM.

The EBI also supports the CompactFlash and the NAND Flash/SmartMedia protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the

EBI handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or

32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (NCS[5:0]) and several control pins that are generally multiplexed between the different external Memory

Controllers.

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32015D–AVR32–10/07

AT32AP7001

17.3

Block Diagram

17.3.1

External Bus Interface

Figure 17-1

shows the organization of the External Bus Interface.

Figure 17-1. Organization of the External Bus Interface

Bus Matrix

External Bus Interface 0

HSB

SDRAM

Controller

Address Decoders

Static

Memory

Controller

Chip Select

Assignor

CompactFlash

Logic

NAND Flash

SmartMedia

Logic

ECC

Controller

User Interface

MUX

Logic

PIO

D[15:0]

A0/NBS0

A1/NWR2/NBS2

A[15:2], A[22:18]

A16/BA0

A17/BA1

NCS0

NCS1/SDCS

NCS3/NANDCS

NRD/NOE/CFOE

NWR0/NWE/CFWE

NWR1/NBS1/CFIO

NWR3/NBS3/CFIO

SDCK

SDCKE

RAS

CAS

SDWE

SDA10

NANDOE

NANDWE

D[31:16]

A[25:23]

CFRNW

NCS4/CFCS0

NCS5/CFCS1

NCS2

NWAIT

CFCE1

CFCE2

Peripheral Bus

151

32015D–AVR32–10/07

AT32AP7001

32015D–AVR32–10/07

152

AT32AP7001

17.4

I/O Lines Description

Table 17-1.

EBI I/O Lines Description

Name Function

D0 - D31

A0 - A25

NWAIT

NCS0 - NCS5

NWR0 - NWR3

NOE

NRD

NWE

NBS0 - NBS3

CFCE1 - CFCE2

CFOE

CFWE

CFIOR

CFIOW

CFRNW

CFCS0 - CFCS1

NANDCS

NANDOE

NANDWE

SDCK

SDCKE

SDCS

BA0 - BA1

SDWE

RAS - CAS

NWR0 - NWR3

NBS0 - NBS3

SDA10

EBI

Data Bus

Address Bus

External Wait Signal

SMC

Chip Select Lines

Write Signals

Output Enable

Read Signal

Write Enable

Byte Mask Signals

EBI for CompactFlash Support

CompactFlash Chip Enable

CompactFlash Output Enable

CompactFlash Write Enable

CompactFlash I/O Read Signal

CompactFlash I/O Write Signal

CompactFlash Read Not Write Signal

CompactFlash Chip Select Lines

EBI for NAND Flash/SmartMedia Support

NAND Flash Chip Select Line

NAND Flash Output Enable

NAND Flash Write Enable

SDRAM Controller

SDRAM Clock

SDRAM Clock Enable

SDRAM Controller Chip Select Line

Bank Select

SDRAM Write Enable

Row and Column Signal

Write Signals

Byte Mask Signals

SDRAM Address 10 Line

Type

I/O

Output

Input

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Active Level

High

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

153

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AT32AP7001

Depending on the Memory Controller in use, all signals are not connected directly through the

Mux Logic.

Table 17-2 on page 154 details the connections between the two Memory Controllers and the

EBI pins.

Table 17-2.

EBI Pins and Memory Controllers I/O Lines Connections

EBI Pins

NWR1/NBS1/CFIOR

SDRAMC I/O Lines

NBS1

SMC I/O Lines

NWR1/NUB

A0/NBS0

A1/NBS2/NWR2

A[11:2]

SDA10

A12

A[14:13]

A[22:15]

D[31:0]

Not Supported

Not Supported

SDRAMC_A[9:0]

SDRAMC_A10

Not Supported

SDRAMC_A[12:11]

Not Supported

D[31:0]

SMC_A0/NLB

SMC_A1

SMC_A[11:2]

Not Supported

SMC_A12

SMC_A[14:13]

SMC_A[22:15]

D[31:0]

154

AT32AP7001

17.5

Application Example

17.5.1

Hardware Interface

Table 17-3 on page 155 details the connections to be applied between the EBI pins and the

external devices for each Memory Controller.

Table 17-3.

EBI Pins and External Static Devices Connections

Pins of the Interfaced Device

8-bit Static

Device

2 x 8-bit

Static

Devices

16-bit Static

Device

4 x 8-bit

Static

Devices

Signals

Controller

D0 - D7

D8 - D15

D16 - D23

D24 - D31

A0/NBS0

A1/NWR2/NBS2

A2 - A22

A23 - A25

NCS0

NCS1/SDCS

NCS2

NCS3/NANDCS

NCS4/CFCS0

NCS5/CFCS1

NRD/NOE/CFOE

NWR0/NWE

NWR1/NBS1

NWR3/NBS3

CS

CS

OE

WE

CS

CS

CS

CS

D0 - D7

A0

A1

A[2:22]

A[23:25]

CS

CS

OE

WE

(1)

WE

(1)

CS

CS

CS

CS

D0 - D7

D8 - D15

A0

A[1:21]

A[22:24]

CS

CS

OE

WE

CS

CS

CS

CS

NUB

D0 - D7

D8 - D15

NLB

A0

A[1:21]

A[22:24]

SMC

D0 - D7

D8 - D15

D16 - D23

D24 - D31

WE

(2)

A[0:20]

A[21:23]

CS

CS

CS

CS

CS

CS

OE

WE

(2)

WE

(2)

WE

(2)

2 x 16-bit

Static

Devices

D0 - D7

D8 - 15

D16 - D23

D24 - D31

NLB

(3)

NLB

(4)

A[0:20]

A[21:23]

CS

CS

CS

CS

CS

CS

OE

WE

NUB

(3)

NUB

(4)

32-bit Static

Device

D0 - D7

D8 - 15

D16 - D23

D24 - D31

BE0

(5)

BE2

(5)

A[0:20]

A[21:23]

CS

CS

CS

CS

CS

CS

OE

WE

BE1

(5)

BE3

(5)

Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.

2. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3)

3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.

4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.

5. BEx: Byte x Enable (x = 0,1,2 or 3)

155

32015D–AVR32–10/07

AT32AP7001

Signals

Controller

A12

A13 - A14

A15

A16/BA0

A17/BA1

A18 - A20

A21

A22

D0 - D7

D8 - D15

D16 - D31

A0/NBS0

A1/NWR2/NBS2

A2 - A10

A11

SDA10

A23 - A24

A25

NCS0

NCS1/SDCS

NCS2

NCS3/NANDCS

NCS4/CFCS0

NCS5/CFCS1

NANDOE

NANDWE

NRD/NOE/CFOE

NWR0/NWE/CFWE

NWR1/NBS1/CFIOR

NWR3/NBS3/CFIOW

CFRNW

CFCE1

CFCE2

Table 17-4.

EBI Pins and External Devices Connections

SDRAM

SDRAMC

DQM1

DQM3

CS[0]

A[11:12]

BA0

BA1

D0 - D7

D8 - D15

D16 - D31

DQM0

DQM2

A[0:8]

A9

A10

Pins of the Interfaced Device

Compact

Flash

Compact

Flash

True IDE Mode

SMC

WE

IOR

IOW

CFRNW

(1)

CS0

CS1

CFCS0

(1)

CFCS1

(1)

REG

D0 - D7

D8 - 15

A0

A1

A[2:10]

OE

WE

IOR

IOW

CFRNW

(1)

CE1

CE2

CFCS0

(1)

CFCS1

(1)

REG

D0 - D7

D8 - 15

A0

A1

A[2:10]

Smart Media or

NAND Flash

OE

WE

CLE

(3)

ALE

(3)

AD0-AD7

AD8-AD15

156

32015D–AVR32–10/07

AT32AP7001

Signals

Controller

SDCK

SDCKE

RAS

CAS

SDWE

NWAIT

Pxx

(2)

Pxx

(2)

Pxx

(2)

Table 17-4.

EBI Pins and External Devices Connections (Continued)

Pins of the Interfaced Device

SDRAM

SDRAMC

Compact

Flash

Compact

Flash

True IDE Mode

SMC

Smart Media or

NAND Flash

WE

CLK

CKE

RAS

CAS

WAIT

CD1 or CD2

WAIT

CD1 or CD2

CE

– – – RDY

Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot.

2. Any PIO line.

3. The CLE and ALE signals of the NAND Flash device may be driven by any address bit. For details, see

”SmartMedia and NAND Flash Support” on page 164 .

4.

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17.5.2

Connection Examples

Figure 17-2

shows an example of connections between the EBI and external devices.

Figure 17-2. EBI Connections to Memory Devices

EBI

D0-D31

RAS

CAS

SDCK

SDCKE

SDWE

A0/NBS0

NWR1/NBS1

A1/NWR2/NBS2

NWR3/NBS3

NRD/NOE

NWR0/NWE

D0-D7

D0-D7

2M x 8

SDRAM

SDWE

NBS0

CS

CLK

CKE

WE

RAS

CAS

DQM

A0-A9, A11

A10

BA0

BA1

A2-A11, A13

SDA10

A16/BA0

A17/BA1

SDA10

A2-A15

A16/BA0

A17/BA1

A18-A25

NCS0

NCS1/SDCS

NCS2

NCS3

NCS4

NCS5

D16-D23

D0-D7

SDWE

CS

CLK

CKE

WE

RAS

CAS

DQM

NBS2

2M x 8

SDRAM

A0-A9, A11

A10

BA0

BA1

A2-A11, A13

SDA10

A16/BA0

A17/BA1

D8-D15

D0-D7

2M x 8

SDRAM

SDWE

NBS1

CS

CLK

CKE

WE

RAS

CAS

DQM

A0-A9, A11 A2-A11, A13

A10 SDA10

BA0

BA1

A16/BA0

A17/BA1

D24-D31

D0-D7

SDWE

NBS3

CS

CLK

CKE

WE

RAS

CAS

DQM

2M x 8

SDRAM

A0-A9, A11

A10

BA0

BA1

A2-A11, A13

SDA10

A16/BA0

A17/BA1

D0-D7

CS

NRD/NOE

A0/NWR0/NBS0

OE

WE

D0-D7

128K x 8

SRAM

A0-A16

A1-A17

D8-D15

CS

NRD/NOE

NWR1/NBS1

OE

WE

128K x 8

SRAM

D0-D7

A0-A16

A1-A17

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17.6

Product Dependencies

17.6.1

I/O Lines

The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.

The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.

17.7

Functional Description

17.7.1

17.7.2

17.7.3

17.7.4

17.7.5

The EBI transfers data between the internal HSB Bus (handled by the HMatrix) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control busses and is composed of the following elements:

• The Static Memory Controller (SMC)

• The SDRAM Controller (SDRAMC)

• The ECC Controller (ECC)

• A chip select assignment feature that assigns an HSB address space to the external devices

• A multiplex controller circuit that shares the pins between the different Memory Controllers

• Programmable CompactFlash support logic

• Programmable SmartMedia and NAND Flash support logic

Bus Multiplexing

Pull-up Control

The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests.

Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermore, refresh cycles of the SDRAM are executed independently by the SDRAM Controller without delaying the other external Memory Controller accesses.

A specific HMATRIX_SFR register in the Matrix User Interface permit enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the PIO Controller lines. For details on this register, refer to the Peripherals Section. The pull-up resistors are enabled after reset. Setting the EBI_DBPUC bit disables the pull-up resistors on lines not muxed with PIO. Enabling the pullup resistor on lines multiplexed with PIO lines can be performed by programming the appropriate PIO controller.

Static Memory Controller

For information on the Static Memory Controller, refer to the Static Memory Controller Section.

SDRAM Controller

ECC Controller

For information on the SDRAM Controller, refer to the SDRAM Section.

For information on the ECC Controller, refer to the ECC Section.

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17.7.6

17.7.6.1

CompactFlash Support

The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.

The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or

NCS5 address space. Programming the EBI_CS4A and/or EBI_CS5A bits in a HMATRIX_SFR

Register to the appropriate value enables this logic.

For details on this register, refer to the

Peripherals Section.

Access to an external CompactFlash device is then made by accessing the address space reserved to NCS4 and/or NCS5 (i.e., between 0x04000 0000 and 0x07FF FFFF for NCS4 and between 0x2000 0000 and 0x23FF FFFF for NCS5).

All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled.

I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode

Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish

I/O mode, common memory mode, attribute memory mode and True IDE mode.

The different modes are accessed through a specific memory mapping as illustrated on Figure

17-3 . A[23:21] bits of the transfer address are used to select the desired mode as described in

Table 17-5 on page 161 .

Figure 17-3. CompactFlash Memory Mapping

CF Address Space

Offset 0x00E0 0000

Offset 0x00C0 0000

Offset 0x0080 0000

Offset 0x0040 0000

Offset 0x0000 0000

True IDE Alternate Mode Space

True IDE Mode Space

I/O Mode Space

Common Memory Mode Space

Attribute Memory Mode Space

Note: The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE mode).

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Table 17-5.

CompactFlash Mode Selection

A[23:21]

000

010

100

110

111

Mode Base Address

Attribute Memory

Common Memory

I/O Mode

True IDE Mode

Alternate True IDE Mode

17.7.6.2

CFCE1 and CFCE2 signals

To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd byte access on the D[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the corresponding NCS pin (NCS4 or NCS5). The Chip Select

Register (DBW field in the corresponding Chip Select Register) of the NCS4 and/or NCS5

address space must be set as shown in Table 17-6 to enable the required access type.

NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select.

The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller Section.

Table 17-6.

CFCE1 and CFCE2 Truth Table

Mode CFCE2 CFCE1

Attribute Memory NBS1 NBS0

DBW

16 bits

SMC Access Mode

Byte Select

Common Memory

I/O Mode

NBS1

1

NBS1

1

NBS0

0

NBS0

0

16bits

8 bits

16 bits

8 bits

Comment

Access to Even Byte on D[7:0]

Access to Even Byte on D[7:0]

Access to Odd Byte on D[15:8]

Access to Odd Byte on D[7:0]

Access to Even Byte on D[7:0]

Access to Odd Byte on D[15:8]

Access to Odd Byte on D[7:0]

Byte Select

Byte Select

True IDE Mode

Task File

Data Register

1

1

0

0

8 bits

16 bits

Access to Even Byte on D[7:0]

Access to Odd Byte on D[7:0]

Access to Even Byte on D[7:0]

Access to Odd Byte on D[15:8]

Byte Select

Alternate True IDE Mode

Control Register

Alternate Status Read

Drive Address

Standby Mode or

Address Space is not assigned to CF

0

0

1

1

1

1

Don’t

Care

8 bits

Access to Even Byte on D[7:0]

Access to Odd Byte on D[7:0]

Don’t Care

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17.7.6.3

Read/Write Signals

In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deactivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated.

Figure

17-4 on page 162

demonstrates a schematic representation of this logic.

Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values.

For details on these signal waveforms, please refer to the section: Setup and Hold Cycles of the

Static Memory Controller Section.

Figure 17-4. CompactFlash Read/Write Control Signals

External Bus Interface

SMC

A23

CompactFlash Logic

1

1

0

1

0

1

0

1

CFOE

CFWE

A22

NRD_NOE

NWR0_NWE

1

1

0

1

CFIOR

CFIOW

17.7.6.4

Table 17-7.

CompactFlash Mode Selection

Mode Base Address CFOE

Attribute Memory

Common Memory

I/O Mode

True IDE Mode

NRD_NOE

1

0

CFWE

NWR0_NWE

1

1

CFIOR

1

NRD_NOE

NRD_NOE

CFIOW

1

NWR0_NWE

NWR0_NWE

Multiplexing of CompactFlash Signals on EBI Pins

Table 17-8 on page 163 and Table 17-9 on page 163 illustrate the multiplexing of the Compact-

Flash logic signals with other EBI signals on the EBI pins. The EBI pins in

Table 17-8 are strictly

dedicated to the CompactFlash interface as soon as the EBI_CS4A and/or EBI_CS5A field of a specific HMATRIX_SFR Register is set, see the Peripherals Section for details. These pins must not be used to drive any other memory devices.

The EBI pins in Table 17-9 on page 163 remain shared between all memory areas when the cor-

responding CompactFlash interface is enabled (EBI_CS4A = 1 and/or EBI_CS5A = 1).

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Table 17-8.

Dedicated CompactFlash Interface Multiplexing

CompactFlash Signals

Pins

NCS4/CFCS0

CS4A = 1

CFCS0

CS5A = 1 CS4A = 0

NCS4

EBI Signals

CS5A = 0

NCS5/CFCS1 CFCS1 NCS5

17.7.6.5

Table 17-9.

Shared CompactFlash Interface Multiplexing

Access to

CompactFlash Device

Pins

NOE/NRD/CFOE

NWR0/NWE/CFWE

NWR1/NBS1/CFIOR

NWR3/NBS3/CFIOW

A25/CFRNW

CompactFlash Signals

CFOE

CFWE

CFIOR

CFIOW

CFRNW

Access to

Other EBI Devices

EBI Signals

NRD/NOE

NWR0/NWE

NWR1/NBS1

NWR3/NBS3

A25

Application Example

Figure 17-5 on page 164

illustrates an example of a CompactFlash application. CFCS0 and

CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device. The timing of the CFCS0 signal is identical to the NCS4 signal. Moreover, the CFRNW signal remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the Static Memory Controller Section.

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Figure 17-5. CompactFlash Application Example

EBI

D[15:0]

DIR /OE

A25/CFRNW

NCS4/CFCS0

CD (PIO)

/OE

A[10:0]

A22/REG

NOE/CFOE

NWE/CFWE

NWR1/CFIOR

NWR3/CFIOW

CFCE1

CFCE2

NWAIT

AT32AP7001

CompactFlash Connector

D[15:0]

_CD1

_CD2

A[10:0]

_REG

_OE

_WE

_IORD

_IOWR

_CE1

_CE2

_WAIT

17.7.7

SmartMedia and NAND Flash Support

The External Bus Interface integrates circuitry that interfaces to SmartMedia and NAND Flash devices.

The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space.

Programming the EBI_CS3A field in a specific HMATRIX_SFR Register to the appropriate value enables the NAND Flash logic.

For details on this register, refer to the Peripherals Section.

Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x0C00 0000 and 0x0FFF FFFF).

The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. See Figure

”NAND Flash

Signal Multiplexing on EBI Pins” on page 165 for more informations. For details on these wave-

forms, refer to the Static Memory Controller Section.

The SmartMedia device is connected the same way as the NAND Flash device.

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Figure 17-6. NAND Flash Signal Multiplexing on EBI Pins

SMC SmartMedia Logic

NCSx

NRD_NOE

NANDOE

NANDOE

NANDWE

NANDWE

NWR0_NWE

17.7.7.1

NAND Flash Signals

The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The user should note that any bit on the EBI address bus can also be used for this purpose. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the

NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode.

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Figure 17-7. NAND Flash Application Example

D[7:0]

A[22:21]

NCSx/NANDCS

Not Connected

EBI

AD[7:0]

ALE

CLE

NANDOE

NANDWE

PIO

PIO

CE

R/B

Note: The External Bus Interfaces is also able to support 16-bits devices.

SmartMedia

NOE

NWE

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18. DMA Controller (DMACA)

Rev: 2.0.6a.3

18.1

Features

2 HSB Master Interfaces

3 Channels

Software and Hardware Handshaking Interfaces

– 11 Hardware Handshaking Interfaces

Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer

Single-block DMA Transfer

Multi-block DMA Transfer

– Linked Lists

– Auto-Reloading

– Contiguous Blocks

DMA Controller is Always the Flow Controller

Additional Features

– Scatter and Gather Operations

– Channel Locking

– Bus Locking

– FIFO Mode

– Pseudo Fly-by Operation

18.2

Description

The DMA Controller (DMACA) is an HSB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more System Bus. One channel is required for each source/destination pair. In the most basic configuration, the DMACA has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two System Bus transfers are required for each DMA data transfer. This is also known as a dual-access transfer.

The DMACA is programmed via the HSB slave interface.

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18.3

Block Diagram

Figure 18-1. DMA Controller (DMACA) Block Diagram

DMA Controller

HSB Slave

HSB Slave

I/F

CFG

Channel 1

Channel 0

FIFO

Interrupt

Generator

HSB Master

HSB Master

I/F

SRC

FSM

DST

FSM irq_dma

18.4

Product Dependencies

18.4.1

18.4.2

18.4.3

18.4.4

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.

The programmer must first program the PIO controllers to assign the DMACA pins to their peripheral functions.

Power Management

The DMACA clock is generated by the Power Manager. Before using the DMACA, the programmer must ensure that the DMACA clock is enabled in the Power Manager.

To prevent bus errors the DMACA operation must be terminated before entering sleep mode.

Interrupt

The DMACA interface has an interrupt line connected to the Interrupt Controller. Handling the

DMACA interrupt requires programming the interrupt controller before configuring the DMACA.

Peripherals

Both the source peripheral and the destination peripheral must be set up correctly prior to the

DMA transfer.

18.5

Functional Description

18.5.1

Basic Definitions

Source peripheral: Device on a System Bus layer from where the DMACA reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel.

Destination peripheral: Device to which the DMACA writes the stored data from the FIFO (previously read from the source peripheral).

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Memory: Source or destination that is always “ready” for a DMA transfer and does not require a handshaking interface to interact with the DMACA. A peripheral should be assigned as memory only if it does not insert more than 16 wait states. If more than 16 wait states are required, then the peripheral should use a handshaking interface (the default if the peripheral is not programmed to be memory) in order to signal when it is ready to accept or supply data.

Channel: Read/write datapath between a source peripheral on one configured System Bus layer and a destination peripheral on the same or different System Bus layer that occurs through the channel FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination handshaking interface is assigned to the channel. Source and destination handshaking interfaces can be assigned dynamically by programming the channel registers.

Master interface: DMACA is a master on the HSB bus reading data from the source and writing it to the destination over the HSB bus.

Slave interface: The HSB interface over which the DMACA is programmed. The slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer.

Handshaking interface: A set of signal registers that conform to a protocol and handshake between the DMACA and source or destination peripheral to control the transfer of a single or burst transaction between them. This interface is used to request, acknowledge, and control a

DMACA transaction. A channel can receive a request through one of three types of handshaking interface: hardware, software, or peripheral interrupt.

Hardware handshaking interface: Uses hardware signals to control the transfer of a single or burst transaction between the DMACA and the source or destination peripheral.

Software handshaking interface: Uses software registers to control the transfer of a single or burst transaction between the DMACA and the source or destination peripheral. No special

DMACA handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing an existing peripheral to the DMACA without modifying it.

Peripheral interrupt handshaking interface: A simple use of the hardware handshaking interface. In this mode, the interrupt line from the peripheral is tied to the dma_req input of the hardware handshaking interface. Other interface signals are ignored.

Flow controller: The device (either the DMACA or source/destination peripheral) that determines the length of and terminates a DMA block transfer. If the length of a block is known before enabling the channel, then the DMACA should be programmed as the flow controller. If the length of a block is not known prior to enabling the channel, the source or destination peripheral needs to terminate a block transfer. In this mode, the peripheral is the flow controller.

Flow control mode (CFGx.FCMODE): Special mode that only applies when the destination peripheral is the flow controller. It controls the pre-fetching of data from the source peripheral.

Transfer hierarchy:

Figure 18-2 on page 170

illustrates the hierarchy between DMACA transfers, block transfers, transactions (single or burst), and System Bus transfers (single or burst) for

non-memory peripherals. Figure 18-3 on page 170

shows the transfer hierarchy for memory.

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Figure 18-2. DMACA Transfer Hierarchy for Non-Memory Peripheral

DMAC Transfer

DMA Transfer

Level

Block

Block Block

Block Transfer

Level

Burst

Transaction

Burst

Transaction

Burst

Transaction

Single

Transaction

DMA Transaction

Level

System Bus

Burst

Transfer

System Bus

Burst

Transfer

System Bus

Burst

Transfer

System Bus

Single

Transfer

System Bus

Single

Transfer

System Bus

Transfer Level

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Figure 18-3. DMACA Transfer Hierarchy for Memory

DMAC Transfer

Block

Block

System Bus

Burst

Transfer

System Bus

Burst

Transfer

Block

DMA Transfer

Level

Block Transfer

Level

System Bus

Burst

Transfer

System Bus

Single

Transfer

System Bus

Transfer Level

Block: A block of DMACA data. The amount of data (block length) is determined by the flow controller. For transfers between the DMACA and memory, a block is broken directly into a sequence of System Bus bursts and single transfers. For transfers between the DMACA and a non-memory peripheral, a block is broken into a sequence of DMACA transactions (single and bursts). These are in turn broken into a sequence of System Bus transfers.

Transaction: A basic unit of a DMACA transfer as determined by either the hardware or software handshaking interface. A transaction is only relevant for transfers between the DMACA and a source or destination peripheral if the source or destination peripheral is a non-memory device. There are two types of transactions: single and burst.

Single transaction: The length of a single transaction is always 1 and is converted to a single System Bus transfer.

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Burst transaction: The length of a burst transaction is programmed into the

DMACA. The burst transaction is converted into a sequence of System Bus bursts and single transfers. DMACA executes each burst transfer by performing incremental bursts that are no longer than the maximum System Bus burst size set.

The burst transaction length is under program control and normally bears some relationship to the FIFO sizes in the DMACA and in the source and destination peripherals.

DMA transfer: Software controls the number of blocks in a DMACA transfer. Once the DMA transfer has completed, then hardware within the DMACA disables the channel and can generate an interrupt to signal the completion of the DMA transfer. You can then re-program the channel for a new DMA transfer.

Single-block DMA transfer: Consists of a single block.

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Multi-block DMA transfer: A DMA transfer may consist of multiple DMACA blocks. Multi-block

DMA transfers are supported through block chaining (linked list pointers), auto-reloading of channel registers, and contiguous blocks. The source and destination can independently select which method to use.

Linked lists (block chaining) – A linked list pointer (LLP) points to the location in system memory where the next linked list item (LLI) exists. The LLI is a set of registers that describe the next block (block descriptor) and an LLP register. The

DMACA fetches the LLI at the beginning of every block when block chaining is enabled.

Auto-reloading – The DMACA automatically reloads the channel registers at the end of each block to the value when the channel was first enabled.

Contiguous blocks – Where the address between successive blocks is selected to be a continuation from the end of the previous block.

Scatter: Relevant to destination transfers within a block. The destination System Bus address is incremented/decremented by a programmed amount when a scatter boundary is reached. The number of System Bus transfers between successive scatter boundaries is under software control.

Gather: Relevant to source transfers within a block. The source System Bus address is incremented/decremented by a programmed amount when a gather boundary is reached. The number of System Bus transfers between successive gather boundaries is under software control.

Channel locking: Software can program a channel to keep the HSB master interface by locking the arbitration for the master bus interface for the duration of a DMA transfer, block, or transaction (single or burst).

Bus locking: Software can program a channel to maintain control of the System Bus bus by asserting hlock for the duration of a DMA transfer, block, or transaction (single or burst). Channel locking is asserted for the duration of bus locking at a minimum.

FIFO mode: Special mode to improve bandwidth. When enabled, the channel waits until the

FIFO is less than half full to fetch the data from the source peripheral and waits until the FIFO is greater than or equal to half full to send data to the destination peripheral. Thus, the channel can transfer the data using System Bus bursts, eliminating the need to arbitrate for the HSB master interface for each single System Bus transfer. When this mode is not enabled, the channel only waits until the FIFO can transmit/accept a single System Bus transfer before requesting the master bus interface.

Pseudo fly-by operation: Typically, it takes two System Bus cycles to complete a transfer, one for reading the source and one for writing to the destination. However, when the source and destination peripherals of a DMA transfer are on different System Bus layers, it is possible for the

DMACA to fetch data from the source and store it in the channel FIFO at the same time as the

DMACA extracts data from the channel FIFO and writes it to the destination peripheral. This activity is known as pseudo fly-by operation. For this to occur, the master interface for both source and destination layers must win arbitration of their HSB layer. Similarly, the source and destination peripherals must win ownership of their respective master interfaces.

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18.6

Memory Peripherals

Figure 18-3 on page 170 shows the DMA transfer hierarchy of the DMACA for a memory periph-

eral. There is no handshaking interface with the DMACA, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMACA to attempt System Bus transfers to the peripheral once the channel is enabled. If the peripheral slave cannot accept these System Bus transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. By using the handshaking interface, the peripheral can signal to the DMACA that it is ready to transmit/receive data, and then the DMACA can access the peripheral without the peripheral inserting wait states onto the bus.

18.7

Handshaking Interface

Handshaking interfaces are used at the transaction level to control the flow of single or burst transactions. The operation of the handshaking interface is different and depends on whether the peripheral or the DMACA is the flow controller.

The peripheral uses the handshaking interface to indicate to the DMACA that it is ready to transfer/accept data over the System Bus. A non-memory peripheral can request a DMA transfer through the DMACA using one of two handshaking interfaces:

•Hardware handshaking

•Software handshaking

Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished using a dedicated handshaking interface.

18.7.1

18.7.1.1

Software Handshaking

When the slave peripheral requires the DMACA to perform a DMA transaction, it communicates this request by sending an interrupt to the CPU or interrupt controller.

The interrupt service routine then uses the software registers to initiate and control a DMA transaction. These software registers are used to implement the software handshaking interface.

The HS_SEL_SRC/HS_SEL_DST bit in the CFGx channel configuration register must be set to enable software handshaking.

When the peripheral is not the flow controller, then the last transaction registers LstSrcReg and

LstDstReg are not used, and the values in these registers are ignored.

Burst Transactions

Writing a 1 to the ReqSrcReg[x]/ReqDstReg[x] register is always interpreted as a burst transaction request, where x is the channel number. However, in order for a burst transaction request to start, software must write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] register.

You can write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] and ReqSrcReg[x]/ReqDstReg[x] registers in any order, but both registers must be asserted in order to initiate a burst transaction.

Upon completion of the burst transaction, the hardware clears the SglReqSrcReg[x]/SglReqDstReg[x] and ReqSrcReg[x]/ReqDstReg[x] registers.

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18.7.1.2

18.7.2

Single Transactions

Writing a 1 to the SglReqSrcReg/SglReqDstReg initiates a single transaction. Upon completion of the single transaction, both the SglReqSrcReg/SglReqDstReg and ReqSrcReg/ReqDstReg bits are cleared by hardware. Therefore, writing a 1 to the ReqSrcReg/ReqDstReg is ignored while a single transaction has been initiated, and the requested burst transaction is not serviced.

Again, writing a 1 to the ReqSrcReg/ReqDstReg register is always a burst transaction request.

However, in order for a burst transaction request to start, the corresponding channel bit in the

SglReqSrcReg/SglReqDstReg must be asserted. Therefore, to ensure that a burst transaction is serviced, you must write a 1 to the ReqSrcReg/ReqDstReg before writing a 1 to the SglReqSrcReg/SglReqDstReg register.

Software can poll the relevant channel bit in the SglReqSrcReg/ SglReqDstReg and ReqSrcReg/ReqDstReg registers. When both are 0, then either the requested burst or single transaction has completed. Alternatively, the IntSrcTran or IntDstTran interrupts can be enabled and unmasked in order to generate an interrupt when the requested source or destination transaction has completed.

Note: The transaction-complete interrupts are triggered when both single and burst transactions are complete. The same transaction-complete interrupt is used for both single and burst transactions.

Hardware Handshaking

There are 11 hardware handshaking interfaces between the DMACA and peripherals. Refer to the “Peripherals” chapter for the device-specific mapping of these interfaces.

18.7.2.1

External DMA Request Definition

When an external slave peripheral requires the DMACA to perform DMA transactions, it communicates its request by asserting the external nDMAREQx signal. This signal is resynchronized to

ensure a proper functionality (see ”External DMA Request Timing” on page 175

).

The external nDMAREQx is asserted when the source threshold level is reached. After resynchronization, the rising edge of dma_req starts the transfer. dma_req is de-asserted when dma_ack is asserted.

The external nDMAREQx signal must be de-asserted after the last transfer and re-asserted again before a new transaction starts.

For a source FIFO, an active edge is triggered on nDMAREQx when the source FIFO exceeds a watermark level. For a destination FIFO, an active edge is triggered on nDMAREQx when the destination FIFO drops below the watermark level.

The source transaction length, CTLx.SRC_MSIZE, and destination transaction length,

CTLx.DEST_MSIZE, must be set according to watermark levels on the source/destination peripherals.

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Figure 18-4. External DMA Request Timing

Hclk

DMA Transaction nDMAREQx dma_req

DMA Transfers DMA Transfers dma_ack

DMA Transfers

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18.8

DMACA Transfer Types

A DMA transfer may consist of single or multi-block transfers. On successive blocks of a multiblock transfer, the SARx/DARx register in the DMACA is reprogrammed using either of the following methods:

•Block chaining using linked lists

•Auto-reloading

•Contiguous address between blocks

On successive blocks of a multi-block transfer, the CTLx register in the DMACA is re-programmed using either of the following methods:

•Block chaining using linked lists

•Auto-reloading

When block chaining, using linked lists is the multi-block method of choice, and on successive blocks, the LLPx register in the DMACA is re-programmed using the following method:

•Block chaining using linked lists

A block descriptor (LLI) consists of following registers, SARx, DARx, LLPx, CTL. These registers, along with the CFGx register, are used by the DMACA to set up and describe the block transfer.

18.8.1

18.8.1.1

Multi-block Transfers

Block Chaining Using Linked Lists

In this case, the DMACA re-programs the channel registers prior to the start of each block by fetching the block descriptor for that block from system memory. This is known as an LLI update.

DMACA block chaining is supported by using a Linked List Pointer register (LLPx) that stores the address in memory of the next linked list item. Each LLI (block descriptor) contains the corresponding block descriptor (SARx, DARx, LLPx, CTLx).

To set up block chaining, a sequence of linked lists must be programmed in memory.

The SARx, DARx, LLPx and CTLx registers are fetched from system memory on an LLI update.

The updated contents of the CTLx register are written back to memory on block completion. Figure 18-5 on page 177 shows how to use chained linked lists in memory to define multi-block

transfers using block chaining.

The Linked List multi-block transfers is initiated by programming LLPx with LLPx(0) (LLI(0) base address) and CTLx with CTLx.LLP_S_EN and CTLx.LLP_D_EN.

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Figure 18-5. Multi-block Transfer Using Linked Lists

System Memory

LLI(0)

LLPx(0)

CTLx[63..32]

CTLx[31..0]

LLPx(1)

DARx

SARx

LLI(1)

CTLx[63..32]

CTLx[31..0]

LLPx(2)

DARx

LLPx(1)

SARx

LLPx(2)

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Table 18-1.

Programming of Transfer Types and Channel Register Update Method (DMACA State Machine Table)

Transfer Type

LLP.

LOC

= 0

LLP_S_EN

(

CTLx)

RELOAD_

SR

(

CFGx)

LLP_D_EN

(

CTLx)

RELOAD_

DS

(

CFGx)

CTLx,

LLPx

Update

Method

SARx Update

Method

DARx

Update

Method

1) Single Block or last transfer of multi-

Block

2) AutoReload multiblock transfer with contiguous SAR

3) AutoReload multiblock transfer with contiguous DAR

4) AutoReload multiblock transfer

Yes

Yes

Yes

Yes

0

0

0

0

0

0

1

1

0

0

0

0

0

1

0

1

None, user reprograms

CTLx,LLPx are reloaded from initial values.

CTLx,LLPx are reloaded from initial values.

CTLx,LLPx are reloaded from initial values.

None (single)

Contiguous

Auto-Reload

Auto-Reload

None

(single)

Auto-

Reload

Contiguous

Auto-

Reload

5) Single Block or last transfer of multiblock

6) Linked List multiblock transfer with contiguous SAR

7) Linked List multiblock transfer with auto-reload SAR

8) Linked List multiblock transfer with contiguous DAR

9) Linked List multiblock transfer with auto-reload DAR

10) Linked List multiblock transfer

No

No

No

No

No

No

0

0

0

1

1

1

0

0

1

0

0

0

0

1

1

0

0

1

0

0

0

0

1

0

None, user reprograms

CTLx,LLPx loaded from next

Linked List item

CTLx,LLPx loaded from next

Linked List item

CTLx,LLPx loaded from next

Linked List item

CTLx,LLPx loaded from next

Linked List item

CTLx,LLPx loaded from next

Linked List item

None (single)

Contiguous

Auto-Reload

Linked List

Linked List

Linked List

None

(single)

Linked

List

Linked

List

Contiguous

Auto-

Reload

Linked

List

18.8.1.2

Auto-reloading of Channel Registers

During auto-reloading, the channel registers are reloaded with their initial values at the completion of each block and the new values used for the new block. Depending on the row number in

Table 18-1 on page 179

, some or all of the SARx, DARx and CTLx channel registers are reloaded from their initial value at the start of a block transfer.

18.8.1.3

Contiguous Address Between Blocks

In this case, the address between successive blocks is selected to be a continuation from the end of the previous block. Enabling the source or destination address to be contiguous between blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and

CFGx.RELOAD_DS registers (see

Figure 18-1 on page 168 ).

Note: Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the max-

imum value, use Row 10 of

Table 18-1 on page 179

and setup the LLI.SARx address of the block descriptor to be equal to the end SARx address of the previous block. Similarly, setup the

LLI.DARx address of the block descriptor to be equal to the end DARx address of the previous block.

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18.8.1.4

Suspension of Transfers Between Blocks

At the end of every block transfer, an end of block interrupt is asserted if:

•interrupts are enabled, CTLx.INT_EN = 1

•the channel block interrupt is unmasked, MaskBlock[n] = 0, where n is the channel number.

Note: The block complete interrupt is generated at the completion of the block transfer to the destination.

For rows 6, 8, and 10 of

Table 18-1 on page 179

, the DMA transfer does not stall between block transfers. For example, at the end of block N, the DMACA automatically proceeds to block N + 1.

For rows 2, 3, 4, 7, and 9 of Table 18-1 on page 179

(SARx and/or DARx auto-reloaded between block transfers), the DMA transfer automatically stalls after the end of block. Interrupt is asserted if the end of block interrupt is enabled and unmasked.

The DMACA does not proceed to the next block transfer until a write to the block interrupt clear register, ClearBlock[n], is performed by software. This clears the channel block complete interrupt.

For rows 2, 3, 4, 7, and 9 of Table 18-1 on page 179

(SARx and/or DARx auto-reloaded between block transfers), the DMA transfer does not stall if either:

•interrupts are disabled, CTLx.INT_EN = 0, or

•the channel block interrupt is masked, MaskBlock[n] = 1, where n is the channel number.

Channel suspension between blocks is used to ensure that the end of block ISR (interrupt service routine) of the next-to-last block is serviced before the start of the final block commences.

This ensures that the ISR has cleared the CFGx.RELOAD_SR and/or CFGx.RELOAD_DS bits b e f o r e c o m p l e t i o n o f t h e f i n a l b l o c k . T h e r e l o a d b i t s C F G x . R E L O A D _ S R a n d / o r

CFGx.RELOAD_DS should be cleared in the ‘end of block ISR’ for the next-to-last block transfer.

18.8.2

Ending Multi-block Transfers

All multi-block transfers must end as shown in either Row 1 or Row 5 of Table 18-1 on page 179 .

At the end of every block transfer, the DMACA samples the row number, and if the DMACA is in

Row 1 or Row 5 state, then the previous block transferred was the last block and the DMA transfer is terminated.

Note: Row 1 and Row 5 are used for single block transfers or terminating multiblock transfers. Ending in

Row 5 state enables status fetch for the last block. Ending in Row 1 state disables status fetch for the last block.

For rows 2,3 and 4 of

Table 18-1 on page 179 , (LLPx = 0 and CFGx.RELOAD_SR and/or

C F G x . R E L O A D _ D S i s s e t ) , m u l t i - b l o c k D M A t r a n s f e r s c o n t i n u e u n t i l b o t h t h e

CFGx.RELOAD_SR and CFGx.RELOAD_DS registers are cleared by software. They should be programmed to zero in the end of block interrupt service routine that services the next-to-last block transfer. This puts the DMACA into Row 1 state.

For rows 6, 8, and 10 (both CFGx.RELOAD_SR and CFGx.RELOAD_DS cleared) the user must setup the last block descriptor in memory such that both LLI.CTLx.LLP_S_EN and

LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block descriptor in memory is zero, then the DMA transfer is terminated in Row 1.

For rows 7 and 9, the end-of-block interrupt service routine that services the next-to-last block transfer should clear the CFGx.RELOAD_SR and CFGx.RELOAD_DS reload bits. The last

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block descriptor in memory should be set up so that both the LLI.CTLx.LLP_S_EN and

LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block descriptor in memory is zero, then the DMA transfer is terminated in Row 1.

Note:

The only allowed transitions between the rows of

Table 18-1 on page 179 are from any row into

row 1 or row 5. As already stated, a transition into row 1 or row 5 is used to terminate the DMA transfer. All other transitions between rows are not allowed. Software must ensure that illegal transitions between rows do not occur between blocks of a multi-block transfer. For example, if block N is in row 10 then the only allowed rows for block N + 1 are rows 10, 5 or 1.

18.9

Programming a Channel

Three registers, the LLPx, the CTLx and CFGx, need to be programmed to set up whether single or multi-block transfers take place, and which type of multi-block transfer is used. The different transfer types are shown in

Table 18-1 on page 179 .

The “Update Method” column indicates where the values of SARx, DARx, CTLx, and LLPx are obtained for the next block transfer when multi-block DMACA transfers are enabled.

Note:

In

Table 18-1 on page 179

, all other combinations of LLPx.LOC = 0, CTLx.LLP_S_EN,

CFGx.RELOAD_SR, CTLx.LLP_D_EN, and CFGx.RELOAD_DS are illegal, and causes indeterminate or erroneous behavior.

18.9.1

18.9.1.1

Programming Examples

Single-block Transfer (Row 1)

Row 5 in

Table 18-1 on page 179

is also a single block transfer.

1. Read the Channel Enable register to choose a free (disabled) channel.

2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, Clear-

Err. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared.

3. Program the following channel registers: a. Write the starting source address in the SARx register for channel x.

b. Write the starting destination address in the DARx register for channel x.

c. Program CTLx and CFGx according to Row 1 as shown in

Table 18-1 on page 179 .

Program the LLPx register with ‘0’.

d. Write the control information for the DMA transfer in the CTLx register for channel x.

For example, in the register, you can program the following:

–i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register.

–ii. Set up the transfer characteristics, such as:

– Transfer width for the source in the SRC_TR_WIDTH field.

– Transfer width for the destination in the DST_TR_WIDTH field.

– Source master layer in the SMS field where source resides.

– Destination master layer in the DMS field where destination resides.

– Incrementing/decrementing or fixed address for source in SINC field.

– Incrementing/decrementing or fixed address for destination in DINC field.

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18.9.1.2

e. Write the channel configuration information into the CFGx register for channel x.

–i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination requests.

Writing a ‘1’ activates the software handshaking interface to handle source/destination requests.

–ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral.

This requires programming the SRC_PER and DEST_PER bits, respectively.

4. After the DMACA selected channel has been programmed, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is enabled.

5. Source and destination request single and burst DMA transactions to transfer the block of data (assuming non-memory peripherals). The DMACA acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer.

6. Once the transfer completes, hardware sets the interrupts and disables the channel. At this time you can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete.

Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10)

1. Read the Channel Enable register to choose a free (disabled) channel.

2. Set up the chain of Linked List Items (otherwise known as block descriptors) in memory.

Write the control information in the LLI.CTLx register location of the block descriptor for each LLI in memory (see

Figure 18-5 on page 177

) for channel x. For example, in the register, you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register.

b. Set up the transfer characteristics, such as:

–i. Transfer width for the source in the SRC_TR_WIDTH field.

–ii. Transfer width for the destination in the DST_TR_WIDTH field.

–iii. Source master layer in the SMS field where source resides.

–iv. Destination master layer in the DMS field where destination resides.

–v. Incrementing/decrementing or fixed address for source in SINC field.

–vi. Incrementing/decrementing or fixed address for destination DINC field.

3. Write the channel configuration information into the CFGx register for channel x.

a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘1’ activates the software handshaking interface to handle source/destination requests.

b. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively.

4. Make sure that the LLI.CTLx register locations of all LLI entries in memory (except the

last) are set as shown in Row 10 of Table 18-1 on page 179

. The LLI.CTLx register of

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the last Linked List Item must be set as described in Row 1 or Row 5 of Table 18-1 on page 179 .

Figure 18-7 on page 185

shows a Linked List example with two list items.

5. Make sure that the LLI.LLPx register locations of all LLI entries in memory (except the last) are non-zero and point to the base address of the next Linked List Item.

6. Make sure that the LLI.SARx/LLI.DARx register locations of all LLI entries in memory point to the start source/destination block address preceding that LLI fetch.

7. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLI entries in memory are cleared.

8. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, Clear-

Err. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared.

9. Program the CTLx, CFGx registers according to Row 10 as shown in Table 18-1 on page

179

.

10.Program the LLPx register with LLPx(0), the pointer to the first Linked List item.

11.Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is performed.

12.The DMACA fetches the first LLI from the location pointed to by LLPx(0).

Note: The LLI.SARx, LLI. DARx, LLI.LLPx and LLI.CTLx registers are fetched. The DMACA automatically reprograms the SARx, DARx, LLPx and CTLx channel registers from the LLPx(0).

13.Source and destination request single and burst DMA transactions to transfer the block of data (assuming non-memory peripheral). The DMACA acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer.

Note:

Table 18-1 on page 179

14.The DMACA does not wait for the block interrupt to be cleared, but continues fetching the next LLI from the memory location pointed to by current LLPx register and automatically reprograms the SARx, DARx, LLPx and CTLx channel registers. The DMA transfer continues until the DMACA determines that the CTLx and LLPx registers at the end of a block transfer match that described in Row 1 or Row 5 of

Table 18-1 on page

179

. The DMACA then knows that the previous block transferred was the last block in the DMA transfer. The DMA transfer might look like that shown in

Figure 18-6 on page

184

.

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Figure 18-6. Multi-Block with Linked List Address for Source and Destination

Address of

Source Layer

Address of

Destination Layer

Block 2 Block 2

SAR(2) DAR(2)

Block 1 Block 1

SAR(1) DAR(1)

Block 0

Block 0

SAR(0)

DAR(0)

Source Blocks Destination Blocks

If the user needs to execute a DMA transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum block size

CTLx.BLOCK_TS, then this can be achieved using the type of multi-block transfer as shown in

Figure 18-7 on page 185 .

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Figure 18-7. Multi-Block with Linked Address for Source and Destination Blocks are

Contiguous

Address of

Source Layer

Address of

Destination Layer

Block 2

DAR(3)

Block 2

Block 2

SAR(3)

DAR(2)

Block 2

Block 1

SAR(2)

DAR(1)

Block 1

Block 0

SAR(1)

DAR(0)

Block 0

SAR(0)

Source Blocks

Destination Blocks

The DMA transfer flow is shown in Figure 18-9 on page 188

.

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Figure 18-8. DMA Transfer Flow for Source and Destination Linked List Address

Channel enabled by software

LLI Fetch

Hardware reprograms

SARx, DARx, CTLx, LLPx

DMAC block transfer

Source/destination status fetch

Block Complete interrupt generated here

Is DMAC in

Row1 of

DMAC State Machine Table?

no

DMAC transfer Complete interrupt generated here yes

Channel Disabled by hardware

18.9.1.3

Multi-block Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 4)

1. Read the Channel Enable register to choose an available (disabled) channel.

2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, Clear-

Err. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared.

3. Program the following channel registers:

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a. Write the starting source address in the SARx register for channel x.

b. Write the starting destination address in the DARx register for channel x.

c. Program CTLx and CFGx according to Row 4 as shown in

Table 18-1 on page 179 .

Program the LLPx register with ‘0’.

d. Write the control information for the DMA transfer in the CTLx register for channel x.

For example, in the register, you can program the following:

–i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register.

–ii. Set up the transfer characteristics, such as:

– Transfer width for the source in the SRC_TR_WIDTH field.

– Transfer width for the destination in the DST_TR_WIDTH field.

– Source master layer in the SMS field where source resides.

– Destination master layer in the DMS field where destination resides.

– Incrementing/decrementing or fixed address for source in SINC field.

– Incrementing/decrementing or fixed address for destination in DINC field.

e. Write the channel configuration information into the CFGx register for channel x.

Ensure that the reload bits, CFGx. RELOAD_SR and CFGx.RELOAD_DS are enabled.

–i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘1’ activates the software handshaking interface to handle source/destination requests.

–ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral.

This requires programming the SRC_PER and DEST_PER bits, respectively.

4. After the DMACA selected channel has been programmed, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is enabled.

5. Source and destination request single and burst DMACA transactions to transfer the block of data (assuming non-memory peripherals). The DMACA acknowledges on completion of each burst/single transaction and carry out the block transfer.

6. When the block transfer has completed, the DMACA reloads the SARx, DARx and CTLx registers. Hardware sets the Block Complete interrupt. The DMACA then samples the

row number as shown in Table 18-1 on page 179 . If the DMACA is in Row 1, then the

DMA transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. So you can either respond to the Block Complete or Transfer

Complete interrupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is disabled, to detect when the transfer is complete. If the DMACA is not in Row 1, the next step is performed.

7. The DMA transfer proceeds as follows: a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is unmasked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine)

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should clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers. This put the DMACA into Row 1 as shown in

Table 18-1 on page 179

. If the next block is not the last block in the DMA transfer, then the reload bits should remain enabled to keep the DMACA in Row 4.

b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is masked (MaskBlock[x] = 1’b0, where x is the channel number), then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case software must clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers to put the

DMACA into ROW 1 of

Table 18-1 on page 179 before the last block of the DMA

transfer has completed. The transfer is similar to that shown in Figure 18-9 on page

188

. The DMA transfer flow is shown in Figure 18-10 on page 189 .

Figure 18-9. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded

Address of

Source Layer

Address of

Destination Layer

Block0

Block1

Block2

SAR

Source Blocks

BlockN

Destination Blocks

DAR

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Figure 18-10. DMA Transfer Flow for Source and Destination Address Auto-reloaded

Channel Enabled by software

Block Transfer

Reload SARx, DARx, CTLx

Block Complete interrupt generated here

DMAC transfer Complete interrupt generated here yes Is DMAC in Row1 of

DMAC State Machine Table?

Channel Disabled by hardware no

CTLx.INT_EN=1

&&

MASKBLOCK[x]=1?

yes

Stall until block complete interrupt cleared by software no

18.9.1.4

Multi-block Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row7)

1. Read the Channel Enable register to choose a free (disabled) channel.

2. Set up the chain of linked list items (otherwise known as block descriptors) in memory.

Write the control information in the LLI.CTLx register location of the block descriptor for each LLI in memory for channel x. For example, in the register you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control peripheral by programming the TT_FC of the CTLx register.

b. Set up the transfer characteristics, such as:

–i. Transfer width for the source in the SRC_TR_WIDTH field.

–ii. Transfer width for the destination in the DST_TR_WIDTH field.

–iii. Source master layer in the SMS field where source resides.

–iv. Destination master layer in the DMS field where destination resides.

–v. Incrementing/decrementing or fixed address for source in SINC field.

–vi. Incrementing/decrementing or fixed address for destination DINC field.

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3. Write the starting source address in the SARx register for channel x.

Note: The values in the LLI.SARx register locations of each of the Linked List Items (LLIs) setup up in memory, although fetched during a LLI fetch, are not used.

4. Write the channel configuration information into the CFGx register for channel x.

a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘1’ activates the software handshaking interface source/destination requests.

b. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral.

This requires programming the SRC_PER and DEST_PER bits, respectively.

5. Make sure that the LLI.CTLx register locations of all LLIs in memory (except the last) are set as shown in Row 7 of

Table 18-1 on page 179 while the LLI.CTLx register of the last

Linked List item must be set as described in Row 1 or Row 5 of Table 18-1 on page

179

.

Figure 18-5 on page 177 shows a Linked List example with two list items.

6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item.

7. Make sure that the LLI.DARx register location of all LLIs in memory point to the start destination block address proceeding that LLI fetch.

8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in memory is cleared.

9. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, Clear-

Err. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared.

10.Program the CTLx, CFGx registers according to Row 7 as shown in Table 18-1 on page

179

.

11.Program the LLPx register with LLPx(0), the pointer to the first Linked List item.

12.Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is performed. Make sure that bit 0 of the DmaCfgReg register is enabled.

13.The DMACA fetches the first LLI from the location pointed to by LLPx(0).

Note: The LLI.SARx, LLI.DARx, LLI. LLPx and LLI.CTLx registers are fetched. The LLI.SARx register although fetched is not used.

14.Source and destination request single and burst DMACA transactions to transfer the block of data (assuming non-memory peripherals). DMACA acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer.

15.

Table 18-1 on page 179

The DMACA reloads the SARx register from the initial value.

Hardware sets the block complete interrupt. The DMACA samples the row number as

shown in Table 18-1 on page 179 . If the DMACA is in Row 1 or 5, then the DMA trans-

fer has completed. Hardware sets the transfer complete interrupt and disables the channel. You can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMACA is not in Row 1 or 5 as shown in

Table 18-1 on page 179 the following steps are performed.

16.The DMA transfer proceeds as follows: a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is unmasked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the

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block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should clear the CFGx.RELOAD_SR source reload bit. This puts the DMACA into

Row1 as shown in

Table 18-1 on page 179 . If the next block is not the last block in

the DMA transfer, then the source reload bit should remain enabled to keep the

DMACA in Row 7 as shown in

Table 18-1 on page 179 .

b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is masked (MaskBlock[x] = 1’b0, where x is the channel number) then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case, software must clear the source reload bit, CFGx.RELOAD_SR, to put the device into Row 1 of

Table 18-1 on page 179 before the last block of the DMA transfer has completed.

17.The DMACA fetches the next LLI from memory location pointed to by the current LLPx register, and automatically reprograms the DARx, CTLx and LLPx channel registers.

Note that the SARx is not re-programmed as the reloaded value is used for the next

DMA block transfer. If the next block is the last block of the DMA transfer then the CTLx

and LLPx registers just fetched from the LLI should match Row 1 or Row 5 of Table 18-

1 on page 179

. The DMA transfer might look like that shown in

Figure 18-11 on page

191

.

Figure 18-11. Multi-Block DMA Transfer with Source Address Auto-reloaded and Linked List

Address of

Source Layer

Address of

Destination Layer

SAR

Block0

DAR(0)

Block1

DAR(1)

Block2

DAR(2)

BlockN

DAR(N)

Source Blocks

Destination Blocks

Destination Address

The DMA Transfer flow is shown in Figure 18-12 on page 192

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AT32AP7001

Figure 18-12. DMA Transfer Flow for Source Address Auto-reloaded and Linked List Destination Address

Channel Enabled by software

LLI Fetch

Hardware reprograms

DARx, CTLx, LLPx

DMAC block transfer

Source/destination status fetch

Reload SARx

Block Complete interrupt generated here yes

DMAC Transfer Complete interrupt generated here

Is DMAC in

Row1 or Row5 of

DMAC State Machine Table?

Channel Disabled by hardware no

CTLx.INT_EN=1

&&

MASKBLOCK[X]=1 ?

no yes

Stall until block interrupt

Cleared by hardware

192

AT32AP7001

18.9.1.5

Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3)

1. Read the Channel Enable register to choose a free (disabled) channel.

2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, Clear-

Err. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared.

3. Program the following channel registers: a. Write the starting source address in the SARx register for channel x.

b. Write the starting destination address in the DARx register for channel x.

c. Program CTLx and CFGx according to Row 3 as shown in

Table 18-1 on page 179 .

Program the LLPx register with ‘0’.

d. Write the control information for the DMA transfer in the CTLx register for channel x.

For example, in this register, you can program the following:

–i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register.

–ii. Set up the transfer characteristics, such as:

– Transfer width for the source in the SRC_TR_WIDTH field.

– Transfer width for the destination in the DST_TR_WIDTH field.

– Source master layer in the SMS field where source resides.

– Destination master layer in the DMS field where destination resides.

– Incrementing/decrementing or fixed address for source in SINC field.

– Incrementing/decrementing or fixed address for destination in DINC field.

e. Write the channel configuration information into the CFGx register for channel x.

–i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘1’ activates the software handshaking interface to handle source/destination requests.

–ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral.

This requires programming the SRC_PER and DEST_PER bits, respectively.

4. After the DMACA channel has been programmed, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is enabled.

5. Source and destination request single and burst DMACA transactions to transfer the block of data (assuming non-memory peripherals). The DMACA acknowledges at the completion of every transaction (burst and single) in the block and carries out the block transfer.

6. When the block transfer has completed, the DMACA reloads the SARx register. The

DARx register remains unchanged. Hardware sets the block complete interrupt. The

DMACA then samples the row number as shown in

Table 18-1 on page 179 . If the

DMACA is in Row 1, then the DMA transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. So you can either respond to the Block

Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEn-

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Reg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete.

If the DMACA is not in Row 1, the next step is performed.

7. The DMA transfer proceeds as follows: a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is unmasked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should clear the source reload bit, CFGx.RELOAD_SR. This puts the DMACA into

Row1 as shown in

Table 18-1 on page 179 . If the next block is not the last block in

the DMA transfer then the source reload bit should remain enabled to keep the

DMACA in Row3 as shown in Table 18-1 on page 179 .

b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is masked (MaskBlock[x] = 1’b0, where x is the channel number) then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case software must clear the source reload bit, CFGx.RELOAD_SR, to put the device into ROW 1 of

Table 18-1 on page 179 before the last block of the DMA transfer has completed.

The transfer is similar to that shown in Figure 18-13 on page 194 .

The DMA Transfer flow is shown in Figure 18-14 on page 195 .

Figure 18-13. Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address

Address of

Source Layer

Address of

Destination Layer

Block2

DAR(2)

Block1

DAR(1)

Block0

SAR

DAR(0)

Source Blocks

Destination Blocks

194

AT32AP7001

Figure 18-14. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination

Address

Channel Enabled by software

Block Transfer

Reload SARx, CTLx

Block Complete interrupt generated here

DMAC Transfer Complete interrupt generated here yes Is DMAC in Row1 of

DMAC State Machine Table?

Channel Disabled by hardware no

CTLx.INT_EN=1

&&

MASKBLOCK[x]=1?

no yes

Stall until Block Complete interrupt cleared by software

18.9.1.6

Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8)

1. Read the Channel Enable register to choose a free (disabled) channel.

2. Set up the linked list in memory. Write the control information in the LLI. CTLx register location of the block descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the CTLx register.

b. Set up the transfer characteristics, such as:

–i. Transfer width for the source in the SRC_TR_WIDTH field.

–ii. Transfer width for the destination in the DST_TR_WIDTH field.

–iii. Source master layer in the SMS field where source resides.

–iv. Destination master layer in the DMS field where destination resides.

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–v. Incrementing/decrementing or fixed address for source in SINC field.

–vi. Incrementing/decrementing or fixed address for destination DINC field.

3. Write the starting destination address in the DARx register for channel x.

Note: The values in the LLI.DARx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used.

4. Write the channel configuration information into the CFGx register for channel x.

a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘1’ activates the software handshaking interface to handle source/destination requests.

b. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripherals.

This requires programming the SRC_PER and DEST_PER bits, respectively.

5. Make sure that all LLI.CTLx register locations of the LLI (except the last) are set as

shown in Row 8 of Table 18-1 on page 179 , while the LLI.CTLx register of the last

Linked List item must be set as described in Row 1 or Row 5 of Table 18-1 on page

179

.

Figure 18-5 on page 177 shows a Linked List example with two list items.

6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item.

7. Make sure that the LLI.SARx register location of all LLIs in memory point to the start source block address proceeding that LLI fetch.

8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in memory is cleared.

9. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, Clear-

Err. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared.

10.Program the CTLx, CFGx registers according to Row 8 as shown in Table 18-1 on page

179

11.Program the LLPx register with LLPx(0), the pointer to the first Linked List item.

12.Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is performed. Make sure that bit 0 of the DmaCfgReg register is enabled.

13.The DMACA fetches the first LLI from the location pointed to by LLPx(0).

Note: The LLI.SARx, LLI.DARx, LLI.LLPx and LLI.CTLx registers are fetched. The LLI.DARx register location of the LLI although fetched is not used. The DARx register in the DMACA remains unchanged.

14.Source and destination requests single and burst DMACA transactions to transfer the block of data (assuming non-memory peripherals). The DMACA acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer.

Note:

15.The DMACA does not wait for the block interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by current LLPx register and automatically reprograms the SARx, CTLx and LLPx channel registers. The DARx register is left unchanged. The DMA transfer continues until the DMACA samples the CTLx and LLPx registers at the end of a block transfer match that described in Row 1 or Row

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5 of Table 18-1 on page 179 . The DMACA then knows that the previous block trans-

ferred was the last block in the DMA transfer.

The DMACA transfer might look like that shown in Figure 18-15 on page 197 Note that the des-

tination address is decrementing.

Figure 18-15. DMA Transfer with Linked List Source Address and Contiguous Destination

Address

Address of

Source Layer

Address of

Destination Layer

Block 2

SAR(2)

Block 2

DAR(2)

Block 1

Block 1

SAR(1) DAR(1)

Block 0

Block 0

SAR(0)

Source Blocks

Destination Blocks

The DMA transfer flow is shown in Figure 18-16 on page 198 .

DAR(0)

197

AT32AP7001

Figure 18-16. DMA Transfer Flow for Source Address Auto-reloaded and Contiguous Destination Address

Channel Enabled by software

LLI Fetch

Hardware reprograms

SARx, CTLx, LLPx

DMAC block transfer

Source/destination status fetch

Block Complete interrupt generated here

Is DMAC in

Row 1 of Table 4 ?

no

DMAC Transfer Complete interrupt generated here yes

Channel Disabled by hardware

18.10 Disabling a Channel Prior to Transfer Completion

Under normal operation, software enables a channel by writing a ‘1’ to the Channel Enable Register, ChEnReg.CH_EN, and hardware disables a channel on transfer completion by clearing the

ChEnReg.CH_EN register bit.

The recommended way for software to disable a channel without losing data is to use the

CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register

(CFGx) register.

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1. If software wishes to disable a channel prior to the DMA transfer completion, then it can set the CFGx.CH_SUSP bit to tell the DMACA to halt all transfers from the source peripheral. Therefore, the channel FIFO receives no new data.

2. Software can now poll the CFGx.FIFO_EMPTY bit until it indicates that the channel FIFO is empty.

3. The ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is empty.

When CTLx.SRC_TR_WIDTH is less than CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel

FIFO but not enough to form a single transfer of CTLx.DST_TR_WIDTH width. In this configuration, once the channel is disabled, the remaining data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the suspension state by writing a ‘0’ to the CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.

Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement.

18.10.1

Abnormal Transfer Termination

A DMACA DMA transfer may be terminated abruptly by software by clearing the channel enable bit, ChEnReg.CH_EN. This does not mean that the channel is disabled immediately after the

ChEnReg.CH_EN bit is cleared over the HSB slave interface. Consider this as a request to disable the channel. The ChEnReg.CH_EN must be polled and then it must be confirmed that the channel is disabled by reading back 0. A case where the channel is not be disabled after a channel disable request is where either the source or destination has received a split or retry response. The DMACA must keep re-attempting the transfer to the system HADDR that originally received the split or retry response until an OKAY response is returned. To do otherwise is an System Bus protocol violation.

Software may terminate all channels abruptly by clearing the global enable bit in the DMACA

Configuration Register (DmaCfgReg[0]). Again, this does not mean that all channels are disabled immediately after the DmaCfgReg[0] is cleared over the HSB slave interface. Consider this as a request to disable all channels. The ChEnReg must be polled and then it must be confirmed that all channels are disabled by reading back ‘0’.

Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals such as a source FIFO this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral upon request and is not lost.

Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement.

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18.11 DMA Controller (DMACA) User Interface

Table 18-2.

DMA Controller (DMACA) User Interface

Offset Register

0x60

0x64

0x68

0x7C

0x70

0x74

0x78

0x7C

0x40

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x80

0x84

0x88

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x0

0x4

0x8

0xC

0x10

0x14

0x18

0x1C

Channel 0 Source Address Register

Reserved

Channel 0 Destination Address Register

Reserved

Channel 0 Linked List Pointer Register

Reserved

Channel 0 Control Register Low

Channel 0 Control Register High

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Channel 0 Configuration Register low

Channel 0 Configuration Register High

Reserved

Reserved

Reserved

Reserved

Channel 1 Source Address Register

Reserved

Channel 1 Destination Address Register

Reserved

Channel 1 Linked List Pointer Register

Reserved

Channel 1 Control Register Low

Channel 1 Control Register High

Reserved

Reserved

Reserved

Reserved

Reserved

SAR1

-

DAR1

-

LLP1

-

CTL1L

CTL1H

-

-

-

-

-

-

-

-

-

-

-

CFG0L

CFG0H

Register Name

SAR0

-

DAR0

-

LLP0

-

-

-

-

-

CTL0L

CTL0H

-

-

32015D–AVR32–10/07

0x0

-

-

-

0x0

-

0x0

-

-

-

0x00000c00

0x00000004

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Reset Value

0x0

-

0x0

-

0x0

-

200

-

-

Read/Write

Read/Write

-

-

-

-

Read/Write

-

Read/Write

-

Read/Write

-

Read/Write

Read/Write

-

-

-

-

-

Access

Read/Write

-

Read/Write

-

Read/Write

-

Read/Write

Read/Write

-

-

-

-

-

-

AT32AP7001

0xec

0xf0

0xf4

0xf8

0xfc

0x100..0x2b

c

0x2c0

0xcc

0xd0

0xd4

0xd8

0xdc

0xe0

0xe4

0xe8

0x2c4

0x2c8

0x2cc

0x2d0

0xac

0xb0

0xb4

0xb8

0xbc

0xc0

0xc4

0xc8

0x8C

0x90

0x94

0x98

0x9C

0xa0

0xa4

0xa8

Table 18-2.

DMA Controller (DMACA) User Interface (Continued)

Offset Register Register Name

Reserved

Reserved

Reserved

Channel 1 Configuration Register Low

Channel 1 Configuration Register High

Reserved

Reserved

Reserved

Channel 2 Source Address Register

Reserved

Channel 2 Destination Address Register

Reserved

Channel 2 Linked List Pointer Register

Reserved

Channel 2 Control Register Low

Channel 2 Control Register High

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Channel 2 Configuration Register low

Channel 2 Configuration Register High

Reserved

Reserved

Reserved

Reserved

Raw Status for IntTfr Interrupt

Reserved

Raw Status for IntBlock Interrupt

Reserved

Raw Status for IntSrcTran Interrupt

-

-

-

-

-

-

-

-

CFG2L

CFG2H

-

-

-

SAR2

-

DAR2

-

LLP2

-

CTL2L

CTL2H

-

-

-

CFG1L

CFG1H

-

-

-

-

RawTfr

-

RawBlock

-

RawSrcTran

-

-

0x00000c00

0x00000004

-

-

-

-

-

-

-

-

-

-

-

0x0

-

0x0

-

-

-

0x0

-

Reset Value

-

-

-

0x00000c20

0x00000004

-

-

0x0

-

0x0

-

0x0

Read/Write

Read/Write

-

-

-

-

-

-

-

-

Read/Write

Read/Write

-

-

-

Access

-

-

-

Read/Write

Read/Write

-

-

-

Read/Write

-

Read/Write

-

Read/Write

-

-

Read

-

Read

-

Read

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Table 18-2.

DMA Controller (DMACA) User Interface (Continued)

Offset Register Register Name

0x334

0x338

0x33c

0x340

0x344

0x348

0x34c

0x350

0x314

0x318

0x31c

0x320

0x324

0x328

0x32c

0x330

0x354

0x358

0x35c

0x360

0x2f4

0x2f8

0x2fc

0x300

0x304

0x308

0x30c

0x310

0x2d4

0x2d8

0x2dc

0x2e0

0x2e4

0x2e8

0x2ec

0x2f0

Reserved

Raw Status for IntDstTran Interrupt

Reserved

Raw Status for IntErr Interrupt

Reserved

Status for IntTfr Interrupt

Reserved

Status for IntBlock Interrupt

Reserved

Status for IntSrcTran Interrupt

Reserved

Status for IntDstTran Interrupt

Reserved

Status for IntErr Interrupt

Reserved

Mask for IntTfr Interrupt

Reserved

Mask for IntBlock Interrupt

Reserved

Mask for IntSrcTran Interrupt

Reserved

Mask for IntDstTran Interrupt

Reserved

Mask for IntErr Interrupt

Reserved

Clear for IntTfr Interrupt

Reserved

Clear for IntBlock Interrupt

Reserved

Clear for IntSrcTran Interrupt

Reserved

Clear for IntDstTran Interrupt

Reserved

Clear for IntErr Interrupt

Reserved

Status for each interrupt type

-

MaskBlock

-

MaskSrcTran

-

MaskDstTran

-

MaskErr

-

ClearTfr

-

ClearBlock

-

ClearSrcTran

-

ClearDstTran

-

ClearErr

-

StatusInt

-

RawDstTran

-

RawErr

-

StatusTfr

-

StatusBlock

-

StatusSrcTran

-

StatusDstTran

-

StatusErr

-

MaskTfr

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

Reset Value

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

-

0x0

-

Read/Write

-

Read/Write

-

Read/Write

-

Read/Write

-

Read/Write

-

Write

-

Write

-

Write

-

Write

-

Write

-

Read

-

Read

-

Read

-

Read

-

Read

Access

-

Read

-

Read

-

Read

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Table 18-2.

DMA Controller (DMACA) User Interface (Continued)

Offset Register Register Name

0x384

0x388

0x38c

0x390

0x394

0x398

0x39c

0x3a0

0x364

0x368

0x36c

0x370

0x374

0x378

0x37c

0x380

0x3a4

0x3a8

0x3ac

0x3b0

0x3b4

0x3b8

0x3b8

Reserved

Source Software Transaction Request Register

Reserved

Destination Software Transaction Request Register

Reserved

Single Source Transaction Request Register

Reserved

Single Destination Transaction Request Register

Reserved

Last Source Transaction Request Register

Reserved

Last Destination Transaction Request Register

Reserved

DMA Configuration Register

Reserved

Channel Enable Register

Reserved

DMA ID Register

Reserved

DMA Test Register

Reserved

Reserved

Reserved

-

ReqSrcReg

-

ReqDstReg

-

SglReqSrcReg

-

SglReqDstReg

-

LstSrcReg

-

LstDstReg

-

DmaCfgReg

-

ChEnReg

-

IdReg

-

DmaTestReg

-

-

-

Access

-

Read/Write

-

Read/Write

-

Read/Write

-

Read/Write

-

Read/Write

-

Read/Write

-

Read/Write

-

Read/Write

-

Read

-

Read/Write

-

-

-

-

0x0

-

0x0

-

0x0

-

0x0

Reset Value

-

0x0

-

0x0

-

0x0

-

0x0

-

DMA_ID_NUM

-

-

-

-

-

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18.11.1

Channel x Source Address Register

Name: SARx

Access: Read/Write

Reset: 0x0

31 30 29 28

23

15

7

22

14

6

21

13

5

20

12

4

SADD

27

19

SADD

11

SADD

3

SADD

10

2

26

18

9

1

25

17

8

0

24

16

The address offset for each channel is: [x *0x58]

For example, SAR0: 0x000, SAR1: 0x058, etc.

• SADD: Source Address of DMA transfer

The starting System Bus source address is programmed by software before the DMA channel is enabled or by a LLI update before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the source address of the current System Bus transfer.

Updated after each source System Bus transfer. The SINC field in the CTLx register determines whether the address increments, decrements, or is left unchanged on every source System Bus transfer throughout the block transfer.

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18.11.2

Channel x Destination Address Register

Name: DARx

Access: Read/Write

Reset: 0x0

31 30 29 28

23

15

7

22

14

6

21

13

5

20

12

4

DADD

27

19

DADD

11

DADD

3

DADD

10

2

26

18

9

1

25

17

8

0

24

16

The address offset for each channel is: 0x08+[x * 0x58]

For example, DAR0: 0x008, DAR1: 0x060, etc.

• DADD: Destination Address of DMA transfer

The starting System Bus destination address is programmed by software before the DMA channel is enabled or by a LLI update before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the destination address of the current System Bus transfer.

Updated after each destination System Bus transfer. The DINC field in the CTLx register determines whether the address increments, decrements or is left unchanged on every destination System Bus transfer throughout the block transfer.

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18.11.3

Linked List Pointer Register for Channel x

Name: LLPx

Access: Read/Write

Reset: 0x0

31 30 29 28

23

15

7

22

14

6

21

13

5

20

12

4

LOC

LOC

LOC

11

3

27

19

10

2

26

18

9

1

25

17

8

0

24

16

LOC LMS

The address offset for each channel is: 0x10+[x * 0x58]

For example, LLP0: 0x010, LLP1: 0x068, etc.

• LMS: List Master Select

Identifies the High speed bus interface for the device that stores the next linked list item.

• LOC: Address of the next LLI

Starting address in memory of next LLI if block chaining is enabled.

The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled.

The LLP register has two functions:

1. The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA transfer (single or multi-block).

If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to enabling the channel in order to set up the transfer type.

It (LLP.LOC != 0) contains the pointer to the next Linked Listed Item for block chaining using linked lists.

2. The LLPx register is also used to point to the address where write back of the control and source/destination status information occurs after block completion.

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18.11.4

Control Register for Channel x Low

Name: CTLxL

Access: Read/Write

Reset: 0x0

31

23

DMS

15

7

DINC

SRC_MSIZE

14

6

30

22

29

21

28

LLP_S_EN

20

TT_FC

13 12

5

SRC_TR_WIDTH

DEST_MSIZE

4

27

LLP_D_EN

19

-

11

3

26

SMS

18

-

10

SINC

2

DST_TR_WIDTH

25

17

-

9

1

24

DMS

16

SRC_MSIZE

8

DINC

0

INT_EN

The address offset for each channel is: 0x18+[x * 0x58]

For example, CTL0: 0x018, CTL1: 0x070, etc.

This register contains fields that control the DMA transfer. The CTLxL register is part of the block descriptor (linked list item) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled.

• INT_EN: Interrupt Enable Bit

If set, then all five interrupt generating sources are enabled.

• DST_TR_WIDTH: Destination Transfer Width

• SRC_TR_WIDTH: Source Transfer Width

SRC_TR_WIDTH/DST_TR_WIDTH

000

001

010

Other

Size (bits)

8

16

32

Reserved

• DINC: Destination Address Increment

Indicates whether to increment or decrement the destination address on every destination System Bus transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change”.

00 = Increment

01 = Decrement

1x = No change

• SINC: Source Address Increment

Indicates whether to increment or decrement the source address on every source System Bus transfer. If your device is fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change”.

00 = Increment

01 = Decrement

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1x = No change

• DEST_MSIZE: Destination Burst Transaction Length

Number of data items, each of width CTLx.DST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface.

• SRC_MSIZE: Source Burst Transaction Length

Number of data items, each of width CTLx.SRC_TR_WIDTH, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface.

• TT_FC: Transfer Type and Flow Control

The following transfer types are supported.

• Memory to Memory

• Memory to Peripheral

• Peripheral to Memory

Flow Control can be assigned to the DMACA, the source peripheral, or the destination peripheral.

TT_FC

000

001

010

011

100

101

110

111

Transfer Type

Memory to Memory

Memory to Peripheral

Peripheral to Memory

Peripheral to Peripheral

Peripheral to Memory

Peripheral to Peripheral

Memory to Peripheral

Peripheral to Peripheral

Flow Controller

DMACA

DMACA

DMACA

DMACA

Peripheral

Source Peripheral

Peripheral

Destination Peripheral

• DMS: Destination Master Select

Identifies the Master Interface layer where the destination device (peripheral or memory) resides.

00 = HSB master 1

01 = Reserved

10 = Reserved

11 = Reserved

• SMS: Source Master Select

Identifies the Master Interface layer where the source device (peripheral or memory) is accessed from.

00 = HSB master 1

01 = Reserved

10 = Reserved

11 = Reserved

• LLP_D_EN

Block chaining is only enabled on the destination side if the LLP_D_EN field is high and LLPx.LOC is non-zero.

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• LLP_S_EN

Block chaining is only enabled on the source side if the LLP_S_EN field is high and LLPx.LOC is non-zero.

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18.11.5

Control Register for Channel x High

Name: CTLxH

Access: Read/Write

Reset: 0x0

31

23

30

22

29

21

28

20

15

7

14

6

13

5

12

4

BLOCK_TS

11

3

27

19

26

18

10

BLOCK_TS

2

9

1

25

17

8

0

24

16

• BLOCK_TS: Block Transfer Size

When the DMACA is flow controller, this field is written by the user before the channel is enabled to indicate the block size.

The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer. The width of the single transaction is determined by CTLx.SRC_TR_WIDTH.

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18.11.6

Configuration Register for Channel x Low

Name: CFGxL

Access: Read/Write

Reset: 0x0

31 30

RELOAD_DS RELOAD_SR

23 22

MAX_ABRST

29

21

15 14 13

7

LOCK_B_L

6

CH_PRIOR

5

LOCK_CH_L

28

20

12

4

27

19

11

MAX_ABRST

26

18

SR_HS_POL DS_HS_POL

10

25

17

LOCK_B

9

HS_SEL_SR HS_SEL_DS FIFO_EMPT

3 2 1

– – –

24

16

LOCK_CH

8

CH_SUSP

0

The address offset for each channel is: 0x40+[x * 0x58]

For example, CFG0: 0x040, CFG1: 0x098, etc.

• CH_PRIOR: Channel priority

A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the following range [0, x – 1]

A programmed value outside this range causes erroneous behavior.

• CH_SUSP: Channel Suspend

Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel without losing any data.

0 = Not Suspended.

1 = Suspend. Suspend DMA transfer from the source.

• FIFO_EMPTY

Indicates if there is data left in the channel's FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel.

1 = Channel's FIFO empty

0 = Channel's FIFO not empty

• HS_SEL_DST: Destination Software or Hardware Handshaking Select

This register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this channel.

0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.

1 = Software handshaking interface. Hardware Initiated transaction requests are ignored.

If the destination peripheral is memory, then this bit is ignored.

• HS_SEL_SRC: Source Software or Hardware Handshaking Select

This register selects which of the handshaking interfaces, hardware or software, is active for source requests on this channel.

0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.

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1 = Software handshaking interface. Hardware-initiated transaction requests are ignored.

If the source peripheral is memory, then this bit is ignored.

• LOCK_CH_L: Channel Lock Level

Indicates the duration over which CFGx.LOCK_CH bit applies.

00 = Over complete DMA transfer

01 = Over complete DMA block transfer

1x = Over complete DMA transaction

• LOCK_B_L: Bus Lock Level

Indicates the duration over which CFGx.LOCK_B bit applies.

00 = Over complete DMA transfer

01 = Over complete DMA block transfer

1x = Over complete DMA transaction

• LOCK_CH: Channel Lock Bit

When the channel is granted control of the master bus interface and if the CFGx.LOCK_CH bit is asserted, then no other channels are granted control of the master bus interface for the duration specified in CFGx.LOCK_CH_L. Indicates to the master bus interface arbiter that this channel wants exclusive access to the master bus interface for the duration specified in CFGx.LOCK_CH_L.

• LOCK_B: Bus Lock Bit

When active, the System Bus master signal hlock is asserted for the duration specified in CFGx.LOCK_B_L.

• DS_HS_POL: Destination Handshaking Interface Polarity

0 = Active high

1 = Active low

• SR_HS_POL: Source Handshaking Interface Polarity

0 = Active high

1 = Active low

• MAX_ABRST: Maximum System Bus Burst Length

Maximum System Bus burst length that is used for DMA transfers on this channel. A value of ‘0’ indicates that software is not limiting the maximum burst length for DMA transfers on this channel.

• RELOAD_SR: Automatic Source Reload

The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.

• RELOAD_DS: Automatic Destination Reload

The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.

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18.11.7

Configuration Register for Channel x High

Name: CFGxH

Access: Read/Write

Reset: 0x0

31

23

15

7

SRC_PER

30

22

14

6

-

29

21

13

DEST_PER

5

-

28

20

12

4

27

19

11

3

PROTCTL

26

18

10

2

25

17

9

SRC_PER

1

FIFO_MODE

24

16

8

0

FCMODE

• FCMODE: Flow Control Mode

Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller.

0 = Source transaction requests are serviced when they occur. Data pre-fetching is enabled.

1 = Source transaction requests are not serviced until a destination transaction request occurs. In this mode the amount of data transferred from the source is limited such that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.

• FIFO_MODE: R/W 0x0 FIFO Mode Select

Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced.

0 = Space/data available for single System Bus transfer of the specified transfer width.

1 = Space/data available is greater than or equal to half the FIFO depth for destination transfers and less than half the FIFO depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.

• PROTCTL: Protection Control

Bits used to drive the System Bus HPROT[3:1] bus. The System Bus Specification recommends that the default value of

HPROT indicates a non-cached, nonbuffered, privileged data access. The reset value is used to indicate such an access.

HPROT[0] is tied high as all transfers are data accesses as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals.

• SRC_PER: Source Hardware Handshaking Interface

Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the source of channel x if the

CFGx.HS_SEL_SRC field is 0. Otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface via the assigned hardware handshaking interface.

For correct DMACA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.

• DEST_PER: Destination Hardware Handshaking Interface

Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of channel x if the

CFGx.HS_SEL_DST field is 0. Otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface via the assigned hardware handshaking interface.

For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.

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18.11.8

Interrupt Registers

The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel, there are five types of interrupt sources:

• IntTfr: DMA Transfer Complete Interrupt

This interrupt is generated on DMA transfer completion to the destination peripheral.

• IntBlock: Block Transfer Complete Interrupt

This interrupt is generated on DMA block transfer completion to the destination peripheral.

• IntSrcTran: Source Transaction Complete Interrupt

This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from the handshaking interface on the source side.

If the source for a channel is memory, then that channel never generates a IntSrcTran interrupt and hence the corresponding bit in this field is not set.

• IntDstTran: Destination Transaction Complete Interrupt

This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from the handshaking interface on the destination side.

If the destination for a channel is memory, then that channel never generates the IntDstTran interrupt and hence the corresponding bit in this field is not set.

• IntErr: Error Interrupt

This interrupt is generated when an ERROR response is received from an HSB slave on the HRESP bus during a DMA transfer. In addition, the DMA transfer is cancelled and the channel is disabled.

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18.11.9

Interrupt Raw Status Registers

Name: RawTfr, RawBlock, RawSrcTran, RawDstTran, RawErr

Access: Read

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

10

2

RAW2

25

17

1

9

RAW1

24

16

0

8

RAW0

The address offset are

RawTfr – 0x2c0

RawBlock – 0x2c8

RawSrcTran – 0x2d0

RawDstTran – 0x2d8

RawErr – 0x2e0

• RAW[2:0]: Raw interrupt for each channel

Interrupt events are stored in these Raw Interrupt Status Registers before masking: RawTfr, RawBlock, RawSrcTran,

RawDstTran, RawErr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr[2] is Channel 2’s raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers.

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18.11.10 Interrupt Status Registers

Name: StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr

Access: Read

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

10

2

STATUS2

25

17

1

9

STATUS1

24

16

0

8

STATUS0

The address offset are

StatusTfr: 0x2e8

StatusBlock: 0x2f0

StatusSrcTran: 0x2f8

StatusDstTran: 0x300

StatusErr: 0x308

• STATUS[2:0]

All interrupt events from all channels are stored in these Interrupt Status Registers after masking: StatusTfr, StatusBlock,

StatusSrcTran, StatusDstTran, StatusErr. Each Interrupt Status register has a bit allocated per channel, for example, StatusTfr[2] is Channel 2’s status transfer complete interrupt.The contents of these registers are used to generate the interrupt signals leaving the DMACA.

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18.11.11 Interrupt Status Registers

Name: MaskTfr, MaskBlock, MaskSrcTran, MaskDstTran, MaskErr

Access: Read/Write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

10

INT_M_WE2

2

INT_MASK2

25

17

24

16

9

8

INT_M_WE1 INT_M_WE0

1 0

INT_MASK1 INT_MASK0

The address offset are

MaskTfr: 0x310

MaskBlock: 0x318

MaskSrcTran: 0x320

MaskDstTran: 0x328

MaskErr: 0x330

The contents of the Raw Status Registers are masked with the contents of the Mask Registers: MaskTfr, MaskBlock,

MaskSrcTran, MaskDstTran, MaskErr. Each Interrupt Mask register has a bit allocated per channel, for example, Mask-

Tfr[2] is the mask bit for Channel 2’s transfer complete interrupt.

A channel’s INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same System Bus write transfer. This allows software to set a mask bit without performing a read-modified write operation.

For example, writing hex 01x1 to the MaskTfr register writes a 1 into MaskTfr[0], while MaskTfr[7:1] remains unchanged.

Writing hex 00xx leaves MaskTfr[7:0] unchanged.

Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMACA to set the appropriate bit in the Status Registers.

• INT_MASK[2:0]: Interrupt Mask

0 = Masked

1 = Unmasked

• INT_M_WE[10:8]: Interrupt Mask Write Enable

0 = Write disabled

1 = Write enabled

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18.11.12 Interrupt Clear Registers

Name: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,ClearErr

Access: Write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

10

2

CLEAR2

25

17

1

9

CLEAR1

24

16

0

8

CLEAR0

The address offset are

ClearTfr: 0x338

ClearBlock: 0x340

ClearSrcTran: 0x348

ClearDstTran: 0x350

ClearErr: 0x358

• CLEAR[2:0]: Interrupt Clear

0 = No effect

1 = Clear interrupt

Each bit in the Raw Status and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in the Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Each Interrupt Clear register has a bit allocated per channel, for example, ClearTfr[2] is the clear bit for Channel 2’s transfer complete interrupt. Writing a 0 has no effect. These registers are not readable.

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18.11.13 Combined Interrupt Status Registers

Name: StatusInt

Access: Read

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

28

20

12

4

ERR

27

19

11

3

DSTT

26

18

10

2

SRCT

25

17

1

9

BLOCK

24

16

0

8

TFR

The contents of each of the five Status Registers (StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr) is

OR’d to produce a single bit per interrupt type in the Combined Status Register (StatusInt).

• TFR

OR of the contents of StatusTfr Register.

• BLOCK

OR of the contents of StatusBlock Register.

• SRCT

OR of the contents of StatusSrcTran Register.

• DSTT

OR of the contents of StatusDstTran Register.

• ERR

OR of the contents of StatusErr Register.

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18.11.14 Source Software Transaction Request Register

Name: ReqSrcReg

Access: Read/write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

10

REQ_WE2

2

SRC_REQ2

25

17

9

REQ_WE1

1

SRC_REQ1

24

16

8

REQ_WE0

0

SRC_REQ0

A bit is assigned for each channel in this register. ReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n.

A channel SRC_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write transfer.

For example, writing 0x101 writes a 1 into ReqSrcReg[0], while ReqSrcReg[3:1] remains unchanged. Writing hex 0x0yy leaves ReqSrcReg[3:0] unchanged. This allows software to set a bit in the ReqSrcReg register without performing a readmodified write

• SRC_REQ[2:0]: Source request

• REQ_WE[10:8]: Request write enable

0 = Write disabled

1 = Write enabled

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18.11.15 Destination Software Transaction Request Register

Name: ReqDstReg

Access: Read/write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

10

REQ_WE2

2

DST_REQ2

25

17

9

REQ_WE1

1

DST_REQ1

24

16

8

REQ_WE0

0

DST_REQ0

A bit is assigned for each channel in this register. ReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n.

A channel DST_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write transfer.

DST_REQ[

2:0]: Destination request

• REQ_WE[10:8]: Request write enable

0 = Write disabled

1 = Write enabled

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18.11.16 Single Source Transaction Request Register

Name: SglReqSrcReg

Access: Read/write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

25

17

24

16

10

REQ_WE2

2

9

REQ_WE1

1

8

REQ_WE0

0

S_SG_REQ2 S_SG_REQ1 S_SG_REQ0

A bit is assigned for each channel in this register. SglReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n.

A channel S_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write transfer.

• S_SG_REQ[2:0]: Source single request

• REQ_WE[10:8]: Request write enable

0 = Write disabled

1 = Write enabled

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18.11.17 Single Destination Transaction Request Register

Name: SglReqDstReg

Access: Read/write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

25

17

24

16

10

REQ_WE2

2

9

REQ_WE1

1

8

REQ_WE0

0

D_SG_REQ2 D_SG_REQ1 D_SG_REQ0

A bit is assigned for each channel in this register. SglReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n.

A channel D_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same System Bus write transfer.

• D_SG_REQ[2:0]: Destination single request

• REQ_WE[10:8]: Request write enable

0 = Write disabled

1 = Write enabled

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18.11.18 Last Source Transaction Request Register

Name: LstSrcReqReg

Access: Read/write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

25

17

24

16

10

9

8

LSTSR_WE2 LSTSR_WE1 LSTSR_WE0

2 1 0

LSTSRC2 LSTSRC1 LSTSRC0

A bit is assigned for each channel in this register. LstSrcReqReg[n] is ignored when software handshaking is not enabled for the source of channel n.

A channel LSTSRC bit is written only if the corresponding channel write enable bit in the LSTSR_WE field is asserted on the same System Bus write transfer.

• LSTSRC[2:0]: Source Last Transaction request

• LSTSR_WE[10 : 8]: Source Last Transaction request write enable

0 = Write disabled

1 = Write enabled

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18.11.19 Last Destination Transaction Request Register

Name: LstDstReqReg

Access: Read/write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

25

17

24

16

10

9

8

LSTDS_WE2 LSTDS_WE1 LSTDS_WE0

2 1 0

LSTDST2 LSTDST1 LSTDST0

A bit is assigned for each channel in this register. LstDstReqReg[n] is ignored when software handshaking is not enabled for the source of channel n.

A channel LSTDST bit is written only if the corresponding channel write enable bit in the LSTDS_WE field is asserted on the same System Bus write transfer.

• LSTDST[2:0]: Destination Last Transaction request

• LSTDS_WE[10:8]: Destination Last Transaction request write enable

0 = Write disabled

1 = Write enabled

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18.11.20 DMACA Configuration Register

Name: DmaCfgReg

Access: Read/Write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

10

2

26

18

1

9

25

17

24

16

0

8

DMA_EN

• DMA_EN: DMA Controller Enable

0 = DMACA Disabled

1 = DMACA Enabled.

This register is used to enable the DMACA, which must be done before any channel activity can begin.

If the global channel enable bit is cleared while any channel is still active, then DmaCfgReg.DMA_EN still returns ‘1’ to indicate that there are channels still active until hardware has terminated all activity on all channels, at which point the

DmaCfgReg.DMA_EN bit returns ‘0’.

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18.11.21 DMACA Channel Enable Register

Name: ChEnReg

Access: Read/Write

Reset: 0x0

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

25

17

24

16

10

9

8

CH_EN_WE2 CH_EN_WE1 CH_EN_WE0

2 1 0

CH_EN2 CH_EN1 CH_EN0

• CH_EN[2:0]

0 = Disable the Channel

1 = Enable the Channel

Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel.

The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last System Bus transfer of the DMA transfer to the destination has completed.Software can therefore poll this bit to determine when a DMA transfer has completed.

• CH_EN_WE[10:8]

The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on the same System Bus write transfer.

For example, writing 0x101 writes a 1 into ChEnReg[0], while ChEnReg[7:1] remains unchanged.

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19. Peripheral DMA Controller (PDC)

Rev: 1.0.0.1

19.1

Features

Generates Transfers to/from Peripherals such as USART, SSC and SPI

Supports Up to 20 Channels (Product Dependent)

One Master Clock Cycle Needed for a Transfer from Memory to Peripheral

Two Master Clock Cycles Needed for a Transfer from Peripheral to Memory

19.2

Description

The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, and the on- and off-chip memories. Using the Peripheral DMA

Controller avoids processor intervention and removes the processor interrupt-handling overhead. This significantly reduces the number of clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and makes it more power efficient.

The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral. One channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each UART, USART, SSC and SPI.

The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains:

• A 32-bit memory pointer register

• A 16-bit transfer count register

• A 32-bit register for next memory pointer

• A 16-bit register for next transfer count

The peripheral triggers PDC transfers using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral.

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19.3

Block Diagram

Figure 19-1. Block Diagram

Peripheral

THR

Peripheral DMA Controller

PDC Channel 0

RHR

PDC Channel 1 Control

Status & Control

Control

Memory

Controller

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19.4

Product Dependencies

19.4.1

19.4.2

19.4.3

Power Management

The PDC clock is generated by the Power Manager. The PDC also depends on the HSB-HSB bridge clock. Before using the PDC, the programmer must ensure that the PDC clock and HSB-

HSB bridge clock are enabled in the Power Manager.

To prevent bus errors the PDC operation must be terminated before entering sleep mode

Interrupt

The PDC has an interrupt line for each channel connected to the Interrupt Controller via the corresponding peripheral. Handling the PDC interrupt requires programming the interrupt controller before configuring the PDC.

Peripherals

Before using each PDC channel the corresponding peripheral has to be configured correctly.

19.5

Functional Description

19.5.1

Configuration

The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to.

Per peripheral, it contains four 32-bit Pointer Registers (RPR, RNPR, TPR, and TNPR) and four

16-bit Counter Registers (RCR, RNCR, TCR, and TNCR).

The size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel.

The memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. It is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC Transfer Control Register. These control bits enable reading the pointer and counter registers safely without any risk of their changing between both reads.

The PDC sends status flags to the peripheral visible in its status-register (ENDRX, ENDTX,

RXBUFF, and TXBUFE).

ENDRX flag is set when the PERIPH_RCR register reaches zero.

RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.

ENDTX flag is set when the PERIPH_TCR register reaches zero.

TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.

These status flags are described in the peripheral status register.

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19.5.2

19.5.3

19.5.4

Memory Pointers

Each peripheral is connected to the PDC by a receiver data channel and a transmitter data channel. Each channel has an internal 32-bit memory pointer. Each memory pointer points to a location anywhere in the memory space (on-chip memory or external bus interface memory).

Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4, respectively for peripheral transfers. The size of the transfer is setup up in the peripheral’s control register and automatically sensed by the PDC. The size is always rounded up to wither byte, half-word or word.

If a memory pointer is reprogrammed while the PDC is in operation, the transfer address is changed, and the PDC performs transfers using the new address.

Transfer Counters

Data Transfers

There is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its associated channel. These counters are decremented after each data transfer. When the counter reaches zero, the transfer is complete and the PDC stops transferring data.

If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag.

If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value.

Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to re-enable the triggers.

For each channel, two status bits indicate the end of the current buffer (ENDRX, ENTX) and the end of both current and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the peripheral status register and can trigger an interrupt request to the Interrupt Controller.

The peripheral end flag is automatically cleared when one of the counter-registers (Counter or

Next Counter Register) is written.

Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero.

The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals.

When the peripheral receives an external character, it sends a Receive Ready signal to the PDC which then requests access to the system bus. When access is granted, the PDC starts a read of the peripheral Receive Holding Register (RHR) and then triggers a write in the memory.

After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decremented. When the memory block size is reached, a signal is sent to the peripheral and the transfer stops.

The same procedure is followed, in reverse, for transmit transfers.

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19.5.5

Priority of PDC Transfer Requests

The Peripheral DMA Controller handles transfer requests from the channel according to priorities fixed for each product.These priorities are defined in the product datasheet.

If simultaneous requests of the same type (receiver or transmitter) occur on identical peripherals, the priority is determined by the numbering of the peripherals.

If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests.

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19.6

Peripheral DMA Controller (PDC) User Interface

Table 19-1.

Register Mapping

Offset

0x100

0x104

0x108

0x10C

0x110

0x114

0x118

0x11C

0x120

0x124

Register

Receive Pointer Register

Receive Counter Register

Transmit Pointer Register

Transmit Counter Register

Receive Next Pointer Register

Receive Next Counter Register

Transmit Next Pointer Register

Transmit Next Counter Register

PDC Transfer Control Register

PDC Transfer Status Register

Register Name

PERIPH

(1)

_RPR

PERIPH_RCR

PERIPH_TPR

PERIPH_TCR

PERIPH_RNPR

PERIPH_RNCR

PERIPH_TNPR

PERIPH_TNCR

PERIPH_PTCR

PERIPH_PTSR

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Write-only

Read-only

0x0

0x0

-

0x0

Reset

0x0

0x0

0x0

0x0

0x0

0x0

Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (USART, SSC, SPI, etc).

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19.6.1

PDC Receive Pointer Register

Register Name:

Access Type:

31 30 29

PERIPH_RPR

Read/Write

28

23

15

7

22

14

6

21

13

5

20

12

4

RXPTR

27

19

RXPTR

11

RXPTR

3

RXPTR

RXPTR: Receive Pointer Address

Address of the next receive transfer.

10

2

26

18

9

1

25

17

8

0

24

16

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19.6.2

PDC Receive Counter Register

Register Name:

Access Type:

31 30 29

PERIPH_RCR

Read/Write

28

23

15

7

22

14

6

21

13

5

27

--

20 19

--

12

RXCTR

11

4 3

RXCTR

RXCTR: Receive Counter Value

Number of receive transfers to be performed.

10

2

26

18

9

1

25

17

8

0

24

16

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19.6.3

PDC Transmit Pointer Register

Register Name:

Access Type:

31 30 29

PERIPH_TPR

Read/Write

28

23

15

7

22

14

6

21

13

5

20

12

4

TXPTR

27

19

TXPTR

11

TXPTR

3

TXPTR

TXPTR: Transmit Pointer Address

Address of the transmit buffer.

10

2

26

18

9

1

25

17

8

0

24

16

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19.6.4

PDC Transmit Counter Register

Register Name:

Access Type:

31 30 29

PERIPH_TCR

Read/Write

28 27 26 25

--

23 22 21 20 19 18 17

--

15 14 13 12 11 10 9

TXCTR

7 6 5 4 3 2 1

TXCTR

TXCTR: Transmit Counter Value

TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral data transfer is stopped.

8

0

24

16

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19.6.5

PDC Receive Next Pointer Register

Register Name:

Access Type:

31 30 29

PERIPH_RNPR

Read/Write

28

23 22 21

RXNPTR

20

RXNPTR

15 14 13 12

27

19

11

RXNPTR

7 6 5 4 3

RXNPTR

26

18

10

2

RXNPTR: Receive Next Pointer Address

RXNPTR is the address of the next buffer to fill with received data when the current buffer is full.

25

17

9

1

8

0

24

16

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19.6.6

PDC Receive Next Counter Register

Register Name:

Access Type:

31 30 29

PERIPH_RNCR

Read/Write

28

23

15

7

22

14

6

21

13

5

27

--

20 19

--

12

RXNCR

11

4 3

RXNCR

RXNCR: Receive Next Counter Value

RXNCR is the size of the next buffer to receive.

10

2

26

18

9

1

25

17

8

0

24

16

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19.6.7

PDC Transmit Next Pointer Register

Register Name:

Access Type:

31 30 29

PERIPH_TNPR

Read/Write

28 27 26

TXNPTR

23 22 21 20 19 18

TXNPTR

15 14 13 12 11 10

TXNPTR

7 6 5 4 3 2

TXNPTR

TXNPTR: Transmit Next Pointer Address

TXNPTR is the address of the next buffer to transmit when the current buffer is empty.

9

1

25

17

8

0

24

16

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19.6.8

PDC Transmit Next Counter Register

Register Name:

Access Type:

31 30 29

PERIPH_TNCR

Read/Write

28

23

15

7

22

14

6

21

13

5

27

--

20 19

--

12

TXNCR

11

4 3

TXNCR

TXNCR: Transmit Next Counter Value

TXNCR is the size of the next buffer to transmit.

10

2

26

18

9

1

25

17

8

0

24

16

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19.6.9

PDC Transfer Control Register

Register Name:

Access Type:

31

23

15

7

14

6

30

22

13

5

29

PERIPH_PTCR

Write

-

only

28

21

20

12

4

RXTEN: Receiver Transfer Enable

0 = No effect.

1 = Enables the receiver PDC transfer requests if RXTDIS is not set.

RXTDIS: Receiver Transfer Disable

0 = No effect.

1 = Disables the receiver PDC transfer requests.

TXTEN: Transmitter Transfer Enable

0 = No effect.

1 = Enables the transmitter PDC transfer requests.

TXTDIS: Transmitter Transfer Disable

0 = No effect.

1 = Disables the transmitter PDC transfer requests

11

3

27

19

10

2

26

18

25

17

9

TXTDIS

1

RXTDIS

24

16

8

TXTEN

0

RXTEN

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19.6.10

PDC Transfer Status Register

Register Name:

Access Type:

31

23

15

7

14

6

30

22

13

5

29

21

PERIPH_PTSR

Read-only

28

20

12

4

RXTEN: Receiver Transfer Enable

0 = Receiver PDC transfer requests are disabled.

1 = Receiver PDC transfer requests are enabled.

TXTEN: Transmitter Transfer Enable

0 = Transmitter PDC transfer requests are disabled.

1 = Transmitter PDC transfer requests are enabled.

11

3

27

19

10

2

26

18

1

9

25

17

24

16

8

TXTEN

0

RXTEN

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20. Parallel Input/Output Controller (PIO)

Rev: 2.0.2.2

20.1

Features

Up to 32 Programmable I/O Lines

Fully Programmable through Set/Clear Registers

Multiplexing of Two Peripheral Functions per I/O Line

For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)

– Input Change Interrupt

– Glitch Filter

– Programmable Pull Up on Each I/O Line

– Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time

Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write

20.2

Description

The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product.

Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User

Interface.

Each I/O line of the PIO Controller features:

• An input change interrupt enabling level change detection on any I/O line.

• A glitch filter providing rejection of pulses lower than one-half of clock cycle.

• Control of the the pull-up of the I/O line.

• Input visibility and output control.

The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.

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20.3

Block Diagram

Figure 20-1. Block Diagram

Interrupt

Controller

PIO Interrupt

Power Manager

PIO Clock

PIO Controller

Data, Enable

Embedded

Peripheral

Data, Enable

Up to 32 peripheral IOs

Up to 32 peripheral IOs

Embedded

Peripheral

Peripheral Bus

PIN 0

PIN 1

Up to 32 pins

PIN 31

Figure 20-2. Application Block Diagram

Keyboard Driver Control & Command

Driver

Keyboard Driver

PIO Controller

General Purpose I/Os

On-Chip Peripheral Drivers

On-Chip Peripherals

External Devices

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20.4

Product Dependencies

20.4.1

Pin Multiplexing

Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.

20.4.2

20.4.3

20.4.4

External Interrupt Lines

The external interrupt request signals are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO

Controller has no effect on inputs and the external interrupt lines are used only as inputs.

Power Management

The PIO clock is generated by the Power Manager. Before accessing the PIO, the programmer must ensure that the PIO clock is enabled in the Power Manager. Note that the PIO clock must be enabled when using the Input Change interrupt.

In the PIO description, Master Clock (MCK) is the clock of the peripheral bus to which the PIO is connected.

Interrupt Generation

The PIO interrupt line is connected to the Interrupt Controller. Using the PIO interrupt requires the Interrupt Controller to be programmed first.

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20.5

Functional Description

The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in

Figure 20-3 . In this description each signal shown

represents but one of up to 32 possible indexes.

Figure 20-3. I/O Line Control Logic

PIO_MDER[0]

PIO_MDSR[0]

PIO_MDDR[0]

PIO_SODR[0]

PIO_ODSR[0]

PIO_CODR[0]

PIO_OER[0]

PIO_OSR[0]

PIO_ODR[0]

1

1

Peripheral A

Output Enable 0

0

0

Peripheral B

Output Enable

PIO_ASR[0]

PIO_ABSR[0]

PIO_BSR[0]

Peripheral A

Output

1

0

Peripheral B

Output

1

PIO_SODR[0]

PIO_ODSR[0]

PIO_CODR[0]

PIO_PER[0]

PIO_PSR[0]

PIO_PDR[0]

1

0

0

1

PIO_MDER[0]

PIO_MDSR[0]

PIO_MDDR[0]

PIO_PUER[0]

PIO_PUSR[0]

PIO_PUDR[0]

Pad

Glitch

Filter

PIO_IFER[0]

PIO_IFSR[0]

PIO_IFDR[0]

1

PIO_PDSR[0]

0

Edge

Detector

PIO_IER[0]

PIO_ISR[0]

PIO_IMR[0]

PIO_IDR[0]

PIO_ISR[31]

PIO_IER[31]

PIO_IMR[31]

PIO_IDR[31]

Peripheral A

Input

Peripheral B

Input

(Up to 32 possible inputs)

PIO Interrupt

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20.5.1

20.5.2

20.5.3

20.5.4

Pull-up Resistor Control

Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PUER (Pull-up Enable Register) and PUDR (Pull-up Disable

Resistor). Writing in these registers results in setting or clearing the corresponding bit in PUSR

(Pull-up Status Register). Reading a 1 in PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.

Control of the pull-up resistor is possible regardless of the configuration of the I/O line.

After reset, all of the pull-ups are enabled, i.e. PUSR resets at the value 0x0.

I/O Line or Peripheral Function Selection

When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PER (PIO Enable Register) and PDR (PIO Disable Register). The register PSR

(PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the ABSR (AB Select

Status Register). A value of 1 indicates the pin is controlled by the PIO controller.

If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PER and PDR have no effect and PSR returns 1 for the corresponding bit.

After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PSR resets at

1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PSR is defined at the product level, depending on the multiplexing of the device.

Peripheral A or B Selection

The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing ASR (A Select Register) and BSR (Select B Register). ABSR

(AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected.

Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input.

After reset, ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.

Writing in ASR and BSR manages ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (ASR or BSR) in addition to a write in PDR.

Output Control

When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in ABSR, determines whether the pin is driven or not.

When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing OER (Output Enable Register) and ODR (Output Disable Register). The results of these write operations are detected in OSR (Output Status Register). When a bit in this

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20.5.5

20.5.6

register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller.

The level driven on an I/O line can be determined by writing in SODR (Set Output Data Register) and CODR (Clear Output Data Register). These write operations respectively set and clear

ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in OER and ODR manages OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller.

Similarly, writing in SODR and CODR effects ODSR. This is important as it defines the first level driven on the I/O line.

Multi-drive capability

The PIO is able to configure each pin as open drain to support external drivers on the same pin.

This is done by writing MDER (Multi-Drive Enable Register) and MDDR (Multi-Drive Disable

Register). The result of these write operations are detected in MDSR (multui-Drive Status Register). The multi-drive mode is only available when the PIO is controlling the pin, i.e. PSR is set.

When using multi-drive the PIO will tri-state the pin when ODSR is set and drive the pin low when ODSR is cleared. writing to OER or ODR will have no effect.

Synchronous Data Output

Controlling all parallel busses using several PIOs requires two successive write operations in the

SODR and CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to ODSR (Output Data Status Register). Only bits unmasked by OSWSR (Output Write Status Register) are written. The mask bits in the OWSR are set by writing to OWER (Output Write Enable Register) and cleared by writing to

OWDR (Output Write Disable Register).

After reset, the synchronous data output is disabled on all the I/O lines as OWSR resets at 0x0.

20.5.7

Output Line Timings

Figure 20-4 shows how the outputs are driven either by writing SODR or CODR, or by directly

writing ODSR. This last case is valid only if the corresponding bit in OWSR is set.

Figure 20-4

also shows when the feedback in PDSR is available.

Figure 20-4. Output Line Timings

MCK

Write PIO_SODR

Write PIO_ODSR at 1

Write PIO_CODR

Write PIO_ODSR at 0

PIO_ODSR

Peripheral Bus Access

Peripheral Bus Access

2 cycles 2 cycles

PIO_PDSR

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20.5.8

Inputs

The level on each I/O line can be read through PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.

Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise

PDSR reads the levels present on the I/O line at the time the clock was disabled.

20.5.9

Input Glitch Filtering

Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in

Figure 20-5

.

The glitch filters are controlled by the register set; IFER (Input Filter Enable Register), IFDR

(Input Filter Disable Register) and IFSR (Input Filter Status Register). Writing IFER and IFDR respectively sets and clears bits in IFSR. This last register enables the glitch filter on the I/O lines.

When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals.

It acts only on the value read in PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled.

Figure 20-5. Input Glitch Filter Timing

MCK up to 1.5 cycles

Pin Level

PIO_PDSR if PIO_IFSR = 0

PIO_PDSR if PIO_IFSR = 1

1 cycle 1 cycle 1 cycle

2 cycles up to 2.5 cycles

1 cycle

1 cycle up to 2 cycles

20.5.10

Input Change Interrupt

The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing IER (Interrupt Enable Register) and IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO

Controller or assigned to a peripheral function.

250

32015D–AVR32–10/07

AT32AP7001

When an input change is detected on an I/O line, the corresponding bit in ISR (Interrupt Status

Register) is set. If the corresponding bit in IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Interrupt Controller.

When the software reads ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when ISR is read must be handled.

Figure 20-6. Input Change Interrupt Timings

MCK

Pin Level

PIO_ISR

Read PIO_ISR Peripheral Bus Access Peripheral Bus Access

20.6

I/O Lines Programming Example

The programing example as shown in

Table 20-1 below is used to define the following

configuration.

• 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation)

• Four output signals on I/O lines 4 to 7 (to drive LEDs for example)

• Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts

• Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter

• I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor

• I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor

• I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor

251

32015D–AVR32–10/07

32015D–AVR32–10/07

Table 20-1.

Programming Example

Register

IER

IDR

PUDR

PUER

ASR

BSR

OWER

OWDR

PER

PDR

OER

ODR

IFER

IFDR

SODR

CODR

AT32AP7001

Value to be Written

0x0000 FFFF

0x0FFF 0000

0x0000 00FF

0x0FFF FF00

0x0000 0F00

0x0FFF F0FF

0x0000 0000

0x0FFF FFFF

0x0F00 0F00

0x00FF F0FF

0x00F0 00F0

0x0F0F FF0F

0x0F0F 0000

0x00F0 0000

0x0000 000F

0x0FFF FFF0

252

AT32AP7001

20.7

User Interface

Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PSR returns 1 systematically.

0x0044

0x0048

0x004C

0x0050

0x0054

0x0058

0x005C

0x0060

0x0064

0x0068

0x006C

0x0024

0x0028

0x002C

0x0030

0x0034

0x0038

0x003C

0x0040

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020

Table 20-2.

Register Mapping

Offset

0x0000

Register

PIO Enable Register

PIO Disable Register

PIO Status Register

(1)

Reserved

Output Enable Register

Output Disable Register

Output Status Register

Reserved

Glitch Input Filter Enable Register

Glitch Input Filter Disable Register

Glitch Input Filter Status Register

Reserved

Set Output Data Register

Clear Output Data Register

Output Data Status Register

(2)

Pin Data Status Register

(3)

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Interrupt Status Register

(4)

Multi-driver Enable Register

Multi-driver Disable Register

Multi-driver Status Register

Reserved

Pull-up Disable Register

Pull-up Enable Register

Pad Pull-up Status Register

Reserved

IFER

IFDR

IFSR

SODR

CODR

ODSR

PDSR

IER

IDR

IMR

ISR

MDER

MDDR

MDSR

PUDR

PUER

PUSR

Name

PER

PDR

PSR

OER

ODR

OSR

Access

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Read-only

Write-only

Write-only

Read-only

Read-only

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Reset Value

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

0x0000 0000

253

32015D–AVR32–10/07

AT32AP7001

Table 20-2.

Register Mapping (Continued)

Offset

0x0070

0x0074

Register

Peripheral A Select Register

(5)

Peripheral B Select Register

(5)

AB Status Register

(5)

0x0078

0x007C to

0x009C

0x00A0

Reserved

Output Write Enable

0x00A4

0x00A8

0x00AC

Output Write Disable

Output Write Status Register

Reserved

Name

ASR

BSR

ABSR

OWER

OWDR

OWSR

Access

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Reset Value

0x0000 0000

0x0000 0000

Notes: 1. Reset value of PSR depends on the product implementation.

2. ODSR is Read-only or Read/Write depending on OWSR I/O lines.

3. Reset value of PDSR depends on the level of the I/O lines.

4. ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred.

5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register.

254

32015D–AVR32–10/07

AT32AP7001

20.7.1

PIO Controller PIO Enable Register

Name:

Access Type:

PER

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

• P0-P31: PIO Enable

0 = No effect.

1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

255

32015D–AVR32–10/07

AT32AP7001

20.7.2

PIO Controller PIO Disable Register

Name:

Access Type:

PDR

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

• P0-P31: PIO Disable

0 = No effect.

1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

256

32015D–AVR32–10/07

AT32AP7001

20.7.3

PIO Controller PIO Status Register

Name:

Access Type:

PSR

Read-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

28

P28

20

P20

12

P12

4

P4

• P0-P31: PIO Status

0 = PIO is inactive on the corresponding I/O line (peripheral is active).

1 = PIO is active on the corresponding I/O line (peripheral is inactive).

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

257

32015D–AVR32–10/07

AT32AP7001

20.7.4

PIO Controller Output Enable Register

Name:

Access Type:

OER

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Enable

0 = No effect.

1 = Enables the output on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

258

32015D–AVR32–10/07

AT32AP7001

20.7.5

PIO Controller Output Disable Register

Name:

Access Type:

ODR

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Disable

0 = No effect.

1 = Disables the output on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

259

32015D–AVR32–10/07

AT32AP7001

20.7.6

PIO Controller Output Status Register

Name:

Access Type:

OSR

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Status

0 = The I/O line is a pure input.

1 = The I/O line is enabled in output.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

260

32015D–AVR32–10/07

AT32AP7001

20.7.7

PIO Controller Glitch Input Filter Enable Register

Name:

Access Type:

IFER

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Filter Enable

0 = No effect.

1 = Enables the input glitch filter on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

261

32015D–AVR32–10/07

AT32AP7001

20.7.8

PIO Controller Glitch Input Filter Disable Register

Name:

Access Type:

IFDR

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Filter Disable

0 = No effect.

1 = Disables the input glitch filter on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

262

32015D–AVR32–10/07

AT32AP7001

20.7.9

PIO Controller Glitch Input Filter Status Register

Name:

Access Type:

IFSR

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Filer Status

0 = The input glitch filter is disabled on the I/O line.

1 = The input glitch filter is enabled on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

263

32015D–AVR32–10/07

AT32AP7001

20.7.10

PIO Controller Set Output Data Register

Name:

Access Type:

SODR

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Set Output Data

0 = No effect.

1 = Sets the data to be driven on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

264

32015D–AVR32–10/07

AT32AP7001

20.7.11

PIO Controller Clear Output Data Register

Name:

Access Type:

CODR

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Set Output Data

0 = No effect.

1 = Clears the data to be driven on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

265

32015D–AVR32–10/07

AT32AP7001

20.7.12

PIO Controller Output Data Status Register

Name:

Access Type:

ODSR

Read-only or Read/Write

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Data Status

0 = The data to be driven on the I/O line is 0.

1 = The data to be driven on the I/O line is 1.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

266

32015D–AVR32–10/07

AT32AP7001

20.7.13

PIO Controller Pin Data Status Register

Name:

Access Type:

PDSR

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Output Data Status

0 = The I/O line is at level 0.

1 = The I/O line is at level 1.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

267

32015D–AVR32–10/07

AT32AP7001

20.7.14

PIO Controller Interrupt Enable Register

Name:

Access Type:

IER

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Change Interrupt Enable

0 = No effect.

1 = Enables the Input Change Interrupt on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

268

32015D–AVR32–10/07

AT32AP7001

20.7.15

PIO Controller Interrupt Disable Register

Name:

Access Type:

IDR

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Change Interrupt Disable

0 = No effect.

1 = Disables the Input Change Interrupt on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

269

32015D–AVR32–10/07

AT32AP7001

20.7.16

PIO Controller Interrupt Mask Register

Name:

Access Type:

IMR

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

• P0-P31: Input Change Interrupt Mask

0 = Input Change Interrupt is disabled on the I/O line.

1 = Input Change Interrupt is enabled on the I/O line.

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

270

32015D–AVR32–10/07

AT32AP7001

20.7.17

PIO Controller Interrupt Status Register

Name:

Access Type:

ISR

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

• P0-P31: Input Change Interrupt Status

0 = No Input Change has been detected on the I/O line since ISR was last read or since reset.

1 = At least one Input Change has been detected on the I/O line since ISR was last read or since reset.

24

P24

16

P16

8

P8

0

P0

271

32015D–AVR32–10/07

AT32AP7001

20.7.18

PIO Controller Multi-driver Enable Register

Name:

Access Type:

MDER

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

This register is used to enable PIO output drivers to be configured as open drain to support external drivers on the same pin.

• P0-P31:

0 = No effect.

1 = Enables multi-drive option on the corresponding pin.

272

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20.7.19

PIO Controller Multi-driver Disable Register

Name:

Access Type:

MDDR

Write-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

This register is used to diasble the open drain configuration of the output buffer.

• P0-P31:

0 = No effect.

1 = Disables multi-drive option on the corresponding pin.

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.20

PIO Controller Multi-driver Status Register

Name:

Access Type:

MDSR

Read-only

31

P31

30

P30

29

P29

28

P28

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

This register indicates which pins are configured with open drain drivers.

• P0-P31:

0 = PIO is not configured as an open drain.

1 = PIO is configured as an open drain.

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.21

PIO Pull Up Disable Register

Name:

Access Type:

PUDR

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Pull Up Disable.

0 = No effect.

1 = Disables the pull up resistor on the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.22

PIO Pull Up Enable Register

Name:

Access Type:

PUER

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Pull Up Enable.

0 = No effect.

1 = Enables the pull up resistor on the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.23

PIO Pull Up Status Register

Name:

Access Type:

PUSR

Read-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Pull Up Status.

0 = Pull Up resistor is enabled on the I/O line.

1 = Pull Up resistor is disabled on the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.24

PIO Peripheral A Select Register

Name:

Access Type:

ASR

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Peripheral A Select.

0 = No effect.

1 = Assigns the I/O line to the Peripheral A function.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.25

PIO Peripheral B Select Register

Name:

Access Type:

BSR

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Peripheral B Select.

0 = No effect.

1 = Assigns the I/O line to the peripheral B function.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.26

PIO Peripheral A B Status Register

Name:

Access Type:

ABSR

Read-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Peripheral A B Status.

0 = The I/O line is assigned to the Peripheral A.

1 = The I/O line is assigned to the Peripheral B.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.27

PIO Output Write Enable Register

Name:

Access Type:

OWER

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Output Write Enable.

0 = No effect.

1 = Enables writing ODSR for the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.28

PIO Output Write Disable Register

Name:

Access Type:

OWDR

Write-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Output Write Disable.

0 = No effect.

1 = Disables writing ODSR for the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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20.7.29

PIO Output Write Status Register

Name:

Access Type:

OWSR

Read-only

31

P31

30

P30

29

P29

23

P23

15

P15

7

P7

22

P22

14

P14

6

P6

21

P21

13

P13

5

P5

• P0-P31: Output Write Status.

0 = Writing ODSR does not affect the I/O line.

1 = Writing ODSR affects the I/O line.

28

P28

20

P20

12

P12

4

P4

27

P27

19

P19

11

P11

3

P3

26

P26

18

P18

10

P10

2

P2

25

P25

17

P17

9

P9

1

P1

24

P24

16

P16

8

P8

0

P0

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21. Serial Peripheral Interface (SPI)

Rev: 1.7.1.3

21.1

Features

Supports Communication with Serial External Devices

– Four Chip Selects with External Decoder Support Allow Communication with Up to 15

Peripherals

– Serial Memories, such as DataFlash and 3-wire EEPROMs

– Serial Peripherals, such as ADCs, DACs, CAN Controllers and Sensors

– External Co-processors

Master or Slave Serial Peripheral Bus Interface

– 8- to 16-bit Programmable Data Length Per Chip Select

– Programmable Phase and Polarity Per Chip Select

– Programmable Transfer Delays Between Consecutive Transfers and Between Clock and Data

Per Chip Select

– Programmable Delay Between Consecutive Transfers

– Selectable Mode Fault Detection

Connection to PDC Channel Capabilities Optimizes Data Transfers

– One Channel for the Receiver, One Channel for the Transmitter

– Next Buffer Support

21.2

Description

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.

The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master.

Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master

Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time.

A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS).

The SPI system consists of two data lines and two control lines:

• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s).

• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer.

• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.

• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

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21.3

Block Diagram

Figure 21-1. Block Diagram

PDC eral Bus

Power

Manager

MCK

DIV

MCK

(1)

32

SPI Interface

Interrupt Control

SPI Interrupt

PIO

SPCK

MISO

MOSI

NPCS0/NSS

NPCS1

NPCS2

NPCS3

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21.4

Application Block Diagram

Figure 21-2. Application Block Diagram: Single Master/Multiple Slave Implementation

SPI Master

SPCK

MISO

MOSI

NPCS0

NPCS1

NPCS2

NPCS3

NC

MISO

MOSI

NSS

SPCK

MISO

MOSI

NSS

SPCK

MISO

MOSI

NSS

SPCK

Slave 0

Slave 1

Slave 2

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21.5

Signal Description

Table 21-1.

Signal Description

Pin Name

MISO

MOSI

SPCK

NPCS1-NPCS3

NPCS0/NSS

Pin Description

Master In Slave Out

Master Out Slave In

Serial Clock

Peripheral Chip Selects

Peripheral Chip Select/Slave Select

Master

Input

Output

Output

Output

Output

Type

Slave

Output

Input

Input

Unused

Input

32015D–AVR32–10/07

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AT32AP7001

21.6

Product Dependencies

21.6.1

21.6.2

21.6.3

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.

The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. To use the local loopback function the SPI pins must be controlled by the SPI.

Power Management

The SPI clock is generated by the Power Manager. Before using the SPI, the programmer must ensure that the SPI clock is enabled in the Power Manager.

In the SPI description, Master Clock (MCK) is the clock of the peripheral bus to which the SPI is connected.

Interrupt

The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires programming the interrupt controller before configuring the SPI.

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21.7

Functional Description

21.7.1

21.7.2

Modes of Operation

The SPI operates in Master Mode or in Slave Mode.

Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register.

The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter.

If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a

Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes.

The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.

Data Transfer

Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave.

Table 21-2

shows the four modes and corresponding parameter settings.

Table 21-2.

SPI Bus Protocol Mode

SPI Mode

0

1

2

3

CPOL

0

0

1

1

NCPHA

1

0

1

0

Figure 21-3 and Figure 21-4

show examples of data transfers.

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Figure 21-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)

SPCK cycle (for reference)

1 2 3 4

SPCK

(CPOL = 0)

5

SPCK

(CPOL = 1)

MOSI

(from master)

MISO

(from slave)

MSB 6

MSB 6

5

5

4

4

3

3

2

7

2 1

NSS

(to slave)

* Not defined, but normally MSB of previous character received.

Figure 21-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)

1 2 3 4

SPCK cycle (for reference)

SPCK

(CPOL = 0)

5 6 7

8

1 LSB

LSB

8

*

SPCK

(CPOL = 1)

MOSI

(from master)

MISO

(from slave)

NSS

(to slave)

MSB 6

*

MSB 6

5

5

4

4

3

3

* Not defined but normally LSB of previous character transmitted.

2

2 1

1 LSB

LSB

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21.7.3

Master Mode Operations

When configured in Master Mode, the SPI uses the internal programmable baud rate generator as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK).

The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate.

After enabling the SPI, a data transfer begins when the processor writes to the TDR (Transmit

Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception.

Before writing the TDR, the PCS field must be set in order to select a slave.

If new data is written in TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to RDR, the data in TDR is loaded in the Shift Register and a new transfer starts.

The transfer of a data written in TDR in the Shift Register is indicated by the TDRE bit (Transmit

Data Register Empty) in the Status Register (SR). When new data is written in TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel.

The end of transfer is indicated by the TXEMPTY flag in the SR register. If a transfer delay (DLY-

BCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay.

The master clock (MCK) can be switched off at this time.

The transfer of received data from the Shift Register in RDR is indicated by the RDRF bit

(Receive Data Register Full) in the Status Register (SR). When the received data is read, the

RDRF bit is cleared.

If the RDR (Receive Data Register) has not been read before new data is received, the Overrun

Error bit (OVRES) in SR is set. When this bit is set the SPI will continue to update RDR when data is received, overwriting the previously received data. The user has to read the status register to clear the OVRES bit.

Figure 21-5 on page 292

shows a block diagram of the SPI when operating in Master Mode. Figure 21-6 on page 293 shows a flow chart describing how transfers are handled.

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21.7.3.1

Master Mode Block Diagram

Figure 21-5. Master Mode Block Diagram

FDIV

SPI_CSR0..3

SCBR

MCK

0

Baud Rate Generator

MCK/N

1

SPI

Clock

MISO

SPI_CSR0..3

BITS

NCPHA

CPOL

LSB

SPI_RDR

Shift Register

RD

MSB

RDRF

OVRES

SPI_MR

PCS

PS

0

SPI_TDR

TD

SPI_CSR0..3

CSAAT

TDRE

SPI_RDR

PCS

PCSDEC

Current

Peripheral

SPI_TDR

PCS

1

SPCK

MOSI

NPCS3

NPCS2

NPCS1

NPCS0

MSTR

MODF

NPCS0

MODFDIS

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21.7.3.2

Master Mode Flow Diagram

Figure 21-6. Master Mode Flow Diagram S

SPI Enable

- NPCS defines the current Chip Select

- CSAAT, DLYBS, DLYBCT refer to the fields of the

Chip Select Register corresponding to the Current Chip Select

- When NPCS is 0xF, CSAAT is 0.

1

TDRE ?

0

1

CSAAT ?

0

PS ?

1

Variable peripheral

NPCS = SPI_TDR(PCS)

0

Fixed

peripheral

NPCS = SPI_MR(PCS)

PS ?

1

Variable peripheral

0

Fixed

peripheral yes

SPI_TDR(PCS)

= NPCS ?

no

NPCS = 0xF

SPI_MR(PCS)

= NPCS ?

no

NPCS = 0xF

Delay DLYBCS

NPCS = SPI_TDR(PCS)

Delay DLYBCS

NPCS = SPI_MR(PCS),

SPI_TDR(PCS)

Delay DLYBS

Serializer = SPI_TDR(TD)

TDRE = 1

Data Transfer

SPI_RDR(RD) = Serializer

RDRF = 1

Delay DLYBCT

1

TDRE ?

1

CSAAT ?

0

NPCS = 0xF

Delay DLYBCS

0

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21.7.3.3

21.7.3.4

Clock Generation

The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock divided by 32, by a value between 1 and 255. The selection between Master Clock or Master

Clock divided by 32 is done by the FDIV value set in the Mode Register

This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255*32.

Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.

At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.

The divisor can be defined independently for each chip select, as it has to be programmed in the

SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.

Transfer Delays

Figure 21-7 shows a chip select transfer change and consecutive transfers on the same chip

select. Three delays can be programmed to modify the transfer waveforms:

• The delay between chip selects, programmable only once for all the chip selects by writing the

DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.

• The delay before SPCK, independently programmable for each chip select by writing the field

DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted.

• The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select

These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.

Figure 21-7. Programmable Delays

Chip Select 1

Chip Select 2

SPCK

DLYBCS DLYBS DLYBCT DLYBCT

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21.7.3.5

21.7.3.6

Peripheral Selection

The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.

The peripheral selection can be performed in two different ways:

• Fixed Peripheral Select: SPI exchanges data with only one peripheral

• Variable Peripheral Select: Data can be exchanged with more than one peripheral

Fixed Peripheral Select is activated by writing the PS bit to zero in MR (Mode Register). In this case, the current peripheral is defined by the PCS field in MR and the PCS field in TDR have no effect.

Variable Peripheral Select is activated by setting PS bit to one. The PCS field in TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data.

The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed.

The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the

SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor.

Peripheral Chip Select Decoding

The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip

Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCS-

DEC bit at 1 in the Mode Register (MR).

When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low.

When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS).

As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded.

The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the

PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.

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21.7.3.7

Peripheral Deselection

When operating normally, as soon as the transfer of the last data written in TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers.

To facilitate interfacing with such devices, the Chip Select Register can be programmed with the

CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required.

Figure 21-8

shows different peripheral deselection cases and the effect of the CSAAT bit.

Figure 21-8. Peripheral Deselection

CSAAT = 0 CSAAT = 1

TDRE

NPCS[0..3] A

DLYBCT

A

DLYBCT

DLYBCS

PCS = A

A A

DLYBCS

PCS = A

A

Write SPI_TDR

TDRE

NPCS[0..3] A

DLYBCT

DLYBCS

PCS=A

A

Write SPI_TDR

TDRE

NPCS[0..3]

A

DLYBCT

DLYBCS

PCS = B

Write SPI_TDR

B

A

DLYBCT

A

DLYBCS

PCS = A

A

A

DLYBCT

PCS = B

DLYBCS

B

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21.7.3.8

21.7.4

Mode Fault Detection

A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open-drain through the PIO controller, so that external pull up resistors are needed to guarantee high level.

When a mode fault is detected, the MODF bit in the SR is set until the SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the CR (Control Register) at 1.

By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (MR).

SPI Slave Mode

When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).

The SPI waits for NSS to go active before receiving the serial clock from an external master.

When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode.

The bits are shifted out on the MISO line and sampled on the MOSI line.

When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If RDRF is already high when the data is transferred, the Overrun bit rises and the data transfer to RDR is aborted.

When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0.

When a first data is written in TDR, it is transferred immediately in the Shift Register and the

TDRE bit rises. If new data is written, it remains in TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers.

Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in TDR since the last load from TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted.

Figure 21-9

shows a block diagram of the SPI when operating in Slave Mode.

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Figure 21-9. Slave Mode Functional Block Diagram

SPCK

NSS

SPI

Clock

MOSI

SPIEN

SPIENS

SPIDIS

SPI_CSR0

BITS

NCPHA

CPOL

LSB

SPI_RDR

Shift Register

RD

MSB

RDRF

OVRES

FLOAD

SPI_TDR

TD

TDRE

MISO

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AT32AP7001

21.8

Serial Peripheral Interface (SPI) User Interface

Table 21-3.

SPI Register Mapping

Offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

Control Register

Mode Register

Receive Data Register

Transmit Data Register

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

0x20 - 0x2C

0x30

0x34

0x38

Reserved

Chip Select Register 0

Chip Select Register 1

Chip Select Register 2

0x3C Chip Select Register 3

0x004C - 0x00F8 Reserved

0x00FC

0x100 - 0x124

Version Register

Reserved for the PDC

CSR0

CSR1

CSR2

CSR3

VERSION

CR

MR

RDR

TDR

SR

IER

IDR

IMR

Note: 1. Values in the Version Register vary with the version of the IP block implementation.

Write-only

Read/Write

Read-only

Write-only

Read-only

Write-only

Write-only

Read-only

Read/Write

Read/Write

Read/Write

Read/Write

Read-only

Reset

---

0x0

0x0

---

0x000000F0

---

---

0x0

0x0

0x0

0x0

0x0

0x-

(1)

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21.8.1

31

23

SPI Control Register

Name: CR

Access Type: Write-only

15

7

SWRST

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

10

2

26

18

25

17

9

1

SPIDIS

24

LASTXFER

16

8

0

SPIEN

SPIEN: SPI Enable

0 = No effect.

1 = Enables the SPI to transfer and receive data.

SPIDIS: SPI Disable

0 = No effect.

1 = Disables the SPI.

As soon as SPDIS is set, SPI finishes its transfer.

All pins are set in input mode and no data is received or transmitted.

If a transfer is in progress, the transfer is finished before the SPI is disabled.

If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.

SWRST: SPI Software Reset

0 = No effect.

1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.

The SPI is in slave mode after a software reset.

PDC channels are not affected by software reset.

LASTXFER: Last Transfer

0 = No effect.

1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

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21.8.2

SPI Mode Register

Name: MR

Access Type: Read/Write

31 30 29 28 27

DLYBCS

23

22

21

20

19

15

7

LLB

14

6

13

5

12

4

MODFDIS

11

3

FDIV

26

18

PCS

25

17

24

16

10

2

PCSDEC

9

1

PS

8

0

MSTR

MSTR: Master/Slave Mode

0 = SPI is in Slave mode.

1 = SPI is in Master mode.

PS: Peripheral Select

0 = Fixed Peripheral Select.

1 = Variable Peripheral Select.

PCSDEC: Chip Select Decode

0 = The chip selects are directly connected to a peripheral device.

1 = The four chip select lines are connected to a 4- to 16-bit decoder.

When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:

CSR0 defines peripheral chip select signals 0 to 3.

CSR1 defines peripheral chip select signals 4 to 7.

CSR2 defines peripheral chip select signals 8 to 11.

CSR3 defines peripheral chip select signals 12 to 14.

FDIV: Clock Selection

0 = The SPI operates at MCK.

1 = The SPI operates at MCK/N.

MODFDIS: Mode Fault Detection

0 = Mode fault detection is enabled.

1 = Mode fault detection is disabled.

LLB: Local Loopback Enable

0 = Local loopback path disabled.

1 = Local loopback path enabled.

LLB controls the local loopback on the data serializer for testing in Master Mode only. MISO is internally connected to

MOSI.

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PCS: Peripheral Chip Select

This field is only used if Fixed Peripheral Select is active (PS = 0).

If PCSDEC = 0:

PCS = xxx0

PCS = xx01

PCS = x011

PCS = 0111

NPCS[3:0] = 1110

NPCS[3:0] = 1101

NPCS[3:0] = 1011

NPCS[3:0] = 0111 forbidden (no peripheral is selected) PCS = 1111

(x = don’t care)

If PCSDEC = 1:

NPCS[3:0] output signals = PCS.

DLYBCS: Delay Between Chip Selects

This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times.

If DLYBCS is less than or equal to six, six MCK periods (or 6*N MCK periods if FDIV is set) will be inserted by default.

Otherwise, the following equation determines the delay:

If FDIV is 0:

Delay Between Chip Selects

=

MCK

If FDIV is 1:

Delay Between Chip Selects

=

DLYBCS

×

N

---------------------------------

MCK

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21.8.3

SPI Receive Data Register

Name: RDR

Access Type: Read-only

31

23

30

22

29

21

28

20

27

19

15 14 13 12 11

RD

7 6 5 4 3

RD

26

18

10

2

PCS

25

17

9

1

24

16

8

0

RD: Receive Data

Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.

PCS: Peripheral Chip Select

In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.

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21.8.4

SPI Transmit Data Register

Name: TDR

Access Type: Write-only

31

23

30

22

29

21

28

20

27

19

15 14 13 12 11

TD

7 6 5 4 3

TD

26

18

10

2

PCS

25

17

9

1

24

LASTXFER

16

8

0

TD: Transmit Data

Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.

PCS: Peripheral Chip Select

This field is only used if Variable Peripheral Select is active (PS = 1).

If PCSDEC = 0:

PCS = xxx0

PCS = xx01

PCS = x011

NPCS[3:0] = 1110

NPCS[3:0] = 1101

NPCS[3:0] = 1011

PCS = 0111

PCS = 1111

(x = don’t care)

If PCSDEC = 1:

NPCS[3:0] = 0111 forbidden (no peripheral is selected)

NPCS[3:0] output signals = PCS

LASTXFER: Last Transfer

0 = No effect.

1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.

This field is only used if Variable Peripheral Select is active (PS = 1).

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21.8.5

31

23

SPI Status Register

Name: SR

Access Type: Read-only

15

7

TXBUFE

30

22

14

6

RXBUFF

29

21

13

5

ENDTX

28

20

12

4

ENDRX

27

19

11

3

OVRES

26

18

10

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

SPIENS

8

NSSR

0

RDRF

RDRF: Receive Data Register Full

0 = No data has been received since the last read of RDR

1 = Data has been received and the received data has been transferred from the serializer to RDR since the last read of

RDR.

• TDRE: Transmit Data Register Empty

0 = Data has been written to TDR and not yet transferred to the serializer.

1 = The last data written in the Transmit Data Register has been transferred to the serializer.

TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.

• MODF: Mode Fault Error

0 = No Mode Fault has been detected since the last read of SR.

1 = A Mode Fault occurred since the last read of the SR.

• OVRES: Overrun Error Status

0 = No overrun has been detected since the last read of SR.

1 = An overrun has occurred since the last read of SR.

An overrun occurs when RDR is loaded at least twice from the serializer since the last read of the RDR.

ENDRX: End of RX buffer

0 = The Receive Counter Register has not reached 0 since the last write in RCR or RNCR.

1 = The Receive Counter Register has reached 0 since the last write in RCR or RNCR.

ENDTX: End of TX buffer

0 = The Transmit Counter Register has not reached 0 since the last write in TCR or TNCR.

1 = The Transmit Counter Register has reached 0 since the last write in TCR or TNCR.

RXBUFF: RX Buffer Full

0 = RCR or RNCR has a value other than 0.

1 = Both RCR and RNCR has a value of 0.

TXBUFE: TX Buffer Empty

0 = TCR or TNCR has a value other than 0.

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1 = Both TCR and TNCR has a value of 0.

NSSR: NSS Rising

0 = No rising edge detected on NSS pin since last read.

1 = A rising edge occurred on NSS pin since last read.

• TXEMPTY: Transmission Registers Empty

0 = As soon as data is written in TDR.

1 = TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

• SPIENS: SPI Enable Status

0 = SPI is disabled.

1 = SPI is enabled.

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21.8.6

SPI Interrupt Enable Register

Name: IER

Access Type: Write-only

31

23

30

22

29

21

15

7

TXBUFE

14

6

RXBUFF

13

5

ENDTX

28

20

12

4

ENDRX

• RDRF: Receive Data Register Full Interrupt Enable

• TDRE: SPI Transmit Data Register Empty Interrupt Enable

• MODF: Mode Fault Error Interrupt Enable

• OVRES: Overrun Error Interrupt Enable

ENDRX: End of Receive Buffer Interrupt Enable

ENDTX: End of Transmit Buffer Interrupt Enable

RXBUFF: Receive Buffer Full Interrupt Enable

TXBUFE: Transmit Buffer Empty Interrupt Enable

TXEMPTY: Transmission Registers Empty Enable

NSSR: NSS Rising Interrupt Enable

0 = No effect.

1 = Enables the corresponding interrupt.

27

19

11

3

OVRES

26

18

10

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

8

NSSR

0

RDRF

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21.8.7

SPI Interrupt Disable Register

Name: IDR

Access Type: Write-only

31

23

30

22

29

21

15

7

TXBUFE

14

6

RXBUFF

13

5

ENDTX

28

20

12

4

ENDRX

• RDRF: Receive Data Register Full Interrupt Disable

• TDRE: SPI Transmit Data Register Empty Interrupt Disable

• MODF: Mode Fault Error Interrupt Disable

• OVRES: Overrun Error Interrupt Disable

ENDRX: End of Receive Buffer Interrupt Disable

ENDTX: End of Transmit Buffer Interrupt Disable

RXBUFF: Receive Buffer Full Interrupt Disable

TXBUFE: Transmit Buffer Empty Interrupt Disable

TXEMPTY: Transmission Registers Empty Disable

NSSR: NSS Rising Interrupt Disable

0 = No effect.

1 = Disables the corresponding interrupt.

27

19

11

3

OVRES

26

18

10

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

8

NSSR

0

RDRF

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21.8.8

SPI Interrupt Mask Register

Name: IMR

Access Type: Read-only

31

23

30

22

29

21

28

20

15

7

TXBUFE

14

6

RXBUFF

13

5

ENDTX

12

4

ENDRX

• RDRF: Receive Data Register Full Interrupt Mask

• TDRE: SPI Transmit Data Register Empty Interrupt Mask

• MODF: Mode Fault Error Interrupt Mask

• OVRES: Overrun Error Interrupt Mask

ENDRX: End of Receive Buffer Interrupt Mask

ENDTX: End of Transmit Buffer Interrupt Mask

RXBUFF: Receive Buffer Full Interrupt Mask

TXBUFE: Transmit Buffer Empty Interrupt Mask

TXEMPTY: Transmission Registers Empty Mask

NSSR: NSS Rising Interrupt Mask

27

19

11

3

OVRES

0 = The corresponding interrupt is not enabled.

1 = The corresponding interrupt is enabled.

26

18

10

2

MODF

25

17

9

TXEMPTY

1

TDRE

24

16

8

NSSR

0

RDRF

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21.8.9

SPI Chip Select Register

Access Type: Read/Write

31 30 29 28 27 26 25 24

DLYBCT

23 22 21 20 19 18 17 16

DLYBS

15 14 13 12 11 10 9 8

SCBR

7 6

BITS

5 4 3

CSAAT

2

1

NCPHA

0

CPOL

• CPOL: Clock Polarity

0 = The inactive state value of SPCK is logic level zero.

1 = The inactive state value of SPCK is logic level one.

CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.

• NCPHA: Clock Phase

0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.

1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.

• CSAAT: Chip Select Active After Transfer

0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.

1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select.

• BITS: Bits Per Transfer

The BITS field determines the number of data bits transferred. Reserved values should not be used, see

Table 21-4 on page 311 .

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.

Table 21-4.

BITS, Bits Per Transfer

BITS

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

Bits Per Transfer

8

9

10

11

12

13

14

15

16

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

• SCBR: Serial Clock Baud Rate

In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The

Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:

If FDIV is 0:

SPCK Baudrate =

SCBR

If FDIV is 1:

SPCK Baudrate = ------------------------------

N

MCK

×

SCBR

)

Note: N = 32

Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.

At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.

• DLYBS: Delay Before SPCK

This field defines the delay from NPCS valid to the first valid SPCK transition.

When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.

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Otherwise, the following equations determine the delay:

If FDIV is 0:

Delay Before SPCK =

MCK

If FDIV is 1:

Delay Before SPCK =

N

×

DLYBS

MCK

Note: N = 32

• DLYBCT: Delay Between Consecutive Transfers

This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.

The delay is always inserted after each transfer and before removing the chip select if needed.

When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.

Otherwise, the following equation determines the delay:

If FDIV is 0:

Delay Between Consecutive Transfers =

32

×

DLYBCT

MCK

+

2

MCK

If FDIV is 1:

Delay Between Consecutive Transfers =

32

×

N

×

MCK

Note: N = 32

+

N

×

SCBR

2

MCK

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22. Two-wire Interface (TWI)

Rev: 1.8.0.1

22.1

Features

Compatible with Philips’ I

2

C protocol

One, Two or Three Bytes for Slave Address

Sequential Read/Write Operations

22.2

Description

The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel two-wire bus Serial EEPROM. The TWI is programmable as a master with sequential or single-byte access. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.

22.3

Block Diagram

Figure 22-1. Block Diagram

Peripheral Bus

Bridge

PIO

TWCK

TWD

Power

Manager

MCK

Two-wire

Interface

TWI

Interrupt

Interrupt

Controller

22.4

Application Block Diagram

Figure 22-2. Application Block Diagram

R R

VDD

Host with

TWI

Interface

TWD

TWCK

AT24LC16

U1

Slave 1

AT24LC16

U2

Slave 2

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22.4.1

I/O Lines Description

Table 22-1.

I/O Lines Description

Pin Name Pin Description

TWD

TWCK

Two-wire Serial Data

Two-wire Serial Clock

Type

Input/Output

Input/Output

22.5

Product Dependencies

22.5.1

I/O Lines

Both TWD and TWCK are bi-directional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 1-2 on page 1 ). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function.

TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must program the PIO controller to dedicate TWD and TWCK as peripheral lines.

22.5.2

22.5.3

Power Management

The TWI clock is generated by the power manager. Before using the TWI, the programmer must ensure that the TWI clock is enabled in the power manager.

In the TWI description, Master Clock (MCK) is the clock of the peripheral bus to which the TWI is connected.

Interrupt

The TWI interface has an interrupt line connected to the interrupt controller. In order to handle interrupts, the interrupt controller must be programmed before configuring the TWI.

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22.6

Functional Description

22.6.1

Transfer format

The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must

be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure

22-4 on page 315

).

Each transfer begins with a START condition and terminates with a STOP condition (see

Figure

22-3 on page 315

).

• A high-to-low transition on the TWD line while TWCK is high defines the START condition.

• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.

Figure 22-3. START and STOP Conditions

TWD

TWCK

Start Stop

Figure 22-4. Transfer Format

TWD

TWCK

22.6.2

22.6.3

Start Address R/W Ack Data Ack Data Ack Stop

Modes of Operation

The TWI has two modes of operation:

• Master transmitter mode

• Master receiver mode

The TWI Control Register (CR) allows configuration of the interface in Master Mode. In this mode, it generates the clock according to the value programmed in the Clock Waveform Generator Register (CWGR). This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks.

Transmitting Data

After the master initiates a Start condition, it sends a 7-bit slave address, configured in the Master Mode register (DADR in MMR), to notify the slave device. The bit following the slave address indicates the transfer direction (write or read). If this bit is 0, it indicates a write operation (transmit operation). If the bit is 1, it indicates a request for data read (receive operation).

The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the

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other status bits, an interrupt can be generated if enabled in the interrupt enable register (IER).

After writing in the transmit-holding register (THR), setting the START bit in the control register starts the transmission. The data is shifted in the internal shifter and when an acknowledge is detected, the TXRDY bit is set until a new write in the THR (see

Figure 22-6 below). The master

generates a stop condition to end the transfer.

The read sequence begins by setting the START bit. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (RHR). The RXRDY bit is reset when reading the RHR.

The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address).

The three internal address bytes are configurable through the Master Mode register (MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (IADR).

Figure 22-5. Master Write with One, Two or Three Bytes Internal Address and One Data Byte

Three bytes internal address

TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA

TWD

Two bytes internal address

S DADR W

TWD

One byte internal address

S DADR W

A

A

IADR(15:8)

IADR(7:0)

A

A

IADR(7:0)

DATA

A

A P

DATA A

P

A P

Figure 22-6. Master Write with One Byte Internal Address and Multiple Data Bytes

TWD

S DADR W

A IADR(7:0) A

DATA A

DATA

TXCOMP

Write THR

TXRDY

Write THR

Write THR

A

Write THR

DATA A

P

Figure 22-7. Master Read with One, Two or Three Bytes Internal Address and One Data Byte

TWD

Three bytes internal address

S DADR

W

A IADR(23:16) A

IADR(15:8)

A

IADR(7:0) A S DADR

DATA

TWD

Two bytes internal address

S DADR W

TWD

One byte internal address

S DADR W

A

A

IADR(15:8)

IADR(7:0)

A

A

IADR(7:0) A

S DADR R

S

A

DADR

DATA

R A

N P

DATA

R A

N P

N P

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Figure 22-8. Master Read with One Byte Internal Address and Multiple Data Bytes

TWD

S DADR W

A IADR(7:0) A S DADR R A DATA A

DATA

TXCOMP

Write START Bit

Write STOP Bit

N P

RXRDY

Read RHR Read RHR

• S = Start

• P = Stop

• W = Write

• R = Read

• A = Acknowledge

• N = Not Acknowledge

• DADR= Device Address

• IADR = Internal Address

Figure 22-9 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the

use of internal addresses to access the device.

Figure 22-9. Internal Address Usage

S

T

A

R

T

Device

Address

0

W

R

I

T

E

FIRST

WORD ADDRESS

SECOND

WORD ADDRESS

M

S

B

L

S

B

R

/

W

A

C

K

M

S

B

A

C

K

L

S

B

A

C

K

DATA

A

C

K

S

T

O

P

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AT32AP7001

22.6.4

Read/Write Flowcharts

The following flowcharts shown in Figure 22-10 on page 318

and in Figure 22-11 on page 319

give examples for read and write operations in Master Mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register

(IER) be configured first.

Figure 22-10. TWI Write in Master Mode

START

Set TWI clock:

CWGR = clock

Set the control register:

- Master enable

CR = MSEN

Set the Master Mode register:

- Device slave address

- Internal address size

- Transfer direction bit

Write ==> bit MREAD = 0

Internal address size = 0?

Yes

Load transmit register

THR = Data to send

Set theinternal address

IADR = address

Read status register

THR = data to send

TXRDY = 0?

Yes

Data to send?

Yes

Read status register

TXCOMP = 0?

END

Yes

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Figure 22-11. TWI Read in Master Mode

START

Set TWI clock:

CWGR = clock

Set the control register:

- Master enable

CR = MSEN

Set the Master Mode register:

- Device slave address

- Internal address size

- Transfer direction bit

Read ==> bit MREAD = 0

Internal address size = 0?

Yes

Start the transfer

CR = START

Read status register

RXRDY = 0?

Read RHR

Yes

Data to read?

Stop the transfer

CR = STOP

Read status register

TXCOMP = 0?

END

Yes

Yes

Set the internal address

IADR = address

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AT32AP7001

22.7

TWI User Interface

22.7.1

Register Mapping

Table 22-2.

Two-wire Interface (TWI) User Interface

Offset Register

0x0000

0x0004

0x0008

0x000C

0x0010

0x0020

0x0024

0x0028

0x002C

0x0030

0x0034

Control Register

Master Mode Register

Reserved

Internal Address Register

Clock Waveform Generator Register

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Receive Holding Register

Transmit Holding Register

Name

CR

MMR

-

IADR

CWGR

SR

IER

IDR

IMR

RHR

THR

Access

Write-only

Read/Write

-

Read/Write

Read/Write

Read-only

Write-only

Write-only

Read-only

Read-only

Read/Write

Reset Value

N/A

0x0000

-

0x0000

0x0000

0x0008

N/A

N/A

0x0000

0x0000

0x0000

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22.7.2

TWI Control Register

Register Name:

Access Type:

31

23

15

7

SWRST

30

22

14

6

13

5

29

21

CR

Write-only

28

20

12

4

27

19

11

3

MSDIS

26

18

10

2

MSEN

25

17

9

1

STOP

24

16

8

0

START

• START: Send a START Condition

0 = No effect.

1 = A frame beginning with a START bit is transmitted according to the settings in the mode register.

This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register.

• STOP: Send a STOP Condition

0 = No effect.

1 = STOP Condition is sent just after completing the current byte transmission in master read or write mode.

In single data byte master read or write, the START and STOP must both be set.

In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission.

In master read mode, if a NACK bit is received, the STOP is automatically performed.

In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent.

• MSEN: TWI Master Transfer Enabled

0 = No effect.

1 = If MSDIS = 0, the master data transfer is enabled.

• MSDIS: TWI Master Transfer Disabled

0 = No effect.

1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if they contain data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.

• SWRST: Software Reset

0 = No effect.

1 = Equivalent to a system reset.

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22.7.3

TWI Master Mode Register

Register Name:

Address Type:

31

30

29

22 21 23

15

7

14

6

13

5

• IADRSZ: Internal Device Address Size

MMR

Read/Write

28

20

12

MREAD

4

27

19

DADR

11

3

10

2

26

18

1

1

0

0

IADRSZ[9:8]

0

1

0

1

No internal device address (Byte command protocol)

One-byte internal device address

Two-byte internal device address

Three-byte internal device address

• MREAD: Master Read Direction

0 = Master write direction.

1 = Master read direction.

• DADR: Device Address

The device address is used in Master Mode to access slave devices in read or write mode.

25

17

1

9

IADRSZ

8

0

24

16

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22.7.4

TWI Internal Address Register

Register Name:

Access Type:

31

23

15

7

30

22

14

6

29

21

13

5

IADR

Read/Write

28

20

IADR

12

IADR

4

IADR

• IADR: Internal Address

0, 1, 2 or 3 bytes depending on IADRSZ.

– Low significant byte address in 10-bit mode addresses.

27

19

11

3

10

2

26

18

9

1

25

17

8

0

24

16

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22.7.5

TWI Clock Waveform Generator Register

Register Name:

Access Type:

CWGR

Read/Write

31

30

29

28

23

15

22

14

21

13

20

12

CHDIV

7 6 5 4

CLDIV

27

19

11

3

• CLDIV: Clock Low Divider

The SCL low period is defined as follows:

T low

=

( (

CLDIV

×

2

CKDIV

)

+ 3

) ×

T

MCK

• CHDIV: Clock High Divider

The SCL high period is defined as follows:

T high

=

( (

CHDIV

×

2

CKDIV

)

+

3

) ×

T

MCK

• CKDIV: Clock Divider

The CKDIV is used to increase both SCL high and low periods.

10

2

26

18

25

17

CKDIV

9

1

8

0

24

16

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22.7.6

TWI Status Register

Register Name:

Access Type:

31

23

15

7

30

22

14

6

13

5

29

21

SR

Read-only

28

20

12

4

11

3

27

19

26

18

10

2

TXRDY

25

17

9

1

RXRDY

24

16

8

NACK

0

TXCOMP

• TXCOMP: Transmission Completed

0 = In master, during the length of the current frame. In slave, from START received to STOP received.

1 = When both holding and shift registers are empty and STOP condition has been sent (in Master), or when MSEN is set

(enable TWI).

• RXRDY: Receive Holding Register Ready

0 = No character has been received since the last RHR read operation.

1 = A byte has been received in theRHR since the last read.

• TXRDY: Transmit Holding Register Ready

0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into THR register.

1 = As soon as data byte is transferred from THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).

• NACK: Not Acknowledged

0 = Each data byte has been correctly received by the far-end side TWI slave component.

1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.

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22.7.7

TWI Interrupt Enable Register

Register Name:

Access Type:

31

30

29

23

15

7

22

14

6

21

13

5

• TXCOMP: Transmission Completed

• RXRDY: Receive Holding Register Ready

• TXRDY: Transmit Holding Register Ready

• NACK: Not Acknowledge

0 = No effect.

1 = Enables the corresponding interrupt.

IER

Write-only

28

20

12

4

11

3

27

19

26

18

10

2

TXRDY

25

17

9

1

RXRDY

24

16

8

NACK

0

TXCOMP

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AT32AP7001

22.7.8

TWI Interrupt Disable Register

Register Name:

Access Type:

31

30

29

23

15

7

22

14

6

21

13

5

• TXCOMP: Transmission Completed

• RXRDY: Receive Holding Register Ready

• TXRDY: Transmit Holding Register Ready

• NACK: Not Acknowledge

0 = No effect.

1 = Disables the corresponding interrupt.

IDR

Write-only

28

20

12

4

11

3

27

19

26

18

10

2

TXRDY

25

17

9

1

RXRDY

24

16

8

NACK

0

TXCOMP

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AT32AP7001

22.7.9

TWI Interrupt Mask Register

Register Name:

Access Type:

31

30

29

23

15

7

22

14

6

21

13

5

• TXCOMP: Transmission Completed

• RXRDY: Receive Holding Register Ready

• TXRDY: Transmit Holding Register Ready

• NACK: Not Acknowledge

0 = The corresponding interrupt is disabled.

1 = The corresponding interrupt is enabled.

IMR

Read-only

28

20

12

4

11

3

27

19

26

18

10

2

TXRDY

25

17

9

1

RXRDY

24

16

8

NACK

0

TXCOMP

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AT32AP7001

22.7.10

TWI Receive Holding Register

Register Name:

Access Type:

31

23

15

7

30

22

14

6

29

21

13

5

RHR

Read-only

28

20

12

4

RXDATA

11

3

27

19

• RXDATA: Master or Slave Receive Holding Data

10

2

26

18

9

1

25

17

8

0

24

16

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329

AT32AP7001

22.7.11

TWI Transmit Holding Register

Register Name:

Access Type:

31

30

29

23

15

7

22

14

6

21

13

5

THR

Read/Write

28

20

12

4

TXDATA

11

3

27

19

• TXDATA: Master or Slave Transmit Holding Data

10

2

26

18

9

1

25

17

8

0

24

16

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23. PS/2 Module (PSIF)

Rev: 1.0.0.0

23.1

Features

PS/2 Host

Receive and transmit capability

Parity generation and error detection

Overrun error detection

23.2

Description

The PS/2 module provides host functionality allowing the MCU to interface PS/2 devices such as keyboard and mice. The module is capable of both host-to-device and device-to-host communication.

23.3

Product Dependencies

23.3.1

23.3.2

23.3.3

I/O Lines

The PS/2 may be multiplexed with PIO lines. The programmer must first program the PIO controller to give control of the pins to the PS/2 module.

Power Management

The clock for the PS/2 module is generated by the power manager. The programmer must ensure that the PS/2 clock is enabled in the power manager before using the PS/2 module.

Interrupt

The PS/2 module has an interrupt line connected to the interrupt controller. Handling the PS/2 interrupt requires programming the interrupt controller before configuring the PS/2 module.

23.4

The PS/2 Protocol

The PS/2 protocol is a bidirectional synchronous serial communication protocol. It connects a single master - referred to as the ‘host’ - to a single slave - referred to as the ‘device’. Communication is done through two lines called ‘data’ and ‘clock’. Both of these must be open-drain or open-collector with a pullup resistor to perform a wired-AND function. When the bus is idle, both lines are high.

The device always generates the clock signal, but the host may pull the clock low to inhibit transfers. The clock frequency is in the range 10-16.7 kHz. Both the host and the slave may initiate a transfer, but the host has ultimate control of the bus.

Data are transmitted one byte at a time in a frame consisting of 11-12 bits. The transfer format is described in detail below.

23.4.1

Device to host communication

The device can only initiate a transfer when the bus is idle. If the host at any time pulls the clock low, the device must stop transferring data and prepare to receive data from the host.

The device transmits data using a 11-bit frame. The device writes a bit on the data line when the clock is high, and the host reads the bit when the clock is low.

The format of the frame is:

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• 1 start bit - always 0.

• 8 data bits, least significant bit first.

• 1 parity bit - odd parity.

• 1 stop bit - always 1.

Figure 23-1. Device to host transfer

CLOCK

DATA

23.4.2

Host to device communication

Because the device always generates the clock, host to device communication is done differently than device to host communication.

• The host starts by inhibiting communication by pulling clock low for a minimum of 100 microseconds.

• Then applies a “request-to-send” by releasing clock and pulling data low.

The device must check for this state at least every 10 milliseconds. Once it detects a request-tosend, it must start generating the clock and receive one frame of data. The host writes a data bit when the clock is low, and the device reads the bit when the clock is high.

The format of the frame is:

• 1 start bit - always 0.

• 8 data bits - least significant bit first.

• 1 parity bit - odd parity

• 1 stop bit - always one.

• 1 acknowledge bit - the device acknowledges by pulling data low.

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Figure 23-2. Host to device transfer

CLOCK

DATA

Host Clock

Host Data

Device Clock

Device Data

23.5

Functional Description

23.5.1

Prescaler

For all data transfers on the PS/2 bus, the device is responsible for generating the clock and thus controlling the timing of the communications. When a host wants to initiate a transfer however, it needs to pull the clock line low for a given time (minimum 100µs). A clock prescaler controls the timing of the transfer request pulse.

Before initiating host to device transfers, the programmer must write PSR (Prescale Register).

This value determines the length of the “transfer request” pulse and is found by:

PRSCV = Pulse length * PS/2 module frequency

23.5.2

23.5.3

According to the PS/2 specifications, the pulse length should be at least 100µs. The PS/2 module frequency is the frequency of the peripheral bus to which the module is connected.

Receiving data

The receiver is enabled by writing the RXEN bit in CR (Control Register) to ‘1’. When enabled, the receiver will continuously receive data transmitted by the device. The data is stored in RHR

(Receive Holding Register). When a byte has been received, the RXRDY bit in SR (Status Register) is set.

For each received byte, the parity is calculated. If it doesn’t match the parity bit received from the device, the PARITY bit in SR is set. The received byte should then be discarded.

If a received byte in RHR is not read before a new byte has been received, the overrun bit -

OVRUN in SR is set. The new data is stored in RHR overwriting the previously received byte.

Transmitting data

The transmitter is enabled by writing the TXEN bit in CR to ‘1’. When enabled, a data transfer to the device will be started by writing the transmit data to THR (Transmit Holding Register). Any ongoing transfer from the device will be aborted.

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0x01C

0x020

0x100

0x104

0x108

0x10C

0x110

0x114

Offset

0x000

0x004

0x008

0x00C

0x010

0x014

0x018

0x118

0x11C

0x120

When the data written to THR has been transmitted to the device, the TXRDY bit in SR will be set and a new value can be loaded into THR.

At the end of the transfer, the device should acknowledge the transfer by pulling the data line low for one cycle. If an acknowledge is not detected, the NACK bit in SR will be set.

If the device fails to acknowledge the frame, the NACK bit in SR will be set. The software is responsible for any retries.

All transfers from host to device are started by the host pulling the clock line low for at least

100µs. The programmer must ensure that the prescaler is programmed to generate correct pulse length.

23.5.4

Interrupts

23.6

User Interface

The PS/2 module can be configured to signal an interrupt when one of the bits in SR is set. The interrupt is enabled by writing to IER (Interrupt Enable Register) and disabled by writing to IDR

(Interrupt Disable Register). The current setting of an interrupt line can be seen by reading IMR

(Interrupt Mask Register).

Register

PS/2 Control Register 0

PS/2 Receive Holding Register 0

PS/2 Transmit Holding Register 0

RESERVED

PS/2 Status Register 0

PS/2 Interrupt Enable Register 0

PS/2 Interrupt Disable Register 0

PS/2 Interrupt Mask Register 0

PS/2 Prescale Register 0

PS/2 Control Register 1

PS/2 Receive Holding Register 1

PS/2 Transmit Holding Register 1

RESERVED

PS/2 Status Register 1

PS/2 Interrupt Enable Register 1

PS/2 Interrupt Disable Register 1

PS/2 Interrupt Mask Register 1

PS/2 Prescale Register 1

Register Name

CR0

RHR0

THR0

-

SR0

IER0

IDR0

IMR0

PSR0

CR1

RHR1

THR1

-

SR1

IER1

IDR1

IMR1

PSR1

Access

Write-only

Read-only

Write-only

-

Read-only

Write-only

Write-only

Read-only

Write-only

Write-only

Read-only

Write-only

-

Read-only

Write-only

Write-only

Read-only

Write-only

-

-

0x0

-

0x0

0x0

-

0x0

Reset

-

0x0

-

-

0x0

-

-

-

0x0

0x0

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23.6.1

Name:

PS/2 Control Register

Access Type:

CR0, CR1

Write-only

31

-

23

-

15

SWRST

30

-

22

-

14

-

29

-

21

-

13

-

28

-

20

-

12

-

27

-

19

-

11

-

26

-

18

-

10

-

25

-

17

-

9

TXDIS

24

-

16

-

8

TXEN

7

-

6

-

5

-

4

-

3

-

2

-

1

RXDIS

0

RXEN

SWRST: Software Reset

Writing this strobe causes a reset of the PS/2 interface module. Data shift registers are cleared and configuration registers are reset to default values.

TXDIS: Transmitter Disable

0: No effect.

1: Disables the transmitter.

TXEN: Transmitter Enable

0: No effect.

1: Enables the transmitter if TXDIS=0.

RXDIS: Receiver Disable

0: No effect.

1: Disables the receiver.

RXEN: Receiver Enable

0: No effect.

1: Enables the receiver if RXDIS=0.

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23.6.2

Name:

PS/2 Receive Holding Register

Access Type:

RHR0, RHR1

Read-only

15

-

7

31

-

23

-

14

-

6

30

-

22

-

RXDATA: Receive Data

Data received from the device.

13

-

5

29

-

21

-

12

-

4

28

-

20

-

RXDATA

11

-

3

27

-

19

-

10

-

2

26

-

18

-

9

-

1

25

-

17

-

8

-

0

24

-

16

-

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23.6.3

Name:

PS/2 Transmit Holding Register

Access Type:

THR0, THR1

Write-only

15

-

7

31

-

23

-

14

-

6

30

-

22

-

TXDATA: Transmit Data

• Data to be transmitted to the device.

13

-

5

29

-

21

-

12

-

4

28

-

20

-

TXDATA

11

-

3

27

-

19

-

10

-

2

26

-

18

-

9

-

1

25

-

17

-

8

-

0

24

-

16

-

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23.6.4

Name:

PS/2 Status Register

Access Type:

SR0, SR1

Read-only

31 30 29 28 27 26 25

-

23

-

15

-

-

22

-

14

-

-

21

-

13

-

-

20

-

12

-

-

19

-

11

-

-

18

-

10

-

-

17

-

9

PARITY

7

-

6

-

5

OVRUN

4

RXRDY

3

-

2

-

PARITY:

0: No parity errors detected on incoming data since last read of SR.

1: At least one parity error detected on incoming data since last read of SR.

NACK: Not Acknowledge

0: All transmissions has been properly acknowledged by the device since last read of SR.

1: At least one transmission was not properly acknowledged by the device since last read of SR.

OVRUN: Overrun

0: No receive overrun has occured since the last read of SR.

1: At least one receive overrun condition has occured since the last read of SR.

RXRDY: Receiver Ready

0: RHR is empty.

1: RHR contains valid data received from the device.

TXEMPTY: Transmitter Empty

0: Data remains in THR or is currently being transmitted from the shift register.

1: Both THR and the shift register are empty.

TXRDY: Transmitter Ready

0: Data has been loaded in THR and is waiting to be loaded into the shift register.

1: THR is empty.

1

TXEMPTY

24

-

16

-

8

NACK

0

TXRDY

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23.6.5

Name:

PS/2 Interrupt Enable Register

Access Type:

IER0, IER1

Write-only

31

-

23

-

15

-

30

-

22

-

14

-

7

-

6

-

5

OVRUN

PARITY: PARITY Interrupt Enable

NACK: Not Acknowledge Interrupt Enable

OVRUN: Overrun Interrupt Enable

RXRDY: Overrun Interrupt Enable

TXEMPTY: Overrun Interrupt Enable

TXRDY: Overrun Interrupt Enable

0: No effect.

1: Enables the corresponding interrupt.

29

-

21

-

13

-

12

-

4

RXRDY

28

-

20

-

11

-

3

-

27

-

19

-

10

-

2

-

26

-

18

-

25

-

17

-

9

PARITY

1

TXEMPTY

8

NACK

0

TXRDY

24

-

16

-

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23.6.6

Name:

PS/2 Interrupt Disable Register

Access Type:

IDR0, IDR1

Write-Only

31

-

23

-

15

-

30

-

22

-

14

-

7

-

6

-

5

OVRUN

PARITY: PARITY Interrupt Disable

NACK: Not Acknowledge Interrupt Disable

OVRUN: Overrun Interrupt Disable

RXRDY: Overrun Interrupt Disable

TXEMPTY: Overrun Interrupt Disable

TXRDY: Overrun Interrupt Disable

0: No effect.

1: Disables the corresponding interrupt.

29

-

21

-

13

-

12

-

4

RXRDY

28

-

20

-

11

-

3

-

27

-

19

-

10

-

2

-

26

-

18

-

25

-

17

-

9

PARITY

1

TXEMPTY

8

NACK

0

TXRDY

24

-

16

-

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23.6.7

Name:

PS/2 Interrupt Mask Register

Access Type:

IMR0, IMR1

Read-only

31

-

23

-

15

-

30

-

22

-

14

-

29

-

21

-

13

-

7

-

6

-

5

OVRUN

PARITY: PARITY Interrupt Mask

NACK: Not Acknowledge Interrupt Mask

OVRUN: Overrun Interrupt Mask

RXRDY: Overrun Interrupt Mask

TXEMPTY: Overrun Interrupt Mask

TXRDY: Overrun Interrupt Mask

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

4

RXRDY

28

-

20

-

12

-

11

-

3

-

27

-

19

-

10

-

2

-

26

-

18

-

25

-

17

-

9

PARITY

1

TXEMPTY

8

NACK

0

TXRDY

24

-

16

-

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23.6.8

Name:

PS/2 Prescale Register

Access Type:

PSR0, PSR1

Read/Write

31

15

-

7

-

23

-

30

14

-

6

-

22

-

29

13

-

5

-

21

-

PRSCV: Prescale Value

28

-

20

-

12

4

PRSCV

3

27

-

19

-

11

26

-

18

-

10

PRSCV

2

25

-

17

-

9

1

24

-

16

-

8

0

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24. Synchronous Serial Controller (SSC)

Rev: 2.2.0.0

24.1

Features

Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications

Contains an Independent Receiver and Transmitter and a Common Clock Divider

Interfaced with Two PDC Channels (DMA Access) to Reduce Processor Overhead

Offers a Configurable Frame Sync and Data Length

Receiver and Transmitter Can be Programmed to Start Automatically or on Detection of Different

Events on the Frame Sync Signal

Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Synchronization

Signal

24.2

Description

The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.

The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the

TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal.

The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention.

Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following:

• CODEC’s in master or slave mode

• DAC through dedicated serial interface, particularly I2S

• Magnetic card reader

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24.3

Block Diagram

Figure 24-1. Block Diagram

High

Speed

Bus

Peripheral Bus

Bridge

PDC

Peripheral

Bus

Power

Manager

MCK

SSC Interface

PIO

Interrupt Control

SSC Interrupt

24.4

Application Block Diagram

Figure 24-2. Application Block Diagram

OS or RTOS Driver

Serial AUDIO Codec

Power

Management

Interrupt

Management

Test

Management

SSC

Time Slot

Management

Frame

Management

Line Interface

RF

RK

RD

TF

TK

TD

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24.5

Pin Name List

Table 24-1.

I/O Lines Description

Pin Name Pin Description

RF

RK

RD

TF

TK

TD

Receiver Frame Synchro

Receiver Clock

Receiver Data

Transmitter Frame Synchro

Transmitter Clock

Transmitter Data

Type

Input/Output

Input/Output

Input

Input/Output

Input/Output

Output

24.6

Product Dependencies

24.6.1

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.

Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode.

Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode.

24.6.2

24.6.3

Power Management

The SSC clock is generated by the power manager. Before using the SSC, the programmer must ensure that the SSC clock is enabled in the power manager.

In the SSC description, Master Clock (MCK) is the bus clock of the peripheral bus to which the

SSC is connected.

Interrupt

The SSC interface has an interrupt line connected to the interrupt controller. Handling interrupts requires programming the interrupt controller before configuring the SSC.

All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register.

24.7

Functional Description

This chapter contains the functional description of the following: SSC Functional Block, Clock

Management, Data format, Start, Transmitter, Receiver and Frame Sync.

The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the

SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2.

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Figure 24-3. SSC Functional Block Diagram

MCK

Clock

Divider

Transmitter

Clock Output

Controller

TK Input

Transmit Clock

Controller

TX clock

Frame Sync

Controller

RX clock

TF

RF

Start

Selector

TX PDC

Transmit Shift Register

Transmit Holding

Register

Load Shift

Transmit Sync

Holding Register

TK

TF

TD

Peripheral

Bus

User

Interface

PDC

Interrupt Control

Receiver

Clock Output

Controller

RK Input

Receive Clock

Controller

RX Clock

Frame Sync

Controller

TX Clock

RF

TF

Start

Selector

Receive Shift Register

RX PDC

Receive Holding

Register

Load Shift

Receive Sync

Holding Register

RK

RF

RD

Interrupt Controller

24.7.1

Clock Management

The transmitter clock can be generated by:

• an external clock received on the TK I/O pad

• the receiver clock

• the internal clock divider

The receiver clock can be generated by:

• an external clock received on the RK I/O pad

• the transmitter clock

• the internal clock divider

Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad.

This allows the SSC to support many Master and Slave Mode data transfers.

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24.7.1.1

Clock Divider

Figure 24-4. Divided Clock Block Diagram

Clock Divider

SSC_CMR

MCK

/ 2

12-bit Counter

Divided Clock

AT32AP7001

The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive.

When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master

Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd.

Figure 24-5. Divided Clock Generation

Master Clock

Divided Clock

DIV = 1

Divided Clock Frequency = MCK/2

Master Clock

Divided Clock

DIV = 3

Divided Clock Frequency = MCK/6

24.7.1.2

Table 24-2.

Maximum

MCK / 2

Minimum

MCK / 8190

Transmitter Clock Management

The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in TCMR

(Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in TCMR.

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The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results.

Figure 24-6. Transmitter Clock Management

TK (pin)

MUX Tri_state

Controller

Clock

Output

Receiver

Clock

Divider

Clock

CKO

Data Transfer

CKS

INV

MUX

Tri-state

Controller

Transmitter

Clock

CKI CKG

24.7.1.3

Receiver Clock Management

The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in RCMR

(Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in RCMR.

The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer.

The clock output is configured by the RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results.

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Figure 24-7. Receiver Clock Management

RK (pin)

MUX

Tri-state

Controller

Transmitter

Clock

Divider

Clock

CKO

Data Transfer

CKS INV

MUX

Clock

Output

Tri-state

Controller

Receiver

Clock

CKI

CKG

24.7.1.4

24.7.2

Serial Clock Ratio Considerations

The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is:

– Master Clock divided by 2 if Receiver Frame Synchro is input

– Master Clock divided by 3 if Receiver Frame Synchro is output

In addition, the maximum clock speed allowed on the TK pin is:

– Master Clock divided by 6 if Transmit Frame Synchro is input

– Master Clock divided by 2 if Transmit Frame Synchro is output

Transmitter Operations

A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission.

The start event is configured by setting the Transmit Clock Mode Register (TCMR). See Section

“24.7.4” on page 351.

The frame synchronization is configured setting the Transmit Frame Mode Register (TFMR).

See Section “24.7.5” on page 353.

To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the TCMR. Data is written by the application to the THR register then transferred to the shift register according to the data format selected.

When both the THR and the transmit shift register are empty, the status flag TXEMPTY is set in

SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SR and additional data can be loaded in the holding register.

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Figure 24-8. Transmitter Block Diagram

SSC_CR.TXEN

SSC_SR.TXEN

SSC_CR.TXDIS

SSC_TFMR.DATDEF

RF

TF

Transmitter Clock

Start

Selector

SSC_TFMR.MSBF

Transmit Shift Register

1

0

SSC_TFMR.FSDEN

SSC_TCMR.STTDLY

0 1

SSC_TFMR.DATLEN

SSC_THR SSC_TSHR

SSC_TCMR.STTDLY

SSC_TFMR.FSDEN

SSC_TFMR.DATNB

SSC_TFMR.FSLEN

TD

24.7.3

Receiver Operations

A received frame is triggered by a start event and can be followed by synchronization data before data transmission.

The start event is configured setting the Receive Clock Mode Register (RCMR).

See Section

“24.7.4” on page 351.

The frame synchronization is configured setting the Receive Frame Mode Register (RFMR). See

Section “24.7.5” on page 353.

The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the RCMR. The data is transferred from the shift register depending on the data format selected.

When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SR and the receiver shift register is transferred in the RHR register.

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Figure 24-9. Receiver Block Diagram

SSC_CR.RXEN

SSC_SR.RXEN

SSC_CR.RXDIS

RF TF

Receiver Clock

Start

Selector

SSC_RFMR.MSBF

SSC_RFMR.DATNB

Receive Shift Register

RD

24.7.4

SSC_RCMR.STTDLY

Start

SSC_RSHR SSC_RHR

SSC_RFMR.FSLEN

SSC_RFMR.DATLEN

The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of TCMR and in the Receive

Start Selection (START) field of RCMR.

Under the following conditions the start event is independently programmable:

• Continuous. In this case, the transmission starts as soon as a word is written in THR and the reception starts as soon as the Receiver is enabled.

• Synchronously with the transmitter/receiver

• On detection of a falling/rising edge on TF/RF

• On detection of a low level/high level on TF/RF

• On detection of a level change or an edge on TF/RF

A start can be programmed in the same manner on either side of the Transmit/Receive Clock

Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive).

Moreover, the Receiver can start when data is detected in the bit stream with the Compare

Functions.

Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode

Register (TFMR/RFMR).

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Figure 24-10. Transmit Start Mode

TK

TF

(Input)

Start = Low Level on TF

TD

(Output)

Start = Falling Edge on TF

TD

(Output)

Start = High Level on TF

TD

(Output)

Start = Rising Edge on TF TD

(Output)

Start = Level Change on TF

TD

(Output)

Start = Any Edge on TF

TD

(Output)

X BO B1

STTDLY

X

X

X

BO B1

X

BO

X

BO

B1

STTDLY

BO B1

STTDLY

BO B1

B1 BO

STTDLY

B1

STTDLY

BO B1

STTDLY

Figure 24-11. Receive Pulse/Edge Start Modes

RK

RF

(Input)

Start = Low Level on RF

RD

(Input)

Start = Falling Edge on RF

RD

(Input)

Start = High Level on RF

Start = Rising Edge on RF

RD

(Input)

RD

(Input)

Start = Level Change on RF

RD

(Input)

Start = Any Edge on RF

RD

(Input)

X

X

X

X

BO

X

BO

X

BO

B1

BO

B1

B1

STTDLY

STTDLY

BO B1

STTDLY

BO B1

B1 BO

STTDLY

B1

STTDLY

BO B1

STTDLY

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AT32AP7001

24.7.5

24.7.5.1

Frame Sync

The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (RFMR) and in the Transmit Frame Mode Register (TFMR) are used to select the required waveform.

• Programmable low or high levels during data transfer are supported.

• Programmable high levels before the start of data transfers or toggling are also supported.

If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in RFMR and TFMR programs the length of the pulse, from 1 bit time up to 16 bit time.

The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in RCMR and TCMR.

Frame Sync Data

Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.

During the Frame Sync signal, the Receiver can sample the RD line and store the data in the

Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in RFMR/TFMR.

Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register.

The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync

Data Enable (FSDEN) in TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit

Register, then shifted out.

24.7.5.2

Frame Sync Edge Detection

The Frame Sync Edge detection is programmed by the FSEDGE field in RFMR/TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SR) on frame synchro edge detection (signals RF/TF).

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24.7.6

Receive Compare Modes

Figure 24-12. Receive Compare Modes

RK

RD

(Input)

CMP0 CMP1 CMP2 CMP3

Start

FSLEN

Up to 16 Bits

(4 in This Example)

Ignored

STDLY

B0 B1

DATLEN

B2

24.7.6.1

24.7.7

Compare Functions

Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last FSLEN bits received at the FSLEN lower bit of the data contained in the

Compare 0 Register (RC0R). When this start event is selected, the user can program the

Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in RCMR.

Data Format

The data framing format of both the transmitter and the receiver are programmable through the

Transmitter Frame Mode Register (TFMR) and the Receiver Frame Mode Register (RFMR). In either case, the user can independently select:

• the event that starts the data transfer (START)

• the delay in number of bit periods between the start event and the first data bit (

STTDLY

)

• the length of the data (DATLEN)

• the number of data to be transferred for each start event (DATNB).

• the length of synchronization transferred for each start event (FSLEN)

• the bit sense: most or lowest significant bit first (MSBF).

Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync

Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in TFMR.

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Table 24-3.

Data Frame Registers

Transmitter Receiver

TFMR

TFMR

TFMR

TFMR

TFMR

TFMR

TCMR

TCMR

RFMR

RFMR

RFMR

RFMR

RCMR

RCMR

Field

DATLEN

DATNB

MSBF

FSLEN

DATDEF

FSDEN

PERIOD

STTDLY

Length

Up to 32

Up to 16

Up to 16

0 or 1

Up to 512

Up to 255

Comment

Size of word

Number of words transmitted in frame

Most significant bit first

Size of Synchro data register

Data default value ended

Enable send TSHR

Frame size

Size of transmit start delay

Figure 24-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes

Start

PERIOD

TF/RF

(1)

FSLEN

TD

(If FSDEN = 1)

Sync Data Default

From SSC_TSHR FromDATDEF

TD

(If FSDEN = 0)

RD

Default

From DATDEF

Ignored

Sync Data

To SSC_RSHR

Data

From SSC_THR

Data

From SSC_THR

Data

To SSC_RHR

STTDLY DATLEN

Start

Data

From SSC_THR

Data

From SSC_THR

Data

To SSC_RHR

DATLEN

Default

FromDATDEF

Sync Data

Default

From DATDEF

Ignored

Sync Data

DATNB

Note: 1. Example of input on falling edge of TF/RF.

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Figure 24-14. Transmit Frame Format in Continuous Mode

Start

TD

Data

From SSC_THR

DATLEN

Start: 1. TXEMPTY set to 1

2. Write into the SSC_THR

Data

From SSC_THR

DATLEN

Default

Note: 1. STTDLY is set to 0. In this example, THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode.

Figure 24-15. Receive Frame Format in Continuous Mode

Start = Enable Receiver

RD Data

To SSC_RHR

DATLEN

Data

To SSC_RHR

DATLEN

Note: 1. STTDLY is set to 0.

24.7.8

Loop Mode

The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.

24.7.9

Interrupt

Most bits in SR have a corresponding bit in interrupt management registers.

The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing IER (Interrupt Enable Register) and IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the interrupt controller.

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Figure 24-16. Interrupt Block Diagram

SSC_IMR

SSC_IER

Set

SSC_IDR

Clear

PDC

TXBUFE

ENDTX

Transmitter

TXRDY

TXEMPTY

TXSYNC

Interrupt

Control

SSC Interrupt

RXBUFF

ENDRX

Receiver

RXRDY

OVRUN

RXSYNC

24.8

SSC Application Examples

The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here.

Figure 24-17. Audio Application Block Diagram

Clock SCK

TK

Word Select WS

TF

Data SD

TD

SSC

RD

Clock SCK

RF

Word Select WS

RK

Data SD

I2S

RECEIVER

MSB

Left Channel

LSB

MSB

Right Channel

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Figure 24-18. Codec Application Block Diagram

Serial Data Clock (SCLK)

TK

Frame sync (FSYNC)

TF

Serial Data Out

TD

SSC

Serial Data In

RD

RF

RK

Serial Data Clock (SCLK)

Frame sync (FSYNC)

Serial Data Out

Serial Data In

CODEC

First Time Slot

Dstart

Figure 24-19. Time Slot Application Block Diagram

SCLK

TK

FSYNC

TF

Data Out

TD

SSC

Data in

RD

RF

RK

CODEC

First

Time Slot

CODEC

Second

Time Slot

Dend

Serial Data Clock (SCLK)

Frame sync (FSYNC)

Serial Data Out

Serial Data in

First Time Slot

Dstart

Second Time Slot

Dend

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24.9

Synchronous Serial Controller (SSC) User Interface

Table 24-4.

Register Mapping

Offset

0x0

0x4

Register

Control Register

Clock Mode Register

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

0x44

0x8

0xC

0x10

0x14

0x18

0x1C

0x20

0x24

Reserved

Reserved

Receive Clock Mode Register

Receive Frame Mode Register

Transmit Clock Mode Register

Transmit Frame Mode Register

Receive Holding Register

Transmit Holding Register

Reserved

Reserved

Receive Sync. Holding Register

Transmit Sync. Holding Register

Receive Compare 0 Register

Receive Compare 1 Register

Status Register

Interrupt Enable Register

0x48

0x4C

Interrupt Disable Register

Interrupt Mask Register

0x50-0xFC Reserved

0x100- 0x124 Reserved for Peripheral Data Controller (PDC)

Register Name

CR

CMR

RCMR

RFMR

TCMR

TFMR

RHR

THR

RSHR

TSHR

RC0R

RC1R

SR

IER

IDR

IMR

Access

Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read

Write

Read

Read/Write

Read/Write

Read/Write

Read

Write

Write

Read

0x0

0x0

0x0

0x0

0x0

Reset

0x0

0x0

0x0

0x0

0x0

0x000000CC

0x0

359

32015D–AVR32–10/07

AT32AP7001

24.9.1

Name:

SSC Control Register

CR

Access Type:

31

Write-only

30

29

23

15

SWRST

7

22

14

6

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

TXDIS

1

RXDIS

• RXEN: Receive Enable

0: No effect.

1: Enables Receive if RXDIS is not set.

• RXDIS: Receive Disable

0: No effect.

1: Disables Receive. If a character is currently being received, disables at end of current character reception.

• TXEN: Transmit Enable

0: No effect.

1: Enables Transmit if TXDIS is not set.

• TXDIS: Transmit Disable

0: No effect.

1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission.

• SWRST: Software Reset

0: No effect.

1: Performs a software reset. Has priority on any other bit in CR.

24

16

8

TXEN

0

RXEN

360

32015D–AVR32–10/07

AT32AP7001

24.9.2

Name:

SSC Clock Mode Register

CMR

Access Type:

31

Read/Write

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

DIV

25

17

9

1

24

16

8

0

DIV

• DIV: Clock Divider

0: The Clock Divider is not active.

Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.

361

32015D–AVR32–10/07

AT32AP7001

24.9.3

Name:

SSC Receive Clock Mode Register

RCMR

Access Type:

31

Read/Write

30 29

23

15

7

CKG

22

14

6

21

13

5

CKI

28

PERIOD

27

20

STTDLY

19

11 12

STOP

4 3

CKO

• CKS: Receive Clock Selection

CKS

0x0

0x1

0x2

0x3

Selected Receive Clock

Divided Clock

TK Clock signal

RK pin

Reserved

• CKO: Receive Clock Output Mode Selection

CKO Receive Clock Output Mode

0x0

0x1

0x2

0x3-0x7

None

Continuous Receive Clock

Receive Clock only during data transfers

Reserved

26

18

25

17

10

START

9

2 1

8

CKS

0

RK pin

Input-only

Output

Output

24

16

• CKI: Receive Clock Inversion

0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge.

1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge.

CKI affects only the Receive Clock and not the output clock signal.

362

32015D–AVR32–10/07

AT32AP7001

• CKG: Receive Clock Gating Selection

CKG

0x0

0x1

0x2

0x3

Receive Clock Gating

None, continuous clock

Receive Clock enabled only if RF Low

Receive Clock enabled only if RF High

Reserved

• START: Receive Start Selection

START

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9-0xF

Receive Start

Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.

Transmit start

Detection of a low level on RF signal

Detection of a high level on RF signal

Detection of a falling edge on RF signal

Detection of a rising edge on RF signal

Detection of any level change on RF signal

Detection of any edge on RF signal

Compare 0

Reserved

• STOP: Receive Stop Selection

0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0.

1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.

• STTDLY: Receive Start Delay

If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.

When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.

Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG

(Receive Sync Data) reception.

• PERIOD: Receive Period Divider Selection

This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no

PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.

363

32015D–AVR32–10/07

AT32AP7001

24.9.4

Name:

SSC Receive Frame Mode Register

RFMR

Access Type:

31

-

Read/Write

30

-

29

-

22 23

15

7

MSBF

14

6

21

FSOS

13

5

LOOP

28

-

20

12

4

27

19

11

26

18

10

FSLEN

DATNB

25

17

9

24

FSEDGE

16

8

3 2

DATLEN

1 0

• DATLEN: Data Length

0: Forbidden value (1-bit data length not supported).

Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the

PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and

15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.

• LOOP: Loop Mode

0: Normal operating mode.

1: RD is driven by TD, RF is driven by TF and TK drives RK.

• MSBF: Most Significant Bit First

0: The lowest significant bit of the data register is sampled first in the bit stream.

1: The most significant bit of the data register is sampled first in the bit stream.

• DATNB: Data Number per Frame

This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).

• FSLEN: Receive Frame Sync Length

This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive

Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register.

Pulse length is equal to (FSLEN + 1) Receive Clock periods. Thus, if FSLEN is 0, the Receive Frame Sync signal is generated during one Receive Clock period.

364

32015D–AVR32–10/07

AT32AP7001

• FSOS: Receive Frame Sync Output Selection

FSOS

0x0

0x1

0x2

0x3

0x4

0x5

0x6-0x7

Selected Receive Frame Sync Signal

None

Negative Pulse

Positive Pulse

Driven Low during data transfer

Driven High during data transfer

Toggling at each start of data transfer

Reserved

• FSEDGE: Frame Sync Edge Detection

Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.

FSEDGE

0x0

0x1

Frame Sync Edge Detection

Positive Edge Detection

Negative Edge Detection

RF Pin

Input-only

Output

Output

Output

Output

Output

Undefined

365

32015D–AVR32–10/07

AT32AP7001

24.9.5

Name:

SSC Transmit Clock Mode Register

TCMR

Access Type:

31

Read/Write

30 29

23

15

22

14

21

13

7

CKG

6 5

CKI

• CKS: Transmit Clock Selection

CKS Selected Transmit Clock

0x0

0x1

0x2

0x3

Divided Clock

RK Clock signal

TK Pin

Reserved

4

28

PERIOD

27

20

STTDLY

19

12

11

3

CKO

• CKO: Transmit Clock Output Mode Selection

CKO Transmit Clock Output Mode

0x0

0x1

0x2

0x3-0x7

None

Continuous Transmit Clock

Transmit Clock only during data transfers

Reserved

26

18

25

17

10

START

9

2 1

8

CKS

0

TK pin

Input-only

Output

Output

24

16

• CKI: Transmit Clock Inversion

0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge.

1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge.

CKI affects only the Transmit Clock and not the output clock signal.

366

32015D–AVR32–10/07

AT32AP7001

• CKG: Transmit Clock Gating Selection

CKG

0x0

0x1

0x2

0x3

Transmit Clock Gating

None, continuous clock

Transmit Clock enabled only if TF Low

Transmit Clock enabled only if TF High

Reserved

• START: Transmit Start Selection

START

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8 - 0xF

Transmit Start

Continuous, as soon as a word is written in the THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.

Receive start

Detection of a low level on TF signal

Detection of a high level on TF signal

Detection of a falling edge on TF signal

Detection of a rising edge on TF signal

Detection of any level change on TF signal

Detection of any edge on TF signal

Reserved

• STTDLY: Transmit Start Delay

If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.

Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG.

• PERIOD: Transmit Period Divider Selection

This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.

367

32015D–AVR32–10/07

AT32AP7001

24.9.6

Name:

SSC Transmit Frame Mode Register

TFMR

Access Type:

31

-

Read/Write

30

-

29

-

28

-

27

19

26

18

25

17

24

FSEDGE

16 23

FSDEN

15

7

MSBF

22

14

6

21

FSOS

13

5

DATDEF

20

12

4

11 10

FSLEN

DATNB

9 8

3 2

DATLEN

1 0

• DATLEN: Data Length

0: Forbidden value (1-bit data length not supported).

Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the

PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15

(included), half-words are transferred, and for any other value, 32-bit words are transferred.

• DATDEF: Data Default Value

This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the

PIO Controller, the pin is enabled only if the SCC TD output is 1.

• MSBF: Most Significant Bit First

0: The lowest significant bit of the data register is shifted out first in the bit stream.

1: The most significant bit of the data register is shifted out first in the bit stream.

• DATNB: Data Number per frame

This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).

• FSLEN: Transmit Frame Sync Length

This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync

Data Register if FSDEN is 1.

Pulse length is equal to (FSLEN + 1) Transmit Clock periods, i.e., the pulse length can range from 1 to 16 Transmit Clock periods. If FSLEN is 0, the Transmit Frame Sync signal is generated during one Transmit Clock period.

368

32015D–AVR32–10/07

• FSOS: Transmit Frame Sync Output Selection

FSOS

0x0

0x1

0x2

0x3

0x4

0x5

0x6-0x7

Selected Transmit Frame Sync Signal

None

Negative Pulse

Positive Pulse

Driven Low during data transfer

Driven High during data transfer

Toggling at each start of data transfer

Reserved

• FSDEN: Frame Sync Data Enable

0: The TD line is driven with the default value during the Transmit Frame Sync signal.

1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.

• FSEDGE: Frame Sync Edge Detection

Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).

FSEDGE

0x0

0x1

Frame Sync Edge Detection

Positive Edge Detection

Negative Edge Detection

AT32AP7001

TF Pin

Input-only

Output

Output

Output

Output

Output

Undefined

369

32015D–AVR32–10/07

AT32AP7001

24.9.7

Name:

SSC Receive Holding Register

RHR

Access Type:

31

Read-only

30 29 28 27 26

RDAT

23 22 21 20 19 18

RDAT

15 14 13 12 11 10

RDAT

7 6 5 4 3

RDAT

• RDAT: Receive Data

Right aligned regardless of the number of data bits defined by DATLEN in RFMR.

2

9

1

25

17

8

0

24

16

370

32015D–AVR32–10/07

AT32AP7001

24.9.8

Name:

SSC Transmit Holding Register

THR

Access Type:

31

Write-only

30 29 28 27 26

TDAT

23 22 21 20 19 18

TDAT

15 14 13 12 11 10

TDAT

7 6 5 4 3

TDAT

• TDAT: Transmit Data

Right aligned regardless of the number of data bits defined by DATLEN in TFMR.

2

9

1

25

17

8

0

24

16

371

32015D–AVR32–10/07

AT32AP7001

24.9.9

Name:

SSC Receive Synchronization Holding Register

RSHR

Access Type:

31

Read-only

30

29

28

23

15

22

14

21

13

20

12

RSDAT

27

19

11

7 6 5 4 3

RSDAT

• RSDAT: Receive Synchronization Data

26

18

10

2

25

17

9

1

24

16

8

0

372

32015D–AVR32–10/07

AT32AP7001

24.9.10

SSC Transmit Synchronization Holding Register

Name:

TSHR

Access Type:

31

Read/Write

30

29

28

23

15

22

14

21

13

20

12

TSDAT

27

19

11

7 6 5 4 3

TSDAT

• TSDAT: Transmit Synchronization Data

26

18

10

2

25

17

9

1

24

16

8

0

373

32015D–AVR32–10/07

AT32AP7001

24.9.11

SSC Receive Compare 0 Register

Name:

RC0R

Access Type:

31

Read/Write

30

29

23

15

22

14

21

13

7 6 5

28

20

12

CP0

4

CP0

27

19

11

3

• CP0: Receive Compare Data 0

26

18

10

2

25

17

9

1

24

16

8

0

374

32015D–AVR32–10/07

AT32AP7001

24.9.12

SSC Receive Compare 1 Register

Name:

RC1R

Access Type:

31

Read/Write

30

29

23

15

22

14

21

13

7 6 5

28

20

12

CP1

4

CP1

27

19

11

3

• CP1: Receive Compare Data 1

26

18

10

2

25

17

9

1

24

16

8

0

375

32015D–AVR32–10/07

AT32AP7001

24.9.13

SSC Status Register

Name:

SR

Access Type:

31

Read-only

30

29

23

15

7

RXBUFF

22

14

6

ENDRX

21

13

5

OVRUN

28

20

12

4

RXRDY

27

19

11

RXSYN

3

TXBUFE

26

18

10

TXSYN

2

ENDTX

25

17

RXEN

9

CP1

1

TXEMPTY

• TXRDY: Transmit Ready

0: Data has been loaded in THR and is waiting to be loaded in the Transmit Shift Register (TSR).

1: THR is empty.

• TXEMPTY: Transmit Empty

0: Data remains in THR or is currently transmitted from TSR.

1: Last data written in THR has been loaded in TSR and last data loaded in TSR has been transmitted.

• ENDTX: End of Transmission

0: The register TCR has not reached 0 since the last write in TCR or TNCR.

1: The register TCR has reached 0 since the last write in TCR or TNCR.

• TXBUFE: Transmit Buffer Empty

0: TCR or TNCR have a value other than 0.

1: Both TCR and TNCR have a value of 0.

• RXRDY: Receive Ready

0: RHR is empty.

1: Data has been received and loaded in RHR.

• OVRUN: Receive Overrun

0: No data has been loaded in RHR while previous data has not been read since the last read of the Status Register.

1: Data has been loaded in RHR while previous data has not yet been read since the last read of the Status Register.

• ENDRX: End of Reception

0: Data is written on the Receive Counter Register or Receive Next Counter Register.

1: End of PDC transfer when Receive Counter Register has arrived at zero.

• RXBUFF: Receive Buffer Full

0: RCR or RNCR have a value other than 0.

1: Both RCR and RNCR have a value of 0.

24

16

TXEN

8

CP0

0

TXRDY

376

32015D–AVR32–10/07

• CP0: Compare 0

0: A compare 0 has not occurred since the last read of the Status Register.

1: A compare 0 has occurred since the last read of the Status Register.

• CP1: Compare 1

0: A compare 1 has not occurred since the last read of the Status Register.

1: A compare 1 has occurred since the last read of the Status Register.

• TXSYN: Transmit Sync

0: A Tx Sync has not occurred since the last read of the Status Register.

1: A Tx Sync has occurred since the last read of the Status Register.

• RXSYN: Receive Sync

0: An Rx Sync has not occurred since the last read of the Status Register.

1: An Rx Sync has occurred since the last read of the Status Register.

• TXEN: Transmit Enable

0: Transmit is disabled.

1: Transmit is enabled.

• RXEN: Receive Enable

0: Receive is disabled.

1: Receive is enabled.

AT32AP7001

377

32015D–AVR32–10/07

AT32AP7001

24.9.14

SSC Interrupt Enable Register

Name:

IER

Access Type:

31

Write-only

30

29

23

15

7

RXBUFF

22

14

6

ENDRX

21

13

5

OVRUN

• TXRDY: Transmit Ready Interrupt Enable

0: No effect.

1: Enables the Transmit Ready Interrupt.

• TXEMPTY: Transmit Empty Interrupt Enable

0: No effect.

1: Enables the Transmit Empty Interrupt.

• ENDTX: End of Transmission Interrupt Enable

0: No effect.

1: Enables the End of Transmission Interrupt.

• TXBUFE: Transmit Buffer Empty Interrupt Enable

0: No effect.

1: Enables the Transmit Buffer Empty Interrupt

• RXRDY: Receive Ready Interrupt Enable

0: No effect.

1: Enables the Receive Ready Interrupt.

• OVRUN: Receive Overrun Interrupt Enable

0: No effect.

1: Enables the Receive Overrun Interrupt.

• ENDRX: End of Reception Interrupt Enable

0: No effect.

1: Enables the End of Reception Interrupt.

• RXBUFF: Receive Buffer Full Interrupt Enable

0: No effect.

1: Enables the Receive Buffer Full Interrupt.

28

20

12

4

RXRDY

27

19

11

RXSYN

3

TXBUFE

26

18

10

TXSYN

2

ENDTX

25

17

9

CP1

1

TXEMPTY

24

16

8

CP0

0

TXRDY

378

32015D–AVR32–10/07

• CP0: Compare 0 Interrupt Enable

0: No effect.

1: Enables the Compare 0 Interrupt.

• CP1: Compare 1 Interrupt Enable

0: No effect.

1: Enables the Compare 1 Interrupt.

• TXSYN: Tx Sync Interrupt Enable

0: No effect.

1: Enables the Tx Sync Interrupt.

• RXSYN: Rx Sync Interrupt Enable

0: No effect.

1: Enables the Rx Sync Interrupt.

AT32AP7001

32015D–AVR32–10/07

379

AT32AP7001

24.9.15

SSC Interrupt Disable Register

Name:

IDR

Access Type:

31

Write-only

30

29

23

15

7

RXBUFF

22

14

6

ENDRX

21

13

5

OVRUN

• TXRDY: Transmit Ready Interrupt Disable

0: No effect.

1: Disables the Transmit Ready Interrupt.

• TXEMPTY: Transmit Empty Interrupt Disable

0: No effect.

1: Disables the Transmit Empty Interrupt.

• ENDTX: End of Transmission Interrupt Disable

0: No effect.

1: Disables the End of Transmission Interrupt.

• TXBUFE: Transmit Buffer Empty Interrupt Disable

0: No effect.

1: Disables the Transmit Buffer Empty Interrupt.

• RXRDY: Receive Ready Interrupt Disable

0: No effect.

1: Disables the Receive Ready Interrupt.

• OVRUN: Receive Overrun Interrupt Disable

0: No effect.

1: Disables the Receive Overrun Interrupt.

• ENDRX: End of Reception Interrupt Disable

0: No effect.

1: Disables the End of Reception Interrupt.

• RXBUFF: Receive Buffer Full Interrupt Disable

0: No effect.

1: Disables the Receive Buffer Full Interrupt.

28

20

12

4

RXRDY

27

19

11

RXSYN

3

TXBUFE

26

18

10

TXSYN

2

ENDTX

25

17

9

CP1

1

TXEMPTY

24

16

8

CP0

0

TXRDY

380

32015D–AVR32–10/07

• CP0: Compare 0 Interrupt Disable

0: No effect.

1: Disables the Compare 0 Interrupt.

• CP1: Compare 1 Interrupt Disable

0: No effect.

1: Disables the Compare 1 Interrupt.

• TXSYN: Tx Sync Interrupt Enable

0: No effect.

1: Disables the Tx Sync Interrupt.

• RXSYN: Rx Sync Interrupt Enable

0: No effect.

1: Disables the Rx Sync Interrupt.

AT32AP7001

32015D–AVR32–10/07

381

AT32AP7001

24.9.16

SSC Interrupt Mask Register

Name:

IMR

Access Type:

31

Read-only

30

29

23

15

7

RXBUF

22

14

6

ENDRX

21

13

5

OVRUN

• TXRDY: Transmit Ready Interrupt Mask

0: The Transmit Ready Interrupt is disabled.

1: The Transmit Ready Interrupt is enabled.

• TXEMPTY: Transmit Empty Interrupt Mask

0: The Transmit Empty Interrupt is disabled.

1: The Transmit Empty Interrupt is enabled.

• ENDTX: End of Transmission Interrupt Mask

0: The End of Transmission Interrupt is disabled.

1: The End of Transmission Interrupt is enabled.

• TXBUFE: Transmit Buffer Empty Interrupt Mask

0: The Transmit Buffer Empty Interrupt is disabled.

1: The Transmit Buffer Empty Interrupt is enabled.

• RXRDY: Receive Ready Interrupt Mask

0: The Receive Ready Interrupt is disabled.

1: The Receive Ready Interrupt is enabled.

• OVRUN: Receive Overrun Interrupt Mask

0: The Receive Overrun Interrupt is disabled.

1: The Receive Overrun Interrupt is enabled.

• ENDRX: End of Reception Interrupt Mask

0: The End of Reception Interrupt is disabled.

1: The End of Reception Interrupt is enabled.

• RXBUFF: Receive Buffer Full Interrupt Mask

0: The Receive Buffer Full Interrupt is disabled.

1: The Receive Buffer Full Interrupt is enabled.

28

20

12

4

RXRDY

27

19

11

RXSYN

3

TXBUFE

26

18

10

TXSYN

2

ENDTX

25

17

9

CP1

1

TXEMPTY

24

16

8

CP0

0

TXRDY

382

32015D–AVR32–10/07

• CP0: Compare 0 Interrupt Mask

0: The Compare 0 Interrupt is disabled.

1: The Compare 0 Interrupt is enabled.

• CP1: Compare 1 Interrupt Mask

0: The Compare 1 Interrupt is disabled.

1: The Compare 1 Interrupt is enabled.

• TXSYN: Tx Sync Interrupt Mask

0: The Tx Sync Interrupt is disabled.

1: The Tx Sync Interrupt is enabled.

• RXSYN: Rx Sync Interrupt Mask

0: The Rx Sync Interrupt is disabled.

1: The Rx Sync Interrupt is enabled.

AT32AP7001

32015D–AVR32–10/07

383

AT32AP7001

25. Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

Rev: 3.0.2.1

25.1

Features

Programmable Baud Rate Generator

5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications

– 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode

– Parity Generation and Error Detection

– Framing Error Detection, Overrun Error Detection

– MSB- or LSB-first

– Optional Break Generation and Detection

– By 8 or by 16 Over-sampling Receiver Frequency

– Optional Hardware Handshaking RTS-CTS

– Receiver Time-out and Transmitter Timeguard

– Optional Multidrop Mode with Address Generation and Detection

RS485 with Driver Control Signal

ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards

– NACK Handling, Error Counter with Repetition and Iteration Limit

IrDA Modulation and Demodulation

– Communication at up to 115.2 Kbps

Test Modes

– Remote Loopback, Local Loopback, Automatic Echo

Supports Connection of Two Peripheral DMA Controller Channels (PDC)

– Offers Buffer Transfer without Processor Intervention

25.2

Description

The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission.

The USART features three test modes: remote loopback, local loopback and automatic echo.

The USART supports specific operating modes providing interfaces on RS485 buses, with

ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and

CTS.

The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor.

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25.3

Block Diagram

Figure 25-1. USART Block Diagram

Interrupt

Controller

USART

Interrupt

USART

Peripheral DMA

Controller

Channel Channel

Receiver

Transmitter

PIO

Controller

RXD

RTS

TXD

CTS

SCK

Power

Manager

MCK

DIV

MCK/DIV

SLCK

User Interface

Peripheral Bus

Baud Rate

Generator

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25.4

Application Block Diagram

Figure 25-2. Application Block Diagram

PPP

Serial

Driver

Field Bus

Driver

EMV

Driver

USART

IrLAP

IrDA

Driver

RS232

Drivers

RS485

Drivers

Serial

Port

Differential

Bus

25.5

I/O Lines Description

Table 25-1.

I/O Line Description

Name

SCK

Description

Serial Clock

TXD

RXD

CTS

RTS

Transmit Serial Data

Receive Serial Data

Clear to Send

Request to Send

Smart

Card

Slot

IrDA

Transceivers

Type

I/O

I/O

Input

Input

Output

Active Level

Low

Low

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25.6

Product Dependencies

25.6.1

25.6.2

25.6.3

I/O Lines

The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller.

To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.

Power Management

The USART is not continuously clocked. The programmer must ensure that the USART clock is enabled in the Power Manager (PM) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Master Clock

(MCK) in the USART description is the clock for the peripheral bus to which the USART is connected.

Interrupt

The USART interrupt line is connected on one of the internal sources of the Interrupt Controller.

Using the USART interrupt requires the interrupt controller to be programmed first.

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25.7

Functional Description

25.7.1

The USART is capable of managing several types of serial synchronous or asynchronous communications.

It supports the following communication modes:

• 5- to 9-bit full-duplex asynchronous serial communication

– MSB- or LSB-first

– 1, 1.5 or 2 stop bits

– Parity even, odd, marked, space or none

– By 8 or by 16 over-sampling receiver frequency

– Optional hardware handshaking

– Optional break management

– Optional multidrop serial communication

• High-speed 5- to 9-bit full-duplex synchronous serial communication

– MSB- or LSB-first

– 1 or 2 stop bits

– Parity even, odd, marked, space or none

– By 8 or by 16 over-sampling frequency

– Optional hardware handshaking

– Optional break management

– Optional multidrop serial communication

• RS485 with driver control signal

• ISO7816, T0 or T1 protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

• InfraRed IrDA Modulation and Demodulation

• Test modes

– Remote loopback, local loopback, automatic echo

Baud Rate Generator

The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.

The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode

Register (MR) between:

• the Master Clock MCK

• a division of the Master Clock, the divider being product dependent, but generally set to 8

• the external clock, available on the SCK pin

The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive.

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If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK.

Figure 25-3. Baud Rate Generator

USCLKS

CD

CD

MCK

MCK/DIV

SCK

Reserved

2

3

0

1

16-bit Counter

0

>1

1

0

0

OVER

FIDI

Sampling

Divider

0

SCK

SYNC

1

Baud Rate

Clock

1

SYNC

USCLKS = 3

Sampling

Clock

25.7.1.1

Baud Rate in Asynchronous Mode

If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in MR.

If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock.

The following formula performs the calculation of the Baud Rate.

Baudrate

=

(

SelectedClock

(

Over

)

This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1.

25.7.1.2

Baud Rate Calculation Example

Table 25-2

shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error.

Table 25-2.

Baud Rate Example (OVER = 0)

Source Clock

MHz

Expected Baud

Rate

Bit/s

Calculation Result

3 686 400

4 915 200

5 000 000

38 400

38 400

38 400

6.00

8.00

8.14

CD

6

8

8

Actual Baud Rate

Bit/s

38 400.00

38 400.00

39 062.50

Error

0.00%

0.00%

1.70%

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Table 25-2.

Baud Rate Example (OVER = 0) (Continued)

Source Clock

7 372 800

Expected Baud

Rate

38 400

Calculation Result

12.00

8 000 000

12 000 000

12 288 000

14 318 180

14 745 600

18 432 000

24 000 000

24 576 000

25 000 000

32 000 000

32 768 000

33 000 000

40 000 000

50 000 000

60 000 000

70 000 000

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

38 400

40.69

52.08

53.33

53.71

65.10

81.38

97.66

113.93

13.02

19.53

20.00

23.30

24.00

30.00

39.06

40.00

40

52

53

54

24

30

39

40

65

81

98

114

CD

12

13

20

20

23

Actual Baud Rate

38 400.00

38 461.54

37 500.00

38 400.00

38 908.10

38 400.00

38 400.00

38 461.54

38 400.00

38 109.76

38 461.54

38 641.51

38 194.44

38 461.54

38 580.25

38 265.31

38 377.19

0.00%

0.00%

0.16%

0.00%

0.76%

0.16%

0.63%

0.54%

Error

0.00%

0.16%

2.40%

0.00%

1.31%

0.16%

0.47%

0.35%

0.06%

The baud rate is calculated with the following formula:

BaudRate

=

⁄ ×

16

The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.

Error

=

1

---------------------------------------------------

ActualBaudRate

25.7.1.3

Fractional Baud Rate in Asynchronous Mode

The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.

This fractional part is programmed with the FP field in the Baud Rate Generator Register

(BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud

Rate is calculated using the following formula:

Baudrate

=

(

Over

+ -------

8

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The modified architecture is presented below:

Figure 25-4. Fractional Baud Rate Generator

FP

USCLKS

MCK

MCK/DIV

SCK

Reserved

2

3

0

1

25.7.1.4

25.7.1.5

CD

Modulus

Control

16-bit Counter

FP glitch-free

logic

0

CD

>1

1

0

1

0

SCK

FIDI

OVER

Sampling

Divider

0

SYNC

Baud Rate

Clock

1

Sampling

Clock

SYNC

USCLKS = 3

Baud Rate in Synchronous Mode

If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in BRGR.

BaudRate

=

CD

In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock.

When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the

SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.

Baud Rate in ISO 7816 Mode

The ISO7816 specification defines the bit rate with the following formula:

B

=

Di f

Fi

× where:

• B is the bit rate

• Di is the bit-rate adjustment factor

• Fi is the clock frequency division factor

• f is the ISO7816 clock frequency (Hz)

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Di is a binary value encoded on a 4-bit field, named DI, as represented in

Table 25-3

.

Table 25-3.

Binary and Decimal Values for Di

DI field 0001 0010 0011

Di (decimal) 1 2 4

0100

8

0101

16

0110

32

1000

12

1001

20

Fi is a binary value encoded on a 4-bit field, named FI, as represented in

Table 25-4

.

Table 25-4.

Binary and Decimal Values for Fi

FI field 0000 0001 0010 0011

Fi (decimal 372 372 558 744

0100

1116

0101

1488

0110

1860

1001

512

1010

768

1011

1024

1100

1536

1101

2048

Table 25-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the

baud rate clock.

Table 25-5.

Possible Values for the Fi/Di Ratio

Fi/Di

1

372

372

558

558

774

744

1116

1116

32

12

20

8

16

2

4

186

93

46.5

23.25

11.62

31

18.6

279

139.5

69.75

34.87

17.43

46.5

372

186

93

46.5

23.25

62

558

279

139.5

69.75

34.87

93

1488

1488

744

372

186

93

46.5

124

1806

1860

930

465

232.5

116.2

58.13

155

512

512

256

128

64

32

16

42.66

96

48

24

64

768

768

384

192

1024

1024

512

256

128

64

32

85.33

1536

1536

768

384

192

96

48

128

27.9

37.2

55.8

74.4

93 25.6

38.4

51.2

76.8

102.4

If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the

Mode Register (MR) is first divided by the value programmed in the field CD in the Baud Rate

Generator Register (BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in MR.

2048

2048

1024

512

256

128

64

170.6

This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (FIDI). This is performed by the Sampling Divider, which performs a division by up to

2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value.

The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1).

Figure 25-5 shows the relation between the Elementary Time Unit, corresponding to a bit time,

and the ISO 7816 clock.

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Figure 25-5. Elementary Time Unit (ETU)

FI_DI_RATIO

ISO7816 Clock Cycles

ISO7816 Clock on SCK

ISO7816 I/O Line on TXD

1 ETU

25.7.2

Receiver and Transmitter Control

25.7.3

25.7.3.1

After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (CR). However, the receiver registers can be programmed before the receiver clock is enabled.

After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the

Control Register (CR). However, the transmitter registers can be programmed before being enabled.

The Receiver and the Transmitter can be enabled together or independently.

At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (CR).

The reset commands have the same effect as a hardware reset on the corresponding logic.

Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped.

The user can also independently disable the receiver or the transmitter by setting RXDIS and

TXDIS respectively in CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (THR). If a timeguard is programmed, it is handled normally.

Synchronous and Asynchronous Modes

Transmitter Operations

The transmitter performs the same in both synchronous and asynchronous operating modes

(SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock.

The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register

(MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in MR. The 1.5 stop bit is supported in asynchronous mode only.

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Figure 25-6. Character Transmit

Example: 8-bit, Parity Enabled One Stop

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7 Parity

Bit

Stop

Bit

The characters are sent by writing in the Transmit Holding Register (THR). The transmitter reports two status bits in the Channel Status Register (CSR): TXRDY (Transmitter Ready), which indicates that THR is empty and TXEMPTY, which indicates that all the characters written in THR have been processed. When the current character processing is completed, the last character written in THR is transferred into the Shift Register of the transmitter and THR becomes empty, thus TXRDY raises.

Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in

THR while TXRDY is active has no effect and the written character is lost.

Figure 25-7. Transmitter Status

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop Start

Bit Bit Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Write

US_THR

TXRDY

TXEMPTY

25.7.3.2

Manchester Encoder

When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the

MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10

10 01 01 01 10, assuming the default polarity of the encoder. Figure 25-8

illustrates this coding scheme.

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Figure 25-8. NRZ to Manchester Encoding

1 NRZ encoded data

Manchester encoded data

Txd

0 1 1 0 0 0 1

The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE,

ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the MAN register, the field

TX_PL is used to configure the preamble length.

Figure 25-9

illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the

TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition.

Figure 25-9. Preamble Patterns, Default Polarity Assumed

Manchester encoded data

Txd

SFD DATA

8 bit width "ALL_ONE" Preamble

Manchester encoded data

Txd

SFD

DATA

8 bit width "ALL_ZERO" Preamble

Manchester encoded data

Txd

SFD

DATA

8 bit width "ZERO_ONE" Preamble

Manchester encoded data

Txd

SFD

DATA

8 bit width "ONE_ZERO" Preamble

A start frame delimiter is to be configured using the ONEBIT field in the MR register. It consists of a user-defined pattern that indicates the beginning of a valid data.

Figure 25-10 illustrates

these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at

0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character.

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The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in MR register must be set to 1. In this case, the MODSYNC field in MR is bypassed and the sync configuration is held in the TXSYNH in the THR register. The USART character format is modified and includes sync information.

Figure 25-10. Start Frame Delimiter

Preamble Length is set to 0

SFD

Manchester encoded data

Txd

DATA

One bit start frame delimiter

SFD

Manchester encoded data

Txd

DATA

Manchester encoded data

Txd

SFD

Command Sync start frame delimiter

DATA

Data Sync start frame delimiter

25.7.3.3

Drift Compensation

Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken.

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Figure 25-11. Bit Resynchronization

Oversampling

16x Clock

RXD

Sampling point

Synchro.

Error

Synchro.

Jump

Expected edge

Tolerance

Sync

Jump

Synchro.

Error

25.7.3.4

Asynchronous Receiver

If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (MR).

The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.

If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8

(OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.

The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. The number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit.

Figure 25-12

and

Figure 25-13 illustrate start detection and character reception when USART

operates in asynchronous mode.

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Figure 25-12. Asynchronous Start Detection

Baud Rate

Clock

Sampling

Clock (x16)

RXD

Sampling

1 2 3 4 5 6 7 8

Start

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

D0

Sampling

Detection

RXD

Sampling

1 2 3 4 5 6 7 0 1 2 3 4

Start

Rejection

Figure 25-13. Asynchronous Character Reception

Example: 8-bit, Parity Enabled

Baud Rate

Clock

RXD

Start

Detection

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

16 samples

D0 D1 D2 D3 D4 D5 D6 D7

Parity

Bit

Stop

Bit

25.7.3.5

Manchester Decoder

When the MAN field in MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to

Manchester encoded input data.

An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in MAN register.

Depending on the desired application the preamble pattern matching is to be defined via the

RX_PP field in MAN. See

Figure 25-9

for available preamble patterns.

Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder.

So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled dur-

ing one quarter of a bit time at zero, a start bit is detected. See Figure 25-14 . The sample pulse

rejection mechanism applies.

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Figure 25-14. Asynchronous Start Bit Detection

Sampling

Clock

(16 x)

Manchester encoded data

Txd

1 2 3 4

Start

Detection

The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time.

If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming

stream is decoded into NRZ data and passed to USART for processing. Figure 25-15

illustrates

Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in CSR register is raised. It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1. See

Figure 25-16

for an example of

Manchester error detection during data phase.

Figure 25-15. Preamble Pattern Mismatch

Preamble Mismatch

Manchester coding error

Preamble Mismatch invalid pattern

Manchester encoded data

Txd

SFD DATA

Preamble Length is set to 8

Figure 25-16. Manchester Error Flag

Preamble Length is set to 4

SFD

Elementary character bit time

Manchester encoded data

Txd

Entering USART character area sampling points

Preamble subpacket and Start Frame Delimiter were successfully decoded

Manchester

Coding Error detected

When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR

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25.7.3.6

field in the RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register.

As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-toone transition.

Radio Interface: Manchester Encoded USART Application

This section describes low data rate RF transmission systems and their integration with a

Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes.

The goal is to perform full duplex radio transmission of characters using two different frequency

carriers. See the configuration in Figure 25-17 .

Figure 25-17. Manchester Encoded Characters RF Transmission

Fup frequency Carrier

Upstream

Emitter

Fdown frequency Carrier

Downstream

Receiver

ASK/FSK

Upstream Receiver

LNA

VCO

RF filter

Demod control bi-dir line

ASK/FSK downstream transmitter

PA

RF filter

Mod

VCO control

Serial

Configuration

Interface

Manchester decoder

Manchester encoder

USART

Receiver

USART

Emitter

The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See

Figure 25-18 for an exam-

ple of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency.

When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator out-

puts an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 25-19

.

From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder.

Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a

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user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration.

Figure 25-18. ASK Modulator Output

1

NRZ stream

Manchester encoded data default polarity unipolar output

ASK Modulator

Output

Uptstream Frequency F0

Txd

0 0 1

Figure 25-19. FSK Modulator Output

1

NRZ stream

Manchester encoded data default polarity unipolar output

FSK Modulator

Output

Uptstream Frequencies

[F0, F0+offset]

Txd

0 0 1

25.7.3.7

Synchronous Receiver

In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability.

Configuration fields and bits are the same as in asynchronous mode.

Figure 25-20

illustrates a character reception in synchronous mode.

Figure 25-20. Synchronous Mode Character Reception

Example: 8-bit, Parity Enabled 1 Stop

Baud Rate

Clock

RXD

Sampling

Start D0 D1 D2 D3 D4 D5 D6 D7

Parity Bit

Stop Bit

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25.7.3.8

Receiver Operations

When a character reception is completed, it is transferred to the Receive Holding Register

(RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into

RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register

(CR) with the RSTSTA (Reset Status) bit at 1.

Figure 25-21. Receiver Status

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop Start

Bit Bit Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

RSTSTA = 1

Write

US_CR

Read

US_RHR

RXRDY

OVRE

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25.7.3.9

Parity

The USART supports five parity modes selected by programming the PAR field in the Mode

Register (MR). The PAR field also enables the Multidrop mode, see

”Multidrop Mode” on page

404 . Even and odd parity bit generation and error detection are supported.

If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received

1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error.

Table 25-6

shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even.

Table 25-6.

Parity Bit Examples

Character

A

Hexa

0x41

A

A

A

A

0x41

0x41

0x41

0x41

Binary

0100 0001

0100 0001

0100 0001

0100 0001

0100 0001

Parity Bit

1

0

1

0

None

Parity Mode

Odd

Even

Mark

Space

None

When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status

Register (CSR). The PARE bit can be cleared by writing the Control Register (CR) with the RST-

STA bit at 1. Figure 25-22

illustrates the parity bit status setting and clearing.

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Figure 25-22. Parity Error

Baud Rate

Clock

RXD

Write

US_CR

PARE

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Bad

Parity

Bit

Stop

Bit

RXRDY

RSTSTA = 1

25.7.3.10

Multidrop Mode

If the PAR field in the Mode Register (MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.

If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1.

To handle parity error, the PARE bit is cleared when the Control Register is written with the bit

RSTSTA at 1.

The transmitter sends an address byte (parity bit set) when SENDA is written to CR. In this case, the next byte written to THR is transmitted as an address. Any character written in THR without having written the command SENDA is transmitted normally with the parity at 0.

25.7.3.11

Transmitter Timeguard

The timeguard feature enables the USART interface with slow remote devices.

The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit.

The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits.

As illustrated in Figure 25-23

, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in

THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted.

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Figure 25-23. Timeguard Operations

TG = 4

TG = 4

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Write

US_THR

TXRDY

TXEMPTY

25.7.3.12

Table 25-7 indicates the maximum length of a timeguard period that the transmitter can handle

in relation to the function of the Baud Rate.

Table 25-7.

Maximum Timeguard Length Depending on Baud Rate

Baud Rate Bit time

Bit/sec

1 200

µs

833

9 600 104

14400 69.4

19200

28800

33400

56000

57600

115200

52.1

34.7

29.9

17.9

17.4

8.7

Timeguard

ms

212.50

26.56

17.71

13.28

8.85

7.63

4.55

4.43

2.21

Receiver Time-out

The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel

Status Register (CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame.

The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (RTOR). If the TO field is programmed at 0, the

Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in CSR remains at

0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises.

The user can either:

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• Obtain an interrupt when a time-out is detected after having received at least one character.

This is performed by writing the Control Register (CR) with the STTTO (Start Time-out) bit at

1.

• Obtain a periodic interrupt while no character is received. This is performed by writing CR with the RETTO (Reload and Start Time-out) bit at 1.

If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected.

If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.

Figure 25-24

shows the block diagram of the Receiver Time-out feature.

Figure 25-24. Receiver Time-out Block Diagram

Baud Rate

Clock

TO

16-bit

Value

1

D Q

Clock 16-bit Time-out

Counter

STTTO

= TIMEOUT

Load 0

Clear

Character

Received

RETTO

Table 25-8

gives the maximum time-out period for some standard baud rates.

Table 25-8.

Maximum Time-out Period

Baud Rate Bit Time

bit/sec

600

1 200

2 400

4 800

9 600

14400

19200

28800

33400

56000

57600

200000

µs

1 667

833

417

208

104

69

52

35

30

18

17

5

4 551

3 413

2 276

1 962

1 170

1 138

328

Time-out

ms

109 225

54 613

27 306

13 653

6 827

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25.7.3.13

Framing Error

The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.

A framing error is reported on the FRAME bit of the Channel Status Register (CSR). The

FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1.

Figure 25-25. Framing Error Status

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

RSTSTA = 1

Write

US_CR

FRAME

RXRDY

25.7.3.14

Transmit Break

The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a

0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the

TXD line at least during one character until the user requests the break condition to be removed.

A break is transmitted by writing the Control Register (CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low.

Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed.

The break condition is removed by writing CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes.

The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed.

Writing CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All

STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored.

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After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times.

Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period.

After holding the TXD line for this period, the transmitter resumes normal operations.

Figure 25-26

illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line.

Figure 25-26. Break Transmission

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

STTBRK = 1

Break Transmission

STPBRK = 1

End of Break

Write

US_CR

TXRDY

TXEMPTY

25.7.3.15

25.7.3.16

Receive Break

The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low.

When the low stop bit is detected, the receiver asserts the RXBRK bit in CSR. This bit may be cleared by writing the Control Register (CR) with the bit RSTSTA at 1.

An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.

Hardware Handshaking

The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins

are used to connect with the remote device, as shown in Figure 25-27

.

Figure 25-27. Connection with a Remote Device for Hardware Handshaking

USART

TXD

RXD

CTS

RTS

Remote

Device

RXD

TXD

RTS

CTS

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Setting the USART to operate with hardware handshaking is performed by writing the MODE field in the Mode Register (MR) to the value 0x2.

The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case.

Figure 25-28 shows how the receiver operates if hardware handshaking is enabled. The RTS

pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low.

Figure 25-28. Receiver Behavior when Operating with Hardware Handshaking

RXD

Write

US_CR

RXEN = 1

RXDIS = 1

RTS

RXBUFF

Figure 25-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS

pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls.

Figure 25-29. Transmitter Behavior when Operating with Hardware Handshaking

CTS

TXD

25.7.4

25.7.4.1

ISO7816 Mode

The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link.

Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported.

Setting the USART in ISO7816 mode is performed by writing the MODE field in the Mode Register (MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1.

ISO7816 Mode Overview

The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is

determined by a division of the clock provided to the remote device (see ”Baud Rate Generator” on page 388 ).

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The USART connects to a smart card as shown in Figure 25-30

. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock.

Figure 25-30. Connection of a Smart Card to the USART

USART

SCK

CLK

Smart

Card

I/O

TXD

25.7.4.2

When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to

”USART Mode Register” on page 421

and

”PAR: Parity Type” on page 422

.

The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results.

The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit

Holding Register (THR) or after reading it in the Receive Holding Register (RHR).

Protocol T = 0

In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the

I/O line during the guard time.

If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter

can continue with the transmission of the next character, as shown in Figure 25-31

.

If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as

shown in Figure 25-32

. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time.

When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (RHR). It appropriately sets the PARE bit in the Status Register

(SR) so that the software can handle the error.

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Figure 25-31. T = 0 Protocol without Parity Error

Baud Rate

Clock

RXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity

Bit

Guard

Time 1

Guard

Time 2

Next

Start

Bit

Figure 25-32. T = 0 Protocol with Parity Error

Baud Rate

Clock

I/O

Start

Bit

D0 D1 D2 D3

25.7.4.3

25.7.4.4

25.7.4.5

25.7.4.6

D4 D5 D6 D7

Error

Parity

Bit

Guard

Time 1

Guard

Time 2

Start

Bit

D0

Repetition

D1

Receive Error Counter

The USART receiver also records the total number of errors. This can be read in the Number of

Error (NER) register. The NB_ERRORS field can record up to 255 errors. Reading NER automatically clears the NB_ERRORS field.

Receive NACK Inhibit

The USART can also be configured to inhibit an error. This can be achieved by setting the

INACK bit in the Mode Register (MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (SR). The INACK bit can be cleared by writing the Control Register (CR) with the RSTNACK bit at 1.

Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding

Register, as if no error occurred. However, the RXRDY bit does not raise.

Transmit Character Repetition

When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before m oving on to the next one. Repetition is en abled by writin g the

MAX_ITERATION field in the Mode Register (MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions.

If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION.

When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the

Channel Status Register (CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared.

The ITERATION bit in CSR can be cleared by writing the Control Register with the RSIT bit at 1.

Disable Successive Receive NACK

The receiver can limit the number of successive NACKs sent back to the remote transmitter.

This is programmed by setting the bit DSNACK in the Mode Register (MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as

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25.7.4.7

25.7.5

MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set.

Protocol T = 1

When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (CSR).

IrDA Mode

The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in

Figure 25-33

. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to

115.2 Kb/s.

The USART IrDA mode is enabled by setting the MODE field in the Mode Register (MR) to the value 0x8. The IrDA Filter Register (IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated.

Figure 25-33. Connection to IrDA Transceivers

Receiver

USART

Demodulator

RXD RX

IrDA

Transceivers

TX

Transmitter

Modulator

TXD

25.7.5.1

The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed.

IrDA Modulation

For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in

Table 25-9 .

Table 25-9.

IrDA Pulse Duration

Baud Rate

2.4 Kb/s

9.6 Kb/s

19.2 Kb/s

Pulse Duration (3/16)

78.13 µs

19.53 µs

9.77 µs

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Table 25-9.

IrDA Pulse Duration

Baud Rate

38.4 Kb/s

57.6 Kb/s

115.2 Kb/s

Pulse Duration (3/16)

4.88 µs

3.26 µs

1.63 µs

Figure 25-34

shows an example of character transmission.

Figure 25-34. IrDA Modulation

Transmitter

Output

Start

Bit

0

1

0

1

Data Bits

0

0

1 1

0

Stop

Bit

1

TXD

25.7.5.2

Bit Period

3

16

Bit Period

IrDA Baud Rate

Table 25-10 gives some examples of CD values, baud rate error and pulse duration. Note that

the requirement on the maximum acceptable error of ±1.87% must be met.

Table 25-10. IrDA Baud Rate Error

Peripheral Clock Baud Rate

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

40 000 000

38 400

38 400

38 400

38 400

19 200

19 200

19 200

19 200

115 200

115 200

115 200

115 200

57 600

57 600

57 600

57 600

53

65

12

65

36

43

6

33

107

130

18

22

4

22

CD

2

11

Baud Rate Error

0.00%

1.38%

1.25%

1.38%

0.00%

1.38%

1.25%

0.93%

0.00%

1.38%

0.63%

0.16%

0.00%

0.16%

0.31%

0.16%

4.88

4.88

9.77

9.77

3.26

3.26

4.88

4.88

9.77

9.77

Pulse Time

1.63

1.63

1.63

1.63

3.26

3.26

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25.7.5.3

Table 25-10. IrDA Baud Rate Error (Continued)

Peripheral Clock Baud Rate CD

3 686 400

20 000 000

32 768 000

40 000 000

3 686 400

20 000 000

32 768 000

9 600

9 600

9 600

9 600

2 400

2 400

2 400

24

130

213

260

96

521

853

Baud Rate Error

0.00%

0.16%

0.16%

0.16%

0.00%

0.03%

0.04%

Pulse Time

19.53

19.53

19.53

19.53

78.13

78.13

78.13

IrDA Demodulator

The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.

Figure 25-35

illustrates the operations of the IrDA demodulator.

Figure 25-35. IrDA Demodulator Operations

MCK

RXD

Counter

Value

Receiver

Input

6 5 4 3 2 6

Pulse

Rejected

6 5 4 3 2 1 0

Pulse

Accepted

Driven Low During 16 Baud Rate Clock Cycles

As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly.

414

32015D–AVR32–10/07

AT32AP7001

25.7.6

RS485 Mode

The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in

Figure 25-36 .

Figure 25-36. Typical Connection to a RS485 Bus

USART

RXD

TXD

RTS

Differential

Bus

The USART is set in RS485 mode by programming the MODE field in the Mode Register (MR) to the value 0x1.

The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion.

Figure 25-37 gives an example of the RTS waveform during a character transmission

when the timeguard is enabled.

Figure 25-37. Example of RTS Drive with Timeguard

TG = 4

Baud Rate

Clock

TXD

Start

Bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity Stop

Bit Bit

Write

US_THR

TXRDY

TXEMPTY

RTS

415

32015D–AVR32–10/07

AT32AP7001

25.7.7

25.7.7.1

Test Modes

Normal Mode

The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally.

Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.

Figure 25-38. Normal Mode Configuration

RXD

Receiver

TXD

Transmitter

25.7.7.2

Automatic Echo Mode

Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it

is sent to the TXD pin, as shown in Figure 25-39 . Programming the transmitter has no effect on

the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active.

Figure 25-39. Automatic Echo Mode Configuration

RXD

Receiver

TXD

Transmitter

25.7.7.3

Local Loopback Mode

Local loopback mode connects the output of the transmitter directly to the input of the receiver,

as shown in Figure 25-40 . The TXD and RXD pins are not used. The RXD pin has no effect on

the receiver and the TXD pin is continuously driven high, as in idle state.

Figure 25-40. Local Loopback Mode Configuration

RXD

Receiver

TXD

Transmitter

1

416

32015D–AVR32–10/07

AT32AP7001

25.7.7.4

Remote Loopback Mode

Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 25-41 .

The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission.

Figure 25-41. Remote Loopback Mode Configuration

RXD

Receiver

1

TXD

Transmitter

32015D–AVR32–10/07

417

25.8

USART User Interface

Table 25-11. USART Memory Map

Offset

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020

0x0024

0x0028

0x2C - 0x3C

0x0040

0x0044

0x0048

0x004C

0x0050

0x5C - 0xF8

0xFC

0x100 - 0x128

Register

Control Register

Mode Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Channel Status Register

Receiver Holding Register

Transmitter Holding Register

Baud Rate Generator Register

Receiver Time-out Register

Transmitter Timeguard Register

Reserved

FI DI Ratio Register

Number of Errors Register

Reserved

IrDA Filter Register

Manchester Encoder Decoder Register

Reserved

Version Register

Reserved for PDC Registers

RHR

THR

BRGR

RTOR

TTGR

FIDI

NER

Name

CR

MR

IER

IDR

IMR

CSR

-

IF

MAN

US_VERSION

Note: 1. Values in the Version Register vary with the version of the IP block implementation.

Write-only

Read/Write

Write-only

Write-only

Read-only

Read-only

Read-only

Write-only

Read/Write

Read/Write

Read/Write

Read/Write

Read-only

Read/Write

Read/Write

Read-only

AT32AP7001

0x0

0x0

0x0

0x174

0x0

0x30011004

0x–

(1)

0x0

0x0

418

32015D–AVR32–10/07

AT32AP7001

25.8.1

USART Control Register

Name:

Access Type:

31

CR

Write-only

30

29

23

15

RETTO

7

TXDIS

22

14

RSTNACK

6

TXEN

21

13

RSTIT

5

RXDIS

28

20

12

SENDA

4

RXEN

27

19

RTSDIS

11

STTTO

3

RSTTX

26

18

RTSEN

10

STPBRK

2

RSTRX

25

17

9

STTBRK

1

24

16

8

RSTSTA

0

• RSTRX: Reset Receiver

0: No effect.

1: Resets the receiver.

• RSTTX: Reset Transmitter

0: No effect.

1: Resets the transmitter.

• RXEN: Receiver Enable

0: No effect.

1: Enables the receiver, if RXDIS is 0.

• RXDIS: Receiver Disable

0: No effect.

1: Disables the receiver.

• TXEN: Transmitter Enable

0: No effect.

1: Enables the transmitter if TXDIS is 0.

• TXDIS: Transmitter Disable

0: No effect.

1: Disables the transmitter.

• RSTSTA: Reset Status Bits

0: No effect.

1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in CSR.

• STTBRK: Start Break

0: No effect.

1: Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted.

419

32015D–AVR32–10/07

AT32AP7001

• STPBRK: Stop Break

0: No effect.

1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.

No effect if no break is being transmitted.

• STTTO: Start Time-out

0: No effect

1: Starts waiting for a character before clocking the time-out counter.

• SENDA: Send Address

0: No effect.

1: In Multidrop Mode only, the next character written to the THR is sent with the address bit set.

• RSTIT: Reset Iterations

0: No effect.

1: Resets ITERATION in CSR. No effect if the ISO7816 is not enabled.

• RSTNACK: Reset Non Acknowledge

0: No effect

1: Resets NACK in CSR.

• RETTO: Rearm Time-out

0: No effect

1: Restart Time-out

• RTSEN: Request to Send Enable

0: No effect.

1: Drives the pin RTS to 0.

• RTSDIS: Request to Send Disable

0: No effect.

1: Drives the pin RTS to 1.

420

32015D–AVR32–10/07

AT32AP7001

25.8.2

USART Mode Register

Name:

Access Type:

31

ONEBIT

MR

Read/Write

30

MODSYNC–

29

MAN

23

22

VAR_SYNC

15

CHMODE

14

7 6

CHRL

21

DSNACK

28

FILTER

20

INACK

13

NBSTOP

12

5 4

USCLKS

• MODE

0

0

0

0

0

0

0

0

1

1

• USCLKS: Clock Selection

1

1

0

1

0

0

0

1

0

1

MODE

USCLKS

0

0

1

1

• CHRL: Character Length.

0

1

0

1

0

1

1

0

0

0

1

1

0 x

Selected Clock

MCK

MCK / DIV

Reserved

SCK

0

CHRL

0

Character Length

5 bits

1

0

1

0

0

1

0

1

0 x

27

19

OVER

11

3

26

18

CLKO

10

PAR

2

MODE

25

MAX_ITERATION

17

MODE9

9

1

24

16

MSBF

8

SYNC

0

Mode of the USART

Normal

RS485

Hardware Handshaking

Reserved

IS07816 Protocol: T = 0

Reserved

IS07816 Protocol: T = 1

Reserved

IrDA

Reserved

421

32015D–AVR32–10/07

0

1

1

1

0

1

6 bits

7 bits

8 bits

• SYNC: Synchronous Mode Select

0: USART operates in Asynchronous Mode.

1: USART operates in Synchronous Mode.

• PAR: Parity Type

0

0

0

0

1

1

0

1

1

1

PAR

0

0

0

1

0

1 x x

• NBSTOP: Number of Stop Bits

Parity Type

Even parity

Odd parity

Parity forced to 0 (Space)

Parity forced to 1 (Mark)

No parity

Multidrop mode

NBSTOP

0

0

1

1

0

1

0

1

• CHMODE: Channel Mode

Asynchronous (SYNC = 0)

1 stop bit

1.5 stop bits

2 stop bits

Reserved

Synchronous (SYNC = 1)

1 stop bit

Reserved

2 stop bits

Reserved

0

0

1

1

CHMODE

0

1

0

1

Mode Description

Normal Mode

Automatic Echo. Receiver input is connected to the TXD pin.

Local Loopback. Transmitter output is connected to the Receiver Input..

Remote Loopback. RXD pin is internally connected to the TXD pin.

• MSBF: Bit Order

0: Least Significant Bit is sent/received first.

1: Most Significant Bit is sent/received first.

• MODE9: 9-bit Character Length

0: CHRL defines character length.

1: 9-bit character length.

• CKLO: Clock Output Select

0: The USART does not drive the SCK pin.

AT32AP7001

422

32015D–AVR32–10/07

AT32AP7001

1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.

• OVER: Oversampling Mode

0: 16x Oversampling.

1: 8x Oversampling.

• INACK: Inhibit Non Acknowledge

0: The NACK is generated.

1: The NACK is not generated.

• DSNACK: Disable Successive NACK

0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).

1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag

ITERATION is asserted.

• VAR_SYNC: Variable synchronization of command/data sync Start Frame Delimiter

0: User defined configuration of command or data sync field depending on SYNC value.

1: The sync field is updated when a character is written into THR register.

• MAX_ITERATION

Defines the maximum number of iterations in mode ISO7816, protocol T= 0.

• FILTER: Infrared Receive Line Filter

0: The USART does not filter the receive line.

1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).

• MAN: Manchester Encoder/Decoder Enable

0: Manchester Encoder/Decoder are disabled.

1: Manchester Encoder/Decoder are enabled.

MODSYNC

: Manchester Synchronization mode

0:The Manchester Start bit is a 0 to 1 transition

1: The Manchester Start bit is a 1 to 0 transition.

• ONEBIT: Start Frame Delimiter selector

0: Start Frame delimiter is COMMAND or DATA SYNC.

1: Start Frame delimiter is One Bit.

423

32015D–AVR32–10/07

AT32AP7001

25.8.3

USART Interrupt Enable Register

Name:

Access Type:

31

IER

Write-only

30

29

23

15

22

14

21

13

NACK

28

20

MANE

12

RXBUFF

7

PARE

6

FRAME

5

OVRE

4

ENDTX

• RXRDY: RXRDY Interrupt Enable

• TXRDY: TXRDY Interrupt Enable

• RXBRK: Receiver Break Interrupt Enable

• ENDRX: End of Receive Transfer Interrupt Enable

• ENDTX: End of Transmit Interrupt Enable

• OVRE: Overrun Error Interrupt Enable

• FRAME: Framing Error Interrupt Enable

• PARE: Parity Error Interrupt Enable

• TIMEOUT: Time-out Interrupt Enable

• TXEMPTY: TXEMPTY Interrupt Enable

• ITERATION: Iteration Interrupt Enable

• TXBUFE: Buffer Empty Interrupt Enable

• RXBUFF: Buffer Full Interrupt Enable

• NACK: Non Acknowledge Interrupt Enable

• CTSIC: Clear to Send Input Change Interrupt Enable

• MANE: Manchester Error Interrupt Enable

0: No effect.

1: Enables the corresponding interrupt.

27

19

CTSIC

11

TXBUFE

3

ENDRX

26

18

10

ITERATION

2

RXBRK

25

17

9

TXEMPTY

1

TXRDY

24

16

8

TIMEOUT

0

RXRDY

424

32015D–AVR32–10/07

AT32AP7001

25.8.4

USART Interrupt Disable Register

Name:

Access Type:

31

IDR

Write-only

30

29

23

15

22

14

21

13

NACK

28

20

MANE

12

RXBUFF

7

PARE

6

FRAME

5

OVRE

4

ENDTX

• RXRDY: RXRDY Interrupt Disable

• TXRDY: TXRDY Interrupt Disable

• RXBRK: Receiver Break Interrupt Disable

• ENDRX: End of Receive Transfer Interrupt Disable

• ENDTX: End of Transmit Interrupt Disable

• OVRE: Overrun Error Interrupt Disable

• FRAME: Framing Error Interrupt Disable

• PARE: Parity Error Interrupt Disable

• TIMEOUT: Time-out Interrupt Disable

• TXEMPTY: TXEMPTY Interrupt Disable

• ITERATION: Iteration Interrupt Disable

• TXBUFE: Buffer Empty Interrupt Disable

• RXBUFF: Buffer Full Interrupt Disable

• NACK: Non Acknowledge Interrupt Disable

• CTSIC: Clear to Send Input Change Interrupt Disable

• MANE: Manchester Error Interrupt Disable

0: No effect.

1: Disables the corresponding interrupt.

27

19

CTSIC

11

TXBUFE

3

ENDRX

26

18

10

ITERATION

2

RXBRK

25

17

9

TXEMPTY

1

TXRDY

24

16

8

TIMEOUT

0

RXRDY

425

32015D–AVR32–10/07

AT32AP7001

25.8.5

USART Interrupt Mask Register

Name:

Access Type:

31

IMR

Read-only

30

29

23

15

7

PARE

22

14

6

FRAME

21

13

NACK

5

OVRE

• RXRDY: RXRDY Interrupt Mask

• TXRDY: TXRDY Interrupt Mask

• RXBRK: Receiver Break Interrupt Mask

• ENDRX: End of Receive Transfer Interrupt Mask

• ENDTX: End of Transmit Interrupt Mask

• OVRE: Overrun Error Interrupt Mask

• FRAME: Framing Error Interrupt Mask

• PARE: Parity Error Interrupt Mask

• TIMEOUT: Time-out Interrupt Mask

• TXEMPTY: TXEMPTY Interrupt Mask

• ITERATION: Iteration Interrupt Mask

• TXBUFE: Buffer Empty Interrupt Mask

• RXBUFF: Buffer Full Interrupt Mask

• NACK: Non Acknowledge Interrupt Mask

• CTSIC: Clear to Send Input Change Interrupt Mask

• MANE: Manchester Error Interrupt Mask

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

28

20

MANE

12

RXBUFF

4

ENDTX

27

19

CTSIC

11

TXBUFE

3

ENDRX

26

18

10

ITERATION

2

RXBRK

25

17

9

TXEMPTY

1

TXRDY

24

16

8

TIMEOUT

0

RXRDY

426

32015D–AVR32–10/07

AT32AP7001

25.8.6

USART Channel Status Register

Name:

Access Type:

31

CSR

Read-only

30

29

23

CTS

15

7

PARE

22

14

6

FRAME

21

13

NACK

5

OVRE

28

20

12

RXBUFF

4

ENDTX

27

19

CTSIC

11

TXBUFE

3

ENDRX

26

18

10

ITERATION

2

RXBRK

25

17

9

TXEMPTY

1

TXRDY

24

MANERR

16

8

TIMEOUT

0

RXRDY

• RXRDY: Receiver Ready

0: No complete character has been received since the last read of RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.

1: At least one complete character has been received and RHR has not yet been read.

• TXRDY: Transmitter Ready

0: A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.

1: There is no character in the THR.

• RXBRK: Break Received/End of Break

0: No Break received or End of Break detected since the last RSTSTA.

1: Break Received or End of Break detected since the last RSTSTA.

• ENDRX: End of Receiver Transfer

0: The End of Transfer signal from the Receive PDC channel is inactive.

1: The End of Transfer signal from the Receive PDC channel is active.

• ENDTX: End of Transmitter Transfer

0: The End of Transfer signal from the Transmit PDC channel is inactive.

1: The End of Transfer signal from the Transmit PDC channel is active.

• OVRE: Overrun Error

0: No overrun error has occurred since the last RSTSTA.

1: At least one overrun error has occurred since the last RSTSTA.

• FRAME: Framing Error

0: No stop bit has been detected low since the last RSTSTA.

1: At least one stop bit has been detected low since the last RSTSTA.

• PARE: Parity Error

0: No parity error has been detected since the last RSTSTA.

427

32015D–AVR32–10/07

AT32AP7001

1: At least one parity error has been detected since the last RSTSTA.

• TIMEOUT: Receiver Time-out

0: There has not been a time-out since the last Start Time-out command or the Time-out Register is 0.

1: There has been a time-out since the last Start Time-out command.

• TXEMPTY: Transmitter Empty

0: There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled.

TXEMPTY == 1 means that the transmit shift register is empty and that there is no data in THR.

• ITERATION: Max number of Repetitions Reached

0: Maximum number of repetitions has not been reached since the last RSIT.

1: Maximum number of repetitions has been reached since the last RSIT.

• TXBUFE: Transmission Buffer Empty

0: The signal Buffer Empty from the Transmit PDC channel is inactive.

1: The signal Buffer Empty from the Transmit PDC channel is active.

• RXBUFF: Reception Buffer Full

0: The signal Buffer Full from the Receive PDC channel is inactive.

1: The signal Buffer Full from the Receive PDC channel is active.

• NACK: Non Acknowledge

0: No Non Acknowledge has not been detected since the last RSTNACK.

1: At least one Non Acknowledge has been detected since the last RSTNACK.

• CTSIC: Clear to Send Input Change Flag

0: No input change has been detected on the CTS pin since the last read of CSR.

1: At least one input change has been detected on the CTS pin since the last read of CSR.

• CTS: Image of CTS Input

0: CTS is at 0.

1: CTS is at 1.

• MANERR: Manchester Error

0: No Manchester error has been detected since the last RSTSTA.

1: At least one Manchester error has been detected since the last RSTSTA.

428

32015D–AVR32–10/07

AT32AP7001

25.8.7

USART Receive Holding Register

Name:

Access Type:

31

RHR

Read-only

30

29

23

15

RXSYNH

7

22

14

6

21

13

5

28

20

12

4

RXCHR

11

3

27

19

• RXCHR: Received Character

Last character received if RXRDY is set.

• RXSYNH: Received Sync

0: Last Character received is a Data.

1: Last Character received is a Command.

26

18

10

2

25

17

9

1

24

16

8

RXCHR

0

429

32015D–AVR32–10/07

AT32AP7001

25.8.8

USART Transmit Holding Register

Name:

Access Type:

31

THR

Write-only

30

29

23

15

TXSYNH

7

22

14

6

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

TXCHR

• TXCHR: Character to be Transmitted

Next character to be transmitted after the current character if TXRDY is not set.

• TXSYNH: Sync Field to be transmitted

0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.

1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.

25

17

9

1

24

16

8

TXCHR

0

430

32015D–AVR32–10/07

AT32AP7001

25.8.9

USART Baud Rate Generator Register

Name:

Access Type:

31

BRGR

Read/Write

30

29

28

23

15

22

14

21

13

20

12

27

19

11

26

18

10

CD

7 6 5 4 3 2

CD

• CD: Clock Divider

CD

0

1 to 65535

MODE

ISO7816

OVER = 0

Baud Rate =

Selected Clock/16/CD

SYNC = 0

SYNC = 1

OVER = 1

Baud Rate Clock Disabled

Baud Rate =

Selected Clock/8/CD

Baud Rate =

Selected Clock /CD

• FP: Fractional Part

0: Fractional divider is disabled.

1 - 7: Baudrate resolution, defined by FP x 1/8.

25

17

FP

9

1

MODE = ISO7816

Baud Rate = Selected

Clock/CD/FI_DI_RATIO

8

0

24

16

431

32015D–AVR32–10/07

AT32AP7001

25.8.10

USART Receiver Time-out Register

Name:

Access Type:

31

RTOR

Read/Write

30

29

23

15

22

14

21

13

28

20

12

27

19

11

TO

7 6 5 4 3 2

TO

• TO: Time-out Value

0: The Receiver Time-out is disabled.

1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.

26

18

10

25

17

9

1

24

16

8

0

432

32015D–AVR32–10/07

AT32AP7001

25.8.11

USART Transmitter Timeguard Register

Name:

Access Type:

31

TTGR

Read/Write

30

29

28

23

15

7

22

14

6

21

13

5

20

12

4

27

19

11

3

26

18

10

2

TG

• TG: Timeguard Value

0: The Transmitter Timeguard is disabled.

1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.

25

17

9

1

24

16

8

0

433

32015D–AVR32–10/07

AT32AP7001

25.8.12

USART FI DI RATIO Register

Name:

Access Type:

Reset Value :

31

FIDI

Read/Write

0x174

30

29

23

15

7

22

14

6

21

13

5

28

20

12

11

4

FI_DI_RATIO

3

27

19

26

18

10

2

25

17

9

FI_DI_RATIO

1

• FI_DI_RATIO: FI Over DI Ratio Value

0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.

1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.

24

16

8

0

434

32015D–AVR32–10/07

AT32AP7001

25.8.13

USART Number of Errors Register

Name:

Access Type:

31

NER

Read-only

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

NB_ERRORS

3

27

19

11

26

18

10

2

25

17

9

1

• NB_ERRORS: Number of Errors

Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.

24

16

8

0

435

32015D–AVR32–10/07

AT32AP7001

25.8.14

USART Manchester Configuration Register

Name:

Access Type:

31

MAN

Read/Write

30

DRIFT

29

28

RX_MPOL

23

15

7

22

14

6

21

13

5

20

12

TX_MPOL

4

• TX_PL: Transmitter Preamble Length

0: The Transmitter Preamble pattern generation is disabled

1 - 15: The Preamble Length is TX_PL x Bit Period

• TX_PP: Transmitter Preamble Pattern

11

3

27

19

10

2

26

18

RX_PL

TX_PL

9

1

1

1

0

0

TX_PP

0

1

0

1

Preamble Pattern default polarity assumed (TX_MPOL field not set)

ALL_ONE

ALL_ZERO

ZERO_ONE

ONE_ZERO

• TX_MPOL: Transmitter Manchester Polarity

0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.

1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.

• RX_PL: Receiver Preamble Length

0: The receiver preamble pattern detection is disabled

1 - 15: The detected preamble length is RX_PL x Bit Period

• RX_PP: Receiver Preamble Pattern detected

0

0

1

1

RX_PP

0

1

0

1

Preamble Pattern default polarity assumed (RX_MPOL field not set)

ALL_ONE

ALL_ZERO

ZERO_ONE

ONE_ZERO

• RX_MPOL: Receiver Manchester Polarity

0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.

25

RX_PP

24

17 16

TX_PP

8

0

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1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.

• DRIFT: Drift compensation

0: The USART can not recover from an important clock drift

1: The USART can recover from clock drift. The 16X clock mode must be enabled.

AT32AP7001

32015D–AVR32–10/07

437

AT32AP7001

25.8.15

USART IrDA FILTER Register

Name:

Access Type:

31

IF

Read/Write

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

IRDA_FILTER

3

27

19

11

26

18

10

2

25

17

9

1

• IRDA_FILTER: IrDA Filter

Sets the filter of the IrDA demodulator.

25.9

USART Version Register

Name:

US_VERSION

Access Type:

31

Read-only

30

29

23

15

7

22

14

6

21

13

5

28

20

12

4

VERSION

3

27

19

11

26

18

10

VERSION

9

2 1

25

17

MFN

24

16

8

0

• VERSION

Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell.

• MFN

Reserved. Value subject to change. No functionality associated.

24

16

8

0

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26. AC97 Controller (AC97C)

Rev: 2.1.0.0

26.1

Features

Compliant with AC97 2.2 Component Specification

2 independent communication channels

– Codec Channel, dedicated to the AC97 Analog Front End Control and Status Monitoring

– 2 channels associated with DMA Controller interface for Isochronous Audio Streaming

Transfer

Variable Sampling Rate AC97 Codec Interface Support

One Primary Codec Support

Independent input and Output Slot to Channel Assignment, Several Slots Can Be Assigned to the

Same Channel.

Channels Support Mono/Stereo/Multichannel Samples of 10, 16, 18 and 20 Bits.

26.2

Description

The AC97 Controller is the hardware implementation of the AC97 digital controller (DC’97) compliant with AC97 Component Specification 2.2. The AC97 Controller communicates with an audio codec (AC97) or a modem codec (MC’97) via the AC-link digital serial interface. All digital audio, modem and handset data streams, as well as control (command/status) informations are transferred in accordance to the AC-link protocol.

The AC97 Controller features a DMA Controller interface for audio streaming transfers. It also supports variable sampling rate and four Pulse Code Modulation (PCM) sample resolutions of

10, 16, 18 and 20 bits.

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26.3

Block Diagram

Figure 26-1. Functional Block Diagram

MCK Clock Domain

AC97 Tag Controller

AC97C Interrupt

AC97 CODEC Channel

AC97C_COTHR

AC97C_CORHR

AC97 Channel A

AC97C_CATHR

AC97C_CARHR

AC97 Channel B

AC97C_CBTHR

AC97C_CBRHR

MCK

User Interface

Slot Number

Slot #0

Slot #0,1

Slot #1,2

Slot #2

Transmit Shift Register

Receive Shift Register

AC97 Slot Controller

Slot Number

16/20 bits

M

U

X

Transmit Shift Register

Receive Shift Register

Slot #3...12

Transmit Shift Register

Receive Shift Register

Slot #3...12

Transmit Shift Register

Receive Shift Register

M

U

D

E

X

Bit Clock Domain

Peripheral Bus

SYNC

SDO

SDI

SCLK

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26.4

Pin Name List

Table 26-1.

I/O Lines Description

Pin Name Pin Description

SCLK

SDI

SYNC

SDO

12.288-MHz bit-rate clock (Referred as BITCLK in AC-link spec)

Receiver Data (Referred as SDATA_IN in AC-link spec)

48-KHz frame indicator and synchronizer

Transmitter Data (Referred as SDATA_OUT in AC-link spec)

The AC97 reset signal provided to the primary codec can be generated by a PIO.

26.5

Application Block Diagram

Figure 26-2. Application Block diagram

AC 97 Controller AC'97 Primary Codec AC-link

AC97_RESET

PIOx

AC97_SYNC

SYNC

AC97_BITCLK

SCLK

SDO

AC97_SDATA_OUT

AC97_SDATA_IN

SDI

Type

Input

Input

Output

Output

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26.6

Product Dependencies

26.6.1

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.

Before using the AC97 Controller receiver, the PIO controller must be configured in order for the

AC97C receiver I/O lines to be in AC97 Controller peripheral mode.

Before using the AC97 Controller transmitter, the PIO controller must be configured in order for the AC97C transmitter I/O lines to be in AC97 Controller peripheral mode.

26.6.2

26.6.3

Power Management

The AC97 clock is generated by the power manager. Before using the AC97, the programmer must ensure that the AC’97 clock is enabled in the power manager.

In the AC97 description, Master Clock (MCK) is the clock of the peripheral bus to which the

AC97 is connected. It is important that that the MCK clock frequency is higher than the SCLK

(Bit Clock) clock frequancy as signals that cross the two clock domains are re-synchronized.

Interrupt

The AC97 interface has an interrupt line connected to the interrupt controller. In order to handle interrupts, the interrupt controller must be programmed before configuring the AC97.

All AC97 Controller interrupts can be enabled/disabled by writing to the AC97 Controller Interrupt Enable/Disable Registers. Each pending and unmasked AC97 Controller interrupt will assert the interrupt line. The AC97 Controller interrupt service routine can get the interrupt source in two steps:

• Reading and ANDing AC97 Controller Interrupt Mask Register (IMR) and AC97 Controller

Status Register (SR).

• Reading AC97 Controller Channel x Status Register (CxSR).)

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26.7

Functional Description

26.7.1

Protocol overview

AC-link protocol is a bidirectional, fixed clock rate, serial digital stream. AC-link handles multiple input and output Pulse Code Modulation PCM audio streams, as well as control register accesses employing a Time Division Multiplexed (TDM) scheme that divides each audio frame in 12 outgoing and 12 incoming 20-bit wide data slots.

Figure 26-3. Bidirectional AC-link Frame with Slot Assignment

Slot #

0 1 2 3 4 5

AC97FS

6 7 8 9 10 11 12

AC97TX

(Controller Output)

TAG

CMD

ADDR

CMD

DATA

PCM

L Front

PCM

R Front

LINE 1

DAC

PCM

Center

PCM

L SURR

PCM

R SURR

PCM

LFE

LINE 2

DAC

HSET

DAC

IO

CTRL

AC97RX

(Codec output)

TAG

STATUS

ADDR

STATUS

DATA

PCM

LEFT

PCM

RIGHT

LINE 1

DAC

PCM

MIC

RSVED RSVED RSVED

LINE 2

ADC

HSET

ADC

IO

STATUS

Table 26-2.

AC-link Output Slots Transmitted from the AC97C Controller

Slot # Pin Description

10

11

12

0

1

2

3,4

5

6, 7, 8

9

TAG

Command Address Port

Command Data Port

PCM playback Left/Right Channel

Modem Line 1 Output Channel

PCM Center/Left Surround/Right Surround

PCM LFE DAC

Modem Line 2 Output Channel

Modem Handset Output Channel

Modem GPIO Control Channel

Table 26-3.

AC-link Input Slots Transmitted from the AC97C Controller

Slot # Pin Description

0

1

2

3,4

5

6

7, 8, 9

10

11

12

TAG

Status Address Port

Status Data Port

PCM playback Left/Right Channel

Modem Line 1 ADC

Dedicated Microphone ADC

Vendor Reserved

Modem Line 2 ADC

Modem Handset Input ADC

Modem IO Status

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26.7.2

26.7.2.1

Slot Description

Tag Slot

The tag slot, or slot 0, is a 16-bit wide slot that always goes at the beginning of an outgoing or incoming frame. Within tag slot, the first bit is a global bit that flags the entire frame validity. The next 12 bit positions sampled by the AC97 Controller indicate which of the corresponding 12 time slots contain valid data. The slot’s last two bits (combined) called Codec ID, are used to distinguish primary and secondary codec.

The 16-bit wide tag slot of the output frame is automatically generated by the AC97 Controller according to the transmit request of each channel and to the SLOTREQ from the previous input frame, sent by the AC97 Codec, in Variable Sample Rate mode.

26.7.2.2

Codec Slot 1

The command/status slot is a 20-bit wide slot used to control features, and monitors status for

AC97 Codec functions.

The control interface architecture supports up to sixty-four 16-bit wide read/write registers. Only the even registers are currently defined and addressed.

Slot 1’s bitmap is the following:

• Bit 19 is for read/write command, 1= read, 0 = write.

• Bits [18:12] are for control register index.

• Bits [11:0] are reserved.

26.7.2.3

26.7.2.4

Codec Slot 2

Slot 2 is a 20-bit wide slot used to carry 16-bit wide AC97 Codec control register data. If the current command port operation is a read, the entire slot time is stuffed with zeros. Its bitmap is the following:

• Bits [19:4] are the control register data

• Bits [3:0] are reserved and stuffed with zeros.

Data Slots [3:12]

Slots [3:12] are 20-bit wide data slots, they usually carry audio PCM or/and modem I/O data.

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26.7.3

AC97 Controller Channel Organization

The AC97 Controller features a Codec channel and 2 logical channels; Channel A and Channel

B.

The Codec channel controls AC97 Codec registers, it enables write and read configuration values in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot

1 and slot 2 exclusively, in both input and output directions.

Channel A and Channel B transfer data to/from AC97 codec. All audio samples and modem data must transit by these two channels.

Each slot of the input or the output frame that belongs to this range [3 to 12] can be operated by either Channel A or Channel B. The slot to channel assignment is configured by two registers:

• AC97 Controller Input Channel Assignment Register (ICA)

• AC97 Controller Output Channel Assignment Register (OCA)

The AC97 Controller Input Channel Assignment Register (ICA) configures the input slot to channel assignment. The AC97 Controller Output Channel Assignment Register (OCA) configures the output slot to channel assignment.

A slot can be left unassigned to a channel by the AC97 Controller. Slots 0, 1,and 2 cannot be assigned to Channel A or to Channel B through the OCA and ICA Registers.

The width of sample data, that transit via Channel A and Channel B varies and can take one of these values; 10, 16, 18 or 20 bits.

Figure 26-4. Logical Channel Assignment

Slot # 0 1 2 3

AC97FS

4 5 6 7 8 9 10 11 12

AC97TX

(Controller Output)

TAG

CMD

ADDR

CMD

DATA

PCM

L Front

PCM

R Front

LINE 1

DAC

PCM

Center

PCM

L SURR

PCM

R SURR

PCM

LFE

LINE 2

DAC

HSET

DAC

IO

CTRL

Codec Channel

AC97C_OCA = 0x0000_0209

Channel A

AC97RX

(Codec output)

TAG

STATUS

ADDR

STATUS

DATA

PCM

LEFT

PCM

RIGHT

LINE 1

DAC

PCM

MIC

RSVED RSVED RSVED

LINE 2

ADC

HSET

ADC

IO

STATUS

Codec Channel

AC97C_ICA = 0x0000_0009

Channel A

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26.7.3.1

26.7.3.2

AC97 Controller Setup

The following operations must be performed in order to bring the AC97 Controller into an operating state:

1.

Enable the AC97 Controller clock in the power manager.

2.

Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register (MR).

3.

Configure the input channel assignment by controlling the AC97 Controller Input

Assignment Register (ICA).

4.

Configure the output channel assignment by controlling the AC97 Controller Input

Assignment Register (OCA).

5.

Configure sample width for Channel A and Channel B by writing the SIZE bit field in

AC97C Channel A Mode Register (CAMR) and AC97C Channel B Mode Register

(CBMR). The application can write 10, 16, 18,or 20-bit wide PCM samples through the

AC97 interface and they will be transferred into 20-bit wide slots.

6.

Configure data Endianness for Channel A and Channel B by writing CEM bit field in

CAMR and CBMR registers. Data on the AC-link are shifted MSB first. The application can write little- or big-endian data to the AC97 Controller interface.

7.

Configure the PIO controller to drive the RESET signal of the external Codec. The

RESET signal must fulfill external AC97 Codec timing requirements.

8.

Enable Channel A and/or Channel B by writing CEN bit field in CAMR and CBMR registers.

Transmit Operation

The application must perform the following steps in order to send data via a channel to the AC97

Codec:

• Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x Status

Register (CxSR). x being one of the 2 channels.

• Write data to the AC97 Controller Channel x Transmit Holding Register (CxTHR).

Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automatically set by the AC97 Controller which allows the application to start a new write action. The application can also wait for an interrupt notice associated with TXRDY in order to send data. The interrupt remains active until TXRDY flag is cleared..

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Figure 26-5. Audio Transfer (PCM L Front, PCM R Front) on Channel x

Slot # 0 1 2 3 4 5 6 7

AC97FS

AC97TX

(Controller Output)

TAG

CMD

ADDR

CMD

DATA

PCM

L Front

PCM

R Front

LINE 1

DAC

8 9

PCM

Center

PCM

L SURR

PCM

R SURR

PCM

LFE

TXRDYCx

(AC97C_SR)

TXEMPTY

(AC97C_SR)

Write access to

AC97C_THRx

26.7.3.3

10 11 12

LINE 2

DAC

HSET

DAC

IO

CTRL

PCM L Front transfered to the shift register

PCM R Front transfered to the shift register

The TXEMPTY flag in the AC97 Controller Channel x Status Register (CxSR) is set when all requested transmissions for a channel have been shifted on the AC-link. The application can either poll TXEMPTY flag in CxSR or wait for an interrupt notice associated with the same flag.

In most cases, the AC97 Controller is embedded in chips that target audio player devices. In such cases, the AC97 Controller is exposed to heavy audio transfers. Using the polling technique increases processor overhead and may fail to keep the required pace under an operating system.

In order to avoid these polling drawbacks, the application can perform audio streams by using a

DMA controller (DMAC) connected to both channels, which reduces processor overhead and increases performance especially under an operating system.

The DMAC transmit counter values must be equal to the number of PCM samples to be transmitted, each sample goes in one slot.

AC97 Output Frame

The AC97 Controller outputs a thirteen-slot frame on the AC-Link. The first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. Slots 1 and 2 are used if the application performs control and status monitoring actions on AC97 Codec control/status registers. Slots [3:12] are used according to the content of the

AC97 Controller Output Channel Assignment Register (OCA). If the application performs many transmit requests on a channel, some of the slots associated to this channel or all of them will carry valid data.

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26.7.3.4

Receive Operation

The AC97 Controller can also receive data from AC97 Codec. Data is received in the channel’s shift register and then transferred to the AC97 Controller Channel x Read Holding Register. To read the newly received data, the application must perform the following steps:

• Poll RXRDY flag in AC97 Controller Channel x Status Register (CxSR). x being one of the 2 channels.

• Read data from AC97 Controller Channel x Read Holding Register.

The application can also wait for an interrupt notice in order to read data from CxRHR. The interrupt remains active until RXRDY is cleared by reading CxSR.

The RXRDY flag in CxSR is set automatically when data is received in the Channel x shift register. Data is then shifted to CxRHR.

Figure 26-6. Audio Transfer (PCM L Front, PCM R Front) on Channel x

Slot # 0 1 2 3 4 5 6 7

AC97FS

TAG

STATUS

ADDR

STATUS

DATA

PCM

LEFT

PCM

RIGHT

LINE 1

DAC

8 9 10 11 12

HSET

ADC

IO

STATUS

AC97RX

(Codec output)

RXRDYCx

(AC97C_SR)

Read access to

AC97C_RHRx

PCM

MIC

RSVED RSVED RSVED

LINE 2

ADC

If the previously received data has not been read by the application, the new data overwrites the data already waiting in CxRHR, therefore the OVRUN flag in CxSR is raised. The application can either poll the OVRUN flag in CxSR or wait for an interrupt notice. The interrupt remains active until the OVRUN flag in CxSR is set.

The AC97 Controller can also be used in sound recording devices in association with an AC97

Codec. The AC97 Controller may also be exposed to heavy PCM transfers.

The application can use the DMAC connected to both channels in order to reduce processor overhead and increase performance especially under an operating system.

The DMAC receive counter values must be equal to the number of PCM samples to be received.

When more than one timeslot is assigned to a channel using DMA, the different timeslot samples will be interleaved.

26.7.3.5

AC97 Input Frame

The AC97 Controller receives a thirteen slot frame on the AC-Link sent by the AC97 Codec. The first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. Slots 1 and 2 are used if the application requires status informations from AC97 Codec. Slots [3:12] are used according to AC97 Controller Output

Channel Assignment Register (ICA) content. The AC97 Controller will not receive any data from any slot if ICA is not assigned to a channel in input.

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26.7.3.6

Configuring and Using Interrupts

Instead of polling flags in AC97 Controller Global Status Register (SR) and in AC97 Controller

Channel x Status Register (CxSR), the application can wait for an interrupt notice. The following steps show how to configure and use interrupts correctly:

• Set the interruptible flag in AC97 Controller Channel x Mode Register (CxMR).

• Set the interruptible event and channel event in AC97 Controller Interrupt Enable Register

(IER).

The interrupt handler must read both AC97 Controller Global Status Register (SR) and AC97

Controller Interrupt Mask Register (IMR) and AND them to get the real interrupt source. Furthermore, to get which event was activated, the interrupt handler has to read AC97 Controller

Channel x Status Register (CxSR), x being the channel whose event triggers the interrupt.

The application can disable event interrupts by writing in AC97 Controller Interrupt Disable Register (IDR). The AC97 Controller Interrupt Mask Register (IMR) shows which event can trigger an interrupt and which one cannot.

26.7.3.7

Endianness

Endianness can be managed automatically for each channel, except for the Codec channel, by writing to Channel Endianness Mode (CEM) in CxMR. This enables transferring data on AC-link in Little Endian format without any additional operation.

26.7.3.8

31

To Transmit a Word Stored in Little Endian Format on AC-link

Word to be written in AC97 Controller Channel x Transmit Holding Register (CxTHR) (as it is stored in memory or microprocessor register).

24 23 16 15 8 7 0

Byte3[7:0] Byte2[7:0] Byte1[7:0] Byte0[7:0]

31

Word stored in Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit)

.

24 23

20 19

Byte1[3:0]

16 15

Byte2[7:0]

8 7

Byte3[7:0]

0

26.7.3.9

31

31

Data transmitted on appropriate slot: data[19:0] = {Byte1[3:0], Byte2[7:0], Byte3[7:0]}.

To Transmit A Halfword Stored in Little Endian Format on AC-link

Halfword to be written in AC97 Controller Channel x Transmit Holding Register (CxTHR).

24 23 16 15 8 7

– – Byte0[7:0] Byte1[7:0]

0

Halfword stored in AC97 Controller Channel x Transmit Holding Register (CxTHR) (data to transmit).

24 23 16 15 8 7 0

– Byte1[7:0] Byte0[7:0]

Data emitted on related slot: data[19:0] = {Byte1[7:0], Byte0[7:0], 0x0}.

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26.7.3.10

31

31

To Transmit a10-bit Sample Stored in Little Endian Format on AC-link

Halfword to be written in AC97 Controller Channel x Transmit Holding Register (CxTHR).

24 23 16 15 8 7

– – Byte0[7:0] {0x00, Byte1[1:0]}

0

Halfword stored in AC97 Controller Channel x Transmit Holding Register (CxTHR) (data to transmit).

24 23 16 15 0

– –

10 9 8 7

Byte1

[1:0]

Byte0[7:0]

Data emitted on related slot: data[19:0] = {Byte1[1:0], Byte0[7:0], 0x000}.

26.7.3.11

31

To Receive Word transfers

Data received on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}.

Word stored in AC97 Controller Channel x Receive Holding Register (CxRHR) (Received Data)

.

24 23

20 19

Byte2[3:0]

16 15

Byte1[7:0]

8 7

Byte0[7:0]

0

31

26.7.3.12

31

Byte0[7:0]

Data is read from AC97 Controller Channel x Receive Holding Register (CxRHR) when Channel x data size is greater than 16 bits and when little endian mode is enabled (data written to memory).

24 23 16 15 8 7 0

Byte1[7:0] {0x0, Byte2[3:0]} 0x00

To Receive Halfword Transfers

Data received on appropriate slot: data[19:0] = {Byte1[7:0], Byte0[7:0], 0x0 }.

Halfword stored in AC97 Controller Channel x Receive Holding Register (CxRHR) (Received

Data).

24 23 16 15 8 7 0

– – Byte1[7:0] Byte0[7:0]

31

Data is read from AC97 Controller Channel x Receive Holding Register (CxRHR) when data size is equal to 16 bits and when little endian mode is enabled.

24 23 16 15 8 7 0

– Byte0[7:0] Byte1[7:0]

26.7.3.13

To Receive 10-bit Samples

Data received on appropriate slot: data[19:0] = {Byte1[1:0], Byte0[7:0], 0x000}. Halfword stored in AC97 Controller Channel x Receive Holding Register (CxRHR) (Received Data)

31 24 23 16 15 0

– – –

10 9 8 7

Byte1

[1:0]

Byte0[7:0]

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31

26.7.4

Data read from AC97 Controller Channel x Receive Holding Register (CxRHR) when data size is equal to 10 bits and when little endian mode is enabled.

24 23 16 15 8 7

– Byte0[7:0] 0x00

3 1 0

Byte1

[1:0]

Variable Sample Rate

The problem of variable sample rate can be summarized by a simple example. When passing a

44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. The new AC97 standard approach calls for the addition of “on-demand” slot request flags. The AC97 Codec examines its sample rate control register, the state of its FIFOs, and the incoming SDATA_OUT tag bits (slot 0) of each output frame and then determines which SLOTREQ bits to set active (low). These bits are passed from the AC97

Codec to the AC97 Controller in slot 1/SLOTREQ in every audio input frame. Each time the

AC97 controller sees one or more of the newly defined slot request flags set active (low) in a given audio input frame, it must pass along the next PCM sample for the corresponding slot(s) in the AC-link output frame that immediately follows.

The variable Sample Rate mode is enabled by performing the following steps:

• Setting the VRA bit in the AC97 Controller Mode Register (MR).

• Enable Variable Rate mode in the AC97 Codec by performing a transfer on the Codec channel.

Slot 1 of the input frame is automatically interpreted as SLOTREQ signaling bits. The AC97 Controller will automatically fill the active slots according to both SLOTREQ and OCA register in the next transmitted frame.

26.7.5

26.7.5.1

Power Management

Powering Down the AC-Link

The AC97 Codecs can be placed in low power mode. The application can bring AC97 Codec to a power down state by performing sequential writes to AC97 Codec powerdown register . Both the bit clock (clock delivered by AC97 Codec, SCLK) and the input line (SDI) are held at a logic low voltage level. This puts AC97 Codec in power down state while all its registers are still holding current values. Without the bit clock, the AC-link is completely in a power down state.

The AC97 Controller should not attempt to play or capture audio data until it has awakened

AC97 Codec.

To set the AC97 Codec in low power mode, the PR4 bit in the AC97 Codec powerdown register

(Codec address 0x26) must be set to 1. Then the primary Codec drives both BITCLK and SDI to a low logic voltage level.

The following operations must be done to put AC97 Codec in low power mode:

• Disable Channel A clearing CEN in the CAMR register.

• Disable Channel B clearing CEN field in the CBMR register.

• Write 0x2680 value in the COTHR register.

• Poll the TXEMPTY flag in CxSR registers for the 2 channels.

At this point AC97 Codec is in low power mode.

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26.7.5.2

26.7.5.3

26.7.5.4

Waking up the AC-link

There are two methods to bring the AC-link out of low power mode. Regardless of the method, it is always the AC97 Controller that performs the wake-up.

Wake-up Tiggered by the AC97 Controller

The AC97 Controller can wake up the AC97 Codec by issuing either a cold or a warm reset.

The AC97 Controller can also wake up the AC97 Codec by asserting SYNC signal, however this action should not be performed for a minimum period of four audio frames following the frame in which the powerdown was issued.

Wake-up Triggered by the AC97 Codec

This feature is implemented in AC97 modem codecs that need to report events such as Caller-

ID and wake-up on ring.

The AC97 Codec can drive SDI signal from low to high level and holding it high until the controller issues either a cold or a warm reset. The SDI rising edge is asynchronously (regarding

SYNC) detected by the AC97 Controller. If WKUP bit is enabled in IMR register, an interrupt is triggered that wakes up the AC97 Controller which should then immediately issue a cold or a warm reset.

If the processor needs to be awakened by an external event, the SDI signal must be externally connected to the WAKEUP entry of the system controller.

Figure 26-7. AC97 Power-Down/Up Sequence

Power Down Frame

Sleep State

Wake Event

Warm Reset

New Audio Frame

AC97CK

AC97FS

AC97TX

AC97RX

TAG

Write to

0x26

Data

PR4

TAG

Write to

0x26

Data

PR4

TAG Slot1 Slot2

TAG Slot1 Slot2

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26.7.5.5

26.7.5.6

26.7.5.7

AC97 Codec Reset

There are three ways to reset an AC97 Codec.

Cold AC97 Reset

A cold reset is generated by asserting the RESET signal low for the minimum specified time

(depending on the AC97 Codec) and then by de-asserting RESET high. BITCLK and SYNC is reactivated and all AC97 Codec registers are set to their default power-on values. Transfers on

AC-link can resume.

The RESET signal will be controlled via a PIO line. This is how an application should perform a cold reset:

• Clear and set ENA flag in the MR register to reset the AC97 Controller

• Clear PIO line output controlling the AC97 RESET signal

• Wait for the minimum specified time

• Set PIO line output controlling the AC97 RESET signal

BITCLK, the clock provided by AC97 Codec, is detected by the controller.

Warm AC97 Reset

A warm reset reactivates the AC-link without altering AC97 Codec registers. A warm reset is signaled by driving AC97FX signal high for a minimum of 1us in the absence of BITCLK. In the absence of BITCLK, AC97FX is treated as an asynchronous (regarding AC97FX) input used to signal a warm reset to AC97 Codec.

This is the right way to perform a warm reset:

• Set WRST in the MR register.

• Wait for at least 1us

• Clear WRST in the MR register.

The application can check that operations have resumed by checking SOF flag in the SR register or wait for an interrupt notice if SOF is enabled in IMR.

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26.8

AC97 Controller (AC97C) User Interface

Table 26-4.

Register Mapping

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

0x40

Offset

0x0-0x4

0x8

0xC

0x10

0x14

0x18-0x1C

0x20

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x60-0xFB

Register

Reserved

Mode Register

Reserved

Input Channel Assignment Register

Output Channel Assignment Register

Reserved

Channel A Receive Holding Register

Channel A Transmit Holding Register

Channel A Status Register

Channel A Mode Register

Channel B Receive Holding Register

Channel B Transmit Holding Register

Channel B Status Register

Channel B Mode Register

Codec Receive Holding Register

Codec Transmit Holding Register

Codec Status Register

Codec Mode Register

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Reserved

Register Name

MR

ICA

OCA

CARHR

CATHR

CASR

CAMR

CBRHR

CBTHR

CBSR

CBMR

CORHR

COTHR

COSR

COMR

SR

IER

IDR

IMR

0x0

0x0

0x0

0x0

0x0

0x0

Reset

0x0

0x0

0x0

0x0

0x0

0x0

0x0

0x0

Access

Read/Write

Read/Write

Read/Write

Read

Write

Read

Read/Write

Read

Write

Read

Read/Write

Read

Write

Read

Read/Write

Read

Write

Write

Read

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26.8.1

AC97 Controller Mode Register

Name:

Access Type:

MR

Read-Write

15

7

31

23

14

6

30

22

13

5

29

21

12

4

28

20

11

3

27

19

26

18

10

2

VRA

• VRA: Variable Rate (for Data Slots 3-12)

0: Variable Rate is inactive. (48 KHz only)

1: Variable Rate is active.

• WRST: Warm Reset

0: Warm Reset is inactive.

1: Warm Reset is active.

• ENA: AC97 Controller Global Enable

0: No effect. AC97 function as well as access to other AC97 Controller registers are disabled.

1: Activates the AC97 function.

25

17

1

9

WRST

24

16

0

8

ENA

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26.8.2

AC97 Controller Input Channel Assignment Register

Register Name:

Access Type:

ICA

Read/Write

31

23

30

22

CHID10

14

29

21

28

CHID12

20

12 15

CHID8

7

CHID5

6

13

CHID7

5 4

CHID4

27

19

CHID9

11

3

• CHIDx: Channel ID

for the input slot x

CHIDx

0x0

0x1

0x2

Selected Receive Channel

None. No data will be received during this Slot x

Channel A data will be received during this slot time.

Channel B data will be received during this slot time

26

18

10

CHID6

2

25

CHID11

17

CHID8

9

1

CHID3

24

16

8

CHID5

0

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AT32AP7001

26.8.3

AC97 Controller Output Channel Assignment Register

Register Name:

Access Type:

OCA

Read/Write

31

23

30

22

CHID10

14

29

21

28

CHID12

20

12

27

19

CHID9

11 15

CHID8

7

CHID5

6

13

CHID7

5 4

CHID4

3

• CHIDx: Channel ID

for the output slot x

CHIDx

0x0

0x1

0x2

Selected Transmit Channel

None. No data will be transmitted during this Slot x

Channel A data will be transferred during this slot time.

Channel B data will be transferred during this slot time

26

18

10

CHID6

2

25

CHID11

17

CHID8

9

1

CHID3

24

16

8

CHID5

0

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26.8.4

AC97 Controller Codec Channel Receive Holding Register

Register Name:

Access Type:

CORHR

Read-only

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

SDATA

7 6 5 4 3

SDATA

• SDATA: Status Data

Data sent by the CODEC in the third AC97 input frame slot (Slot 2).

26

18

10

2

25

17

9

1

24

16

8

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26.8.5

AC97 Controller Codec Channel Transmit Holding Register

Register Name:

Access Type:

COTHR

Write-only

31

23

READ

15

30

22

14

29

21

13

28

20

12

27

19

CADDR

11

CDATA

7 6 5 4 3

CDATA

• READ: Read/Write command

0: Write operation to the CODEC register indexed by the CADDR address.

1: Read operation to the CODEC register indexed by the CADDR address.

This flag is sent during the second AC97 frame slot

• CADDR: CODEC control register index

Data sent to the CODEC in the second AC97 frame slot.

• CDATA: Command Data

Data sent to the CODEC in the third AC97 frame slot (Slot 2).

10

2

26

18

9

1

25

17

8

0

24

16

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26.8.6

AC97 Controller Channel A, Channel B Receive Holding Register

Register Name:

Access Type:

CARHR, CBRHR

Read-only

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

RDATA

7 6 5 4 3

RDATA

26

18

10

2

RDATA

25

17

9

1

• RDATA: Receive Data

Received Data on channel x.

8

0

24

16

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AT32AP7001

26.8.7

AC97 Controller Channel A, channel B Transmit Holding Register

Register Name:

Access Type:

CATHR, CBTHR

Write-only

31

23

15

30

22

14

29

21

13

28

20

12

27

19

11

TDATA

7 6 5 4 3

TDATA

26

18

10

2

TDATA

25

17

9

1

• TDATA: Transmit Data

Data to be sent on channel x.

8

0

24

16

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26.8.8

AC97 Controller Channel A Status Register

Register Name:

Access Type:

CASR

Read-only

15

7

31

23

14

6

30

22

29

21

13

5

OVRUN

28

20

12

4

RXRDY

11

3

27

19

26

18

10

2

UNRUN

25

17

1

9

TXEMPTY

24

16

0

8

TXRDY

26.8.9

AC97 Controller Channel B Status Register

Register Name:

Access Type:

CBSR

Read-only

15

7

31

23

14

6

30

22

29

21

13

5

OVRUN

28

20

12

4

RXRDY

11

3

27

19

26

18

10

2

UNRUN

25

17

1

9

TXEMPTY

24

16

0

8

TXRDY

26.8.10

AC97 Controller Codec Channel Status Register

Register Name:

Access Type:

COSR

Read-only

15

7

31

23

14

6

30

22

29

21

13

5

OVRUN

28

20

12

4

RXRDY

11

3

27

19

10

2

-

26

18

25

17

1

9

TXEMPTY

24

16

0

8

TXRDY

• TXRDY: Channel Transmit Ready

0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register.

1: Channel Transmit Register is empty.

• TXEMPTY: Channel Transmit Empty

0: Data remains in the Channel Transmit Register or is currently transmitted from the Channel Transmit Shift Register.

1: Data in the Channel Transmit Register have been loaded in the Channel Transmit Shift Register and sent to the codec.

• RXRDY: Channel Receive Ready

0: Channel Receive Holding Register is empty.

1: Data has been received and loaded in Channel Receive Holding Register.

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• OVRUN: Receive Overrun

Automatically cleared by a processor read operation.

0: No data has been loaded in the Channel Receive Holding Register while previous data has not been read since the last read of the Status Register.

1: Data has been loaded in the Channel Receive Holding Register while previous data has not yet been read since the last read of the Status Register.

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26.8.11

AC97 Controller Channel A Mode Register

Register Name:

Access Type:

CAMR

Read/Write

15

7

31

23

30

22

DMAEN

14

6

29

21

CEN

13

5

OVRUN

28

20

12

4

RXRDY

11

3

27

19

26

18

CEM

10

2

UNRUN

25

17

9

1

TXEMPTY

SIZE

24

16

8

0

TXRDY

• DMAEN: DMA Enable

0: Disable DMA transfers for this channel.

1: Enable DMA transfers for this channel using DMAC.

• CEM: Channel A Endian Mode

0: Transferring Data through Channel A is straight forward (Big Endian).

1: Transferring Data through Channel A from/to a memory is performed with from/to Little Endian format translation.

• SIZE: Channel A Data Size

SIZE Encoding

SIZE

0x0

0x1

0x2

0x3

Selected Channel

20 bits

18bits

16 bits

10 bits

Note: Each time slot in the data phase is 20 bit long. For example, if a 16-bit sample stream is being played to an AC 97 DAC, the first

16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the AC97 Controller fills with zeroes. This process ensures that the least significant bits do not introduce any DC biasing, regardless of the implemented DAC’s resolution (16-, 18-, or 20-bit).

• CEN: Channel A Enable

0: Data transfer is disabled on Channel A.

1: Data transfer is enabled on Channel A.

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26.8.12

AC97 Controller Channel B Mode Register

Register Name:

Access Type:

CBMR

Read/Write

15

7

31

23

30

22

DMAEN

14

6

29

21

CEN

13

5

OVRUN

28

20

12

4

RXRDY

11

3

27

19

26

18

CEM

10

2

UNRUN

25

17

9

1

TXEMPTY

SIZE

24

16

8

0

TXRDY

• DMAEN: DMA Enable

0: Disable DMA transfers for this channel.

1: Enable DMA transfers for this channel using DMAC.

• CEM: Channel B Endian Mode

0: Transferring Data through Channel B is straight forward (Big Endian).

1: Transferring Data through Channel B from/to a memory is performed with from/to Little Endian format translation.

• SIZE: Channel B Data Size

SIZE Encoding

SIZE

0x0

0x1

0x2

0x3

Selected Channel

20 bits

18bits

16 bits

10 bits

Note: Each time slot in the data phase is 20 bit long. For example, if a 16-bit sample stream is being played to an AC 97 DAC, the first

16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the AC97 Controller fills with zeroes. This process ensures that the least significant bits do not introduce any DC biasing, regardless of the implemented DAC’s resolution (16-, 18-, or 20-bit).

• CEN: Channel B Enable

0: Data transfer is disabled on Channel B.

1: Data transfer is enabled on Channel B.

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26.8.13

AC97 Controller Codec Channel Mode Register

Register Name:

Access Type:

COMR

Read/Write

15

7

31

23

14

6

30

22

29

21

13

5

OVRUN

28

20

12

4

RXRDY

11

3

27

19

10

2

-

26

18

• TXRDY: Channel Transmit Ready Interrupt Enable

• TXEMPTY: Channel Transmit Empty Interrupt Enable

• RXRDY: Channel Receive Ready Interrupt Enable

• OVRUN: Receive Overrun Interrupt Enable

0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.

1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.

25

17

1

9

TXEMPTY

24

16

0

8

TXRDY

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26.8.14

AC97 Controller Status Register

Register Name:

Access Type:

SR

Read-only

15

7

31

23

14

6

30

22

13

5

29

21

28

20

12

4

CBEVT

27

19

11

3

CAEVT

26

18

10

2

COEVT

25

17

1

9

WKUP

24

16

0

8

SOF

WKUP and SOF flags in SR register are automatically cleared by a processor read operation.

• SOF: Start Of Frame

0: No Start of Frame has been detected since the last read of the Status Register.

1: At least one Start of frame has been detected since the last read of the Status Register.

• WKUP: Wake Up detection

0: No Wake-up has been detected.

1: At least one rising edge on SDATA_IN has been asynchronously detected. That means AC97 Codec has notified a wake-up.

• COEVT: CODEC Channel Event

A Codec channel event occurs when COSR AND COMR is not 0. COEVT flag is automatically cleared when the channel event condition is cleared.

0: No event on the CODEC channel has been detected since the last read of the Status Register.

1: At least one event on the CODEC channel is active.

• CAEVT: Channel A Event

A channel A event occurs when CASR AND CAMR is not 0. CAEVT flag is automatically cleared when the channel event condition is cleared.

0: No event on the channel A has been detected since the last read of the Status Register.

1: At least one event on the channel A is active.

• CBEVT: Channel B Event

A channel B event occurs when CBSR AND CBMR is not 0. CBEVT flag is automatically cleared when the channel event condition is cleared.

0: No event on the channel B has been detected since the last read of the Status Register.

1: At least one event on the channel B is active.

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26.8.15

AC97 Controller Interrupt Enable Register

Register Name:

Access Type:

IER

Write-only

15

7

31

23

14

6

30

22

13

5

29

21

28

20

12

4

CBEVT

• SOF: Start Of Frame

• WKUP: Wake Up

• COEVT: Codec Event

• CAEVT: Channel A Event

• CBEVT: Channel B Event

0: No Effect.

1: Enables the corresponding interrupt.

27

19

11

3

CAEVT

26

18

10

2

COEVT

25

17

1

9

WKUP

24

16

0

8

SOF

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32015D–AVR32–10/07

AT32AP7001

26.8.16

AC97 Controller Interrupt Disable Register

Register Name:

Access Type:

IDR

Write-only

15

7

31

23

14

6

30

22

13

5

29

21

28

20

12

4

CBEVT

• SOF: Start Of Frame

• WKUP: Wake Up

• COEVT: Codec Event

• CAEVT: Channel A Event

• CBEVT: Channel B Event

0: No Effect.

1: Disables the corresponding interrupt.

27

19

11

3

CAEVT

26

18

10

2

COEVT

25

17

1

9

WKUP

24

16

0

8

SOF

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26.8.17

AC97 Controller Interrupt Mask Register

Register Name:

Access Type:

IMR

Read-only

15

7

31

23

14

6

30

22

13

5

29

21

28

20

12

4

CBEVT

• SOF: Start Of Frame

• WKUP: Wake Up

• COEVT: Codec Event

• CAEVT: Channel A Event

• CBEVT: Channel B Event

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

27

19

11

3

CAEVT

26

18

10

2

COEVT

25

17

1

9

WKUP

24

16

0

8

SOF

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27. Audio Bitstream DAC (ABDAC)

Rev: 1.0.1.1

27.1

Features

Digital Stereo DAC

Oversampled D/A conversion architecture

– Oversampling ratio fixed 128x

– FIR equalization filter

– Digital interpolation filter: Comb4

– 3rd Order Sigma-Delta D/A converters

Digital bitstream outputs

Parallel interface

Connected to DMA Controller for background transfer without CPU intervention

27.2

Description

The Audio Bitstream DAC converts a 16-bit sample value to a digital bitstream with an average value proportional to the sample value. Two channels are supported, making the Audio Bitstream DAC particularly suitable for stereo audio. Each channel has a pair of complementary digital outputs, DACn and DACn_N, which can be connected to an external high input impedance amplifier.

The Audio Bitstream DAC is compromised of two 3rd order Sigma Delta D/A converter with an oversampling ratio of 128. The samples are upsampled with a 4th order Sinc interpolation filter

(Comb4) before being input to the Sigmal Delta Modulator. In order to compensate for the pass band frequency response of the interpolation filter and flatten the overall frequency response, the input to the interpolation filter is first filtered with a simple 3-tap FIR filter.The total frequency response of the Equalization FIR filter and the interpolation filter is given in

Figure 27-2 on page

483 . The digital output bitstreams from the Sigma Delta Modulators should be low-pass filtered

to remove high frequency noise inserted by the Modulation process.

The output DACn and DACn_N should be as ideal as possible before filtering, to achieve the best SNR quality. The output can be connected to a class D amplifier output stage, or it can be low pass filtered and connected to a high input impedance amplifier. A simple 1st order or higher low pass filter that filters all the frequencies above 50 kHz should be adequate.

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27.3

Block Diagram

Figure 27-1. Functional Block Diagram

clk sample_clk din1[15:0] din2[15:0]

Audio Bitstream DAC

Clock Generator

Equalization FIR

Equalization FIR

COMB

(INT=128)

COMB

(INT=128) bit_clk

Sigma-Delta

DA-MOD

Sigma-Delta

DA-MOD bit_out1 bit_out2

27.4

Pin Name List

Table 27-1.

I/O Lines Description

Pin Name

DATA0

Pin Description

Output from Audio Bitstream DAC Channel 0

DATA1

DATAN0

DATAN1

Output from Audio Bitstream DAC Channel 1

Inverted output from Audio Bitstream DAC Channel 0

Inverted output from Audio Bitstream DAC Channel 1

Type

Output

Output

Output

Output

27.5

Product Dependencies

27.5.1

I/O Lines

The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed with PIO lines.

Before using the Audio Bitstream DAC, the PIO controller must be configured in order for the

Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode.

27.5.2

Power Management

The PB-bus clock to the Audio Bitstream DAC is generated by the power manager. Before using the Audio Bitstream DAC, the programmer must ensure that the Audio Bitstream DAC clock is enabled in the power manager.

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27.5.3

27.5.4

Clock Management

The Audio Bitstream DAC needs a separate clock for the D/A conversion operation. This clock should be set up in the generic clock register in the power manager. The frequency of this clock must be 256 times the frequency of the desired samplerate (f s

). For f s

=48kHz this means that the clock must have a frequency of 12.288MHz.

Interrupts

The Audio Bitstream DAC interface has an interrupt line connected to the interrupt controller. In order to handle interrupts, the interrupt controller must be programmed before configuring the

Audio Bitstream DAC.

All Audio Bitstream DAC interrupts can be enabled/disabled by writing to the Audio Bitstream

DAC Interrupt Enable/Disable Registers. Each pending and unmasked Audio Bitstream DAC interrupt will assert the interrupt line. The Audio Bitstream DAC interrupt service routine can get the interrupt source by reading the Interrupt Status Register.

DMA 27.5.5

The Audio Bitstream DAC is connected to the DMA controller. The DMA controller can be programmed to automatically transfer samples to the Audio Bitstream DAC Sample Data Register

(SDR) when the Audio Bitstream DAC is ready for new samples. This enables the Audio Bitstream DAC to operate without any CPU intervention such as polling the Interrupt Status

Register (ISR) or using interrupts. See the DMA controller documentation for details on how to setup DMA transfers.

27.6

Functional Description

27.6.1

In order to use the Audio Bitstream DAC the product dependencies given in

Section 27.5 on page 472

must be resolved. Particular attention should be given to the configuration of clocks and I/O lines in order to ensure correct operation of the Audio Bitstream DAC.

The Audio Bitstream DAC is enabled by writing the ENABLE bit in the Audio Bitstream DAC

Control Register (CR). The two 16-bit sample values for channel 0 and 1 can then be written to the least and most significant halfword of the Sample Data Register (SDR), respectively. The

TX_READY bit in the Interrupt Status Register (ISR) will be set whenever the DAC is ready to receive a new sample. A new sample value should be written to SDR before 256 DAC clock cycles, or an underrun will occur, as indicated by the UNDERRUN status flags in ISR. ISR is cleared when read, or when writing one to the corresponding bits in the Interrupt Clear Register

(ICR).

For interrupt-based operation, the relevant interrupts must be enabled by writing one to the corresponding bits in the Interrupt Enable Register (IER). Interrupts can be disabled by the Interrupt

Disable Register (IDR), and active interrupts are indicated in the read-only Interrupt Mask Register (IMR).

The Audio Bitstream DAC can also be configured for peripheral DMA access, in which case only the enable bit in the control register needs to be set in the Audio Bitstream DAC module.

Equalization Filter

The equalization filter is a simple 3-tap FIR filter. The purpose of this filter is to compensate for the pass band frequency response of the sinc interpolation filter. The equalization filter makes the pass band response more flat and moves the -3dB corner a little higher.

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27.6.2

27.6.3

27.6.4

Interpolation filter

The interpolation filter interpolates from f s

to 128f s

. This filter is a 4th order Cascaded Integrator-

Comb filter, and the basic building blocks of this filter is a comb part and an integrator part.

Sigma Delta Modulator

This part is a 3rd order Sigma Delta Modulator consisting of three differentiators (delta blocks), three integrators (sigma blocks) and a one bit quantizer. The purpose of the integrators is to shape the noise, so that the noise is reduces in the band of interest and increased at the higher frequencies, where it can be filtered.

Data Format

Input data is on two’s complement format.

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27.7

Audio Bitstream DAC User Interface

Table 27-2.

Register Mapping

Offset

0x0

0x4

0x8

0xc

0x10

0x14

0x18

0x1C

Sample Data Register

Reserved

Control Register

Interrupt Mask Register

Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Clear Register

Interrupt Status Register

Register Name

SDR

-

CR

IMR

IER

IDR

ICR

ISR

Access

Read/Write

-

Read/Write

Read

Write

Write

Write

Read

Reset

0x0

-

0x0

0x0

-

-

-

0x0

32015D–AVR32–10/07

475

AT32AP7001

27.7.1

Audio Bitstream DAC Sample Data Register

Name:

Access Type:

SDR

Read-Write

31 30 29 28

CHANNEL1

23 22 21 20

27

19

CHANNEL1

15 14 13 12 11

CHANNEL0

7 6 5 4 3

CHANNEL0

26

18

10

2

25

17

9

1

24

16

8

0

• CHANNEL0: Sample Data for Channel 0

Signed 16-bit Sample Data for channel 0. When the SWAP bit in the DAC Control Register (CR) is set writing to the Sample

Data Register (SDR) will cause the values written to CHANNEL0 and CHANNEL1 to be swapped.

• CHANNEL1: Sample Data for Channel 1

Signed 16-bit Sample Data for channel 1. When the SWAP bit in the DAC Control Register (CR) is set writing to the Sample

Data Register (SDR) will cause the values written to CHANNEL0 and CHANNEL1 to be swapped.

476

32015D–AVR32–10/07

AT32AP7001

27.7.2

Audio Bitstream DAC Control Register

Name:

Access Type:

CR

Read-Write

31

EN

23

-

15

-

7

-

30

SWAP

22

-

14

-

6

-

-

13

-

5

-

29

-

21

-

12

-

4

-

28

-

20

-

11

-

3

-

27

-

19

-

10

-

2

-

26

-

18

-

1

-

9

-

25

-

17

-

0

-

8

-

24

-

16

• SWAP: Swap Channels

0: The CHANNEL0 and CHANNEL1 samples will not be swapped when writing the Audio Bitstream DAC Sample Data

Register (SDR).

1: The CHANNEL0 and CHANNEL1 samples will be swapped when writing the Audio Bitstream DAC Sample Data Register (SDR).

• EN: Enable Audio Bitstream DAC

0: Audio Bitstream DAC is disabled.

1: Audio Bitstream DAC is enabled.

477

32015D–AVR32–10/07

AT32AP7001

27.7.3

Audio Bitstream DAC Interrupt Mask Register

Name:

Access Type:

IMR

Read-only

-

15

-

7

-

31

-

23

-

14

-

6

-

30

-

22

29

TX_READY

21

-

13

-

5

-

28

UNDERRUN

20

-

12

-

4

-

• UNDERRUN: Underrun Interrupt Mask

0: The Audio Bitstream DAC Underrun interrupt is disabled.

1: The Audio Bitstream DAC Underrun interrupt is enabled.

• TX_READY: TX Ready Interrupt Mask

0: The Audio Bitstream DAC TX Ready interrupt is disabled.

1: The Audio Bitstream DAC TX Ready interrupt is enabled.

-

11

-

3

-

27

-

19

-

10

-

2

-

26

-

18

-

1

-

9

-

25

-

17

-

0

-

8

-

24

-

16

478

32015D–AVR32–10/07

AT32AP7001

27.7.4

Audio Bitstream DAC Interrupt Enable Register

Name:

Access Type:

IER

Write-only

-

15

-

7

-

31

-

23

-

14

-

6

-

30

-

22

29

TX_READY

21

-

13

-

5

-

28

UNDERRUN

20

-

12

-

4

-

• UNDERRUN: Underrun Interrupt Enable

0: No effect.

1: Enables the Audio Bitstream DAC Underrun interrupt.

• TX_READY: TX Ready Interrupt Enable

0: No effect.

1: Enables the Audio Bitstream DAC TX Ready interrupt.

-

11

-

3

-

27

-

19

-

10

-

2

-

26

-

18

-

1

-

9

-

25

-

17

-

0

-

8

-

24

-

16

479

32015D–AVR32–10/07

AT32AP7001

27.7.5

Audio Bitstream DAC Interrupt Disable Register

Name:

Access Type:

IDR

Write-only

-

15

-

7

-

31

-

23

-

14

-

6

-

30

-

22

29

TX_READY

21

-

13

-

5

-

28

UNDERRUN

20

-

12

-

4

-

• UNDERRUN: Underrun Interrupt Disable

0: No effect.

1: Disable the Audio Bitstream DAC Underrun interrupt.

• TX_READY: TX Ready Interrupt Disable

0: No effect.

1: Disable the Audio Bitstream DAC TX Ready interrupt.

-

11

-

3

-

27

-

19

-

10

-

2

-

26

-

18

-

1

-

9

-

25

-

17

-

0

-

8

-

24

-

16

480

32015D–AVR32–10/07

AT32AP7001

27.7.6

Audio Bitstream DAC Interrupt Clear Register

Name:

Access Type:

ICR

Write-only

-

15

-

7

-

31

-

23

-

14

-

6

-

30

-

22

29

TX_READY

21

-

13

-

5

-

28

UNDERRUN

20

-

12

-

4

-

• UNDERRUN: Underrun Interrupt Clear

0: No effect.

1: Clear the Audio Bitstream DAC Underrun interrupt.

• TX_READY: TX Ready Interrupt Clear

0: No effect.

1: Clear the Audio Bitstream DAC TX Ready interrupt.

-

11

-

3

-

27

-

19

-

10

-

2

-

26

-

18

-

1

-

9

-

25

-

17

-

0

-

8

-

24

-

16

481

32015D–AVR32–10/07

AT32AP7001

27.7.7

Audio Bitstream DAC Interrupt Status Register

Name:

Access Type:

ISR

Read-only

-

15

-

7

-

31

-

23

-

14

-

6

-

30

-

22

29

TX_READY

21

-

13

-

5

-

28

UNDERRUN

20

-

12

-

4

-

-

11

-

3

-

27

-

19

-

10

-

2

-

26

-

18

-

1

-

9

-

25

-

17

• UNDERRUN: Underrun Interrupt Status

0: No Audio Bitstream DAC Underrun has occured since the last time ISR was read or since reset.

1: At least one Audio Bitstream DAC Underrun has occured since the last time ISR was read or since reset.

• TX_READY: TX Ready Interrupt Status

0: No Audio Bitstream DAC TX Ready has occuredt since the last time ISR was read.

1: At least one Audio Bitstream DAC TX Ready has occuredt since the last time ISR was read.

-

0

-

8

-

24

-

16

482

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AT32AP7001

27.8

Frequency Response

Figure 27-2. Frequecy response, EQ-FIR+COMB

4

1 0

0

- 1 0

- 2 0

- 3 0

- 4 0

- 5 0

- 6 0

0 1 2 3 4 5 6 7 8 9 1 0 x 1 0

4

483

32015D–AVR32–10/07

AT32AP7001

28. Static Memory Controller (SMC)

Rev: 1.0.4.2

28.1

Features

6 Chip Selects Available

64-Mbyte Address Space per Chip Select

8-, 16- or 32-bit Data Bus

Word, Halfword, Byte Transfers

Byte Write or Byte Select Lines

Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

Programmable Data Float Time per Chip Select

Compliant with LCD Module

External Wait Request

Automatic Switch to Slow Clock Mode

Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

28.2

Description

The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The

32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.

The SMC can manage wait requests from external devices to extend the current access. The

SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from userprogrammed waveforms to slow-rate specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up to 32 bytes.

484

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28.3

Block Diagram

Figure 28-1. SMC Block Diagram

Bus

Matrix

SMC

Chip Select

PMC

MCK

SMC

PIO

Controller

NCS[5:0]

NRD

NWR0/NWE

A0/NBS0

NWR1/NBS1

A1/NWR2/NBS2

NWR3/NBS3

A[25:2]

D[31:0]

NWAIT

User Interface

Peripheral Bus

485

32015D–AVR32–10/07

AT32AP7001

28.4

I/O Lines Description

Table 28-1.

I/O Line Description

Name Description

NCS[5:0]

NRD

NWR0/NWE

A0/NBS0

NWR1/NBS1

A1/NWR2/NBS2

NWR3/NBS3

A[25:2]

Static Memory Controller Chip Select Lines

Read Signal

Write 0/Write Enable Signal

Address Bit 0/Byte 0 Select Signal

Write 1/Byte 1 Select Signal

Address Bit 1/Write 2/Byte 2 Select Signal

Write 3/Byte 3 Select Signal

Address Bus

NWAIT External Wait Signal

Type

Output

Output

Output

Output

Output

Output

Output

Output

I/O

Input

Active Level

Low

Low

Low

Low

Low

Low

Low

Low

28.5

Multiplexed Signals

Table 28-2.

Static Memory Controller (SMC) Multiplexed Signals

NWR0

A0

Multiplexed Signals

NWE

NBS0

Related Function

Byte-write or byte-select access, see ”BAT - Byte Write or Byte Select Access” on page

488

8-bit or 16-/32-bit data bus, see

”Data Bus Width” on page 488

NWR1

A1

NWR3

NBS1

NWR2

NBS3

NBS2

Byte-write or byte-select access see ”BAT - Byte Write or Byte Select Access” on page

488

8-/16-bit or 32-bit data bus, see

”Data Bus Width” on page 488 .

Byte-write or byte-select access, see ”BAT - Byte Write or Byte Select Access” on page

488

Byte-write or byte-select access see ”BAT - Byte Write or Byte Select Access” on page

488

486

32015D–AVR32–10/07

AT32AP7001

28.6

Application Example

28.6.1

Hardware Interface

Figure 28-2. SMC Connections to Static Memory Devices

D0-D31

A0/NBS0

NWR0/NWE

NWR1/NBS1

A1/NWR2/NBS2

NWR3/NBS3

NCS0

NCS1

NCS2

NCS3

NCS4

NCS5

NCS6

NCS7

D0 - D7

D0 - D7

128K x 8

SRAM

CS

A0 - A16

NRD

NWR0/NWE

OE

WE

A2 - A18

D8-D15

128K x 8

D0-D7

SRAM

CS

A0 - A16

NRD

NWR1/NBS1

OE

WE

A2 - A18

A2 - A25

D16 - D23

128K x 8

SRAM

D0 - D7

CS

A0 - A16

A2 - A18

NRD

A1/NWR2/NBS2

OE

WE

D24-D31

128K x 8

D0-D7

SRAM

CS

A0 - A16

NRD

NWR3/NBS3

OE

WE

A2 - A18

Static Memory

Controller

28.7

Product Dependencies

28.7.1

I/O Lines

The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller.

487

32015D–AVR32–10/07

AT32AP7001

28.8

External Memory Mapping

The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory.

If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid

access to the memory device within the page (see Figure 28-1 ).

A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for

32-bit memory.

Figure 28-3. Memory Connections for Eight External Devices

SMC

NCS[0] - NCS[5]

NRD

NWE

A[25:0]

D[31:0]

NCS5

NCS4

Memory Enable

Memory Enable

NCS3

Memory Enable

NCS2

NCS1

Memory Enable

Memory Enable

NCS0

Memory Enable

Output Enable

Write Enable

8 or 16 or 32

A[25:0]

D[31:0] or D[15:0] or

D[7:0]

28.9

Connection to External Devices

28.9.1

Data Bus Width

A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is controlled by the field DBW in MODE (Mode Register) for the corresponding chip select.

Figure 28-4 shows how to connect a 512K x 8-bit memory on NCS2. Figure 28-5 shows how to

connect a 512K x 16-bit memory on NCS2.

Figure 28-6

shows two 16-bit memories connected as a single 32-bit memory

28.9.2

BAT - Byte Write or Byte Select Access

Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access. This is controlled by the BAT (BAT = Byte Select

Access) field of the MODE register for the corresponding chip select.

488

32015D–AVR32–10/07

32015D–AVR32–10/07

AT32AP7001

Figure 28-4. Memory Connection for an 8-bit Data Bus

D[7:0] D[7:0]

SMC

A[18:2]

A0

A1

NWE

NRD

NCS[2]

A[18:2]

A0

A1

Write Enable

Output Enable

Memory Enable

Figure 28-5. Memory Connection for a 16-bit Data Bus

SMC

D[15:0]

A[19:2]

A1

NBS0

NBS1

NWE

NRD

NCS[2]

D[15:0]

A[18:1]

A[0]

Low Byte Enable

High Byte Enable

Write Enable

Output Enable

Memory Enable

Figure 28-6. Memory Connection for a 32-bit Data Bus

D[31:16]

D[15:0]

A[20:2]

SMC

NBS0

NBS1

NBS2

NBS3

NWE

NRD

NCS[2]

D[31:16]

D[15:0]

A[18:0]

Byte 0 Enable

Byte 1 Enable

Byte 2 Enable

Byte 3 Enable

Write Enable

Output Enable

Memory Enable

489

AT32AP7001

28.9.2.1

28.9.2.2

Byte Write Access

Byte write access supports one byte write signal per byte of the data bus and a single read signal.

• For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0

(lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided.

Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.

• For 32-bit devices: NWR0, NWR1, NWR2 and NWR3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. One single read signal (NRD) is provided.

Byte Write Access is used to connect 4 x 8-bit devices as a 32-bit memory.

Byte Write option is illustrated on

Figure 28-7 on page 490 .

Byte Select Access

In this mode, read/write operations can be enabled/disabled at a byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write.

• For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus.

Byte Select Access is used to connect one 16-bit device.

• For 32-bit devices: NBS0, NBS1, NBS2 and NBS3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. Byte Select Access is used to connect two 16-bit devices.

Figure 28-8 on page 491

shows how to connect two 16-bit devices on a 32-bit data bus in Byte

Select Access mode, on NCS3.

Figure 28-7. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option

D[7:0] D[7:0]

D[15:8]

A[24:2]

SMC

A1

NWR0

NWR1

NRD

NCS[3]

A[23:1]

A[0]

Write Enable

Read Enable

Memory Enable

D[15:8]

A[23:1]

A[0]

Write Enable

Read Enable

Memory Enable

490

32015D–AVR32–10/07

AT32AP7001

28.9.2.3

Signal Multiplexing

Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed.

Table 28-3 on page 491

shows signal multiplexing depending on the data bus width and the byte access type.

For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused.

When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused.

Figure 28-8. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option)

D[15:0]

SMC

D[15:0]

D[31:16]

A[25:2]

NWE

NBS0

NBS1

NBS2

NBS3

NRD

NCS[3]

A[23:0]

Write Enable

Low Byte Enable

High Byte Enable

Read Enable

Memory Enable

D[31:16]

A[23:0]

Write Enable

Low Byte Enable

High Byte Enable

Read Enable

Memory Enable

Table 28-3.

SMC Multiplexed Signal Translation

Signal Name

Device Type 1x32-bit

32-bit Bus

2x16-bit

Byte Access Type (BAT)

NBS0_A0

NWE_NWR0

NBS1_NWR1

NBS2_NWR2_A1

NBS3_NWR3

Byte Select

NBS0

NWE

NBS1

NBS2

NBS3

Byte Select

NBS0

NWE

NBS1

NBS2

NBS3

4 x 8-bit

Byte Write

NWR0

NWR1

NWR2

NWR3

16-bit Bus

1x16-bit 2 x 8-bit

Byte Select

NBS0

Byte Write

NWE

NBS1

A1

NWR0

NWR1

A1

8-bit Bus

1 x 8-bit

A0

NWE

A1

491

32015D–AVR32–10/07

AT32AP7001

28.10 Standard Read and Write Protocols

In the following sections, the byte access type is not considered. Byte select lines (NBS0 to

NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way,

NCS represents one of the NCS[0..NB_CS-1] chip select lines.

28.10.1

Read Waveforms

The read cycle is shown on Figure 28-9 on page 492 .

The read cycle starts with the address setting on the memory address bus, i.e.:

{A[25:2], A1, A0} for 8-bit devices

{A[25:2], A1} for 16-bit devices

A[25:2] for 32-bit devices.

Figure 28-9. Standard Read Cycle

MCK

A[25:2]

NBS0,NBS1,

NBS2,NBS3,

A0, A1

NRD

NCS

D[31:0]

NRD_SETUP

NCS_RD_SETUP

NRD_PULSE

NCS_RD_PULSE

NRD_CYCLE

NRD_HOLD

NCS_RD_HOLD

28.10.1.1

NRD Waveform

The NRD signal is characterized by a setup timing, a pulse width and a hold timing.

1.

NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge;

2.

NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge;

3.

NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge.

492

32015D–AVR32–10/07

AT32AP7001

28.10.1.2

28.10.1.3

28.10.1.4

NCS Waveform

Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:

1.

NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge.

2.

NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and

NCS rising edge;

3.

NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the

NCS rising edge.

Read Cycle

The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to:

NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD

= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD

All NRD and NCS timings are defined separately for each chip select as an integer number of

Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as:

NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE

NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE

Null Delay Setup and Hold

If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain

active continuously in case of consecutive read cycles in the same memory (see Figure 28-10

).

493

32015D–AVR32–10/07

AT32AP7001

Figure 28-10. No Setup, No Hold On NRD and NCS Read Signals

MCK

A[25:2]

NBS0,NBS1,

NBS2,NBS3,

A0, A1

NRD

NCS

D[31:0]

NRD_PULSE

NCS_RD_PULSE

NRD_PULSE NRD_PULSE

NCS_RD_PULSE

NCS_RD_PULSE

NRD_CYCLE NRD_CYCLE NRD_CYCLE

28.10.1.5

Null Pulse

Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.

28.10.2

Read Mode

28.10.2.1

As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter indicates which signal (NCS or NRD) controls the read operation. This parameter resides in the MODE register of the corresponding chip select.

Read is Controlled by NRD (READ_MODE = 1):

Figure 28-11 on page 495 shows the waveforms of a read operation of a typical asynchronous

RAM. The read data is available t

PACC

after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the programmed waveform of NCS may be.

494

32015D–AVR32–10/07

AT32AP7001

Figure 28-11. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD

MCK

A[25:2]

NBS0,NBS1,

NBS2,NBS3,

A0, A1

NRD

NCS

D[31:0] t

PACC

Data Sampling

28.10.2.2

Read is Controlled by NCS (READ_MODE = 0)

Figure 28-12 on page 495 shows the typical read cycle of an LCD module. The read data is valid

t

PACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be.

Figure 28-12. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS

MCK

A[25:2]

NBS0,NBS1,

NBS2,NBS3,

A0, A1

NRD

NCS

D[31:0] t

PACC

Data Sampling

495

32015D–AVR32–10/07

AT32AP7001

28.10.3

Write Waveforms

The write protocol is similar to the read protocol. It is depicted in Figure 28-13 on page 496 . The

write cycle starts with the address setting on the memory address bus.

28.10.3.1

NWE Waveforms

The NWE signal is characterized by a setup timing, a pulse width and a hold timing.

1.

NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge;

2.

NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge;

3.

NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge.

The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.

28.10.3.2

NCS Waveforms

The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately defined:

1.

NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge.

2.

NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and

NCS rising edge;

3.

NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the

NCS rising edge.

Figure 28-13. Write Cycle

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1

NWE

NCS

NWE_SETUP

NCS_WR_SETUP

NWE_PULSE

NCS_WR_PULSE

NWE_CYCLE

NWE_HOLD

NCS_WR_HOLD

496

32015D–AVR32–10/07

AT32AP7001

28.10.3.3

28.10.3.4

Write Cycle

The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to:

NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD

= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD

All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as:

NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE

NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE

Null Delay Setup and Hold

If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active

continuously in case of consecutive write cycles in the same memory (see Figure 28-14 on page

497

). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.

Figure 28-14. Null Setup and Hold Values of NCS and NWE in Write Cycle

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1

NWE,

NWR0, NWR1,

NWR2, NWR3

NCS

D[31:0]

NWE_PULSE

NCS_WR_PULSE

NWE_PULSE NWE_PULSE

NCS_WR_PULSE NCS_WR_PULSE

NWE_CYCLE NWE_CYCLE NWE_CYCLE

28.10.3.5

Null Pulse

Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.

497

32015D–AVR32–10/07

AT32AP7001

28.10.4

Write Mode

28.10.4.1

The WRITE_MODE parameter in the MODE register of the corresponding chip select indicates which signal controls the write operation.

Write is Controlled by NWE (WRITE_MODE = 1):

Figure 28-15 on page 498

shows the waveforms of a write operation with WRITE_MODE set to

1. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.

Figure 28-15. WRITE_MODE = 1. The write operation is controlled by NWE

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1

NWE,

NWR0, NWR1,

NWR2, NWR3

NCS

D[31:0]

28.10.4.2

Write is Controlled by NCS (WRITE_MODE = 0)

Figure 28-16 on page 499

shows the waveforms of a write operation with WRITE_MODE set to

0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.

498

32015D–AVR32–10/07

AT32AP7001

Figure 28-16. WRITE_MODE = 0. The write operation is controlled by NCS

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1

NWE,

NWR0, NWR1,

NWR2, NWR3

NCS

D[31:0]

28.10.5

Coding Timing Parameters

All timing parameters are defined for one chip select and are grouped together in one

SMC_REGISTER according to their type.

The SETUP register groups the definition of all setup parameters:

• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP

The PULSE register groups the definition of all pulse parameters:

• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE

The CYCLE register groups the definition of all cycle parameters:

• NRD_CYCLE, NWE_CYCLE

Section 28-4 on page 499

shows how the timing parameters are coded and their permitted range.

Table 28-4.

Coding and Range of Timing Parameters

Coded Value

setup [5:0] pulse [6:0] cycle [8:0]

Number of Bits

6

7

9

Effective Value

128 x setup[5] + setup[4:0]

256 x pulse[6] + pulse[5:0]

256 x cycle[8:7] + cycle[6:0]

Permitted Range

Coded Value

0

≤ ≤

31

0

≤ ≤

63

0

≤ ≤

127

Effective Value

128

≤ ≤

128+31

256

≤ ≤

256+63

256

≤ ≤

256+127

512

≤ ≤

512+127

768

≤ ≤

768+127

499

32015D–AVR32–10/07

AT32AP7001

28.10.6

Reset Values of Timing Parameters

Section 28-5 on page 500

gives the default value of timing parameters at reset.

Table 28-5.

Reset Values of Timing Parameters

Register Reset Value

SETUP

PULSE

CYCLE

WRITE_MODE

READ_MODE

0x01010101

0x01010101

0x00030003

1

1

All setup timings are set to 1

All pulse timings are set to 1

The read and write operation last 3 Master Clock cycles and provide one hold cycle

Write is controlled with NWE

Read is controlled with NRD

28.10.7

Usage Restriction

The SMC does not check the validity of the user-programmed parameters. If the sum of

SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.

For read operations:

Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals.

For write operations:

If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE =

1 only. See

”Early Read Wait State” on page 501 .

For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior.

In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus.

28.11 Automatic Wait States

Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict.

28.11.1

Chip Select Wait States

The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one.

During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to

NWR3, NCS[0..NB_CS-1], NRD lines are all set to 1.

Figure 28-17 on page 501

illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.

500

32015D–AVR32–10/07

AT32AP7001

Figure 28-17. Chip Select Wait State between a Read Access on NCS0 and a Write Access on

NCS2

MCK

A[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NRD

NWE

NCS0

NCS2

NRD_CYCLE NWE_CYCLE

D[31:0]

Read to Write

Wait State

Chip Select

Wait State

28.11.2

Early Read Wait State

In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select).

An early read wait state is automatically inserted if at least one of the following conditions is valid:

• if the write controlling signal has no hold time and the read controlling signal has no setup time (

Figure 28-18 on page 502

).

• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS

signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode ( Figure

28-19 on page 502 ). The write operation must end with a NCS rising edge. Without an Early

Read Wait State, the write operation could not complete properly.

• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD =

0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are

maintained one more cycle. See Figure 28-20 on page 503 .

501

32015D–AVR32–10/07

32015D–AVR32–10/07

AT32AP7001

Figure 28-18. Early Read Wait State: Write with No Hold Followed by Read with No Setup

MCK

A[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1

NWE

NRD

D[31:0] no hold no setup write cycle

Early Read wait state read cycle

Figure 28-19. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read

MCK

A[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NCS

NRD

D[31:0] no hold no setup write cycle

(WRITE_MODE = 0)

Early Read wait state read cycle

(READ_MODE = 0 or READ_MODE = 1) with No NCS Setup

502

AT32AP7001

Figure 28-20. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read

MCK

A [25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1 internal write controlling signal external write controlling signal

(NWE)

NRD

D[31:0] no hold read setup = 1 write cycle

(WRITE_MODE = 1)

Early Read wait state read cycle

(READ_MODE = 0 or READ_MODE = 1) with one Set-up Cycle

28.11.3

Reload User Configuration Wait State

The user may change any of the configuration parameters by writing the SMC user interface.

When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration

Wait State” is used by the SMC to load the new set of parameters to apply to next accesses.

The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming the user interface are made to different devices

(Chip Selects), then one single Chip Select Wait State is applied.

On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload Configuration Wait State is inserted, even if the change does not concern the current Chip Select.

28.11.3.1

28.11.3.2

User Procedure

To insert a Reload Configuration Wait State, the SMC detects a write access to any MODE register of the user interface. If the user only modifies timing registers (SETUP, PULSE, CYCLE registers) in the user interface, he must validate the modification by writing the MODE, even if no change was made on the mode parameters.

Slow Clock Mode Transition

A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or

exited, after the end of the current transfer (see ”Slow Clock Mode” on page 515

).

503

32015D–AVR32–10/07

AT32AP7001

28.11.4

Read to Write Wait State

Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.

This wait cycle is referred to as a read to write wait state in this document.

This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See

Figure 28-17 on page 501

.

32015D–AVR32–10/07

504

AT32AP7001

28.12 Data Float Wait States

Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access:

• before starting a read access to a different external memory

• before starting a write access to the same device or to a different external one.

The Data Float Output Time (t

DF

) for each external memory device is programmed in the

TDF_CYCLES field of the MODE register for the corresponding chip select. The value of

TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled.

Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long t

DF will not slow down the execution of a program from internal memory.

The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the MODE register for the corresponding chip select.

28.12.1

READ_MODE

Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles.

When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS.

Figure 28-21 on page 506 illustrates the Data Float Period in NRD-controlled mode

(READ_MODE =1), assuming a data float period of 2 cycles (TDF_CYCLES = 2).

Figure 28-22 on page 506

shows the read operation when controlled by NCS (READ_MODE = 0) and the

TDF_CYCLES parameter equals 3.

505

32015D–AVR32–10/07

32015D–AVR32–10/07

AT32AP7001

Figure 28-21. TDF Period in NRD Controlled Read Access (TDF = 2)

MCK

A[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1

NRD

NCS

D[31:0] tpacc

TDF = 2 clock cycles

NRD controlled read operation

Figure 28-22. TDF Period in NCS Controlled Read Operation (TDF = 3)

MCK

A[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NRD

NCS

D[31:0] tpacc

TDF = 3 clock cycles

NCS controlled read operation

506

AT32AP7001

28.12.2

TDF Optimization Enabled (TDF_MODE = 1)

When the TDF_MODE of the MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.

Figure 28-23 on page 507

shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with:

NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)

NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)

TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).

Figure 28-23. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins

MCK

A

[25:2]

NRD

NRD_HOLD= 4

NWE

NWE_SETUP= 3

NCS0

TDF_CYCLES = 6

D[31:0] read access on NCS0 (NRD controlled)

Read to Write

Wait State write access on NCS0 (NWE controlled)

28.12.3

TDF Optimization Disabled (TDF_MODE = 0)

When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted.

Figure 28-24 on page 508 , Figure 28-25 on page 508

and

Figure 28-26 on page 509

illustrate the cases:

• read access followed by a read access on another chip select,

• read access followed by a write access on another chip select,

• read access followed by a write access on the same chip select, with no TDF optimization.

507

32015D–AVR32–10/07

AT32AP7001

Figure 28-24. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects

MCK

A[

25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1 read1 controlling signal

(NRD) read2 controlling signal

(NRD)

D[31:0] read1 hold = 1

TDF_CYCLES = 6 read2 setup = 1

5 TDF WAIT STATES read1 cycle

TDF_CYCLES = 6

Chip Select Wait State read 2 cycle

TDF_MODE = 0

(optimization disabled)

Figure 28-25. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1 read1 controlling signal

(NRD) write2 controlling signal

(NWE)

D[31:0] read1 hold = 1

TDF_CYCLES = 4 write2 setup = 1 read1 cycle

TDF_CYCLES = 4

Read to Write Chip Select

Wait State Wait State

2 TDF WAIT STATES write2 cycle

TDF_MODE = 0

(optimization disabled)

508

32015D–AVR32–10/07

AT32AP7001

Figure 28-26. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select

MCK

A [25:2]

NBS0, NBS1,

NBS2, NBS3,

A0, A1 read1 controlling signal

(NRD) write2 controlling signal

(NWE)

D[31:0] read1 hold = 1

TDF_CYCLES = 5 write2 setup = 1

4 TDF WAIT STATES read1 cycle

TDF_CYCLES = 5

Read to Write

Wait State write2 cycle

TDF_MODE = 0

(optimization disabled)

28.13 External Wait

Any access can be extended by an external device using the NWAIT input signal of the SMC.

The EXNW_MODE field of the MODE register on the corresponding chip select must be set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select.

28.13.1

Restriction

When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page

Mode (

”Asynchronous Page Mode” on page 518

), or in Slow Clock Mode ( ”Slow Clock Mode” on page 515

).

The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior.

509

32015D–AVR32–10/07

AT32AP7001

28.13.2

Frozen Mode

When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See

Figure 28-

27 on page 510

. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC.

The assertion of the NWAIT signal outside the expected period is ignored as illustrated in

Figure

28-28 on page 511

.

Figure 28-27. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NWE

NCS

D[31:0]

6

4

5 4

3 2

3

1

2

1

FROZEN STATE

1 1

2 2 2

0

1 0

NWAIT internally synchronized

NWAIT signal

Write cycle

EXNW_MODE = 10 (Frozen)

WRITE_MODE = 1 (NWE_controlled)

NWE_PULSE = 5

NCS_WR_PULSE = 7

510

32015D–AVR32–10/07

AT32AP7001

Figure 28-28. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NCS

1

4 3

0

2

FROZEN STATE

2 2 1 0

NRD

NWAIT

5 5 5

4 3

2

2 internally synchronized

NWAIT signal

Read cycle

EXNW_MODE = 10 (Frozen)

READ_MODE = 0 (NCS_controlled)

NRD_PULSE = 2, NRD_HOLD = 6

NCS_RD_PULSE =5, NCS_RD_HOLD =3

Assertion is ignored

1

1

0

0

511

32015D–AVR32–10/07

AT32AP7001

28.13.3

Ready Mode

In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.

If asserted, the SMC suspends the access as shown in

Figure 28-29 on page 512 and

Figure

28-30 on page 513

. After deassertion, the access is completed: the hold step of the access is performed.

This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation.

If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the

pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 28-30 on page 513

.

Figure 28-29. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

4 3 2 1 0

Wait STATE

0 0

NWE

NCS

6 5 4 3 2 1 1 1 0

D[31:0]

NWAIT internally synchronized

NWAIT signal

Write cycle

EXNW_MODE = 11 (Ready mode)

WRITE_MODE = 1 (NWE_controlled)

NWE_PULSE = 5

NCS_WR_PULSE = 7

512

32015D–AVR32–10/07

AT32AP7001

Figure 28-30. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11)

MCK

A[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NCS

6 5 4 3 2 1 0

Wait STATE

0

6 5 4 3 2 1 1

NRD

0

NWAIT internally synchronized

NWAIT signal

Assertion is ignored

Read cycle

EXNW_MODE = 11(Ready mode)

READ_MODE = 0 (NCS_controlled)

NRD_PULSE = 7

NCS_RD_PULSE =7

Assertion is ignored

513

32015D–AVR32–10/07

AT32AP7001

28.13.4

NWAIT Latency and Read/write Timings

There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT

signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 28-31 on page 514

.

When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle

Figure 28-31. NWAIT Latency

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

4 3 0 0

WAIT STATE

0

NRD

2 1 minimal pulse length

NWAIT intenally synchronized

NWAIT signal

NWAIT latency 2 cycle resynchronization

Read cycle

EXNW_MODE = 10 or 11

READ_MODE = 1 (NRD_controlled)

NRD_PULSE = 5

514

32015D–AVR32–10/07

AT32AP7001

28.14 Slow Clock Mode

The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects.

28.14.1

Slow Clock Mode Waveforms

Figure 28-32 on page 515 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Section 28-6 on page 515

indicates the value of read and write parameters in slow clock mode.

Figure 28-32. Read/write Cycles in Slow Clock Mode

MCK MCK

A [25:2] A[ 25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NRD

NWE 1 1

1

1

1

NCS

NCS

NWE_CYCLE = 3

SLOW CLOCK MODE WRITE

NRD_CYCLE = 2

SLOW CLOCK MODE READ

Table 28-6.

Read and Write Timing Parameters in Slow Clock Mode

Read Parameters

NRD_SETUP

Duration (cycles)

1

Write Parameters

NWE_SETUP

NRD_PULSE

NCS_RD_SETUP

NCS_RD_PULSE

NRD_CYCLE

2

2

1

0

NWE_PULSE

NCS_WR_SETUP

NCS_WR_PULSE

NWE_CYCLE

Duration (cycles)

1

1

0

3

3

515

32015D–AVR32–10/07

AT32AP7001

28.14.2

Switching from (to) Slow Clock Mode to (from) Normal Mode

When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See

Figure 28-33 on page 516

. The external device may not be fast enough to support such timings.

Figure 28-34 on page 517 illustrates the recommended procedure to properly switch from one

mode to the other.

Figure 28-33. Clock Rate Transition Occurs while the SMC is Performing a Write Operation

Slow Clock Mode internal signal from PMC

MCK

A

[25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NWE

1 1 1 1 1 1 2

3

2

NCS

NWE_CYCLE = 3

SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE

NWE_CYCLE = 7

NORMAL MODE WRITE

This write cycle finishes with the slow clock mode set of parameters after the clock rate transition

Slow clock mode transition is detected:

Reload Configuration Wait State

516

32015D–AVR32–10/07

AT32AP7001

Figure 28-34. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow

Clock Mode

Slow Clock Mode internal signal from PMC

MCK

A [25:2]

NBS0, NBS1,

NBS2, NBS3,

A0,A1

NWE

NCS

1 1 1 2

3

2

SLOW CLOCK MODE WRITE

IDLE STATE NORMAL MODE WRITE

Reload Configuration

Wait State

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28.15 Asynchronous Page Mode

The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the MODE register (PMEN field). The page size must be configured in the MODE register (PS field) to 4, 8, 16 or 32 bytes.

The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The

MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in

Table 28-7 on page 518

.

With page mode memory devices, the first access to one page (t pa

) takes longer than the subsequent accesses to the page (t sa

) as shown in Figure 28-35 on page 518 . When in page mode,

the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page.

Table 28-7.

Page Address and Data Address within a Page

Page Size Page Address

(1)

Data Address in the Page

(2)

4 bytes

8 bytes

16 bytes

32 bytes

A[25:2]

A[25:3]

A[25:4]

A[25:5]

A[1:0]

A[2:0]

A[3:0]

A[4:0]

Notes: 1. A denotes the address bus of the memory device

2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.

28.15.1

Protocol and Timings in Page Mode

Figure 28-35 on page 518

shows the NRD and NCS timings in page mode access.

Figure 28-35. Page Mode Read Protocol (Address MSB and LSB are defined in

Table 28-7 on page 518 )

MCK

A[MSB]

A[LSB]

NRD

NCS tpa tsa tsa

D[31:0]

NCS_RD_PULSE

NRD_PULSE

NRD_PULSE

The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the

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NCS_RD_PULSE field of the PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter.

In page mode, the programming of the read timings is described in Table 28-8 on page 519 :

Table 28-8.

Programming of Read Timings in Page Mode

Parameter Value Definition

READ_MODE

NCS_RD_SETUP

NCS_RD_PULSE

NRD_SETUP

NRD_PULSE

NRD_CYCLE t pa

‘x’ t sa

‘x’

Access time of first access to the page

No impact

Access time of subsequent accesses in the page

No impact

The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access timing (t pa

) and the NRD_PULSE for accesses to the page (t sa

), even if the programmed value for t pa

is shorter than the programmed value for t sa

.

28.15.2

Byte Access Type in Page Mode

The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page m o d e d e v i c e s t ha t r e q u i r e b y t e s e l e c t i o n s i g n a l s , c o n fi g u re t h e B A T f i e l d o f t h e

SMC_REGISTER to 0 (byte select access type).

28.15.3

Page Mode Restriction

The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior.

28.15.4

Sequential and Non-sequential Accesses

If the chip select and the MSB of addresses as defined in Table 28-7 on page 518

are identical, then the current access lies in the same page as the previous one, and no page break occurs.

Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa

).

Figure 28-36 on page 520

illustrates access to an 8-bit memory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long access time (t pa

). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (t sa

).

If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses.

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AT32AP7001

Figure 28-36. Access to Non-sequential Data within the Same Page

MCK

A [25:3]

Page address

2], A1, A0

A1 A3

NRD

NCS

D[7:0]

NCS_RD_PULSE

A7

D1

NRD_PULSE

D3

NRD_PULSE

D7

520

AT32AP7001

28.16 Static Memory Controller (SMC) User Interface

The SMC is programmed using the registers listed in

Table 28-9 on page 521

. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In

Table 28-9 on page 521 , “CS_number” denotes

the chip select number. 16 bytes (0x10) are required per chip select.

The user must complete writing the configuration by writing any one of the MODE registers.

Table 28-9.

SMC Register Mapping

Offset

0x10 x CS_number + 0x00

Register Name

SMC Setup Register SETUP

0x10 x CS_number + 0x04

0x10 x CS_number + 0x08

0x10 x CS_number + 0x0C

SMC Pulse Register

SMC Cycle Register

SMC Mode Register

PULSE

CYCLE

MODE

Read/Write

Read/Write

Read/Write

Read/Write

0x00010001

0x04030402

0x00050005

0x10011103

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521

AT32AP7001

28.16.1

SMC Setup Register

Register Name:

SETUP[0 ..

NB_CS-1 ]

Access Type:

Read/Write

31

23

15

30

22

14

29

21

13

28

20

12

27 26

NCS_RD_SETUP

19

NRD_SETUP

18

11 10

NCS_WR_SETUP

7

6

5 4 3

NWE_SETUP

2

• NWE_SETUP: NWE Setup Length

The NWE signal setup length is defined as:

NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles

• NCS_WR_SETUP: NCS Setup Length in WRITE Access

In write access, the NCS signal setup length is defined as:

NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles

• NRD_SETUP: NRD Setup Length

The NRD signal setup length is defined in clock cycles as:

NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles

• NCS_RD_SETUP: NCS Setup Length in READ Access

In read access, the NCS signal setup length is defined as:

NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles

25

17

9

1

24

16

8

0

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28.16.2

SMC Pulse Register

Register Name:

PULSE[0..

NB_CS-1 ]

Access Type:

Read/Write

31

23

15

30

22

14

29

21

13

28

20

12

27

NCS_RD_PULSE

19

NRD_PULSE

11

NCS_WR_PULSE

26

18

10

25

17

9

24

16

8

7

6 5 4 3

NWE_PULSE

2 1 0

• NWE_PULSE: NWE Pulse Length

The NWE signal pulse length is defined as:

NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles

The NWE pulse length must be at least 1 clock cycle.

• NCS_WR_PULSE: NCS Pulse Length in WRITE Access

In write access, the NCS signal pulse length is defined as:

NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles

The NCS pulse length must be at least 1 clock cycle.

• NRD_PULSE: NRD Pulse Length

In standard read access, the NRD signal pulse length is defined in clock cycles as:

NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles

The NRD pulse length must be at least 1 clock cycle.

In page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page.

• NCS_RD_PULSE: NCS Pulse Length in READ Access

In standard read access, the NCS signal pulse length is defined as:

NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles

The NCS pulse length must be at least 1 clock cycle.

In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page.

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28.16.3

SMC Cycle Register

Register Name:

CYCLE[0..

NB_CS-1 ]

Access Type:

Read/Write

31

23

30

22

29

21

28

27

20

NRD_CYCLE

19

12

11

26

18

25

17

24

NRD_CYCLE

16

15

14

13

10

9

8

NWE_CYCLE

7 6 5 4

NWE_CYCLE

3 2 1 0

• NWE_CYCLE: Total Write Cycle Length

The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals. It is defined as:

Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles

• NRD_CYCLE: Total Read Cycle Length

The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as:

Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles

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28.16.4

SMC MODE Register

Register Name:

MODE[0..

NB_CS-1 ]

Access Type:

31

Read/Write

30

29

PS

23

22

21

15

7

14

6

28

20

TDF_MODE

13 12

DBW

5

EXNW_MODE

4

11

3

27

19

10

2

26

25

18

TDF_CYCLES

17

9

1

WRITE_MOD

E

24

PMEN

16

8

BAT

0

READ_MODE

• READ_MODE:

1: The read operation is controlled by the NRD signal.

– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.

– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.

0: The read operation is controlled by the NCS signal.

– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.

– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.

• WRITE_MODE

1: The write operation is controlled by the NWE signal.

– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.

0: The write operation is controlled by the NCS signal.

– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.

• EXNW_MODE: NWAIT Mode

The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal.

1

1

0

0

EXNW_MODE

0

1

0

1

NWAIT Mode

Disabled

Reserved

Frozen Mode

Ready Mode

• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.

• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.

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• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until

NWAIT returns high.

• BAT: Byte Access Type

This field is used only if DBW defines a 16- or 32-bit data bus.

• 1: Byte write access type:

– Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3.

– Read operation is controlled using NCS and NRD.

• 0: Byte select access type:

– Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3

– Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3

• DBW: Data Bus Width

DBW

0

0

1

1

0

1

0

1

Data Bus Width

8-bit bus

16-bit bus

32-bit bus

Reserved

• TDF_CYCLES: Data Float Time

This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set.

• TDF_MODE: TDF Optimization

1: TDF optimization is enabled.

– The number of TDF wait states is optimized using the setup period of the next read/write access.

0: TDF optimization is disabled.

– The number of TDF wait states is inserted before the next access begins.

• PMEN: Page Mode Enabled

1: Asynchronous burst read in page mode is applied on the corresponding chip select.

0: Standard read is applied.

• PS: Page Size

If page mode is enabled, this field indicates the size of the page in bytes.

PS

0

0

1

1

0

1

0

1

Page Size

4-byte page

8-byte page

16-byte page

32-byte page

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29. SDRAM Controller (SDRAMC)

Rev: 2.0.0.2

29.1

Features

Numerous Configurations Supported

– 2K, 4K, 8K Row Address Memory Parts

– SDRAM with Two or Four Internal Banks

– SDRAM with 16- or 32-bit Data Path

Programming Facilities

– Word, Half-word, Byte Access

– Automatic Page Break When Memory Boundary Has Been Reached

– Multibank Ping-pong Access

– Timing Parameters Specified by Software

– Automatic Refresh Operation, Refresh Rate is Programmable

– Automatic Update of DS, TCR and PASR Parameters (Mobile SDRAM Devices)

Energy-saving Capabilities

– Self-refresh, Power-down and Deep Power Modes Supported

– Supports Mobile SDRAM Devices

Error Detection

– Refresh Error Interrupt

SDRAM Power-up Initialization by Software

CAS Latency of 1, 2, 3 Supported

Auto Precharge Command Not Used

29.2

Description

The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from

2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word

(16-bit) and word (32-bit) accesses.

The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank.

The SDRAM controller supports a CAS latency of 1, 2 or 3 and optimizes the read access depending on the frequency.

The different modes available - self-refresh, power-down and deep power-down modes - minimize power consumption on the SDRAM device.

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29.3

Block Diagram

Figure 29-1. SDRAM Controller Block Diagram

SDRAMC

Chip Select

Memory

Controller

SDRAMC

Interrupt

PMC

MCK

SDRAMC

User Interface

Peripheral Bus

29.4

I/O Lines Description

Table 29-1.

I/O Line Description

Name

SDCK

Description

SDRAM Clock

SDCKE

SDCS

BA[1:0]

RAS

CAS

SDWE

NBS[3:0]

SDRAMC_A[12:0]

D[31:0]

SDRAM Clock Enable

SDRAM Controller Chip Select

Bank Select Signals

Row Signal

Column Signal

SDRAM Write Enable

Data Mask Enable Signals

Address Bus

Data Bus

32015D–AVR32–10/07

PIO

Controller

SDCK

SDCKE

SDCS

BA[1:0]

RAS

CAS

SDWE

NBS[3:0]

SDRAMC_A[12:0]

D[31:0]

Type

Output

Output

Output

Output

Output

Output

Output

Output

Output

I/O

Active Level

High

Low

Low

Low

Low

Low

528

AT32AP7001

29.5

Application Example

29.5.1

Hardware Interface

Figure 29-2 shows an example of SDRAM device connection to the SDRAM Controller using a

32-bit data bus width.

Figure 29-3 shows an example of SDRAM device connection using a 16-

bit data bus width. It is important to note that these examples are given for a direct connection of the devices to the SDRAM Controller, without External Bus Interface or PIO Controller multiplexing.

Figure 29-2. SDRAM Controller Connections to SDRAM Devices: 32-bit Data Bus Width

D0-D31

RAS

CAS

SDCK

SDCKE

SDWE

NBS0

NBS1

NBS2

NBS3

D0-D7

SDWE

2M x 8

D0-D7

SDRAM

CS

CLK

CKE

WE

RAS

CAS

DQM

A0-A9, A11

SDRAMC_A[0-9], SDRAMC_A11

A10 SDRAMC_A10

BA0

BA0

BA1

BA1

NBS0

D8-D15

2M x 8

D0-D7

SDRAM

SDWE

NBS1

CS

CLK

CKE

WE

RAS

CAS

DQM

A0-A9, A11

SDRAMC_A[0-9], SDRAMC_A11

A10 SDRAMC_A10

BA0

BA0

BA1

BA1

SDRAMC_A[0-12]

BA0

BA1

SDCS

SDRAM

Controller

D16-D23

2M x 8

D0-D7

SDRAM

SDWE

CS

CLK

CKE

WE

RAS

CAS

DQM

NBS2

A0-A9, A11

SDRAMC_A[0-9], SDRAMC_ A11

A10 SDRAMC_A10

BA0

BA0

BA1

BA1

D24-D31

2M x 8

D0-D7

SDRAM

SDWE

NBS3

CS

CLK

CKE

WE

RAS

CAS

DQM

A0-A9, A11

A10

BA0

BA1

SDRAMC_A[0-9], SDRAMC_A11

SDRAMC_A10

BA0

BA1

Figure 29-3. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width

D0-D31

RAS

CAS

SDCK

SDCKE

SDWE

NBS0

NBS1

D0-D7

SDWE

2M x 8

D0-D7

SDRAM

CS

CLK

CKE

WE

RAS

CAS

DQM

A0-A9, A11

BA0

SDRAMC_A[0-9], SDRAMC_A11

A10 SDRAMC_A10

BA0

BA1 BA1

NBS0

D8-D15

2M x 8

D0-D7

SDRAM

SDWE

NBS1

CS

CLK

CKE

WE

RAS

CAS

DQM

A0-A9, A11

A10

BA0

BA1

SDRAMC_A[0-9], SDRAMC_A11

SDRAMC_A10

BA0

BA1

SDRAMC_A[0-12]

BA0

BA1

SDRAM

Controller

SDCS

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29.5.2

Software Interface

The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller allows mapping different memory types according to the values set in the SDRAMC configuration register.

The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to the user.

Table 29-2 to

Table 29-7

illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated.

32-bit Memory Data Bus Width 29.5.2.1

Table 29-2.

SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns

2

7

2

6

2

5

2

4

2

3

Bk[1:0]

Bk[1:0]

Bk[1:0]

2

2

Bk[1:0]

2

1

2

0

1

9

1

8

1

7

1

6

CPU Address Line

1

5

Row[10:0]

1

4

1

3

1

2

Row[10:0]

Row[10:0]

Row[10:0]

1

1

1

0 9 8 7 6 5

Column[7:0]

4

Column[8:0]

Column[9:0]

Column[10:0]

3 2 1

M[1:0]

0

M[1:0]

M[1:0]

M[1:0]

Table 29-3.

SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns

2

7

2

6

2

5

2

4

Bk[1:0]

Bk[1:0]

Bk[1:0]

2

3

Bk[1:0]

2

2

2

1

2

0

1

9

1

8

1

7

1

6

1

5

Row[11:0]

CPU Address Line

1

4

1

3

1

2

Row[11:0]

Row[11:0]

Row[11:0]

1

1

1

0 9 8 7 6 5

Column[7:0]

4

Column[8:0]

Column[9:0]

Column[10:0]

3 2 1

M[1:0]

0

M[1:0]

M[1:0]

M[1:0]

Table 29-4.

SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns

2

7

2

6

Bk[1:0]

Bk[1:0]

2

5

2

4

Bk[1:0]

Bk[1:0]

2

3

2

2

2

1

2

0

1

9

1

8

1

7

1

6

Row[12:0]

Row[12:0]

CPU Address Line

1

5

1

4

1

3

1

2

Row[12:0]

Row[12:0]

1

1

1

0 9 8 7 6 5

Column[7:0]

Column[8:0]

4

Column[9:0]

Column[10:0]

Notes: 1. M[1:0] is the byte address inside a 32-bit word.

2. Bk[1] = BA1, Bk[0] = BA0.

3 2 1

M[1:0]

M[1:0]

0

M[1:0]

M[1:0]

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29.5.2.2

16-bit Memory Data Bus Width

Table 29-5.

SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns

2

7

2

6

2

5

2

4

2

3

2

2

2

1

Bk[1:0]

2

0

1

9

1

8

1

7

1

6

CPU Address Line

1

5

1

4

1

3

1

2

Row[10:0]

1

1

1

0 9 8 7

Bk[1:0]

Bk[1:0]

Bk[1:0]

Row[10:0]

Row[10:0]

Row[10:0]

6 5 4

Column[7:0]

3 2

Column[8:0]

Column[9:0]

Column[10:0]

1

M

0

M

0

0

M

0

M

0

Table 29-6.

SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns

2

7

2

6

2

5

2

4

2

3

2

2

Bk[1:0]

2

1

2

0

1

9

1

8

1

7

1

6

CPU Address Line

1

5

1

4

Row[11:0]

1

3

1

2

1

1

1

0 9 8 7

Bk[1:0]

Bk[1:0]

Bk[1:0]

Row[11:0]

Row[11:0]

Row[11:0]

6 5 4

Column[7:0]

3 2

Column[8:0]

Column[9:0]

Column[10:0]

1

M

0

M

0

0

M

0

M

0

Table 29-7.

SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns

2

7

2

6

2

5

2

4

2

3

Bk[1:0]

2

2

2

1

2

0

1

9

1

8

1

7

1

6

CPU Address Line

1

5

Row[12:0]

1

4

1

3

1

2

1

1

1

0 9 8 7

Bk[1:0]

Bk[1:0]

Bk[1:0]

Row[12:0]

Row[12:0]

Row[12:0]

6 5 4

Column[7:0]

3 2

Column[8:0]

Column[9:0]

Column[10:0]

1

M

0

M

0

0

M

0

M

0

Notes: 1. M0 is the byte address inside a 16-bit half-word.

2. Bk[1] = BA1, Bk[0] = BA0.

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29.6

Product Dependencies

29.6.1

SDRAM Device Initialization

The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence:

1.

SDRAM features must be set in the configuration register: asynchronous timings (TRC,

TRAS, ...), number of column, rows, CAS latency, and the data bus width.

2.

For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low Power Register.

3.

The SDRAM memory type must be set in the Memory Device Register.

4.

A minimum pause of 200 µs is provided to precede any signal toggle.

5.

An All Banks Precharge command must be issued to the SDRAM devices. The application must set Mode to 2 in the Mode Register and perform a write access to any SDRAM address.

6.

Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in the Mode Register and performs a write access to any SDRAM location eight times.

7.

A Mode Register set (MRS) cycle must be issued to program the parameters of the

SDRAM devices, in particular CAS latency and burst length. The application must set

Mode to 3 in the Mode Register and perform a write access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB

SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000.

8.

For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle must be issued to program the SDRAM parameters (TCSR, PASR, DS). The application must set

Mode to 5 in the Mode Register and perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a 16-bit

128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write access should be done at the address 0x20800000 or 0x20400000.

9.

The application must go into Normal Mode, setting Mode to 0 in the Mode Register and performing a write access at any location in the SDRAM.

10. Write the refresh rate into the count field in the SDRAMC Refresh Timer register.

(Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh every 15.625 us or 7.81 us. With a 100 MHz frequency, the Refresh Timer Counter Register must be set with the value 1562 (15.625 µs x 100 MHz) or 781 (7.81 µs x 100 MHz).

After initialization, the SDRAM devices are fully functional.

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Figure 29-4. SDRAM Device Initialization Sequence

SDCKE t

RP

SDCK

SDRAMC_A[9:0]

A10

SDRAMC_A[12:11]

SDCS t

RC t

MRD

RAS

CAS

SDWE

NBS

Inputs Stable for

200

μ sec

29.6.2

I/O Lines

Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command

The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their peripheral function. If I/O lines of the SDRAM Controller are not used by the application, they can be used for other purposes by the PIO Controller.

29.6.3

Interrupt

The SDRAM Controller has an interrupt line connected to the interrupt controller. In order to handle interrupts, the interrupt controller must be programmed before configuring the SDRAM

Controller.

Using the SDRAM Controller interrupt requires the IC to be programmed first.)

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29.7

Functional Description

29.7.1

SDRAM Controller Write Cycle

The SDRAM Controller allows burst access or single access. In both cases, the SDRAM controller keeps track of the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAM Controller generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (t

RP

) commands and active/write (t

RCD

) commands. For definition of these timing parameters, refer to the

”SDRAMC

Configuration Register” on page 544

. This is described in Figure 29-5 below.

Figure 29-5. Write Burst, 32-bit SDRAM Access t

RCD

= 3

SDCS

SDCK

SDRAMC_A[12:0]

RAS

Row n col a col b col c col d col e col f col g col h col i col j col k col l

CAS

SDWE

D[31:0]

Dna Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl

29.7.2

SDRAM Controller Read Cycle

The SDRAM Controller allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAM controller automatically generates a precharge command, activates the new row and starts the read command. To comply with the SDRAM timing parameters, additional clock cycles on SDCK are inserted between precharge and active commands

(t

RP

) and between active and read command (t

RCD

). These two parameters are set in the configuration register of the SDRAM Controller. After a read command, additional wait states are generated to comply with the CAS latency (1, 2 or 3 clock delays specified in the configuration register).

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For a single access or an incremented burst of unspecified length, the SDRAM Controller anticipates the next access. While the last value of the column is returned by the SDRAM Controller on the bus, the SDRAM Controller anticipates the read to the next column and thus anticipates the CAS latency. This reduces the effect of the CAS latency on the internal bus.

For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads to the best performance. If the burst is broken (border, busy mode, etc.), the next access is handled as an incrementing burst of unspecified length.

Figure 29-6. Read Burst, 32-bit SDRAM Access t

RCD

= 3

SDCS

CAS = 2

SDCK

SDRAMC_A[12:0]

Row n col a col b col c col d col e col f

RAS

CAS

SDWE

D[31:0]

(Input)

Dna Dnb Dnc Dnd Dne Dnf

29.7.3

Border Management

When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (t

RP

) command and the active/read (t

RCD

) command. This is described in

Figure 29-7

below.

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Figure 29-7. Read Burst with Boundary Row Access

T

RP

= 3

SDCS

SDCK

SDRAMC_A[12:0]

Row n col a col b col c col d

RAS

CAS

SDWE

D[31:0] Dna Dnb Dnc Dnd

T

RCD

= 3 CAS = 2

Row m col a col b col c col d col e

Dma Dmb

Dmc Dmd Dme

29.7.4

SDRAM Controller Refresh Cycles

An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically.

The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is loaded with the value in the register TR that indicates the number of clock cycles between refresh cycles.

A refresh error interrupt is generated when the previous auto-refresh command did not perform.

It is acknowledged by reading the Interrupt Status Register (ISR).

When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the

device is busy and the master is held by a wait signal. See Figure 29-8 .

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Figure 29-8. Refresh Cycle Followed by a Read Access t

RP

= 3

SDCS t

RC

= 8

SDCK

SDRAMC_A[12:0]

Row n col c col d

RAS

CAS

SDWE

D[31:0]

(input)

Dnb Dnc Dnd t

RCD

= 3 CAS = 2

Row m col a

Dma

29.7.5

29.7.5.1

Power Management

Three low-power modes are available:

• Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the

SDRAM Controller. Current drained by the SDRAM is very low.

• Power-down Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between auto-refresh cycles, the SDRAM is in power-down. Current drained in Power-down mode is higher than in Self-refresh Mode.

• Deep Power-down Mode: (Only available with Mobile SDRAM) The SDRAM contents are lost, but the SDRAM does not drain any current.

The SDRAM Controller activates one low-power mode as soon as the SDRAM device is not selected. It is possible to delay the entry in self-refresh and power-down mode after the last access by programming a timeout value in the Low Power Register.

Self-refresh Mode

This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register.

In self-refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh mode.

Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter or all banks of the SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR) and Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to the low-power SDRAM during initialization.

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AT32AP7001

After initialization, as soon as PASR/DS/TCSR fields are modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and PASR/DS/TCSR bits are updated before entry into self-refresh mode.

The SDRAM device must remain in self-refresh mode for a minimum period of t

RAS

and may

remain in self-refresh mode for an indefinite period. This is described in Figure 29-9 .

Figure 29-9. Self-refresh Mode Behavior

Self Refresh Mode T

XSR

= 3

SRCB = 1

Write

SDRAMC_SRR

SDRAMC_A[12:0]

Row

SDCK

SDCKE

SDCS

RAS

CAS

SDWE

Access Request to the SDRAM Controller

29.7.5.2

Low-power Mode

This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register.

Power consumption is greater than in self-refresh mode. All the input and output buffers of the

SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). As no auto-refresh operations are performed by the

SDRAM itself, the SDRAM Controller carries out the refresh operation. The exit procedure is faster than in self-refresh mode.

This is described in

Figure 29-10 .

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AT32AP7001

Figure 29-10. Low-power Mode Behavior

T

RCD

= 3

SDCS

SDCK

SDRAMC_A[12:0]

RAS

Row n

CAS = 2 col a col b col c col d col e col f

CAS

SDCKE

D[31:0]

(input)

Dna Dnb Dnc Dnd Dne Dnf

Low Power Mode

29.7.5.3

Deep Power-down Mode

This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register.

When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost.

When this mode is enabled, the application must not access to the SDRAM until a new initializa-

tion sequence is done (See ”SDRAM Device Initialization” on page 532

).

This is described in

Figure 29-11 .

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32015D–AVR32–10/07

Figure 29-11. Deep Power-down Mode Behavior

SDCS

SDCK

SDRAMC_A[12:0]

Row n col c col d

RAS

CAS

SDWE

CKE

D[31:0]

(input)

Dnb Dnc Dnd t

RP

= 3

AT32AP7001

540

29.8

SDRAM Controller User Interface

Table 29-8.

SDRAM Controller Memory Map

Offset Register

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

SDRAMC Mode Register

SDRAMC Refresh Timer Register

SDRAMC Configuration Register

SDRAMC High Speed Register

SDRAMC Low Power Register

SDRAMC Interrupt Enable Register

SDRAMC Interrupt Disable Register

SDRAMC Interrupt Mask Register

0x20

0x24

SDRAMC Interrupt Status Register

SDRAMC Memory Device Register

0x28 - 0xFC Reserved

AT32AP7001

Name

MR

TR

CR

HSR

LPR

IER

IDR

IMR

ISR

MDR

Access

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Write-only

Write-only

Read-only

Read-only

Read/Write

Reset State

0x00000000

0x00000000

0x852372C0

0x00

0x0

0x0

0x0

0x0

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AT32AP7001

29.8.1

SDRAMC Mode Register

Register Name:

Access Type:

Reset Value:

31

30

29

23

15

22

14

21

13

MR

Read/Write

0x00000000

28

20

12

27

19

11

26

18

10

25

17

9

24

16

8

7

6

5

4

3

2 1

MODE

0

MODE: SDRAMC Command Mode

This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.

Table 29-9.

0

MODE

0

0 0

0

0

1

1

1

1

1

0

0

1

0

1

0

1

0

1

0

Description

Normal mode. Any access to the SDRAM is decoded normally.

The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle.

The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of the cycle.

The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the cycle. The command will load the CAS latency from the Configuration Register and every other value set to 0 into the Mode Register.

The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of the cycle. Previously, an “All Banks Precharge” command must be issued.

The SDRAM Controller issues an extended load mode register command when the SDRAM device is accessed regardless of the cycle. The command will load the PASR, DS and TCR from the Low Power Register and every other value set to 0 into the Extended Mode Register.

Deep power-down mode. Enters deep power-down mode.

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32015D–AVR32–10/07

AT32AP7001

29.8.2

SDRAMC Refresh Timer Register

Register Name:

Access Type:

Reset Value:

31

30

29

TR

Read/Write

0x00000000

28

23

15

22

14

21

13

20

12

27

19

11

26

18

10

COUNT

25

17

9

24

16

8

7 6 5 4 3 2 1 0

COUNT

COUNT: SDRAMC Refresh Timer Count

This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate of the SDRAM device and the refresh burst length where 15.6 µs per row is a typical value for a burst of length one.

To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out.

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29.8.3

SDRAMC Configuration Register

Register Name:

Access Type:

Reset Value:

31 30 29

TXSR

CR

Read/Write

0x852372C0

28

23 22 21 20

TRCD

13 12 15 14

TRC

7

DBW

6

NC: Number of Column Bits

Reset value is 8 column bits.

CAS

5 4

NB

NC

0

0

1

1

0

1

0

1

NR: Number of Row Bits

Reset value is 11 row bits.

Column Bits

8

9

10

11

NR

1

1

0

0

0

1

0

1

NB: Number of Banks

Reset value is two banks.

Row Bits

11

12

13

Reserved

NB

0

1

Number of Banks

2

4

27

19

11

3

NR

26

TRAS

25

18 17

TRP

10 9

TWR

2 1

NC

24

16

8

0

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32015D–AVR32–10/07

AT32AP7001

CAS: CAS Latency

Reset value is two cycles.

In the SDRAMC, only a CAS latency of one, two and three cycles is managed.

1

1

0

0

CAS

0

1

0

1

CAS Latency (Cycles)

Reserved

1

2

3

DBW: Data Bus Width

Reset value is 16 bits

0: Data bus width is 32 bits.

1: Data bus width is 16 bits.

TWR: Write Recovery Delay

Reset value is two cycles.

This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.

TRC: Row Cycle Delay

Reset value is seven cycles.

This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0 and 15.

TRP: Row Precharge Delay

Reset value is three cycles.

This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 0 and 15.

TRCD: Row to Column Delay

Reset value is two cycles.

This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 0 and 15.

TRAS: Active to Precharge Delay

Reset value is five cycles.

This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 0 and 15.

TXSR: Exit Self Refresh to Active Delay

Reset value is height cycles.

This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is between 0 and 15.

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32015D–AVR32–10/07

AT32AP7001

29.8.4

SDRAMC High Speed Register

Register Name:

Access Type:

31

30

29

HSR

Read/Write

28

23

15

22

14

21

13

20

12

27

19

11

26

18

10

25

17

9

7

6

5

4

3

2

1

DA: Decode Cycle Enable

A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus.

The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory.

0: Decode cycle is disabled.

1: Decode cycle is enabled.

0

DA

24

16

8

546

32015D–AVR32–10/07

AT32AP7001

29.8.5

SDRAMC Low Power Register

Register Name:

Access Type:

Reset Value:

31

30

29

LPR

Read/Write

0x0

28

23

15

22

14

21

20

13

TIMEOUT

12

4 7

6 5

PASR

LPCB: Low-power Configuration Bits

27

19

11

3

DS

26

18

10

2

25

17

9

TCSR

24

16

8

1 0

LPCB

00

01

10

11

Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device.

The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access.

The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the

SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access.

The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM.

PASR: Partial Array Self-refresh (only for low-power SDRAM)

PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set according to the SDRAM device specification.

After initialization, as soon as PASR field is modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and PASR bits are updated before entry in self-refresh mode.

TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM)

TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device specification.

After initialization, as soon as TCSR field is modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and TCSR bits are updated before entry in self-refresh mode.

DS: Drive Strength (only for low-power SDRAM)

DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be set according to the SDRAM device specification.

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AT32AP7001

After initialization, as soon as DS field is modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and DS bits are updated before entry in self-refresh mode.

TIMEOUT: Time to define when low-power mode is enabled

00

01

10

11

The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer.

The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.

The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.

Reserved.

32015D–AVR32–10/07

548

AT32AP7001

29.8.6

SDRAMC Interrupt Enable Register

Register Name:

Access Type:

31

30

29

IER

Write-only

28

23

15

22

14

7

6

RES: Refresh Error Status

0: No effect.

1: Enables the refresh error interrupt.

5

21

13

20

12

4

27

19

11

3

26

18

10

2

25

17

9

1

24

16

8

0

RES

549

32015D–AVR32–10/07

AT32AP7001

29.8.7

SDRAMC Interrupt Disable Register

Register Name:

Access Type:

31

30

29

IDR

Write-only

28

23

15

22

14

7

6

RES: Refresh Error Status

0: No effect.

1: Disables the refresh error interrupt.

5

21

13

20

12

4

27

19

11

3

26

18

10

2

25

17

9

1

24

16

8

0

RES

550

32015D–AVR32–10/07

AT32AP7001

29.8.8

SDRAMC Interrupt Mask Register

Register Name:

Access Type:

31

30

29

IMR

Read-only

28

23

15

22

14

7

6

5

RES: Refresh Error Status

0: The refresh error interrupt is disabled.

1: The refresh error interrupt is enabled.

21

13

20

12

4

27

19

11

3

26

18

10

2

25

17

9

1

24

16

8

0

RES

551

32015D–AVR32–10/07

AT32AP7001

29.8.9

SDRAMC Interrupt Status Register

Register Name:

Access Type:

31

30

29

ISR

Read-only

28

23

15

22

14

21

13

20

12

7

6

5

4

3

RES: Refresh Error Status

0: No refresh error has been detected since the register was last read.

1: A refresh error has been detected since the register was last read.

27

19

11

26

18

10

2

25

17

9

1

24

16

8

0

RES

552

32015D–AVR32–10/07

AT32AP7001

29.8.10

SDRAMC Memory Device Register

Register Name:

Access Type:

31

30

29

MDR

Read/Write

28

23

15

22

14

7

6

MD: Memory Device Type

21

13

5

20

12

4

00

01

10

11

SDRAM

Low-power SDRAM

Reserved

Reserved.

27

19

11

3

26

18

10

2

25

17

9

1

MD

24

16

8

0

553

32015D–AVR32–10/07

AT32AP7001

30. Error Corrected Code (ECC) Controller

Rev: 1.0.0.0

30.1

Features

Hardware Error Corrected Code (ECC) Generation

– Detection and Correction by Software

Supports NAND Flash and SmartMedia

Devices with 8- or 16-bit Data Path.

Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes, Specified by Software

30.2

Description

30.3

Block Diagram

NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur which can be detected/corrected by ECC code.

The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data. The ECC controller is capable of single bit error correction and 2-bit random detection. When NAND Flash/SmartMedia have more than 2 bits of errors, the data cannot be corrected.

The ECC user interface is accesible through the peripheral bus.

Figure 30-1. Block Diagram

Static

Memory

Controller

NAND Flash

SmartMedia

Logic

ECC

Controller

Ctrl/ECC Algorithm

User Interface

Peripheral Bus

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32015D–AVR32–10/07

AT32AP7001

30.4

Functional Description

A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main data plus the number of words in the extra area used for redundancy.

The only configuration required for ECC is the NAND Flash or the SmartMedia page size

(528/1056/2112/4224). Page size is configured setting the PAGESIZE field in the ECC Mode

Register (MR).

ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND

Flash or the SmartMedia is detected. Read and write access must start at a page boundary.

ECC is computed as soon as the counter reaches the page size. Values in the ECC Parity Register (PR) and ECC NParity Register (NPR) are then valid and locked until a new start condition

(read/write command followed by five access address cycles).

30.4.1

30.4.2

Write Access

Read Access

Once the flash memory page is written, the computed ECC code is available in the ECC Parity

Error (PR) and ECC_NParity Error (NPR) registers. The ECC code value must be written by the software application at the end of the page, in the extra area used for redundancy.

After reading main data in the page area, the application can perform read access to the extra area used for redundancy. Error detection is automatically performed by the ECC controller. The application can check the ECC Status Register (SR) for any detected errors.

It is up to the application to correct any detected error. ECC computation can detect four different circumstances:

• No error: XOR between the ECC computation and the ECC code stored at the end of the

NAND Flash or SmartMedia page is equal to 0. No error flags in the ECC Status Register

(SR).

• Recoverable error: Only the RECERR flag in the ECC Status register (SR) is set. The corrupted word offset in the read page is defined by the WORDADDR field in the ECC Parity

Register (PR). The corrupted bit position in the concerned word is defined in the BITADDR field in the ECC Parity Register (PR).

• ECC error: The ECCERR flag in the ECC Status Register is set. An error has been detected in the ECC code stored in the Flash memory. The position of the corrupted bit can be found by the application performing an XOR between the Parity and the NParity contained in the

ECC code stored in the flash memory.

• Non correctable error: The MULERR flag in the ECC Status Register is set. Several unrecoverable errors have been detected in the flash memory page.

ECC Status Register, ECC Parity Register and ECC NParity Register are cleared when a read/write command is detected or a software register is enabled.

For single bit Error Correction and double bit Error Detection (SEC-DED) hsiao code is used. 32bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit

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words. Of the 32 ECC bits, 26 bits are for line parity and 6 bits are for column parity. They are

generated according to the schemes shown in Figure 30-2

and

Figure 30-3

.

Figure 30-2. Parity Generation for 512/1024/2048/4096 8-bit Words1

1st byte

2nd byte

3rd byte

4 th byte

Bit7 Bit6

Bit5

Bit4 Bit3

Bit2

Bit1

Bit0

Bit7

Bit6 Bit5

Bit4 Bit3

Bit2

Bit1

Bit0

Bit7

Bit6 Bit5

Bit4 Bit3 Bit2 Bit1 Bit0

Bit7 Bit6

Bit5

Bit4 Bit3

Bit2

Bit1

Bit0

P8

P8'

P8

P8'

P16

P16'

PX

(page size -3 )th byte

(page size -2 )th byte

(page size -1 )th byte

Page size th byte

Bit7

Bit6 Bit5

Bit4 Bit3

Bit2

Bit1

Bit0

Bit7 Bit6

Bit5

Bit4 Bit3 Bit2 Bit1 Bit0

Bit7 Bit6

Bit5

Bit4 Bit3

Bit2

Bit1

Bit0

Bit7

Bit6 Bit5

Bit4 Bit3

Bit2

Bit1

Bit0

P1

P2

P1'

P4

P1

P2'

P1'

P1

P2

P1'

P4'

P1

P2'

P1'

P8

P8'

P8

P8'

P16

P16'

P32

Page size = 512 Px = 2048

Page size = 1024 Px = 4096

Page size = 2048 Px = 8192

Page size = 4096 Px = 16384

P1=bit7(+)bit5(+)bit3(+)bit1(+)P1

P2=bit7(+)bit6(+)bit3(+)bit2(+)P2

P4=bit7(+)bit6(+)bit5(+)bit4(+)P4

P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1'

P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2'

P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'

To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.

Page size = 2 n

for i =0 to n

begin

for (j = 0 to page_size_byte)

begin

if(j[i] ==1)

P[2 i+3

]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)

bit2(+)bit1(+)bit0(+)P[2 i+3

]

else

P[2 i+3

]’=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)

bit2(+)bit1(+)bit0(+)P[2 i+3

]'

end

end

32015D–AVR32–10/07

PX'

556

Figure 30-3. Parity Generation for 512/1024/2048/4096 16-bit Words

AT32AP7001

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To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.

Page size = 2 n

for i =0 to n

begin

for (j = 0 to page_size_word)

begin

if(j[i] ==1)

P[2 i+3

]= bit15(+)bit14(+)bit13(+)bit12(+)

bit11(+)bit10(+)bit9(+)bit8(+)

bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)

bit2(+)bit1(+)bit0(+)P[2 n+3

]

else

P[2 i+3

]’=bit15(+)bit14(+)bit13(+)bit12(+)

bit11(+)bit10(+)bit9(+)bit8(+)

bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)

bit2(+)bit1(+)bit0(+)P[2 i+3

]'

end

end

AT32AP7001

558

30.5

ECC User Interface

Table 30-1.

ECC Register Mapping

Offset Register

0x00

0x04

0x8

0x0C

0x10

0x14-0xF8

0x14 - 0xFC

ECC Control Register

ECC Mode Register

ECC Status Register

ECC Parity Register

ECC NParity Register

Reserved

Reserved

AT32AP7001

Register Name

CR

MR

SR

PR

NPR

Access

Write-only

Read/Write

Read-only

Read-only

Read-only

Reset

0x0

0x0

0x0

0x0

0x0

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AT32AP7001

30.5.1

ECC Control Register

Name:

Access Type:

CR

Write-only

15

7

31

23

14

6

30

22

13

5

29

21

• RST: RESET Parity

Provides reset to current ECC by software.

0: No effect

1: Reset sECC Parity and ECC NParity register

12

4

28

20

11

3

27

19

10

2

26

18

1

9

25

17

24

16

0

8

RST

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AT32AP7001

30.5.2

ECC Mode Register

Register Name:

Access Type:

15

7

31

23

14

6

30

22

MR

Read/Write

13

5

29

21

12

4

28

20

11

3

27

19

10

2

26

18

9

1

25

17

PAGESIZE

8

0

24

16

• PAGESIZE: Page Size

This field defines the page size of the NAND Flash device.

Page Size Description

00 528 words

01

10

1056 words

2112 words

11 4224 words

A word has a value of 8 bits or 16 bits, depending on the NAND Flash or Smartmedia memory organization.

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30.5.3

15

7

31

23

ECC Status Register

Register Name:

Access Type:

14

6

30

22

SR

Read-only

13

5

29

21

12

4

28

20

11

3

27

19

26

18

10

2

MULERR

25

17

9

1

ECCERR

24

16

8

0

RECERR

• RECERR: Recoverable Error

0: No Errors Detected

1: Errors Detected. If MULERR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected

• ECCERR: ECC Error

0: No Errors Detected

1: A single bit error occurred in the ECC bytes.

Read both ECC Parity and ECC Parityn register, the error occurred at the location which contains a 1 in the least significant

16 bits.

• MULERR: Multiple Error

0: No Multiple Errors Detected

1: Multiple Errors Detected

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30.5.4

31

23

15

7

ECC Parity Register

Register Name:

Access Type:

30

22

14

PR

Read-only

29

21

13

6

WORDADDR

5

28

20

12

WORDADDR

27

19

11

4 3

26

18

10

25

17

9

2

BITADDR

1

24

16

8

0

During a page write, the value of the entire register must be written in the extra area used for redundancy (for a 512-byte page size: address 512-513)

• BITADDR

During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless.

• WORDADDR

During a page read, this value contains the word address (8-bit or 16-bit word depending on the memory plane organization) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless.

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30.5.5

7

ECC NParity Register

Register Name:

Access Type:

31

23

15

30

22

14

NPR

Read-only

6

29

21

13

5

28

20

12

4

NPARITY

27

19

11

3

NPARITY

26

18

10

2

25

17

9

1

24

16

8

0

• NPARITY:

During a write, the value of this register must be written in the extra area used for redundancy (for a 512-byte page size: address 514-515)

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AT32AP7001

31. MultiMedia Card Interface (MCI)

Rev: 2.1.0.1

31.1

Features

Compatible with MultiMedia Card Specification Version 2.2

Compatible with SD Memory Card Specification Version 1.0

Compatible with MultiMedia Card Specification Version 3.31

Compatible with SDIO Specification Version 1.1

Cards Clock Rate Up to Master Clock Divided by 2

Embedded Power Management to Slow Down Clock Rate When Not Used

Supports 2 Multiplexed Slot(s)

– Each Slot for either a MultiMediaCard Bus (Up to 30 Cards) or an SD Memory Card

Support for Stream, Block and Multi-block Data Read and Write

Supports Connection to DMA Controller

– Minimizes Processor Intervention for Large Buffer Transfers

31.2

Description

The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead.

The MCI supports stream, block and multi-block data read and write, and is compatible with a

DMA Controller, minimizing processor intervention for large buffer transfers.

The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface with a MultiMedia Card bus (up to 30 Cards) or with a

SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection.

The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMediaCard on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use).

The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology.

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31.3

Block Diagram

Figure 31-1. Block Diagram

Peripheral Bus Bridge

PDC / DMA

Peripheral

Bus

PM

MCK

MCI Interface

Interrupt Control

PIO

MCCK

(1)

MCCDA

(1)

MCDA0

(1)

MCDA1

(1)

MCDA2

(1)

MCDA3

(1)

MCCDB

(1)

MCDB0

(1)

MCDB1

(1)

MCDB2

(1)

MCDB3

(1)

MCI Interrupt

Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCI x CK, MCCDA to

MCI x CDA, MCDAy to MCIx DAy, MCDBy to MCIx DBy

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31.4

Application Block Diagram

Figure 31-2. Application Block Diagram

Application Layer ex: File System, Audio, Security, etc.

AT32AP7001

Physical Layer

MCI Interface

31.5

Pin Name List

Table 31-1.

I/O Lines Description

Pin Name

MCCDA/MCCDB

MCCK

MCDA0 - MCDA3

Pin Description

Command/response

Clock

Data 0..3 of Slot A

MCDB0 - MCDB3 Data 0..3 of Slot B

Note: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.

1 2 3 4 5 6 7

MMC

9

1 2 3 4 5 6 7 8

SDCard

Type

(1)

Comments

I/O/PP/OD CMD of an MMC or SD Card

I/O CLK of an MMC or SD Card

I/O/PP

I/O/PP

DAT0 of an MMC

DAT[0..3] of an SD Card

DAT0 of an MMC

DAT[0..3] of an SD Card

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AT32AP7001

31.6

Product Dependencies

31.6.1

31.6.2

31.6.3

I/O Lines

The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins.

Power Management

The MCI may receive a clock from the Power Manager (PM), so the programmer must first configure the PM to enable the MCI clock.

Interrupt

The MCI interface has an interrupt line connected to the Interrupt Controller (INTC).

Handling the MCI interrupt requires programming the INTC before configuring the MCI.

31.7

Bus Topology

Figure 31-3. MultiMedia Memory Card Bus Topology

1 2 3 4 5 6 7

MMC

The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines.

Table 31-2.

Bus Topology

4

5

6

7

1

2

3

Pin

Number Name

RSV

CMD

VSS1

VDD

CLK

VSS2

DAT[0]

Type

(1)

NC

I/O/PP/OD

S

S

I/O

S

I/O/PP

Description

Not connected

Command/response

Supply voltage ground

Supply voltage

Clock

Supply voltage ground

Data 0

MCI Pin Name

(Slot x)

MCCDx

VSS

VDD

MCCK

VSS

MCDx0

Note: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.

2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCI x CK, MCCDA to

MCI x CDA, MCDAy to MCIx DAy, MCDBy to MCIx DBy

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AT32AP7001

Figure 31-4. MMC Bus Connections (One Slot)

MCI

MCCDA

MCDA0

MCCK

1 2 3 4 5 6 7

MMC1

1 2 3 4 5 6 7

MMC2

1 2 3 4 5 6 7

MMC3

Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCI x CK, MCCDA to

MCI x CDA, MCDAy to MCIx DAy

Figure 31-5. SD Memory Card Bus Topology

9

1 2 3 4 5 6 7 8

SD CARD

The SD Memory Card bus includes the signals listed in

Table 31-3 on page 569 .

Table 31-3.

SD Memory Card Bus Signals

7

8

9

5

6

3

4

Pin Number Name

1

2

CD/DAT[3]

CMD

VSS1

VDD

CLK

VSS2

DAT[0]

DAT[1]

DAT[2]

Type

S

S

I/O

S

(1)

I/O/PP

PP

I/O/PP

I/O/PP

I/O/PP

Note: 1. I: input, O: output, PP: Push Pull, OD: Open Drain

Description

Card detect/ Data line Bit 3

Command/response

Supply voltage ground

Supply voltage

Clock

Supply voltage ground

Data line Bit 0

Data line Bit 1 or Interrupt

Data line Bit 2

MCI Pin Name

(Slot x)

MCDx3

MCCDx

VSS

VDD

MCCK

VSS

MCDx0

MCDx1

MCDx2

569

32015D–AVR32–10/07

AT32AP7001

Figure 31-6. SD Card Bus Connections with Two Slots

MCDA0 - MCDA3

MCCK

MCCDA

MCDB0 - MCDB3

MCCDB

SD CARD 1

SD CARD 2

Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCI x CK, MCCDA to

MCI x CDA, MCDAy to MCIx DAy, MCDBy to MCIx DBy

Figure 31-7. Mixing MultiMedia and SD Memory Cards with Two Slots

MCDA0

MCCDA

MCCK

1 2 3 4 5 6 7

MMC1

1 2 3 4 5 6 7

MMC2

1 2 3 4 5 6 7

MMC3

MCDB0 - MCDB3

SD CARD

MCCDB

Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCI x CK, MCCDA to

MCI x CDA, MCDAy to MCIx DAy, MCDBy to MCIx DBy

When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs.

570

AT32AP7001

31.8

MultiMedia Card Operations

31.8.1

After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens:

• Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command).

A command is transferred serially on the CMD line.

• Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line.

• Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line.

Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards.

The structure of commands, responses and data blocks is described in the MultiMedia-Card

System Specification. See also Table 31-4 on page 572 .

MultiMediaCard bus data transfers are composed of these tokens.

There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the MCI

Clock.

Two types of data transfer commands are defined:

• Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum.

• Block-oriented commands: These commands send a data block succeeded by CRC bits.

Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the

sequential read or when a multiple block transmission has a predefined block count ( See ”Data

Transfer Operation” on page 573.

).

The MCI provides a set of registers to perform the entire range of MultiMedia Card operations.

Command - Response Operation

After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the CR (MCI

Control Register).

The PWSEN bit saves power by dividing the MCI clock by 2

PWSDIV

+ 1 when the bus is inactive.

The two bits RDPROOF and WRPROOF in the MCI Mode Register (MR) allow stopping the MCI

Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.

The command and the response of the card are clocked out with the rising edge of the MCI

Clock.

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AT32AP7001

All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification.

The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The CMDR allows a command to be carried out.

For example, to perform an ALL_SEND_CID command:

CMD S T

Host Command

Content

N

ID

Cycles CID

CRC E Z ****** Z S T Content

The command ALL_SEND_CID and the fields and values for the CMDR Control Register are

described in Table 31-4 and Table 31-5

.

Table 31-4.

ALL_SEND_CID Command Description

CMD Index

CMD2

Type

bcr

Argument

[31:0] stuff bits

Resp Abbreviation

R2 ALL_SEND_CID

Command

Description

Asks all cards to send their CID numbers on the CMD line

Note: bcr means broadcast command with response.

Z Z Z

Table 31-5.

Fields and Values for CMDR Command Register

Field

CMDNB (command number)

Value

2 (CMD2)

RSPTYP (response type)

SPCMD (special command)

2 (R2: 136 bits response)

0 (not a special command)

OPCMD (open drain command) 1

MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles)

TRCMD (transfer command)

TRDIR (transfer direction)

TRTYP (transfer type)

0 (No transfer)

X (available only in transfer command)

X (available only in transfer command)

The ARGR contains the argument field of the command.

To send a command, the user must perform the following steps:

• Fill the argument register (ARGR) with the command argument.

• Set the command register (CMDR) (see

Table 31-5

).

The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (RSPR). The response size can be from

48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer.

572

AT32AP7001

The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (IER) allows using an interrupt method.

Figure 31-8. Command/Response Functional Flow Diagram

Set the command argument

MCI_ARGR = Argument

(1)

Set the command

MCI_CMDR = Command

Read MCI_SR

0

Wait for command ready status flag

Check error bits in the status register (1)

CMDRDY

1

Status error flags?

Yes

Read response if required

RETURN ERROR

(1)

RETURN OK

31.8.2

Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification).

Data Transfer Operation

The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI

Command Register (CMDR).

These operations can be done using the a DMA Controller.

In all cases, the block length (BLKLEN field) must be defined either in the mode register MR, or in the Block Register BLKR. This field determines the size of the data block.

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Enabling PDC Force Byte Transfer (PDCFBYTE in the MR) allows the PDC to manage with internal byte transfers, so that transfers of blocks with a size different from modulo 4 can be supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words, otherwise the type of transfers are in bytes.

Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time):

• Open-ended/Infinite Multiple block read (or write):

The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received.

• Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):

The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read

(or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the MCI Block Register (BLKR).

Otherwise the card will start an open-ended multiple block read. The BCNT field of the Block

Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer.

31.8.3

Read Operation

The following flowchart shows how to read a single block with or without use of DMA facilities. In this example, a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (IER) to trigger an interrupt at the end of read.

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AT32AP7001

Figure 31-9. Read Functional Flow Diagram

Send command SEL_DESEL_CARD to select the card

Send command SET_BLOCKLEN

No

Reset the PDCMODE bit

MCI_MR &= ~PDCMODE

Set the block length (in bytes)

MCI_MR |= (BlockLenght <<16)

Send command

READ_SINGLE_BLOCK

(1)

Read with DMA

Yes

Set the block length (in bytes)

MCI_MR |= (BlockLength << 16)

Configure the DMA controller

Send command

READ_SINGLE_BLOCK

(1)

Number of words to read = BlockLength/4

Wait for data from MMC

Yes

Number of words to read = 0 ?

No

Read status register MCI_SR

Data received?

No

Yes

Poll the bit

RXRDY = 0?

No

Read data = MCI_RDR

Number of words to read =

Number of words to read -1

Yes

DMA transfer complete ?

Yes

No

RETURN

RETURN

31.8.4

Note: 1. This command is supposed to have been correctly sent (see

Figure 31-8 ).

Write Operation

In write operation, the MCI Mode Register (MR) is used to define the padding value when writing non-multiple block size. If the bit DMAPADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used.

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The following flowchart shows how to write a single block with or without use of DMA facilities.

Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (IMR).

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Figure 31-10. Write Functional Flow Diagram

Send command SEL_DESEL_CARD to select the card

Send command SET_BLOCKLEN

No

Reset the PDCMODE bit

MCI_MR &= ~PDCMODE

Set the block length

MCI_MR |= (BlockLenght <<16)

Send command

WRITE_SINGLE_BLOCK

(1)

Write with DMA

Yes

Set the block length (in bytes)

MCI_MR |= (BlockLength << 16)

Configure the DMA controller

Send command

WRITE_SINGLE_BLOCK

(1)

Number of words to write = BlockLength/4

Wait for data transfer to MMC complete

Yes

Number of words to write = 0 ?

No

Read status register MCI_SR

Data transmitted?

No

Yes

Poll the bit

TXRDY = 0?

Yes

DMA transfer complete ?

No

No

MCI_TDR = Data to write

Number of words to write =

Number of words to write -1

Yes

RETURN

RETURN

Note:

1. It is assumed that this command has been correctly sent (see Figure 31-8

).

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31.9

SD Card Operations

31.9.1

31.9.2

The MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands.

SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. The physical form factor, pin assignment and data transfer protocol are forward-compatible with the MMC with some additions. SD slots can actually be used for more than flash memory cards. Devices that support SDIO can use small devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth adapters, modems, barcode readers, IrDA adapters, FM radio tuners, RFID readers, digital cameras and more.

SD/SDIO is covered by numerous patents and trademarks, and licensing is only available through the Secure Digital Card Association.

The SD/SDIO Card communication is based on a 9-pin interface (Clock, Command, 4 x Data and 3 x Power lines). The communication protocol is defined as a part of this specification. The main difference between the SD/SDIO Card and the MMC is the initialization process.

The SD/SDIO Card Register (SDCR) allows selection of the Card Slot and the data bus width.

The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power up, by default, the SD/SDIO Card uses only DAT0 for data transfer. After initialization, the host can change the bus width (number of active data lines).

SDIO Data Transfer Type

SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format

(1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The TRTYP field in the MCI Command Register (CMDR) allows to choose between SDIO Byte or SDIO

Block transfer.

The number of bytes/blocks to transfer is set through the BCNT field in the MCI Block Register

(BLKR). In SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not used in SDIO Byte mode.

An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing of access to the host among multiple devices,

SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the

SDIO Specification for more details). To send a suspend or a resume command, the host must set the SDIO Special Command field (IOSPCMD) in the MCI Command Register.

SDIO Interrupts

Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO interrupt on each slot can be enabled through the MCI Interrupt Enable Register. The SDIO interrupt is sampled regardless of the currently selected slot.

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31.10 MultiMedia Card Interface (MCI) User Interface

Table 31-6.

Register Mapping

Offset

0x20

0x24

0x28

0x2C

0x30

0x34

0x38 - 0x3C

0x40

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

0x44

0x48

0x4C

0x50-0xF8

0xFC

Control Register

Mode Register

Data Timeout Register

SD/SDIO Card Register

Argument Register

Command Register

Block Register

Reserved

Response Register

(1)

Response Register

(1)

Response Register

(1)

Response Register

(1)

Receive Data Register

Transmit Data Register

Reserved

Status Register

Interrupt Enable Register

Interrupt Disable Register

Interrupt Mask Register

Reserved

Version Register

RSPR

RSPR

RSPR

RSPR

RDR

TDR

SR

CR

MR

DTOR

SDCR

ARGR

CMDR

BLKR

IER

IDR

IMR

MCI_VERSION

Read

Read

Read

Read

Read

Write

Read

Write

Read/write

Read/write

Read/write

Read/write

Write

Read/write

Write

Write

Read

Read-only

0x0

0x0

0x0

0x0

0x0

0xC0E5

0x0

0x–

(2)

0x0

-

0x0

0x0

0x0

Note: 1. The response register can be read by N accesses at the same RSPR or at consecutive addresses (0x20 to 0x2C).

N depends on the size of the response.

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2. Values in the Version Register vary with the version of the IP block implementation.

31.10.1

MCI Control Register

Name: CR

Access Type: Write-only

31

30

29

23

15

7

SWRST

22

14

6

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

MCIEN: Multi-Media Interface Enable

0 = No effect.

1 = Enables the Multi-Media Interface if MCDIS is 0.

MCIDIS: Multi-Media Interface Disable

0 = No effect.

1 = Disables the Multi-Media Interface.

SWRST: Software Reset

0 = No effect.

1 = Resets the MCI. A software triggered hardware reset of the MCI interface is performed.

25

17

9

1

MCIDIS

24

16

8

0

MCIEN

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31.10.2

MCI Mode Register<