Digitally controlled low frequency square wave electronic ballast

Digitally controlled low frequency square wave electronic ballast
Digitally controlled low frequency square wave
electronic ballast
with resonant ignition and power loop
F. J. Díaz, F. J. Azcondo, Ch. Brañas, R. Casanueva
R. Zane
Electronics Technology, Systems and Automation
Engineering Department
University of Cantabria
Santander, Spain
{diazrf, azcondof, branasc, casanuer}@unican.es
Department of Electrical and Computer Engineering
University of Colorado at Boulder
Boulder, CO USA
[email protected]
Abstract— The paper proposes a digital controller for a low
frequency square wave (LFSW) electronic ballast implemented in
a dsPIC30F2010 microcontroller that includes: the ignition
sequence, a double control loop and the selection of the positive
and negative operation modes. The whole ballast is a two stage
circuit, where the first stage is a power factor correction (PFC)
stage and the second is a full-bridge converter (FB) used for both
ignition and square wave drive. Ignition is achieved by
approaching the resonant frequency of the LC filter when the
lamp is in the off-state and the FB is working as a resonant
inverter. After ignition the converter operates as a LFSW
inverter by controlling the FB to act alternately as a Buck
converter supplying positive or negative current. While ignition
occurs at the LC filter resonance (fo=25kHz), the Buck converter
switching frequency (fsw=200kHz) is selected significantly higher
than fo to attenuate high frequency harmonics and avoid exciting
acoustic resonance. Lamp stability is achieved by controlling the
inductor current of the LC filter, and power mode control is
achieved adjusting the average current and voltage supplied by
the PFC stage. A SEPIC converter operating in the continuous
conduction mode (CCM) is used for the PFC stage. The
microcontroller selects the different operation modes of the FB
converter according to the lamp requirements.
Keywords-Sepic converter; Buck converter; Low frequncy
square wave; Metal halide lamp; acoustic resonance.
I.
INTRODUCTION
The illumination industry is looking for new solutions to
avoid excitation of acoustic resonances [1] in discharged
lamps, especially in metal halide lamps (MHL). This kind of
lamp has become very popular as a practical light source for
general and specific applications for its high efficacy
(measured in lumens per watt) and for the creation of compact
lamps with superior color rendering properties. The frequencies
at which acoustic resonance appears depend on the size of the
arc tube, gas pressure and its composition. The elements that
compose the gas enclosed in the vessel determine the lamp
chromatic rendering; in this way, a more complete spectrum of
the source light requires a more complex composition of the
lamp gas that then presents more resonant modes. Square-wave
electronic ballast is an alternative to resonant converters and,
theoretically, is a solution to prevent the acoustic resonance
provided that the lamp power has no ac component. Standard
solutions for square-wave high-intensity discharge (HID) lamp
drivers over 100 W require three stages: (1) a power factor
correction (PFC) stage, (2) a current mode controlled dc-dc
converter and (3) a full bridge (FB) inverter, in addition to an
external lamp ignition circuit [2-3]. In this paper we propose
the digital control of a simple square-wave electronic ballast in
which, stages (2), (3) and the ignition circuit are integrated in a
single stage, as is depicted in Fig. 1. The use of a
microcontroller with a suitable digital control allows the FB to
work as a resonant inverter during the start-up and warm-up of
the lamp and as a LFSW inverter during the steady state of the
lamp.
Electronic ballast should also meet the IEC 61000 3-2 class
C focused on lighting electronic equipment [4]. For high power
lamps a PFC stage is commonly used to meet the utility
standard and to reject the utility disturbance to a certain degree,
and the Boost converter is commonly used. However the boost
output DC voltage has to be set to be greater than the input line
peak voltage (normal greater than 400V). In some applications
where an intermediate output voltage level is required,
converter with step-up and step-down conversion ratio is
needed. In this way, the ballast system has a Single-Ended
Primary Inductance Converter (SEPIC) configured as a nonisolated high power factor preregulator in continuous
conduction mode (CCM).
This paper describes the design of amplitude-modulated
control of the electronic ballast using the PFC stage to regulate
the power supplied by the utility line while the LFSW
stabilizes lamp current. In comparison to [5] no extra sensor is
required to achieve power mode control because the output
voltage is required for PFC action.
The control law used during normal lamp operation to
generate the FB duty cycle d and the PFC reference current Iin
is depicted in the functional block diagram in Fig. 2. System
stability in short-term, i.e. ballast action, and long-term power
control, including dimming capability, are achieved with a
double control: a fast control that provides stability to the lamp,
controlling the average inductor current, i, and adjusts the duty
cycle, d (D in steady-state). The second low-speed control is a
power-mode control that regulates the average power, <Pg>
supplied by PFC stage. Both control loops use the same sensor
resistor Rg, for sampled current, and power loop use Rvd for
sampled of Vg, see Fig. 1.
Stage 1
Stage 2 with igniter
ig
S1
+
220Vac ~
50Hz
D3
D1
+
Rvi
PFC
L
i
S3
v C
Vg
Rlamp
-
S2
Rvd
D4
D2
S4
Rg
Fig. 1. Square-wave electronic ballast. Stage 1 is a Power Factor Corrector
stage, and stage 2 is a full bridge that works as a resonant inverter or low
frequency square wave inverter according to the state of the lamp.
z −1
Rs i
Vsen
Ig
-
ADC
kp
+
DAC
1 − z −1
I in
Pg,ref
Vgsen
ADC
1
Reqd
Iref
+-
kc
d
Fig. 2. Block diagram of the proposed digital control: power loop and inductor
current loop.
II. LFSW ELECTRONIC BALLAST
A front-end PFC stage supplies constant dc voltage, Vg, to
the FB converter, and operates in voltage mode, with
maximum Vg, when the lamp is off and during the start-up and
warm-up time, until the target power is achieved. Then PFC
stage operates in power mode supplying constant power, Pg.
The microcontroller selects the operation mode of the PFC
stage.
Also, the microcontroller imposes different operation
modes on the bridge converter to operate initially as a resonant
igniter, and then as a positive and negative Buck converter. The
bridge converter, inductor L and capacitor C form a parallel
resonant inverter before the lamp ignition, where the control
circuit defines a soft start-up ignition sequence by performing a
frequency sweep towards parallel resonance [6].
During the ignition sequence, resonant inverter operation is
obtained since the transition from positive to negative and vice
versa in the converter output voltage is carried out at high
frequency. This frequency is called the inverter switching
frequency, fisw, which, in this mode, is higher than the resonant
frequency, fo, of the LC filter (see Fig. 1) when the lamp is off
and gradually approaches fo, where the voltage gain is high
enough to produce the discharge. One benefit of sweeping the
frequency for ignition is that the capacitive coupling induces
current through the lamp gas and reduces the required over
voltage to achieve ignition [7-8].
Part of the lamp warm-up is also carried out using the high
frequency inverter mode. During ignition and initial warm-up
the duty cycle control is disabled and the converter operates as
a traditional full-bridge resonant inverter.
Then, the control circuit enters in LFSW mode, where the
bridge converter is driven alternately as a positive and negative
Buck converter. The inverter switching frequency, fisw, is in this
mode a constant low frequency. The square wave oscillator
imposes 50% of the low frequency period Ti = 1/fisw to change
from, positive to negative mode and vice versa. On the other
hand, the Buck converter switching frequency, fsw = 1/T >> fo,
is also constant. Control signals of the FB transistors for the
Buck operation modes are defined in Fig. 3. In the LFSW
mode, the duty cycle, d=ton/T, is regulated to control the
inductor current, i, and stabilize the lamp current in the short
term, and to regulate <Pg> in the long term for power
adjustment and dimming control if required.
In LFSW operation, the inductor L and the capacitor C
define the converter low pass filter that limits the ac component
of the lamp power below the level that can excite acoustic
resonances. Current mode control is achieved by regulating
inductor current i, which is the PFC output current ig during
DT, sensed by Rg. The inductor current, i, circulates as is
showed in Fig. 4; with continuous line during dT time, and
discontinuous line during (1-d)T time. Also, Fig. 4 shows the
Buck operation mode: above the positive Buck (positive lamp
current) and below negative Buck (negative lamp current). On
the other hand, power mode control is achieved multiplying the
PFC average output current, <ig>, and voltage, Vg.
Since the Buck converter input current, ig, is discontinuous,
the sampled inductor current, i*, is multiplied by d to obtain the
sampled average input current <ig*>. The inner high-speed
current loop provides the ballast action since it stabilizes the
lamp current, which is assumed to be equal to the averaged
inductor current, <i>, resulting in high output impedance for
the inverter. The outer power loop provides the current
reference, iref, to the inductor current loop to achieve the
designed lamp power, Plamp. The power sample data is
Pg*=Vg*<ig*>. The power mode control [9] does not
necessitate high-speed performance in the controller.
To simplify the current loop design with no influence on
the measured current conditioner, the generation of open-loop
transitions from positive to negative current through the lamp
and vice-versa is proposed. If the duty cycle does not change
during the transition from positive to negative output voltage
and vice versa, the transition response depends on the quality
factor of the filter loaded with the lamp. The control circuit
should detect the end of the transition to retake control of the
current and power mode
UC3854, Vff is the feedforward voltage from vin, and Imo
represents the input line current to control, i.e. output of the
UC3854 multiplier. The sample of output voltage is defined by
vGS1
vGS1
ON
OFF
t
vGS2
t
vGS2
OFF
OFF
ON
ON
Vgsen = Vg
OFF
t
t
vGS3
vGS3
OFF
t
vGS4
vGS4
OFF
ON
DT
T
L1
OFF
OFF
ON
DT
t
T
ig
+
Vg
D3
D1
i
+
Rvi
220Vac
50Hz
L
S3
+ v -
Iin
DAC
C
Rci
Rlamp
S2
D4
D2
-
dsPIC
Cpk
Rvf
S4
Rff1
Rvac
Ccz
Cvf
Rpk1
Ccp
1u
S1
+
Vg
D3
D1
i
L
S3
S2
D2
+ v -
16
6
8
1
13
14 12
9
120
Cff1
Rff3
33k
Cff2
Css
Ct
Rset
C
D4
Fig. 5. Scheme of the SEPIC converter controlled by UC3854A
S4
CC
iac
Fig. 4. Input (ig) and inductor (i) current direction. In continuous line during
DT time, and discontinuous line during (1-D)T time. Above, positive Buck.
Below, negative Buck.
L1
+
vin
-
iQ
iC1
M
iD
i2
L2
Ig +
iC2
Cg
Req
Rs
PFC STAGE: SEPIC CONVERTER
For practical implementation, in this work the SEPIC
converter operating in CCM is the chosen PFC stage, whose
implementation under voltage and power mode control is using
the circuit UC3854A. The complete scheme of the SEPIC
converter controlled by UC3854A is shown in Fig.5
The PFC controller requires sensing of the input current, iin,
input voltage, vin, and output voltage, Vg. The SEPIC control
circuit and its sampled signals are summarized in Fig.6. for the
digital power mode controller requires sampling of the output
current and voltage, Ig and Vg respectively. The first is obtained
from the current loop, <ig*>, and the sample of output voltage,
Vgsen, is necessary for operation of UC3854A. The equation that
defines the operation mode of the controller is
.
54 32
10
11 UC3854A
D1N5818
Rg
I AC (Vvea − 1)
V ff2
157
Rff2
Rlamp
-
Vg
Rpk2
Rcz
18Vdc
ig
I mo =
Cg
Vgsen
100u 150k
III.
L2
Rs
Rg
PFC
+
M
Cin
Rmo
-
220Vac
~
50Hz
D
Rvd
S1
PFC
CC
t
Fig. 3. Control signals of the FB transistors. Left: for positive lamp current
(positive Buck). Right: for negative lamp current (negative Buck).
220Vac
~
50Hz
(2)
The PFC stage works as limited output voltage source, Vg =
380 Vdc, of the FB during the start-up and warn-up of the lamp,
and then works as power source during the steady state..
ON
t
Rvd .
Rvd + Rvi
(1)
Where IAC is the instant input voltage sampled as a current
signal, Vvea is the output of the voltage error amplifier of
-
Iin
UC3854A
Vg
dsPIC
+
DAC
Rvi
+
Rvd
Vgsen
-
Fig. 6. SEPIC converter with necessary sensor for power control.
IV. CURRENT MODE AND POWER MODE OPERATION
The implementation of a suitable regulation of the lamp
should result in a double actuation. On the one hand, the ballast
needs to stabilize the lamp in the short term, and on the other
hand, it needs to have the capacity to fix the power of the lamp
in medium and long term.
Here it is proposed use a fast current mode control [10-11]
that stabilizes the lamp and power mode control that fixes the
nominal lamp power and implements dimming control when
required.
In order to achieve that the FB converter emulates an
equivalent resistance load, Req, for the PFC section the duty
cycle command is obtained from a high speed current loop,
where the input current reference, Iref, is defined as Vg/Req by
the control system. Therefore, the low frequency ac load for the
PFC is a positive resistance, Req. On the other hand the PFC
outer loop is a power mode control loop. The FB current loop
does not require the zero error specification and provides the
system with the required stability even for very irregular load,
e.g. discharges using a fast proportional current controller.
Computational resources are required for the integral action
and voltage limitation in the PFC power mode control, but with
low speed requirements they are solved by a low cost dsPIC
processor. A single sensor, Rg, samples the average value of the
inductor current during the on time, for both the PFC and FB
converter control loops and a voltage divider samples the PFC
output voltage, Vgsen.
If it is assumed that the ripple of the PFC output voltage,
Vg, is negligible, then the averaged model equation is described
by
dVg − v
Ts
sL
= i
Ts
.
(3)
sL
(4)
Equation (4) can be used to analyze the effects of the
perturbations of the duty cycle and output voltage on the
inductor current, i. The desired small-signal control transfer
function from duty cycle to inductor current can then be
derived including (5) in (4) and is given by (6)
vˆ = iˆ
20
15
10
5
0
-5
-10
0
-45
-90
2
10
3
zlamp
1 + sCzlamp
4
10
10
(5)
5
10
Frequency (Hz)
Fig. 7. Estimated Bode plot of Gid(s). Above: gain in dB. Below: phase.
Power mode control is easily implemented since
(7)
and
,
(8)
= Req ,
(9)
ig = d i
Vg
= iˆ
(6)
Bode Diagram
25
Plamp = ηlfsw ⋅ Vg ⋅ < ig >= ηlfsw ⋅ Pg ,
The average inductor current <i> is the variable to control for
the current mode control. The resulting averaged small signal
model is given by
ˆ − vˆ
dV
g
V
1 + sCzlamp
iˆ
= g
dˆ zlamp 1 + s L + s 2 LC
zlamp
Where zlamp is the lamp incremental impedance. The gain
and phase of the transfer function given in (6) is represented by
a continuous line in Fig. 7. The model (6) is valid in this case
in a rather restricted range of frequencies. Because of the
nature of the averaged model maximum valid frequency is half
the switching frequency and due to the lamp behavior the
frequency where zlamp behaves as positive impedance has a
minimum. For the case presented it is consider that Gid in (6) is
valid from 1 kHz to 100 kHz. The desired cross-over frequency
is going to be fixed in a range from 3 kHz to 10 kHz. To obtain
the plots in Fig. 7, zlamp is considered a positive resistance of
around 30 Ω [12-13] at the frequency of interest,. From this
result, a suitable compensator can be designed.
Magnitude (dB)
The two control variables of a PFC plus FB converter
systems are: the command signal of the PFC outer loop that
regulates the amplitude of the PFC input current, Iin, i.e. line
current, and the control signal of the FB converter that results
in the duty cycle, d, of the switching period, as is presented in
Figs. 1 and 2.
Gid (s ) =
Phase (deg)
In LFSW mode, i = ig during DT (on time), the inductor
current can be captured at Rg (see Fig. 1) for the current loop.
As mentioned above, power mode control is implemented by
taking a sample of Vg, Vgsen from Fig. 6, and multiplying by
<ig*>, that is the sample of <ig> and is calculated by
multiplying the sampled inductor current, i*, by the duty cycle,
d. Therefore, the power control variable is the PFC output
power, Pg.
ig
where ηlfsw is the efficiency of the LFSW converter and the
reference for the average inductor current, Iref, (see Fig. 2) is
the variable under control for power mode operation.
In Fig. 8, the transistor drive signal, vgs, the input current, ig,
and its sample, Rgig=vsen, are shown. The buck converter is
working in continuous conduction mode and ∆i is small, so that
one sample during DT is valid to obtain the average inductor
current with small enough error.
load, rL, is negative. In Fig. 9 Iˆg is the perturbation of the
current supplied to the PFC output filter and load averaged
over the utility line period, ro = −Vˆg Iˆg is the output
impedance and Cg the filter capacitor. For a constant power
load if the input voltage of that stage is reduced it will react by
increasing the current, in order to maintain the output power
constant. In this case rL will cancel with r0 and will yield:
Vsen
DT
i
g
T
t
∆i
<ig>
DT
T
Vˆg
1
=
ˆI
sCg
g
t
Vgs
(12)
+
DT
T
t
Fig. 8. Top: measured input current, Vsen=igRg. Middle: input current, ig.
Bottom: transistor drive signal, vgs.
Controlled transition from positive to negative lamp current
and vice versa may result in a slow transient that might
produce reignition, flickering effect and low frequency
harmonics. As an example, in [14] a PWM controller
modulates the output current with a square wave whose rising
time is several times that of the Buck converter switching
period. Here, to achieve a fast transient, an open-loop transition
is proposed.
As L and C form a low pass filter loaded with Rlamp, the step
response depends on the quality factor. If the quality factor, Q,
is between 0.4 and 1.2 [5], the desired output voltage step
response from positive to negative and vice versa is obtained.
A continuous time equivalent for the digital inductor
current control loop gain, Td, is
Td ( s ) = Gc ( esT1 ) H ( s )Gid ( s )e− std
,
(10)
where Gc is the discrete-time compensator with z = esT1,
− st d
T1=2/fsw is the sampling period, and e
represents the total
delay of the controller from the input current sampling instant
to time of corresponding duty cycle actuation. The sample
constant is H(s) = 0.25. The sample frequency is set half of the
Buck converter switching frequency, with sampling instants
just prior to the end of the duty cycle. The gain of the input
current A/D converter and DPWM are assumed to be unity.
Based on Gid(s) given in (6), shown in Fig. 7, inductor
current loop requires a simple proportional compensator to
stabilize the electrical discharge, at suitable bandwidth.
Assuming a total controller delay of one sample, td = T, and a
desired loop gain crossover frequency of fc = 5 kHz, a suitable
compensator [15] is given by Gc(s) = 0.5 and the corresponding
digital current control algorithm is given by
d [n ] = 0.5(i * [n ] − iref )
.
(11)
The common application of PFC regulators is to supply
constant voltage to the subsequent converters while shaping the
input current. It is known that the control of dc to dc converters
supplied by PFC sections results in an equivalent constant
power load for the PFC, therefore the equivalent small signal
δ Ig
ro
Cg
rL
δ Vg
-
Fig. 9. Small signal model for the PFC at the frequency of interest for the
power loop.
A suitable compensator is given by
G p ( s ) = 0.012
s + 400
s
(13)
Zero-order hold (ZOH) was used for z-transform [13-14] of
the Gp(s) and the corresponding digital power control algorithm
is given by
iin max [n ] = iin max [ n − 1] + 0.012[ Pg − Pgref ]
(14)
V. PRACTICAL IMPLEMENTATION
The converter operation is summarized in the flowchart of
the dsPIC30F2010 program in Fig. 10. Four operation modes
may be distinguished to provide the corresponding drive
signals for the switches:
a) Soft start-up ignition sequence mode
The frequency sweep from 100 kHz to 20 kHz is performed
for the FB resonant inverter. If needed, the sweep is repeated
until the lamp ignition is achieved.
b) Warm-up mode
When the lamp ignition is detected, the circuit provides a
fixed switching frequency slightly above the unloaded resonant
frequency during a specified period.
c) LFSW: Positive Buck mode.
After warm-up, the control circuit establishes an alternate
operation of the FB inverter as a positive and negative Buck
converter with a frequency of 200 Hz. A dead time is included
to assure safe operation. Positive Buck mode is achieved when
the control circuit turns S1 on and S2 off, S3 is also turned off
and the drive signal of S4 is provided at a switching frequency
of 200 kHz with the corresponding duty cycle.
d) LFSW: negative Buck mode.
Is achieved, analogously, when the control circuit turns S3
on, S4 off and S1 off and the corresponding drive signal of S2
is generated. In positive and negative buck mode, an inductor
current control and power mode control is activated.
During the Soft start-up ignition sequence mode and
Warm-up mode, the SEPIC converter is working as voltage
source and then change to works as power source.
Start
Rcz = 8.2 kΩ, Ccz =820 pF, Ccp =220 pF, Rff1 =820 kΩ,
Rff2 =82 kΩ, Rff3 =20 kΩ, Cff1 =100 nF, Cff2 =470 nF, Rs= 0.25
Ω the target Pg being 160 W.
Experimental results include the utility line waves in Fig.
11, the resonant lamp ignition sequence in Fig. 12 and, square
wave operation in Fig. 13. A transition from positive to
negative current through the lamp under no control is showed
in Figs. 14.
Modify Iin
No
Initialize PIC
Modify iref
Yes
Pg =Pgref ?
Yes
Iref[n]=Vgsen /Req d[n-1]
No
Lamp ON?
No
Modify d
Vsen<Vmin?
Yes
Soft start-up
sequence
Yes
Lamp ON?
d[n]=kcec
RI at constant
frequency
LFSW
mode
Delay
No
Increase ignition
counter
No
Count max?
No
Counter=0?
Yes
Yes
Fig. 11
SEPIC operation. Yellow, line voltage. Blue, line current.
Stop
End
Fig. 10. Control program flowchart.
VI. EXPERIMENTAL RESULTS
Next, experimental results are shown as verification of the
proposal, the implementation of LFSW electronic ballast with
double control, in this case for 150 W MH lamp (SYLVANIA)
HSI-TD Metalarc and 150W HPS lamp ( PHILIPS), whose
nominal electrical parameters are: Vlamp = 100 Vrms, Ilamp = 1.5
Arms. The digital control circuit is implemented in a
dsPIC30F2010 whose work frequency is 120 MHz. This dsPIC
have some especial characteristic as 6 PWM outputs and ADC
with 10 bits resolution, 154ns sample and hold time and 2 µs
conversion time. A MAX550A DAC is used for control of Iin
from Fig. 2.
The FB, shown in Fig. 1, that controls the target power, has
been built using IGBT’s HGTP12N60A4D that include an ultra
fast diode to implement the switches S1-D1 and S3-D3. The
switches S2 and S4 are MOSFETs IRFP340. Gate drive signals
are generated with two IR2110 drivers. The inductor (1.3 mH)
of the LC filter uses an E42 core size, material N27 and the
capacitor is a 1600V MKP, 47nF. The number of turns of the
inductor L is calculated to prevent core saturation during the
ignition sequence, where the flux density in the core is
maximal. On the other hand, the copper section is calculated
according to the inductor current in steady-state.
On the other hand, the PFC stage uses the following
component values referring to Figs. 5 and 6: L1 = L2 = 400 µH,
inductors are coupled in the same soft saturation Kool Mu core,
Cg = 680 µF, Cin = 1 µF, Cc = 330nF, Rvi = 1.2 MΩ,
Rvd =8.2 kΩ, Rvf = 150 kΩ, Cvf = 100 nF, Rmo = Rci = 9.5 kΩ,
Fig. 12. Start-up for 150W HPS lamp. Above: lamp voltage. Below: lamp
current.
Fig. 13. Experimental waveforms steady-state operation. Upper: lamp
voltage, middle: lamp current, lower: lamp power.
REFERENCES
[1]
[2]
[3]
[4]
[5]
Fig. 14. Transitions from positive to negative current through the lamp that
depends on the quality factor of the filter.
VII. CONCLUSIONS
A new digital control for low-frequency square-wave
ballast using a single FB circuit for both low-frequency drive
and resonant lamp ignition has been presented. The ballast
system uses a SEPIC PFC stage that regulates the steady-state
lamp power while the control of the next stage stabilizes the
light discharge. One of the benefits of this electronic ballast is
the reduction of components due to use of digital control and
fewer power stages than similar ballast, and the lower output
voltage of the PFC section. In this way, the proposed converter
is a universal solution for different lamps of the same wattage
(HPS and MHL). The converter is digitally controlled to define
three operation modes: as a resonant inverter close to the
resonant frequency to achieve the lamp ignition and initiate the
warm-up, and as a positive and negative Buck converter. The
Buck converter operation is input current controlled with high
output impedance, as is required to stabilize the lamp operation
in the short term (ballast action) and also to provide constant
lamp power during the lamp lifetime (long term). Transitions
from positive to negative Buck converter and vice versa are
performed in open-loop to obtain a fast response. The design of
the LC filter assures a quality factor that limits the resonant
current during the ignition and generates non-controlled
transitions of the low-frequency square-wave around the
critically damped behavior. Experimental results confirm the
system stability with different lamp types and aging. No light
arc distortion has been observed, and lamp power is accurately
established in nominal conditions and under dimming control
operation.
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
ACKNOWLEDGMENT
This work is co-sponsored by the Spanish Government
through the project CICYT TEC 2004-02607/MIC "Power
systems for discharge lamps and electrical discharge
machining" and the National Science Foundation (under Grant
No. 0348772).
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