S6B0723 V09

S6B0723 V09
S6B0723
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
June. 2000.
Ver. 0.9
Prepared by: Kyu-tae, Lim
[email protected]
Contents in this document are subject to change without notice. No part of this document may be reproduced or
transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written
permission of LCD Driver IC Team.
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
S6B0723 Specification Revision History
Version
0.0
Content
Initial version
Date
1998
1. VDD level changed(1.8V ~ 3.6V → 2.4V ~ 5.5V)
2. Power save mode changed (compound instruction)
0.1
3. Oscillator ON command deleted
4. Vref voltage changed (1.4V → 2.1 V)
Mar.1999
5. Internal resistor (Ra / Rb) ratio changed
6. n-line inversion deleted
0.2
1. PAD name changed (VSS → TEST4)
Mar.1999
0.3
1. Eq2. changed (page 32)
Mar.1999
0.4
1. figure 10. figure 11. changed
Mar.1999
0.5
1. Set static indicator register changed (page 46)
1. Modify following sections
Introduction, Features, Pad Configuration, Pin Description,
Power Supply Circuits, Reference Circuit Examples,
DC/AC Characteristics, Connection Between S6B0723 and LCD Panel
Apr.1999
0.7
1. S6B0723 Application circuit is changed(page 65~67)
Aug.1999
0.8
1. Operating VDD range is changed
Oct.1999
0.9
1. READ timing is changed(Figure 5)
Jun.2000
0.6
2
Apr.1999
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION ..................................................................................................................................................1
FEATURES ..........................................................................................................................................................1
BLOCK DIAGRAM ...............................................................................................................................................3
PAD CONFIGURATION .......................................................................................................................................4
PAD CENTER COORDINATES............................................................................................................................5
PIN DESCRIPTION ..............................................................................................................................................8
POWER SUPPLY..........................................................................................................................................8
LCD DRIVER SUPPLY..................................................................................................................................8
SYSTEM CONTROL .....................................................................................................................................9
MICROPROCESSOR INTERFACE .............................................................................................................11
LCD DRIVER OUTPUTS .............................................................................................................................13
FUNCTIONAL DESCRIPTION............................................................................................................................14
MICROPROCESSOR INTERFACE .............................................................................................................14
DISPLAY DATA RAM (DDRAM) ..................................................................................................................18
LCD DISPLAY CIRCUITS............................................................................................................................21
LCD DRIVER CIRCUITS .............................................................................................................................24
POWER SUPPLY CIRCUITS ......................................................................................................................25
REFERENCE CIRCUIT EXAMPLES ...........................................................................................................32
RESET CIRCUIT .........................................................................................................................................34
INSTRUCTION DESCRIPTION...........................................................................................................................35
SPECIFICATIONS..............................................................................................................................................50
ABSOLUTE MAXIMUM RATINGS...............................................................................................................50
DC CHARACTERISTICS.............................................................................................................................51
AC CHARACTERISTICS .............................................................................................................................54
REFERENCE APPLICATIONS...........................................................................................................................58
MICROPROCESSOR INTERFACE .............................................................................................................58
CONNECTIONS BETWEEN S6B0723 AND LCD PANEL ............................................................................59
S6B0723 APPLICATION CIRCUIT (6800 / 8080 / SERIAL) .........................................................................65
TCP PIN LAYOUT (SAMPLE)......................................................................................................................68
3
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The S6B0723 is a single-chip driver & controller LSI for graphic dot-matrix liquid crystal display systems. This chip
can be connected directly to a microprocessor, accepts serial or 8-bit parallel display data from the microprocessor,
stores the display data in an on-chip display data RAM of 65 x 132 bits and generates a liquid crystal display drive
signal independent of the microprocessor. It provides a high-flexible display section due to 1-to-1 correspondence
between on-chip display data RAM bits and LCD panel pixels. It contains 65 common driver circuits and 132
segment driver circuits, so that a single chip can drive a 65 x 132 dot display. And the capacity of the display can be
increased through the use of master/slave multi-chip structures. This chip is able to minimize power consumption
because it performs display data RAM read/write operation with no external operation clock. In addition, because it
contains power supply circuits necessary to drive liquid crystal, which is a display clock oscillator circuit, high
performance voltage converter circuit, high-accuracy voltage regulator circuit, low power consumption voltage
divider resistors and OP-Amp for liquid crystal driver power voltage, it is possible to make the lowest power
consumption display system with the fewest components for high performance portable systems.
FEATURES
Display Driver Output Circuits
−
65 common outputs / 132 segment outputs
On-chip Display Data RAM
−
−
−
Capacity: 65 x 132 = 8,580 bits
RAM bit data “1”: a dot of display is illuminated.
RAM bit data “0”: a dot of display is not illuminated.
Applicable Duty Ratios
Duty ratio
Applicable LCD bias
Maximum display area
1/65
1/7 or 1/9
65 × 132
1/55
1/6 or 1/8
55 × 132
1/49
1/6 or 1/8
49 × 132
1/33
1/5 or 1/6
33 × 132
Microprocessor Interface
−
−
High-speed 8-bit parallel bi-directional interface with 6800-series or 8080-series
Serial interface (only write operation) available
Various Function Set
−
−
−
Display ON / OFF, set initial display line, set page address, set column address, read status, write / read display
data, select segment driver output, reverse display ON / OFF, entire display ON / OFF, select LCD bias,
set/reset modify-read, select common driver output, control display power circuit, select internal regulator
resistor ratio for V0 voltage regulation, electronic volume, set static indicator state.
H/W and S/W reset available
Static drive circuit equipped internally for indicators with 4 flashing modes
1
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Built-in Analog Circuit
−
−
−
−
−
−
On-chip oscillator circuit for display clock (external clock can also be used)
High performance voltage converter (with booster ratios of x2, x3, x4 and x5, where the step-up reference
voltage can be used externally)
High accuracy voltage regulator (temperature coefficient: -0.05%/°C or external input)
Electronic contrast control function (64 steps)
Vref = 2.1V ± 3% (V0 voltage adjustment voltage)
High performance voltage follower (V1 to V4 voltage divider resistors and OP-Amp for increasing drive
capacity)
Operating Voltage Range
−
−
Supply voltage (VDD): 2.4 to 3.6V
LCD driving voltage (VLCD = V0 - VSS): 4.5 to 15.0V
Low Power Consumption
−
−
Operating power: 40µΑ typical (conditions: VDD = 3V, x 4 boosting (VCI = VDD), V0 = 11V, Internal power supply
ON, display OFF and normal mode is selected)
Standby power: 10 µΑ maximum (during power save[standby] mode)
Operating Temperatures
−
Wide range of operating temperatures : -40 to 85°C
CMOS Process
Package Type
−
2
TCP
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
BLOCK DIAGRAM
COMS
COM63
:
COM32
SEG131
33 COMMON
DRIVER
CIRCUITS
COMMON OUTPUT
CONTROLLER CIRCUIT
V/F
CIRCUIT
PAGE
I/O
ADDRESS
BUFFER
CIRCUIT
V0
VR
INTRS
REF
VEXT
SEG130
:
132 SEGMENT
DRIVER CIRCUITS
DISPLAY DATA
CONTROL CIRCUIT
HPMB
SEG129
:
SEG2
SEG1
33 COMMON
DRIVER
CIRCUITS
SEG0
:
COM31
COM0
COMS
VDD
V0
V1
V2
V3
V4
VSS
V/R
CIRCUIT
DISPLAY DATA RAM
65 X 132 = 8,580 Bits
LINE
ADDRESS
CIRCUIT
DISPLAY
TIMING
GENERATOR
CIRCUIT
MS
CL
M
FRS
FR
DISP
DUTY0
DUTY1
OSCILLATOR
CLS
COLUMN ADDRESS
CIRCUIT
VOUT
C1C1+
C2C2+
C3+
C4+
VCI
V/C
CIRCUIT
STATUS REGISTER
INSTRUCTION REGISTER
BUS HOLDER
INSTRUCTION DECODER
MPU INTERFACE (PARALLEL & SERIAL)
TEST1
TEST2
TEST3
DB0
DB1
DB2
DB3
DB4
DB5
DB6(SCLK)
DB7(SID)
C68
RESETB
PS
RW_WRB
E_RD
RS
CS2
CS1B
Figure 1. Block Diagram
3
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
PAD CONFIGURATION
137
296
ððð ððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððð ððð
Y
S6B0723
(TOP VIEW)
(0,0)
X
ðððððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððððððð
1
ðððð- - - -ðððð
307
ðððð- - - -ðððð
297
136
126
125
Figure 2. S6B0723 Chip Configuration
Item
Chip size
Pad pitch
Bumped pad size
(Bottom)
Bumped pad height
Table 1. S6B0723 Pad Dimensions
Size
Pad No.
X
Y
8850
1980
151 to 282
52
2 to 21, 105 to 124
55
138 to 150, 283 to 295
22 to 104
70
150 to 151, 282 to 283
75
1 to 2, 124 to 125
80
137 to 138, 295 to 296
126 to 136, 297 to 307
150
21 to 22, 104 to 105
226
1, 125, 137, 296
62
70
2 to 21, 105 to 124
34
70
138 to 150, 283 to 295
151 to 282
34
70
22 to 104
52
70
126 to 136, 297 to 307
38
70
All pad
14 (Typ.)
COG Align Key Coordinate
30µm 30µm 30µm
108µm
108µm
42µm
(+4144.25, +436.95)
42µm
42µm
60µm
108µm
108µm
30µm
4
42µm
(-4134.2, +451.95)
(+4078.25, +186.95)
µm
ILB Align Key Coordinate
30µm 30µm 30µm
30µm 30µm 30µm
(+4078.7, -397.2)
Unit
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pad
name
DUMMY
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
FRS
FR
TEST1
TEST2
TEST3
M
CL
DISP
TEST4
VSS
CS1B
CS2
VDD
RESETB
RS
VSS
RW_WRB
E_RDB
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VDD
X
-4221
-4141
-4086
-4031
-3976
-3921
-3866
-3811
-3756
-3701
-3646
-3591
-3536
-3481
-3426
-3371
-3316
-3261
-3206
-3151
-3096
-2870
-2800
-2730
-2660
-2590
-2520
-2450
-2380
-2310
-2240
-2170
-2100
-2030
-1960
-1890
-1820
-1750
-1680
-1610
-1540
-1470
-1400
-1330
-1260
-1190
-1120
-1050
-980
-910
Y
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
Pad
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pad
name
DUTY0
DUTY1
VSS
VDD
VDD
VDD
VCI
VCI
VSS
VSS
VSS
VOUT
VOUT
C4+
C4+
C3+
C3+
C1C1C1+
C1+
C2+
C2+
C2C2VDD
VEXT
REF
VSS
V1
V1
V2
V2
V3
V3
V4
V4
V0
V0
VR
VR
VSS
VSS
VDD
MS
CLS
VSS
C68
PS
VDD
X
-840
-770
-700
-630
-560
-490
-420
-350
-280
-210
-140
-70
0
70
140
210
280
350
420
490
560
630
700
770
840
910
980
1050
1120
1190
1260
1330
1400
1470
1540
1610
1680
1750
1820
1890
1960
2030
2100
2170
2240
2310
2380
2450
2520
2590
Y
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
Pad
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Pad
name
HPMB
VSS
INTRS
VDD
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
X
2660
2730
2800
2870
3096
3151
3206
3261
3316
3371
3426
3481
3536
3591
3646
3701
3756
3811
3866
3921
3976
4031
4086
4141
4221
4345
4345
4345
4345
4345
4345
4345
4345
4345
4345
4345
4221
4141
4086
4031
3976
3921
3866
3811
3756
3701
3646
3591
3536
3481
Y
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-865
-750
-600
-450
-300
-150
0
150
300
450
600
750
865
865
865
865
865
865
865
865
865
865
865
865
865
865
5
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
Pad
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
6
Pad
name
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
X
3406
3354
3302
3250
3198
3146
3094
3042
2990
2938
2886
2834
2782
2730
2678
2626
2574
2522
2470
2418
2366
2314
2262
2210
2158
2106
2054
2002
1950
1898
1846
1794
1742
1690
1638
1586
1534
1482
1430
1378
1326
1274
1222
1170
1118
1066
1014
962
910
858
Y
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
Pad
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Pad
name
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
X
806
754
702
650
598
546
494
442
390
338
286
234
182
130
78
26
-26
-78
-130
-182
-234
-286
-338
-390
-442
-494
-546
-598
-650
-702
-754
-806
-858
-910
-962
-1014
-1066
-1118
-1170
-1222
-1274
-1326
-1378
-1430
-1482
-1534
–1586
-1638
-1690
-1742
Y
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
Pad
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Pad
name
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
X
-1794
-1846
-1898
-1950
-2002
-2054
-2106
-2158
-2210
-2262
2314
-2366
-2418
-2470
-2522
-2574
-2626
-2678
-2730
-2782
-2834
-2886
-2938
-2990
-3042
-3094
-3146
-3198
-3250
-3302
-3354
-3406
-3481
-3536
-3591
-3646
-3701
-3756
-3811
-3866
-3921
-3976
-4031
-4086
-4141
-4221
-4345
-4345
-4345
-4345
Y
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
865
750
600
450
300
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
Pad
No.
301
302
303
304
305
306
307
Pad
name
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
X
-4345
-4345
-4345
-4345
-4345
-4345
-4345
Y
Pad
No.
Pad
name
X
Y
Pad
No.
Pad
name
X
Y
150
0
-150
-300
-450
-600
-750
7
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pins Description
Name
I/O
VDD
Supply
Power supply
VSS
Supply
Ground
V0
V1
V2
V3
V4
I/O
Description
LCD driver supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier
for application.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD bias.
LCD bias
V1
V2
V3
V4
1/9 bias
(8/9) x V0
(7/9) x V0
(2/9) x V0
(1/9) x V0
1/8 bias
(7/8) x V0
(6/8) x V0
(2/8) x V0
(1/8) x V0
1/7 bias
(6/7) x V0
(5/7) x V0
(2/7) x V0
(1/7) x V0
1/6 bias
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/5 bias
(4/5) x V0
(3/5) x V0
(2/5) x V0
(1/5) x V0
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pins Description
8
Name
C1C1+
C2C2+
C3+
C4+
I/O
O
O
O
O
O
O
VOUT
I/O
VR
I
VCI
I
VEXT
I
REF
I
Description
Capacitor 1 negative connection pin for voltage converter
Capacitor 1 positive connection pin for voltage converter
Capacitor 2 negative connection pin for voltage converter
Capacitor 2 positive connection pin for voltage converter
Capacitor 3 positive connection pin for voltage converter
Capacitor 4 positive connection pin for voltage converter
Voltage converter input/output pin
Connect this pin to VSS through capacitor.
V0 voltage adjustment pin
It is valid only when internal voltage regulator resistors are not used (INTRS = "L").
This is the reference voltage for the voltage converter circuit for the LCD driving.
Whether internal voltage converter use or not use, this pin should be fixed.
The voltage should have the following range: 2.4V ≤ VCI ≤ 3.6V
This is the external-input reference voltage (VREF) for the internal voltage regulator.
It is valid only when external VREF is used (REF = "L").
When using internal VREF, this pin is Open
Select the external VREF voltage via VEXT pin
− REF = "L": using the external VREF
− REF = "H": using the internal VREF
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
SYSTEM CONTROL
Table 5. System Control Pins Description
Name
MS
I/O
I
CLS
I
CL
I/O
M
I/O
FRS
O
FR
O
DISP
I/O
INTRS
I
Description
Master / slave mode select input
Master makes some signals for display, and slave gets them. This is for display
synchronization.
− MS = "H": master mode
− MS = "L": slave mode
The following table depends on the MS status.
Power
OSC
MS
CLS
supply
CL
M
FR
circuit
circuit
H
Enabled Enabled
Output
Output
Output
H
L
Disabled Enabled
Input
Output
Output
L
Disabled Disabled
Input
Input
Output
DISP
Output
Output
Input
Built-in oscillator circuit enable / disable select pin
− CLS = “H”: enable
− CLS = “L”: disable (external display clock input to CL pin)
Display clock input / output pin
When the S6B0723 is used in master/slave mode (multi-chip), the CL pins must be
connected each other.
LCD AC Signal input / output pin
When the S6B0723 is used in master/slave mode (multi-chip), the M pins must be
connected each other.
− MS = “H”: output
− MS = “L”: input
Static driver segment output pin
This pin is used together with the FR pin.
Static driver common output pin
This pin is used together with the FRS pin.
LCD display blanking control input / output
When S6B0723 is used in master/slave mode (multi-chip), the DISP pins must be
connected each other.
− MS = “H”: output
− MS = “L”: input
Internal resistor select pin
This pin selects the resistors for adjusting V0 voltage level and is valid only in master
operation.
− INTRS = "H": use the internal resistors.
− INTRS = "L": use the external resistors.
V0 voltage is controlled by VR pin and external resistive divider.
9
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
Table 5. System Control Pins Description (Continued)
Name
I/O
Description
The LCD driver duty ratio depends on the following table.
DUTY0
DUTY1
HPMB
10
I
I
DUTY1
L
L
H
H
DUTY0
L
H
L
H
Power control pin of the power supply circuits for LCD driver.
− HPMB = "H": normal mode
− HPMB = "L": high power mode
This pin is valid only in master operation.
Duty ratio
1/33
1/49
1/55
1/65
S6B0723
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
MICROPROCESSOR INTERFACE
Table 6. Microprocessor Interface Pins Description
Name
I/O
RESETB
I
Description
Reset input pin
When RESETB is "L", initialization is executed.
Parallel / Serial data input select input
Chip
Data /
Data
Read / Write
Serial clock
select
instruction
CS1B,
E_RDB
H
Parallel
RS
DB0 to DB7
CS2
RW_WRB
CS1B,
L
Serial
RS
SID (DB7)
Write only
SCLK (DB6)
CS2
*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to
DB5 are high impedance and E_RDB and RW_WRB must be fixed to either "H" or "L".
PS
PS
I
C68
I
CS1B
CS2
RS
I
I
Interface
mode
Microprocessor interface select input pin in parallel mode
− C68 = "H": 6800-series MPU interface
− C68 = "L": 8080-series MPU interface
Chip select input pins
Data/instruction I/O is enabled only when CS1B is "L" and CS2 is "H". When chip
select is non-active, DB0 to DB7 may be high impedance.
Register select input pin
− RS = "H": DB0 to DB7 are display data
− RS = "L": DB0 to DB7 are control data
Read / Write execution control pin
C68
MPU Type
RW_WRB
RW_WRB
H
6800-series
RW
L
8080-series
/WRB
I
Description
Read / Write control input pin
− RW = "H": read
− RW = "L": write
Write enable clock input pin
The data on DB0 to DB7 are latched at the rising
edge of the /WRB signal.
11
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Table 6. Microprocessor Interface Pins Description (Continued)
Name
I/O
Description
Read / Write execution control pin
C68
E_RDB
I
MPU Type
E_RDB
H
6800-series
E
L
8080-series
/RDB
Description
Read/Write control input pin
− RW = "H": When E is "H", DB0 to DB7 are in an
output status.
− RW = "L": The data on DB0 to DB7 are latched at
the falling edge of the E signal.
Read enable clock input pin
When /RDB is "L", DB0 to DB7 are in an output
status.
DB0
to
DB7
I/O
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data
bus. When the serial interface selected (PS = "L");
− DB0 to DB5: high impedance
− DB6: serial input clock (SCLK)
− DB7: serial input data (SID)
When chip select is not active, DB0 to DB7 may be high impedance.
TEST1
to
TEST4
I/O
These are pins for IC chip testing
They are set to Open.
NOTE: DUMMY – These pins should be opened (floated).
12
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER OUTPUTS
Table 7. LCD Driver Output Pins Description
Name
I/O
Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
SEG0
to
SEG131
O
Display data
FR
H
Segment driver output voltage
Normal display
Reverse display
H
V0
V2
H
L
VSS
V3
L
H
V2
V0
L
L
V3
VSS
VSS
VSS
Power save mode
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
COM0
to
COM63
O
Scan data
FR
Common driver output voltage
H
H
VSS
H
L
V0
L
H
V1
L
L
V4
Power save mode
COMS
O
VSS
Common output for the icons
The output signals of two pins are same. When not used, these pins should be left Open. In
multi-chip (master / slave) mode, all COMS pins on both master and slave units are the
same signal.
13
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There are CS1B and CS2 pins for chip selection. The S6B0723 can interface with an MPU only when CS1B is "L"
and CS2 is "H". When these pins are set to any other combination, RS, E_RDB, and RW_WRB inputs are disabled
and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter
are reset.
Parallel / Serial Interface
S6B0723 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or
serial interface is determined by PS pin as shown in table 8.
Table 8. Parallel / Serial Interface Mode
PS
Type
CS1B
CS2
H
Parallel
CS1B
CS2
L
Serial
CS1B
CS2
C68
Interface mode
H
6800-series MPU mode
L
8080-series MPU mode
*×
Serial-mode
*×: Don't care
Parallel Interface (PS = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in
table 9. The type of data transfer is determined by signals at RS, E_RDB and RW_WRB as shown in table 10.
Table 9. Microprocessor Selection for Parallel Interface
C68
CS1B
CS2
RS
E_RDB
RW_WRB
DB0 to DB7
MPU bus
H
CS1B
CS2
RS
E
RW
DB0 to DB7
6800-series
L
CS1B
CS2
RS
/RDB
/WRB
DB0 to DB7
8080-series
Table 10. Parallel Data Transfer
Common
14
6800-series
8080-series
RS
E_RDB
(E)
RW_WRB
(RW)
E_RDB
(/RDB)
RW_WRB
(/WRB)
Description
H
H
H
L
H
Display data read out
H
H
L
H
L
Display data write
L
H
H
L
H
Register status read
L
H
L
H
L
Writes to internal register (instruction)
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Serial Interface (PS = "L")
When the S6B0723 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal
8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into
DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high
and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by
the line length, the operation check on the actual machine is recommended.
CS1B
CS2
SID
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
SCLK
RS
Figure 3. Serial Interface Timing
Busy Flag
The Busy Flag indicates whether the S6B0723 is operating or not. When DB7 is "H" in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.
15
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Data Transfer
The S6B0723 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU
to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And when
reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy
read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure5. This
means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address
sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction
right after the address sets, but can be output at the second read of data.
MPU signals
RS
/WRB
DB0 to DB7
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
/WRB
BUS HOLDER
COLUMN ADDRESS
N
N+1
Figure 4. Write Timing
16
N+2
N+3
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
MPU signals
RS
/WRB
/RDB
DB0 to DB7
Dummy
N
D(N)
D(N+1)
D(N+2)
Internal signals
/WRB
/RDB
BUS HOLDER
COLUMN ADDRESS
N
D(N)
N
N+1
D(N+1)
D(N+2)
N+2
N+3
Figure 5. Read Timing
17
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel can
be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and
the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through
DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as
shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD
controller operates independently, data can be written into RAM at the same time as data is being displayed without
causing the LCD flicker.
DB0
0
0
1
--
0
COM0
--
DB1
1
0
0
--
1
COM1
--
DB2
0
1
1
--
0
COM2
--
DB3
1
0
1
--
0
COM3
--
DB4
0
0
0
--
1
COM4
--
Display Data RAM
LCD Display
Figure 6. RAM-to-LCD Data Transfer
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the "Set Page" instruction. Page Address 8 (DB3 is "H", but DB2, DB1 and DB0
are "L") is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is
impossible to access to on-chip RAM.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by
setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the
initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register
are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
132-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU
can not access Line Address of icons.
18
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Column Address Circuit
Column Address circuit has an 8-bit preset counter that provides column address to the Display Data RAM as shown
in figure 8. When Set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this
address is increased by 1 each a read or write data instruction, microprocessor can access the display data
continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is unlocked
if a column address is set again by set Column Address MSB / LSB instruction. And the Column Address counter is
independent of page address register.
ADC Select instruction makes it possible to invert the relationship between the Column Address and the segment
outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the
following figure 7.
SEG output
SEG
0
SEG
1
SEG
2
SEG
3
... ...
SEG
128
SEG
129
SEG
130
SEG
131
Column address [Y7:Y0]
00H
01H
02H
03H
... ...
80H
81H
82H
83H
Display data
1
0
1
0
1
1
0
0
LCD panel display
( ADC = 0 )
LCD panel display
( ADC = 1 )
... ...
... ...
Figure 7. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit
This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF
instructions without changing the data in the display data RAM.
19
DB1
DB0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
ADC=0
ADC=1
Page1
Page2
Page3
Page4
Page5
Page6
Page7
Page8
7E 7F 80 81 82 83
05 04 03 02 01 00
SEG131
SEG130
SEG129
SEG128
SEG127
SEG126
SEG5
SEG4
-----
SEG3
---------
SEG2
00 01 02 03 04 05
83 82 81 80 7F 7E
SEG1
LCD Output
Page0
SEG0
Column
Address
Data
Figure 8. Display Data RAM Map
20
Line
Address
COM
Output
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
Start
1/33
Duty
DB2
S6B0723
1/55
Duty
Page Address
DB3
PRELIMINARY SPEC. VER. 0.9
1/49
Duty
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
When the initial display
line address
is 1C[HEX]
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DISPLAY CIRCUITS
Oscillator
This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in
the voltage converter and display timing generation circuit. The oscillator circuit is only enabled when MS = “ H” and
CLS = “H". When on-chip oscillator is not used, CLS pin must be "L" condition. In this time, external clock must be
input from CL pin.
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL generated by oscillation
clock, generates a clock to the line counter and a latch signal to the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 132-bit display data is latched by the
display data latch circuit in synchronization with the display clock. The display data which is read to the LCD driver is
completely independent of the access to the display data RAM from the microprocessor. The LCD AC signal, M is
generated from the display clock. 2-frame AC driver waveforms with internal timing signal are shown in figure 9.
In a multiple chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 11 shows
the M, SYNC, CL, and DISP status.
Table 11. Master and Slave Timing Signal Status
Operation mode
Master
Slave
Oscillator
M
CL
DISP
ON (internal clock used)
Output
Output
Output
OFF (external clock used)
Output
Input
Output
-
Input
Input
Input
21
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
64
65
1
2
3
4
5
6
7
8
9
10
11
12
PRELIMINARY SPEC. VER. 0.9
58
59
60
61
62
63
64
65
1
S6B0723
2
3
4
5
6
CL
FR
COM0
V0
V1
V2
V3
V4
VSS
COM1
V0
V1
V2
V3
V4
VSS
SEGn
V0
V1
V2
V3
V4
VSS
Figure 9. 2-frame AC Driving Waveform (Duty Ratio = 1/65)
22
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Common Output Control Circuit
This circuit controls the relationship between the number of common output and specified duty ratio. SHL select
instruction specifies the scanning direction of the common output pins.
Table 12. The Relationship between Duty Ratio and Common Output
Common output pins
Duty SHL
1/33
1/49
1/55
1/65
0
1
0
1
0
1
0
1
COM
COM
[0:15]
[16:23]
COM[0:15]
COM[31:16]
COM[0:23]
COM[47:24]
COM[0:26]
COM[53:27]
COM
[24:26]
COM
[27:36]
*NC
*NC
*NC
*NC
*NC
*NC
COM[0:63]
COM[63:0]
COM
[37:39]
COM
[40:47]
COM
COMS
[48:63]
COM[16:31]
COMS
COM[15:0]
COM[24:47]
COMS
COM[23:0]
COM[27:53]
COMS
COM[26:0]
COMS
*NC: No Connection
23
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
LCD DRIVER CIRCUITS
This driver circuit is configured by 66-channel (including 2 COMS channels) common driver and 132-channel
segment driver. This LCD panel driver voltage depends on the combination of display data and FR signal.
VDD
COM0
FR
COM1
VSS
COM2
V0
V1
V2
COM0
COM3
COM4
V3
V4
VSS
V0
V1
V2
COM5
COM1
COM6
COM7
V3
V4
VSS
V0
V1
V2
COM8
COM2
COM9
V0
V1
V2
COM10
SEG0
COM11
COM12
V3
V4
VSS
V0
V1
V2
COM13
SEG1
COM14
COM15
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
V3
V4
VSS
V0
V1
V2
SEG2
Figure 10. Segment and Common Timing
24
V3
V4
VSS
V3
V4
VSS
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and
voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For
details, refers to "Instruction Description". Table 13 shows the referenced combinations in using Power Supply
circuits.
Table 13. Recommended Power Supply Combinations
User Setup
Power
control
(VC VR VF)
V/C
circuits
V/R
circuits
V/F
circuits
VOUT
V0
V1 to V4
Only the internal power
supply circuits are used
111
ON
ON
ON
Open
Open
Open
Only the voltage
regulator circuits and
voltage follower circuits
are used
011
OFF
ON
ON
External
input
Open
Open
Only the voltage follower
circuits are used
001
OFF
OFF
ON
Open
External
input
Open
Only the external power
supply circuits are used
000
OFF
OFF
OFF
Open
External
input
External
input
25
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Voltage Converter Circuits
These circuits boost up the electric potential between VCI and VSS to 2, 3, 4, or 5 times toward positive side and
boosted voltage is outputted from VOUT pin.
[C1 = 1.0 to 4.7 µF]
VDD
VDD
VCI
VCI
VCI
VCI
V SS
-
VOUT
+
C1
V SS
-
VOUT
+
C4+
C4+
C3+
C3+
C1-
-
C1+
+
C1
VOUT = 2 × VCI
C2+
VCI
C2-
C1
VOUT = 3 × VCI
C1-
-
C1+
C2+
+
+
C2-
-
C1
C1
V SS
Figure 11. Two Times Boosting Circuit
VDD
VCI
V SS
Figure 12. Three Times Boosting Circuit
VDD
VCI
VCI
VCI
VCI
VSS
-
VOUT
+
C1
C4+
C3+
C1C1+
C2+
C2-
+
C1
C1
+
+
C1
-
VOUT = 4 × VCI
VSS
-
VOUT
+
C4+
C3+
+
C1-
-
C1+
VCI
VSS
Figure 13. Four Times Boosting Circuit
VOUT = 5 × VCI
C1
C2+
C2-
C1
C1
+
+
C1
+
C1
VCI
VSS
Figure 14. Five Times Boosting Circuit
* The VCI voltage range must be set so that the VOUT voltage does not exceed the absolute maximum
rated value
26
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Voltage Regulator Circuits
The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting
resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operationalamplifier circuits shown in Figure 15, it is necessary to be applied internally or externally.
For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS
pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value
selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta = 25°C is
shown in table 14-1.
Rb
V0 = ( 1 +  ) x VEV [V] ------ (Eq. 1)
Ra
(63 - α)
VEV = ( 1 -  ) x VREF [V] ------ (Eq. 2)
162
Table 14-1. VREF Voltage at Ta = 25 °C
REF
Temp. coefficient
VREF [V]
H
-0.05% / °C
2.1
L
External input
VEXT
Table 14-2. Electronic Contrast Control Register (64 Steps)
SV5
SV4
SV3
SV2
SV1
SV0
Reference voltage
parameter (α)
V0
Contrast
0
0
0
0
0
0
0
Minimum
Low
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
32 (default)
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Maximum
High
27
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
VOUT
+
V0
VEV
Rb
VR
Ra
VSS
GND
Figure 15. Internal Voltage Regulator Circuit
28
S6B0723
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
In Case of Using Internal Resistors, Ra and Rb (INTRS = "H")
When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between
V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage".
Table 15. Internal Rb / Ra ratio depending on 3-bit data (R2 R1 R0)
3-bit data settings (R2 R1 R0)
1 + (Rb / Ra)
000
001
010
011
100
101
110
111
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.4
The following figure shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and 6-bit
electronic volume registers for each temperature coefficient at Ta = 25 °C.
16.00
14.00
(1
(1
(1
(1
(0
(0
(0
(0
12.00
10.00
V0
8.00
[V]
6.00
1
1
0
0
1
1
0
0
1)
0)
1)
0)
1)
0)
1)
0)
4.00
2.00
0.00
0
8
16
24
32
40
48
56
Electronic volume level
Figure 16. Electronic Volume Level
29
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
In Case of Using External Resistors, Ra and Rb (INTRS = "L")
When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb
between V0 and VR.
Example: For the following requirements
1. LCD driver voltage, V0 = 10V
2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)
3. Maximum current flowing Ra, Rb = 1 uA
From Eq. 1
Rb
10 = ( 1 +  ) x VEV [V] ------ (Eq. 3)
Ra
From Eq. 2
(63 - 32)
VEV = ( 1 -  ) x 2.1 ≅ 1.698 [V] ------ (Eq. 4)
162
From requirement 3.
10
 = 1 [uA] ------ (Eq. 5)
Ra + Rb
From equations Eq. 3, 4 and 5
Ra ≅ 1.69 [MΩ]
Rb ≅ 8.31 [MΩ]
The following table shows the range of V0 depending on the above requirements.
Table 16. V0 Depending on Electronic Volume Level
Electronic volume level
V0
30
0
.......
32
.......
63
7.57
.......
10.00
.......
12.43
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Voltage Follower Circuits
VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3, V4), and those output impedance are
converted by the Voltage Follower for increasing drive capability. The following table shows the relationship
between V1 to V4 level and each duty ratio.
Table 17. The Relationship between V1 to V4 Level and Duty Ratio
Duty ratio
DUTY1
DUTY0
1/33
L
L
1/49
L
H
1/55
H
L
1/65
H
H
LCD bias
V1
V2
V3
V4
1/5
(4/5) x V0
(3/5) x V0
(2/5) x V0
(1/5) x V0
1/6
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/6
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/8
(7/8) x V0
(6/8) x V0
(2/8) x V0
(1/8) x V0
1/6
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/8
(7/8) x V0
(6/8) x V0
(2/8) x V0
(1/8) x V0
1/7
(6/7) x V0
(5/7) x V0
(2/7) x V0
(1/7) x V0
1/9
(8/9) x V0
(7/9) x V0
(2/9) x V0
(1/9) x V0
High Power Mode
The power supply circuit equipped in the S6B0723 for LCD drive has very low power consumption (in normal mode:
HPMB = “H”). If use for LCD panels with large loads, this low-power power supply may cause display quality to
degrade. When this occurs, setting the HPMB pin to “L”(high power mode) can improve the quality of the display.
Moreover, if the quality of display is inadequate even after high power mode has been set, then it is necessary to add
a liquid crystal drive power supply externally (Vout or V0 or V1 / V2 / V3 / V4).
31
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
REFERENCE CIRCUIT EXAMPLES
When using internal regulator resistors
V DD
When not using internal regulator resistors
VDD
MS INTRS
VCI
V SS
VOUT
C4+
C3+
C1C1+
C2+
C2VR
C1
C1
C1
C1
C2
C2
C2
C2
C2
-
+
+
+
+
+
C1
C1
C1
C1
Ra
C2
C2
C2
C2
C2
V0
V1
V2
V3
V4
V SS
-
+
+
+
+
+
Rb
MS INTRS
VCI
VSS
VOUT
C4+
C3+
C1C1+
C2+
C2VR
VSS
V0
V1
V2
V3
V4
V SS
Figure 17. When Using all Internal LCD Power Circuits (VCI = VDD, 4-time V/C: ON, V/R: ON, V/F: ON)
When using internal regulator resistors
V DD
When not using internal regulator resistors
V DD
External
Power
Supply
MS INTRS
VCI
VOUT
C4+
C3+
C1C1+
C2+
C2-
External
Power
Supply
MS INTRS
VCI
VOUT
C4+
C3+
C1C1+
C2+
C2-
VSS
Ra
VR
C2
C2
C2
C2
C2
V SS
-
+
+
+
+
+
V0
V1
V2
V3
V4
C2
C2
C2
C2
C2
-
VR
+ Rb
V0
+
V1
+
V2
+
V3
+
V4
V SS
Figure 18. When Using some Internal LCD Power Circuits (VCI = VDD, V/C: OFF, V/R: ON, V/F: ON)
32
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
V DD
External
Power
Supply
MS INTRS
VCI
VOUT
C4+
C3+
C1C1+
C2+
C2VR
C2
C2
C2
C2
C2
-
+
+
+
+
+
V0
V1
V2
V3
V4
V SS
Figure 19. When Using some Internal LCD Power Circuits (VCI = VDD, V/C: OFF, V/R: OFF, V/F: ON)
V DD
MS INTRS
VCI
VOUT
C4+
C3+
C1C1+
C2+
C2VR
External
Power
Supply
Value of external Capacitance
Item
Value
C1
1.0 to 4.7
C2
0.47 to 1.0
Unit
µF
V0
V1
V2
V3
V4
VSS
Figure 20. When not Using any Internal LCD Power Supply Circuits
(VCI = VDD, V/C: OFF, V/R: OFF, V/F: OFF)
* C1 and C2 are determined by the size of the LCD being driven.
Select a value that will stabilize the liquid crystal drive voltage.
33
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
RESET CIRCUIT
Setting RESETB to "L" or Reset instruction can initialize internal function.
When RESETB becomes "L", following procedure is occurred.
Display ON / OFF: OFF
Entire display ON / OFF: OFF (normal)
ADC select: OFF (normal)
Reverse display ON / OFF: OFF (normal)
Power control register (VC, VR, VF) = (0, 0, 0)
Serial interface internal register data clear
LCD bias ratio: 1/9 (1/65 duty), 1/8 (1/55 duty), 1/8 (1/49 duty), 1/6 (1/33 duty)
On-chip oscillator OFF
Power save release
Read-modify-write: OFF
SHL select: OFF (normal)
Static indicator mode: OFF
Static indicator register: (S1, S0) = (0, 0)
Display start line: 0 (first)
Column address: 0
Page address: 0
Regulator resistor select register: (R2, R1, R0) = (1, 0, 0)
Reference voltage set: OFF
Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0)
Test mode release
When RESET instruction is issued, following procedure is occurred.
Read-modify-write: OFF
Static indicator mode: OFF
Static indicator register: (S1, S0) = (0, 0)
SHL select: 0
Display start line: 0 (first)
Column address: 0
Page address: 0
Regulator resistor select register: (R2, R1, R0) = (1, 0, 0)
Reference voltage set: OFF
Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0)
Test mode release
While RESETB is "L" or Reset instruction is executed, no instruction except read status could be accepted. Reset
status appears at DB4. After DB4 becomes "L", any instruction can be accepted. RESETB must be connected to the
reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential
before used.
34
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Table 18. Instruction Table
×: Don't care
Instruction
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Display ON / OFF
0
0
1
0
1
0
1
1
1
DON
ST4S
T3
ST2
ST1 ST0
Description
Turn ON / OFF LCD panelWhen
DON = 0: display OFF
When DON = 1: display ON
Initial display line
0
0
0
1
ST5
Set page address
0
0
1
0
1
1
P3
P2
P1
Specify DDRAM line for COM0
P0
Set page address
Set column address MSB
0
0
0
0
0
1
Y7
Y6
Y5
Y4
Set column address MSB
Set column address LSB
0
0
0
0
0
0
Y3
Y2
Y1
Y0
Set column address LSB
Read status
0
1
BUSY
ADC
ON/OFF
RESETB
0
0
0
0
Read the internal status
Write display data
1
0
Write data
Write data into DDRAM
Read display data
1
1
Read data
Read data from DDRAM
ADC select
0
0
1
0
1
0
0
0
0
ADC
Reverse display ON / OFF
0
0
1
0
1
0
0
1
1
REV
Entire display ON / OFF
0
0
1
0
1
0
0
1
0
EON
LCD bias select
0
0
1
0
1
0
0
0
1
BIAS
Select SEG output direction
When ADC = 0: normal direction
(SEG0→SEG131)
When ADC = 1: reverse direction
(SEG131→SEG0)
Select normal / reverse display
When REV = 0: normal display
When REV = 1: reverse display
Select normal/ entire display ON
When EON = 0: normal display.
When EON = 1: entire display
ON
Select LCD bias
Set modify-read
0
0
1
1
1
0
0
0
0
0
Set modify-read mode
Reset modify-read
0
0
1
1
1
0
1
1
1
0
release modify-read mode
Reset
0
0
1
1
1
0
0
0
1
0
Initialize the internal functions
Select COM output direction
When SHL = 0: normal direction
(COM0→COM63)
When SHL = 1: reverse direction
(COM63→COM0)
SHL select
0
0
1
1
0
0
SHL
×
×
×
Power control
0
0
0
0
1
0
1
VC
VR
VF
Control power circuit operation
Regulator resistor select
0
0
0
0
1
0
0
R2
R1
R0
Select internal resistance ratio of
the regulator resistor
Set reference voltage
mode
0
0
1
0
0
0
0
0
0
1
Set reference voltage
register
0
0
×
×
SV5
SV4
SV3
SV2
SV1
SV0
Set reference voltage register
Set static indicator mode
0
0
1
0
1
0
1
1
0
SM
Set static indicator mode
Set static indicator register
0
0
×
×
×
×
×
×
S1
S0
Set static indicator register
Power save
-
-
-
-
-
-
-
-
-
-
Set reference voltage mode
Compound Instruction of display
OFF and entire display ON
35
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Table 18. Instruction Table (Continued)
×: Don't care
36
Instruction
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Description
NOP
0
0
1
1
1
0
0
0
1
1
Non-Operation command
Test Iistruction_1
0
0
1
1
1
1
×
×
×
×
Don’ t use this instruction
Test instruction_2
0
0
1
0
0
1
×
×
×
×
Don’ t use this instruction
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Display ON / OFF
Turns the Display ON or OFF
RS
RW
0
0
DON = 1: display ON
DON = 0: display OFF
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
1
1
1
DON
Initial Display Line
Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed at
the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
ST5
ST4
ST3
ST2
ST1
ST0
ST5
ST4
ST3
ST2
ST1
ST0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Set Page Address
Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM
data bit can be accessed when its Page Address and column address are specified. Along with the column
address, the Page Address defines the address of the display RAM to write or read display data. Changing the
page address doesn't effect to the display status.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
P3
P2
P1
P0
P3
P2
P1
P0
Page
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
0
1
1
1
7
1
0
0
0
8
37
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Set Column Address
Sets the Column Address of display RAM from the microprocessor into the Column Address register. Along with
the Column Address, the Column Address defines the address of the display RAM to write or read display data.
When the microprocessor reads or writes display data to or from display RAM, Column Addresses are
automatically increased.
Set Column Address MSB
RS
RW
DB7
0
0
0
Set Column Address LSB
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
Y7
Y6
Y5
Y4
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Y1
Y0
0
0
0
0
0
0
Y3
Y2
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
1
0
130
1
0
0
0
0
0
1
1
131
Read Status
Indicates the internal status of the S6B0723
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BUSY
ADC
ON / OFF
RESETB
0
0
0
0
Flag
BUSY
ADC
38
Description
The device is busy when internal operation or reset.
Any instruction is rejected until BUSY goes Low.
0: chip is active, 1: chip is being busy
Indicates the relationship between RAM column address and segment driver.
0: reverse direction (SEG131 → SEG0), 1: normal direction (SEG0 → SEG131)
ON / OFF
Indicates display ON / OFF status.
0: display ON, 1: display OFF
RESETB
Indicates the initialization is in progress by RESETB signal.
0: chip is active, 1: chip is being reset
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Write Display Data
8-bit data of display data from the microprocessor can be written to the RAM location specified by the column
address and page address. The column address is increased by 1 automatically so that the microprocessor can
continuously write data to the addressed page.
RS
RW
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write data
Set Page Address
Set Page Address
Set Column Address
Set Column Address
Data write
Dummy Data Read
Column = Column + 1
Column = Column + 1
Data Write Continue ?
Data Read
YES
Column = Column + 1
NO
Optional Status
Data Read Continue ?
YES
NO
Optional Status
Figure 21. Sequence for Writing Display Data
Figure 22. Sequence for Reading Display Data
Read Display Data
8-bit data from display data RAM specified by the column address and page address can be read by this
instruction. As the column address is increased by 1 automatically after each this instruction, the
microprocessor can continuously read data from the addressed page. A dummy read is required after loading
an address into the column address register. Display data cannot be read through the serial interface.
RS
RW
1
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read data
ADC Select (Segment Driver Direction Select)
Changes the relationship between RAM column address and segment driver. The direction of segment driver
output pins can be reversed by software. This makes IC layout flexible in LCD module assembly.
RS
RW
DB7
DB6
DB5
0
0
1
0
1
ADC = 0: normal direction (SEG0 → SEG131)
ADC = 1: reverse direction (SEG131 → SEG0)
DB4
DB3
DB2
DB1
DB0
0
0
0
0
ADC
39
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Reverse Display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the display data RAM.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
1
1
REV
REV
RAM bit data = "1"
RAM bit data = "0"
0 (normal)
LCD pixel is illuminated
LCD pixel is not illuminated
1 (reverse)
LCD pixel is not illuminated
LCD pixel is illuminated
Entire Display ON / OFF
Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time,
the contents of the display data RAM are held. This instruction has priority over the Reverse Display On/Off
instruction.
RS
RW
DB7
0
0
1
EON = 0: normal display
EON = 1: entire display ON
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
1
0
EON
Select LCD Bias
Selects LCD bias ratio of the voltage required for driving the LCD.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
0
1
Bias
Duty
ratio
DUTY1
DUTY0
1/33
0
1/49
LCD bias
Bias = 0
Bias = 1
0
1/6
1/5
0
1
1/8
1/6
1/55
1
0
1/8
1/6
1/65
1
1
1/9
1/7
Set Modify-Read
This instruction stops the automatic increment of the column address by the read display data instruction, but
the column address is still increased by the write display data instruction. And it reduces the load of
microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This
mode is canceled by the reset Modify-read instruction.
40
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
0
0
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Reset Modify-Read
This instruction cancels the Modify-read mode, and makes the column address return to its initial value just
before the set Modify-read instruction is started.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
1
1
1
0
Set Page Address
Set Column Address (N)
Set Modify-Read
Dummy Read
Data Read
Data Process
Data Write
NO
Change Complete ?
YES
Reset Modify-Read
Return Column Address (N)
Figure 23. Sequence for Cursor Display
Reset
This instruction resets initial display line, column address, page address, and common output status select to
their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD
power supply, which is initialized by the RESETB pin.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
1
0
41
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
SHL Select (Common Output Mode Select)
COM output scanning direction is selected by this instruction which determines the LCD driver output status.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
1
1
0
0
SHL
×
×
SHL = 0: normal direction (COM0 → COM63)
SHL = 1: reverse direction (COM63 → COM0)
DB0
×
× : Don’ t care
Power Control
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal
power supply functions can be used simultaneously.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
1
VC
VR
VF
VC
VR
VF
Status of internal power supply circuits
0
1
Internal voltage converter circuit is OFF
Internal voltage converter circuit is ON
0
1
Internal voltage regulator circuit is OFF
Internal voltage regulator circuit is ON
0
1
Internal voltage follower circuit is OFF
Internal voltage follower circuit is ON
Regulator Resistor Select
Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator
section in power supply circuit. Refer to the table 15.
42
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
0
R2
R1
R0
R2
R1
R0
(1 + Rb / Ra) ratio
0
0
0
3.0
0
0
1
3.5
0
1
0
4.0
0
1
1
4.5
1
0
0
5.0 (default)
1
0
1
5.5
1
1
0
6.0
1
1
1
6.4
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Reference Voltage Select
Consists of 2-byte instruction. The 1st instruction sets reference voltage mode, the 2nd one updates the contents
of reference voltage register. After second instruction, reference voltage mode is released.
The 1st Instruction: Set Reference Voltage Select Mode
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
The 2nd Instruction: Set Reference Voltage Register
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
×
SV4
SV3
SV2
SV1
SV0
SV5
SV4
SV3
SV2
SV1
SV0
Reference voltage
parameter (α)
V0
Contrast
0
0
0
0
0
0
0
Minimum
Low
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Maximum
High
0
0
0
1
0
0
×
SV5
32 (default)
Setting Reference Voltage Start
1st Instruction for Mode Setting
2nd Instruction for Register Setting
Setting Reference Voltage End
Figure 24. Sequence for Setting the Reference Voltage
43
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Set Static Indicator State
Consists of two bytes instruction. The first byte instruction (set Static Indicator Mode) enables the second byte
instruction (set Static Indicator Register) to be valid. The first byte sets the static indicator ON / OFF. When it is
on, the second byte updates the contents of static indicator register without issuing any other instruction and
this Static Indicator state is released after setting the data of indicator register.
The 1st Instruction: Set Static Indicator Mode (ON / OFF)
RS
RW
DB7
DB6
DB5
DB4
0
0
1
SM = 0: static indicator OFF
SM = 1: static indicator ON
0
1
The 2nd Instruction: Set Static Indicator Register
RS
RW
DB7
DB6
DB5
0
×
0
×
×
DB3
DB2
DB1
DB0
0
1
1
0
SM
DB4
DB3
DB2
DB1
DB0
×
×
×
S1
S0
S1
S0
Status of static indicator output
0
0
OFF
0
1
ON (about 1 second blinking)
1
0
ON (about 0.5 second blinking)
1
1
ON (always ON)
NOP
Non Operation Instruction
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
1
1
Test Instruction (Test Instruction_1 & Test Instruction_2)
These are the instruction for IC chip testing. Please do not use it. If the test instruction is used by accident, it can
be cleared by applying “0” signal to the RESETB input pin or the reset instruction.
44
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
1
×
×
×
×
0
0
1
0
0
1
×
×
×
×
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Power Save (Compound Instruction)
If the entire display ON / OFF instruction is issued during the display OFF state, S6B0723 enters the Power
Save status to reduce the power consumption to the static power consumption value. According to the status of
static indicator mode, power save is entered to one mode of sleep and standby mode. When Static Indicator
mode is ON, standby mode is issued. When OFF, sleep mode is issued. Power save mode is released by the
entire display OFF instruction.
Static Indicator OFF
Static Indicator ON
Power Save (Compound Instruction)
[Display OFF]
[Entire Display ON]
Sleep Mode
[Oscillator Circuit: OFF]
[LCD Power Supply Circuit: OFF]
[All COM / SEG Outputs: VSS]
[Consumption Current: <2uA]
Standby Mode
[Oscillator Circuit: ON]
[LCD Power Supply Circuit: OFF]
[All COM / SEG Outputs: VSS]
[Consumption Current: <10uA]
Power Save OFF (Compound Instruction)
[Entire Display OFF]
[Static Indicator ON]
2 Bytes Command
Power Save OFF
[Entire Display OFF]
Release Sleep Mode
Release Standby Mode
Figure 25. Power Save (Compound Instruction)
−
Sleep Mode
This stops all operations in the LCD display system, and as long as there are no access from the MPU, the
consumption current is reduced to a value near the static current. The internal modes during sleep mode are
as follows:
a. The oscillator circuit and the LCD power supply circuit are halted.
b. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VSS level.
−
Standby Mode
The duty LCD display system operations are halted and only the static drive system for the indicator
continues to operate, providing the minimum required consumption current for the static drive.
The internal modes are in the following states during standby mode.
a. The LCD power supply circuits are halted. The oscillator circuit continues to operate.
b. The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs
a VSS level. The static drive system does not operate.
When a reset command is performed while in standby mode, the system enters sleep mode.
45
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
Referential Instruction Setup Flow (1)
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESETB Pin = “L”
Waiting for Stabilizing the Power
RESETB Pin = “H”
User Application Setup by Internal Instructions
[ADC Select]
[SHL Select]
[LCD Bias Select]
User LCD Power Setup by Internal Instructions
[Voltage Converter ON]
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Voltage Regulator ON]
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Voltage Follower ON]
User LCD Power Setup by Internal Instructions
[Regulator Resistor Select]
[Reference Voltage Register Set]
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 26. Initializing with the Built-in Power Supply Circuits
46
S6B0723
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (2)
User System Setup by External Pins
Start of Iitialization
Power ON (VDD - VSS) Keeping the RESETB Pin = “L”
Waiting for Stabilizing the Power
RESETB Pin = “H”
Set Power Save
User Application Setup by Internal Instructions
[ADC Select]
[SHL Select]
[LCD Bias Select]
User LCD Power Setup by Internal Instructions
[Regulator Resistor Select]
[Reference Voltage Register Set]
Release Power Save
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 27. Initializing without the Built-in Power Supply Circuits
47
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
Referential Instruction Setup Flow (3)
End of Initialization
Display Data RAM Addressing by Instruction
[Initial Display Line]
[Set Page Address]
[Set Column Address]
Write Display ON / OFF by Instruction
[Display ON /OFF]
Turn Display ON / OFF by Instruction
[Display ON / OFF]
End of Data Display
Figure 28. Data Displaying
48
S6B0723
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (4)
Optional Status
Turn Display ON /OFF by Instruction
[Display OFF]
User LCD Power Setup by Internal Instructions
[Voltage Regulator OFF]
Waiting for ≥ 50ms
User LCD Power Setup by Internal Instructions
[Voltage Follower OFF]
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Voltage Converter OFF]
Waiting for ≥ 1ms
Power OFF (VDD - VSS)
Figure 29. Power OFF
49
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 19. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VDD
- 0.3 to +7.0
V
VLCD
- 0.3 to +17.0
V
Input voltage range
VIN
- 0.3 to VDD + 0.3
V
Operating temperature range
TOPR
- 40 to +85
°C
Storage temperature range
TSTR
- 55 to +125
°C
Supply voltage range
NOTES:
1. VDD and VLCD are based on VSS = 0V.
2. Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied.( VLCD = V0 – VSS)
3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation.
Otherwise, this LSI may malfunction or reduced LSI reliability may result.
50
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
DC CHARACTERISTICS
Table 20. DC Characteristics
(VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85°C)
Item
Symbol
Operating voltage (1)
Condition
Min.
Typ.
Max.
Unit
Pin used
VDD
2.4
-
3.6
V
VDD *1
Operating voltage (2)
V0
4.5
-
15.0
V
V0 *2
High
VIH
0.8VDD
-
VDD
V
*3
Low
VIL
VSS
-
0.2VDD
High
VOH
IOH = -0.5mA
0.8VDD
-
VDD
V
*4
Low
VOL
IOL = 0.5mA
VSS
-
0.2VDD
Input leakage current
IIL
VIN = VDD or VSS
- 1.0
-
+ 1.0
µA
*5
Output leakage current
IOZ
VIN = VDD or VSS
- 3.0
-
+ 3.0
µA
*6
LCD driver ON
resistance
RON
Ta = 25°C, V0 = 8V
-
2.0
3.0
kΩ
SEGn
COMn *7
Internal
f OSC
32.7
43.6
54.5
External
f CL
Ta = 25°C
Duty ratio = 1/65
4.09
5.45
6.81
kHz
CL *8
×2
2.4
-
3.6
×3
2.4
-
3.6
×4
V
VCI
2.4
-
3.6
×5
2.4
-
3.2
×2 / ×3 / ×4 / ×5
voltage conversion
(no-load )
95
99
-
%
VOUT
Input voltage
Output
voltage
Oscillator
frequency
Voltage converter
input voltage
VCI
Voltage converter
output voltage
VOUT
Voltage regulator
operating voltage
VOUT
6.0
-
16.0
V
VOUT
Voltage follower
operating voltage
V0
4.5
-
15.0
V
V0 *9
Reference voltage
VREF
2.04
2.1
2.16
V
*10
Ta = 25°C
- 0.05%/°C
51
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Dynamic Current Consumption (1) when the Built-in Power Circuit is OFF (At Operate Mode)
(Ta = 25°C)
Item
Symbol
Dynamic current
consumption (1)
IDD1
Condition
Min.
Typ.
Max.
Unit
Pin used
VDD = 3.0V
V0 – VSS = 11.0V
1/65 duty ratio
Display pattern OFF
-
15
23
µΑ
*11
Dynamic Current Consumption (2) when the Built-in Power Circuit is ON (At Operate Mode)
(Ta = 25°C)
Item
Dynamic current
consumption (2)
Symbol
Condition
Min.
Typ.
Max.
Unit
Pin used
VDD = 3.0V,
(VCI = VDD, 4 times boosting)
V0 – VSS = 11.0V,
1/65 duty ratio,
Display pattern OFF,
Normal power mode
-
40
60
µΑ
*12
VDD = 3.0V,
(VCI = VDD, 4 times boosting)
V0 – VSS = 11.0V,
1/65 duty ratio,
Display pattern checker,
Normal power mode
-
150
200
µΑ
*12
IDD2
Current Consumption during Power Save Mode
(Ta = 25°C)
Item
Sleep mode
current
Standby mode
current
52
Symbol
Condition
Min.
Typ.
Max.
Unit
IDDS1
During sleep
-
-
2.0
µA
IDDS2
During standby
-
-
10.0
µA
Pin used
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 21. The Relationship between Oscillation Frequency and Frame Frequency
Duty ratio
Item
fCL
On-chip oscillator circuit is
used
fOSC
fOSC


8
2 × 8 × 65
On-chip oscillator circuit is
not used
External input (f CL)

On-chip oscillator circuit is
used
fOSC
fOSC


On-chip oscillator circuit is
not used
External input (f CL)
On-chip oscillator circuit is
used
fOSC
fOSC


10
2 × 10 × 49
On-chip oscillator circuit is
not used
External input (f CL)

On-chip oscillator circuit is
used
fOSC
fOSC


15
2 × 15 × 33
On-chip oscillator circuit is
not used
External input (f CL)

1/65
1/55
1/49
1/33
fFR
fOSC
9
2 × 65
2 × 9 × 55
fOSC

2 × 55
fOSC
2 × 49
fOSC
2 × 33
(f OSC: oscillation frequency, f CL: display clock frequency, f FR: LCD AC signal frequency)
[* Remark Solves]
*1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage
assurance during access from the MPU.
*2. In case of external power supply is applied.
*3. CS1B, CS2, RS, DB0 to DB7, E_RDB, RW_WRB, RESETB, MS, C68, PS, INTRS, HPMB, CLS, CL, M, FR,
DISP pins.
*4. DB0 to DB7, M, FR, DISP, CL pins.
*5. CS1B, CS2, RS, DB[7:0], E_RDB, RW_WRB, RESETB, MS, C68, PS, INTRS, HPMB, CLS, CL, M, FR, DISP
pins.
*6. Applies when the DB[7:0], M, FR, DISP, and CL pins are in high impedance.
*7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn.
RON = ∆V / 0.1 [kΩ] (∆V: voltage change when ± 0.1[mA] is applied in the ON status.)
*8. See table 21 for the relationship between oscillation frequency and frame frequency.
*9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range
*10. On-chip reference voltage source of the voltage regulator circuit to adjust V0.
*11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU.
The current consumption, when the built-in power supply circuit is ON or OFF.
The current flowing through voltage regulation resistors (Ra and Rb) is not included.
It does not include the current of the LCD panel capacity, wiring capacity, etc.
53
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
AC CHARACTERISTICS
Read / Write Characteristics (8080-series MPU)
RS
tAS80
tAH80
CS1B
(CS2=1)
tCY80
tPW80(R),
RDB, WRB
0.9V DD
tPW80(W)
0.1VDD
tDS80
tDH80
DB0 to DB7
(Write)
tACC80
tOD80
DB0 to DB7
(Read)
Figure 30. Read / Write Characteristics (8080-series MPU)
Item
Address setup time
Address hold time
System cycle time
Pulse width (WRB)
Pulse width (RDB)
Data setup time
Data hold time
Read access time
Output disable time
54
Signal
RS
RS
RW_WRB
E_RDB
DB7
to
DB0
Symbol
tAS80
tAH80
tCY80
tPW80 (W)
tPW80 (R)
tDS80
tDH80
tACC80
tOD80
Min.
0
0
300
60
60
40
15
10
Typ.
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Max.
Unit
Remark
-
-
ns
-
-
ns
ns
ns
-
-
ns
-
140
100
ns
CL = 100 pF
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Read / Write Characteristics (6800-series Microprocessor)
RS
tAS68
tAH68
CS1B
(CS2=1)
tCY68
tPW68(R), tPW68(W)
E
0.1VDD
0.9VDD
tDS68
tDH68
DB0 to DB7
(Write)
tACC68
tOD68
DB0 to DB7
(Read)
Figure 31. Read / Write Characteristics (6800-series Microprocessor)
Item
Address setup time
Address hold time
Signal
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable pulse
Read
width
Write
Symbol
tAS68
tAH68
Min.
0
0
RS
tCY68
300
DB7
to
DB0
tDS68
tDH68
tACC68
tOD68
E_RDB
tPW68(R)
tPW68(W)
40
15
10
120
60
RS
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Typ.
Max.
Unit
Remark
-
-
ns
-
-
ns
-
-
ns
-
140
100
ns
-
-
-
CL = 100 pF
55
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Serial Interface Characteristics
tCSS
CS1B
(CS2 = 1)
tCHS
tASS
tAHS
RS
tCYS
DB6
(SCLK)
0.9VDD
0.1VDD
tWLS
tWHS
tDSS
tDHS
DB7
(SID)
Figure 32. Serial Interface Characteristics
56
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Max.
Unit
Remark
Item
Signal
Symbol
Min.
Typ.
Serial clock cycle
SCLK high pulse width
SCLK low pulse width
DB6
(SCLK)
tCYS
tWHS
tWLS
250
100
100
-
-
ns
Address setup time
Address hold time
RS
tASS
tAHS
150
150
-
-
ns
Data setup time
Data hold time
DB7
(SID)
tDSS
tDHS
100
100
-
-
ns
CS1B setup time
CS1B hold time
CS1B
tCSS
tCHS
150
150
-
-
ns
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Reset Input Timing
tRW
RESETB
tR
Internal
status
During reset
Reset complete
Figure 33. Reset Input Timing
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Remark
Max.
Unit
Item
Signal
Symbol
Min.
Typ.
Reset low pulse width
RESETB
tRW
1.0
-
-
µs
Reset time
-
tR
-
-
1.0
µs
Display Control Output Timing
tDFR
CL
(OUT)
FR
Figure 34. Display Control Output Timing
Item
Signal
Symbol
Min.
FR delay time
FR
tDFR
-
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Typ.
Remark
Max.
Unit
20
80
ns
CL = 50 pF
57
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
In Case of Interfacing with 6800-series (PS = "H", C68 = "H")
6800-series
MPU
CS1B
CS2
RS
E
RW
DB0 to DB7
RESETB
V DD
V DD
CS1B
CS2
RS
S6B0723
E_RDB
RW_WRB
DB0 to DB7
RESETB
C68
PS
Figure 35. Interfacing with 6800-series (PS = "H", C68 = "H")
In Case of Interfacing with 8080-series (PS = "H", C68 = "L")
CS1B
CS2
RS
8080-series
MPU
RDB
WRB
DB0 to DB7
RESETB
CS1B
CS2
RS
E_RDB
RW_WRB
S6B0723
DB0 to DB7
VSS
RESETB
C68
VDD
PS
Figure 36. Interfacing with 8080-series (PS = "H", C68 = "L")
In Case of Serial Interface (PS = "L", C68 = "H or L")
CS1B
CS2
MPU
RS
SID
SCLK
CS1B
CS2
RS
DB7(SID)
S6B0723
RESETB
DB6(SCLK)
RESETB
OPEN
V DD or VSS
V SS
DB0 to DB5
C68
PS
Figure 37. Serial Interface (PS = "L", C68 = "H or L")
58
S6B0723
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
CONNECTIONS BETWEEN S6B0723 AND LCD PANEL
Single Chip Structure (1/65 Duty Configurations)
♣
♦ ♥ ♠
Ξ 
♣
64 × 132 pixels
♣
SEG0
COMS
COM0
:
COM31
♦ ♥ ♠
♣
SEG131
S6B0723
(Bottom View)
COM32
:
COM63
COMS
Figure 38. SHL = 1, ADC = 0
COM31
:
COM0
COMS
S6B0723
(Top View)
SEG0
...........
♣
♦ ♥ ♠
COMS
COM63
:
COM32
SEG131
Ξ 
64 × 132 pixels
♣
♦ ♥ ♠
Ξ 
64 × 132 pixels
Ξ 
...........
♦ ♥ ♠
Ξ 
Figure 40. SHL = 0, ADC = 0
♦ ♥ ♠
SEG131
COM32
:
COM63
COMS
Ξ 
...........
SEG0
COMS
COM0
:
COM31
S6B0723
(Top View)
Figure 39. SHL = 1, ADC = 1
COMS
COM63
:
COM32
S6B0723
(Bottom View)
SEG131
............
♣
♦ ♥ ♠
COM31
:
COM0
COMS
SEG0
Ξ 
64 × 132 pixels
♣
♦ ♥ ♠
Ξ 
Figure 41. SHL = 0, ADC = 1
59
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Single Chip Structure (1/55 Duty Configurations)
♣
♦ ♥ ♠
Ξ 
♣
54 × 132 pixels
♣
SEG0
COMS
COM0
:
COM26
♦ ♥ ♠
♣
SEG131
S6B0723
(Bottom View)
COM37
:
COM63
COMS
Figure 42. SHL = 1, ADC = 0
COM26
:
COM0
COMS
S6B0723
(Top View)
SEG0
...........
♣
♦ ♥ ♠
COMS
COM63
:
COM37
SEG131
Ξ 
54 × 132 pixels
♣
♦ ♥ ♠
Ξ 
Figure 44. SHL = 0, ADC = 0
60
Ξ 
54 × 132 pixels
Ξ 
...........
♦ ♥ ♠
♦ ♥ ♠
SEG131
COM37
:
COM63
COMS
Ξ 
...........
SEG0
COMS
COM0
:
COM26
S6B0723
(Top View)
Figure 43. SHL = 1, ADC = 1
COMS
COM63
:
COM37
S6B0723
(Bottom View)
SEG131
............
♣
♦ ♥ ♠
COM26
:
COM0
COMS
SEG0
Ξ 
54 × 132 pixels
♣
♦ ♥ ♠
Ξ 
Figure 45. SHL = 0, ADC = 1
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Single Chip Structure (1/49 Duty Configurations)
♣
♦ ♥ ♠
Ξ 
♣
48 × 132 pixels
♣
SEG0
COMS
COM0
:
COM23
♦ ♥ ♠
♣
SEG131
S6B0723
(Bottom View)
COM40
:
COM63
COMS
Figure 46. SHL = 1, ADC = 0
COM23
:
COM0
COMS
S6B0723
(Top View)
SEG0
...........
♣
♦ ♥ ♠
COMS
COM63
:
COM40
SEG131
Ξ 
48 × 132 pixels
♣
♦ ♥ ♠
Ξ 
48 × 132 pixels
Ξ 
...........
♦ ♥ ♠
Ξ 
Figure 48. SHL = 0, ADC = 0
♦ ♥ ♠
SEG131
COM40
:
COM63
COMS
Ξ 
...........
SEG0
COMS
COM0
:
COM23
S6B0723
(Top View)
Figure 47. SHL = 1, ADC = 1
COMS
COM63
:
COM40
S6B0723
(Bottom View)
SEG131
............
♣
♦ ♥ ♠
COM23
:
COM0
COMS
SEG0
Ξ 
48 × 132 pixels
♣
♦ ♥ ♠
Ξ 
Figure 49. SHL = 0, ADC = 1
61
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723
Single Chip Structure (1/33 Duty Configurations)
♣
♦ ♥ ♠
Ξ 
♣
32 × 132 pixels
♣
SEG0
COMS
COM0
:
COM15
♦ ♥ ♠
♣
SEG131
S6B0723
(Bottom View)
COM48
:
COM63
COMS
Figure 50. SHL = 1, ADC = 0
COM15
:
COM0
COMS
S6B0723
(Top View)
SEG0
...........
♣
♦ ♥ ♠
COMS
COM63
:
COM48
SEG131
Ξ 
32 × 132 pixels
♣
♦ ♥ ♠
Ξ 
Figure 52. SHL = 0, ADC = 0
62
Ξ 
32 × 132 pixels
Ξ 
...........
♦ ♥ ♠
♦ ♥ ♠
SEG131
COM48
:
COM63
COMS
Ξ 
...........
SEG0
S6B0723
(Top View)
COMS
COM0
:
COM15
Figure 51. SHL = 1, ADC = 1
COMS
COM63
:
COM48
S6B0723
(Bottom View)
SEG131
............
♣
♦ ♥ ♠
COM15
:
COM0
COMS
SEG0
Ξ 
32 × 132 pixels
♣
♦ ♥ ♠
Ξ 
Figure 53. SHL = 0, ADC = 1
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Multiple Chip Structure
- 65COM (64COM + 1COMS) × 264SEG (132SEG × 2)
♣
♦ ♥ ♠
Ξ 
64 × 264 pixels
♣
SEG131
...............
COM32
:
COM63
COMS
S6B0723
(Top View)
(Master)
♦ ♥ ♠
SEG0
Ξ 
SEG131
COMS
COM0
:
COM31
COM32
:
COM63
COMS
...............
S6B0723
(Top View)
(Slave)
SEG0
COMS
COM0
:
COM31
Figure 54. SHL = 1, ADC = 1
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
COM31
:
COM0
COMS
S6B0723
(Top View)
(Master)
SEG0
...................
COMS
COM63
:
COM32
SEG131
♣
COM31
:
COM0
COMS
SEG0
♦ ♥ ♠
S6B0723
(Top View)
(Slave)
...................
COMS
COM63
:
COM32
SEG131
Ξ 
64 × 264 pixels
♣
♦ ♥ ♠
Ξ 
Figure 55. SHL = 0, ADC = 0
♦
Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
63
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
- 130COM (128COM + 2COMS) × 132SEG
COM31
:
COM0
COMS
COMS
COM63
:
COM32
S6B0723
(Top View)
(Master)
SEG0
...................
♣
♦
♥
♠
SEG131
Ξ

128 × 132 pixels
♣
SEG131
COM32
:
COM63
COMS
♦
♥
♠
Ξ
...................

SEG0
S6B0723
(Top View)
(Slave)
COMS
COM0
:
COM31
Figure 56. 130COM (128COM + 2COMS) × 132SEG
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
♦ Common/Segment output direction select
- Master chip: SHL = 0, ADC = 0
- Slave chip: SHL = 1, ADC = 1
64
S6B0723
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0723 APPLICATION CIRCUIT (6800 / 8080 / SERIAL)
S6B0723 Application Circuit for 6800-series
n
n
Package Type: TCP
Device Mode: Master Mode, Internal OSC, Normal Mode, 4 Times Boost-up, Internal Rb / Ra
S6B0723
FRS
FR
TEST1
TEST2
TEST3
M
CL
DISP
TEST4
VSS
CS1B
CS2
VDD
RESETB
RS
VSS
RW_WRB
E_RDB
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VDD
DUTY0
DUTY1
VSS
VDD [3]
VCI [2]
VSS [3]
VOUT [2]
C4+ [2]
C3+ [2]
C1- [2]
C1+ [2]
C2+ [2]
C2- [2]
VDD
VEXT
REF
VSS
V1 [2]
V2 [2]
V3 [2]
V4 [2]
V0 [2]
VR [2]
VSS [2]
VDD
MS
CLS
VSS
C68
PS
VDD
HPMB
VSS
INTRS
VDD
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
V DD
V SS
TCP outside
Figure 57. S6B0723 Application Circuit for 68-series
65
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
S6B0723 Application Circuit for 8080-series
n
n
Package Type: TCP
Device Mode: Master Mode, Internal OSC, Normal Mode, 4 Times Boost-up, Internal Rb / Ra
S6B0723
FRS
FR
TEST1
TEST2
TEST3
M
CL
DISP
TEST4
VSS
CS1B
CS2
VDD
RESETB
RS
VSS
RW_WRB
E_RDB
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VDD
DUTY0
DUTY1
VSS
VDD [3]
VCI [2]
VSS [3]
VOUT [2]
C4+ [2]
C3+ [2]
C1- [2]
C1+ [2]
C2+ [2]
C2- [2]
VDD
VEXT
REF
VSS
V1 [2]
V2 [2]
V3 [2]
V4 [2]
V0 [2]
VR [2]
VSS [2]
VDD
MS
CLS
VSS
C68
PS
VDD
HPMB
VSS
INTRS
VDD
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
MPU
V DD
V SS
TCP outside
Figure 58. S6B0723 Application Circuit for 80-series
66
S6B0723
S6B0723
PRELIMINARY SPEC. VER. 0.9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0723 Application Circuit for Serial
n
n
Package Type: TCP
Device Mode: Master Mode, Internal OSC, Normal Mode, 4 Times Boost-up, Internal Rb / Ra
S6B0723
FRS
FR
TEST1
TEST2
TEST3
M
CL
DISP
TEST4
VSS
CS1B
CS2
VDD
RESETB
RS
VSS
RW_WRB
E_RDB
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6 (SCL)
DB7 (SI)
VSS
VDD
DUTY0
DUTY1
VSS
VDD [3]
VCI [2]
VSS [3]
VOUT [2]
C4+ [2]
C3+ [2]
C1- [2]
C1+ [2]
C2+ [2]
C2- [2]
VDD
VEXT
REF
VSS
V1 [2]
V2 [2]
V3 [2]
V4 [2]
V0 [2]
VR [2]
VSS [2]
VDD
MS
CLS
VSS
C68
PS
VDD
HPMB
VSS
INTRS
VDD
MPU
MPU
MPU
MPU
MPU
V DD
V SS
TCP outside
Figure 59. S6B0723 Application Circuit for Serial
67
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.9
TCP PIN LAYOUT (SAMPLE)
S6B0723
(TOP VIEW)
TEST1 (PAD_CK)
TEST2 (SCL)
TEST3 (SDA)
M
CL
DISP
TEST4
CS1B
CS2
RESETB
RS
RW_WRB
E_RDB
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DUTY0
DUTY1
VDD
VCI
VSS
VOUT
C4+
C3+
C1C1+
C2+
C2VEXT
REF
V1
V2
V3
V4
V0
VR
MS
CLS
C68
PS
HPMB
INTRS
Figure 60. TCP Pin Layout
68
FR
FRS
COMS
COM63
COM62
:
:
:
COM48
COM47
COM46
:
:
:
COM35
COM34
COM33
COM32
SEG131
SEG130
SEG129
SEG128
:
:
:
:
SEG66
SEG65
SEG64
SEG63
:
:
:
:
SEG3
SEG2
SEG1
SEG0
COMS
COM0
COM1
:
:
:
COM15
COM16
COM17
:
:
:
COM28
COM29
COM30
COM31
S6B0723
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