Bank VREF (2) Optional Function(s)

Bank VREF (2) Optional Function(s)
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
VREF
PinName/Function (2)
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
TDO
nCSO
TMS
AS_DATA3
TCK
AS_DATA2
TDI
AS_DATA1
DCLK
AS_DATA0,ASDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
CLK0n,FPLL_BL_FBn
CLK0p,FPLL_BL_FBp
FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn
FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB
CLK1n
CLK1p
RZQ_0
CLK2n
CLK2p
CLK3n
CLK3p
Configuration
Function
TDO
DATA4
TMS
DATA3
TCK
DATA2
TDI
DATA1
DCLK
DATA0
DATA6
DATA5
DATA8
DATA7
DATA10
DATA9
DATA12
DATA11
DATA14
DATA13
CLKUSR
DATA15
PR_DONE
PR_READY
PR_ERROR
Dedicated Tx/Rx
Channel
DIFFIO_RX_B1n
DIFFIO_TX_B2n
DIFFIO_RX_B1p
DIFFIO_TX_B2p
DIFFIO_RX_B3n
DIFFIO_TX_B4n
DIFFIO_RX_B3p
DIFFIO_TX_B4p
DIFFIO_RX_B5n
DIFFIO_TX_B6n
DIFFIO_RX_B5p
DIFFIO_TX_B6p
DIFFIO_RX_B7n
DIFFIO_TX_B8n
DIFFIO_RX_B7p
DIFFIO_TX_B8p
DIFFIO_TX_B25n
DIFFIO_RX_B26n
DIFFIO_TX_B25p
DIFFIO_RX_B26p
DIFFIO_RX_B27n
DIFFIO_TX_B28n
DIFFIO_RX_B27p
DIFFIO_TX_B28p
DIFFIO_TX_B29n
DIFFIO_RX_B30n
DIFFIO_TX_B29p
DIFFIO_RX_B30p
DIFFIO_RX_B31n
DIFFIO_TX_B32n
DIFFIO_RX_B31p
DIFFIO_TX_B32p
DIFFIO_TX_B33n
DIFFIO_RX_B34n
DIFFIO_TX_B33p
DIFFIO_RX_B34p
DIFFIO_RX_B35n
DIFFIO_TX_B36n
DIFFIO_RX_B35p
DIFFIO_TX_B36p
DIFFIO_TX_B37n
DIFFIO_RX_B38n
DIFFIO_TX_B37p
DIFFIO_RX_B38p
DIFFIO_RX_B39n
DIFFIO_TX_B40n
DIFFIO_RX_B39p
DIFFIO_TX_B40p
DIFFIO_TX_B41n
DIFFIO_RX_B42n
DIFFIO_TX_B41p
DIFFIO_RX_B42p
DIFFIO_RX_B43n
DIFFIO_TX_B44n
DIFFIO_RX_B43p
DIFFIO_TX_B44p
DIFFIO_TX_B45n
DIFFIO_RX_B46n
DIFFIO_TX_B45p
DIFFIO_RX_B46p
DIFFIO_RX_B47n
DIFFIO_TX_B48n
DIFFIO_RX_B47p
DIFFIO_TX_B48p
DIFFIO_RX_B50n
DIFFIO_TX_B49p
DIFFIO_RX_B50p
DIFFIO_RX_B51n
DIFFIO_TX_B52n
DIFFIO_RX_B51p
DIFFIO_TX_B52p
DIFFIO_TX_B53n
DIFFIO_RX_B54n
DIFFIO_TX_B53p
DIFFIO_RX_B54p
DIFFIO_RX_B55n
DIFFIO_TX_B56n
DIFFIO_RX_B55p
DIFFIO_TX_B56p
DIFFIO_RX_B58n
DIFFIO_TX_B57p
DIFFIO_RX_B58p
DIFFIO_RX_B59n
DIFFIO_TX_B60n
DIFFIO_RX_B59p
DIFFIO_TX_B60p
DIFFIO_TX_B61n
DIFFIO_RX_B62n
DIFFIO_TX_B61p
DIFFIO_RX_B62p
DIFFIO_TX_B64n
DIFFIO_TX_B64p
DIFFIO_RX_B66n
DIFFIO_TX_B65p
DIFFIO_RX_B66p
DIFFIO_RX_B67n
DIFFIO_TX_B68n
DIFFIO_RX_B67p
DIFFIO_TX_B69n
DIFFIO_RX_B70n
DIFFIO_TX_B69p
DIFFIO_RX_B70p
DIFFIO_TX_B72n
DIFFIO_TX_B72p
DIFFIO_RX_B74n
Emulated LVDS
Output Channel
DIFFOUT_B1n
DIFFOUT_B2n
DIFFOUT_B1p
DIFFOUT_B2p
DIFFOUT_B3n
DIFFOUT_B4n
DIFFOUT_B3p
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B6n
DIFFOUT_B5p
DIFFOUT_B6p
DIFFOUT_B7n
DIFFOUT_B8n
DIFFOUT_B7p
DIFFOUT_B8p
DIFFOUT_B25n
DIFFOUT_B26n
DIFFOUT_B25p
DIFFOUT_B26p
DIFFOUT_B27n
DIFFOUT_B28n
DIFFOUT_B27p
DIFFOUT_B28p
DIFFOUT_B29n
DIFFOUT_B30n
DIFFOUT_B29p
DIFFOUT_B30p
DIFFOUT_B31n
DIFFOUT_B32n
DIFFOUT_B31p
DIFFOUT_B32p
DIFFOUT_B33n
DIFFOUT_B34n
DIFFOUT_B33p
DIFFOUT_B34p
DIFFOUT_B35n
DIFFOUT_B36n
DIFFOUT_B35p
DIFFOUT_B36p
DIFFOUT_B37n
DIFFOUT_B38n
DIFFOUT_B37p
DIFFOUT_B38p
DIFFOUT_B39n
DIFFOUT_B40n
DIFFOUT_B39p
DIFFOUT_B40p
DIFFOUT_B41n
DIFFOUT_B42n
DIFFOUT_B41p
DIFFOUT_B42p
DIFFOUT_B43n
DIFFOUT_B44n
DIFFOUT_B43p
DIFFOUT_B44p
DIFFOUT_B45n
DIFFOUT_B46n
DIFFOUT_B45p
DIFFOUT_B46p
DIFFOUT_B47n
DIFFOUT_B48n
DIFFOUT_B47p
DIFFOUT_B48p
DIFFOUT_B50n
DIFFOUT_B49p
DIFFOUT_B50p
DIFFOUT_B51n
DIFFOUT_B52n
DIFFOUT_B51p
DIFFOUT_B52p
DIFFOUT_B53n
DIFFOUT_B54n
DIFFOUT_B53p
DIFFOUT_B54p
DIFFOUT_B55n
DIFFOUT_B56n
DIFFOUT_B55p
DIFFOUT_B56p
DIFFOUT_B58n
DIFFOUT_B57p
DIFFOUT_B58p
DIFFOUT_B59n
DIFFOUT_B60n
DIFFOUT_B59p
DIFFOUT_B60p
DIFFOUT_B61n
DIFFOUT_B62n
DIFFOUT_B61p
DIFFOUT_B62p
DIFFOUT_B64n
DIFFOUT_B64p
DIFFOUT_B66n
DIFFOUT_B65p
DIFFOUT_B66p
DIFFOUT_B67n
DIFFOUT_B68n
DIFFOUT_B67p
DIFFOUT_B69n
DIFFOUT_B70n
DIFFOUT_B69p
DIFFOUT_B70p
DIFFOUT_B72n
DIFFOUT_B72p
DIFFOUT_B74n
U672
Y9
AA6
AC7
AB6
AB5
AC5
W10
AC6
AA8
AD7
Y8
Y4
W8
Y5
T8
AB4
U9
AA4
V10
AD4
U10
AC4
AA11
AE6
Y11
AD5
AF4
AE9
AE4
AD10
U11
AF8
T11
AE7
AF9
AE11
AE8
AD11
W11
AF6
V11
AF5
AG6
AF10
AF7
AF11
T12
AH2
T13
AH3
AH4
AD12
AG5
AE12
W12
AH5
V12
AH6
AH7
AF13
AG8
AG13
U13
AH8
U14
AG9
AH9
AE15
AG10
AF15
AA13
AH11
Y13
AG11
AG16
AH12
AF17
V13
AH13
W14
AG14
AH14
AE17
AG15
AD17
AA15
AH16
Y15
AH17
AD19
AF18
AE19
AA18
AH18
AA19
AG18
AH19
AD20
AG19
AE20
AG20
AF20
AF21
AG21
AF22
AE22
AH21
AD23
AH22
AF23
AH23
AG23
AH24
AG24
AE23
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
GND
DQ2B
DQ2B
DQ2B
DQ2B
GND
B_A_15
B_WE#
B_A_14
B_CS#_1
B_A_13
B_CS#_0
B_A_12
B_A_11
B_A_9
B_A_10
B_A_8
DQ2B
B_RAS#
DQ2B
DQ3B
DQ3B
DQ3B
DQ3B
B_CAS#
GND
B_BA_2
B_BA_0
B_BA_1
B_CK#
B_A_7
B_CK
B_A_6
B_A_3
B_A_5
B_A_2
B_A_4
B_CK#
B_CA_7
B_CK
B_CA_6
B_CA_3
B_CA_5
B_CA_2
B_CA_4
DQ3B
B_A_1
B_CA_1
DQ3B
B_A_0
B_CA_0
DQ4B
DQ4B
DQ4B
DQSn4B
DQ4B
DQS4B
B_DQ_0
B_DQ_2
B_DQ_1
B_DQS#_0
B_DQ_3
B_DQS_0
B_ODT_0
B_ODT_1
B_DQ_4
B_DQ_6
B_DQ_5
B_DQ_0
B_DQ_2
B_DQ_1
B_DQS#_0
B_DQ_3
B_DQS_0
B_ODT_0
B_ODT_1
B_DQ_4
B_DQ_6
B_DQ_5
B_DQ_7
B_DQ_7
B_DM_0
B_DQ_8
B_DQ_10
B_DQ_9
B_DQS#_1
B_DQ_11
B_DQS_1
B_CKE_1
B_CKE_0
B_DQ_12
B_DQ_14
B_DQ_13
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
DQ1B
DQ1B
DQ1B
DQSn1B
DQ1B
DQS1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQSn2B
DQ2B
DQS2B
DQ3B
DQ3B
DQ3B
DQSn3B
DQ3B
DQS3B
DQ4B
DQ4B
DQ4B
DQ4B
DQ4B
B_CS#_1
B_CS#_0
B_CA_9
B_CA_8
GND
DQ4B
DQ5B
DQ5B
DQ5B
DQSn5B
DQ5B
DQS5B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ5B
DQ5B
DQ5B
DQ5B
DQ1B
DQ1B
DQ1B
DQ1B
B_DM_0
B_DQ_8
B_DQ_10
B_DQ_9
B_DQS#_1
B_DQ_11
B_DQS_1
B_CKE_1
B_CKE_0
B_DQ_12
B_DQ_14
B_DQ_13
DQ5B
DQ1B
B_DQ_15
B_DQ_15
DQ5B
DQ6B
DQ6B
DQ6B
DQSn6B
DQ6B
DQS6B
DQ1B
DQ1B
DQ1B
DQ1B
DQSn1B
DQ1B
DQS1B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ6B
DQ7B
DQ7B
DQ7B
DQSn7B
DQ7B
DQS7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ7B
DQ8B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
B_DM_1
B_DQ_16
B_DQ_18
B_DQ_17
B_DQS#_2
B_DQ_19
B_DQS_2
B_RESET#
GND
B_DQ_20
B_DQ_22
B_DQ_21
B_DQ_23
B_DM_2
B_DQ_24
B_DQ_26
B_DQ_25
B_DQS#_3
B_DQ_27
B_DQS_3
GND
B_DQ_28
B_DQ_30
B_DQ_29
B_DQ_31
B_DM_3
B_DQ_32
B_DM_1
B_DQ_16
B_DQ_18
B_DQ_17
B_DQS#_2
B_DQ_19
B_DQS_2
B_RESET#
GND
B_DQ_20
B_DQ_22
B_DQ_21
B_DQ_23
B_DM_2
B_DQ_24
B_DQ_26
B_DQ_25
B_DQS#_3
B_DQ_27
B_DQS_3
GND
B_DQ_28
B_DQ_30
B_DQ_29
B_DQ_31
B_DM_3
B_DQ_32
Pin List U23
Page 1 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5B
5B
5B
5B
5B
5B
5B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREF
PinName/Function (2)
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI13
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI12
HPS_GPI11
HPS_DDR
HPS_GPI10
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6BN0_HPS
HPS_DDR
HPS_GPI9
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI8
HPS_GPI7
HPS_DDR
HPS_GPI6
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI5
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI4
HPS_GPI3
HPS_DDR
HPS_GPI2
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI1
HPS_GPI0
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
RZQ_1
INIT_DONE
PR_REQUEST
CRC_ERROR
nCEO
CvP_CONFDONE
DEV_OE
DEV_CLRn
CLK5p
FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB
CLK5n
FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn
CLK4p,FPLL_BR_FBp
CLK4n,FPLL_BR_FBn
RZQ_2
Dedicated Tx/Rx
Channel
DIFFIO_TX_B73p
DIFFIO_RX_B74p
DIFFIO_RX_B75n
DIFFIO_TX_B76n
DIFFIO_RX_B75p
DIFFIO_TX_B77n
DIFFIO_RX_B78n
DIFFIO_TX_B77p
DIFFIO_RX_B78p
DIFFIO_TX_B80n
DIFFIO_TX_B80p
DIFFIO_TX_R1p
DIFFIO_RX_R2p
DIFFIO_TX_R1n
DIFFIO_RX_R2n
DIFFIO_TX_R3p
DIFFIO_RX_R4p
DIFFIO_TX_R3n
DIFFIO_RX_R4n
DIFFIO_TX_R5p
DIFFIO_RX_R6p
DIFFIO_TX_R5n
DIFFIO_RX_R6n
DIFFIO_TX_R7p
DIFFIO_RX_R8p
DIFFIO_TX_R7n
DIFFIO_RX_R8n
DIFFIO_RX_R21p
DIFFIO_TX_R22p
DIFFIO_RX_R21n
DIFFIO_TX_R22n
DIFFIO_RX_R23p
DIFFIO_RX_R23n
DIFFIO_TX_R24n
Emulated LVDS
Output Channel
DIFFOUT_B73p
DIFFOUT_B74p
DIFFOUT_B75n
DIFFOUT_B76n
DIFFOUT_B75p
DIFFOUT_B77n
DIFFOUT_B78n
DIFFOUT_B77p
DIFFOUT_B78p
DIFFOUT_B80n
DIFFOUT_B80p
DIFFOUT_R1p
DIFFOUT_R2p
DIFFOUT_R1n
DIFFOUT_R2n
DIFFOUT_R3p
DIFFOUT_R4p
DIFFOUT_R3n
DIFFOUT_R4n
DIFFOUT_R5p
DIFFOUT_R6p
DIFFOUT_R5n
DIFFOUT_R6n
DIFFOUT_R7p
DIFFOUT_R8p
DIFFOUT_R7n
DIFFOUT_R8n
DIFFOUT_R21p
DIFFOUT_R22p
DIFFOUT_R21n
DIFFOUT_R22n
DIFFOUT_R23p
DIFFOUT_R23n
DIFFOUT_R24n
U672
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
AG26
AE24
AC23
AH26
AC22
AH27
AG25
AG28
AF25
AF28
AF27
AF26
AA20
AE26
Y19
AE25
Y17
AD26
Y18
AC24
Y16
AB23
W15
AA24
V16
AA23
V15
W21
AB26
W20
AA26
Y24
W24
AB25
AE28
AD28
V20
AE27
V19
V18
V24
V17
V25
U25
AC28
T26
AC27
U16
AB28
U15
AA27
T24
Y27
R24
T27
U19
Y26
T20
W26
R25
AA28
R26
Y28
T16
W28
T17
V27
N27
R27
N26
P26
T19
V28
T18
U28
N25
T28
N24
R28
R21
P28
R20
N28
M26
M28
M27
L28
R19
K28
R18
J28
L25
J27
K25
K27
M25
G28
F28
K26
G27
J26
G26
R17
D28
R16
D27
J24
E28
J25
H28
C28
B28
J21
E26
J20
DQ8B
DQ8B
DQSn8B
DQ8B
DQS8B
DQ8B
DQ8B
DQ8B
DQ8B
DQ8B
DQ8B
DQ1R
DQ2B
DQ2B
DQSn2B
DQ2B
DQS2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
B_DQ_34
B_DQ_33
B_DQS#_4
B_DQ_35
B_DQS_4
GND
B_DQ_36
B_DQ_38
B_DQ_37
B_DQ_39
B_DM_4
HMC Pin Assignment for
LPDDR2
B_DQ_34
B_DQ_33
B_DQS#_4
B_DQ_35
B_DQS_4
GND
B_DQ_36
B_DQ_38
B_DQ_37
B_DQ_39
B_DM_4
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS_DM_3
HPS_DM_3
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQS_3
HPS_DQS_3
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DM_2
HPS_DM_2
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQS1R
DQ1R
DQSn1R
DQ1R
DQ1R
DQ1R
Pin List U23
HPS_DM_1
HPS_DM_1
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_A_0
HPS_A_1
HPS_A_4
HPS_A_2
HPS_A_5
HPS_CA_0
HPS_CA_1
HPS_CA_4
HPS_CA_2
HPS_CA_5
Page 2 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREF
PinName/Function (2)
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_RZQ_0
GND
GND
HPS_nRST
HPS_nPOR
HPS_TDO
VCCRSTCLK_HPS
HPS_TMS
HPS_TCK
HPS_TRST
HPS_TDI
GND
HPS_PORSEL
HPS_CLK1
HPS_CLK2
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0,BOOTSEL0
UART0_RX
UART0_TX,CLKSEL1
I2C0_SDA
I2C0_SCL
CAN0_RX
CAN0_TX,CLKSEL0
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE,BOOTSEL2
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0,BOOTSEL1
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
IO
IO
IO
IO
IO
IO
MSEL0
CONF_DONE
MSEL1
nSTATUS
nCE
MSEL2
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
8A
8A
8A
8A
8A
8A
9A
9A
9A
9A
9A
9A
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
CLK7p
CLK7n
FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn
CLK6p,FPLL_TL_FBp
CLK6n,FPLL_TL_FBn
Dedicated Tx/Rx
Channel
DIFFIO_RX_T1p
DIFFIO_RX_T1n
DIFFIO_TX_T4p
DIFFIO_TX_T4n
DIFFIO_RX_T9p
DIFFIO_RX_T9n
MSEL0
CONF_DONE
MSEL1
nSTATUS
nCE
MSEL2
Emulated LVDS
Output Channel
DIFFOUT_T1p
DIFFOUT_T1n
DIFFOUT_T4p
DIFFOUT_T4n
DIFFOUT_T9p
DIFFOUT_T9n
U672
DQS for X8
D26
N21
C26
N20
B26
H25
A27
G25
A26
A25
F26
A24
F25
B24
L21
D24
L20
C24
G23
E25
F24
D25
F23
E23
A23
H19
B23
J19
C23
K19
C22
D22
D21
E18
E20
D20
C21
A22
B21
A21
K18
A20
J18
A19
C18
A18
C17
B18
J17
A17
H17
C19
B16
B19
C16
J15
A16
J14
A15
D17
A14
E16
A13
J13
A12
J12
A11
C15
A9
D15
A8
H16
A7
J16
A6
C14
B14
D14
A5
C13
B6
H13
A4
H12
B4
B12
B8
B11
B9
E4
C10
F5
C9
C4
C8
D4
C7
F4
C6
G4
C5
E5
D5
D12
C12
E8
D8
E11
D11
J10
J8
H9
H8
E6
G6
DQS for X16
HMC Pin Assignment for DDR3
HPS_A_3
HPS_CK
HPS_A_6
HPS_CK#
HPS_A_7
HPS_BA_1
HPS_BA_0
HPS_BA_2
HPS_CAS#
HPS_RAS#
HPS_A_8
HPS_A_10
HPS_A_9
HPS_A_11
HPS_CS#_0
HPS_A_12
HPS_CS#_1
HPS_A_13
HPS_A_14
HPS_WE#
HPS_A_15
HMC Pin Assignment for
LPDDR2
HPS_CA_3
HPS_CK
HPS_CA_6
HPS_CK#
HPS_CA_7
HPS Pin Mux Select 3
HPS Pin Mux Select 1
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
SPIS1_CLK
SPIS1_MOSI
SPIS1_SS0
SPIS1_MISO
I2C1_SDA
I2C1_SCL
CAN1_RX
CAN1_TX
CAN0_RX
CAN0_TX
UART1_RX
UART1_TX
UART0_RX
UART0_TX
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RXD0
RGMII1_MDIO
RGMII1_MDC
RGMII1_RX_CTL
RGMII1_TX_CTL
RGMII1_RX_CLK
RGMII1_RXD1
RGMII1_RXD2
RGMII1_RXD3
QSPI_SS1
UART0_RX
UART0_TX
I2C1_SDA
I2C1_SCL
CAN1_RX
CAN1_TX
I2C0_SDA
I2C0_SCL
UART0_CTS
UART0_RTS
UART1_CTS
UART1_RTS
SPIM0_SS1
SPIM1_SS1
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
QSPI_SS3
USB1_D0
USB1_D1
USB1_D2
USB1_D3
HPS Pin Mux Select 0
HPS_CA_8
HPS_CA_9
HPS_CS#_0
HPS_CS#_1
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
UART0_RX
UART0_TX
I2C0_SDA
I2C0_SCL
CAN0_RX
CAN0_TX
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
Pin List U23
HPS Pin Mux Select 2
I2C3_SDA
I2C3_SCL
USB1_D4
USB1_D5
USB1_D6
USB1_D7
QSPI_SS2
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
USB0_D0
USB0_D1
USB0_D2
USB0_D3
USB0_D4
USB0_D5
USB0_D6
USB0_D7
USB0_CLK
USB0_STP
USB0_DIR
USB0_NXT
USB1_D0
USB1_D1
USB1_D2
USB1_D3
USB1_D4
USB1_D5
USB1_D6
USB1_D7
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
I2C2_SDA
I2C2_SCL
HPS_GPIO48
HPS_GPIO49
HPS_GPIO50
HPS_GPIO51
HPS_GPIO52
HPS_GPIO53
HPS_GPIO54
HPS_GPIO55
HPS_GPIO56
HPS_GPIO57
HPS_GPIO58
HPS_GPIO59
HPS_GPIO60
HPS_GPIO61
HPS_GPIO62
HPS_GPIO63
HPS_GPIO64
HPS_GPIO65
HPS_GPIO66
HPS_GPIO14
HPS_GPIO15
HPS_GPIO16
HPS_GPIO17
HPS_GPIO18
HPS_GPIO19
HPS_GPIO20
HPS_GPIO21
HPS_GPIO22
HPS_GPIO23
HPS_GPIO24
HPS_GPIO25
HPS_GPIO26
HPS_GPIO27
HPS_GPIO28
HPS_GPIO29
HPS_GPIO30
HPS_GPIO31
HPS_GPIO32
HPS_GPIO33
HPS_GPIO34
HPS_GPIO35
HPS_GPIO36
HPS_GPIO37
HPS_GPIO38
HPS_GPIO39
HPS_GPIO40
HPS_GPIO41
HPS_GPIO42
HPS_GPIO43
HPS_GPIO44
HPS_GPIO45
HPS_GPIO46
HPS_GPIO47
HPS_GPIO0
HPS_GPIO1
HPS_GPIO2
HPS_GPIO3
HPS_GPIO4
HPS_GPIO5
HPS_GPIO6
HPS_GPIO7
HPS_GPIO8
HPS_GPIO9
HPS_GPIO10
HPS_GPIO11
HPS_GPIO12
HPS_GPIO13
Page 3 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
9A
9A
9A
VREF
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
PinName/Function (2)
MSEL3
nCONFIG
MSEL4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Optional Function(s)
Configuration
Function
MSEL3
nCONFIG
MSEL4
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U672
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
K10
F7
K9
F6
N8
P8
F2
F1
K2
K1
P2
P1
V2
V1
AB2
AB1
AF2
AF1
V5
V4
A10
A3
AA1
AA17
AA2
AA3
AA9
AB24
AB27
AB3
AC1
AC2
AC3
AD14
AD22
AD25
AD3
AD6
AD8
AE1
AE16
AE18
AE2
AE3
AF24
AF3
AG1
AG17
AG2
AG27
AG3
AG7
AH10
AH20
B15
B17
B20
B22
B25
B27
B3
B5
B7
C1
C11
C2
C3
D10
D13
D16
D3
E1
E19
E2
E22
E24
E27
E3
E9
F3
G1
G2
G3
H11
H15
H18
H20
H24
H27
H3
H4
H5
H6
J1
J2
J3
J5
J9
K11
K12
K14
K16
K20
K3
K4
K8
L1
L10
L13
L15
L17
L19
L2
L24
L27
Pin List U23
Page 4 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VCCPGM
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U672
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
L3
L5
L8
L9
M10
M11
M14
M16
M20
M3
M8
N1
N13
N15
N17
N19
N2
N3
N4
P10
P12
P16
P18
P20
P25
P3
P5
P9
R1
R11
R13
R15
R2
R3
R8
T10
T14
T3
U1
U12
U17
U2
U20
U24
U27
U3
U5
V14
V3
V8
V9
W1
W16
W18
W2
W3
W4
Y12
Y14
Y20
Y25
Y3
V26
V21
J11
K13
K15
L11
L12
L14
M12
M13
M15
M9
N10
N11
N12
N14
N9
P11
P13
P14
P15
R10
R12
R14
R9
T15
T9
L4
T4
M5
N5
R5
T5
U26
A2
B2
D1
D2
H1
H2
M1
M2
T1
T2
Y1
Y2
AD1
AD2
U8
AE14
D23
E12
Y10
Pin List U23
Page 5 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
3A
3B
4A
5A
5B
8A
VREF
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB5AN0
VREFB5BN0
VREFB7A7B7C7DN0_HPS
VREFB8AN0
PinName/Function (2)
Optional Function(s)
VCCPGM
VCCPGM
VCCBAT
VCCIO3A
VCCIO3A
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO5A
VCCIO5A
VCCIO5B
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6A_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO6B_HPS
VCCIO7A_HPS
VCCIO7A_HPS
VCCIO7B_HPS
VCCIO7B_HPS
VCCIO7C_HPS
VCCIO7D_HPS
VCCIO7D_HPS
VCCIO8A
VCCPD3A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD5A
VCCPD5B
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD6A6B_HPS
VCCPD7A_HPS
VCCPD7B_HPS
VCCPD7C_HPS
VCCPD7D_HPS
VCCPD8A
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB5AN0
VREFB5BN0
VREFB7A7B7C7DN0_HPS
VREFB8AN0
VCCRSTCLK_HPS
RREF_TL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX
VCC_AUX_SHARED
VCCPLL_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
VCC_HPS
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
U672
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
AD24
H10
D7
AA5
W9
AA12
AE10
AE13
AG4
AA16
AE21
AF14
AF19
AG12
AG22
AH15
AH25
W13
AC25
W17
W25
C25
C27
F27
G24
H21
H26
L26
M21
AD27
P27
T21
T25
U18
W27
C20
D18
B13
H14
B10
D6
G5
E7
AA10
AA14
AD13
AD16
AD18
AD21
AD9
Y21
W19
K21
K24
M24
P21
P24
E21
E17
E14
E13
E10
AE5
AF12
AF16
AC26
AA25
D19
D9
F22
B1
K5
P4
U4
W5
J4
AA21
M4
R4
AC21
AC8
AD15
E15
F8
F21
H23
U21
K17
L16
L18
M17
M18
M19
N16
N18
P17
P19
Notes:
(1) For more information about pin definitions and pin connection guidelines, refer to the
Cyclone V Device Family Pin Connection Guidelines.
(2) HPS_DDR pins are for memory interface only. For the dedicated pin function corresponding with the respective memory interfaces, refer to the HMC columns.
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Pin List U23
Page 6 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
VREF
PinName/Function (2)
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3AN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB3BN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
TDO
nCSO
TMS
AS_DATA3
TCK
AS_DATA2
TDI
AS_DATA1
DCLK
AS_DATA0,ASDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
CLK0n,FPLL_BL_FBn
CLK0p,FPLL_BL_FBp
FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTn
FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTp,FPLL_BL_FB
CLK1n
CLK1p
RZQ_0
CLK2n
CLK2p
Configuration
Function
TDO
DATA4
TMS
DATA3
TCK
DATA2
TDI
DATA1
DCLK
DATA0
DATA6
DATA5
DATA8
DATA7
DATA10
DATA9
DATA12
DATA11
DATA14
DATA13
CLKUSR
DATA15
PR_DONE
PR_READY
PR_ERROR
Dedicated Tx/Rx
Channel
DIFFIO_RX_B1n
DIFFIO_TX_B2n
DIFFIO_RX_B1p
DIFFIO_TX_B2p
DIFFIO_RX_B3n
DIFFIO_TX_B4n
DIFFIO_RX_B3p
DIFFIO_TX_B4p
DIFFIO_RX_B5n
DIFFIO_TX_B6n
DIFFIO_RX_B5p
DIFFIO_TX_B6p
DIFFIO_RX_B7n
DIFFIO_TX_B8n
DIFFIO_RX_B7p
DIFFIO_TX_B8p
DIFFIO_TX_B9n
DIFFIO_RX_B10n
DIFFIO_TX_B9p
DIFFIO_RX_B10p
DIFFIO_RX_B11n
DIFFIO_TX_B12n
DIFFIO_RX_B11p
DIFFIO_TX_B12p
DIFFIO_TX_B13n
DIFFIO_RX_B14n
DIFFIO_TX_B13p
DIFFIO_RX_B14p
DIFFIO_RX_B15n
DIFFIO_TX_B16n
DIFFIO_RX_B15p
DIFFIO_TX_B16p
DIFFIO_TX_B17n
DIFFIO_RX_B18n
DIFFIO_TX_B17p
DIFFIO_RX_B18p
DIFFIO_RX_B19n
DIFFIO_TX_B20n
DIFFIO_RX_B19p
DIFFIO_TX_B20p
DIFFIO_TX_B21n
DIFFIO_RX_B22n
DIFFIO_TX_B21p
DIFFIO_RX_B22p
DIFFIO_RX_B23n
DIFFIO_TX_B24n
DIFFIO_RX_B23p
DIFFIO_TX_B24p
DIFFIO_TX_B25n
DIFFIO_RX_B26n
DIFFIO_TX_B25p
DIFFIO_RX_B26p
DIFFIO_RX_B27n
DIFFIO_TX_B28n
DIFFIO_RX_B27p
DIFFIO_TX_B28p
DIFFIO_TX_B29n
DIFFIO_RX_B30n
DIFFIO_TX_B29p
DIFFIO_RX_B30p
DIFFIO_RX_B31n
DIFFIO_TX_B32n
DIFFIO_RX_B31p
DIFFIO_TX_B32p
DIFFIO_TX_B33n
DIFFIO_RX_B34n
DIFFIO_TX_B33p
DIFFIO_RX_B34p
DIFFIO_RX_B35n
DIFFIO_TX_B36n
DIFFIO_RX_B35p
DIFFIO_TX_B36p
DIFFIO_TX_B37n
DIFFIO_RX_B38n
DIFFIO_TX_B37p
DIFFIO_RX_B38p
DIFFIO_RX_B39n
DIFFIO_TX_B40n
DIFFIO_RX_B39p
DIFFIO_TX_B40p
DIFFIO_TX_B41n
DIFFIO_RX_B42n
DIFFIO_TX_B41p
DIFFIO_RX_B42p
DIFFIO_RX_B43n
DIFFIO_TX_B44n
DIFFIO_RX_B43p
DIFFIO_TX_B44p
DIFFIO_TX_B45n
DIFFIO_RX_B46n
DIFFIO_TX_B45p
DIFFIO_RX_B46p
DIFFIO_RX_B47n
DIFFIO_TX_B48n
DIFFIO_RX_B47p
DIFFIO_TX_B48p
DIFFIO_TX_B49n
DIFFIO_RX_B50n
DIFFIO_TX_B49p
DIFFIO_RX_B50p
DIFFIO_RX_B51n
DIFFIO_TX_B52n
DIFFIO_RX_B51p
DIFFIO_TX_B52p
DIFFIO_TX_B53n
Emulated LVDS
Output Channel
DIFFOUT_B1n
DIFFOUT_B2n
DIFFOUT_B1p
DIFFOUT_B2p
DIFFOUT_B3n
DIFFOUT_B4n
DIFFOUT_B3p
DIFFOUT_B4p
DIFFOUT_B5n
DIFFOUT_B6n
DIFFOUT_B5p
DIFFOUT_B6p
DIFFOUT_B7n
DIFFOUT_B8n
DIFFOUT_B7p
DIFFOUT_B8p
DIFFOUT_B9n
DIFFOUT_B10n
DIFFOUT_B9p
DIFFOUT_B10p
DIFFOUT_B11n
DIFFOUT_B12n
DIFFOUT_B11p
DIFFOUT_B12p
DIFFOUT_B13n
DIFFOUT_B14n
DIFFOUT_B13p
DIFFOUT_B14p
DIFFOUT_B15n
DIFFOUT_B16n
DIFFOUT_B15p
DIFFOUT_B16p
DIFFOUT_B17n
DIFFOUT_B18n
DIFFOUT_B17p
DIFFOUT_B18p
DIFFOUT_B19n
DIFFOUT_B20n
DIFFOUT_B19p
DIFFOUT_B20p
DIFFOUT_B21n
DIFFOUT_B22n
DIFFOUT_B21p
DIFFOUT_B22p
DIFFOUT_B23n
DIFFOUT_B24n
DIFFOUT_B23p
DIFFOUT_B24p
DIFFOUT_B25n
DIFFOUT_B26n
DIFFOUT_B25p
DIFFOUT_B26p
DIFFOUT_B27n
DIFFOUT_B28n
DIFFOUT_B27p
DIFFOUT_B28p
DIFFOUT_B29n
DIFFOUT_B30n
DIFFOUT_B29p
DIFFOUT_B30p
DIFFOUT_B31n
DIFFOUT_B32n
DIFFOUT_B31p
DIFFOUT_B32p
DIFFOUT_B33n
DIFFOUT_B34n
DIFFOUT_B33p
DIFFOUT_B34p
DIFFOUT_B35n
DIFFOUT_B36n
DIFFOUT_B35p
DIFFOUT_B36p
DIFFOUT_B37n
DIFFOUT_B38n
DIFFOUT_B37p
DIFFOUT_B38p
DIFFOUT_B39n
DIFFOUT_B40n
DIFFOUT_B39p
DIFFOUT_B40p
DIFFOUT_B41n
DIFFOUT_B42n
DIFFOUT_B41p
DIFFOUT_B42p
DIFFOUT_B43n
DIFFOUT_B44n
DIFFOUT_B43p
DIFFOUT_B44p
DIFFOUT_B45n
DIFFOUT_B46n
DIFFOUT_B45p
DIFFOUT_B46p
DIFFOUT_B47n
DIFFOUT_B48n
DIFFOUT_B47p
DIFFOUT_B48p
DIFFOUT_B49n
DIFFOUT_B50n
DIFFOUT_B49p
DIFFOUT_B50p
DIFFOUT_B51n
DIFFOUT_B52n
DIFFOUT_B51p
DIFFOUT_B52p
DIFFOUT_B53n
F896
AB9
AB8
V9
AC7
AC5
AE8
U8
AE5
U7
AE6
AE12
AE9
AD11
AD9
AD10
AF10
AC9
AE11
AE7
AH4
AD7
AG3
AF5
AG8
AF4
AF9
AG7
AH2
AF8
AG1
AB12
AG6
AA12
AF6
AH5
AJ2
AG5
AJ1
AD12
AH3
AC12
AG2
AH9
AG11
AG10
AF11
AB13
AK3
AA13
AK2
AK4
AF13
AJ4
AE13
AE14
AK6
AD14
AJ5
AJ7
AG13
AJ6
AG12
AC14
AK8
AB15
AK7
AK9
AH14
AJ9
AH13
AF15
AH8
AF14
AH7
AJ10
AK11
AH10
AJ11
AA15
AK13
AA14
AK12
AJ12
AH15
AH12
AG15
Y16
AK14
W15
AJ14
AG17
AF18
AG16
AE17
W16
AF16
V16
AE16
AK16
AH20
AJ16
AG21
AB17
AH18
AA16
AH17
AH19
AK18
AG18
AJ17
W17
AK19
V17
AJ19
AJ21
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
GND
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
DQ1B
DQ1B
DQ1B
DQSn1B
DQ1B
DQS1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ2B
DQ2B
DQ2B
DQSn2B
DQ2B
DQS2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ3B
DQ3B
DQ3B
DQSn3B
DQ3B
DQS3B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ1B
DQ3B
DQ3B
DQ3B
DQ3B
DQ1B
DQ1B
DQ1B
DQ1B
DQ3B
DQ1B
DQ3B
DQ1B
DQ4B
DQ4B
DQ4B
DQSn4B
DQ4B
DQS4B
DQ1B
DQ1B
DQ1B
DQSn1B
DQ1B
DQS1B
DQ4B
DQ4B
DQ4B
DQ4B
DQ1B
DQ1B
DQ1B
DQ1B
GND
B_A_15
B_WE#
B_A_14
B_CS#_1
B_A_13
B_CS#_0
B_A_12
B_A_11
B_A_9
B_A_10
B_A_8
DQ4B
DQ1B
B_RAS#
DQ4B
DQ1B
DQ5B
DQ5B
DQ5B
DQ5B
B_CAS#
GND
B_BA_2
B_BA_0
B_BA_1
B_CK#
B_A_7
B_CK
B_A_6
B_A_3
B_A_5
B_A_2
B_A_4
B_CK#
B_CA_7
B_CK
B_CA_6
B_CA_3
B_CA_5
B_CA_2
B_CA_4
DQ5B
B_A_1
B_CA_1
DQ5B
B_A_0
B_CA_0
DQ6B
DQ6B
DQ6B
DQSn6B
DQ6B
DQS6B
DQ6B
DQ6B
DQ6B
DQ6B
B_DQ_0
B_DQ_2
B_DQ_1
B_DQS#_0
B_DQ_3
B_DQS_0
B_ODT_0
B_ODT_1
B_DQ_4
B_DQ_6
B_DQ_5
B_DQ_0
B_DQ_2
B_DQ_1
B_DQS#_0
B_DQ_3
B_DQS_0
B_ODT_0
B_ODT_1
B_DQ_4
B_DQ_6
B_DQ_5
DQ6B
B_DQ_7
B_DQ_7
DQ6B
B_DM_0
GND
B_DQ_8
B_DQ_10
B_DQ_9
B_DQS#_1
B_DQ_11
B_DQS_1
B_CKE_1
B_CKE_0
B_DM_0
GND
B_DQ_8
B_DQ_10
B_DQ_9
B_DQS#_1
B_DQ_11
B_DQS_1
B_CKE_1
B_CKE_0
DQ5B
DQ5B
DQ5B
DQSn5B
DQ5B
DQS5B
DQ7B
DQ7B
DQ7B
DQSn7B
DQ7B
DQS7B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ2B
DQ7B
DQ2B
Pin List F31
B_CS#_1
B_CS#_0
B_CA_9
B_CA_8
GND
Page 7 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
4A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
5B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
VREF
PinName/Function (2)
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB4AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5AN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB5BN0
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI13
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
CLK3n
CLK3p
RZQ_1
INIT_DONE
PR_REQUEST
CRC_ERROR
nCEO
CvP_CONFDONE
DEV_OE
DEV_CLRn
CLK5p
FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTp,FPLL_BR_FB
CLK5n
FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTn
CLK4p,FPLL_BR_FBp
CLK4n,FPLL_BR_FBn
RZQ_2
Dedicated Tx/Rx
Channel
DIFFIO_RX_B54n
DIFFIO_TX_B53p
DIFFIO_RX_B54p
DIFFIO_RX_B55n
DIFFIO_TX_B56n
DIFFIO_RX_B55p
DIFFIO_TX_B56p
DIFFIO_TX_B57n
DIFFIO_RX_B58n
DIFFIO_TX_B57p
DIFFIO_RX_B58p
DIFFIO_RX_B59n
DIFFIO_TX_B60n
DIFFIO_RX_B59p
DIFFIO_TX_B60p
DIFFIO_TX_B61n
DIFFIO_RX_B62n
DIFFIO_TX_B61p
DIFFIO_RX_B62p
DIFFIO_RX_B63n
DIFFIO_TX_B64n
DIFFIO_RX_B63p
DIFFIO_TX_B64p
DIFFIO_TX_B65n
DIFFIO_RX_B66n
DIFFIO_TX_B65p
DIFFIO_RX_B66p
DIFFIO_RX_B67n
DIFFIO_TX_B68n
DIFFIO_RX_B67p
DIFFIO_TX_B68p
DIFFIO_TX_B69n
DIFFIO_RX_B70n
DIFFIO_TX_B69p
DIFFIO_RX_B70p
DIFFIO_RX_B71n
DIFFIO_TX_B72n
DIFFIO_RX_B71p
DIFFIO_TX_B72p
DIFFIO_TX_B73n
DIFFIO_RX_B74n
DIFFIO_TX_B73p
DIFFIO_RX_B74p
DIFFIO_RX_B75n
DIFFIO_TX_B76n
DIFFIO_RX_B75p
DIFFIO_TX_B76p
DIFFIO_TX_B77n
DIFFIO_RX_B78n
DIFFIO_TX_B77p
DIFFIO_RX_B78p
DIFFIO_RX_B79n
DIFFIO_TX_B80n
DIFFIO_RX_B79p
DIFFIO_TX_B80p
DIFFIO_TX_R1p
DIFFIO_RX_R2p
DIFFIO_TX_R1n
DIFFIO_RX_R2n
DIFFIO_TX_R3p
DIFFIO_RX_R4p
DIFFIO_TX_R3n
DIFFIO_RX_R4n
DIFFIO_TX_R5p
DIFFIO_RX_R6p
DIFFIO_TX_R5n
DIFFIO_RX_R6n
DIFFIO_TX_R7p
DIFFIO_RX_R8p
DIFFIO_TX_R7n
DIFFIO_RX_R8n
DIFFIO_RX_R9p
DIFFIO_TX_R10p
DIFFIO_RX_R9n
DIFFIO_TX_R10n
DIFFIO_RX_R11p
DIFFIO_TX_R12p
DIFFIO_RX_R11n
DIFFIO_TX_R12n
DIFFIO_RX_R13p
DIFFIO_TX_R14p
DIFFIO_RX_R13n
DIFFIO_TX_R14n
DIFFIO_RX_R15p
DIFFIO_TX_R16p
DIFFIO_RX_R15n
DIFFIO_TX_R16n
DIFFIO_RX_R17p
DIFFIO_TX_R18p
DIFFIO_RX_R17n
DIFFIO_TX_R18n
DIFFIO_RX_R19p
DIFFIO_TX_R20p
DIFFIO_RX_R19n
DIFFIO_TX_R20n
DIFFIO_RX_R21p
DIFFIO_TX_R22p
DIFFIO_RX_R21n
DIFFIO_TX_R22n
DIFFIO_RX_R23p
DIFFIO_TX_R24p
DIFFIO_RX_R23n
DIFFIO_TX_R24n
Emulated LVDS
Output Channel
DIFFOUT_B54n
DIFFOUT_B53p
DIFFOUT_B54p
DIFFOUT_B55n
DIFFOUT_B56n
DIFFOUT_B55p
DIFFOUT_B56p
DIFFOUT_B57n
DIFFOUT_B58n
DIFFOUT_B57p
DIFFOUT_B58p
DIFFOUT_B59n
DIFFOUT_B60n
DIFFOUT_B59p
DIFFOUT_B60p
DIFFOUT_B61n
DIFFOUT_B62n
DIFFOUT_B61p
DIFFOUT_B62p
DIFFOUT_B63n
DIFFOUT_B64n
DIFFOUT_B63p
DIFFOUT_B64p
DIFFOUT_B65n
DIFFOUT_B66n
DIFFOUT_B65p
DIFFOUT_B66p
DIFFOUT_B67n
DIFFOUT_B68n
DIFFOUT_B67p
DIFFOUT_B68p
DIFFOUT_B69n
DIFFOUT_B70n
DIFFOUT_B69p
DIFFOUT_B70p
DIFFOUT_B71n
DIFFOUT_B72n
DIFFOUT_B71p
DIFFOUT_B72p
DIFFOUT_B73n
DIFFOUT_B74n
DIFFOUT_B73p
DIFFOUT_B74p
DIFFOUT_B75n
DIFFOUT_B76n
DIFFOUT_B75p
DIFFOUT_B76p
DIFFOUT_B77n
DIFFOUT_B78n
DIFFOUT_B77p
DIFFOUT_B78p
DIFFOUT_B79n
DIFFOUT_B80n
DIFFOUT_B79p
DIFFOUT_B80p
DIFFOUT_R1p
DIFFOUT_R2p
DIFFOUT_R1n
DIFFOUT_R2n
DIFFOUT_R3p
DIFFOUT_R4p
DIFFOUT_R3n
DIFFOUT_R4n
DIFFOUT_R5p
DIFFOUT_R6p
DIFFOUT_R5n
DIFFOUT_R6n
DIFFOUT_R7p
DIFFOUT_R8p
DIFFOUT_R7n
DIFFOUT_R8n
DIFFOUT_R9p
DIFFOUT_R10p
DIFFOUT_R9n
DIFFOUT_R10n
DIFFOUT_R11p
DIFFOUT_R12p
DIFFOUT_R11n
DIFFOUT_R12n
DIFFOUT_R13p
DIFFOUT_R14p
DIFFOUT_R13n
DIFFOUT_R14n
DIFFOUT_R15p
DIFFOUT_R16p
DIFFOUT_R15n
DIFFOUT_R16n
DIFFOUT_R17p
DIFFOUT_R18p
DIFFOUT_R17n
DIFFOUT_R18n
DIFFOUT_R19p
DIFFOUT_R20p
DIFFOUT_R19n
DIFFOUT_R20n
DIFFOUT_R21p
DIFFOUT_R22p
DIFFOUT_R21n
DIFFOUT_R22n
DIFFOUT_R23p
DIFFOUT_R24p
DIFFOUT_R23n
DIFFOUT_R24n
F896
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
AG20
AJ20
AF19
AD17
AH24
AC18
AG23
AH22
AE19
AG22
AE18
AA18
AK22
Y17
AK21
AJ22
AF21
AH23
AF20
AA19
AK24
Y18
AK23
AJ25
AF24
AJ24
AF23
AD19
AK26
AC20
AJ26
AH25
AE23
AG25
AE22
W19
AK27
V18
AJ27
AK29
AD21
AK28
AD20
AA20
AH27
Y19
AG26
AF26
AC23
AF25
AC22
AB21
AE24
AA21
AD24
AG27
AD25
AH28
AC25
AJ29
W20
AH29
Y21
AE26
W21
AD27
W22
AA25
AB22
AB26
AB23
AA24
AE27
AB25
AE28
Y23
AG28
Y24
AF28
V23
AF29
W24
AF30
AD26
AH30
AC27
AG30
W25
AC28
V25
AC29
AB30
AB28
AA30
AA28
AA26
AE29
AB27
AD29
Y26
AD30
Y27
AC30
W27
Y29
U25
V27
T25
T24
Y28
T23
V28
R24
U27
W26
DQ7B
DQ7B
DQ7B
DQ2B
DQ2B
DQ2B
B_DQ_12
B_DQ_14
B_DQ_13
HMC Pin Assignment for
LPDDR2
B_DQ_12
B_DQ_14
B_DQ_13
DQ7B
DQ2B
B_DQ_15
B_DQ_15
DQ7B
DQ2B
DQ8B
DQ8B
DQ8B
DQSn8B
DQ8B
DQS8B
DQ2B
DQ2B
DQ2B
DQSn2B
DQ2B
DQS2B
DQ8B
DQ8B
DQ8B
DQ8B
DQ2B
DQ2B
DQ2B
DQ2B
DQ8B
DQ2B
DQ8B
DQ2B
DQ9B
DQ9B
DQ9B
DQSn9B
DQ9B
DQS9B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ3B
DQ9B
DQ9B
DQ9B
DQ9B
DQ3B
DQ3B
DQ3B
DQ3B
DQ9B
DQ3B
DQ9B
DQ3B
DQ10B
DQ10B
DQ10B
DQSn10B
DQ10B
DQS10B
DQ3B
DQ3B
DQ3B
DQSn3B
DQ3B
DQS3B
DQ10B
DQ10B
DQ10B
DQ10B
DQ3B
DQ3B
DQ3B
DQ3B
DQ10B
DQ3B
DQ10B
DQ1R
DQ3B
B_DM_1
GND
B_DQ_16
B_DQ_18
B_DQ_17
B_DQS#_2
B_DQ_19
B_DQS_2
B_RESET#
GND
B_DQ_20
B_DQ_22
B_DQ_21
GND
B_DQ_23
GND
B_DM_2
GND
B_DQ_24
B_DQ_26
B_DQ_25
B_DQS#_3
B_DQ_27
B_DQS_3
GND
GND
B_DQ_28
B_DQ_30
B_DQ_29
GND
B_DQ_31
GND
B_DM_3
GND
B_DQ_32
B_DQ_34
B_DQ_33
B_DQS#_4
B_DQ_35
B_DQS_4
GND
GND
B_DQ_36
B_DQ_38
B_DQ_37
GND
B_DQ_39
GND
B_DM_4
B_DM_1
GND
B_DQ_16
B_DQ_18
B_DQ_17
B_DQS#_2
B_DQ_19
B_DQS_2
B_RESET#
GND
B_DQ_20
B_DQ_22
B_DQ_21
GND
B_DQ_23
GND
B_DM_2
GND
B_DQ_24
B_DQ_26
B_DQ_25
B_DQS#_3
B_DQ_27
B_DQS_3
GND
GND
B_DQ_28
B_DQ_30
B_DQ_29
GND
B_DQ_31
GND
B_DM_3
GND
B_DQ_32
B_DQ_34
B_DQ_33
B_DQS#_4
B_DQ_35
B_DQS_4
GND
GND
B_DQ_36
B_DQ_38
B_DQ_37
GND
B_DQ_39
GND
B_DM_4
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DM_4
HPS_DQ_39
HPS_DQ_37
HPS_DQ_38
HPS_DQ_36
HPS_DQS_4
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS_DQS#_4
HPS_DQ_35
HPS_DQ_33
HPS_DQ_34
HPS_DQ_32
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
DQ1R
DQ1R
DQ1R
DQ1R
DQ1R
DQS1R
DQ1R
DQSn1R
DQ1R
DQ1R
DQ1R
DQ2R
DQ2R
DQ2R
DQ2R
DQ2R
DQ2R
DQS2R
DQSn2R
DQ2R
DQ2R
DQ2R
DQ2R
DQ3R
DQ3R
DQ3R
DQ3R
DQ3R
DQ3R
DQS3R
DQSn3R
DQ3R
DQ3R
DQ3R
DQ3R
Pin List F31
Page 8 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6B
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
VREF
PinName/Function (2)
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6BN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
VREFB6AN0_HPS
HPS_GPI12
HPS_GPI11
HPS_DDR
HPS_GPI10
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6BN0_HPS
HPS_DDR
HPS_GPI9
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI8
HPS_GPI7
HPS_DDR
HPS_GPI6
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI5
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI4
HPS_GPI3
HPS_DDR
HPS_GPI2
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_GPI1
HPS_GPI0
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
VREFB6AN0_HPS
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_DDR
HPS_RZQ_0
GND
GND
HPS_nRST
HPS_nPOR
HPS_TDO
VCCRSTCLK_HPS
HPS_TMS
HPS_TCK
HPS_TRST
HPS_TDI
GND
HPS_PORSEL
HPS_CLK1
HPS_CLK2
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F896
DQS for X8
V29
U20
W30
T21
W29
R26
V30
R27
U30
R22
U28
R21
T28
P25
T29
P24
T30
V20
R28
P22
R29
P27
N27
P26
P29
R19
P30
R18
N28
T26
N29
U26
N30
M22
M28
N23
M30
M27
L28
M26
L29
N25
L30
N24
K27
L26
K29
K26
J26
M25
K28
J29
L24
J30
L25
H29
N18
H28
M19
G28
K22
H30
K23
G27
F26
G30
J25
F28
J27
F30
M23
F29
L23
E28
J24
E29
J23
E27
D30
H27
D29
G26
C30
H24
B30
K21
C29
H25
C28
G25
D27
J22
D26
C27
F23
B28
G23
A29
H22
A28
B27
A26
F24
D25
F25
B26
B25
C25
A25
H23
A24
G21
C24
E23
A23
Pin List F31
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS_DM_3
HPS_DM_3
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQ_31
HPS_DQ_29
HPS_DQ_30
HPS_DQ_28
HPS_DQS_3
HPS_DQS_3
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DQS#_3
HPS_DQ_27
HPS_DQ_25
HPS_DQ_26
HPS_DQ_24
HPS_DM_2
HPS_DM_2
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQ_23
HPS_DQ_21
HPS_DQ_22
HPS_DQ_20
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DQS_2
HPS_RESET#
HPS_DQS#_2
HPS_DQ_19
HPS_DQ_17
HPS_DQ_18
HPS_DQ_16
HPS_DM_1
HPS_DM_1
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DQ_15
HPS_DQ_13
HPS_DQ_14
HPS_DQ_12
HPS_CKE_0
HPS_DQS_1
HPS_CKE_1
HPS_DQS#_1
HPS_DQ_11
HPS_DQ_9
HPS_DQ_10
HPS_DQ_8
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_DM_0
HPS_DQ_7
HPS_DQ_5
HPS_DQ_6
HPS_DQ_4
HPS_ODT_1
HPS_DQS_0
HPS_ODT_0
HPS_DQS#_0
HPS_DQ_3
HPS_DQ_1
HPS_DQ_2
HPS_DQ_0
HPS_A_0
HPS_A_1
HPS_A_4
HPS_A_2
HPS_A_5
HPS_A_3
HPS_CK
HPS_A_6
HPS_CK#
HPS_A_7
HPS_BA_1
HPS_BA_0
HPS_BA_2
HPS_CAS#
HPS_RAS#
HPS_A_8
HPS_A_10
HPS_A_9
HPS_A_11
HPS_CS#_0
HPS_A_12
HPS_CS#_1
HPS_A_13
HPS_A_14
HPS_WE#
HPS_A_15
HPS_CA_0
HPS_CA_1
HPS_CA_4
HPS_CA_2
HPS_CA_5
HPS_CA_3
HPS_CK
HPS_CA_6
HPS_CK#
HPS_CA_7
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
TRACE_CLK
TRACE_D0
TRACE_D1
TRACE_D2
TRACE_D3
TRACE_D4
TRACE_D5
TRACE_D6
TRACE_D7
SPIM0_CLK
SPIS0_CLK
SPIS0_MOSI
SPIS0_MISO
SPIS0_SS0
SPIS1_CLK
SPIS1_MOSI
SPIS1_SS0
SPIS1_MISO
I2C1_SDA
UART0_RX
UART0_TX
I2C1_SDA
I2C1_SCL
CAN1_RX
CAN1_TX
I2C0_SDA
I2C0_SCL
UART0_CTS
HPS_GPIO48
HPS_GPIO49
HPS_GPIO50
HPS_GPIO51
HPS_GPIO52
HPS_GPIO53
HPS_GPIO54
HPS_GPIO55
HPS_GPIO56
HPS_GPIO57
HPS_CA_8
HPS_CA_9
HPS_CS#_0
HPS_CS#_1
Page 9 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
7A
7A
7A
7A
7A
7A
7A
7A
7A
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7C
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
7D
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
VREF
PinName/Function (2)
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB7A7B7C7DN0_HPS
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0,BOOTSEL0
UART0_RX
UART0_TX,CLKSEL1
I2C0_SDA
I2C0_SCL
CAN0_RX
CAN0_TX,CLKSEL0
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE,BOOTSEL2
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0,BOOTSEL1
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
CLK7p
CLK7n
FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTp,FPLL_TL_FB
FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTn
CLK6p,FPLL_TL_FBp
CLK6n,FPLL_TL_FBn
Configuration
Function
Dedicated Tx/Rx
Channel
DIFFIO_RX_T1p
DIFFIO_TX_T2p
DIFFIO_RX_T1n
DIFFIO_TX_T2n
DIFFIO_RX_T3p
DIFFIO_TX_T4p
DIFFIO_RX_T3n
DIFFIO_TX_T4n
DIFFIO_RX_T5p
DIFFIO_TX_T6p
DIFFIO_RX_T5n
DIFFIO_TX_T6n
DIFFIO_RX_T7p
DIFFIO_TX_T8p
DIFFIO_RX_T7n
DIFFIO_TX_T8n
DIFFIO_RX_T9p
DIFFIO_TX_T10p
DIFFIO_RX_T9n
DIFFIO_TX_T10n
DIFFIO_RX_T11p
DIFFIO_TX_T12p
DIFFIO_RX_T11n
DIFFIO_TX_T12n
DIFFIO_RX_T13p
DIFFIO_TX_T14p
DIFFIO_RX_T13n
DIFFIO_TX_T14n
DIFFIO_RX_T15p
DIFFIO_TX_T16p
DIFFIO_RX_T15n
DIFFIO_TX_T16n
DIFFIO_RX_T17p
DIFFIO_TX_T18p
DIFFIO_RX_T17n
DIFFIO_TX_T18n
DIFFIO_RX_T19p
DIFFIO_TX_T20p
DIFFIO_RX_T19n
DIFFIO_TX_T20n
DIFFIO_RX_T21p
DIFFIO_TX_T22p
DIFFIO_RX_T21n
DIFFIO_TX_T22n
DIFFIO_RX_T23p
DIFFIO_TX_T24p
DIFFIO_RX_T23n
DIFFIO_TX_T24n
DIFFIO_RX_T25p
DIFFIO_TX_T26p
DIFFIO_RX_T25n
DIFFIO_TX_T26n
DIFFIO_RX_T27p
DIFFIO_TX_T28p
DIFFIO_RX_T27n
DIFFIO_TX_T28n
DIFFIO_RX_T29p
DIFFIO_TX_T30p
Emulated LVDS
Output Channel
DIFFOUT_T1p
DIFFOUT_T2p
DIFFOUT_T1n
DIFFOUT_T2n
DIFFOUT_T3p
DIFFOUT_T4p
DIFFOUT_T3n
DIFFOUT_T4n
DIFFOUT_T5p
DIFFOUT_T6p
DIFFOUT_T5n
DIFFOUT_T6n
DIFFOUT_T7p
DIFFOUT_T8p
DIFFOUT_T7n
DIFFOUT_T8n
DIFFOUT_T9p
DIFFOUT_T10p
DIFFOUT_T9n
DIFFOUT_T10n
DIFFOUT_T11p
DIFFOUT_T12p
DIFFOUT_T11n
DIFFOUT_T12n
DIFFOUT_T13p
DIFFOUT_T14p
DIFFOUT_T13n
DIFFOUT_T14n
DIFFOUT_T15p
DIFFOUT_T16p
DIFFOUT_T15n
DIFFOUT_T16n
DIFFOUT_T17p
DIFFOUT_T18p
DIFFOUT_T17n
DIFFOUT_T18n
DIFFOUT_T19p
DIFFOUT_T20p
DIFFOUT_T19n
DIFFOUT_T20n
DIFFOUT_T21p
DIFFOUT_T22p
DIFFOUT_T21n
DIFFOUT_T22n
DIFFOUT_T23p
DIFFOUT_T24p
DIFFOUT_T23n
DIFFOUT_T24n
DIFFOUT_T25p
DIFFOUT_T26p
DIFFOUT_T25n
DIFFOUT_T26n
DIFFOUT_T27p
DIFFOUT_T28p
DIFFOUT_T27n
DIFFOUT_T28n
DIFFOUT_T29p
DIFFOUT_T30p
F896
C22
B23
H20
B22
G22
C23
D22
E24
D24
H19
F20
J19
F21
F19
A21
E21
B21
K17
A20
G20
B20
B18
D21
D20
C20
H18
A19
E19
A18
D19
C19
F18
B17
G18
C17
H17
C18
G17
E18
E17
A16
D17
B16
F16
E16
G16
D16
D14
A15
C14
D15
M17
B15
N16
C15
E14
A14
H15
B13
G15
A13
C13
A11
B12
A10
F15
C12
F14
B11
D11
A9
D10
A8
K14
C7
J14
B7
E9
C8
D9
B8
H14
C10
G13
C9
F13
A6
E13
A5
H8
A4
G8
A3
E12
D6
D12
C5
H13
D5
H12
C4
F11
E8
E11
D7
J7
B2
H7
B1
B6
C3
B5
B3
K12
D2
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
SPIM0_MOSI
SPIM0_MISO
SPIM0_SS0
UART0_RX
UART0_TX
I2C0_SDA
I2C0_SCL
CAN0_RX
CAN0_TX
NAND_ALE
NAND_CE
NAND_CLE
NAND_RE
NAND_RB
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_WP
NAND_WE
QSPI_IO0
QSPI_IO1
QSPI_IO2
QSPI_IO3
QSPI_SS0
QSPI_CLK
QSPI_SS1
SDMMC_CMD
SDMMC_PWREN
SDMMC_D0
SDMMC_D1
SDMMC_D4
SDMMC_D5
SDMMC_D6
SDMMC_D7
SDMMC_FB_CLK_IN
SDMMC_CCLK_OUT
SDMMC_D2
SDMMC_D3
RGMII0_TX_CLK
RGMII0_TXD0
RGMII0_TXD1
RGMII0_TXD2
RGMII0_TXD3
RGMII0_RXD0
RGMII0_MDIO
RGMII0_MDC
RGMII0_RX_CTL
RGMII0_TX_CTL
RGMII0_RX_CLK
RGMII0_RXD1
RGMII0_RXD2
RGMII0_RXD3
I2C1_SCL
CAN1_RX
CAN1_TX
CAN0_RX
CAN0_TX
UART1_RX
UART1_TX
UART0_RX
UART0_TX
RGMII1_TX_CLK
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TXD2
RGMII1_TXD3
RGMII1_RXD0
RGMII1_MDIO
RGMII1_MDC
RGMII1_RX_CTL
RGMII1_TX_CTL
RGMII1_RX_CLK
RGMII1_RXD1
RGMII1_RXD2
RGMII1_RXD3
QSPI_SS1
UART0_RTS
UART1_CTS
UART1_RTS
SPIM0_SS1
SPIM1_SS1
SPIM1_CLK
SPIM1_MOSI
SPIM1_MISO
SPIM1_SS0
QSPI_SS3
USB1_D0
USB1_D1
USB1_D2
USB1_D3
HPS_GPIO58
HPS_GPIO59
HPS_GPIO60
HPS_GPIO61
HPS_GPIO62
HPS_GPIO63
HPS_GPIO64
HPS_GPIO65
HPS_GPIO66
HPS_GPIO14
HPS_GPIO15
HPS_GPIO16
HPS_GPIO17
HPS_GPIO18
HPS_GPIO19
HPS_GPIO20
HPS_GPIO21
HPS_GPIO22
HPS_GPIO23
HPS_GPIO24
HPS_GPIO25
HPS_GPIO26
HPS_GPIO27
HPS_GPIO28
HPS_GPIO29
HPS_GPIO30
HPS_GPIO31
HPS_GPIO32
HPS_GPIO33
HPS_GPIO34
HPS_GPIO35
HPS_GPIO36
HPS_GPIO37
HPS_GPIO38
HPS_GPIO39
HPS_GPIO40
HPS_GPIO41
HPS_GPIO42
HPS_GPIO43
HPS_GPIO44
HPS_GPIO45
HPS_GPIO46
HPS_GPIO47
HPS_GPIO0
HPS_GPIO1
HPS_GPIO2
HPS_GPIO3
HPS_GPIO4
HPS_GPIO5
HPS_GPIO6
HPS_GPIO7
HPS_GPIO8
HPS_GPIO9
HPS_GPIO10
HPS_GPIO11
HPS_GPIO12
HPS_GPIO13
I2C3_SDA
I2C3_SCL
USB1_D4
USB1_D5
USB1_D6
USB1_D7
QSPI_SS2
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
USB0_D0
USB0_D1
USB0_D2
USB0_D3
USB0_D4
USB0_D5
USB0_D6
USB0_D7
USB0_CLK
USB0_STP
USB0_DIR
USB0_NXT
USB1_D0
USB1_D1
USB1_D2
USB1_D3
USB1_D4
USB1_D5
USB1_D6
USB1_D7
USB1_CLK
USB1_STP
USB1_DIR
USB1_NXT
I2C2_SDA
I2C2_SCL
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQS1T
DQSn1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ2T
DQ1T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQS2T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQS1T
DQSn2T
DQ2T
DQ2T
DQ2T
DQ2T
DQSn1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ3T
DQ1T
DQ3T
DQ3T
DQ3T
DQ3T
DQ3T
DQS3T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQSn3T
DQ3T
DQ3T
DQ3T
DQ3T
DQ1T
DQ1T
DQ1T
DQ1T
DQ1T
DQ4T
DQ2T
DQ4T
DQ4T
DQ4T
DQ4T
DQ4T
DQS4T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQS2T
Pin List F31
Page 10 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
8A
9A
9A
9A
9A
9A
9A
9A
9A
9A
VREF
PinName/Function (2)
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
VREFB8AN0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MSEL0
CONF_DONE
MSEL1
nSTATUS
nCE
MSEL2
MSEL3
nCONFIG
MSEL4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Optional Function(s)
Configuration
Function
MSEL0
CONF_DONE
MSEL1
nSTATUS
nCE
MSEL2
MSEL3
nCONFIG
MSEL4
Dedicated Tx/Rx
Channel
DIFFIO_RX_T29n
DIFFIO_TX_T30n
DIFFIO_RX_T31p
DIFFIO_TX_T32p
DIFFIO_RX_T31n
DIFFIO_TX_T32n
DIFFIO_RX_T33p
DIFFIO_TX_T34p
DIFFIO_RX_T33n
DIFFIO_TX_T34n
DIFFIO_RX_T35p
DIFFIO_TX_T36p
DIFFIO_RX_T35n
DIFFIO_TX_T36n
DIFFIO_RX_T37p
DIFFIO_TX_T38p
DIFFIO_RX_T37n
DIFFIO_TX_T38n
DIFFIO_RX_T39p
DIFFIO_TX_T40p
DIFFIO_RX_T39n
DIFFIO_TX_T40n
Emulated LVDS
Output Channel
DIFFOUT_T29n
DIFFOUT_T30n
DIFFOUT_T31p
DIFFOUT_T32p
DIFFOUT_T31n
DIFFOUT_T32n
DIFFOUT_T33p
DIFFOUT_T34p
DIFFOUT_T33n
DIFFOUT_T34n
DIFFOUT_T35p
DIFFOUT_T36p
DIFFOUT_T35n
DIFFOUT_T36n
DIFFOUT_T37p
DIFFOUT_T38p
DIFFOUT_T37n
DIFFOUT_T38n
DIFFOUT_T39p
DIFFOUT_T40p
DIFFOUT_T39n
DIFFOUT_T40n
F896
DQS for X8
DQS for X16
J12
C2
G12
E4
G11
D4
K7
E3
K8
E2
G10
E1
F10
D1
J10
E7
J9
E6
F9
G7
F8
F6
L8
F3
K6
F4
G5
G6
L7
J5
L9
J6
J2
J1
L2
L1
N2
N1
P9
P8
T8
T9
R2
R1
U2
U1
W2
W1
AA2
AA1
AC2
AC1
AE2
AE1
W8
W7
A12
A17
A2
A22
A27
AA11
AA22
AA3
AA4
AA6
AA9
AB1
AB19
AB2
AB29
AB5
AB7
AC16
AC26
AC3
AC4
AC6
AC8
AD1
AD2
AD23
AD5
AE10
AE20
AE3
AE4
AF1
AF12
AF17
AF2
AF27
AF3
AG14
AG24
AG9
AH1
AH11
AH21
AH6
AJ18
AJ28
AJ3
AJ30
AK15
AK25
AK5
B14
B19
B24
B29
B9
C1
C16
C21
DQSn4T
DQ4T
DQ4T
DQ4T
DQ4T
DQSn2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ5T
DQ2T
DQ5T
DQ5T
DQ5T
DQ5T
DQ5T
DQS5T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
DQSn5T
DQ5T
DQ5T
DQ5T
DQ5T
DQ2T
DQ2T
DQ2T
DQ2T
DQ2T
Pin List F31
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
Page 11 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
VREF
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
PinName/Function (2)
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F896
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C26
C6
D13
D23
D3
E10
E25
E30
F17
F2
F27
F5
F7
G24
G3
G4
H1
H11
H2
H5
J18
J28
J3
J4
J8
K1
K10
K15
K2
K20
K25
K5
L11
L13
L15
L17
L19
L22
L3
L4
L6
M1
M10
M12
M14
M16
M18
M2
M20
M29
M5
M7
M8
N11
N13
N15
N17
N19
N26
N3
N4
N6
N8
N9
P1
P10
P12
P14
P16
P18
P2
P20
P5
P7
R11
R13
R15
R17
R3
R30
R4
R6
R8
R9
T1
T10
T12
T14
T15
T16
T2
T20
T27
T5
T7
U11
U13
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U15
U17
U24
U29
U3
U4
U6
U9
V1
V10
V12
V14
V19
V2
V21
V5
V7
W11
DQS for X8
Pin List F31
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
Page 12 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
VREF
PinName/Function (2)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
VCCPGM
VCCPGM
VCCPGM
VCCBAT
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5A
VCCIO5B
VCCIO5B
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
VCCIO6A
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
HPS
HPS
HPS
HPS
HPS
Optional Function(s)
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F896
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
W13
W18
W28
W3
W4
W6
W9
Y1
Y10
Y12
Y14
Y15
Y2
Y20
Y25
Y30
Y5
Y7
Y8
U22
T18
M11
M13
M9
N10
N12
N14
P11
P13
R10
R12
R14
T11
T13
U10
U12
U14
V11
V13
V15
W10
W12
W14
Y11
Y13
Y9
L5
R5
W5
AA5
M6
N5
T6
U5
Y6
U21
F1
G2
H3
H4
K3
K4
M3
M4
P3
P4
T3
T4
V3
V4
Y3
Y4
AB3
AB4
AD3
AD4
AA7
AD15
E26
J15
AB10
AA23
J11
H9
AC11
AD8
AF7
AG4
AB14
AD13
AE15
AJ13
AJ8
AK10
AA17
AC21
AD18
AE25
AF22
AG19
AH16
AH26
AJ23
AK20
AB24
AD28
AG29
W23
AA27
AE30
D28
G29
H26
K24
K30
Pin List F31
Page 13 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Note (1)
Bank
Number
3A
3B
4A
5A
5B
8A
VREF
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB5AN0
VREFB5BN0
VREFB7A7B7C7DN0 HPS
VREFB8AN0
PinName/Function (2)
Optional Function(s)
VCCIO6A HPS
VCCIO6A HPS
VCCIO6A HPS
VCCIO6B HPS
VCCIO6B HPS
VCCIO6B HPS
VCCIO6B HPS
VCCIO6B HPS
VCCIO6B HPS
VCCIO7A HPS
VCCIO7A HPS
VCCIO7B HPS
VCCIO7B HPS
VCCIO7C HPS
VCCIO7D HPS
VCCIO7D HPS
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCPD3A
VCCPD3A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD3B4A
VCCPD5A
VCCPD5A
VCCPD5B
VCCPD6A6B HPS
VCCPD6A6B HPS
VCCPD6A6B HPS
VCCPD6A6B HPS
VCCPD6A6B HPS
VCCPD7A HPS
VCCPD7B HPS
VCCPD7C HPS
VCCPD7D HPS
VCCPD8A
VCCPD8A
VCCPD8A
VCCPD8A
VCCPD8A
VREFB3AN0
VREFB3BN0
VREFB4AN0
VREFB5AN0
VREFB5BN0
VREFB7A7B7C7DN0 HPS
VREFB8AN0
VCCRSTCLK HPS
RREF TL
VCCA FPLL
VCCA FPLL
VCCA FPLL
VCCA FPLL
VCCA FPLL
VCCA FPLL
VCCA FPLL
VCCA FPLL
VCCA FPLL
VCC AUX
VCC AUX
VCC AUX
VCC AUX
VCC AUX
VCC AUX SHARED
VCCPLL HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
VCC HPS
Configuration
Function
Dedicated Tx/Rx
Channel
Emulated LVDS
Output Channel
F896
DQS for X8
DQS for X16
HMC Pin Assignment for DDR3
HMC Pin Assignment for
LPDDR2
HPS Pin Mux Select 3
HPS Pin Mux Select 2
HPS Pin Mux Select 1
HPS Pin Mux Select 0
L27
M24
N21
P23
P28
R25
T22
U19
V26
F22
H21
E20
G19
D18
E15
H16
A7
B4
C11
D8
E5
F12
G14
G9
H6
J13
AA10
AC10
AB18
AB20
AC13
AC15
AC17
AC19
AD16
AE21
V22
V24
U23
M21
N22
P21
R20
R23
K19
K18
J17
K16
K11
K13
L10
L12
L14
AD6
AJ15
AK17
AC24
AA29
E22
B10
J20
G1
N7
R7
V8
AA8
K9
Y22
AB6
P6
V6
AB11
AB16
AD22
H10
J16
J21
L21
U18
L16
L18
L20
M15
N20
P15
P17
P19
R16
T17
T19
U16
Notes:
(1) For more information about pin definitions and pin connection guidelines, refer to the
Cyclone V Device Family Pin Connection Guidelines.
(2) HPS_DDR pins are for memory interface only. For the dedicated pin function corresponding with the respective memory interfaces, refer to the HMC columns.
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Pin List F31
Page 14 of 15
Pin Information for the Cyclone® V 5CSEMA6 Device
Version 1.2
Version Number
1.0
1.1
1.2
PT-5CSEMA6-1.2
Copyright © 2013 Altera Corp.
Date
10/18/2012
1/17/2013
3/25/2013
Changes Made
Initial release.
A pin that was marked as VCC_HPS has been corrected to VCCRSTCLK_HPS
Updated the following pin names:
- Changed SDMMC_CLK_IN to SDMMC_FB_CLK_IN
- Changed SDMMC_CLK to SDMMC_CCLK_OUT
Revision History
Page 15 of 15
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