F45P1_PDP4ProgMan_Sep62

F45P1_PDP4ProgMan_Sep62

F-4~ P'

PROGRAMMED DATA

PRO

GRAMMING

MANUAL

DIGITAL EQUIPMENT CORPORATION. MAYNARD,

MA~ SACHUS ET T 5

PD P-4

PROGRAMMING MANUAL

F-45Pl

DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS

TABLE OF CONTENTS

CHAPTER 1

SYSTEM DESCRIPTION

Summary . . . . . . .

System Descri pt ion. . . . . . . . . . . .

Arithmetic and Control Element. . . . . .

Interface . . . . . . .

Input-Output Devices . .

CHAPTER 2

ARITHMETIC AND CONTROL ELEMENT

Functions . . . . . . . .

Interna I Processor . .

Control States . . .

Instruction Operation. . . . .

Memory Reference Instructions and Auto Index ing

Augmented Instructions . . . . . . . . . . . . . .

Input-Output Commands.

Device Selector . . . .

Information Collector . .

Information Distributor . .

Input-Output Skip Faci I ity

Program Interrupt Control.

Clock/Timer . . . . . . .

CHAPTER 3

INPUT-OUTPUT EQUIPMENT

FUNCTIONS AND PROGRAMMING

III

9

9

15

16

16

20

3

3

6

30

30

30

31

27

27

29

Input-Output Devices . . . . . . .

Visual CRT Display, Type 30A .

Light Pen, Type 32 . . . . . . . .

Visual CRT Display, Type 30D and Light Pen, Type 30D.

Analog-to-Digital Converter {Typical Input Device} . .

Low Speed Analog-to-Digital Converter . .

Perforated-Tape Reader and Control . .

Printer-Keyboard and Control, Type 65

Perforated-Tape Punch and Control, Type 75.

Card Reader and Control, Type

40-200-4 . .

Card Punch, Type

41-523-4

Line Printer, Type

62 . . . . .

CHAPTER 4.

THE INTERFACE ELECTRICAL CHARACTERISTICS

Real-Time Option . . . .

The Device Selector

Information Collector . .

Information Distributor . .

Input-Output Skip Foci

I ity .

Program Interrupt Control . .

Data Interrupt Control . .

Appendix

Appendix

2

Appendix 3

Appendix

4

Appendix 5

Appendix

6

Appendix 7

Memory Reference Instructions

Operate Instructions . . . .

Basic lOT Instruction Group

Codes . . . . . . . . . . .

Read-In Mode Sequence

Assemb

I er Program .

Multiply Subroutine. iv

A-I

A-2

A-3

A-6

A-10

A-13

A-18

63

63

65

66

66

68

68

33

33

35

35

53

56

61

36

39

39

43

50

Appendix 8

Appendix 9

Appendix 10

Divide Subroutine . . . . . . . . . . . . .

Input-Output Equipment Characteristics

Powers of 2 . . • . . . . . . . . . . . . .

Page

A-19

A-21

A-22 v

FOREWARD

This manual is for programmers and users of the Programmed Data Processor-4, a high speed, stored program, digital computer manufactured by the Digital Equipment Corporation.

Chapters 2 and 3 contain the detailed information necessary to make use of the machine.

Chapter 1 summarizes the machine's electrical and logical design. Chapter 4 presents information helpful in making the electrical connections to input-output devices. Appendices provide detailed data which may be helpful in specific programming assignments. Although program examples are given in this document, no attempt has been made to teach programming techniques.

VII

SI.;",dord

P D P

Jyslem

CHAPTER 1

SYSTEM DESCRIPTION

SUMMARY

The Digital Equipment Corporation Programmed Data Processor-4 (PDP-4) is designed to be the control element in an information processing system. PDP-4 is a single address, parallel, binary machine with an 18-bit wore length using one's or two1s complement arithmetic. Standard features of the machine are stored program operation, a random access magnetic-core memory, a complete order code, and indirect addressing.

Standard core memory size is 1024 or 4096 words, expandable to 8192 words. The memory cycle time is 8 microseconds. Instruction enactment times are multiples of the 8-micr<:>second memory cycle, with two-cycle instructions such as add, deposit, load, etc., performed in

16 microseconds. Indirect addressing requires an additional 8 microseconds.

Flexible, high-capacity input-output capabilities of the PDP-4 enable it to operate in conjunction with a variety of peripheral devices, such as perforated-tape readers and punches, punched-card readers and punches, teletype printer-keyboard, line printers,. magnetic tape transports, and analog-to-digital converters.

The machine is completely self-contained, requiring no special power sources, air conditioning, or floor bracing. From a single source of 115-volt, 60-cycle, single-phase power, PDP-4 produces circuit operating dc voltages of -15 volts

1) and +10 volts

1) which are varied for marginal checking. Total power consumption is 900 watts. It is constructed with standard

DEC 4000 series system modules and power supplies. Solid-state components and built-in marginal checking facilities insure reliable machineoperation.

SYSTEM DESCRIPTION

The basic PDP-4 system is shown diagramatically in Figure 1. Three portions of the system are delineated according to function: the Arithmetic and Control Element, the Interface, and the Input-Output Equipment. Information originates not only from the Input-Output Equipment

ARITHMETIC OPERATOR _ _ INTERNAL _ _ CORE __ MEMORY

AND CONTROL CONSOLE -PROCESSOR -

*

*

MEMORY,...--------tle""'.-! MODULE,

*

TYPE 17

-----~--=---+-------------

INTERFACE

REAL TIME

..-------I~~

CONNECTION

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

--.J~

*

INPUT-OUTPUT

EQUIPMENT

PERFORATED -

TAPE READER

*

*

INCLUDED IN A

STANDARD PDP-4

-

"

PRINTER- KEYBOARD

AND CONTROL, TYPE 65

PERFORATED -

CONTROL,TVPE 75

Figure 1 PDP-4 System with Real-Time Connection

2

but can be entered manually and modified at the Operator Console.

Ari thmeti c and Contro I EI ement

The Operator Console, Internal Processor, and Core Memory constitute the Arithmetic and

Control Element. The Internal Processor carries out the arithmetic and logical operations, and controls the real-time connection and the core memory. Binary arithmetic with a fixed point is employed.

The Console is used to observe and control the action of the program and the Internal Processor, and to a I ter the contents of I nterna I Processor registers. The contents of Core Memory can be examined or new information deposited. All Internal Processor registers are displayed continuously.

Three memory capacities are available in PDP-4: 1024,4096, or 8192 words. Standard models

PDP-4A and PDP-4B come with 1024-word and 4096-word memories, respectively. The two models are identical in every other respect. The smaller memory has a 32 by 32 by 18 core array; the larger a 64 by 64 by 18 core array. A Memory Module Type 17, containing a 64 by 64 by 18 core array may be added to PDP-4B to give it a 8192-word storage capacity.

The cycl e time (the time required to read inFormation from memory and rewrite information back into me'mory) is 8 microseconds. The access time (the time required to read information from memory) is 2 microseconds. In the event of power failure, the contents of the Core

Memory rema in una I tered •

Interface

The Real-Time Connection,furnished as standard equipment, provides communication between the Internal Processor and the Perforated-Tape Reader, the Perforated-Tape Punch, and the

Keyboard-Printer. The Real-Time Option Type 25, gives the system the additional capability to operate efficiently over a wide range of information handling rates (from seconds per event to 125,000 words per second) and with a large variety of input-output devices (see Figure 2).

The Real-Time Option consists of a Device Selector, an Information Collector, an Information

Distributor, an Input-Output Skip connection, a Program Interrupt facility, a Data Interrupt facility, and a Clock/Timer.

The Device Selector consists of decoding elements to select and establish the state of an

3

A

RITHMETIC

AN

D CONTROL

NTERFACE

OPERATOR

CONSOLE

*

INTERNAL

~

PROCESSOR

*

CORE

~

MEMORY

*

-

-

..

..

..

..

-

~

REAL TIME

OPTION,

TYPE 25

MEMORY

MODULE,

TYPE

17

--- -- ------+--------------

- - - - - - - - -

IN

PUT-OUTPUT

E QUIPMENT

PERFORATED-

TAPE READER

*

I--

!--

r--

~

4

----_.

~

+-- - - - - - - -

I t

PRINTER-KEYBOARD

AND CONTROL, TYPE 65

rf - -

I- - - - -

PERFORATED

-

CONTROL, TYPE 75

,

..

CARD READER

AND CONTROL,

TYPE 41 -200-4

~

FROM OTHER

INPUT

EQUIPMENT

MAGNETIC TAPE

SYSTEM CONTROL.

TYPE 54

1 1

:

!

MAGNETIC TAPE

TRANSPORT UNIT,

TYPE 50

CARD PUNCH

~

CONTROL,

TYPE 40-523-4

--

LINE PRINTER

-

AND CONTROL,

TYPE 62-4

..

--

RELAY BUFFER,

TYPE 67-4

*

INCLUDED IN A

STANDARD POP-4

~

LIGHT PEN,

TYPE 32

VISUAL CRT

DISPLAY, TYPE

30r

~

TO OTHER

OUTPUT

EQUIPMENT

Figure 2 PDP-4 System with Real-Time Option

4

external device when the program issues an input-output transfer instruction. The direction of information transfer (in or out of the Internal Processor) is controlled by signals produced by the Device Selector. Up to 64 Input-Output devices can be selected and these, in turn, may cause the selection of many more. The standard Device Selector has provisions for twenty selector elements.

The Information Collector receives information from input devices (selected by the

Device Selector) and transfers the information to the Internal Processor. Up to 18 bits of information can be collected simultaneously; 8 x 18 bits of information may be collected, broken into variable-sized words.

The I nforma tion Distributor distributes information from the I nterna I Processor to a II output devices. Only the output device selected (or addressed) by the Device Selector samples and reads in the information contained in the Information Distributor. Up to

8 x 18 bits may be distributed.

The Input-Output Skip Connection provides a program skip instruction conditioned by the state of a given Input-Output device logic line. The instruction following the skip instruction will not be executed if the line is a ONE. Eight skip conditions may be sampled.

The Program Interrupt permits one of eleven lines (or conditions) or Input-Output devices to interrupt the program and initiate a subroutine which may return to the original program when the cause for interruption has been processed. The machine state is preserved during a Program Interrupt. This type of interrupt is suited for information or event rates in the range of

°

to 2,000 cycles per second.

The Data Interrupt allows a device to automatically interrupt the program and deposit or extract data from the Core Memory at an address specified by the device. The Data

Interrupt is suited for high speed information transfers, since up to 125,000 18-bit words may be transferred per second.

The Clock/Timer produces a signal which increments a core memory register at a rate of 60 cycles per second. When the register overflows, a Program Interrupt occurs.

5

Input-Output Devices

All of the input-output Devices are optional except the Perforated-Tape Reader.

The Perforated-Tape Reader senses 5-, 7-, or 8-hole perforated-tape information at the rate of 300 lines per second. Either one line of tape (alphanumeric) or 3 lines of tape (binary word) may be read.

The Perforated-Tape Punch and Control, Type 75, perforates 5-,7-, or 8-hole paper tape at a rate of 63.3 lines per second.

The Printer Keyboard and Control, Type 65, includes a Teletype Model KSR-28 Printer and Keyboo rd with an allowable input or printing rate of ten characters per second.

Typed information may be monitored by a program. A program may print information.

The Visual CRT Display, Type 30A or 30D, displays data on a 9 1/4" by 9 1/4

11 area.

Information is plotted on a point by point basis to form either graphical or tabular data. Operation of this device requires the Real-Time Option.

The Light Pen, Type 32, is a photoelectric device which detects information displayed on the Type 30 Visual CRT Display. The Light Pen may be used to draw functions, in effect, on the CRT by monitoring displayed information. Requires Real-Time Option.

The 18-bit Relay Buffer provides contacts which operate devices of higher power rating.

The relays have form "DII contacts, which opel and close in approximately 3 milliseconds.

Requires Real-Time Option.

The Magnetic Tape System Control, Type 54, controls up to four Magneti c Tape Transport

Units, Type 50. Information is read from or written on the tape. The format on the tape may be programmed to be compatible with IBM tapes having a density of 200, 6+1 bit characters per inch. Requires Real-Time Option.

The Magnetic Tape Transport Units, Type 50, are used with the Magnetic Tape System

Control, Type 54.

6

The Line Printer and Control, Type 62-4, operates at up to 600 lines per minute, 120 columns per line. Each column may print one of 64 characters. Spacing format is controlled by a punched format tape in the Printer. Once a command to print or space is given, the Internal Processor is not required. Approximately one per cent of program running time is required to operate the Line Printer at a 600 line per minute rate. Requires Rea I-Time Option.

The Card Reader and Control, Type 41-200-4, operates at a rate of up to 200 cards per minute. Cards are read column by column. Column inform:1tion may be read in alphanumeric or binary mode. The alphanumeric mode converts the 12-bit Hollerith Code of one column into the six-bit binary-coded decimal code with code validity checking. The binary mode reads a 12-bit column directly into the PDP-4. Approximately one per cent of a

Card Reader program running time is required to read the 80 col umns of information at the 200 cards per minute rate. Requires Real- Time Option.

The Card Punch Control, Type 40-523-4, enables the operation of a standard IBM Type

523 Summary Punch with PDP-4. Cards are punched on a row by row basis at a rate of

100 cards per minute. Approximately 0.3 per cent of program running time is required to operate the Card Punch at the 100-card-per-minute rate. Requires Real- Time Option.

7

CHAPTER 2

ARITHMETIC AND CONTROL ELEMENT

In this section the functions of the Arithmetic and Control Element, summarized in the previous section, are described in detail. The instruction codes and operations are then explained and listed.

FUNCTIONS

Internal Processor

The I nterna I Processor performs a ri thmeti c opera ti ons, control s the memory, and handl es information entering and leaving the machine. It consists of six registers, shown within the dotted line in Figure 3: the Accumulator, Link, Memory Buffer, Memory Address,

Program, and Instruction registers.

Accumulator (AC): an 18-bit register, which together with the Memory Buffer, performs the arithmetic operations. The AC may be cleared, complemented, and rotated right or

I eft together with the Link. The contents of the AC and the contents of the Memory

Buffer may be added together, the logical AND formed, and the exclusive OR formed and placed in the AC. The logical OR of the AC and the Accumulator Switches (ACS) on the Operator Console may be placed in the AC. The AC also acts as an input-output buffer register.

Link (L): a one-bit register to extend the facilities of the AC. It may be cleared, complemented, and shifted (as part of the

AC).

It is used as an overflow flip-flop for lis complement arithmetic and as a carry register for 2

1 s complement arithmetic. It functions as a program flag, an overflow Hag, and a carry extension register.

Memory Buffer Register (MB): an 18-bit register which holds information read from a selected memory address (specified by MB). The reading of information from a cell

(the l8-bit word stored at one memory address), clears the contents of the cell. The

MB also specifies the information written back into the selected cell. The time required

9

DATA INTERRUPT

ADDRESS AND

DATA LINE S TO

AND FROM EXTERNAL

DEVICES. UNDER

CONTROL 0 F REAL

TIME OPTI ON

ACCUM U L ATOR

SWI TCHES 18

ADDRESS

SWITCHES 13

NORMAL D ATA

TRANSFER LINES

TO AND FRO M

EXTERNAL DEVICES,

VIA THE RE AL TIME

OPTION OR UNDER

CONTROL 0 F REAL

TIME CONN ECTION

I

KEYS

I

(OF OPERATOR

I

CONSOLE)

(OF OPERATOR

(OF OPERATOR

I i

I

J

CONSOLE) CONSOLE) i-l--

- - - - - - -

---PR~t:- ~

ACCUMULATOR

~

I8

l~

r - -

.-

~

COUNTER

13

M~MORY----l

ADDRESS

~

MEMORY REGISTER I3

AND

~

MEMORY

r

BUFFER

REGISTER 18 .....

I

I

I

MEMORY

MODULE,

TYPE 17

I

LINK I

INSTRUCTION

I

I

COUNTER 4

I---}

CONTROL

I

I

I

I

I

I

INTERNAL

PROCESSOR

INTERNAL PROCESSOR

CONTROL

(CONTROL STATES,

TIMING, ETC.)

~

SIGNALS

TO AND f4-----

FROM ALL

I

J

I

I

I

Figure 3 Arithmetic and Control Element

10

to read information from a cell and rewrite information into the cell (memory cycle time) is 8 microseconds.

The register may be cleared and information read in from the Program Counter, the

Accumulator, or external sources for Data Interrupt. The register may be advanced by one.

Memory Address Register (MA): a 13-bit register used to address (or select) a memory cell. The MA may be cleared and information read in from the MB, the Program Counter, or external sources for Data Interrupt. The 13 bits allow addressing of 8192 words of

Core Memory.

Program Counter (PC): a 13-bit register which contains the address of the cell in memory from which the next instruction will be taken. The register may be cleared and information read in from the MA, MB, or ADDRESS switches of the Operator Consol e. The register may be advanced by one.

Instruction Register (IR): a 4-bit register which contains the instruction currently being carried out by the machine. Information is read into the IR from the MB. Instruction word bits 0 through 3 are stored in the IR. These bits determine control to enact the instruction.

Core Memory and Memory Module, Type 17: The Memory stores information being collected or distributed and instructions for the Internal Processor.

As

described in the previous section, memory capacities of 1024, 4096, and 8192 words are available in PDP-4.

Operator Console: All controls and indications necessary to operate the PDP-4 are located on the Operator Console, shown in Figure 4. The functions of the keys, switches, and indicators on the Operator Console are given below.

11

.

.

_

_ .

.

....

_

,

..

' • • •

...

' . 8 . '

.

'-

I • • • • '

--

"", no

' • •• ••• e e ' ••• ' ••• •••

'

...

'

....

'

'

..

'

,

..

.

.

'

'

...

_.

'

'

.....

'

'

.....

'

'

.-e~·

• ,,

• Iii

·

...

..

_.to.

_f

"

' ",

Figur e 4 Opera t o, Console

1 2

Console Key

START

STOP

CONTINUE

EXAMINE

EXAMINE NEXT

DEPOSIT

DEPOSIT NEXT

Console Switch

POWER

ADDRESS

Function

Starts the computer. The first instruction is taken from the Core Memory at the address indicated by the ADDRESS switches. The START key clears the AC and L, and turns off the Program Interrupt.

Causes the computer to stop at the compl etion of the memory cycle in progress at the time of key operation.

Causes the computer to resume operation, beginning at the address specified by the PC. The key has three positions: off, on and holding, and on with spri ng return to off .

Sets the contents of the memory cell selected by the ADDRESS switches into the AC and MB. The

MA will contain the address of the memory cell being examined. The PC will contain the address of the next memory cell .

Sets the contents of the memory, at the address specified by the PC, into the AC and the MB.

The C(PC) (the contents of the PC) are indexed by one. The MA wi II conta in the address of the register examined.

Sets the word selected by the ACCUMULATOR switches into the memory at the location specified by the ADDRESS switches. The resul ts wi II remain in the AC and MB. The MA will contain the address of the memory cell hoi di ng the information.

The PC will contain the address of the next cell.

Sets the contents of the ACCUMULATOR swi tches into the memory at the location specified by the

PC. The MA will contain the address of the register hoi di ng the information.

Function

Controls the primary power to the computer.

A group of 13 switches which establish the memory address for START, EXAMI NE, and DEPOSI T keys.

13

Console Switch

ACCUMULA TOR

51

NGLE STEP

SI NGLE I NSTRUCTI ON

REPEAT

SPEED

Console Indicator

ACCUMULA TOR

MEMORY BUFFER

INSTRUClfON

MEMORY ADDRESS

PROGRAM COUNTER

LINK

BREAK, EXECUTE,

DEFER, FETCH

RUN

F unc tion

A group of 18 switches which establish the contents of a word to be manually deposited into memory by means of the DEPOSIT or DEPOSIT NEXT key, or to be brough t into the AC under program control.

Ca uses the computer to ha

I t at the compl etion of each memory cycle. Operation of the CONTI NUE key will step the program one cycle at a time.

Causes the computer to stop at the completion of each instruction. Operation of the CONTI NUE key will step to the next instruction.

Causes operations initiated by a key to be repeated as long as the key is depressed. The operations are performed at the rate set by the SPEED switch and S PEED control.

Varies the REPEAT interval from approximately

40 m i c roseconds to

8 seconds.

Indication

The contents of the AC

The contents of the MB

The binary code of the instruction being executed

The contents of the MA

The contents of the PC

The contents of the L (one bit)

The ;-:>rimary control state of the next memory cycle

The computer is executing instructions

14

CONTROL STATES

The PDP-4 operates in one of four primary control states during a core memory cycle: Fetch,

Execute, Control, or Break. The instruction establishes the control state. A decision for the next state or cycle is made at the completion of each state.

Fetch (F): brings a new instruction into the MB from memory. It is initiated before the beginning of each new instruction. The instruction is taken from the location specified by the PC. The instruction part of the word (bits a through 3) is then set into the IR and the PC is advanced by one.

If a two-cycle instruction is fetched, the next state will be either a Defer or an Execute.

If a one-cycle instruction is fetched, the instruction will be enacted and the next cycle or state wi II be another fetch.

Execute (E): enacts the instruction as the last cycle of an instruction. Any instruction which contains a memory address as part of the word, such as add C(Y) to C(AC), draws the contents of the indicated memory address into the MB and performs the indicated operation during the execute state.

Defer (D): obtains an effective address from memory during the defer cycle. This state occurs when a 1 is in bit 4 of a memory reference instruction. When deferring is specified, the contents of the deferred address cell are used to form the effective address. The instruction portion, and bit 4, of the deferred cell is ignored when obtaining the effective address.

Break (B): breaks the sequence of the main program for Data Interrupt or a Program

Interrupt. The Data Interrupt breaks the program only at the completion of an instruction, and allows information to be transferred between memory and an external

(10) device.

The Program Interrupt breaks the program only at the completion of an instruction, to enter a subroutine in register

O.

The Program Interrupt stores the C(PC) and the Link in location 0000 and enters the routine at location 0001 .

15

INSTRUCTION OPERATION

All instructions in the machine utilize bits 0 through 3 to define the instruction code and bits 5 through 17 indicate the Core Memory address of the operand or of operations performed which do not reference the memory. The instructions may be divided into memory reference, which require an operand from memory, and augmented classes, which do not require an operand.

MEMORY REFERENCE INSTRUCTIONS AND AUTO INDEXING

Memory reference instructions employ bit 4 as the indirect address bit. The bit allotment is indicated in figure 5.

A memory reference instruction which is to use an indirect address wil have a 1 in bit 4 of the instruction word. The original address, Y, of the instruction will not be used to locate the operand of the instruction, as is the normal case. Instead it is used to locate a memory register whose contents in bits 5 through 17 will be used as the address. Thus Y is not the location of the operand but the location of the location of the operand. Bit 4 is ignored during the indirect or defer cycle. If the memory register containing the indirect address is registers 10

8

- 17

8

, a 1 is added to the contents of the register before the indirect addressing occurs. The indirect reference to registers 10

8

- 178 is known as auto-indexing.

In the list of memory reference instructions which follows, attention is called to the instructions add Y and tad Y, which initiate lis complement and 2

1 s complement addition, respectivel y.

In lis complement arithmetic, negative numbers are represented by a 1 in the sign position

(bit 0 or leftmost bit) of the word. Each digit of the word decreases in significants from bit 1 to bit 17. The negative of a lis complement number is formed by complementing the number. The complement of a binary number is formed by changing all ones to zeros and all zems to ones. In lis complement convention, -0 (all ONES) results when adding -0 to 0 or adding -n to n.

In 2 1 s complement arithmetic, a negative number is represented by a 1 in the sign position.

The negative of a 2

1 s complement number is formed by complementing it and adding 1 to the resul t.

16

Z o z o

I - z

« 0

Q : -

WI-

0..«

OZ

(!)

Z -

OO

Ow

1 - 0 le::(

Z

(!) oo w o~

I-

eno

enW

WO::

0::-

0

0 oZ

«

II c z

«

0:: w a.> o z

LLO

Ow

=>0

Q:o

1 - 0

(/)

Z o z

01-

(J)<t

CJ)O w

O a:::..J

" o o e::(

(

__ ---------------J

A

- - - - - - - - - - - - - - - - -_ _

, o

I 2 3 4 5 6 7 8 9 10 II 12 13 14 15 16 17

Figure 5 Memory Reference Instruction Format

17

Mnemonic

Code cal Y doc

Y jms

Y dzm Y lac Y xor Y

Octal

Code

00

04

MEMORY REFERENCE INSTRUCTIONS

Time

( jJsec)

16

Operation

16

Call subroutine. The address portion of the instruction, Y, is ignored. If the indirect bit = a, the instruction takes the action jms

20.

If the indirect bit = 1, the action is jms i 20.

If MB = 0, then C(L) =)C(20 o

=)

~(20L_4)'

C(PC) =) C(20

5

21

=)

C(PC) .

0

L

_

17

) .

If

MB

=

1, then C(L) =) C(X a

=)

~(Xl_4)'

C(PC) =) C(X x

+

1

=)

C(

PC) .

5 o)'

_

17

)· x

= C(20 5- 17)

Deposit AC. The C(AC) are deposited in memory register Y. The C(AC) are unaffected by th is operation.

C(AC) =) C(Y) .

10

16

14

20

24

16

16

16

Jump to subroutine. The C(PC) and Link are deposited in memory location Y. The next instruction wi II be taken from Y +

1, the beginning of the subroutine. C(L) =) C(Y a

=) C(Y l

_

4 o),

), C(PC) =) C(Y), Y+1 =) C(PC).

Deposit

0 in memory. The C(Y) are changed to O. The original C(Y) are lost. a

=) C(Y).

Load AC. The C(Y) replace the C(AC). The previous C(AC) are lost. C(Y) =) C(AC) .

Excl usive OR. The excl usive OR logical function is performed on a bit-by-bit basis between the

C(AC) and C(Y). The result is left in the AC and the original C(AC) are lost.

C(AC).

I

-+

C(Y). =) C(AC) ..

I I

C(AC). original

I o o

1

1

Example

C(Y). C(AC). final

I I o a

1 1 o

1

1

0

18

Mnemonic

Code add Y tad Y xct Y isz Y and Y sad Y

Octal

Code

30

34

40

44

50

54

Time

(Il sec )

16

16

Operation lis complement add. The C(Y) are added to the C(AC) in lis complement arithmetic. The resul t is left in the AC and the original C(AC) are lost. The Link bit is set to a one if the magnitude of the sum of C(Y) and C(AC) is greater than 2

17

-1. C(AC)

+

C(Y)

=>

C(AC)

2 1 s compl ement add. The C(Y) a re added to

C(AC) in

2 1 s complement arithmetic. If there is a carry out of bit

0 of the AC, the Link wi II be set to

1.

This feature is useful in multiple precision arithmetic. C(AC)

+

C(Y)

=>

C(AC)

Execute. The instruction in register Y will be executed. The computer wi II act as if the instruction located in Y were in the place of the xct Y.

8+ time of instruction being executed

16

16

16

Index and skip if

O.

The C(Y) are replaced by C(Y)

+

1.

The C(AC) are unaffected by this instruction. The addition is done using

2

1 s complement arithmetic. sum is

If the resulting

0, the instruction following the isz is skipped.

C(Y)

+ 1

=>

C(Y), if C(Y)

+

1 =0, then C(PC)

+ 1

=>

C(PC)

Logical AND. The logical AND function is performed on a bit-by-bit basis between C(AC) and C(Y). The original C(AC) are lost.

C(Y). /\ C(AC).

I I

=>

C(AC) ..

I

C(AC). original

I o o

1

1

Example

C(Y).

I

C(AC).

final

I o

1 o

1

0

0

0

1

Skip if AC is different than Y. The C(Y) are compared with the C(AC). If the two numbers are different, the next instruction in the sequence is skipped. The C(AC) and C(Y) are both unaffected hy the instruction.

19

Mnemonic

Code

Octal

Code

Time

( f.lsec) imp

Y

60

8

Operation

If

C(AC)

-I

C(Y) then C(PC)

+

1

=>

C(PC).

Jump. The C( PC) are reset to address Y. The next instruction to be executed is taken from memory register Y. The original contents of the PC are lost. Y

=>

C(PC)

Augmented Instructions

Augmented instructions use bits 4 through 17 to specify combinations of microcommands. There are three augmented instructions: a. Operd'te instructions perform operations on the AC and Link, and allow a skip to take place as a function of the AC and Link. b. Load AC with a word allows the command to specify a constant with which to load the AC. c. Input-output transfer which pulses external (peripheral) equipment to initiate an information transfer. Input-output instructions are explained in detail in Section 3.

Since augmented instructions are microprogramming instruction, actions are specified by bits within the address portion of the instruction. Several actions may be called for in the same instruction word.

Operate Instruction

The operate (opr) augmented instruction is used for branching or skipping, modifying the contents of the AC, and rotating the contents of the AC. This is a single-cycle instruction which is enacted in 8 microseconds and is initiated by an instruction code of 74

8

, Bit allotment of this instruction is indicated in Figure 6 and the basic operate microinstructions are listed below. Bits of the instructions can be combined to form instructions which perform various operations in sequence.

20

I'J

-. co c

'" o

'"0

(l) o c

CO

3

(l)

-

(l)

-

(l)

:::J a...

-

-

:::J en o

:::J

""" o

-

~ o

-.J

CD

<.D

o

I'\)

()J

~

(J1

0)

The Operate Group

(Operation Code 11110)

ClA Instruction If A "0ne"

II

Cll Instruction If A One

..

A

Second Rotate Instruction

Do Not Skip On Condition If A "One"

Skip If Link Non Zero,SNL,lf A"One"

Skip If AC=O) SZA, If A IIOne"

N

.

Skip If AC

II o

= I, SMA) If A One

II

. I I "

HLT InsTruction If A One

()J

-Po

(J1 m

-.J

RAR Inst-ruction It A "One"

R A Lin s

. II t r u c t

Ion If A 0 n e

II

OAS Instruction If A "One"

CML Instruction If A "One"

• II

CMA Instruction It A One

II

./

cll cia cma oas fV\nemon ic

Code sma sza snl

Octal Code of

Address Part

100

BASIC OPERATE I NSTRUCTI ON GROUP opr 740000 Bit 4 = 0

Operation

200

Skip if the AC is minus.

If

AC

O

= 1 , then C(PC) + 1 => C(PC) .

Skip if the AC is 0 (+0). If ACO-17 bits are all 0, then C(PC)

+

1 =>C(PC).

Sequence

0

0

400 rcs ral rar

1000

2000

4000

10,000

4

15

20

Skip on non-zero link. If L = 1, then

C(PC)

+

1 => C(PC).

.

Reverse the condition for a skip; i.e., do not skip if any of the above skip conditions are present. Bits 9-11 are microprogrammed, and allow the logical expressions to be formed; e.g., smaV sza

V snl in various combinations. For a list of additional skip instructions see the following pages.

Allow a second rotate to take place at event time 1 if a rar or ral is used. (If this bit is a ONE, and ral or rar are used, no other instruction affecting AC may be given; namely, ern a , cml, oas, cia, cll.

Clear Link, 0 => C(L)

Clear AC, 0 => C(AC)

Complement AC, C(AC) => C(AC)

"Inclusive OR" AC switches with AC.

C(ACS) V C(AC) => C(AC)

Rotate AC and Link left one place.

C(AC.) => C(AC. 1)

1 1-

C(AC

O

)

=> C(L)

C(L) => C(AC'7)

Rotate AC and L right one place.

C(AC.) => C(AC. 1).

1 1+

C( L) => C(AC

O

)

C(AC'7) => C(L)

22

0

0

2

2

2

2

Mnemonic

Code

Octa I Code of

Address Part Operation

(If ral or rar are given, cma, cml, oas may not be given.) hit 40

Halt the machine. 0

=>

C(RUN)

Sequence

3 clc skp spa

The following mnemonic words have been assigned to these microprogrammed instructions in the operate class. opr nop las

740000

740000

750004

Operate. No effect.

No operation. No effect. rtl 742010

Load the AC with the ACCUMULATOR switches.

C(AC Switches)

=>

C(AC) .

Rotate the C(AC) and C(L) left two places. This is identical to giving two ral instructions. rtr

742020 Rotate the C(AC) and C(L) right two places. Identical to two rar instructions. stl

744002 sno szl

741001

741000

741100

741200

741400

Set the Link. (Clear the Link then complement the

Link.)

1

~C(L)

Clear the AC, then complement the AC.

-0

=>

C(AC)

Skip. C(PC)

+

1

=>

C(PC)

Skip if AC is positive. (Do not skip if

AC is negative.)

If AC

O

=

0, then C(PC)

+ 1

=>

C(PC)

Skip if AC is non-zero.

If

AC

-10,

then C(PC)

+

1

=>

C(PC)

Skip if

Link is

O.

If

L

=

0, then C(PC)

+

1

=>

C(PC)

The Load-Accumulator- With-Word Instruction law N 760000 Load AC with address portion, N, of the instruction.

Place ones in remaining bits of AC. The indirect bit specifies law if a 1 or opr if a

1

=>

C(AC

O

_

4

)' N

=>

C(AC

5

O.

_

17

)

23

I'V

..j:::...

""T1 co c

......

CD

::J

V>

-.-,

...

CD

- ;

» c co

:3

CD

::J

-r

CD

0

:J

-

C

()

-

-

0....

::J

V>

'"'0 c

-

I

-

::J

'"'0 c

-

0

C

-

- I

()

"'-J

11

0

:3

0

-to

-

~

-

~

01

0

N

().I

~

SPECIFIES THE INPUT-OUTPUT TRANSFER INSTRUCTION

(OPERATION CODE 1110)

: } MAY BE USED TO SELECT A SUB-DEVICE en

-oJ

(J)

CD

~

SELECTS A DEVICE

-

0

-

: J

MAY BE USED TO SELECT A SUB-DEVICE

CLEARS AC AT EVENT TIME I IF AIIONE"

TRANSFERS AN lOT PULSE AT EVENT TIME 3 IFA

I'

ONE -

TRANSFERS AN lOT PULSE AT EVENT TIME 2 IF A

II

ONE-

TRANSFERS AN lOT PULS E AT EVENT TIME

I

IF A

O NEil

The Input-Output -Transfer Instruction

The input-output transfer (jot) augmented instruction causes the Interface to produce iot pulses vvh ich select the

10 devices and transfer information. This is a single-cycle instruction which is enacted in 8 microseconds and is initiated by an instruction code of 70

8

. Bit allotment of this instruction is indicated in f;igure 7.

Operations caused by this instruction occur at three event times which are related to the internal timing of the Arithmetic and Control element. Event times 1 and 2 occur near the end of the cycle, and event time 3 occurs at the beginning of the next instructions. This ti m i ng a !lows one iot instruction to perform mul tipl e operations.

Before information can be transferred into the AC from an

10 device, the AC must be cleared.

Clearing of the AC, when necessary, during an iot instruction is programmed to occur at event time 1 by placing a 1 in bit 14. Use of the iot pulses to establish states or transfer data in

10 devices is discussed in Chapter 3.

25

CHAPTER 3

INPUT-OUTPUT EQUIPMENT

FUNCTIONS AND PROGRAMMING

PDP-4 is capable of operating with the ten input-output devices described in Section 1 and with a variety of others, the maximum number depending on their data rates. The computer can operate with most of the devices simultaneously. The Interface, consisting of the Real- Time

Connection or the Real Time Option, issues commands to the devices, monitors their state of availability, transfers information to them, and receives information from them. Since the

Internal Processor can store or read out data much faster than the devices can operate, the

Interface and the individual devices provide buffering to minimize the amount of program time consumed in transfers.

The Real- Time Connection, furnished as standard equipment, provides communication between the Internal Processor and the perforated-tape reader, the perforated-tape punch, and the keyboard-printer. The Real-Time Option, Type 25, gives the system the additional capability to operate efficiently over a wide range of information handling rates, from seconds per event to 125,000 words per second, and with a large variety of input-output devices. The Real-Time

Option consists of the Device Selector, the Information Collector, the Information Distributor, the Input-Output Skip Facility, the Program Interrupt Control, the Data Interrupt Control, and the Clock/Timer.

The coupling of input-output equipment to PDP-4 is similar for all devices. The electrical characteristics of the coupling are discussed in Chapter 4. The logical functions and programming instructions are given below.

INPUT-OUTPUT COMMANDS

Device Selector

The input-output transfer (iot) augmented instruction causes the Interface to produce pulses which select

10 devices and transfer information. Upon receipt of an instruction, the

Device Selector in the Interface performs one of the following functions:

27

Device

Selector lOT Pulses (3 X 20) _ Jumper Connections

-.

(3X64 Max) TolODevices)ICJIOS

From OS

From Input-

Devices lOT Pulses

(8XI8Mox)

Data Lines (aXIS) .....

.......

-

..

Inform ation

Collector

Flags

Information

Distributor

Data Lines (18) __ To Input

~~--------o~

Devices

Selected lOT

-I~.

In put

Device St-atus

Output

Skip

--

~---------~

Program Interrupt

From 10 Device

ReQuests(II) .....

Flags --

Program

Interrupt

Control

From OS

Selected lOT

P u Is e (C I

0 c k Co nt r

0

I) _

...

Real

Time

Clock

Request

Data

Data Direction.-. Interrupt

(IN/OUT)

Data _ Request Acknowledged

~--~--------~~

-1-3-A-d-d-r-e-s-s----4~~

Data

In t err u p t

Address

18 Incoming

Oat-a

-

Data

Interrupt

Information

UN)

Data

Interrupt

Inform otion

(OUT)

~---------------<>18 0 u t g

0 i n gOa t- a

28

(a) Starts a device (eg. asks for a I ine of perforated tape to be read and assembled into a word, or a card to be moved to a reading or punching station, etc.)

(b) Transfers data from the information buffer of an input device to the AC, through the Information Collector

(c) Transfers information from the AC, through the Information Distributor (10) to the buffer of an output device

(d) Senses the flag(s) associated with a device to determine its availability

(e) Resets the flags. These commands dismiss a device without asking for additional action.

The flags referred to above are binary signals generated by an external device upon completion of its assigned task. This technique allows the internal processor to resume its arithmetic operations after issuing an instruction to a relatively slow input-output device (data rate of less than

20,000 words per second). When a flag is set to

1 by the device, it signifies that:

(a) an output action (punch out, etc.) has occurred; the Ari thmeti c and

Control Element may transmit data to the device.

(b) an input action (card or tape input, etc.) has occurred; information is available for the Arithmetic and Control Element

(c) an alarm condition exists

Flags may be sensed, and a program skip take place, using the Output Skip Facility. Flags may be read into the AC using the iors instruction. Most flags are connected to the Program

I nterrupt (see below) .

The Device Selector selects an input-output device according to the address code of the device in bits 6-11 in the iot instruction. It then generates

10 pulses at event times 1,

2, and 3 if the appropriate micro-instruction code bits are present in bits 17, 16, and 15.

Pulse iot 1 occurs near the end of an iot instruction, followed by iot 2 in 2 microseconds. lot 3 occurs at the beginning of the next instruction, 1.2 microseconds after iot 2. This timing enables one iot instruction to perform multiple operations.

Information Collector

The Information Collector enables information to be collected from eight l8-bit word input devices. The AC must contain ZERO at the time the inputs are sampled. A word can be

29

broken into smaller words according to the word size requirements of the input device. The program steps for reading the contents of a group of static parallel data bits are: cia Clear the AC (AC must equal zero) iot Selected device (sample the selected device outputs) dac Y

Deposit C(AC). The C(AC) are sent to a particular memory cell, Y.

(the first two steps may be microprogrammed together in one instruction)

Information Distributor

The Information Distributor presents the static data contained in the AC to each output device requiring AC information. The devices sample the Information D>istributor using the programcontrolled pulses from the Device Selector. The program steps for transmitting information from a particular memory cell are: lac Y iot cl ear selected output register

Load the AC with C(Y)

Prepare for information iot transmit The information is sampled and placed in the register of the inputoutput device (the second two steps may be combined in one instruction)

Input-Output Skip Facility

The Input-Output Skip facility enables the program to skip (or branch) according to various external device (or 10) states. There are eight inputs to the Skip facility. The iot pulses from the Device Selector strobe an input line and if a logic condition is present, the instruction following the iot is skipped. The iot skip pulse must occur at event time

1.

Program I nterrupt Control

The program interrupt allows a logic line state to interrupt the program. It is used to speed the processing of input-output device information, or to allow certain alarm conditions to be sensed by the computer. The interrupt may be enabled or disabled by the program.

When the interrupt occurs, the contents of the Program Counter and the Link are stored in memory location

0

(bits

0,5 . . . 17) and an interrupt program begins in memory location

1.

30

This action disables the interrupt mode. The interrupt program is responsible for finding the signal causing the interruption, for removing the condition, and for returning to the original program.

When the condition for interruption is removed, an iot signal to re-enabl e the program interrupt is given, followed by the instruction, imp indirect

0, or

6,~0~00.,

The interrupted program will thus resume. If a program interrupt request is waiting, it will be serviced after the

620000 instruction.

If a second interruption condition occurs and the interrupt program is running, the signal will have no effect. That is, there is only one level of interruption. The start key disables the program interrupt system. The iot instructions for the program interrupt are: iof -

700002 -

Disable the program interrupt ion -

700042 -

Enable the program interrupt

The state of the program interrupt may be examined using the iors instruction,

700314.

If the program interrupt is on, a 1 is read into bit 0 of the AC. The other bits of the AC contain the status of other devices.

Clock/Timer

The Clock produces a pulse every

1/60 second

(16.6 milliseconds) which temporarily interrupts the program (in the same manner as the data interrupt) and a 1 is added to the contents of memory cell 7 using 2

1 s compl ement addition. I f the content of memory cell 7 is 0 after the addition, the Clock Flag is set to 1, wh ich initiates a program interrupt. Depressing the START key on the Operator Console clears the Clock Flag and disables the Clock. The iot instructions associated with the Clock are: csf -

700001 -

Skip the next instruction if the Clock Flag is a

1 cof -

700004 -

Disable the Clock and clear the Clock Flag con -

700044 -

Enable the Clock and clear the Clock Flag

Register 7 is identical to other core memory registers, that is, its contents may be examined or modified. By presetting register 7 to a number, a program interrupt wi" occur when the register overflows or after a timed interval.

The status of the Clock may be examined using the iors instruction,

700314.

If bit

6 is a 1, a Clock overflow program interrupt has occurred.

If bit 7 is a 1, Clock counting is enabled.

31

ID

(18) SPECIFIES

X,Y COORDINATES .......

~

~

G

DS

700502

700504

EJ

B

...

JIll""

...

.....

VISUAL

DISPLAY

TYPE

30

CONTROL

" 't

X

.....

..... 16"

"y

"

.....

CATHODE

.....

RAY TUBE

INTENSiFy .....

......

STATUS BITS:

NONE

PROGRAM INTERR UPT:

NONE

Figure 8 Visual CRT Display programming logic

32

INPUT-OUTPUT DEVICES

All of the Input-Output Devices discussed below can be controlled by the Real-Time

Option, Type 25. The Real- Time Connection, furnished as standard equipment, provides communication between the internal processor and the perforated tape reader, the perforated tape punch, and the keyboard-printer. All devices except the perforated tape reader are optional. This section is arranged in the order of increasing complexity of connection.

Visua I CRT Display, Type 30A

Data points are displayed on a

9

1/4 inch by

9

1/4 inch area. Information is plotted on a point by point bas,is to form either graphical or tabular data. Two digital-to-analog converters drive the deflection yokes in the

X and

Y directions. Data can be plotted at a 20 kc rate.

The program loads the AC with a point to be plotted. Bits 0 through

8 specify the

X co-ordinate of the point and Bits 9 through 17 the Y co-ordinate. The C(AC) are then transferred to the Display Buffer. The specifying of the point initiates the plotting of the point on the CRT.

The CRT, Type 30A is selected when the nUnll,,,,;s 0 and 5 (octal) are specified in bits

8 and

9 respectively, of the iot instruction. The display commands are: dis - 7000506 - Load the Display Buffer and select the display. The program loads the Display Buffer from the AC.

A point is plotted as specified by the C(Display Buffer). The plotting requires

50 microseconds, after which another dis can be given. The Light

Pen Flag or Display Flag is cleared with dis.

700502 - Clear the

X and

Y display buffers. 0

=>

C(Display Buffer) .

700504 - C(AC) V'C(Display Buffer)

=>

C(Display Buffer). Plot the point specified by the C(Display Buffer).

The points specified in the AC are plotted as unsigned quantities, beginning in the lower

I eft hand corner of the cathode ray tube. The point locations are:

000777 •

·r

9

1/4"

000000 r..---.-9

1/411----~~

777tO

-----3I..".~1

33

2

9 . pOI nts

G

IC

......... CHECK STATUS

........ (BIT 5)

DS

700501 lOS

.......

......

LIGHT

700502...

PEN

...

CONTROL

......

........

LIGHT

PEN

FLAG

PIC

LIGHT

PEN

TYPE

32

STATUS BITS:

05-LIGHT PEN FLAG =1

PROGRAM INT ERRUPT:

LIGHT PEN FL AG

Figure 9 Light Pen programming logic

34

A program sequence is given in PDP-4 MACRO language below. The program begins in register 40, and plots a point, xy, as specified by Core Memory register 10.

PROGRAM SEQUENCE

/displaya point 30a

1 0/ / x y bits 0 - 8 x, bits 9 - 1 7 y.

40/ lac 10

700506

/place xy co-ordinate in ac

/display the point, next dis command must wait 50 microsec.

- - - - '

Ugh t Pen, Type 32

The Light Pen is a photosensitive device which detects the presence of information displayed on a CRT.

If the Light Pen is held in front of the CRT at a point displayed, the Display Flag will be set to a 1, The Pen is specified by 0 and 5 in bits 8 and 9 of the iot instruction. The commands are: dsf - 700501 - Skip if Display Flag is a 1 , dcf - 700502 - Reset the Display Flag to a O.

The Display Flag is connected to bit 5 of the iors instruction, and to the Program Interrupt.

Visual CRT Display, Type 30D and Light Pen, Type 300

The type 300 display plots points at a 20KC rate. The x and y co-ordinate buffers (XB and

YB) are loaded from the 10 bits, AC

S

_

17

'

The instructions are: dsf - 700501 - Skip if the Display Flag is a 1. The Light Pen is connected to the

Display Flag. dcf - 700601 - Clear the Display Flag. dx I - 700506 - Load the C(X B) wi th C(AC

S

_

17

)' dyl - 700606 - Load the C(YB) wi th C(AC

S

_

17

)' dxs - 700546 - Load the C(XB) with C(AC

8

_

17

). Plot the point: C(XB), C(YB). dys - 700646 - Load the C(YB) with C(AC

8

_

17

). Plot the point: C(XB), C(YB). dlb - 700706 - Load the Brightness Register with AC - AC'7' The bits of AC

J6 specify the brightness of the points displayed. Clear the Display Flag.

35

700502 - Clear XB.

700504 - C(XB) V C(AC)

=>

C(XB). Display a point.

700602 - Clear YB.

700604,- C(YB)

V

C(AC)

,

=>

C(YB). Display a point.

, "

, ,

,

The Display Frag is connected to the Program Interrupt and to bit 05 of the iors instruction.

The displaY~9 po'int locations are:

0, 1777 •

• lT71 1777

9 1/4"

!

X=O, y=Q

5

,.9 1

I

4"

---------1.~1

1777,0 rr--

10

. pOI nts

\

PROGRAM SEQUENSE

/displaya point 30d

10/

Ix

bits

8-17

/y

40/ lac 10 dxl lac

11 dys

/Ioad x

Iload y and plot the point

Analog-to-Digital Converter.(Typicallnput Device)

An analog-to-digital converter with a resolution of a,~its and a conversion time of 2 microseconds may be connected to the Real Time Option. The input-output transfer instructions, series

11, for the converter are: sci- 701115 - Sample the analog input. Convert the'sampled quantity to digital form and load the AC wi th the converted number.

701101 - This microinstru~,tJo~

'starts th~ conv~rter.

In a period of 2 microseconds the conve'~t~ri wi II fo~m an 'a"_bit number proportional to the analog

~

,

~ input.

36

G

(8) INFORMATION

..........

AC 10 -AC17

.........

IC

.......

........

DATA READ IN

DS

EJ

701104

~

11

SERIES

701101

.....

-- (START CONVERSiON) ......

8 BIT

ANALOG

TO-

DIGITAL

CONVERTER

........

.......

ANALOG

INPUT

E1

Figure 10 High-speed analog-to-digital converter programming logic

37

r - -.........

(12)INFORMATION

IC

.........

....

..... _.......

)READ DATA

AC6-AC17

SAMPLE DATA

.....

OS

11 SERIES

,.

701102

CLEAR FLAG ....

701104 .....

START CONVERSiON .....

....

_

...........

701101

)

SKIP IF DONE

CONVERT

12 BIT

ANALOG

TO-

DIGITAL

CONVERTER

ANALOG

.... INPUT

......

; DONE FLAG

STATUS BITS: NONE

PROGRAM INTERRUPT:

CONVERT DONE FLAG t.:J

Figure 11 Slow-speed analog-to-digital converter programming logic

38

701104 - C(A-D Converter) V C(AC)

=>

A(AC)

A program sequence to sampl e a function at the input to the converter, and store the result in memory register 10 would be:

PROGRAM SEQUENCE

/analog-to-digital converter

10/ /Iocation of sampled resul t

42/ sci dac 10

/701115, places sample in AC

/ deposit resul t

Low Speed Analog-to-Digital Converter

An analog-to-digital converter with a resolution of 12 bits and a conversion time of 60 microseconds can be connected to PDP-4. The converter is given an iot command to sample the analog function, and in 60 microseconds the converter will contain a 12-bit number proportional to the input. At the completion of the sample, the Converter Flag is set to a

1 , signifying that the input data is ready.

The contents of the Converter Buffer are read into the AC with a program command. The action which transfers the information from the converter to the AC also resets the Converter

Flag. An iot skip instruction is used which skips if the conversion is complete; i.e., the

Converter Flag is a 1. The program instructions, iot series 11, are: asf - 701101 - Skip if the Converter Flag is a 1 . arb - 701112 - Read Converter Buffer and clear Converter Flag. ase - 701104 - Start the converter and clear the Converter Flag.

701102 - A microinstruction which clears the Converter Flag, and C(Converter)

Buffer) V C(AC)

=>

C(AC)

The Converter Flag migh t connect to the Program Interrupt.

Perforated- Tape Reader and Control

The tape reader senses 5-, 7-, or 8-hole perforated-paper (or Mylar) tape at 300 characters

(or lines) per second photoelectrically. The reader control requests reader movement, assembles data from the reader into a Reader Buffer (RB), and signals the computer when incoming data

39

MB~

(ALPHANUMERIC)

MB~2

(BINARY)

(18)R B (INFORMATION)

. .

_ _ 1 (CH EC K

STATUS)

700102

700104

(SKI p) READER FLAG

FEED HOLE

PERFORATED-

TAPE

8 HOLES OF

INFORMATION PERFORATED-

~~~~~~~~~

TAPE

READER

READER

CONTROL RUN SIGNAL

(CLUTCH ENGAGED,

BRAKE

DISENGAGED)

(INTERRUPT)

STATUS BIT:

1- READER FLAG

INTERRUPT:

READER FLAG

Figure 12 Perforated- Tape Reader programming logic

40

FLAG 0

1---'"

I I I

2·~1

3.3 MSEC r--

SINGLE CHARACTER TIME---+l

I u:

I

RSA

~X~

I

I •

I

I I

I I

RRB----------------------~I~~I~

I I

I I

CHAR. : :

AVAIL··lll!emmt~!!I'!!II!!l!!I'-------------I.,~~-

IN

RBiII_iiiiiiiiiiiiiliiilil -

READER

I(II!!IlI!!'!IIIlI!!If""""""'IPfIIIIII!III!!~eeeeell!!lll!!el!!l!lI!!III!!eI!!I!l!!IeI!!II!'lI!l!!Ii!I!!I!!II!'!II!!II!!I!!I!!!!II!!I!!II!I!~,......-o

I

2

I

4

I

6

I

8

I

10

I

FLAG 0

1-----

u

~

• II

I I

II

I I

RRB------------------------~I~I---------

II

I

CHAR.

AVAIL.~

INRB~~iiiIiIilIiIIIIiillilQiillil

I

.

R EADER - - -......

ENGAGED

...... - - - - - -

Figure 13 Perforated- Tape Reader timing

41

is present. Reader tape movement is started by the reader control request to release the reader brake and simultaneously engage the clutch.

In addition to the reader movement control logic, the control unit contains an 18-bit Reader

Buffer (RB) which can collect 1 or 3 lines from the tape. The C(RB) can be read into the AC.

The Reader Flag becomes a 1 when a character or word has been assembled in RB. A timing diagram of the Reader operation is shown in Figure 13.

An alphanumeric character is one line (5, 7, or 8 holes) on tape. A binary word consists of three consecutive characters (18 bits) on tape which have the 8th hole present. Only 8-hole tape is used in the binary mode; the 7th hole is ignored, and the six remaining bits of each character form one third of the 18 .... bit word. The reader commands, iot select series 01, are: rsf - 700101 - Skip if

Reader Flag is a 1 . rsa - 700104 - Select reader and fetch one alphanumeric character from tape.

Clear the Reader Flag. Reset RB. The charatter is read into

RB bits 10-17. Turn on the Reader Flag when character is present. rsb - 700144 - Select reader and fetch a binary word from tape. Clear the

Reader Flag. Reset the RB. Fetch the next th ree characters

(with 8th hal es present) from perforated tape and place in

RB bits 0-5, 6-11, and 12-17. Turn on Reader Flag when a word is assembl ed . rsf - 700101 - Skip if

Reader Flag is a

1 • rrb - 700112 - Read RB. Clear the Reader Flag, and transfer the contents of

RB to the AC.

700102 - CI ear the Reader Flag. C(RB)

V

C(AC)

=>

C(AC)

The Reader Flag is connected to the Program Interrupt Control and to bit 0 of the iors instruction.

Several methods may be used to program the reader. The following sequence reads a character from tape and places it in the AC. Up to 400 microseconds of program may be given between the end of the sequence and the next command to read a character or word from tape. The sequence, starting in register 40 is:

PROGRAM SEQUENCE

40/

.

700104 /rsa-select reader alphanumeric

42

700101 imp 41

700112

/rsf begin loop to look for character arrival

lend

loop to look for arrival

/rrb-fetch character from reader buffer

By changing instruction 40 to 7000144, or rsb, the sequence waul d fetch a binary word.

Printer-Keyboard and Control, Type 65

The printer-keyboard is a Teletype Model 28 (KSR, keyboard send-receive) which can print or receive ten characters per second. A five-bit code, given in Appendix 4, represents the characters. The printing (output) and keyboard (input) functions have separate commands and control logic.

The signals to and from the KSR to the control logic are standard serial, 7.5-unit-code

Teletype signals. The signals are: start (1.0 unit), information bits 1-5 (1.0 unit each), and stop (1 .5 units). Figure 14 illustrates the current pattern produced by the binary code

10110.

Keyboard

The keyboard control contains a 5-bit buffer (KB) which holds the code for the last key struck. The Keyboard Flag signifies that a character has been typed and its code is present in the Keyboard Buffer. The Keyboard Flag and Keyboard Buffer are cleared each time a character starts to appear on the teletype line. The Keyboard Flag becomes a one, signifying the buffer is full 0.5

±

0.125 units after the end of information bit 5, or 86.6 mill iseconds after key strike time. The instructions to manipulate the Keyboard are: ksf - 700301 - Skip if the Keyboard Flag is a 1 . krb - 700312 - Read Keyboard Buffer. Clear the Keyboard Flag. C(KB)

=>

C(AC)

700302 - Clear the Keyboard Flag. C(KB) V C(AC)

=>

C(AC)

The Keyboard Flag is connected to the Program Interrupt Control and the iors instruction, bit 03.

A timing diagram for the Keyboard is given in Figure 15, and an interconnection diagram is shown in Fi gure

16.

43

I-

100 MS

-I

O(CURRENT)

1 UNIT= 13.33 MS r-1"""1"""1"""1~1~1

:.IE

1.5-+1

(~T;SL~UER""R-E-N-T"'!""')

...

IJJ

0

I

1 1 .

[:J

T

I

!

(RETURN TO

START BIT1 BIT5 STOP

IDLE LINE)

SIGNAL SIGNAL

Figure 14 Teletype timing of information code 10110

44

0

I

10

20 30 40

I

I I I

MSEC

50 60 70

80 90

100

I

I I

I

, I

I

86.6

KEY

STRIKE

I

FLAG 0

1--"

W

KRB--------------------------------------------~-----

I

CHAR.

AVAIL.

INKB

CHAR.

ASSEM.

IN KB

.... I

1-----

COMPUTING TIME=100,uS

-----~.MI

BETWEEN CHARACTERS

AT MAXIMUM RATE

Figure 15 Keyboard timing

45

......... (5) KB (INFO.)

.........

INFO. STROBE

---01

IC

:"'BIT 3 (FOR CHECK

......... STATUS)

..... _ ..

I~T

03

DS

700302

SERIAL

INFO .

KEYBOARD j.NPUT

CONTROL

~

KEYBOARD

-.

700301

....

_

....... lOS ........ (SKIP)

.. ........

KEYBOARD

FLAG

STATUS BIT:

03 KEYBOARD FLAG

(INTERRUPT)

PIC

~~.~--------~

INTERRUPT:

KEYBOARD FLAG

Figure 16 Keyboard programming logic

46

A simple sequence which IIlistens " for keyboard inputs is:

PROGRAM SEQUENCE

II

isten loop for keyboard

400/ 700301 Iksf-skip when a character arrives from keyboard imp

400

krb

1700312-read

in the character

The sequence following the listen sequence, beginning in 403 may operate for up to 100

+

13.3 milliseconds before returning to listen for the next character without missing the next character. The average computing time between any two characters must be less than 100 mi

II iseconds (for an input rate of 10 characters per second) .

Pri nter (Tel epri nter)

The printer is given five bits of information from the AC, coding the character to be printed.

The Teleprinter Buffer (TB) receives this information, transmits it to the Teleprinter serially, and when finished turns on the Teleprinter Flag. The Flag is connected to the PI and to bit

04 of the iors instruction. A timing diagram for the Teleprinter is shown in Figure 17 and the interconnection diagram is shown in Figure 18. The printing rate is 10 characters per second. The instructions for the printer are

= tsf - 700401 - Skip if Teleprinter Flag is a 1 . tis -700406 - Load the Teleprinter from AC bits 13-17, clear the Teleprinter

Flag. Select the Teleprinter for printing. tcf - 700402 - Clear the Teleprinter Flag.

700404 - C(AC) V C( TB). Pri nt a character.

PROGRAM SEQUENCES

/print and wait for Teleprinter tis /print the character from AC bits 13-17 tsf /begin listen loop for printing completion

Ireturn to previous instruction or listen loop again imp .-1

·

/wait for previously printed character completion, then print tsf imp .-1 tis

·

/wait loop unti I previous character printed

/return to wait loop beginning

/print the new character

47

a

10 20 30 40 50 60 70 80 90 100

I

I

I I

I I

I I

I I I

MSEC

FIXED*----~I-------------------------------------------.,--

REF.

FLAG 0 -......

1-----.....

TLS

1 - - - -

OR

TCF**

L.*

PRI NT

ACTION

mmr------'

~ k--BUFFER MUST BE LOADED BY THIS TIME

TO ALLOW 10 CHAR/SEC OPERATION

* *

IF PCF, FLAG WILL NOT COME ON UNTIL NEXT TLS COMPLETE

*

DETERMINED BY PRINTER

Figure 17 Printer timing

48

FROM

KEYBOARO----------------------------------------------~

(5) INFORMATION

10

~--~

(FOR PRINTER

BUFFER)

..

IC

BIT4

..-. (CHECK STATUS)

........

SERIAL

D S H+-__

-+-__

+-7_0_0_4_0_2 P R I N T E R I N FOR MAT 10 N " ...

700404

---=

CONTROL

L---~t~t---~--~~~~~~~

.... PRINTER

~00401

_< ..

PRINTER

I P_) .........

...;F_L;;;",;.,,;A;..;;;G~

........

....

STATUS BIT:

04 PRINT FLAG

INTERRUPT:

PRINT FLAG

Figure 18 Printer programming logic

49

/

In the first sequence above, 20 milliseconds of program time is available between that tis and the next one that can be given. In the second sequence, 100 milliseconds of program time is available between that tis and the next one that can be given.

Perforated- Tape Punch and Control, Type 75

The Tel etype BRPE paper tape punch perforates 5-, 7-, or 8-hole tape at 63.3 characters

(I i nes) per second.

Information to be punched on a I ine of tape is loaded on an 8-bit buffer (PB) from the AC bits 10 through 17. The Punch Flag becomes a 1 at the completion of punch ing action, signalling that new information may be read into PB (and punching initiated). The Punch

Flag is connected to the PI, and to the iors instruction bit 02. The timing for the punch is shown in Figure 19. The Real Time Option connections of the punch and control are shown in Figure 20. The Perforated-Tape Punch instructions, iot series 02, are: psf - 700201 - Skip if the Punch Flag is a 1 • pcf - 700202 - Clear the Punch Flag. pis - 700206 - Load a character into PB from AC bits 10-17. Clear the Punch

Flag. Punch the specified character.

700204 - C( PB) V C(AC)

=>

C( PB). Punch the C( PB) •

PROGRAM SEQUENCES

/punch the contents of AC and wait pis psf imp .-1

/700206 punches AC 10-17

/wait till done loop beginning

/wait till done loop end

/wa it for previous punch i ng, then punch next psf /wait loop for previous character punching imp .-1 pis

/wait loop end

/punch the next character on tape

In the first sequence above, 11.3 milliseconds of program time iS,available between the instruction following the wait loop and the next pis that can be given. In the second sequence, 15.8 milliseconds or more program time is available between the pis and the next time a pis can be given.

50

o

2

I

I

4

I

6

I

8

I

~-------------------------I----------.I-----

FLAG

0 - -

1----~----------~

...... _-**

PLS

OR------------------~---------------------------

PCF

LOAD _ _

PB

PUNCH

ACTION

8fSl

I

BUFFER MUST BE

LOADED BY THIS

TIME TO ALLOW 63.3

CHAR

I

SEC OPERATION

*

DETERMINED BY PUNCH

* *

IF PCF FLAG WILL NOT COME

ON UNTIL NEXT P IS COMPLETE

Figure 19 Perforated- Tape Punch timing

51

_

(8) INFORMATION

~

....

10

...

(FOR PUNCH BUFFER)

IC

BIT 2(CHECK STATUS)

........

OS U ..... .....

-+-7~0~O~2~0~4

: . .

..

PERFORATED

TAPE

PUNCH

CONTROL lOS

700201

.......

~(SKIP)

PUNCH

FLAG

8 INFO.

PUNCH

PIC

(INTERRUPT)

~~.a------

STATUS BIT:

02PUNCH FLAG

INTERRUPT:

PUNCH FLAG

TELETYPE

BRPE

TAPE

PUNCH

Figure 20 Perforated- Tape Punch programming logic

52

Card Reader and Control, Type 40-200-4

The control of the card reader is different than the control of other input devices, in that the timing of the read-in sequence is dictated by the device. Once the command to fetch a card is given, the reader will read all 80 columns of information in order. To read a col umn, the program must respond to a flag set as each new col umn is started. The instruction to read the column must come within 300 microseconds after the flag is set.

The interval between flags is 2.3 milliseconds. Figure 21 shows the timing sequence following a command to read one card. The commands for the card reader, iot series 67, are: crsf - 706701 - Skip if Card Reader Flag is a 1.

If a card column is present for reading, the instruction will skip. crrb - 706712 - Read the card col umn buffer information into AC and clear the

Card Reader Flag. One crrb reads alphanumeric information.

Two crrb instructions read the upper and lower column binary information. crsa - 706704 - Select a card in al phanumeric mode. Select the card reader and start a card moving. Information will appear in alphanumeric form. crsb - 706714 - Select a card in binary mode. Select the card reader and start a card moving. Information will appear in binary form.

Upon instruction to read the card reader buffer, six information bits are placed into AC

12 th rough AC 17' AI phanumeric (or Holl eri th) information on the ca rd is encoded or represented with these six bits. The binary mode enables the 12 bits (or r::>ws) of each column to be obtained. The First read buffer instruction transfers the upper six rows (Y, X,

0,1,2,

and 3), the second instruction the lower six rows (4, 5, 6, 7, 8, and 9). The mode is specified with the Card Read Select instruction. The mode can be changed while the card is being read.

The Card Read Flag is connected to the Program Interrupt Control and to bit 9 of the iors instruction. The Card Read Done status level bit is connected to bit 10 of the iors instruction.

A Card Read Mal function status is connected to bit 11 of the iors instruction. Cord Read

Malfunction status indicates one or more of the following conditions: reader not ready

(power off, etc.), hopper empty, stacker full, card jam, validity check error

(if validity is on), or real circuit failure.

Bit 12 of the iors instruction is connected to the END OF FI LE switch at the Card Reader.

53

o

20 40 60 80 100 120 140 160 180 200 220 240 260 280 300

___

I~~I ~I

__

-L11~1_8~1

__

~I ~I

__

~1 ~I

__

~I ~I

__

~I ~1~2~i~2.1

___

CRSA ____

OR

~----------------------------------------------------

________________ __

CRSB -+11+-15

JJ

SEC

1

NEXT CRSA OR CRSB CANtBE GIVEN DONE

CARD

READER

FLAG

U

,

80-COLUMN READY SIGNALS

EVERY 2.3 MS

CRRB--------------------------~I------------------------------------~-----

\

80- CRRB EACH COMMAND

CLEARS COL FLAG

Figure 21 Card Reader timing

54

..... ...

MB1~(ALPHANUMERIC~.---

_ _

=

ID MB11 (BINARY)

.........

..-..

~(6)INFO.COL.

I I

INFO. STOBE

::..... "if l1li

(BIT 11)

IC

~

(BIT 10)

a.-_............

~

(BIT 9)

-----... (6) INFO.

......

CHECK

OS lOT 67 STATUS

~ t-+l~

CARD

READER

START

~7~0_6_7_0_2_........CO ~

L

_....J-~-t----tr7_0~6:;;;..:..70~4t~-i

• y

....... CAR D NOT

~

OK

......

CARD

~

CARD lOS

....... A

_____

COL.

~~F_L~A~G~~

........

"

'"--'" SKIP

STATUS BITS:

9 -CARD READER FLAG

10-CARD DONE

PIC .......... (INTERRUPT)

.......

11 -CARD MALFUNCTION

12 -END OF FILE

INTERRUPT:

CARD COL. FLAG

Figure 22 Card Reader programming logic

55

The switch is activated manually, and when depressed, holds until the RESET END OF FILE switch is depressed.

PROGRAM SEQUENCE

/sequence t~ read an 80-column card and place alphanumeric codes

/in register 1000-1117 (octal). Program begins in register cardrd. cardrd, crsa lac cardia doc 10 lac cardct dac temp

/read card in alphanumeric mode

/initialize card location table

/place in indexable register

/initialize card count 80 (decimal) cdloop, crsf imp cdloop crrb doc i

10 isz temp imp cdloop hit

/wait for col umn loop

/place col umn information in ac

/i nfo to 1000, 1001 ... 1117

1000-1

/finish of card, and hal t

/Iocation of card table cardia, cardct, temp,

-120+1 o

/80 col umn counter i ntia I va I ue

/reserved for col umn counter

Card Punch, Type 41-523-4

The card punch dictates the timing of a read-out sequence, much as the Card Reader controls the read-in timing. Once a card has started, all 12 rows wi II be punched at intervals of 40 milliseconds. Punching time for each row is 24 milliseconds, leaving 16 milliseconds to load the buffer for the next row. A flag indi cates that the buffer is ready to load. Figure

23 shows the timing sequence following a command to read one card. The commands for the card punch, iot series 64, are: cpsf - 706401 - Skip if Card Punch Flag is a one. The Card Punch Flag indicates the punch buffer is available, and should be loaded. cpcf - 706402 - Clear Card Punch Flag. cpsc - 706442 - Select the Card Punch. Transmit a card to the 80 column punch die from the hopper. cpl b - 706406 - Load the Co rd Punch Buffer from the C(AC). Five load instructions must be given to fi

II the buffer.

56

o

I

100 p08

I

200

I

300

I

400

I

500

I

572

600

I

I

~

1

*

CPSE*---P--------~------------------------------------------~--

PUNCHO ______ ~--~~

FLAG

CPLR

(5)

1----..

------~----~-'"_--~--r_~--~--~--~~~~--_r--~--r_---

I

I

:I

USED ONLY

LOAD

BUFFER

TIME

PUNCH

ACTION

I I

I I

I I

:~I

---J!'!!_~~~

r-

16

TO CLEAR

FLAG

..... mei--'I!!i!!Blr-mm!r"'""""Ilm~nlil,.....,m~'m~"Il'!Imr-mlSr--Im~'m~---

-----.....~-.~'"'W.~"'ftImal'l'ft!lP-

..... ......." •

~24k-

*CPSE MUST BE GIVEN TO MAINTAIN

MAX RATE. A DELAY OF 600 OR 1200 MS

WILL EXIST ON STARTING.

Figure 23 Card Punch timing

57

ID

(1S) INFORMATION

~

(FOR ROW

BUFFER)~

IC

OS

....... BIT 15 "

.......

--v-

I

CARD NOT

OK

STATUS

IOT64

~

...

706401

,.

..oIIIIl

...... lOS ............

(SKIP)

........ l1li

..........

CARD

PUNCH

706402 .....

CARD

706404

~

........

PUNCH

CONTROL

ADVANCE

CARD ___

..........

CARD

........ NOT OK

......

ROW

PUNCH

FLAG

(TYPE

523

SUMMARY

PUNCH)

PIC

~INTERRUPT)

........

STATUS BITS:

13-ROW FLAG

14- CARD NOT OK

INTERRUPT:

ROW FLAG

Figure 24 Card Punch programming logic

58

Since 18 bits are transmitted with each iot instruction, 5 iot instructions must be issued to load the 80-bit row buffer. The first four loading instruction fill the first 72 bits (or columns); the fifth loads the remaining 8 bits of the buffer from AC

10 through AC

17

.

After the last row punching is complete, 28 milliseconds are available to select the next card for punching.

If the next card is not requested in this interval, the card punch will stop. The maximum rate of the punch is 100 cards per minute in continuous operation.

A delay of 1308 milliseconds follows the command to read the first card; a delay of 108 mill iseconds separates the reading of cards in continuous operation.

The Card Punch Flag is connected to the Program Interrupt, and to bit 13 of the instruction.

Faults occurring in the punch are detected by status bit 14 of iors and signify the punch is disabl ed, or the stacker is full, or the hopper is empty.

PROGRAM

SEQUENCE

/sequence to punch 12 rows of data on a card. Each row is stored in

/5 consecutive registers beginning in location 100. The program begins lin register cardph . cardph, cpse lac punloc doc 10 lac rowct

Jac temp 1

Iselect

the card

/initial ize the card image

Ibop 1,

/initialize the row counts, 12. linitialize the

5 groups per row

Isense

punch load availability loop2, punloc, rowct, lac grpct doc temp2 cpsf imp .-1 lac i 10 cplr isz temp2 imp loop2 isz temp 1 imp loopl hit lOO-l

-14+1

15

groups of 18 bi t per row

Iload

buffer command

Itest

for 12 rows

lend

punching 1 card

/Iocation of card image grpct, temp 1, temp2,

-5+1

0

0

/12 rows per co rd

15

groups per row

I

row counter

·59

/group counter

10

MB112

(18) INFORMATION

.-.

.........

IC

.......

.......

~

II

'W"

CHECK STATUS

(BIT 13)

BIT 12

IOT65

~

OS fII •

--

SPACE

....

~SKIP lOS

..... A.

.....

.........

........ 'W"

SKIP

PRINT

PIC

.......

............

.......

(INTERRUPT)

706502 ....

(120) INFO.--.

.......

....

706602 ...

706604~

LINE

PRINTER

...... (8)SPACE

........

.....

CONTROL

INFO

SPACE ----..

.........

SPACE

FLAG

LINE

PRINTER

PRINT

FLAG

STATUS BITS:

16 - SPACE FLAG

15 - PRINT FLAG

INTERRUPT:

SPACE FLAG

PRINT FLAG

Figure 25 Line Printer programming logic

60

Line Printer, Type 62

The Line Printer can print 600 lines of 120 columns per minute. Each column has 64 characters. Spacing rate is approximatel y 132 I ines (or 2-66 I ine pages) per second.

A complete line, or a 120 columns of information, is placed in the Printing Buffer. Six bits specify each character (the codes are given in Appendix 4). The information is transferred to the Printing Buffer through the AC, three characters at a time from AC bits 0-5, 6-11, and 12-17. Forty load print buffer instructions fill the 120-column line.

After the Printing Buffer is loaded, a print instruction is given which prints the contents of the Buffer. The action of printing does not disturb the Printing Buffer. When a col umn of information has been printed, the Printing Flag becomes a 1. Approximately 80 milliseconds are required to print one line.

An eight-channel format-control tape within the printer moves in synchronism with the paper and specifies how far the paper is to be spaced. Holes punched in each channel of the format tape signify the next paper position. The channel is selected by placing a three-bit code in AC

15 through AC

17

, and giving an instruction to space paper. The Spacing flag becomes a one when the spacing action is complete.

TI-,e tape has the following characteristics:

Time Channel (AC

15

_

17

) a

1

2

3

4

5

6

7

Action

Space one line

Restore page

Space two lines

Space th ree lines

1/4 page

1/2 page

1/6 page

Not used

16 msec.

520 msec. for 66 lines

<

2 x 16 msec.

<

3 x 16 msec.

The line printer printing and spacing instructions, iot series 65 and 66, are:

I psf - 706501 - Skip if the Printing Flag is a 1 .

Ipcf - 706502 - Clear the Prin.ting Flag.

Ipld - 706542 - Load the Line Printer Buffer.

Ipsc - 706506 - Select the printer. Print the contents of the Printer Buffer. Clear the Printing Flag. (The Printing Flag becomes a 1 at the completion of the pri nti ng .)

61

Issf - 706506 - Ski p when the Spac ing Flag becomes a 1 .

Iscf - 706602 - Clear the Spacing Flag.

Isis - 706606 - Load the Spacing Buffer from AC -

1

7. and select spacing.

15

Clear the Space Flag. (The spacing flag becomes a 1 when spacing is complete.)

The Printing and Spacing Flags are connected to the Program Interrupt and to the iors instruction bits 15 and 16.

PROGRAM SEQUENCE

/sequence to print a line of 120 columns. Output stored 3 columns

/per word.

lData

begins in register 2000. Sequence assumes printer is

lin

process of printing a line previousl y assigned.

II

Print" is

Ibegin

of prog.

I psf /wa i t ti II previous prj ntj ng done imp .-1 cia

1515

/space 1 line (0 in ac) lac (2000-1/location of data da c 1 0

I

p r i n t ta b lei nit i a liz e lac (-50+ 1 /40x3 characters dac temp

Idloop, lac i 10

Ipld isz temp imp Idloop

/Ioad print buffer loop

Iload

from ac space,

Issf imp space

Ipse

/test for spacing done before proceeding

/print activate ... end of printing a line

62

CHAPTER 4

THE INTERFACE ELECTRICAL CHARACTERISTICS

As explained in previous sections, the standard Interface. contains the Real-Time Connection, wh ich can operate only with the perforated-tape reader, the perforated-tape punch, and the keyboard-printer. The Real- Time Option can operate with a variety of external devices

over

a wide range of information handling rates. In this section the location of the Real-Time

Option, its electrical characteristics, and its connections to input-output devices are presented.

REAL- TIME OPTION

A coordinate system locates modules and connectors in PDP-4 with a four place, alphanumeric code. Bays are numbered 1 and 2, panels are lettered alphabetically downward, connectors or modules are numbered left to right in the panels (blank spaces included), and terminals are lettered alphabetically downward on the connectors or modules. The Real-Time Option is located in panels 2E, 2F, and 2H. Connections to external control units are made through a cable connector in positions 2Jl-6.

The Device Selector (location 2F6-25)

The standard

Device

Selector contains provisions for up to 20 selector modules, each of which is a Pulse Ampl ifier, Type 4605. The amp I ifiers are pulsed with standard DEC 4000 Series negative logic pulses which can drive 18 units of base load.

Each module is wired to respond to one address code only (see Example, Figure 26). The 6-bit address portion of the iot instruction will therefore pass only through the six-level AND gate of those modul es wi red to the same combination of ones and zeros. The output of the AND gate enables three AND gates to pass the common iot 1, 2, and 3 pulses. These pulses are available at terminals E, H, and K, respectively, of modules 2F6-25.

The Device Selector Modules are delivered with jumpers across the address terminals. The user can

remove

appropriate jumpers to establish the module select mode according to the table below.

63

COMMON TOT

1-------------.

COM MaN rOT

2----------....... _

CO MMON lOT

3 - - - - - - - - - . .

SELECTED

..

--t>

1

PA t-+IOT 1

MB8 a

MB10

1

--:...cY

X

MB 11

~Y

1

Figure 26 Typical Pulse Amplifier, Type 4605, used in PDP-4 Device

Selector. Example shown is wired to pass the iot address 001101. The six-level AND gate will pass only that address if it is present in the instruction word from the Memory Buffer, thus enabl ing three AND gates to pass three

10 pulses to the pulse amplifier.

64

Instruction

Word Bit

6

7

8

9

10

11

ZERO Input

Terminal

M

P

S

U

W y

ONE Input

Terminal

N

R

T

V

X

Z

Information Collector (location 2H8-25)

The information collecting sequence begins with an iot pulse from the Device Selector applied to the strobe input of the Information Collector. The IC then ANDS with the Input Device information present level and the results are transmitted to the AC. The results of the AND functions are mixed, or ORed together, to enable eight 18-bit-word devices to read data into the AC. Two or more devices requiring less than 18 bits could share a word, provided their bit-position requirements did not conflict. In such cases, more than eight input devices could be handled by the IC. The incoming information signal polarities are: o vol ts o bit transmitted to AC

-3 vol ts 1 bit transmitted to AC

The IC consists of 18 modules, one for each bit of the word, starting with bit 0 in module 2H8.

All eight input channels are wired to each module. The convent!on for designating bits is

IC. k' where

I, i specifies the bit number and k the channel number. The eight input-level terminals and associated iot-pulse terminals are:

Channel

(k)

Data-Bit

Input

Associated iot Input

0

1

2

3

4

5

6

7

E

H

K

M

S

U

W

Y

T

V

X

Z

F

J

L

N

65

Information Distributor (location

2Hl-3)

The Information Distributor presents the static data contained in the AC to an output device when the Device Selector commands the device to sample the 10. The signal polarities are:

-3 volts o vol ts

AC bit contains a

0

AC bit contains a

1

Eight groups of

18 outputs are available in the ID. The module driving the output bus is a

Type

1690 or

1685

Bus Driver supplying up to

15 ma at

0 or -3 volts. All eight groups must share the bus.

Connections to the IDare made at three taper-pin terminal blocks,

2H1, 2H2, 2H3.

Each block has 3 columns of

20 terminals each. Each column represents a group; the first

18 terminals (A-U) in the column represent AC bits

0-17 and the last two (V, W) the bipolar bit

12 in the Memory Buffer. V and W may be used to select a subdevice. The terminals are ti ed together horizonta II y to form

20 rows.

Input-Output Skip Facility (location 2H06)

There are 8 inputs to Input-Output Skip. The iot pulses from the Device Selector strobe an input line and if a logic condition is present, the instruction following the iot will be skipped.

The conditions for skipping are:

-3 vol ts o vol ts skip do not skip

The iot skip pulse must occur at event time

1 •

The lOS consists of a Capacitor-Diode Gate, Type

4129.

The input connections are:

10

Device

Input

Connection

Device

Selector

Pulse

Connection

F

J

L

N

T

V

X

Z

E

H

K

M

S

U

W

Y

66

13 ADDRESS LINES

(-3VOLTS =1,0 VOLTS =0)

..-

~

18 DATA LINES

(-3VOLTS=1, 0 VOLTS=O)

..-

~

DATA

INTERRUPT

CONTROL

DATA INTERRUPT REQUEST.-.

(-3VOLTS=REQUEST)

--

18 DATA LINES

(-3 VOLTS=O, 0 VOLTS=1)

--

.-.

DATA DIRECTION

(-3 VOLTS = DATA OUT,

-

..-

~

ADDRESS ACCEPTED

PULSE

....

..

(a) DIC SIGNALS

DATA INTERRUPT

REQUEST

- -.....

3.5 J.! SEC --1>1'<1---3.5

I-!

SEC

-~I>J'WI

MINIMUM MAXIMUM

ACKNOWLEDGEMENT

TIME

ADDRESS ACCEPTED - - - - - - - - - - -..

U

TIME TO AVOID

ANOTHER INTERRUPT f4'-2.0

I-!

SEC--t>J

TRANSFER

D~PULSE--------------------~U

(IN EXTERNAL DEVICE)

(b) Die TIMING

Figure 27 Data Interrupt Control signals and timing

67

Program Interrupt Control (location 2H05)

Eleven Program Interrupt lines are available. Anyone of the 11 signars may cause an interruption of a program. All signals are identical; the polarities are:

-3 vol ts

Oval ts interrupt the program no effect

The connections from

10 devi ces wh ich request program interrupt are made to modufe 2H05 at pins -E, F

I

H,

J,

S, T, U, W, X, Y, and Z.

Data Interrupt Control (location 2E13)

The signal levels associated with the DI are shown in Figure 27. In transferring data, the

Memory Address is first transmitted to the Memory Address Register on 13 I ines from the external source. Data is next transferred to or from the MB on 18

+

18 lines.

Incoming data is received from 18 lines and placed in the Memory Buffer and on into Memory.

Outgoing data from the core memory addressed is transferred to the Memory Buffer and appears on 18 lines fC?rsampling by the

10 device.

68

Octal Mnemonic

Code Code

00 cal Y

04

10 doc Y jms Y

14 dzm Y

20

24

30 lac Y xor Y add Y

34 tad Y

40

44 xct Y isz Y

50

54 and Y sad Y

60

76 imp Y law N

APPENDIX 1

TABLE A.1. MEMORY REFERENCE INSTRUCTIONS

Time

(jJsec)

16

8

8

16

16

16

16

8+

16

16

16

16

16

16

Name Operation

Co II Subroutine

Y is ignored jms 20 if bit 4=0, jmsi 20 if bit 4=1 .

Deposit AC

Jump to sub routine

Deposit zero in memory

C(AC) =) C(Y)

C(PC) =) C(y), ),

Y + 1 =) C(PC)

Load AC

Exclusive OR

Add (one

'5 complement)

Two's add (two's complement)

Execute

Index and skip if zero

AND

Skip if AC and Y differ

Jump o

=) C(Y)

C(Y)

=> C(AC)

C(AC)-¥-C(Y) => C(AC)

C(AC) + C(y)

C(AC) + C(y)

If C(AC) = C(Y), then

C(PC) + 1 =) C(PC)

Y =) C(PC)

=) C(AC)

=) C(AC)

C(y) + 1 =) C(y)

I

if C(y) + 1 = 0, then

C(PC) + 1 =) C(PC)

C(AC)

A

C(y) =) C(AC)

Load a Word

1 =)

C(A~_4)'

N => C(A 5-17)

A-l

Octal

Code

740000

740000

740001

740002

740004

750004

740010

742010

740020

742020

740040

740200

741200

741100

740100

741400

740400

741000

744000

744002

750000

741001 rtr hit sza sna spa sma sfl snl skp cll stl cia clc

APPENDIX 2

TABLE A.2. OPERATE INSTRUCTIONS

Mnemonic

Code

Name

Operation oas las ral opr nop cma cml rtl rar

Operate

No Operation

Complement

Complement Link

Inclusive OR ACS

Load AC from Switches

Rotate AC +

Link left one place

Rotate AC left twice

Rotate AC + Link right one place

Rotate AC right twice

Halt

Skip on zero AC

Skip on non-zero AC

Skip on positive AC

Skip on negative AC

Skip on zero Link

Skip on non-zero Link

Skip, unconditional

Clear Link

Set the Link

Clear AC

Clear and Complement AC

A-2

None

None

C(AC)

=)

C(AC)

C(L)

=)

C(L)

C(ACS) V C(AC)

=)

C(AC)

C(AC) Switches)

=>

C(AC)

C(AC.)

1

=>

C(L) - )

C(AC. 1)'

C(A~6)'

C(AC 0)

=)

L)

Same as two ral instructions

C(AC.)

C(L)

C(AC

J>

=)

C(AC. 1)'

e(k-ca)'

1+

17

) =>

L)

Same as two rar instructions

0=>

RUN

Skip if C(AC)

= positive zero

Skip if C(AC)

1=

positive zero

Skip if C(AC

O

) = 0

Skip if C(AC

O

)

-=

1

Skip if C(L)

= 0

Ski p if C(L)

=1

Always skip

0=>

C(L)

1

=>

L

0=>

C(AC)

-0 => C(AC)

APPENDIX 3

TABLE A.3. BASIC lOT INSTRUCTION GROUP

/rnterrupt iof=700002 ion=700042

/IO Equipment iors=700314

/turn off interrrupt

/turn on interrupt

/read status of io equipment

/Clock clsf=700001 clof=7oooo4 clon=700044

/skip if clock flag is 1

/turn off clock, clear clock flag

/turn on clock, clear clock flag

/paper tape reader rsf=700101 /skip if reader flag 1s a 1 rsa=700104 /select reader for alphanumerlc,clear reader flag rsb=700144 /select reader for bry, clear reader flag rrb=700112 /read the reader buffer into AC, clear reader flag

/paper tape punch psf=700201 /skip if punch flag 1s a 1 pls=700206 /load punch buffer and select punch, clear punch flag pcf=700202 /clear punch flag

/Keyboard input from teleprinter ksf=700301 /skip if keyboard flag is a 1 krb=700312 /read the keyboard buffer into the AC, clear keyboard flac

/Teleprinter tsf=7004o1 tls=7004o6 tcf=7004o2

/skip if teleprinter flag is a

/clear the teleprinter flag

1

/load teleprinter buffer and select, clear teleprinter

/Display type 30A dsf=700501 /skip if display flag is a

1 dls=700506 /load display buffer and select, clear display flag dcf=700502 /clear display flag flag

/Display type 30D dsf==700501 dcf=7006o1 dxl=700506 dxs;=700S46 dyl;=7oo606 d v s;=7oo646 dlo=700706

!skip if display flag 1s a

1

(light pen)

!clear display flag

/load x co-ordinate

/load x co-ordinate and select

/load y co-ordinate

/load y co-ordinate and select

/load brightness register

A-3

TABLE A.3. BASIC lOT INSTRUCTION GROUP (continued)

/Magnetic tape mci=707001 mrs=707012 mli=707005 msc=707101 mSi=707201 msf=707301 type 54

/clear tape instruction and character buffer

/read tape status into AC

/load instruction buffer

/skip if character is present for reading

/clear interrupt flag and select interrupt

/ skip if the tape flag is a 1 (end of record) mrl=707112 mrm=707202 mrr=707302

/clear AC, read character buffer into AC left

/clear character buffer

/read character buffer into AC middle

/clear character buffer

/read character buffer into AC right

/clear character buffer

/write a character from AC left

/write a character from AC middle

/write a character from AC right mwl=707104 mwm=707204 mwr=707304

ICard reader crsf=706701 crsa=706704 crsb=706744 crrb=706712

ICard punch cpsf=706401 cpse=706444 cplr=706406 cpcf=706442

/Line printer

Ipsf=706S01

Ipcf=706S02

Ipld=706S42

Ipse=706S06

1ssf=706601

Iscf=706602

Isls=706606 start

/skip if reader character flag is a 1

/select card reader for alphanumeric

/select card reader for binary

/read card column buffer into AC

/skip if the card punch flag is a 1

/select a card, set card punch flag

/load row buffer, clear punch flag

/clear punch flag

/skip if

/load the printin~ flag is a 1

/clear printing flag printing buffer

/select printing, clear printing flag

/skip if spacing flag is a 1

/clear spacing flag

/load spacing buffer and select spacing, clear spacing fIa;

A-4

5

6

7

8

9

2

3

4

10

11

12

13

14

15

16

TABLE A.3.1 IORS COMMAND BIT ASSIGNMENTS AND PROGRAM INTERRUPT CONNECTIONS

IORS

Bit

Device Program

Interrupt

Connected

Status if a 1

0 Prog. Interrupt

Tape Reader Flag

Tape Punch Flag

Keyboard Flag

Teleprinter Flag

Display Flag

Clock Flag

Clock Status

Magnetic Tape Flag

Card Reader Flag

II II II

II II II

II

II II

Card Punch Flag

II II II x x

Line Printer Printing Flag x

Line Printer Space Flag x x x x x x x x x

Prog interrupt is on

Reader buffer has a character

Punching is complete, punch is available

Keyboard buffer has a character

Character has been printed, and is available

Light pen flag is a one

Clock has overflowed

Clock counting is enabled

End of record

Card column is available

Card is at reading station

Card Malfunction

End of Fi Ie button is pressed

Punch buffer is available to load

Card ma I function

Pri nti ng is compl eted

Spacing is completed

A-5

APPENDIX 4

TABLE A.4.1 FlO-DEC CODE

High order bits

01 10 a

A 61 b B 62 c C d D e

E f F g

G

63

64

65

66

67 h H

70 i j

I

J

4i k K

42

1 L

43 m

M

44 n N

45 o a

46 p

P 47 q

Q r

R s

50

51

S 22 t T

23 u v u v

24

25 wW

26 xX

27 yY

30 z Z

31 o

-+

20

1

11

01

2

I

02 j u.:>

<+

.J v""t

5 V 05

6

1\

06

7

8

l

<

07

10

9 t

11

/ ?

21

,

=

33

• x

73

- +

54

J

55 l 57 stop code lower case upper case black red tab backspace carriage return space

Low order bits

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

J...1..01

1110

1111

13

72

74

34

35

36

75

77

00

4()

- I

56

00 space

1 tI

2

I

3 -

4

::>

5

V

6

1\

7

<

8

>

9 t stop code delete punches seventh channel

A-6 a

-+

/ ? s S t

T u U vV wW xX yY z

Z

,

= black red tab

• j

J k K

1 L mM n N o 0 p

P q Q r R

(

L

11 a

A b B c C d D e E f

F g G h H i

I lower case

• x

- + upper case

)

J backspace car ret

TABLE A.4.2 TELETYPE CODE

High order bits

01 10

Low order bits

00

000

001

010

011

100

101

110

T 5 car ret o

9 space

H

#

N

, line feed

E 3

L )

Z

II

R 4

G

&

I

8

P 0

C

11

D

~

J

I

B ? figures

S bell

U

7

Y 6

Q

1

F 1

A -

W 2

K (

111

M

V

X / letters letters

37

32

36

1.1

07

06

03

15

35

12

24

01

34

17

31

27

25

21

30

23

16

22

20

26

13

05

14

A

B c

D

E

F

G

H

I

J

K

L

M

N

S

T u

V

W

X

Y

Z

0

P

Q

R space

04 line feed 10 figures

33

9

~

0

1

2

3

4

5

6

7 e

?

$ bell

&

#

I

,

/

I

0

II carriage return

25

34

14

03

36

11

07

06

15

35

31

20

12

01

30

23

16

22

24

13

05

32

17

27

26

21

02

A-7

A

61

T

23 u

24

V

25 w

26

X

Y

27

30

Z 31 a

12

1 01

2 02

3

03

4 04

5

05

6 06

B

C

D

E

F

62

~~

65

66

G

H

67

70

I

71

J

41

K

42

L

M

N

0 p

Q

R

S

43

44

45

46

47

50

51

22

7

07

8

10

9

11

+

60

-

40

/

21

=

13

,

.$

33

53

1

73

14 t 34

54

)

74 blank 00

TABLE A.4.3 CARD READER CODE

High order bits

00 01 10

Low order bits

0000 blank

0001

0010

0011

0100

1

2

3

4

/

S

T

U

J

K

L

M

0101

0110

0111

5

6

V

W

X

N

0

P

1000

1001

7

() Y

Z

Q

R

1010

1011

1100

9

0

=

[if]

1

[@J

, t

[ %J

~

..

:~ no punch

1

2

3

4

5

6

7

8

9

8-3

8-4

TABLE 3a. HOLLERITH CARD CODE

Zone digit blank

1

2

3

4

5

6

7

8

9

=

I

[ #J [email protected] no zone

12

E

F

G

H

I

+ l

A

&J

B c

D

) 10]

11

J

K

L

M

N

0

P

Q

R

~

.-

0

0

/

S

T

U z

, t

V w

X y

[ %J

11

+

[&J

A

B

C

D

E

F

G

H

I

)

[a]

A-8

A

B

C

D

.L,

F

G h

I

J

K

L

Ivl

N

0 p

Q

R

S

47

50

51

22

T

23 u

24 v

25

\~

26 x

27 y

30

61

62

63

64

65

66

67

70

71

41

42

43

44

45

46

Z 31 a

20

1 01

2 02

3

03

4

04

5

05

6 06

7

07

() 10

-

-

9

11

0

40

/ 21

I

12

:)

14 v

15

1\

16

\I

~

32

,

>

34 t

35

36

<

17

?

37

~

52

=

53 x

72

)

(

13

54

55

57

+

60

33 t~

J

75

[

77

56 space

00

I 76

TABLE A.4.4 HIGH-SPEED LINE PRINTER CODE i-iigh order bi ts

00

01

10

Low order bits

0000

0001

0010

0011

0100 space

1

2

3

4

0

/

S

T

U

J

K

L fv1

0101

0110

5

6

V w

N a

0111

1000

7

8

X y

P

Q

1001

9

Z

II

R

1010

1U11

~

=

1100

1101

:) v

,

> t )

1110

~

1111

1\

,

?

(

A-9

+

]

I

(

I x

F

G

H

A

B

C

D

E

11

APPENDIX 5

READ-IN MODE SEQUENCE

A5.1 GENERAL

The initial data input to PDP-4 is made using the keys and switches on the operator console. A small program read in manually can be used to read in a somewhat larger program from perforated tape. An example of such a routine is given below. It can also be used to read in other programs from perforated tape.

Manually set the read-in loader into the machine by means of the ADDRESS and

ACCUMULATOR switches and the DEPOS

IT

key on the console. When the manual program has been establ ished, load the tape reader, set the ADDRESS switches to enter address, and operate the START key. The manual loader starts at 7770 and automatically transfers to the perforated tape loader when finished. The program keeps track of check sum, and halts at

7755 if an error is detected.

A5.2 MANUAL LOADER

The routine is loaded using the toggle switches on the console. Execution starts at register 7770. Since the subroutine to read one binary word always gives a read tape command after reading the buffer, the imp instruction at the end of the tape must be followed by a dummy last word if the user wishes the tape to stop upon termination of read (necessary to prevent reader chatter when readi ng block format tapes).

Location

Octal Code

Mnemonic

7762/r,

7763/

0

700101

0 rsf

7764/

607763 imp i

7765/

7766/

7767/

7770/

700112

700144

627762

700144 rrb r~b imp i r rsb

7771/g,

107762 jms r

7772/

47775 dac out

Remarks

/read one binary word

/wait for word to come in

/ read buffer

/ read another word

/exit subroutine

/enter here, start reader going

/get next binary word

A-10

Location

7773/

7774/

7775;but,

7776/

Octal Code

407775

107762

0

607771

Mnemonic xct out jms r

0 imp g

Remarks

/ execute control word

/ get data word

/stored data word

/ continue

A5.3 PERFORATED-TAPE LOADER

The block format loader will read a block format binary tape of the following format: doc A

-N

N data words

Checksum

A is the address of the first data word

/ complement of number of data words in block

/data words

/sum of every word in block

The routine occupies register 7737 to 7760, and uses the manual loader subroutine to read each binary word. Upon completing a block, the computed check sum is compared with the read check sum and the loader halts if these differ. The block may be re-read by pulling the tape back to the beginning and pressing the CONTINUE switch on the console.

Location

7737/a, b,

Mnemonic rsb jms r doc s xct s doc cks jms r doc out add cks dac cks

Ims r

/Ioop

Remarks

/block format loader

A-l1

Location s,

Mnemonic isz ou t imp s sad cks imp a hit imp

0-1 xx

ISZ S imp b

Remarks

I

check count, last word read is check sum

Isum

checks, continue

Istop

on check sum error lout

A-12

APPENDIX 6

PDP-4 ASSEMBLER PROGRAM

A6.1 GENERAL

The characteristics of the MACRO assembler program are defined here to provide the background necessary to understand the programming examples in this manual. A separate manua I is avai lable at· DEC which describes the program and explains its use in detai

I .

A6.2 CHARACTER SET

The MACRO character set includes digits

0 through

9, letters a through z, and the following punctation characters:

Punctation Characters

+ plus

1\

V

(

) minus

~ space and or left parenthesis right parenthesis

Meaning add values subtract values add values combine values by logical AND combine values by INCLUSIVE OR enc lose constant word period enc lose constant word has va lue of current address

I

comma assign address tag

= equal sign

/

J

-+I slash carriage return tab overbar assign symbol on left of

= begin comments; set curr~nt address termination character term ination character

The characters £l., variable indicator

J

,and

-.j are used for invisible characters.

A-13

A6.J NUMBERS

Any sequence of digits delimited on the left and right by a punctuation character.

A6.4 SYMBOLS

Any sequence of letters or digits, the first of which must be a letter. Symbols may be any length, but all characters over six are ignored.

'Value symbols' are those symbols which have a numerical value assigned to them, either in the permanent symbol table, or during assembly. Value symbols may be assigned by the use of a comma, indicating the symbol to the left of the comma is an address tag; or by an equals sign, indicating the symbol to the left of the equals sign is to be assigned the value of the word to the right of the equals sign.

Example: a, b

=

-1 c

= a

+ b dzm 100

A6.5 SYLLABLES

A syllable can take several forms. It can be a value symbol, a period (.), a flexowriter input pseudo-instruction ("flex" or "char"), or a constant (a word enclosed in parentheses).

Examples of syllables are: al

100 lz2 flex abc flex now

(add a

+

1) lac abcdef

A6.6 WORDS

A word is a string of syllables connected by the arithmetic operators plus, minus, space, AND or OR, delimited on the left by tab, carriage return, left parenthesis, or equals sign; and on the right by a tab or carriage return. A word may be a single number or symbol so delimited, or a string of symbols connected by the operators.

If the word is delimited on the left by an equals sign then the symbol to the left of the equal sign is assigned a value equal to that of the word. Otherwise, the word

A-14

is a storage word and will become part of the binary version of the program being assembled. The arithmetic operators, plus and space both mean add, while the operator minus means subtract.

Examples of words: sad K

J

lac a

J

1000-20

J

add b+2

J

imp

-2 a+b-c-2

J

J

lac (add a+ 1) ,/

A6.7 THE CHARACTER SLASH

V)

The slash has two meanings: if immediately preceded by a tab or cdrriage return then slash initiates a comment, which is terminated by the next tab or carriage return. If slash if preceded by a word, then the address part of the word indicates to MACRO the address into which the next instruction or data word will go. Normally, MACRO translates the first instruction or data word into register 20 and succeeding instructions or data words into succeeding registers. If the programmer wishes to break th is sequence or wishes to start translating into some register other than 20, then a slash may be used to set the new address.

A6.8 INDIRECT ADDRESSING

Indirect addressing is indicated by the symbol

II i" which has the valuE 20000.

Example: lac i abc

A6.9 THE CHARACTER PER IOD (.)

The character (.) has as its value the current address.

Example: dac. is equivalent to a, dac a

A6.10. PSUEDO - INSTRUCTIONS

A6.10.1 FLEXOWRITER INPUT PSUEDO INSTRUCTIONS

A-15

flex

ACJ:,8

.'6

The psuedo-instruction flex causes the (six -b it) Teletype codes for the three characters following the space

(l:l.)

to be read into one word which is taken as the value of the syllable. The code for the characterCC will go into bits 0 - 5 of the word, for into bits

6 -

11, and for

~ into bits 12 - 17. The code is a six-bit character, the first five of which are the Teletype code, the sixth a 1 for upper case or a 0 for lower case.

Example: flex

~ boy char l:l. z ~

The psuedo-instruction char causes the (six-bit) Teletype character

H to be read into the left, middle, or right six bits of the word, depending on whether Z is r, m, or 1.

Example: char

D. rO char l:::" la

A6.10.2 CONSTANTS

The MACRO assembly system has available a facility by which the program constants may be automatically stored. A constant must follow the rules for a word and is delimited on the left by a left parenthesis. The right delimiter may be a right parenthesis, carriage return, or tab. The value of the syllable

(ex: ) is the address of the register containing

<X

The constantCC wi

II be stored in a constants block at the end of the program, and the address of OC wi

II replace

Examples of the use of constants: add (1)

,j

lac (add z 1)

J

lac (-760000) ,; lac (fl exo abc) ,)

A6.10.3 START

The psuedo-instruction

II start" indi cates the end of the Engl ish tape. Instruction

" start A" must be followed by a carriage return. The "A" is the address at which execution of the program is to begin, and causes a imp A instruction punched at the end of the binary tape on pass 2.

A-16

A6.10.4 DECIMAL

The psuedo-instruction "decimal" tells MACRO to take all numbers as decimal.

A6.10.5 OCTAL

The psuedo-instruction "octal" tells MACRO to take all numbers as octal.

A-17

APPENDIX 7

MULTIPLY SUBROUTINE

IPDP-4 ones complement single precision multiplication subroutine

Icalling sequence:

Ilac

multiplier

lims

mult

Ilac

multiplicand

Ireturn; low order product in AC, high order product in mp5

/time

=

2,6 msec. for non-zero cases, approximatley 100 microsec. for zero

0 mult, 0 dzm mp5 sna imp mpz spa+cll-opr cma+cml-opr dac mpl xct i ml,Jlt sna imp mpz spa cma+cm I-opr dac mp2

~ lac (360000 ral dac mpsign lac (-21 dac mp3 mp4, lac mpl rar dac mpl lac mp5 spl+cll-opr tad mp2 rar dac mp5 isz mp3 imp mp4 mpsign, 0 dac mp5 lac mp 1 rer xct mpsign mpz, isz mul t imp i mult sta rt

A-18

APPENDIX 8

DIVIDE SUBROUTINE

IPDP--4 ones complement divide subroutine

Ica"ing

sequence:

Ilac

high order dIvidend

lims

divide

Ilac

low order dividend

Ilac

divisor

Ireturn; quot

0

In AC, rem. in dvd

0 if high dividend is

Igreater than divisor

I

no divide takes place and

L

=>

1

0

Time

=

301 msec. divi de, 0 spa+c II-opr cma+cm' --opr dac dvd xct i divide' dv5, dv4, dv 3, sp! ema dae quo ims dv5

0

/remainder has sign of dividend isz divide xct i divide sma+em I-opr cma+cml-opr jms dv4

0 cll tad

(1 dac dvs tad dvd isz divide spl imp i divide lac

(-22 dac dvl imp dv2 lac dvd ral doc dvd tad

dvs

spl dac dvd

A-19

dv2, lac quo ral doc quo isz dvl imp dv3 lac dv5 ral lac dvd spl cma doc dvd lac dv4 ral lac quo spl cma+c II-opr imp i divide start

A-20

»

I

I'V

I

Equipment

I

I(D eVlce

!

! and

I l

!

L_

Control)

:--

-

I

Perfcra ted·-

R r j

: Pedoroted-

I '

I

I Tape

.

P',",nc~

I

Pri nter" l

Keyboard

: Visual CRT

I

Display

-30A, D

I

L~~~~

__

Pen

IRelay

~~~~er

!High

Speed

I

[-----_.

Cord

--

Reader

Panels

I

Reqd.

I

I

-I

1

1

0

1

2

0

0

I

I

!

I

20

20

20

0

<1

50

0

0

TABLE A. 9 CHARACTERISTICS OF INPUT-OUTPUT EQU IPMENT

Within Main Console

DC Powe,

Dissi parion

(Wattsl

External to Main Console

! Added

I

(Pounds)

I

I

Maximum

I

Weight

Real Time Option

Distance

Requ i rements

ID IC DS

105

PIC

Size (Inches) from

I-O~

Conso I e

(Feet) Width Depth

Height

Weight

(Pounds)

.e

10

10

10

0

10

20

0

0

0 18 1 1 1 1

8

0

1

4

20 1/4 12 8 3/4

1

1

1

4

73/4 151/4 13

5 5 2 2 2 2

18 0 1 0 0 0

0

0

1 1

18 0

1

0 0 0

18 0 2

0 6

1 1

2

2 2

1

2 1 4

4

21 1/4

20

25 34

6

0 0

44

Approx.

7" long

0

25 663/4 31

25

30

14 3/4

48

0

61 1/4

-17

3"4

42

30

I 24 1/2

55

250

1/8

0

1100

150

Card

Punch

-

Magnetic

Tape System

Type 54

0

1

0

20

0

10

18

0

1 1 1

2

2 1 1

7.5 40

15 28

26

22

491/2

69

678

550

- ' - - -

18 l~

4

AC Power

Dissi potion

KVA

0.132

0.220

0.220

0,88

0

0

2,20

0,132

1 ,10

1 ,32

Watts

125

65

65

920

0

0

2300

40

1150

1380

~

2 n

33 554 432

67 108 864

134 217 728

268 435 456

536 870 912

1 073 741 824

2 147 483 848

4 294 967 296

8 589 934 592

17 179 869 184

34 359 738 368

68 719 476 736

137 438 953 472

274 877 906 944

549 755 813 888

1 099 511 627 776

2 199 023 255 552

4 398 046 511 104

8 796 093 022 208

17

592 186 044 416

35 184 372 088 832

70 368 744 177 66,1

140 737 ·488 355 328

281 474 976 710 656

562 949 953 421 312

1 125 899 906 842 634

2 251 799 813 985 248

4 503 599 627 370 496

9 007 199 254 740 992

18 014 398 509 481 984

36 028 797 018 963 968

72 057 594 037 927 936

144 115 188 075 855 872

288 230 376 151 711 744

576 460 752 303 423 488

1 152 921 504 606 846 976

1 024

2 048

4 096

8

192

16 384

32 768

65 536

131 072

262 144

524 288

1 048 576

2 097 152

4 194 304

8 388 608

16 777 216

32

64

128

256

512

2

4

8

16

5

6

7

8

9

28

29

30

31

32

24

25

26

27

19

20

21

22

23

14

15

16

17

18

10

11

12

13

0

1

2

3

4

44

45

46

47

48

40

41

42

43

33

34

35

36

37

38

39

57

58

59

60

53

54

55

56

49

50

51

52

APPEND IX 1'0

POWERS OF TWO

n

-2

1.0

0.5

0.25

0.125

0.062 5

0.031 25

0.015 625

0.007 812 5

0.003 906 25

0.001 953 125

0.000 976 562 5

0.000 488 281 25

0.000 244 140 625

0.000 122 070 312 5

0.000 061 035 156 25

0.000 030 517 578 125

0.000 015 258 789 062 5

0.000 007 629 394 531 25

0.000 003 814 697 265 625

0.000 001 907 348 632 812 5

0.000 000 953 674 316 406 25

0.000 000 476 837 158 203 125

0.000 000 238 418 579 101 562 5

0.000 000 119 209 289 550 781 25

0.000 000 059 604 644 775 390 625

0.000 000 029 802 322 387 695 312 5

0.000 000 014 901 161 193 847 656 25

0.000 000 007 450 580 596 923 808 125

0.000 000 003 725 290 298 461 914 062 5

0.000 000 001 862 645 149 230 957 031 25

0.000 000 000 931 322 574 615 478 515 625

0.000 000 000 465 661 287 307 739 257 812 5

0.000 000 000 232 830 643 653 869 628 906 25

0.000 000 000 116 415 321 826 934 814 453 125

0.000 000 000 058 207 660 913 467 407 226 562 5

0.000 000 000 029 103 830 456 733 703 613 081 25

0.000 000 000 014 551 915 228 366 851 806 640 625

0.000 000 000 007 275 957 614 183 425 903 320 312 5

0.000 000 000 003 637 978 807 091 712 951 660 156 25

0.000 000 000 001 818 989 403 545 856 475 830 078 125

0.000 000 000 000 909 494 701 772 928 237 915 039 062 5

0.000 000 000 000 454 747 350 886 464 118 957 519 531 25

0.000 000 000 000 227 373 675 443 232 059 478 759 765 625

0.000 000 000 000 113 686 837 721 616 029 739 379 882 812 5

0.000 000 000 000 056 843 418 860 808 014 869 689 941 406 25

0.000 000 000 000 028 421 709 430 404 007 434 844 970 703 125

0.000 000 000 000 014 210 854 715 202 003 717 422 485 351 562 5

0.000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25

0.000 000 000 000 003 552 713 678 800 500 929 355 621 337 890 625

0.000 000 000 000 001 776 356 839 400 250 464 677 810 668 945 312 5

0.000 000 000 000 000 888 178 419 700 125 232 338 905 334 472 656 2S

0.000 000 000 000 000 444 089 209 850 062 616 169 452 667 236 328 125

0.000· 000 000 000 000 222 044 604 925 031 308 084 726 333 668 164 062 5

0.000 000 000 000 000 111 022 302 462 515 654 042 363 166 834 582 031 25

0.000 000 000 000 000 055 511 151 231 257 827 021 171 513 417 041 015 625

0.000 000 000 000 000 027 755 575 615 628 913 510 590 791 708 520 507 812 5

0.000 000 000 000 000 013 877 787 807 814 456 755 215 395 854 260 253 906 2S

0.000 000 000 000 000 006 938 893 903 907 228 377 647 697 927 130 126 953 125

0,000 000 000 000 000 003 469 446 951 953 614 188 823 848 963 565 063 .\76 562 S

0.000 000 000 000 000 001 734 723 475 976 807 094 411 924 481 782 531 738 281

2~,

0.000 000 000 000 000 000 867 361 737 988 403 547 205 962 240 891 265 869 140

62~

A-22

F-45P1

100-

9/62

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