UPD78011F,78012F,78013F,78014F,78015F,78016F,78018F Data Sheet

UPD78011F,78012F,78013F,78014F,78015F,78016F,78018F Data Sheet

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

st

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas

Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

st

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

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DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

8-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, and 78018F are the products in the

µ

PD78018F subseries within the 78K/0 series.

Compared with the older

µ

PD78014 subseries, this subseries operates at lower voltage and provides a fuller set of ROM and RAM variations.

A one-time PROM or EPROM product

µ

PD78P018F capable of operating in the same power supply voltage range as of the mask ROM product and other development tools are also provided.

Functions are described in detail in the following User's Manual, which should be read when carring out design work.

µ

PD78018F, 78018FY Subseries User's Manual : U10659E

78K/0 Series Users Manual – Instruction : U12326E

FEATURES

Large on-chip ROM & RAM

Item

Product Name

µ

PD78011F

µ

PD78012F

µ

PD78013F

µ

PD78014F

µ

PD78015F

µ

PD78016F

µ

PD78018F

Program

Memory

(ROM)

8K bytes

16K bytes

24K bytes

32K bytes

40K bytes

48K bytes

60K bytes

Data Memory

Internal HighInternal

Speed RAM Expanded RAM

512 bytes –

Buffer RAM

32 bytes

1024 bytes

512 bytes

1024 bytes

Package

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14

×

14 mm)

64-pin plastic LQFP (12

×

12 mm)

External memory expansion space : 64K bytes

Minimum instruction execution time can be varied from high-speed (0.4

µ s) to ultra-low-speed (122

µ s)

I/O ports: 53 (N-ch open-drain : 4)

8-bit resolution A/D converter : 8 channels

Serial interface : 2 channels

Timer : 5 channels

Supply voltage : V

DD

= 1.8 to 5.5 V

APPLICATION FIELDS

Cellular phone, pager, VCR, audio, camera, home appliances, etc

Document No. U10280EJ2V1DS00 (2nd edition)

Date Published June 1998 N CP(K)

Printed in Japan

The information in this document is subject to change without notice.

The mark shows major revised points.

© 1994

2

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

ORDERING INFORMATION

Part Number Package

µ

PD78011FCW-

×××

µ

PD78011FGC-

×××

-AB8

µ

PD78011FGK-

×××

-8A8

µ

PD78012FCW-

×××

µ

PD78012FGC-

×××

-AB8

µ

PD78012FGK-

×××

-8A8

µ

PD78013FCW-

×××

µ

PD78013FGC-

×××

-AB8

µ

PD78013FGK-

×××

-8A8

µ

PD78014FCW-

×××

µ

PD78014FGC-

×××

-AB8

µ

PD78014FGK-

×××

-8A8

µ

PD78015FCW-

×××

µ

PD78015FGC-

×××

-AB8

µ

PD78015FGK-

×××

-8A8

µ

PD78016FCW-

×××

µ

PD78016FGC-

×××

-AB8

µ

PD78016FGK-

×××

-8A8

µ

PD78018FCW-

×××

µ

PD78018FGC-

×××

-AB8

µ

PD78018FGK-

×××

-8A8

Remark

×××

indicates a ROM code suffix.

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14

×

14 mm)

64-pin plastic LQFP (12

×

12 mm)

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14

×

14 mm)

64-pin plastic LQFP (12

×

12 mm)

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14

×

14 mm)

64-pin plastic LQFP (12

×

12 mm)

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14

×

14 mm)

64-pin plastic LQFP (12

×

12 mm)

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14

×

14 mm)

64-pin plastic LQFP (12

×

12 mm)

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14

×

14 mm)

64-pin plastic LQFP (12

×

12 mm)

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14

×

14 mm)

64-pin plastic LQFP (12

×

12 mm)

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

78K/0 SERIES DEVELOPMENT

The following shows the products organized according to usage. The names in the parallelograms are subseries names.

78K/0

Series

80-pin

80-pin

Products in mass production

Products under development

Y subseries products are compatible with I

2

C bus.

100-pin

100-pin

100-pin

100-pin

80-pin

80-pin

80-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

42/44-pin

Control

µ

µ

µ

PD78075B

PD78078

PD78070A

µ

PD780058

µ

PD78058F

µ

PD78054

µ

PD780034

µ

PD780024

µ

PD78014H

µ

PD78018F

µ

PD78014

µ

PD780001

µ

PD78002

µ

PD78083

µ

PD78075BY

µ

PD78078Y

µ

PD78070AY

µ

PD780018AY

µ

PD780058Y

Note

µ

PD78058FY

µ

PD78054Y

µ

PD780034Y

µ

PD780024Y

µ

µ

µ

PD78018FY

PD78014Y

PD78002Y Basic subseries for control

µ

On-chip UART, capable of operating at low voltage (1.8 V)

64-pin

64-pin

Inverter control

µ

PD780964

µ

PD780924

FIP

TM

drive

On-chip inverter control circuit and UART. EMI-noise was reduced.

100-pin

100-pin

80-pin

80-pin

100-pin

100-pin

100-pin

PD780228

µ

PD78044H

µ

PD78044F

LCD drive

µ

PD780308

µ

PD78064B

µ

PD78064

µ

µ

PD780308Y

PD78064Y

Basic subseries for driving FIP, Display output total: 34

Basic subseries for driving LCDs, On-chip UART

IEBus

TM

supported

µ

PD78098B

µ

PD78098

80-pin

Meter control

µ

PD780973

On-chip controller/driver for automobile meters

64-pin

LV

µ

PD78P0914

On-chip PWM output, LV digital code decoder, and Hsync counter

Note Under planning

3

4

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

The following lists the main functional differences between subseries products.

Function

ROM

Capacity

Subseries Name

Control

µ

PD78075B 32K-40K

µ

PD78078 48K-60K

µ

PD78070A –

µ

PD780058 24K-60K

µ

PD78058F 48K-60K

µ

PD78054 16K-60K

µ

PD780034 8K-32K

µ

PD780024

µ

PD78014H

µ

PD78018F 8K-60K

µ

PD78014 8K-32K

LCD drive

µ

PD780001 8K

µ

PD78002

µ

PD78083

8K-16K

Inverter

µ

PD780964 8K-32K control

µ

PD780924

FIP drive

µ

PD780208 32K-60K

µ

PD780228 48K-60K

µ

PD78044H 32K-48K

µ

PD78044F 16K-40K

µ

PD780308 48K-60K

µ

PD78064B 32K

µ

PD78064 16K-32K

IEBus

µ

PD78098 supported

µ

PD78098B

40K-60K

32K-60K

Meter control

µ

PD780973 24K-32K

LV

µ

PD78P0914 32K

Timer

8-bit 10-bit 8-bit

8-bit 16-bit Watch WDT A/D A/D

D/A

Serial Interface

4ch 1ch 1ch 1ch 8ch – 2ch 3ch (UART: 1ch)

2ch

3ch

2ch 1ch 1ch

2ch

2ch

3ch

6ch

1ch

1ch

1ch

1ch 1ch

1ch 1ch

1ch 1ch

– 1ch

8ch

8ch

8ch

5ch

8ch

8ch

8ch –

2ch 1ch 1ch 1ch 8ch –

2ch 3ch (time division UART: 1ch)

3ch (UART: 1ch)

3ch (UART: 1ch, time division 3-wire: 1ch)

2ch

– –

1ch

8ch

1ch

1ch (UART: 1ch)

3ch Note – 1ch – 8ch – 2ch (UART: 2ch)

2ch

1ch

2ch 3ch (UART: 1ch)

2ch (UART: 1ch)

2ch

I/O

88

61

68

69

51

53

2ch

– 3ch (time division UART: 1ch) 57

2ch (UART: 1ch)

39

53

33

47

74

72

68

69

56

54

V

DD

MIN.

External

Value Expansion

1.8 V

2.7 V

1.8 V

2.7 V

2.0 V

1.8 V

1.8 V

2.7 V

1.8 V

2.7 V

2.7 V

4.5 V

2.7 V

2.0 V

2.7 V

4.5 V

4.5 V

Note 10-bit timer: 1 channel

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

OVERVIEW OF FUNCTION (1/2)

Item

µ

PD78011F

µ

PD78012F

µ

PD78013F

µ

PD78014F

µ

PD78015F

µ

PD78016F

µ

PD78018F

Product Name

Internal memory

ROM

High-speed

RAM

Expanded

RAM

Buffer RAM

Memory space

8K bytes 16K bytes

512 bytes

24K bytes 32K bytes 40K bytes

1024 bytes

512 bytes

General-purpose registers

32 bytes

64K bytes

8 bits

×

32 registers (8 bits

×

8 registers

×

4 banks)

Minimum instruction execution time

On-chip minimum instruction execution time cycle modification function

When main system clock selected

When subsystem clock selected

0.4

122

µ

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s (at 32.768 kHz operation) s (at 10.0 MHz operation)

48K bytes 60K bytes

1024 bytes

Instruction set

I/O ports

A/D converter

Serial interface

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits,16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, boolean operation)

• BCD correction, etc.

Total

• CMOS input

• CMOS I/O

• N-channel open-drain I/O

: 53

: 0 2

: 47

(15 V withstand voltage) : 0 4

• 8-bit resolution

×

8 channels

• Operable over a wide power supply voltage range: AV

DD

= 1.8 to 5.5 V

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable: 1 channel

• 3-wire mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel

Timer

Timer output

Clock output

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

3 (14-bit PWM output

×

1)

39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock: 10.0 MHz operation), 32.768 kHz (at subsystem clock: 32.768 kHz operation)

Buzzer output

Maskable Vectored interrupt sources

Non-maskable

2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: 10.0 MHz operation)

Internal : 8

External : 4

Internal : 1

Software

1

5

6

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

OVERVIEW OF FUNCTION (2/2)

Item

Product Name

Test input

Supply voltage

Operating ambient temperature

Package

µ

PD78011F

µ

PD78012F

µ

PD78013F

µ

PD78014F

µ

PD78015F

µ

PD78016F

µ

PD78018F

Internal : 1

External : 1

V

DD

= 1.8 to 5.5 V

T

A

= –40 to +85

°

C

• 64-pin plastic shrink DIP (750 mil)

• 64-pin plastic QFP (14

×

14 mm)

• 64-pin plastic LQFP (12

×

12 mm)

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

TABLE OF CONTENTS

1.

PIN CONFIGURATION (TOP VIEW) .......................................................................................................

8

2.

BLOCK DIAGRAM ................................................................................................................................... 11

3.

PIN FUNCTIONS ...................................................................................................................................... 12

3.1

PORT PINS ........................................................................................................................................................ 12

3.2

PINS OTHER THAN PORT PINS ...................................................................................................................... 13

3.3

PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ............................................. 15

4.

MEMORY SPACE .................................................................................................................................... 17

5.

PERIPHEL HARDWARE FUNCTION FEATURES ................................................................................ 19

5.1

PORTS ............................................................................................................................................................... 19

5.2

CLOCK GENERATOR ....................................................................................................................................... 20

5.3

TIMER/EVENT COUNTER ................................................................................................................................ 21

5.4

CLOCK OUTPUT CONTROL CIRCUIT ............................................................................................................ 23

5.5

BUZZER OUTPUT CONTROL CIRCUIT ........................................................................................................... 23

5.6

A/D CONVERTER .............................................................................................................................................. 24

5.7

SERIAL INTERFACES ...................................................................................................................................... 24

6.

INTERRUPT FUNCTIONS AND TEST FUNCTIONS .............................................................................. 26

6.1

INTERRUPT FUNCTIONS ................................................................................................................................. 26

6.2

TEST FUNCTIONS ............................................................................................................................................ 29

7.

EXTERNAL DEVICE EXPANSION FUNCTIONS .................................................................................... 30

8.

STANDBY FUNCTIONS .......................................................................................................................... 30

9.

RESET FUNCTIONS ................................................................................................................................ 30

10. INSTRUCTION SET ................................................................................................................................. 31

11. ELECTRICAL SPECIFICATIONS ............................................................................................................ 34

12. CHARACTERISTIC CURVE (REFERENCE VALUES) ........................................................................... 61

13. PACKAGE DRAWINGS ........................................................................................................................... 62

14. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 65

APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 68

APPENDIX B. RELATED DOCUMENTS ...................................................................................................... 70

7

8

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

1. PIN CONFIGURATION (Top View)

64-Pin Plastic Shrink DIP (750 mil)

µ

PD78011FCW-

×××

, 78012FCW-

×××

, 78013FCW-

×××

,

µ

PD78014FCW-

×××

, 78015FCW-

×××

, 78016FCW-

×××

,

µ

PD78018FCW-

×××

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P25/SI0/SB0

P26/SO0/SB1

P27/SCK0

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/PCL

P36/BUZ

P37

V

SS

P40/AD0

P41/AD1

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

V

SS

28

29

30

31

32

24

25

26

27

20

21

22

23

16

17

18

19

12

13

14

15

8

9

10

11

4

5

6

7

1

2

3

X2

V

DD

P03/INTP3

P02/INTP2

P01/INTP1

P00/INTP0/TI0

RESET

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P63

P62

P61

P60

P57/A15

P56/A14

AV

REF

AV

DD

P17/ANI7

P16/ANI6

P15/ANI5

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

AV

SS

P04/XT1

XT2

IC

X1

37

36

35

34

33

41

40

39

38

45

44

43

42

49

48

47

46

53

52

51

50

57

56

55

54

61

60

59

58

64

63

62

Cautions 1. Always connect the IC (Internally Connected) pin to V

SS

directly.

2. Always connect the AV

DD

pin to V

DD

.

3. Always connect the AV

SS

pin to V

SS

.

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

64-Pin Plastic QFP (14

×

14 mm)

µ

PD78011FGC-

×××

-AB8, 78012FGC-

×××

-AB8, 78013FGC-

×××

-AB8,

µ

PD78014FGC-

×××

-AB8, 78015FGC-

×××

-AB8, 78016FGC-

×××

-AB8,

µ

PD78018FGC-

×××

-AB8

64-Pin Plastic LQFP (12

×

12 mm)

µ

PD78011FGK-

×××

-8A8, 78012FGK-

×××

-8A8, 78013FGK-

×××

-8A8,

µ

PD78014FGK-

×××

-8A8, 78015FGK-

×××

-8A8, 78016FGK-

×××

-8A8,

µ

PD78018FGK-

×××

-8A8

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/PCL

P36/BUZ

P37

V

SS

P40/AD0

P41/AD1

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

8

9

6

7

3

4

5

1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

2 47

46

45

44

43

42

41

40

10

11

12

13

14

39

38

15 34

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

33

37

36

35

IC

X1

X2

V

DD

P11/ANI1

P10/ANI0

AV

SS

P04/XT1

XT2

P03/INTP3

P02/INTP2

P01/INTP1

P00/INTP0/TI0

RESET

P67/ASTB

P66/WAIT

Cautions 1. Always connect the IC (Internally Connected) pin to V

SS

directly.

2. Always connect the AV

DD

pin to V

DD

.

3. Always connect the AV

SS

pin to V

SS

.

9

10

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

A8 to A15

AD0 to AD7

: Address Bus

: Address/Data Bus

ANI0 to ANI7 : Analog Input

ASTB : Address Strobe

AV

DD

AV

REF

AV

SS

BUSY

:

Analog Power Supply

: Analog Reference Voltage

: Analog Ground

: Busy

BUZ

IC

: Buzzer Clock

: Internally Connected

INTP0 to INTP3 : Interrupt from Peripherals

P00 to P04 : Port0

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

: Port1

: Port2

: Port3

: Port4

: Port5

: Port6

PCL

RD

RESET

: Programmable Clock

: Read Strobe

: Reset

SB0, SB1 : Serial Bus

SCK0, SCK1 : Serial Clock

SI0, SI1

SO0, SO1

: Serial Input

: Serial Output

STB

TI0 to TI2

TO0 to TO2

V

DD

V

SS

WAIT

WR

X1, X2

XT1, XT2

: Strobe

: Timer Input

: Timer Output

: Power Supply

: Ground

: Wait

: Write Strobe

: Crystal (Main System Clock)

: Crystal (Subsystem Clock)

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

2. BLOCK DIAGRAM

TO0/P30

TI0/INTP0/P00

TO1/P31

TI1/P33

TO2/P32

TI2/P34

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/

EVENT COUNTER 1

8-bit TIMER/

EVENT COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

78K/0

CPU CORE

RAM

ROM

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

ANI0/P10 to

ANI7/P17

AV

DD

AV

SS

AV

REF

INTP0/P00 to

INTP3/P03

A/D CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

BUZ/P36

PCL/P35

CLOCK OUTPUT

CONTROL

V

DD

V

SS

IC

(V

PP

)

Remarks 1. Internal ROM & RAM capacity varies depending on the product.

2. ( ) :

µ

PD78P018F

PORT0

EXTERNAL

ACCESS

SYSTEM

CONTROL

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

P00

P01 to P03

P04

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

AD0/P40 to

AD7/P47

A8/P50 to

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1

XT2

11

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

3. PIN FUNCTIONS

3.1 PORT PINS (1/2)

Pin Name

P00

P01

P02

P03

P04

Note 1

P10 to P17

I/O

Input

Input/ output

Port 0

5-bit I/O port

Input only

Function

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used in software.

P24

P25

P26

P27

P20

P21

P22

P23

P30

P31

P32

P33

P34

P35

P36

P37

P40 to P47

Input

Input/ output

Input/ output

Input only

Port 1

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used in software.

Note 2

Port 2

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used in software.

Input/ output

Port 3

8-bit input/output port.

Input/output can be specified in 1-bit units.

When used as an input port, on-chip pull-up resistor can be used in software.

Input/ output

Port 4

8-bit input/output port.

Input/output can be specified in 8-bit unit.

When used as an input port, on-chip pull-up resistor can be used in software.

Test input flag (KRIF) is set to 1 by falling edge detection.

On Reset

Input

Input

Input

Input

Input

Input

Input

Dual-

Function Pin

INTP0/TI0

INTP1

INTP2

INTP3

XT1

ANI0 to ANI7

SI1

SO1

SCK1

STB

BUSY

SI0/SB0

SO0/SB1

SCK0

TO0

TO1

TO2

TI1

TI2

PCL

BUZ

AD0 to AD7

Notes 1. When using the P04/XT1 pins as an input port, set 1 to bit 6 (FRC) of the processor clock control register

(PCC). Do not use the on-chip feedback register of the subsystem clock oscillator.

2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, on-chip pull-up resistor is automatically unused.

12

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

3.1 PORT PINS (2/2)

P64

P65

P66

P67

P60

P61

P62

P63

Pin Name

P50 to P57

I/O

Input/ output

Input/ output

Function

Port 5

8-bit input/output port.

LED can be driven directly.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used in software.

Port 6

8-bit input/output port.

Input/output can be specified bit-wise.

N-ch open-drain input/output port.

On-chip pull-up resistor can be specified by mask option.

LED can be driven directly.

When used as an input port, on-chip pull-up resistor can be used in software.

On Reset

Input

Input

Dual-

Function Pin

A8 to A15

RD

WR

WAIT

ASTB

3.2 PINS OTHER THAN PORT PINS (1/2)

Pin Name

SB0

SB1

SCK0

SCK1

STB

BUSY

SI0

SI1

SO0

SO1

INTP0

INTP1

INTP2

INTP3

I/O

Input

Input

Output

Input

/output

Input

/output

Output

Input specified.

Function

External interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be

Falling edge detection external interrupt request input.

Serial interface serial data input.

Serial interface serial data output.

Serial interface serial data input/output.

Serial interface serial clock input/output.

Serial interface automatic transmit/receive strobe output.

Serial interface automatic transmit/receive busy input.

On Reset

Input

Input

Input

Input

Input

Input

Input

P27

P22

P23

P24

P26/SB1

P21

P25/SI0

P26/SO0

Dual-

Function Pin

P00/TI0

P01

P02

P03

P25/SB0

P20

13

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

3.2 PINS OTHER THAN PORT PINS (2/2)

XT2

V

DD

V

SS

IC

ANI0 to ANI7

AV

REF

AV

DD

AV

SS

RESET

X1

X2

XT1

Pin Name I/O

TI0

TI1

TI2

TO0

TO1

TO2

PCL

BUZ

AD0 to AD7

A8 to A15

RD

WR

WAIT

ASTB

Input

Output

Output

Output

Input

/output

Output

Output

Input

Output

Input

Input

Input

Input

Input

Function

External count clock input to 16-bit timer (TM0).

External count clock input to 8-bit timer (TM1).

External count clock input to 8-bit timer (TM2).

16-bit timer (TM0) output (shared as 14-bit PWM output).

8-bit timer (TM1) output.

8-bit timer (TM2) output.

Clock output (for main system clock, subsystem clock trimming).

Buzzer output.

Low-order address/data bus at external memory expansion.

High-order address bus at external memory expansion.

External memory read operation strobe signal output.

External memory write operation strobe signal output.

Wait insertion at external memory access.

Strobe output which latches the address information output at port 4 and port 5 to access external memory.

A/D converter analog input.

A/D converter reference voltage input.

A/D converter analog power supply. Connected to V

DD

.

A/D converter ground potential. Connected to V

SS

.

System reset input.

Main system clock oscillation crystal connection.

Subsystem clock oscillation crystal connection.

Positive power supply.

Ground potential.

Internal connection. Connected to V

SS directly.

Input

Input

On Reset

Input

Input

Input

Input

Input

Dual-

Function Pin

P00/INTP0

P33

P34

P30

P31

P32

P35

P36

P40 to P47

Input

Input

Input

Input

P50 to P57

P64

P65

P66

P67

P04

P10 to P17

14

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.

For the input/output circuit configuration of each type, refer to Figure 3-1.

Pin Name

P00/INTP0/TI0

P01/INTP1

P02/INTP2

P03/INTP3

P04/XT1

P10/ANI0 to P17/ANI7

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P25/SI0/SB0

P26/SO0/SB1

P27/SCK0

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/PCL

P36/BUZ

P37

P40/AD0 to P47/AD7

P50/A8 to P57/A15

P60 to P63

P64/RD

P65/WR

P66/WAIT

P67/ASTB

RESET

XT2

AV

REF

AV

DD

AV

SS

IC

2

16

16

11

8-A

5-A

8-A

5-A

8-A

10-A

Table 3-1. Input/Output Circuit Type of Each Pin

Input/output

Circuit Type

2

8-A

I/O

Input

Input/output

Recommended Connection when Not Used

Connected to V

SS

.

Individually connected to V

SS

via resistor.

5-A

8-A

5-A

5-E

5-A

13-B

5-A

Input

Input/output

Input

Connected to V

DD

or V

SS

.

Individually connected to V

DD

or V

SS via resisitor.

Individually connected to V

DD

via resistor.

Individually connected to V

DD

or V

SS

via resistor.

Individually connected to V

DD

via resistor.

Individually connected to V

DD

or V

SS

via resistor.

Leave open.

Connected to V

SS

.

Connected to V

DD

.

Connected to V

SS

.

Connected to V

SS

directly.

15

16

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Type 2

IN

Figure 3-1. Pin Input/Output Circuits

Type 10-A

pull-up enable data open drain output disable

Schmitt-Triggered Input with Hysteresis Characteristic

V

DD

V

DD

P-ch

P-ch

IN / OUT

N-ch

Type 5-A

pull-up enable data output disable input enable

Type 5-E

pull-up enable data output disable

Type 8-A

pull-up enable data output disable

V

DD

V

DD

P-ch

P-ch

IN / OUT

N-ch

V

DD

V

DD

P-ch

P-ch

IN / OUT

N-ch

Type 11

pull-up enable data output disable

Comparator

P-ch

N-ch

+

V

REF

N-ch

(Threshold Voltage) input enable

V

DD

V

DD

P-ch

P-ch

IN / OUT

Type 13-B

data output disable

Mask

Option

V

DD

IN / OUT

N-ch

V

DD

RD P-ch

Middle-High Voltage Input Buffer

V

DD

V

DD

P-ch

P-ch

IN / OUT

N-ch

Type 16

feedback cut-off

P-ch

XT1

XT2

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

4. MEMORY SPACE

The memory maps of the

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, and 78018F are shown in Figure

4-1 and 4-2.

Figure 4-1. Memory Map (

µ

PD78011F, 78012F, 78013F, 78014F)

FFFFH

Special Function Registers

(SFR) 256

×

8 Bits

FF00H

FEFFH

FEE0H

FEDFH

General-Purpose Registers

32

×

8 Bits

Internal High-Speed RAM

Note

Data

Memory

Space mmmmH mmmmH – 1

FAE0H

FADFH

FAC0H

FABFH

FA80H

FA7FH

Program

Memory

Space nnnnH + 1 nnnnH

Use Prohibited

Buffer RAM 32

×

8 Bits

Use Prohibited

External Memory nnnnH

1000H

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

Program Area

CALLF Entry Area

Program Area

CALLT Table Area

Internal ROM

Note

Vector Table Area

0000H

0000H

Note

Intermal ROM and internal high-speed RAM capacities vary depending on the product (refer to the table below).

Product Name

µ

PD78011F

µ

PD78012F

µ

PD78013F

µ

PD78014F

Intenal ROM End Address nnnnH

1FFFH

3FFFH

5FFFH

7FFFH

Internal High-Speed RAM

Start Address mmmmH

FD00H

FB00H

17

18

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Figure 4-2. Memory Map (

µ

PD78015F, 78016F, 78018F)

FFFFH

Special Function Registers

(SFR) 256

×

8 Bits

FF00H

FEFFH

FEE0H

FEDFH

General-Purpose Registers

32

×

8 Bits

Internal High-Speed RAM

Note

Data

Memory

Space mmmmH mmmmH–1

FAE0H

FADFH

FAC0H

FABFH

Use Prohibited

Buffer RAM 32

×

8 Bits nnnnH

Use Prohibited

Program Area

FA80H

FA7FH

1000H

0FFFH

Use Prohibited

CALLF Entry Area

F800H

Program

F7FFH

Memory

Space kkkkH kkkkH – 1

Internal Expanded RAM

Note

0800H

07FFH

Program Area

0080H

007FH

External Memory nnnnH + 1 nnnnH

CALLT Table Area

0040H

003FH

Internal ROM

Note

Vector Table Area

0000H

0000H

Note Intermal ROM, internal high-speed RAM, and internal expanded RAM capacities vary depending on the product (refer to the table below).

Product Name

µ

PD78015F

µ

PD78016F

µ

PD78018F

Intenal ROM End Address nnnnH

9FFFH

BFFFH

EFFFH

Internal High-Speed RAM

Start Address mmmmH

FB00H

Internal Expanded RAM

Start Address kkkkH

F600H

F400H

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

5. PERIPHERAL HARDWARE FUNCTION FEATURES

5.1 PORTS

The I/O port has the following three types

• CMOS input (P00, P04)

• CMOS input/output (P01 to P03, port 1 to port 5, P64 to P67)

• N-ch open-drain input/output(15V withstand voltage) (P60 to P63)

Total

Port 1

Port 2

Port 3

Port 4

Port Name

Port 0

Pin Name

P00, P04

P01 to P03

P10 to P17

P20 to P27

P30 to P37

P40 to P47

Port 5

Port 6

P50 to P57

P60 to P63

P64 to P67

: 2

: 47

: 4

: 53

Table 5-1. Functions of Ports

Function

Dedicated Input port

Input/output ports. Input/output can be specified bit-wise.

When used as an input port, pull-up resistor can be used in software.

Input/output ports. Input/output can be specified bit-wise.

When used as an input port, pull-up resistor can be used in software.

Input/output ports. Input/output can be specified bit-wise.

When used as an input port, pull-up resistor can be used in software.

Input/output ports. Input/output can be specified bit-wise.

When used as an input port, pull-up resistor can be used in software.

Input/output ports. Input/output can be specified in 8-bit units.

When used as an input port, pull-up resistor can be used in software.

Test input flag (KRIF) is set to 1 by falling edge detection.

Input/output ports. Input/output can be specified bit-wise.

When used as an input port, pull-up resistor can be used in software.

LED can be driven directly.

N-ch open-drain input/output port. Input/output can be specified bit-wise.

On-chip pull-up resistor can be specified by mask option.

LED can be driven directly.

Input/output ports. Input/output can be specified bit-wise.

When used as an input port, pull-up resistor can be used in software.

19

XT1/P04

XT2

X1

X2

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

5.2 CLOCK GENERATOR

There are two types of clock generator: main system clock and subsystem clock.

The minimum instruction exection time can be changed.

• 0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s (Main system clock: at 10.0 MHz operation)

• 122

µ s (Subsystem clock: at 32.768 KHz operation)

Figure 5-1. Clock Generator Block Diagram

Watch Timer

Clock Output

Function

Subsystem

Clock

Oscillator f

XT

Main

System

Clock

Oscillator f

X

Prescaler f

X

2 f

X

2

2 f

X

2 3 f

X

2

4

STOP

Prescaler

Clock to

Peripheral

Hardware

Selector

Standby

Control

Circuit

Wait

Control

Circuit

CPU Clock

(f

CPU

)

INTP0

Sampling Clock

20

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

5.3

TIMER/EVENT COUNTER

The following five channels are incorporated in the timer/event counter.

• 16-bit timer/event counter

• 8-bit timer/event counter

• Watch timer

• Watchdog timer

: 1 channel

: 2 channels

: 1 channel

: 1 channel

Operation Interval timer mode

Externanal event counter

Functions Timer output

PWM output

Pulse width mesurement

Sqare wave output

Interrupt request

Test input

Table 5-2. Operation of Timer/Event Counter

16-bit Timer/Event

Counter

1 channel

1 channel

1 output

1 output

1 input

1 output

2

8-bit Timer/Event

Counter

2 channels

2 channels

2 outputs

2 outputs

2

Watch Timer

1 channel

1

1 input

Figure 5-2. 16-bit Timer/Enent Counter Block Diagram

Internal Bus

Watchdog Timer

1 channel

1

– f

X

/2 f

X

/2 2 f

X

/2

3

TI0/INTP0/P00

Edge

Detector

Selector

Match

16-Bit Compare

Register (CR00)

16-Bit Timer

Register (TM0)

Clear

16-Bit Capture

Register (CR01)

Internal Bus

PWM

Pulse

Output

Control

Circuit

Selector

Output

Control

Circuit

INTTM0

TO0/P30

INTP0

21

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Figure 5-3. 8-bit Timer/Enent Counter Block Diagram

Internal Bus

INTIM1 f

X

/2 2 to f

X

/2 10 f

X

/2 12

TI1/P33 f

X

/2 2 to f

X

/2 10 f

X

/2 12

TI2/P34

8-Bit Compare

Register (CR10)

Match

8-Bit Compare

Register (CR20)

Selector

8-Bit Timer

Register 1 (TM1)

Clear

Selector

8-Bit Timer

Register 2 (TM2)

Clear

Selector

Selector

Internal Bus

Selector

Output

Control

Circuit

TO2/P32

INTTM2

Output

Control

Circuit

TO1/P31

Figure 5-4. Watch Timer Block Diagram

f

X

/2 8 f

X

T

Selector f

W

Prescaler f

W

2

4 f

W

2 5 f

W

2

6 f

W

2 7 f

W

2

8 f

W

2 9

Selector

5-Bit Counter f

W

2 14

Selector f

W

2

13

INTWT

Selector

INTTM3

22

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Figure 5-5. Watchdog Timer Block Diagram

f

X

2 4 f

X

2

5 f

X

2 6 f

X

2 7

Prescaler f

X

2 8 f

X

2 9 f

X

2 10 f

X

2 12

Selector

8-Bit Counter

Control

Circuit

INTWDT

Maskable

Interrupt Request

RESET

INTWDT

Non-Maskable

Interrupt Request

5.4 CLOCK OUTPUT CONTROL CIRCUIT

The clock with the following frequencies can be output for clock output.

• 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation)

• 32.768 kHz (Subsystem clock: at 32.768 kHz operation)

Figure 5-6. Clock Output Control Block Diagram

f

X

/2

3 f

X

/2

4 f

X

/2

5 f

X

/2

6 f

X

/2 7 f

X

/2 8 f

XT

Selector

Synchronization

Circuit

Output Control

Circuit

PCL/P35

5.5 BUZZER OUTPUT CONTROL CIRCUIT

The clock with the following frequencies can be output for buzzer output.

• 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation)

Figure 5-7. Buzzer Output Control Block Diagram

f

X

/2

10 f

X

/2

11 f

X

/2 12

Selector

Output Control

Circuit

BUZ/P36

23

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

5.6 A/D CONVERTER

The A/D converter has on-chip eight 8-bit resolution channels.

There are the following two method to start A/D conversion.

• Hardware starting

• Software starting

Figure 5-8. A/D Converter Block Diagram

ANI0/P10

ANI1/P11

ANI2/P12

ANI3/P13

ANI4/P14

ANI5/P15

ANI6/P16

ANI7/P17

INTP3/P03

Selector

Sample & Hold Circuit

Succesive Approxmation

Register (SAR)

Series Resistor String

Voltage Comparator

Tap

Selector

AV

DD

AV

REF

AV

SS

Falling

Edge

Detector

Control

Circuit

INTAD

INTP3

A/D Conversion

Result Register (ADCR)

Internal Bus

5.7 SERIAL INTERFACES

There are two on-chip clocked serial interfaces as follows.

• Serial Interface channel 0

• Serial Interface channel 1

Table 5-3. Type and Function of Serial Interface

3-wire serial I/O mode

Function

3-wire serial I/O mode with automatic data transmit/ receive function

SBI (Serial Bus Interface) mode

2-wire serial I/O mode

Serial Interface Channel 0

O (MSB/LSB-first switchable)

O (MSB-first)

O (MSB-first)

Serial Interface Channel 1

O (MSB/LSB-first switchable)

O (MSB/LSB-first switchable)

24

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Figure 5-9. Serial Interface Channel 0 Block Diagram

Internal Bus

Selector

Selector

Serial I/O Shift

Register 0 (SIO0)

Output

Latch

Bus Release/Command/

Acknowledge Detection

Circuit

Serial Clock Counter

Serial Clock

Control Circuit

Interrupt

Request

Signal

Generator

Busy/Acknowlede

Output Circuit

INTCSI0

Selector f x

/2 2 to f x/

2 9

TO2

SI1/P20

SO1/P21

STB/P23

BUSY/P24

SCK/P22

Figure 5-10. Serial Interface Channel 1 Block Diagram

Internal Bus

Automatic Data Transmit/

Receive Address Pointer

(ADTP)

Buffer RAM

Serial I/O Shift Register 1 (SIO0)

Handshake

Control

Circuit

Serial Clock Counter

Serial Clock Control Circuit

Interrupt Request

Signal Generator

Selector

INTCSI1 f

X

/2

2

to f

X

/2

9

TO2

25

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS

6.1 INTERRUPT FUNCTIONS

There are interrupt functions, 14 sources of three different kinds, as shown below.

• Non-maskable

• Maskable

• Software

: 1

: 12

: 1

Interrupt Type

Non-maskable

Maskable

Software

Table 6-1. Interrupt Source List

5

6

7

1

2

3

4

Default

Priority

Note 1

–––

0

8

9

10

11

–––

Interrupt Source

Name Trigger

INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected)

INTWDT Watchdog timer overflow (with interval timer mode selected)

INTP0 Pin input edge detection

INTP1

INTP2

INTP3

INTCSI0 Serial interface channel 0 transfer end

INTCSI1 Serial interface channel 1 transfer end

INTTM3 Reference time interval signal from watch timer

INTTM0 16 bit timer/event counter match signal generation

INTTM1 8-bit timer/event counter 1 match signal generation

INTTM2 8-bit timer/event counter 2 match signal generation

INTAD A/D converter conversion end

BRK BRK instruction execution

Internal/ Vector Table

External Address

Internal 0004H

Basic

Configuratin

Type

Note 2

(A)

External

Internal

–––

0006H

0008H

000AH

000CH

000EH

0010H

0012H

0014H

0016H

0018H

001AH

003EH

(B)

(C)

(D)

(B)

(E)

Notes 1. The default pririty is the priority applicable when more than one maskable interrupt request is generated. 0 is the highest priority and 11, the lowest.

2. Basic configuration types (A) to (E) correspond to (A) to (E) on the next page.

26

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Figure 6-1. Basic Interrupt Function Configuration (1/2)

(A) Internal Non-Maskable Interrupt

Interrupt

Request

Priority Control

Circuit

Internal Bus

Vector Table

Address

Generator

Standby Release

Signal

(B) Internal Maskable Interrupt

Interrupt

Request

IF

MK

Internal Bus

IE

PR ISP

Priority Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

(C) External Maskable Interrupt (INTP0)

Sampling Clock

Select Register

(SCS)

External Interrupt

Mode Register

(INTM0)

Interrupt

Request

Sampling

Clock

Edge

Detector

IF

Internal Bus

MK IE PR ISP

Priority Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

27

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Figure 6-1. Basic Interrupt Function Configuration (2/2)

(D) External Maskable Interrupt (Except INTP0)

Interrupt

Request

External Interrupt

Mode Register

(INTM0)

Edge

Detector

IF

Internal Bus

MK IE PR ISP

Priority Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

(E) Software Interrupt

Internal Bus

Interrupt

Request

IF : Interrupt request flag

IE : Interrupt enable flag

ISP : In-service priority flag

MK : Interrupt mask flag

PR : Priority spcification flag

Priority Control

Circuit

Vector Table

Address

Generator

28

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

6.2 TEST FUNCTIONS

There are two test functions as shown in Table 6-2.

Name

INTWT

INTPT4

Table 6-2. Test Source List

Test Source

Trigger

Watch timer overflow

Port 4 falling edge detection

Internal/External

Internal

External

Figure 6-2. Test Function Basic Configuration

Internal Bus

MK

Test

Input

IF

Standby Release

Signal

IF : Test input flag

MK : Test mask flag

29

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

7. EXTERNAL DEVICE EXPANSION FUNCTIONS

The external device expansion function is used to connect external devices to areas other than the internal ROM, RAM and SFR.

Ports 4 to 6 are used for connection with external devices.

8. STANDBY FUNCTIONS

There are the following two standby functions to reduce the current dissipation.

• HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operat ing mode.

• STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates withultra-low power consumption using only the subsystem clock.

Figure 8-1. Standby Functions

Main System

Clock Operation

Interrupt

Request

STOP

Instruction

Interrupt

Request

STOP Mode

(Main system clock oscillation stopped)

CSS=1

CSS=0

HALT

Instruction

HALT Mode

(Clock supply to CPU is stopped, oscillation)

Subsystem Clock

Operation

Note

HALT

Instruction

Interrupt

Request

HALT Mode

Note

(Clock supply to CPU is stopped, oscillation)

Note The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set the bit 7 (MCC) of the processor clock control register (PCC) to stop the main system clock.

The STOP instruction cannot be used.

Caution When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program by the program.

9.

RESET FUNCTIONS

There are the following two reset methods.

• External reset input by RESET pin.

• Internal reset by watchdog timer runaway time detection.

30

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

10. INSTRUCTION SET

(1) 8-Bit Instruction

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, ROR4, ROL4, PUSH, POP, DBNZ

2nd Operand

#byte

1st Operand

A ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

A r

Note

sfr saddr !addr16

PSW

MOV MOV MOV MOV MOV

XCH XCH XCH XCH

ADD

ADDC

ADD

ADDC

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

SUB

AND

OR

XOR

CMP

SUB

SUBC SUBC

AND

OR

XOR

CMP

[DE]

[HL+byte]

[HL] [HL+B] $adder16

[HL+C]

MOV MOV

XCH XCH

MOV

XCH

ADD ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND

OR

AND

OR

XOR

CMP

XOR

CMP

1

ROR

ROL

RORC

ROLC

None r MOV MOV INC

DEC ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

B, C sfr sadder

DBNZ

DBNZ INC

DEC

!adder16

PSW

MOV MOV

MOV MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

MOV MOV PUSH

POP

[DE]

[HL]

MOV

MOV ROR4

ROL4

X

C

[HL+byte]

[HL+B]

[HL+C]

Note Except r=A

MOV

MULU

DIVUW

31

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(2) 16-Bit Instruction

MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand

1st Operand

AX rp

#byte

ADDW

SUBW

CMPW

MOVW

AX

MOVW

Note

rp

Note

MOVW

XCHW saddrp

MOVW

!addr16

MOVW

SP

MOVW sfrp sadderp

!adder16

SP

MOVW

MOVW

MOVW

MOVW

MOVW

MOVW MOVW

Note Only when rp=BC, DE, HL.

(3) Bit Manipulation Instruction

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

2nd Operand

1st Operand

A.bit

A.bit

sfr.bit

saddr.bit

PWS.bit

[HL].bit

CY

MOV1 sfr.bit

saddr.bit

PSW.bit

[HL].bit

CY MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

MOV1

MOV1

MOV1

None

MOVW

INCW, DECW

PUSH, POP

$addr16

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

None

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

32

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(4) Call Instruction/Branch Instruction

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

2nd Operand

1st Operand

Basic instruction BR

AX !addr16

CALL, BR

!addr11

CALLF

[addr5]

CALLT

Compound instruction

$addr16

BR, BC, BNC,

BZ, BNZ

BT,BF, BTCLR,

DBNZ

(5) Other Instruction

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

33

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

11. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

A

= 25

°

C)

Test Conditions Parameter

Supply voltage

Symbol

V

DD

AV

DD

AV

REF

AV

SS

Input voltage

V

I1

V

I2

V

O

P00 to P04, P10 to P17, P20 to P27, P30 to P37

P40 toP47, P50 to P57, P64 to P67, X1, X2, XT2

P60 to P67 Open-drain

Output voltage

Analog input voltage

Output current high

Output current low

V

I

AN

OH

I

OL

Note

P10 to P17 Analog input pin

1 pin

P10 to P17, P20 to P27, P30 to P37 total

P01 to P03, P40 to P47, P50 to P57, P60 to P67 total

Peak value

1 pin rms

P40 to P47, P50 to P55 total Peak value rms

P01 to P03, P56, P57,

P60 to P67 total

Peak value rms

P01 to P03, Peak value

P64 to P67 total rms

P10 to P17, P20 to P27, P30 to P37 Peak value total rms

Operating ambient temperature

T

A

Storage temperature

T stg

Rating

–0.3 to +7.0

–0.3 to V

DD

+ 0.3

–0.3 to V

DD

+ 0.3

–0.3 to +0.3

–0.3 to V

DD

+ 0.3

–0.3 to +16

–0.3 to V

DD

+ 0.3

AV

SS

– 0.3 to AV

REF

+ 0.3

15

100

70

100

–10

–15

–15

30

70

50

20

50

20

–40 to +85

–65 to +150

°

C

Note rms should be calculated as follows: [rms] = [peak value]

× √ duty

Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.

V

V

V mA mA mA mA mA mA mA mA mA mA mA mA mA

°

C

Unit

V

V

V

V

V

34

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Capacitance ( T

A

= 25

°

C, V

DD

= V

SS

= 0 V )

Parameter Symbol Test Conditions MIN.

TYP.

MAX.

Input capacitance

I/O capacitance

C

IN

C

IO f = 1 MHz Unmeasured pins returned to 0 V

P01 to P03, P10 to P17, f = 1 MHz Unmeasured P20 to P27, P30 toP37, pins returned to 0 V P40 toP47, P50 to P57,

P64 to P67

P60 to P63

15

15

20

Remark

The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.

Main System Clock Oscillation Circuit Characteristics ( T

A

= –40 to +85

°

C, V

DD

= 1.8 to 5.5 V)

Resonator

Recommended

Circuit

Parameter Test Conditions MIN.

TYP.

Ceramic resonator

X1

C1

X2

V

SS

R1

C2

Oscillator frequency (f

X

)

Note 1

2.7 V

V

DD

5.5 V

1.8 V

V

DD

<

2.7 V

Oscillation stabilization time

Note 2

After V

DD

reaches oscillator voltage range MIN.

1

1

MAX.

10

5

4

Crystal resonator

X1 X2 V

SS

C1 C2

Oscillator frequency (f

X

)

Note 1

2.7 V

V

DD

5.5 V

1.8 V

V

DD

<

2.7 V

Oscillation stabilization time

Note 2

V

DD

= 4.5 to 5.5 V

1

1

10

5

10

30

External clock

X1 X2

X1 input frequency (f

X

)

Note 1

1.0

10.0

µ

PD74HCU04

X1 input high/low level width

(t

XH

, t

XL

)

45 500

Unit pF pF pF

Unit

MHz ms

MHz ms

MHz ns

Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release.

Cautions 1. When using the main system clock oscillator, wiring the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance.

Wiring should be as short as possible.

Wiring should not cross other signal lines.

Wiring should not be placed close to a varying high current.

The potential of the oscillator capacitor ground should be the same as V

SS

.

Do not ground wiring to a ground pattern in which a high current flows.

Do not fetch a signal from the oscillator.

2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program.

35

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Subsystem Clock Oscillation Circuit Characteristics (T

A

= –40 to +85

°

C, V

DD

= 1.8 to 5.5 V)

Resonator

Recommended

Circuit

Parameter

Test Conditions

MIN.

TYP.

Crystal resonator

XT1 XT2

V

SS

R2

C3

C4

Oscillator frequency (f

XT

)

Note 1

Oscillation stabilization time

Note 2

V

DD

= 4.5 to 5.5 V

32 32.768

1.2

External clock

XT1

XT2

XT1 input frequency (f

XT

)

Note 1

XT1 input high/low level width

(t

XTH

, t

XTL

)

32

5

MAX.

35

2

10

100

15

Unit kHz s kHz

µ s

Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after V

DD

reaches oscillator voltage MIN.

Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance.

Wiring should be as short as possible.

Wiring should not cross other signal lines.

Wiring should not be placed close to a varying high current.

The potential of the oscillator capacitor ground should be the same as V

SS

.

Do not ground wiring to a ground pattern in which a high current flows.

Do not fetch a signal from the oscillator.

2. The subsystem clock oscillation circuit is a circuit with a low amplification level,more prone to misoperation due to noise than the main system clock.

Particular care is therefore required with the wiring method when the subsystem clock is used.

36

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Recommended Oscillation Circuit Constant

Recommended oscillation circuit constant differs depending on the model.

(1)

µ

PD78011F, 78012F, 78013F, 78014F

(a) Main system clock: ceramic resonator (T

A

= –45 to +85

°

C)

Manufacturer Product Name

Frequency

(MHz)

Recommended Oscillation

Circuit Constant

C1 (pF) C2 (pF)

TDK Corp.

CCR4.19MC3

FCR4.19MC5

4.19

4.19

Built-in

Built-in

Built-in

Built-in

Murata Mfg. Co. Ltd.

CCR5.00MC3

FCR5.00MC5

CCR8.38MC

FCR8.38MC5

CCR10.00MC

FCR10.00MC5

CSA4.19MG

CST4.19MGW

CSA5.00MG

CST5.00MGW

CSA8.38MTZ

CST8.38MTW

CSA10.00MTZ

CST10.00MTW

4.19

5.00

5.00

8.38

8.38

10.00

10.00

5.00

5.00

8.00

8.00

10.00

10.00

4.19

Built-in

30

Built-in

30

Built-in

30

Built-in

Built-in

Built-in

Built-in

Built-in

Built-in

Built-in

30

Built-in

30

Built-in

30

Built-in

30

Built-in

Built-in

Built-in

Built-in

Built-in

Built-in

Built-in

30

(b) Main system clock: ceramic resonator (T

A

= –20 to +80

°

C)

Manufacturer Product Name

Frequency

(MHz)

Recommended Oscillation

Circuit Constant

C1 (pF) C2 (pF)

Kyocera Corp.

PBRC5.00A

PBRC5.00B

KBR-5.00MSA

KBR-5.00MKS

KBR-8M

KBR-10M

5.00

5.00

5.00

5.00

8.00

10.00

33

Built-in

33

Built-in

33

33

33

Built-in

33

Built-in

33

33

2.7

2.7

1.8

1.8

1.8

1.8

Oscillation

Voltage Range

MIN. (V)

1.8

1.8

MAX. (V)

5.5

5.5

1.8

1.8

2.7

2.7

5.5

5.5

5.5

5.5

2.7

2.7

2.7

2.7

5.5

5.5

5.5

5.5

5.5

5.5

5.5

5.5

5.5

5.5

Oscillation

Voltage Range

MIN. (V)

1.8

1.8

1.8

MAX. (V)

5.5

5.5

5.5

1.8

2.7

2.7

5.5

5.5

5.5

Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact manufacturer of the resonator being used.

37

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(2)

µ

PD78015F, 78016F

(a) Main system clock: ceramic resonator (T

A

= –45 to +85

°

C)

Manufacturer

TDK Corp.

Product Name

CSB1000J

Frequency

(MHz)

1.00

Recommended Oscillation

Circuit Constant

C1 (pF) C2 (pF) R1 (k

)

100 100 5.6

Murata Mfg. Co. Ltd.

(EMI noise reduced products)

TDK Corp.

CSA2.00MG040

CST2.00MG040

CSA4.00MG040

CST4.00MGW040

CSA6.00MG

CST6.00MGW

CSA10.0MTZ

CST10.0MTW

CSA6.00MG040

CST6.00MGW040

CSA10.0MTZ040

CST10.0MTW040

FCR4.0MC5

FCR10.0MC

10.0

6.00

6.00

10.0

10.0

4.0

10.0

2.00

2.00

4.00

4.00

6.00

6.00

10.0

100

Built

in

100

Built

in

30

Built

in

30

Built

in

100

Built

in

100

Built

in

Built

in

Built

in

100

Built

in

100

Built

in

30

Built

in

30

Built

in

100

Built

in

100

Built

in

Built

in

Built

in

0

2.2

1.0

0

0

0

0

0

0

0

0

0

0

0

1.8

1.8

1.8

1.8

2.7

2.7

2.7

Oscillation

Voltage Range

MIN. (V)

1.8

MAX. (V)

6.0

1.8

1.8

1.8

1.8

6.0

6.0

6.0

6.0

2.7

1.8

1.8

6.0

6.0

6.0

6.0

6.0

6.0

6.0

6.0

6.0

6.0

(b) Main system clock: ceramic resonator (T

A

= –20 to +80

°

C)

Manufacturer Product Name

Frequency

(MHz)

Recommended Oscillation

Circuit Constant

C1 (pF) C2 (pF)

Kyocera Corp.

PBRC5.00A

PBRC5.00B

KBR-5.00MSA

KBR-5.00MKS

KBR-8M

KBR-10M

5.00

5.00

5.00

5.00

8.00

10.00

33

Built

in

33

Built

in

33

33

33

Built

in

33

Built

in

33

33

Oscillation

Voltage Range

MIN. (V)

1.8

1.8

MAX. (V)

5.5

5.5

1.8

1.8

2.7

2.7

5.5

5.5

5.5

5.5

Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact manufacturer of the resonator being used.

38

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(3)

µ

PD78018F

(a) Main system clock: ceramic resonator (T

A

= –40 to +85

°

C)

Manufacturer Product Name

Frequency

(MHz)

Recommended Oscillation

Circuit Constant

TDK Corp.

CCR4.0MC3

4.00

C1 (pF)

Built

in

C2 (pF)

Built

in

FCR4.0MC5

4.00

Built

in Built

in

CCR8.0MC5

FCR8.0MC

CCR10.0MC5

FCR10.0MC

8.00

8.00

10.0

10.0

Built

in

Built

in

Built

in

Built

in

Built

in

Built

in

Built

in

Built

in

Murata Mfg. Co. Ltd.

CSA4.0MG

CST4.0MGW

CSA8.0MTZ

CST8.0MTW

4.00

4.00

8.00

8.00

30

Built

in

30

Built

in

30

Built

in

30

Built

in

(b) Main system clock: ceramic resonator (T

A

= –20 to +80

°

C)

Manufacturer Product Name

Frequency

(MHz)

Recommended Oscillation

Circuit Constant

Kyocera Corp.

FBRC4.00A

FBRC4.00B

KBR-4.00MSB

KBR-4.00MKC

KBR-8M

KBR-10M

4.00

4.00

4.00

4.00

8.00

10.00

C1 (pF)

33

Built

in

33

Built

in

33

33

C2 (pF)

33

Built

in

33

Built

in

33

33

Oscillation

Voltage Range

MIN. (V)

1.8

1.8

MAX. (V)

5.5

5.5

2.7

2.7

2.7

2.7

5.5

5.5

5.5

5.5

1.8

1.8

2.7

2.7

5.5

5.5

5.5

5.5

Oscillation

Voltage Range

MIN. (V)

1.8

1.8

1.8

MAX. (V)

5.5

5.5

5.5

1.8

2.7

2.7

5.5

5.5

5.5

Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact manufacturer of the resonator being used.

39

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

DC Characteristics (T

A

= –40 to +85

°

C, V

DD

= 1.8 to 5.5 V)

Parameter Symbol

Input voltage V

IH1 high

Input voltage low

Output voltage high

Output voltage low

V

V

V

V

V

V

V

V

V

V

V

V

V

IH2

IH3

IH4

IH5

IL1

IL2

IL3

IL4

IL5

OH1

OL1

OL2

OL3

Test Conditions MIN.

P10 to P17, P21, P23, P30 to P32, V

DD

= 2.7 to 5.5 V

P35 to P37, P40 to P47,

P50 to P57, P64 to 67

P00 to P03, P20, P22, P24 to P27, V

DD

= 2.7 to 5.5 V

P33, P34, RESET

P60 to P63

(N-ch open-drain)

X1, X2

V

V

DD

DD

= 2.7 to 5.5 V

= 2.7 to 5.5 V

0.7 V

0.8 V

DD

DD

0.8 V

DD

0.85 V

DD

0.7 V

DD

0.8 V

DD

V

DD

– 0.5

XT1/P04, XT2 4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

1.8 V

V

DD

<

2.7 V

Note

P10 to P17, P21, P23, P30 to P32, V

DD

= 2.7 to 5.5 V

P35 to P37, P40 to P47,

P50 to P57, P64 to 67

P00 to P03, P20, P22, P24 to P27, V

DD

= 2.7 to 5.5 V

P33, P34, RESET

P60 to P63

X1, X2

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

V

DD

= 2.7 to 5.5 V

V

DD

– 0.2

0.8 V

DD

0.9 V

DD

0.9 V

DD

0

0

XT1/P04, XT2 4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

1.8 V

V

DD

<

2.7 V

Note

V

DD

= 4.5 to 5.5 V, I

OH

= –1 mA

I

OH

= –100

µ

A

P50 to P57, P60 to P63 V

DD

= 4.5 to 5.5 V,

I

OL

= 15 mA

P01 to P03, P10 to P17, P20 to P27 V

DD

= 4.5 to 5.5 V,

P30 to P37, P40 to P47, P64 to P67 I

OL

= 1.6 mA

SB0, SB1, SCK0 V

DD

= 4.5 to 5.5 V, open-drain pulled-up (R = 1 K

)

I

OL

= 400

µ

A

0

0

V

DD

– 1.0

V

DD

– 0.5

0

0

0

0

0

0

0

0

TYP.

MAX.

V

DD

0.4

V

DD

0.2 V

2.0

0.4

0.2 V

0.5

DD

DD

0.2 V

DD

0.15 V

DD

0.3 V

DD

0.2 V

DD

0.1 V

DD

0.4

0.2

0.2 V

DD

0.1 V

DD

0.1 V

DD

V

DD

V

DD

V

DD

V

DD

0.3 V

DD

V

DD

V

DD

15

15

V

DD

Unit

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Note

When using XT1/P04 as P04, input the inverse of P04 to XT2 using an inverter.

Remark

The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.

40

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

DC Characteristics (T

A

= –40 to +85

°

C, V

DD

= 1.8 to 5.5 V)

Parameter Symbol

Input leakage I

LIH1 current high

V

IN

= V

DD

I

LIH2

I

LIH3

Input leakege I

LIL1 current low

I

LIL2

I

LIL3

Output leakage I

LOH1 current high

Output leakage I

LOL current low

Mask option R1 pull-up resister

Software R2 pull-up resister

V

IN

= 15 V

V

IN

= 0 V

V

OUT

= V

DD

V

OUT

= 0 V

V

IN

= 0 V, P60 to P63

Test Conditions

P00 to P03, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P50 to P57,

P60 to P67, RESET

X1, X2, XT1/P04, XT2

P60 to P63

P00 to P03, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P50 to P57,

P60 to P67, RESET

X1, X2, XT1/P04, XT2

P60 to P63

V

IN

= 0 V, P01 to P03, P10 to P17, P20 to P27, P30 to P37,

P40 to P47, P50 to P57, P60 to P67

MIN.

TYP.

MAX.

3

Unit

µ

A

20

15

40

40

20

80

–3

–20

–3

Note

3

µ

A

µ

A

µ

A

–3

90

90

µ

A

µ

A

µ

A

µ

A k

Ω k

Note For P60 to P63, if pull-up resistor is not provided (specifiable by mask option) a low-level input leak current of –200

µ

A (MAX.) flows only during the 3 clocks (no-wait time) after an instruction has been executed to read out port 6 (P6) or port mode register 6 (PM6). Outside the period of 3 clocks following execution a read-out instruction, the current is –3

µ

A (MAX.).

Remark

The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.

41

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

DC Characteristics (T

A

= –40 to +85

°

C, V

DD

= 1.8 to 5.5 V)

Parameter Symbol

Supply current

Note 1

I

DD1

I

DD2

I

I

I

I

DD3

DD4

DD5

DD6

Test Conditions

10.00 MHz crystal oscillation operation mode

10.00 MHz crystal oscillation HALT mode

32.768 kHz crystal oscillation operation mode

Note 4

V

DD

= 5.0 V

±

10 %

Note 2

V

DD

= 3.0 V

±

10 %

Note 3

V

DD

= 5.0 V

±

10 %

Note 2

V

DD

= 3.0 V

±

10 %

Note 3

V

DD

= 5.0 V

±

10 %

V

DD

= 3.0 V

±

10 %

32.768 kHz crystal oscillation HALT mode

Note 4

STOP mode when not using feedback resistor

V

DD

= 2.0 V

±

10 %

V

DD

= 5.0 V

±

10 %

V

DD

= 3.0 V

±

10 %

V

DD

= 2.0 V

±

10 %

XT1 = V

DD

V

DD

= 5.0 V

±

10 %

STOP mode when using feedback V

DD

= 3.0 V

±

10 % resistor

XT1 = V

DD

V

DD

= 2.0 V

±

10 %

V

DD

= 5.0 V

±

10 %

V

DD

= 3.0 V

±

10 %

V

DD

= 2.0 V

±

10 %

MIN.

TYP.

MAX.

5

2

1

0.5

60

35

24

25

9.0

1.3

2.4

1.2

0.3

0.1

0.05

0.05

15

10

30

10

120

70

48

50

18.0

2.6

4.8

2.4

10

30

10

10

Unit mA mA mA mA

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

Notes 1. This current excludes the AV

REF

current, port current, and current which flows in the built-in pull-down resistor.

2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H)

3. When operating at low-speed mode (when the PCC is set to 04H)

4. When main system clock stopped.

42

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

AC Characteristics

(1) Basic Operation (T

A

= –40 to +85

°

C, V

DD

= 1.8 to 5.5 V)

Parameter Symbol

Cycle time

(Min. instruction execution time)

T

CY

TI0 input frequency t t

TIH0

TIL0

Test Conditions

Operating on main system clock 3.5 V

V

DD

5.5 V

2.7 V

V

DD

<

3.5 V

1.8 V

V

DD

<

2.7 V

Operating on subsystem clock

3.5 V

V

DD

5.5 V

2.7 V

V

DD

<

3.5 V

1.8 V

V

DD

<

2.7 V

V

DD

= 4.5 to 5.5 V TI1, TI2 input f

TI1 frequency

TI1, TI2 input high/low-level width t t

TIH1

TIL1

Interrupt t

INTH request input t

INTL high/low-level width

V

DD

= 4.5 to 5.5 V

INTP0

INTP1 to INTP3, KR0 to KR7

3.5 V

V

2.7 V

V

DD

<

3.5 V

1.8 V

V

DD

<

2.7 V

V

DD

DD

5.5 V

= 2.7 to 5.5 V

RESET low level width t

RSL

V

DD

= 2.7 to 5.5 V

MIN.

0.4

0.8

2.0

40

2/f sam

+ 0.1

Note

2/f sam

+ 0.2

Note

2/f sam

+ 0.5

Note

0

0

100

TYP.

MAX.

122

64

64

64

125

4

275

1.8

2/f sam

+ 0.1

Note

2/f sam

+ 0.2

Note

2/f sam

+ 0.5

Note

10

20

10

20

Unit

µ s

µ s

µ s

µ s

µ s

µ s

µ s

MHz kHz ns

µ s

µ s

µ s

µ s

µ s

µ s

µ s

µ s

Note In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fX/2

N+1

, fX/64 and fx/128 (when N= 0 to 4).

43

44

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

T

CY

vs V

DD

(At main system clock operation)

60.0

Operation Guaranteed

Range

10.0

5.0

1.0

0.5

0.1

0 1.0

1.8

2.0

2.7

3.0

3.5

4.0

Supply voltage V

DD

[V]

5.0

5.5

6.0

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(2) Read/Write Operation (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 5.5 V)

Parameter

ASTB high-level width

Address setup time

Address hold time

Data input time from address

Data input time from RD

Read data hold time

RD low-level width

WAIT

input time from RD

WAIT

input time from WR

WAIT low-level width

Write data setup time

Write data hold time

WR low-level width

RD

delay time from ASTB

WR

delay time from ASTB

ASTB

delay time from

RD

in external fetch

Address hold time from

RD

in external fetch

Write data output time from RD

↑ t

RDH t

RDL1 t

RDL2 t

RDWT1 t

RDWT2 t

WRWT

Symbol t

ASTH t

ADS t

ADH t

ADD1 t

ADD2 t

RDD1 t

RDD2 t

WTL t

WDS t

WDH t

WRL1 t

ASTRD t

ASTWR t

RDAST

Test Conditions

Load resistor

5 k

Ω t

RDADH t

RDWD

V

DD

= 4.5 to 5.5 V

MIN.

0.5t

CY

0.5t

CY

– 30

50

0

(1.5 + 2n) t

CY

– 20

(2.5 + 2n) t

CY

– 20

(0.5 + 2n) t

CY

+ 10

100

20

(2.5 + 2n) t

CY

– 20

0.5t

CY

– 30

1.5t

CY

– 30

t

CY

– 10 t

CY

Write data output time from WR

Address hold time from WR

RD

delay time from WAIT

WR

delay time from WAIT

↑ t

WRWD t

WRADH t

WTRD t

WTWR

V

DD

= 4.5 to 5.5 V

V

DD

= 4.5 to 5.5 V

0.5t

CY

+ 5

0.5t

CY

+ 15

5

15 t

CY t

CY

0.5t

CY

0.5t

CY

Remarks 1. t

CY

= T

CY

/4

2. n indicates number of waits.

(2.5 + 2n) t

CY

– 50

(3 + 2n) t

CY

– 100

(1 + 2n) t

CY

– 25

(2.5 + 2n) t

CY

– 100

(2 + 2n) t t t

MAX.

0.5t

CY

1.5t

CY

0.5t

CY

CY

CY

+ 40

+ 50

CY

0.5t

CY

+ 30

0.5t

CY

+ 90

30

90 t

CY

+ 60 t

CY

+ 100

2.5t

CY

+ 80

2.5t

CY

+ 80 ns ns ns ns ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

45

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(3) Serial Interface (T

A

= –40 to +85

°

C, V

DD

= 1.8 to 5.5 V)

(a) Serial Interface Channel 0

(i) 3-wire serial I/O mode (SCK0... Internal clock output)

Parameter

SCK0 cycle time

Symbol t

KCY1

Conditions

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

SCK0 high/low-level width

SI0 setup time

(to SCK0

) t

KH1 t

KL1 t

SIK1

V

DD

= 4.5 to 5.5 V

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

MIN.

800

1600

3200

4800 t

KCY1

/2 – 50 t

KCY1

/2 – 100

100

150

300

400

400 SI0 hold time

(from SCK0

) t

KSI1

SO0 output delay time t

KSO1 from SCK0

C = 100 pF

Note

Note C is the load capacitance of SCK0 and SO0 output line.

(ii) 3-wire serial I/O mode (SCK0... External clock input)

Parameter

SCK0 cycle time

Symbol t

KCY2

Test Conditions

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

SCK0 high/low-level width t

KH2 t

KL2

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

MIN.

800

1600

3200

4800

400

800

1600

2400

100

150

400

SI0 setup time

(to SCK0

)

SI0 hold time

(from SCK0

) t t

SIK2

KSI2

SO0 output delay time t

KSO2 from SCK0

SCK0 rise, fall time t

R2 t

F2

V

DD

= 2.0 to 5.5 V

C = 100 pF

Note

V

DD

= 2.0 to 5.5 V

When external device expansion function is used

When external When 16-bit timer device expansion output function is function is not used used When 16-bit timer output function is not used

Note C is the load capacitance of SO0 output line.

46

TYP.

TYP.

MAX.

300

MAX.

300

500

160

700

1000 ns

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(iii) SBI mode (SCK0... Internal clock output)

Parameter

SCK0 cycle time

SCK0 high/low-level width

SB0, SB1 setup time

(to SCK0

↑)

Symbol t

KCY3 t

KH3 t

KL3 t

SIK3

Test Conditions

4.5 V

V

DD

5.5 V

2.0 V

V

DD

<

4.5 V

V

DD

= 4.5 to 6.0 V

4.5 V

V

DD

5.5 V

2.0 V

V

DD

<

4.5 V

MIN.

800

3200

4800 t

KCY3

/2 – 50 t

KCY3

/2 – 150

100

300

400 t

KCY3

/2

TYP.

MAX.

SB0, SB1 hold time

(from SCK0

) t

KSI3

SB0, SB1output delay t

KSO3 time from SCK0

SB0, SB1

from SCK0

↑ t

KSB

SCK0

↓ from SB0, SB1

↓ t

SBK

SB0, SB1 high-level t

SBH width

SB0, SB1 low-level width t

SBL

R = 1 k

,

C = 100 pF

Note

V

DD

= 4.5 to 5.5 V 0

0 t

KCY3 t

KCY3 t

KCY3 t

KCY3

250

1000

Note R and C are the load resistors and load capacitance of the SB0, SB1 and SCK0 output line.

ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns

47

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(iv) SBI mode (SCK0... External clock input)

Parameter

SCK0 cycle time

SCK0 high/low-level width

Symbol t

KCY4 t

KH4 t

KL4

SB0, SB1 setup time

(to SCK0

↑) t

SIK4

Test Conditions

4.5 V

V

DD

5.5 V

2.0 V

V

DD

<

4.5 V

4.5 V

V

DD

5.5 V

2.0 V

V

DD

<

4.5 V

4.5 V

V

DD

5.5 V

2.0 V

V

DD

<

4.5 V

MIN.

2400

100

300

400 t

KCY4

/2

800

3200

4800

400

1600

TYP.

SB0, SB1 hold time

(from SCK0

) t

KSI4

SB0, SB1 output delay t

KSO4 time from SCK0

SB0, SB1

from SCK0

↑ t

KSB

SCK0

↓ from SB0, SB1

↓ t

SBK

SB0, SB1 high-level t

SBH width

SB0, SB1 low-level width

SCK0 rise, fall time t t

SBL

R4 t

F4

R = 1 k

,

C = 100 pF

Note

V

DD

= 4.5 to 5.5 V 0

0 t

KCY4 t

KCY4 t

KCY4 t

KCY4

When external device expansion function is used

When external When 16-bit timer device expansion output function is function is not used used When 16-bit timer output function is not used

Note R and C are the load resistors and load capacitance of the SB0 and SB1 output line.

MAX.

300

1000

160

700

1000 ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

48

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(v) 2-wire serial I/O mode (SCK0... Internal clock output)

Parameter

SCK0 cycle time

Symbol t

KCY5

SCK0 high-level width t

KH5

SCK0 low-level width t

KL5

SB0, SB1 setup time

(to SCK0

↑) t

SIK5

Test Conditions

R = 1 k

,

C = 100 pF

Note

2.7 V

V

DD

5.5 V

2.0 V

V

DD

<

2.7 V

MIN.

1600

3200

4800

V

DD

= 2.7 to 5.5 V t

KCY5

/2 – 160 t

KCY5

/2 – 190

V

DD

= 4.5 to 5.5 V t

KCY5

/2 – 50 t

KCY5

/2 – 100

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

300

350

400

500

600

TYP.

MAX.

SB0, SB1 hold time

(from SCK0

) t

KSI5

SB0, SB1 output delay t

KSO5 time from SCK0

0

Note R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.

300

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns

49

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(vi) 2-wire serial I/O mode (SCK0... External clock input)

Parameter

SCK0 cycle time

Symbol t

KCY6

SCK0 high-level width t

KH6

SCK0 low-level width t

KL6

Test Conditions

2.7 V

V

DD

5.5 V

2.0 V

V

DD

<

2.7 V

2.7 V

V

DD

5.5 V

2.0 V

V

DD

<

2.7 V

2.7 V

V

DD

5.5 V

2.0 V

V

DD

<

2.7 V

MIN.

2100

800

1600

2400

100

150 t

KCY6

/2

1600

3200

4800

650

1300

TYP.

SB0, SB1 setup time

(to SCK0

↑)

SB0, SB1 hold time

(from SCK0

) t t

SIK6

KSI6

SB0, SB1 output delay t

KSO6 time from SCK0

V

DD

= 2.0 to 5.5 V

R = 1 k

,

C = 100 pF

Note

4.5 V

V

DD

5.5 V

2.0 V

V

DD

<

4.5 V

0

0

0

SCK0 rise, fall time t

R6 t

F6

When external device expansion function is used

When external When 16-bit timer device expansion output function is function is not used used When 16-bit timer output function is not used

Note R and C are the load resistors and load capacitance of the SB0 and SB1 output line.

MAX.

1000

300

500

800

160

700 ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns ns

50

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(b) Serial Interface Channel 1

(i) 3-wire serial I/O mode (SCK1... Internal clock output)

Parameter

SCK1 cycle time

Symbol t

KCY7

Test Conditions

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

SCK1 high/low-level width

SI1 setup time

(to SCK1

) t

KH7 t

KL7 t

SIK7

V

DD

= 4.5 to 5.5 V

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

MIN.

800

1600

3200

4800 t

KCY7

/2 – 50 t

KCY7

/2 – 100

100

150

300

400

400 SI1 hold time

(from SCK1

) t

KSI7

SO1 output delay time t

KSO7 from SCK1

C = 100 pF

Note

Note C is the load capacitance of SCK1 and SO1 output line.

(ii) 3-wire serial I/O mode (SCK1... External clock input)

Parameter

SCK1 cycle time

Symbol t

KCY8

Test Conditions

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

SCK1 high/low-level width t

KH8 t

KL8

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

MIN.

800

1600

2400

100

150

400

800

1600

3200

4800

400

SI1 setup time

(to SCK1

) t

SIK8

SI1 hold time

(from SCK1

) t

KSI8

SO0 output delay time t

KSO8 from SCK1

SCK1 rise, fall time t

R8 t

F8

V

DD

= 2.0 to 5.5 V

C = 100 pF

Note

V

DD

= 2.0 to 5.5 V

When external device expansion function is used

When external When 16-bit timer device expansion output function is function is not used used When 16-bit timer output function is not used

Note C is the load capacitance of SO1 output line.

TYP.

TYP.

MAX.

300

MAX.

1000

300

500

160

700 ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns ns

51

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... Internal clock output)

Parameter

SCK1 cycle time

SCK1 high/low-level width

SI1 setup time

(to SCK1

)

Symbol t

KCY9 t

KH9 t

KL9 t

SIK9

SI1 hold time

(from SCK1

) t

KSI9

SO1 output delay time t

KSO9 from SCK1

STB

from SCK1

↑ t

SBD

Strobe signal t

SBW high-level width

Test Conditions

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

V

DD

= 4.5 to 5.5 V

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

C = 100 pF

Note

2.7 V

V

DD

5.5 V

2.0 V

V

DD

<

2.7 V

MIN.

800

1600

3200

4800 t

KCY9

/2 – 50 t

KCY9

/2 – 100

100

150

300

400

400 t

KCY9

/2 – 100 t

KCY9

– 30 t

KCY9

– 60 t

KCY9

– 90

100

TYP.

MAX.

300 t

KCY9

/2 + 100 t

KCY9

+ 30 t

KCY9

+ 60 t

KCY9

+ 90

Busy signal setup time t

BYS

(to busy signal detection timing)

Busy signal hold time t

BYH

(from busy signal detection timing)

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

100

150

200

300

Unit ns ns ns ns ns ns ns ns ns ns ns ns

SCK1

from busy inactive t

SPS

2t

KCY9 ns ns ns ns ns ns ns ns ns ns

Note C is the load capacitance of SCK1 and SO1 output line.

52

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... External clock input)

Parameter

SCK1 cycle time

SCK1 high/low-level width

Symbol t

KCY10 t

KH10

, t

KL10

SI1 setup time

(to SCK1

)

SI1 hold time

(from SCK1

) t t

SIK10

KSI10

SO1 output delay time t

KSO10 from SCK1

SCK1 rise, fall time t

R10

, t

F10

Test Conditions

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

4.5 V

V

DD

5.5 V

2.7 V

V

DD

<

4.5 V

2.0 V

V

DD

<

2.7 V

V

DD

= 2.0 to 5.5 V

C = 100 pF

Note

V

DD

= 2.0 to 5.5 V

MIN.

800

1600

2400

100

150

400

800

1600

3200

4800

400

TYP.

MAX.

300

500

160 When external device expansion function is used

When external device expansion function is not used

1000

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note C is the load capacitance of the SO1 output line.

53

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

AC Timing Test Point (Excluding X1, XT1 Input)

0.8 V

DD

0.2 V

DD

Test Points

0.8 V

DD

0.2 V

DD

Clock Timing

t

XL

1/f

X t

XH

X1 Input

V

IH4

(MIN.)

V

IL4

(MAX.) t

XTL

1/f

XT t

XTH

XT1 Input

V

IH5

(MIN.)

V

IL5

(MAX.)

TI Timing

t

TIL0 t

TIH0

TI0 t

TIL1

1/f

TI1 t

TIH1

TI1,TI2

54

Read/Write Operation

External fetch (No wait):

A8 to A15

AD0 to AD7

ASTB

RD

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Higher 8-Bit Address t

ADS t

ASTH

Lower 8-Bit

Address t

ADD1

H i

-Z t

ADH

Operation Code t

RDD1 t

RDADH t

RDAST t

ASTRD t

RDL1 t

RDH

External fetch (Wait insertion):

A8 to A15

AD0 to AD7 t

ADS t

ASTH

Lower 8-Bit

Address t

ADH

ASTB

RD t

ASTRD

WAIT t

RDWT1

Higher 8-Bit Address t

ADD1

H i

-Z t

RDD1

Operation Code t

RDADH t

RDAST t

WTL t

RDL1 t

WTRD t

RDH

55

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

External data access (No wait):

A8 to A15

AD0 to AD7

Higher 8-Bit Address t

ASTH t

ADS

Lower 8-Bit

Address t

ADD2

H i

-Z t

ADH t

RDD2

Read Data t

RDH

H i

-Z

Write Data

ASTB

RD

WR t

ASTRD t

ASTWR t

RDL2 t

RDWD t

WRWD t

WDS t

WRL1

H i

-Z t

WDH t

WRADH

External data access (Wait insertion):

A8 to A15

AD0 to AD7

ASTB

RD

WR

WAIT t

ADS t

ASTH

Lower 8-Bit

Address t

ADH t

ADD2

H i

-Z t

RDD2 t

ASTRD t

RDWT2 t

Higher 8-Bit Address

Read Data

RDH

H i

-Z

Write Data t

WTL t

RDL2 t

ASTWR t

WTRD t

RDWD t

WRWD t

WDS t

WRL1 t

WRWT t

WTL t

WTWR t

WDH t

WRADH

H i

-Z

56

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Serial Transfer Timing

3-wire serial I/O mode:

t

KLm t

Rn t

KCYm t

KHm t

Fn

SCK0,SCK1

SI0,SI1 t

SIKm t

KSIm

Input Data t

KSOm

SO0,SO1 m = 1, 2, 7, 8 n = 2, 8

SBI mode (Bus release signal transfer):

SCK0

Output Data t

KSB t

SBL t

SBH t

SBK t

KL3, 4 t

KCY3, 4 t

KH3, 4 t

R4 t

F4 t

SIK3, 4 t

KSI3, 4

SB0, SB1 t

KSO3, 4

SBI Mode (command signal transfer):

t

KL3, 4 t

R4 t

KCY3, 4 t

KH3, 4 t

F4

SCK0 t

KSB t

SBK t

SIK3, 4 t

KSI3, 4

SB0, SB1 t

KSO3, 4

57

2-wire serial I/O mode:

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

SCK0 t

KSO5,6 t

KL5,6 t

R6 t

KCY5,6 t

KH5,6 t

F6 t

SIK5,6 t

KSI5,6

SB0, SB1

3-wire serial I/O mode with automatic transmit/receive function:

SO1

D2 D1 D0

SI1

SCK1

D2 t

SIK9,10 t

KSO9,10

D1 t

KH9,10 t

KSI9,10 t

F10

D0 t

KL9,10 t

KCY9,10 t

R10 t

SBD t

SBW

STB

3-wire serial I/O mode with automatic transmit/receive function (busy processing):

SCK1 7

8

9

Note

t

BYS

10

Note

t

BYH

10 + n

Note

t

SPS

BUSY

(Active High)

Note The signal is not actually driven low here; it is shown as such to indicate the timing.

1

D7

D7

58

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

A/D converter characteristics (T

A

= –40 to +85

°

C, AV

DD

= V

DD

= 1.8 to 5.5 V, AV

SS

= V

SS

= 0 V)

Parameter

Resolution

Overall error

Note

Conversion time

Sampling time

Analog input voltage

Reference voltage

AV

REF

resistance

Symbol t

CONV t

SAMP

V

IAN

AV

REF

R

AIREF

Test Conditions

2.7 V

AV

REF

AV

DD

1.8 V

AV

REF

<

2.7 V

2.0 V

AV

DD

5.5 V

1.8 V

AV

DD

<

2.0 V

MIN.

8

19.1

38.2

24/f

X

AV

SS

1.8

4

TYP.

8

MAX.

8

0.6

1.4

200

200

AV

REF

AV

DD

14

Note Overall error excluding quantization error (

±

1/2 LSB). It is indicated as a ratio to the full-scale value.

Unit bit

%

%

µ s

µ s

µ s

V

V k

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T

A

= –40 to +85

°

C)

Parameter Symbol

Data retention supply V

DDDR voltage

Data retention supply I

DDDR current

Test Conditions

V

DDDR

= 1.8 V

Subsystem clock stop and feedback resister disconnected

MIN.

1.8

TYP.

0.1

MAX.

5.5

10

Release signal set time t

SREL

Oscillation stabilization t

WAIT wait time

Release by RESET

Release by interrupt request

0

2

18

/f

X

Note

Unit

V

µ

A

µ s ms ms

Note In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection of 2

13

/f

X

and 2

15

/f

X

to 2

18

/f

X

is possible.

Data Retention Timing (STOP Mode Release by RESET)

Internal Reset Operation

HALT Mode

Operating Mode

STOP Mode

Data Retension Mode

V

DD

V

DDDR t

SREL

STOP Instruction Execution

RESET t

WAIT

59

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Data Retention Timing (Standby Release Signal : STOP Mode Release by Interrupt Request Signal)

HALT Mode

Operating Mode

STOP Mode

Data Retension Mode

V

DD

STOP Instruction Execition

Standby Release Signal

(Interrupt Request)

V

DDDR t

SREL t

WAIT

Interrupt Request Input Timing

INTP0 to INTP2 t

INTL t

INTH t

INTL

INTP3

RESET Input Timing

RESET t

RSL

60

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

12. CHARACTERISTIC CURVE (REFERENCE VALUES)

I

DD

vs V

DD

(Main System Clock: 10.0 MHz)

10.0

5.0

(T

A

= 25

°

C)

PCC = 00H

PCC = 01H

PCC = 02H

PCC = 03H

PCC = 04H

PCC = 30H

HALT (X1 Oscillation,

XT1 Stop)

1.0

0.5

0.1

0.05

PCC = B0H

HALT (X1 Stop,

XT1 Oscillation)

0.01

0.005

f

X

= 10.0 MHz f

XT

= 32.768 kHz

0.001

0 1 2 3 4

Supply Voltage V

DD

[V]

5 6 7 8

61

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

13. PACKAGE DRAWINGS

64 PIN PLASTIC SHRINK DIP (750 mil)

64 33

1 32

A

K

L

F

D N

M

NOTE

1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition.

2) Item "K" to center of leads when formed parallel.

C

B

M

R

D

F

G

J

K

H

I

L

ITEM MILLIMETERS

A

B

C

58.68 MAX.

1.78 MAX.

1.778 (T.P.)

M

N

R

0.50±0.10

0.9 MIN.

3.2±0.3

0.51 MIN.

4.31 MAX.

5.08 MAX.

19.05 (T.P.)

17.0

0.25

0.17

+0.10

–0.05

0~15°

INCHES

2.311 MAX.

0.070 MAX.

0.070 (T.P.)

0.020

+0.004

–0.005

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.750 (T.P.)

0.669

0.010

+0.004

–0.003

0.007

0~15°

P64C-70-750A,C-1

Remark

Dimensions and materials of ES products are the same as those of mass-production products.

62

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

64 PIN PLASTIC QFP ( 14)

A

B

48

49

33

32 detail of lead end

64

1 16

17

G H

I M

J

K

N

NOTE

Each lead centerline is located within 0.15

mm (0.006 inch) of its true position (T.P.) at maximum material condition.

L

M

N

K

L

I

J

G

H

ITEM

A

B

C

D

F

P

Q

S

MILLIMETERS

17.6± 0.4

14.0± 0.2

14.0± 0.2

17.6± 0.4

1.0

1.0

0.35± 0.10

0.15

0.8 (T.P.)

1.8± 0.2

0.8± 0.2

0.15

+0.10

–0.05

0.10

2.55

0.1± 0.1

2.85 MAX.

P64GC-80-AB8-2

INCHES

0.693± 0.016

0.551

+0.009

–0.008

0.551

+0.009

–0.008

0.693± 0.016

0.039

0.039

0.014

+0.004

–0.005

0.006

0.031 (T.P.)

0.071± 0.008

0.031

+0.009

–0.008

0.006

+0.004

–0.003

0.004

0.100

0.004± 0.004

0.112 MAX.

Remark

Dimensions and materials of ES products are the same as those of mass-production products.

63

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

64 PIN PLASTIC LQFP ( 12)

A

B

49

48 33

32 detail of lead end

64

1

G

16

17

H I

M

J

K

N

L

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

M

N

P

Q

R

S

C

D

F

G

H

J

I

K

L

ITEM MILLIMETERS

A 14.8±0.4

B 12.0±0.2

INCHES

0.583±0.016

12.0±0.2

14.8±0.4

1.125

1.125

0.30±0.10

0.472

+0.009

–0.008

0.583±0.016

0.044

0.044

0.13

0.65 (T.P.)

1.4±0.2

0.6±0.2

0.005

0.026 (T.P.)

0.055±0.008

0.15

+0.10

–0.05

0.10

0.006

0.004

+0.004

–0.003

1.4

0.055

0.125±0.075

0.005±0.003

5

°

±5

°

5

°

±5

°

1.7 MAX.

0.067 MAX.

P64GK-65-8A8-1

Remark

Dimensions and materials of ES products are the same as those of mass-production products.

64

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

14. RECOMMENDED SOLDERING CONDITIONS

The

µ

PD78011F/78012F/78013F/78014F/78015F/78016F/78018F should be soldered and mounted under the conditions recommended in the table below.

For detail of recommended soldering conditions, refer to the information document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact our salespersonnel.

Table 14-1. Surface Mounting Type Soldering Conditions (1/2)

(1)

µ

PD78011FGC-

×××

-AB8: 64-Pin Plastic QFP (14

×

14 mm)

µ

PD78012FGC-

×××

-AB8: 64-Pin Plastic QFP (14

×

14 mm)

µ

PD78013FGC-

×××

-AB8: 64-Pin Plastic QFP (14

×

14 mm)

µ

PD78014FGC-

×××

-AB8: 64-Pin Plastic QFP (14

×

14 mm)

µ

PD78015FGC-

×××

-AB8: 64-Pin Plastic QFP (14

×

14 mm)

µ

PD78016FGC-

×××

-AB8: 64-Pin Plastic QFP (14

×

14 mm)

µ

PD78018FGC-

×××

-AB8: 64-Pin Plastic QFP (14

×

14 mm)

Soldering Method

Infrared reflow

VPS

Wave soldering

Partial heating

Soldering Conditions

Package peak temperature: 235

°

C, Duration: 30 sec. max. (at 210

°

C or above),

Number of times: Three times max.

Package peak temperature: 215

°

C, Duration: 40 sec. max. (at 200

°

C or above),

Number of times: Three times max.

Solder bath temperature: 260

°

C max. Duration: 10 sec. max.

Number of times: Once

Preheating temperature: 120

°

C max. (Package surface temperature)

Pin temperature: 300

°

C max., Duration: 3 sec. max. (per device side)

Recommended

Condition Symbol

IR35-00-3

VP15-00-3

WS60-00-1

Caution Use more than one soldering method should be avoided (except in the case of partial heating).

65

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Table 14-1. Surface Mounting Type Soldering Conditions (2/2)

(2)

µ

PD78011FGK-

×××

-8A8 : 64-Pin Plastic LQFP (12

×

12 mm)

µ

PD78012FGK-

×××

-8A8 : 64-Pin Plastic LQFP (12

×

12 mm)

µ

PD78013FGK-

×××

-8A8 : 64-Pin Plastic LQFP (12

×

12 mm)

µ

PD78014FGK-

×××

-8A8 : 64-Pin Plastic LQFP (12

×

12 mm)

µ

PD78015FGK-

×××

-8A8 : 64-Pin Plastic LQFP (12

×

12 mm)

µ

PD78016FGK-

×××

-8A8 : 64-Pin Plastic LQFP (12

×

12 mm)

µ

PD78018FGK-

×××

-8A8 : 64-Pin Plastic LQFP (12

×

12 mm)

Soldering Method

Infrared reflow

VPS

Wave soldering

Partial heating

Soldering Conditions

Recommended

Condition Symbol

IR35-107-2 Package peak temperature: 235

°

C, Duration: 30 sec. max. (at 210

°

C or above),

Number of times: Twice max., Number of days: 7 days

Note

(after that, 125

°

C prebaking for 10 hours is necessary.)

< Precautions >

(1) Start the second reflow after the device temprature by the first reflow returns to normal.

(2) Flux washing by the water after the first reflow should be avoided.

Package peak temperature: 215

°

C, Duration: 40 sec. max. (at 200

°

C or above),

Number of times: Twice max., Number of days: 7 days

Note

(after that, 125

°

C prebaking for 10 hours is necessary.)

< Precautions >

(1) Start the second reflow after the device temprature by the first reflow returns to normal.

(2) Flux washing by the water after the first reflow should be avoided.

Solder bath temperature: 260

°

C max. Duration: 10 sec. max.

Number of times: Once, Preheating temperature: 120

°

C max. (Package surface temperature), Number of days: 7 days

Note

(after that, 125

°

C prebaking for 10 hours is necessary.)

Pin temperature: 300

°

C max., Duration: 3 sec. max. (per device side)

VP15-107-2

WS60-107-1

Note The number of days the device can be stored at 25

°

C, 65% RH MAX. after the dry pack has been opend.

Caution Use more than one soldering method should be avoided (except in the case of partial heating).

66

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Table 14-2. Insertion Type Soldering Conditions

µ

PD78011FCW-

×××

: 64-Pin Plastic Shrink DIP (750 mil)

µ

PD78012FCW-

×××

: 64-Pin Plastic Shrink DIP (750 mil)

µ

PD78013FCW-

×××

: 64-Pin Plastic Shrink DIP (750 mil)

µ

PD78014FCW-

×××

: 64-Pin Plastic Shrink DIP (750 mil)

µ

PD78015FCW-

×××

: 64-Pin Plastic Shrink DIP (750 mil)

µ

PD78016FCW-

×××

: 64-Pin Plastic Shrink DIP (750 mil)

µ

PD78018FCW-

×××

: 64-Pin Plastic Shrink DIP (750 mil)

Soldering Method

Wave soldering

(pin only)

Partial heating

Soldering Conditions

Solder bath temperature: 260

°

C max., Duration: 10 sec. max.

Pin temperature: 300

°

C max., Duration: 3 sec. max. (per pin)

Caution Wave soldering is only for the lead part in order that jet solder can not contact with the chip directly.

67

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

µ

PD78018F subseries.

Language Processing Software

RA78K/0

Notes 1, 2, 3, 4

78K/0 series common assembler package

CC78K/0

Notes 1, 2, 3, 4

DF78014

Notes 1, 2, 3, 4

CC78K/0-L

Notes 1, 2, 3, 4

78K/0 series common C compiler package

Device file common to

µ

PD78014 subseries

78K/0 series common C compiler library source file

PROM Writting Tools

PG-1500

PA-78P014CW

PA-78P018GC

PA-78P018GK

PA-78P018KK-S

PG-1500 controller

Notes 1, 2

PROM programmer

Programmer adapter connected to PG-1500

PG-1500 control program

Debugging Tool

IE-78000-R

IE-78000-R-A

IE-78000-R-BK

IE-78014-R-EM-A

IE-78000-R-SV3

IE-70000-98-IF-B

IE-70000-98N-IF

IE-70000-PC-IF-B

EP-78240CW-R

EP-78240GC-R

EV-78012GK-R

EV-9200GC-64

TGC-064SBW

EV-9900

SM78K0

Notes 5, 6, 7

ID78K0

Notes 4, 5, 6, 7

SD78K/0

Notes 1, 2

DF78014

Notes 1, 2, 4, 5, 6, 7

78K/0 series common in-circuit emulator

78K/0 series common in-circuit emulator (for integrated debugger)

78K/0 series common break board

µ

PD78018F and 78018FY subseries evaluation emulation board (V

DD

= 3.0 to 6.0 V)

Interface adapter and cable when an EWS is used as the host machine (for IE-78000R-A)

Interface adapter when PC-9800 series (except notebook PC) is used as the host machine (for IE-78000-R-A)

Interface adapter and cable when PC-9800 series notebook PC is used as the host machine (for IE-78000-R-A)

Interface adapter when IBM PC/AT

TM

is used as the host machine (for IE-78000-R-A)

Emulation probe common to

µ

PD78244 subseries

µ

PD78018F subseries emulation probe

Socket to be mounted on target system board created for the 64-pin plastic QFP (GC-AB8 type)

Conversion adapter to be mounted on a target system board made for 64-pin plastic QFP (GK-8A8 type)

TGC-100SDW is a product from Tokyo Eletech Corp. (TEL (03) 5295-1661)

When purchasing this product, please consult with our sales offices.

Tools for removing

µ

PD78P018FKK-S from EV-9200GC-64

78K/0 series common system simulator

IE-78000-R-A integrated dubugger

IE-78000-R screen debugger

Device file common to

µ

PD78014 subseries

Real-Time OS

RX78K/0

Notes 1, 2, 3, 4

MX78K0

Notes 1, 2, 3, 4

68

78K/0 series real-time OS

78K/0 series OS

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Fuzzy Inference Devleopment Support System

FE9000

Note 1

/FE9200

Note 6

Fuzzy knowledge data creation tool

FT9080

Note 1

/FT9085

Note 2

FI78K0

Notes 1, 2

FD78K0

Notes 1, 2

Translator

Fuzzy inference module

Fuzzy inference debugger

Notes 1. PC-9800 series (MS-DOS

TM

) based

2. IBM PC/AT and compatible (PC DOS

TM

/IBM DOS

TM

/MS-DOS) based

3. HP9000 series 300

TM

(HP-UX

TM

) based

4. HP9000 series 700

TM

(HP-UX) based, SPARCstation

TM

(SunOS

TM

) based, EWS4800 series (EWS-UX/V) based

5. PC-9800 series (MS-DOS + Windows

TM

) based

6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based

7. NEWS

TM

(NEWS-OS

TM

) based

Remarks 1. For development tools manufactured by a third party, refer to the 78K/0 Series Selection Guide (U11126E).

2. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78014.

69

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

APPENDIX B. RELATED DOCUMENTS

Device Related Documents

Document Name

µ

PD78018F, 78018FY Subseries User’s Manual

78K/0 Series User’s Manual - Instruction

78K/0 Series Instruction Table

78K/0 Series Instruction Set

µ

PD78018F Subseries Special Function Register Table

78K/0 Series Application Note Fundamental (I)

Floating-Point Arithmetic Program

Japanese

Document No.

English

U10659J U10659E

U12326J

U10903J

IEU-1372

U10904J

IEM-5594

IEA-715

IEA-718

IEA-1288

IEA-1289

Development Tools Documents (User’s Manual) (1/2)

Document Name

RA78K Series Assembler Package Operation

Language

RA78K Series Structured Assembler Preprocessor

RA78K0 Assembler Package Operation

CC78K Series C Compiler

Assembly Language

Structured Assembly Language

Operation

Language

CC78K0 C Compiler

CC78K/0 C Compiler Application Note

CC78K Series Library Source File

PG-1500 PROM Programmer

PG-1500 Controller PC-9800 Series (MS-DOS) Based

Operation

Language

Programming Know-how

PG-1500 Controller IBM PC Series (PC DOS) Based

IE-78000-R

E-78000-R-A

IE-78000-R-BK

IE-78014-R-EM-A

EP-78240

EP-78012GK-R

SM78K0 System Simulator Reference

EEA-618

U12322J

U11940J

EEU-704

EEU-5008

U11376J

U10057J

EEU-867

Japanese

Document No.

English

EEU-809 EEU-1399

EEU-815

EEU-817

EEU-1404

EEU-1402

U11802J

U11801J

U11789J

EEU-656

EEU-655

U11517J

U11518J

U11802E

U11801E

U11789E

EEU-1280

EEU-1284

U11517E

U11518E

EEU-962

EEU-986

EEU-5012

U10181J

U10418E

EEU-1513

EEU-1538

U10181E

EEA-1208

EEU-1335

EEU-1291

U10540E

U11376E

U10057E

EEU-1427

Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for designing, etc.

70

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Development Tools Documents (User’s Manual) (2/2)

Document Name

SM78K Series System Simulator

ID78K0 Integrated Debugger EWS Based

ID78K0 Integrated Debugger PC Based

ID78K0 Integrated Debugger Windows Based

SD78K/0 Screen Debugger

PC-9800 Series (MS-DOS) Based

SD78K/0 Screen Debugger

IBM PC/AT (PC DOS) Based

External Part User Open

Interface Specifications

Reference

Reference

Guide

Introduction

Reference

Introduction

Reference

Embedded Software Documents (User’s Manual)

Document Name

78K/0 Series Real-Time OS Fundamental

Installation

Fundamental 78K/0 Series OS MX78K0

Fuzzy Knowledge Data Creation Tool

78K/0, 78K/II, 87AD Series

Fuzzy Inference Development Support System - Translator

78K/0 Series Fuzzy Inference Development Suport System -

Fuzzy Inference Module

78K/0 Series Fuzzy Inference Development Support System -

Fuzzy Inference Debugger

Other Documents

Document Name

IC Package Manual

Semiconductor Device Mounting Technology Manual

Quality Grades on NEC Semiconductor Device

NEC Semiconductor Device Reliability/Quality Control System

Electrostatic Discharge (ESD) Test

Guide to Quality Assurance for Semiconductor Device

Guide for Products Related to Microcomputer: Other Companies

Japanese

Document No.

English

U10092J U10092E

U11151J

U11539J

U11649J

EEU-852

U10952J

EEU-5024

U11279J

U11539E

U11649E

U10539E

EEU-1414

U11279E

Japanese

Document No.

English

U11537J U11537E

U11536J

U12257J

U11536E

EEU-829

EEU-862

EEU-1438

EEU-1444

EEU-858

EEU-921

EEU-1441

EEU-1458

Japanese

Document No.

English

C10943X

C11535J

C11531J

C10535E

C11531E

C10983J

MEM-539

C11893J

U11416J

C10983E

MEI-1202

Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for designing, etc.

71

72

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 2886-9022/9044

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Tel: 01-504-2787

Fax: 01-504-2860

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 65-253-8311

Fax: 65-250-3583

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

Fax: 02-719-5951

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil

Tel: 011-6465-6810

Fax: 011-6465-6829

J98. 2

73

74

µ

PD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F

FIP and IEBus are trademarks of NEC Corporation.

MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.

IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.

HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

SunOS is a trademark of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

The related documents referred to in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M4 96.5

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